| commit | 5ff7acf9640688c355d9e33192185ff9f440efb4 | [log] [tgz] |
|---|---|---|
| author | Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> | Mon Jun 27 14:22:45 2022 +0530 |
| committer | Michal Simek <michal.simek@amd.com> | Tue Jul 26 08:23:54 2022 +0200 |
| tree | abf1f1faf624e9dbd4bf61466330d0556276626d | |
| parent | 3f5228a8fab41bbecb5e1e906f8e42413a78ad30 [diff] |
mmc: zynq_sdhci: Fix timing macros for MMC High speed Timing macro's are wrong for MMC_HS_52 and MMC_DDR_52. Fix it with correct values of MMC_TIMING_MMC_HS and MMC_TIMING_MMC_DDR52 respectively. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/1656319965-12124-1-git-send-email-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>