commit cf3e4173a6071b632a601f60eb529ff209b05ea5
author Masahiro Yamada <yamada.masahiro@socionext.com> Fri Feb 26 14:21:50 2016 +0900
committer Masahiro Yamada <yamada.masahiro@socionext.com> Mon Feb 29 03:50:16 2016 +0900
tree d6c577c517652594178eadb9ce9529dcc2ec6881
parent c9b5edf5ac10b3d78be3874c7745bae26ff25122

ARM: uniphier: rework DRAM size handling in UMC init code

Currently, DRAM size is converted twice:
  size in byte -> size in Gbit -> enum

Optimize the code by converting the "size in byte" into enum directly.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

arch/arm/mach-uniphier/dram/umc-ph1-ld4.c

diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c
index 92b0f18..0eb47d7 100644
--- a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c
@@ -76,7 +76,7 @@
 }
 
 static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
-			     int size, int freq, bool ddr3plus)
+			     int freq, unsigned long size, bool ddr3plus)
 {
 	enum dram_freq freq_e;
 	enum dram_size size_e;
@@ -101,14 +101,14 @@
 	switch (size) {
 	case 0:
 		return 0;
-	case 1:
+	case SZ_128M:
 		size_e = DRAM_SZ_128M;
 		break;
-	case 2:
+	case SZ_256M:
 		size_e = DRAM_SZ_256M;
 		break;
 	default:
-		pr_err("unsupported DRAM size\n");
+		pr_err("unsupported DRAM size 0x%08lx\n", size);
 		return -EINVAL;
 	}
 
@@ -140,7 +140,7 @@
 }
 
 static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
-		       int freq, int size, bool ddr3plus, int ch)
+		       int freq, unsigned long size, bool ddr3plus, int ch)
 {
 	void __iomem *phy_base = dc_base + 0x00001000;
 	int ret;
@@ -159,7 +159,7 @@
 	if (ret)
 		return ret;
 
-	return umc_dramcont_init(dc_base, ca_base, size, freq, ddr3plus);
+	return umc_dramcont_init(dc_base, ca_base, freq, size, ddr3plus);
 }
 
 int ph1_ld4_umc_init(const struct uniphier_board_data *bd)
@@ -172,7 +172,7 @@
 
 	for (ch = 0; ch < DRAM_CH_NR; ch++) {
 		ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
-				  bd->dram_ch[ch].size / SZ_128M,
+				  bd->dram_ch[ch].size,
 				  bd->dram_ddr3plus, ch);
 		if (ret) {
 			pr_err("failed to initialize UMC ch%d\n", ch);

arch/arm/mach-uniphier/dram/umc-ph1-sld8.c

diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c
index a2ed9ba..43e53fd 100644
--- a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c
+++ b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c
@@ -79,7 +79,7 @@
 }
 
 static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
-			     int size, int freq, bool ddr3plus)
+			     int freq, unsigned long size, bool ddr3plus)
 {
 	enum dram_freq freq_e;
 	enum dram_size size_e;
@@ -99,17 +99,17 @@
 	switch (size) {
 	case 0:
 		return 0;
-	case 1:
+	case SZ_128M:
 		size_e = DRAM_SZ_128M;
 		break;
-	case 2:
+	case SZ_256M:
 		size_e = DRAM_SZ_256M;
 		break;
-	case 4:
+	case SZ_512M:
 		size_e = DRAM_SZ_512M;
 		break;
 	default:
-		pr_err("unsupported DRAM size\n");
+		pr_err("unsupported DRAM size 0x%08lx\n", size);
 		return -EINVAL;
 	}
 
@@ -143,7 +143,7 @@
 }
 
 static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
-		       int freq, int size, bool ddr3plus, int ch)
+		       int freq, unsigned long size, bool ddr3plus, int ch)
 {
 	void __iomem *phy_base = dc_base + 0x00001000;
 	int ret;
@@ -162,7 +162,7 @@
 	if (ret)
 		return ret;
 
-	return umc_dramcont_init(dc_base, ca_base, size, freq, ddr3plus);
+	return umc_dramcont_init(dc_base, ca_base, freq, size, ddr3plus);
 }
 
 int ph1_sld8_umc_init(const struct uniphier_board_data *bd)
@@ -175,7 +175,7 @@
 
 	for (ch = 0; ch < DRAM_CH_NR; ch++) {
 		ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
-				  bd->dram_ch[ch].size / SZ_128M,
+				  bd->dram_ch[ch].size,
 				  bd->dram_ddr3plus, ch);
 		if (ret) {
 			pr_err("failed to initialize UMC ch%d\n", ch);