| commit | cf39f7d6629095cbc9ceeeefb10f02072285d9fc | [log] [tgz] |
|---|---|---|
| author | Michal Simek <michal.simek@amd.com> | Tue Sep 03 09:48:15 2024 +0200 |
| committer | Michal Simek <michal.simek@amd.com> | Fri Sep 20 08:31:57 2024 +0200 |
| tree | 248794f2acee19cbdf706953c81a25a525753eb6 | |
| parent | cd4aa88c1d4d3426a718e6705b8bc59c7b56468d [diff] [blame] |
xilinx: Enable SIMPLE_PM_BUS Enable simple-pm-bus driver to handle case where axi bus coming between PS (fixed) part to PL (programmable) part has own clock or power domain. That's why enable driver to be ready for this configuration. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/b9f4bb85be502616edf3be2b79e52a0e2c03e821.1725349691.git.michal.simek@amd.com
diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index 40a9b16..776af9a 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig
@@ -73,6 +73,7 @@ CONFIG_IP_DEFRAG=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_TFTP_BLOCKSIZE=4096 +CONFIG_SIMPLE_PM_BUS=y CONFIG_CLK_VERSAL=y CONFIG_DFU_RAM=y CONFIG_ARM_FFA_TRANSPORT=y