x86: coreboot: Collect the address of the ACPI tables
At present any ACPI tables created by prior-stage firmware are ignored.
It is useful to be able to view these in U-Boot.
Pick this up from the sysinfo tables and display it with the cbsysinfo
command. This allows the 'acpi list' command to work when booting from
coreboot.
Adjust the global_data condition so that acpi_start is available even if
table-generation is disabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/arch/x86/include/asm/cb_sysinfo.h b/arch/x86/include/asm/cb_sysinfo.h
index 0201ac6..6b26614 100644
--- a/arch/x86/include/asm/cb_sysinfo.h
+++ b/arch/x86/include/asm/cb_sysinfo.h
@@ -133,6 +133,7 @@
* @mtc_size: Size of MTC region
* @chromeos_vpd: Chromium OS Vital Product Data region, typically NULL, meaning
* not used
+ * @rsdp: Pointer to ACPI RSDP table
*/
struct sysinfo_t {
unsigned int cpu_khz;
@@ -211,6 +212,7 @@
u64 mtc_start;
u32 mtc_size;
void *chromeos_vpd;
+ void *rsdp;
};
extern struct sysinfo_t lib_sysinfo;
diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h
index f131de5..4de137f 100644
--- a/arch/x86/include/asm/coreboot_tables.h
+++ b/arch/x86/include/asm/coreboot_tables.h
@@ -422,6 +422,8 @@
#define CB_TAG_SERIALNO 0x002a
#define CB_MAX_SERIALNO_LENGTH 32
+#define CB_TAG_ACPI_RSDP 0x0043
+
#define CB_TAG_CMOS_OPTION_TABLE 0x00c8
struct cb_cmos_option_table {
diff --git a/arch/x86/lib/coreboot/cb_sysinfo.c b/arch/x86/lib/coreboot/cb_sysinfo.c
index 748fa4e..a11a258 100644
--- a/arch/x86/lib/coreboot/cb_sysinfo.c
+++ b/arch/x86/lib/coreboot/cb_sysinfo.c
@@ -264,6 +264,13 @@
info->mrc_cache = map_sysmem(cbmem->cbmem_tab, 0);
}
+static void cb_parse_acpi_rsdp(void *ptr, struct sysinfo_t *info)
+{
+ struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr;
+
+ info->rsdp = map_sysmem(cbmem->cbmem_tab, 0);
+}
+
__weak void cb_parse_unhandled(u32 tag, unsigned char *ptr)
{
}
@@ -428,6 +435,9 @@
case CB_TAG_MRC_CACHE:
cb_parse_mrc_cache(rec, info);
break;
+ case CB_TAG_ACPI_RSDP:
+ cb_parse_acpi_rsdp(rec, info);
+ break;
default:
cb_parse_unhandled(rec->tag, ptr);
break;
@@ -454,6 +464,7 @@
if (!ret)
return -ENOENT;
gd->arch.coreboot_table = addr;
+ gd_set_acpi_start(map_to_sysmem(info->rsdp));
gd->flags |= GD_FLG_SKIP_LL_INIT;
return 0;
diff --git a/cmd/x86/cbsysinfo.c b/cmd/x86/cbsysinfo.c
index 34fdaf5..07570b0 100644
--- a/cmd/x86/cbsysinfo.c
+++ b/cmd/x86/cbsysinfo.c
@@ -363,6 +363,7 @@
print_hex("MTC size", info->mtc_size);
print_ptr("Chrome OS VPD", info->chromeos_vpd);
+ print_ptr("RSDP", info->rsdp);
}
static int do_cbsysinfo(struct cmd_tbl *cmdtp, int flag, int argc,
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index 65bf8df..a1e1b9d 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -457,7 +457,7 @@
*/
fdt_addr_t translation_offset;
#endif
-#ifdef CONFIG_GENERATE_ACPI_TABLE
+#ifdef CONFIG_ACPI
/**
* @acpi_ctx: ACPI context pointer
*/
@@ -536,7 +536,7 @@
#define gd_dm_priv_base() NULL
#endif
-#ifdef CONFIG_GENERATE_ACPI_TABLE
+#ifdef CONFIG_ACPI
#define gd_acpi_ctx() gd->acpi_ctx
#define gd_acpi_start() gd->acpi_start
#define gd_set_acpi_start(addr) gd->acpi_start = addr