commit cf191e4aa3c2afdebe78b3298f7ce3d0a1ee2e26
author Jiajie Chen <c@jia.je> Mon Feb 27 23:09:39 2023 +0800
committer Michal Simek <michal.simek@amd.com> Thu Mar 09 13:15:00 2023 +0100
tree 7ec2133048933e1c2a7d6a32fbf0f3ae6dd797e9
parent 9398734501e23c0f4fde55bfc24b9853873b94e1

spi: xilinx_spi: Fix spi reset

It was incorrectly using an old priv->regs pointer, which was
initialized to zero. SPI resets won't happen on first call.

Signed-off-by: Jiajie Chen <c@jia.je>
Link: https://lore.kernel.org/r/20230227150938.211820-1-c@jia.je
Signed-off-by: Michal Simek <michal.simek@amd.com>

drivers/spi/xilinx_spi.c

diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 4e9115d..9e6255a 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -112,10 +112,9 @@
 static int xilinx_spi_probe(struct udevice *bus)
 {
 	struct xilinx_spi_priv *priv = dev_get_priv(bus);
-	struct xilinx_spi_regs *regs = priv->regs;
-
-	priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus);
+	struct xilinx_spi_regs *regs;
 
+	regs = priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus);
 	priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0);
 
 	writel(SPISSR_RESET_VALUE, &regs->srr);