tree ff5766eef6dc2f238791a238bccbc484941373cc
parent 77594b3b9691d2573daba3c9a38476060bf01c27
author York Sun <yorksun@freescale.com> 1446660202 -0800
committer York Sun <yorksun@freescale.com> 1450060048 -0800

armv8/ls2080aqds: Update DDR settings for four chip-select case

When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm,
and 2T timing is enabled.

Signed-off-by: York Sun <yorksun@freescale.com>