| commit | 9782c55c1c6c27bb29712d92734335fe4b906f75 | [log] [tgz] |
|---|---|---|
| author | Andy Fleming <afleming@freescale.com> | Sat Feb 24 01:16:45 2007 -0600 |
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | Mon Apr 23 19:58:28 2007 -0500 |
| tree | 94edfc80e63eb36793f6feed2c46339e0cfb9cce | |
| parent | 4399a519320b31ee66779cf42673633b29b7c224 [diff] |
Tweak DDR ECC error counter Enable single-bit error counter when memory was cleared by ddr controller. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>