arm: socfpga: agilex5: Enable cache flush for system memory cache in CCU
set/way instructions "dc cisw" which is used by the "dcache flush" command
only flushing CPU data caches from L1 -> L2 -> L3 to system memory cache in
cache coherency unit, hence this patch enables data flush from system
memory cache of CCU into DDR memory.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 7e37cca..cccba71 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -65,6 +65,7 @@
obj-y += wrap_handoff_soc64.o
obj-y += wrap_pll_config_soc64.o
obj-y += altera-sysmgr.o
+obj-y += ccu_ncore3.o
endif
ifdef CONFIG_TARGET_SOCFPGA_N5X