| commit | cd49315d6ed218d3e9fcce044c19921f8e66637b | [log] [tgz] |
|---|---|---|
| author | Tien Fong Chee <tien.fong.chee@intel.com> | Thu Aug 08 16:47:39 2024 +0800 |
| committer | Tom Rini <trini@konsulko.com> | Tue Feb 25 10:53:56 2025 -0600 |
| tree | 907454c7d04a3835b451118755479b56c2661d75 | |
| parent | 9b2be718915f75f2168821782b1d6504a5274287 [diff] |
arm: socfpga: agilex5: Enable cache flush for system memory cache in CCU set/way instructions "dc cisw" which is used by the "dcache flush" command only flushing CPU data caches from L1 -> L2 -> L3 to system memory cache in cache coherency unit, hence this patch enables data flush from system memory cache of CCU into DDR memory. Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>