diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 81fcfe0..7693699 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -28,6 +28,9 @@
 	SBI_EXT_HSM = 0x48534D,
 	SBI_EXT_SRST = 0x53525354,
 	SBI_EXT_PMU = 0x504D55,
+	SBI_EXT_DBCN = 0x4442434E,
+	SBI_EXT_SUSP = 0x53555350,
+	SBI_EXT_CPPC = 0x43505043,
 };
 
 enum sbi_ext_base_fid {
@@ -89,6 +92,12 @@
 	SBI_SRST_RESET_REASON_SYS_FAILURE,
 };
 
+enum sbi_ext_dbcn_fid {
+	SBI_EXT_DBCN_CONSOLE_WRITE = 0,
+	SBI_EXT_DBCN_CONSOLE_READ,
+	SBI_EXT_DBCN_CONSOLE_WRITE_BYTE,
+};
+
 #ifdef CONFIG_SBI_V01
 #define SBI_EXT_SET_TIMER		SBI_EXT_0_1_SET_TIMER
 #define SBI_FID_SET_TIMER		0
diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c
index 6f2cad4..c4707fe 100644
--- a/cmd/riscv/sbi.c
+++ b/cmd/riscv/sbi.c
@@ -46,6 +46,9 @@
 	{ SBI_EXT_HSM,			      "Hart State Management Extension" },
 	{ SBI_EXT_SRST,			      "System Reset Extension" },
 	{ SBI_EXT_PMU,			      "Performance Monitoring Unit Extension" },
+	{ SBI_EXT_DBCN,			      "Debug Console Extension" },
+	{ SBI_EXT_SUSP,			      "System Suspend Extension" },
+	{ SBI_EXT_CPPC,			      "Collaborative Processor Performance Control Extension" },
 };
 
 static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc,