Merge tag 'xilinx-for-v2022.07-rc4' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2022.07-rc4
zynqmp:
- Fix DP PLL configuration for zcu102/zcu106 and SOM
- Fix split mode for starting R5s
- DT fixes
- Remove firmware node for mini configurations
- Wire TEE for multi DTB fit image
xilinx:
- Handle board_get_usable_ram_top(0) properly
phy:
- Extend psgtr timeout
mmc:
- Fix mini configuration which misses zynqmp_pm_is_function_supported()
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
index f229880..7261837 100644
--- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
@@ -42,6 +42,12 @@
reg = <0x0 0x0 0x0 0x80000000>;
};
+ si5332_1: si5332_1 { /* u142 - GEM0 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
ina226-vccint {
compatible = "iio-hwmon";
io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
@@ -135,8 +141,17 @@
xlnx,mio-bank = <1>;
};
+/* GEM SGMII */
+&psgtr {
+ status = "okay";
+ /* gem0 */
+ clocks = <&si5332_1>;
+ clock-names = "ref0";
+};
+
&gem0 {
status = "okay";
+ phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;
phy-handle = <&phy0>;
phy-mode = "sgmii";
is-internal-pcspma;
diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
index 86f2ccf..7b3722f 100644
--- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
@@ -77,7 +77,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
- spi-tx-bus-width = <1>;
+ spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
};
diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
index e980fb0..11b2a58 100644
--- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
@@ -73,7 +73,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
- spi-tx-bus-width = <1>;
+ spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
};
diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
index c8c5100..db199c4 100644
--- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
@@ -73,7 +73,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
- spi-tx-bus-width = <1>;
+ spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
};
diff --git a/arch/arm/dts/zynqmp-mini-emmc0.dts b/arch/arm/dts/zynqmp-mini-emmc0.dts
index 8d9f9ca..8467dd8 100644
--- a/arch/arm/dts/zynqmp-mini-emmc0.dts
+++ b/arch/arm/dts/zynqmp-mini-emmc0.dts
@@ -41,46 +41,6 @@
clock-frequency = <200000000>;
};
- firmware {
- zynqmp_firmware: zynqmp-firmware {
- compatible = "xlnx,zynqmp-firmware";
- #power-domain-cells = <1>;
- method = "smc";
- u-boot,dm-pre-reloc;
-
- zynqmp_power: zynqmp-power {
- u-boot,dm-pre-reloc;
- compatible = "xlnx,zynqmp-power";
- mboxes = <&ipi_mailbox_pmu1 0>,
- <&ipi_mailbox_pmu1 1>;
- mbox-names = "tx", "rx";
- };
- };
- };
-
- zynqmp_ipi: zynqmp_ipi {
- u-boot,dm-pre-reloc;
- compatible = "xlnx,zynqmp-ipi-mailbox";
- xlnx,ipi-id = <0>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- ipi_mailbox_pmu1: mailbox@ff990400 {
- u-boot,dm-pre-reloc;
- reg = <0x0 0xff9905c0 0x0 0x20>,
- <0x0 0xff9905e0 0x0 0x20>,
- <0x0 0xff990e80 0x0 0x20>,
- <0x0 0xff990ea0 0x0 0x20>;
- reg-names = "local_request_region",
- "local_response_region",
- "remote_request_region",
- "remote_response_region";
- #mbox-cells = <1>;
- xlnx,ipi-id = <4>;
- };
- };
-
amba: amba {
compatible = "simple-bus";
#address-cells = <2>;
diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts b/arch/arm/dts/zynqmp-mini-emmc1.dts
index 5722b76..2afcc77 100644
--- a/arch/arm/dts/zynqmp-mini-emmc1.dts
+++ b/arch/arm/dts/zynqmp-mini-emmc1.dts
@@ -41,46 +41,6 @@
clock-frequency = <200000000>;
};
- firmware {
- zynqmp_firmware: zynqmp-firmware {
- compatible = "xlnx,zynqmp-firmware";
- #power-domain-cells = <1>;
- method = "smc";
- u-boot,dm-pre-reloc;
-
- zynqmp_power: zynqmp-power {
- u-boot,dm-pre-reloc;
- compatible = "xlnx,zynqmp-power";
- mboxes = <&ipi_mailbox_pmu1 0>,
- <&ipi_mailbox_pmu1 1>;
- mbox-names = "tx", "rx";
- };
- };
- };
-
- zynqmp_ipi: zynqmp_ipi {
- u-boot,dm-pre-reloc;
- compatible = "xlnx,zynqmp-ipi-mailbox";
- xlnx,ipi-id = <0>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- ipi_mailbox_pmu1: mailbox@ff990400 {
- u-boot,dm-pre-reloc;
- reg = <0x0 0xff9905c0 0x0 0x20>,
- <0x0 0xff9905e0 0x0 0x20>,
- <0x0 0xff990e80 0x0 0x20>,
- <0x0 0xff990ea0 0x0 0x20>;
- reg-names = "local_request_region",
- "local_response_region",
- "remote_request_region",
- "remote_response_region";
- #mbox-cells = <1>;
- xlnx,ipi-id = <4>;
- };
- };
-
amba: amba {
compatible = "simple-bus";
#address-cells = <2>;
diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts b/arch/arm/dts/zynqmp-mini-qspi.dts
index 9b4320f..20c21de 100644
--- a/arch/arm/dts/zynqmp-mini-qspi.dts
+++ b/arch/arm/dts/zynqmp-mini-qspi.dts
@@ -68,7 +68,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
- spi-tx-bus-width = <1>;
+ spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <40000000>;
};
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts
index 14ab316..7c2bfa3 100644
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -56,6 +56,9 @@
fwuen {
label = "fwuen";
gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_MISC>;
+ wakeup-source;
+ autorepeat;
};
};
@@ -87,6 +90,21 @@
<&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,
<&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;
};
+
+ pwm-fan {
+ compatible = "pwm-fan";
+ status = "okay";
+ pwms = <&ttc0 2 40000 0>;
+ };
+};
+
+&modepin_gpio {
+ label = "modepin";
+};
+
+&ttc0 {
+ status = "okay";
+ #pwm-cells = <3>;
};
&uart1 { /* MIO36/MIO37 */
@@ -117,7 +135,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
- spi-tx-bus-width = <1>;
+ spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <40000000>; /* 40MHz */
partition@0 {
@@ -341,3 +359,98 @@
&zynqmp_dpsub {
status = "okay";
};
+
+&rtc {
+ status = "okay";
+};
+
+&lpd_dma_chan1 {
+ status = "okay";
+};
+
+&lpd_dma_chan2 {
+ status = "okay";
+};
+
+&lpd_dma_chan3 {
+ status = "okay";
+};
+
+&lpd_dma_chan4 {
+ status = "okay";
+};
+
+&lpd_dma_chan5 {
+ status = "okay";
+};
+
+&lpd_dma_chan6 {
+ status = "okay";
+};
+
+&lpd_dma_chan7 {
+ status = "okay";
+};
+
+&lpd_dma_chan8 {
+ status = "okay";
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&lpd_watchdog {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
+
+&cpu_opp_table {
+ opp00 {
+ opp-hz = /bits/ 64 <1333333333>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <666666666>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <444444444>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <333333333>;
+ };
+};
diff --git a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts
index 300e2eb..3750bb3 100644
--- a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts
+++ b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts
@@ -61,7 +61,7 @@
compatible = "st,m25p80", "n25q256a", "jedec,spi-nor";
m25p,fast-read;
reg = <0x0>;
- spi-tx-bus-width = <1>;
+ spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <166000000>;
#address-cells = <1>;
diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts b/arch/arm/dts/zynqmp-zc1232-revA.dts
index 7543855..63c553f 100644
--- a/arch/arm/dts/zynqmp-zc1232-revA.dts
+++ b/arch/arm/dts/zynqmp-zc1232-revA.dts
@@ -44,7 +44,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
- spi-tx-bus-width = <1>;
+ spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@0 { /* for testing purpose */
diff --git a/arch/arm/dts/zynqmp-zc1254-revA.dts b/arch/arm/dts/zynqmp-zc1254-revA.dts
index 9cc1c0c..343033c 100644
--- a/arch/arm/dts/zynqmp-zc1254-revA.dts
+++ b/arch/arm/dts/zynqmp-zc1254-revA.dts
@@ -45,7 +45,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
- spi-tx-bus-width = <1>;
+ spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@0 { /* for testing purpose */
diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
index 4a87bd6..d20f667 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -351,7 +351,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
- spi-tx-bus-width = <1>;
+ spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@0 { /* for testing purpose */
diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
index f420f83..e153a64 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
@@ -173,7 +173,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
- spi-tx-bus-width = <1>;
+ spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@0 { /* for testing purpose */
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 1b1cabb..c13b52a 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -604,7 +604,26 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
- /* SI5328 - u20 */
+ si5328: clock-generator@69 {/* SI5328 - u20 */
+ compatible = "silabs,si5328";
+ reg = <0x69>;
+ /*
+ * Chip has interrupt present connected to PL
+ * interrupt-parent = <&>;
+ * interrupts = <>;
+ */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+ clocks = <&refhdmi>;
+ clock-names = "xtal";
+ clock-output-names = "si5328";
+
+ si5328_clk: clk0@0 {
+ reg = <0>;
+ clock-frequency = <27000000>;
+ };
+ };
};
/* 5 - 7 unconnected */
};
@@ -948,7 +967,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
- spi-tx-bus-width = <1>;
+ spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@0 { /* for testing purpose */
diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts
index 9cd3044..50bf479 100644
--- a/arch/arm/dts/zynqmp-zcu104-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revA.dts
@@ -434,7 +434,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
- spi-tx-bus-width = <1>;
+ spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@0 { /* for testing purpose */
diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts
index 4519156..752a9e3 100644
--- a/arch/arm/dts/zynqmp-zcu104-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revC.dts
@@ -446,7 +446,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
- spi-tx-bus-width = <1>;
+ spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@0 { /* for testing purpose */
diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts
index 50cc72e..6dfc8fe 100644
--- a/arch/arm/dts/zynqmp-zcu106-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -593,7 +593,26 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
- /* SI5328 - u20 */
+ si5328: clock-generator@69 {/* SI5328 - u20 */
+ compatible = "silabs,si5328";
+ reg = <0x69>;
+ /*
+ * Chip has interrupt present connected to PL
+ * interrupt-parent = <&>;
+ * interrupts = <>;
+ */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+ clocks = <&refhdmi>;
+ clock-names = "xtal";
+ clock-output-names = "si5328";
+
+ si5328_clk: clk0@0 {
+ reg = <0>;
+ clock-frequency = <27000000>;
+ };
+ };
};
i2c@5 {
#address-cells = <1>;
@@ -942,7 +961,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
- spi-tx-bus-width = <1>;
+ spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@0 { /* for testing purpose */
diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts
index 2b15ce1..021fe88 100644
--- a/arch/arm/dts/zynqmp-zcu111-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu111-revA.dts
@@ -784,7 +784,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
- spi-tx-bus-width = <1>;
+ spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@0 { /* for testing purpose */
diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts
index 10d8bc8..e88fc23 100644
--- a/arch/arm/dts/zynqmp-zcu1275-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts
@@ -50,7 +50,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
- spi-tx-bus-width = <1>;
+ spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@0 { /* for testing purpose */
diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts
index 32a6e6f..c5cdd58 100644
--- a/arch/arm/dts/zynqmp-zcu208-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu208-revA.dts
@@ -642,7 +642,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
- spi-tx-bus-width = <1>;
+ spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
};
diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts
index 1e34703..caae169 100644
--- a/arch/arm/dts/zynqmp-zcu216-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu216-revA.dts
@@ -653,7 +653,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
- spi-tx-bus-width = <1>;
+ spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
};
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index c442608..dae8f06 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -13,6 +13,7 @@
*/
#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/power/xlnx-zynqmp-power.h>
#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
@@ -75,7 +76,7 @@
};
};
- cpu_opp_table: cpu-opp-table {
+ cpu_opp_table: opp-table-cpu {
compatible = "operating-points-v2";
opp-shared;
opp00 {
@@ -189,6 +190,12 @@
compatible = "xlnx,zynqmp-pinctrl";
status = "disabled";
};
+
+ modepin_gpio: gpio {
+ compatible = "xlnx,zynqmp-gpio-modepin";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
};
};
@@ -211,6 +218,7 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ power-domains = <&zynqmp_firmware PD_PL>;
};
amba: axi {
@@ -874,6 +882,7 @@
<&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
<&zynqmp_reset ZYNQMP_RESET_USB0_APB>;
reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
+ reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;
ranges;
dwc3_0: usb@fe200000 {
diff --git a/arch/arm/mach-zynqmp/mkimage_fit_atf.sh b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh
index 72a8a3e..40ed23b 100755
--- a/arch/arm/mach-zynqmp/mkimage_fit_atf.sh
+++ b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh
@@ -140,14 +140,24 @@
};
__CONF_SECTION1_EOF
else
+if [ -f $BL32 ]; then
cat << __CONF_SECTION1_EOF
config_1 {
+ description = "Multi DTB with TF-A and TEE";
+ firmware = "atf";
+ loadables = "uboot", "tee", "fdt_1";
+ };
+__CONF_SECTION1_EOF
+else
+cat << __CONF_SECTION1_EOF
+ config_1 {
description = "Multi DTB with TF-A";
firmware = "atf";
loadables = "uboot", "fdt_1";
};
__CONF_SECTION1_EOF
fi
+fi
cat << __ITS_EOF
};
diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c
index 704520e..4f1ed44 100644
--- a/arch/arm/mach-zynqmp/mp.c
+++ b/arch/arm/mach-zynqmp/mp.c
@@ -102,13 +102,21 @@
u32 tmp;
tmp = readl(&crlapb_base->rst_lpd_top);
- if (mode == LOCK || nr == ZYNQMP_CORE_RPU0)
- tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
- ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK);
-
- if (mode == LOCK || nr == ZYNQMP_CORE_RPU1)
+ if (mode == LOCK) {
tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
+ ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK |
ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK);
+ } else {
+ if (nr == ZYNQMP_CORE_RPU0) {
+ tmp |= ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK;
+ if (tmp & ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK)
+ tmp |= ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK;
+ } else {
+ tmp |= ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK;
+ if (tmp & ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK)
+ tmp |= ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK;
+ }
+ }
writel(tmp, &crlapb_base->rst_lpd_top);
}
@@ -142,6 +150,17 @@
udelay(0x500);
}
+static int check_r5_mode(void)
+{
+ u32 tmp;
+
+ tmp = readl(&rpu_base->rpu_glbl_ctrl);
+ if (tmp & ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK)
+ return SPLIT;
+
+ return LOCK;
+}
+
int cpu_disable(u32 nr)
{
if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
@@ -149,7 +168,7 @@
val |= 1 << nr;
writel(val, &crfapb_base->rst_fpd_apu);
} else {
- set_r5_reset(nr, SPLIT);
+ set_r5_reset(nr, check_r5_mode());
}
return 0;
diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
index 2e2807e..a88f5bb 100644
--- a/board/xilinx/versal/board.c
+++ b/board/xilinx/versal/board.c
@@ -256,6 +256,9 @@
phys_addr_t reg;
struct lmb lmb;
+ if (!total_size)
+ return gd->ram_top;
+
/* found enough not-reserved memory to relocated U-Boot */
lmb_init(&lmb);
lmb_add(&lmb, gd->ram_base, gd->ram_size);
diff --git a/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c
index ed02579..e559880 100644
--- a/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c
@@ -74,6 +74,9 @@
psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000A00U);
psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
+ psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C03U);
+ psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01013803U);
psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000203U);
diff --git a/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c
index 8ecd9ee..f99e06a 100644
--- a/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c
@@ -85,8 +85,8 @@
psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
- psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010303U);
- psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01012700U);
+ psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
+ psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C03U);
psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011103U);
psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
psu_mask_write(0xFD1A0064, 0x01003F07U, 0x01000200U);
diff --git a/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c
index 2ac4e03..3dc9bf8 100644
--- a/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c
@@ -81,8 +81,8 @@
psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
- psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010203U);
- psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C00U);
+ psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
+ psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C03U);
psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011303U);
psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
diff --git a/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
index 15f0be1..cbc4362 100644
--- a/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
@@ -81,8 +81,8 @@
psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
- psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010203U);
- psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C00U);
+ psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
+ psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C03U);
psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011303U);
psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 41ecc95..e311aa7 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -516,6 +516,9 @@
phys_addr_t reg;
struct lmb lmb;
+ if (!total_size)
+ return gd->ram_top;
+
if (!IS_ALIGNED((ulong)gd->fdt_blob, 0x8))
panic("Not 64bit aligned DT location: %p\n", gd->fdt_blob);
diff --git a/configs/xilinx_versal_mini_emmc0_defconfig b/configs/xilinx_versal_mini_emmc0_defconfig
index ab14118..9d2f9757 100644
--- a/configs/xilinx_versal_mini_emmc0_defconfig
+++ b/configs/xilinx_versal_mini_emmc0_defconfig
@@ -56,7 +56,6 @@
# CONFIG_NET is not set
# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
-CONFIG_ZYNQMP_FIRMWARE=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_ARM_DCC=y
diff --git a/configs/xilinx_versal_mini_emmc1_defconfig b/configs/xilinx_versal_mini_emmc1_defconfig
index cab3d21..7efb928 100644
--- a/configs/xilinx_versal_mini_emmc1_defconfig
+++ b/configs/xilinx_versal_mini_emmc1_defconfig
@@ -56,7 +56,6 @@
# CONFIG_NET is not set
# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
-CONFIG_ZYNQMP_FIRMWARE=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_ARM_DCC=y
diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig
index e176175..b405277 100644
--- a/configs/xilinx_zynqmp_mini_emmc0_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig
@@ -58,7 +58,6 @@
# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_ZYNQMP_FIRMWARE=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig
index f5b35fb..5fa1337 100644
--- a/configs/xilinx_zynqmp_mini_emmc1_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig
@@ -58,7 +58,6 @@
# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_ZYNQMP_FIRMWARE=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index a59d96c..e978b67 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -79,6 +79,11 @@
return 0;
}
+__weak int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id)
+{
+ return 1;
+}
+
#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
/* Default settings for ZynqMP Clock Phases */
static const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63, 0,
diff --git a/drivers/phy/phy-zynqmp.c b/drivers/phy/phy-zynqmp.c
index 08c1b6e..d1288bb 100644
--- a/drivers/phy/phy-zynqmp.c
+++ b/drivers/phy/phy-zynqmp.c
@@ -168,7 +168,7 @@
};
/* Timeout values */
-#define TIMEOUT_US 1000
+#define TIMEOUT_US 10000
#define IOU_SLCR_GEM_CLK_CTRL 0x308
#define GEM_CTRL_GEM_SGMII_MODE BIT(2)
diff --git a/drivers/soc/soc_xilinx_versal.c b/drivers/soc/soc_xilinx_versal.c
index f8bcd9a..3d8c25c 100644
--- a/drivers/soc/soc_xilinx_versal.c
+++ b/drivers/soc/soc_xilinx_versal.c
@@ -45,7 +45,7 @@
static int soc_xilinx_versal_probe(struct udevice *dev)
{
struct soc_xilinx_versal_priv *priv = dev_get_priv(dev);
- u32 ret_payload[4];
+ u32 ret_payload[PAYLOAD_ARG_CNT];
int ret;
priv->family = versal_family;
diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c
index 7d33ce2..a71115b 100644
--- a/drivers/soc/soc_xilinx_zynqmp.c
+++ b/drivers/soc/soc_xilinx_zynqmp.c
@@ -49,7 +49,7 @@
static int soc_xilinx_zynqmp_probe(struct udevice *dev)
{
struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev);
- u32 ret_payload[4];
+ u32 ret_payload[PAYLOAD_ARG_CNT];
int ret;
priv->family = zynqmp_family;
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 8eb44b1..f25d796 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -226,7 +226,6 @@
#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "atf-uboot.ub"
/* MMC support */
-#ifdef CONFIG_MMC_SDHCI_ZYNQ
# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 /* unused */
# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 /* unused */
# if defined(CONFIG_SPL_LOAD_FIT)
@@ -234,7 +233,6 @@
# else
# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
# endif
-#endif
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU)
# define CONFIG_SPL_HASH