commit ccaa08c607bfc2a5b9d579f14f6b9c8f64823dd2
author Tom Rini <trini@konsulko.com> Thu Apr 30 11:31:33 2020 -0400
committer Tom Rini <trini@konsulko.com> Thu Apr 30 11:34:01 2020 -0400
tree 0976c82eca83479ba9337f9a1824572ea0b9578e
parent 92007cfbe206a69eaecd4dd74cee0c2ecd3be69e
parent ce9dfb978d3130414413a2cbc8bb8ec89247b6d6

Merge tag 'xilinx-for-v2020.07-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2020.07-rc2

mmc:
- Fix dt property handling via generic function

clk:
- Fix versal watchdog clock setting

nand:
- Fix zynq nand command comparison

xilinx:
- Enable ubifs
- Sync board_late_init configurations with initrd_high setup
- Make custom distro boot more verbose

zynq:
- Kconfig alignments
- Fix nand cse configuration

zynqmp:
- Fix zcu104 low level qspi configuration
- Small DT updates

Signed-off-by: Tom Rini <trini@konsulko.com>

configs/zynq_cse_nand_defconfig

diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig
index 19491c9..6a01da2 100644
--- a/configs/zynq_cse_nand_defconfig
+++ b/configs/zynq_cse_nand_defconfig
@@ -5,7 +5,7 @@
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x100000
 CONFIG_ENV_SIZE=0x190
-CONFIG_SYS_MALLOC_LEN=0x1000
+CONFIG_SYS_MALLOC_LEN=0x8000
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_SPL=y
 CONFIG_SYS_CUSTOM_LDSCRIPT=y