tree 454b2834d74a8eebb2cc8bcb17a55de079229641
parent 91d1fce1cc910ee156ecb03c95734c211c1ed3ae
author Pali Rohár <pali@kernel.org> 1649326578 +0200
committer Priyanka Jain <priyanka.jain@nxp.com> 1650973719 +0530

board: freescale: p1_p2_rdb_pc: Fix page attributes for second 1G SDRAM map

Like for first 1G SDRAM map, do not enable Caching-inhibited nor Guarded
attribute for second 1G SDRAM mapping. Whole 2G SDRAM should use caches and
also allow speculative loading (by not setting Guarded attribute).

Also enable Memory Coherency attribute for second 1G SDRAM map. In commit
316f0d0f8f3c ("powerpc: mpc85xx: Fix static TLB table for SDRAM") it was
enabled for all SDRAM maps on all other boards, just missed this one case.

As a last thing, first 1G SDRAM map has wrong comment, so adjust it.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>