commit cc3fe06e09ceb4cbac86e84e4ed3ed81da29d969
author Meng Dongyang <daniel.meng@rock-chips.com> Thu Jun 08 15:34:20 2017 +0800
committer Marek Vasut <marex@denx.de> Sat Jun 17 17:59:03 2017 +0200
tree 4872b13bb49c7f769bc58819aece8a94229dd2b9
parent 183f1d272a03962a75bf7dd7bb7bac97c99cbdb7

usb: dwc2: force to host mode if not support HNP/SRP

In current code, after running the command of "usb start", the controller
will keep in otg mode and can't switch to host mode if not support
SNP/SRP capability. So add the property of "hnp-srp-disable" in the DTS
to config the contrller work in force mode of host.

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>

drivers/usb/host/dwc2.c

diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index bbaefd2..841e596 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -43,6 +43,7 @@
 	struct dwc2_core_regs *regs;
 	int root_hub_devnum;
 	bool ext_vbus;
+	bool hnp_srp_disable;
 	bool oc_disable;
 };
 
@@ -394,6 +395,9 @@
 		usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
 	}
 #endif
+	if (priv->hnp_srp_disable)
+		usbcfg |= DWC2_GUSBCFG_FORCEHOSTMODE;
+
 	writel(usbcfg, &regs->gusbcfg);
 
 	/* Program the GAHBCFG Register. */
@@ -422,12 +426,16 @@
 
 	writel(ahbcfg, &regs->gahbcfg);
 
-	/* Program the GUSBCFG register for HNP/SRP. */
-	setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP);
+	/* Program the capabilities in GUSBCFG Register */
+	usbcfg = 0;
 
+	if (!priv->hnp_srp_disable)
+		usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP;
 #ifdef CONFIG_DWC2_IC_USB_CAP
-	setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP);
+	usbcfg |= DWC2_GUSBCFG_IC_USB_CAP;
 #endif
+
+	setbits_le32(&regs->gusbcfg, usbcfg);
 }
 
 /*
@@ -1244,6 +1252,11 @@
 	if (prop)
 		priv->oc_disable = true;
 
+	prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
+			   "hnp-srp-disable", NULL);
+	if (prop)
+		priv->hnp_srp_disable = true;
+
 	return 0;
 }