common: Convert *.c/h from UTF-8 to ASCII enconfing
Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or
names are converted.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Marek Behún <kabel@kernel.org>
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
index 1541dfb..b1bb29b 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
@@ -258,7 +258,7 @@
/* Wait for SVDD to stabilize */
udelay(100);
- /* For each PLL that’s not disabled via RCW */
+ /* For each PLL that's not disabled via RCW */
#ifdef CONFIG_SYS_FSL_SRDS_1
cfg_tmp = (cfg_rcw5 >> 22) & 0x3;
for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
index c0efc34..fbd5fd7 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
@@ -483,7 +483,7 @@
ret = -1;
}
- /* For each PLL that’s not disabled via RCW enable the SERDES */
+ /* For each PLL that's not disabled via RCW enable the SERDES */
#ifdef CONFIG_SYS_FSL_SRDS_1
cfg_tmp = cfg_rcwsrds1 & 0x3;
do_serdes_enable(cfg_tmp, serdes1_base);
diff --git a/arch/arm/mach-imx/ddrmc-vf610-calibration.c b/arch/arm/mach-imx/ddrmc-vf610-calibration.c
index cd7e95e..7d787d0 100644
--- a/arch/arm/mach-imx/ddrmc-vf610-calibration.c
+++ b/arch/arm/mach-imx/ddrmc-vf610-calibration.c
@@ -45,7 +45,7 @@
* based on trace length differences from their
* layout.
* Mismatches up to 25% or tCK (clock period) are
- * allowed, so the value in the filed doesn’t have
+ * allowed, so the value in the filed doesn't have
* to be very accurate.
*
* - 0x2 (b'10) - RDLVL_DL_0/1 - refers to adjusting the DQS strobe in relation
@@ -184,14 +184,14 @@
debug("RDLVL: PHY_RDLVL_EDGE:\t 0x%x\n",
(tmp >> DDRMC_CR101_PHY_RDLVL_EDGE_OFF) & 0x1); //set 0
- /* Program Leveling mode - CR93[SW_LVL_MODE] to ’b10 */
+ /* Program Leveling mode - CR93[SW_LVL_MODE] to 'b10 */
clrsetbits_le32(&ddrmr->cr[93], DDRMC_CR93_SW_LVL_MODE(0x3),
DDRMC_CR93_SW_LVL_MODE(0x2));
tmp = readl(&ddrmr->cr[93]);
debug("RDLVL: SW_LVL_MODE:\t 0x%x\n",
(tmp >> DDRMC_CR93_SW_LVL_MODE_OFF) & 0x3);
- /* Start procedure - CR93[SWLVL_START] to ’b1 */
+ /* Start procedure - CR93[SWLVL_START] to 'b1 */
sw_leveling_start;
/* Poll CR94[SWLVL_OP_DONE] */
@@ -211,7 +211,7 @@
0xFFFF << DDRMC_CR105_RDLVL_DL_0_OFF,
i << DDRMC_CR105_RDLVL_DL_0_OFF);
- /* Load values CR93[SWLVL_LOAD] to ’b1 */
+ /* Load values CR93[SWLVL_LOAD] to 'b1 */
sw_leveling_load_value;
/* Poll CR94[SWLVL_OP_DONE] */
@@ -263,7 +263,7 @@
0xFFFF << DDRMC_CR110_RDLVL_DL_1_OFF,
i << DDRMC_CR110_RDLVL_DL_1_OFF);
- /* Load values CR93[SWLVL_LOAD] to ’b1 */
+ /* Load values CR93[SWLVL_LOAD] to 'b1 */
sw_leveling_load_value;
/* Poll CR94[SWLVL_OP_DONE] */
@@ -317,7 +317,7 @@
sw_leveling_load_value;
sw_leveling_op_done;
- /* Exit procedure - CR94[SWLVL_EXIT] to ’b1 */
+ /* Exit procedure - CR94[SWLVL_EXIT] to 'b1 */
sw_leveling_exit;
/* Poll CR94[SWLVL_OP_DONE] */
diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c
index 1bdc568..e0da9c2 100644
--- a/arch/arm/mach-imx/mx6/clock.c
+++ b/arch/arm/mach-imx/mx6/clock.c
@@ -714,10 +714,10 @@
/*
* Register: PLL_VIDEO
* Bit Field: POST_DIV_SELECT
- * 00 — Divide by 4.
- * 01 — Divide by 2.
- * 10 — Divide by 1.
- * 11 — Reserved
+ * 00 - Divide by 4.
+ * 01 - Divide by 2.
+ * 10 - Divide by 1.
+ * 11 - Reserved
* No need to check post_div(1)
*/
for (post_div = 2; post_div <= 4; post_div <<= 1) {
diff --git a/arch/arm/mach-imx/mx7/psci-mx7.c b/arch/arm/mach-imx/mx7/psci-mx7.c
index 699a256..0b71fa4 100644
--- a/arch/arm/mach-imx/mx7/psci-mx7.c
+++ b/arch/arm/mach-imx/mx7/psci-mx7.c
@@ -631,9 +631,9 @@
* Workaround:
* If both CPU0/CPU1 are IDLE, the last IDLE CPU should
* disable GIC first, then REG_BYPASS_COUNTER is used
- * to mask wakeup INT, and then execute “wfi” is used to
+ * to mask wakeup INT, and then execute "wfi" is used to
* bring the system into power down processing safely.
- * The counter must be enabled as close to the “wfi” state
+ * The counter must be enabled as close to the "wfi" state
* as possible. The following equation can be used to
* determine the RBC counter value:
* RBC_COUNT * (1/32K RTC frequency) >=