tree c94e691e322097c7cdc43943cd3bb05b3e7c760e
parent 0e92536ed02bb822ae1dbed7f81f486add8b4152
author Stefan Roese <sr@denx.de> 1254152025 +0200
committer Stefan Roese <sr@denx.de> 1254484417 +0200

ppc4xx: Merge PPC4xx DDR and DDR2 ECC handling

This patch merges the ECC handling (ECC parity byte writing) into one
file (ecc.c) for all PPC4xx SDRAM controllers except for PPC440EPx/GRx.
This exception is because only those PPC's use the completely different
Denali SDRAM controller core.

Previously we had two routines to generate/write the ECC parity bytes.
With this patch we now only have one core function left.

Tested on Kilauea (no ECC) and Katmai (with and without ECC).

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Felix Radensky <felix@embedded-sol.com>
Cc: Grant Erickson <gerickson@nuovations.com>
Cc: Pieter Voorthuijsen <pv@prodrive.nl>