// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2021 Rockchip Electronics Co., Ltd
 * (C) Copyright 2023 Akash Gajjar <gajjar04akash@gmail.com>
 */

#include "rk356x-u-boot.dtsi"

&pcie3x2 {
	pinctrl-0 = <&pcie3x2_reset_h>;
};

&pinctrl {
	pcie {
		pcie3x2_reset_h: pcie3x2-reset-h {
			rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};
};

&sdhci {
	cap-mmc-highspeed;
	mmc-hs200-1_8v;
	mmc-hs400-1_8v;
	mmc-hs400-enhanced-strobe;
};

&sfc {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		bootph-pre-ram;
		bootph-some-ram;
		spi-max-frequency = <24000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <1>;
	};
};