Merge tag 'fsl-qoriq-next-2023-3-14' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next
Enable DM_SERIAL for freescale ls2080a
Drop non DM_ETH code for freescale:
lx2160a/ls2080rdb/ls2080aqds/ls1088a
diff --git a/arch/arm/dts/fsl-ls1088a-rdb.dts b/arch/arm/dts/fsl-ls1088a-rdb.dts
index ad05943..01f8fcb 100644
--- a/arch/arm/dts/fsl-ls1088a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1088a-rdb.dts
@@ -19,13 +19,13 @@
&dpmac1 {
status = "okay";
- phy-connection-type = "xgmii";
+ phy-connection-type = "10gbase-r";
};
&dpmac2 {
status = "okay";
phy-handle = <&mdio2_phy1>;
- phy-connection-type = "xgmii";
+ phy-connection-type = "10gbase-r";
};
&dpmac3 {
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index a183745..d754eb4 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -6,18 +6,32 @@
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*/
+#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
+
/ {
compatible = "fsl,ls2080a";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ };
+
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x80000000>;
/* DRAM space - 1, size : 2 GB DRAM */
};
+ sysclk: sysclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "sysclk";
+ };
+
gic: interrupt-controller@6000000 {
compatible = "arm,gic-v3";
reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
@@ -35,20 +49,37 @@
<1 10 0x8>; /* Hypervisor PPI, active-low */
};
- serial0: serial@21c0500 {
- device_type = "serial";
- compatible = "fsl,ns16550", "ns16550a";
- reg = <0x0 0x21c0500 0x0 0x100>;
- clock-frequency = <0>; /* Updated by bootloader */
- interrupts = <0 32 0x1>; /* edge triggered */
- };
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
+
+ clockgen: clocking@1300000 {
+ compatible = "fsl,ls2080a-clockgen";
+ reg = <0 0x1300000 0 0xa0000>;
+ #clock-cells = <2>;
+ clocks = <&sysclk>;
+ };
+
+ serial0: serial@21c0500 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21c0500 0x0 0x100>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(4)>;
+ interrupts = <0 32 0x4>; /* Level high type */
+ bootph-all;
+ };
- serial1: serial@21c0600 {
- device_type = "serial";
- compatible = "fsl,ns16550", "ns16550a";
- reg = <0x0 0x21c0600 0x0 0x100>;
- clock-frequency = <0>; /* Updated by bootloader */
- interrupts = <0 32 0x1>; /* edge triggered */
+ serial1: serial@21c0600 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21c0600 0x0 0x100>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(4)>;
+ interrupts = <0 32 0x4>; /* Level high type */
+ bootph-all;
+ };
};
i2c0: i2c@2000000 {
diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c
index 8fe643f..f62f5fd 100644
--- a/board/freescale/ls1088a/eth_ls1088aqds.c
+++ b/board/freescale/ls1088a/eth_ls1088aqds.c
@@ -3,742 +3,9 @@
* Copyright 2017 NXP
*/
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <log.h>
-#include <net.h>
-#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/fsl_serdes.h>
-#include <hwconfig.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <phy.h>
-#include <fm_eth.h>
-#include <i2c.h>
-#include <miiphy.h>
#include <fsl-mc/fsl_mc.h>
-#include <fsl-mc/ldpaa_wriop.h>
-#include <linux/delay.h>
-
-#include "../common/qixis.h"
-
-#include "ls1088a_qixis.h"
-
-#ifndef CONFIG_DM_ETH
-#ifdef CONFIG_FSL_MC_ENET
-
-#define SFP_TX 0
-
- /* - In LS1088A A there are only 16 SERDES lanes, spread across 2 SERDES banks.
- * Bank 1 -> Lanes A, B, C, D,
- * Bank 2 -> Lanes A,B, C, D,
- */
-
- /* Mapping of 8 SERDES lanes to LS1088A QDS board slots. A value of '0' here
- * means that the mapping must be determined dynamically, or that the lane
- * maps to something other than a board slot.
- */
-
-static u8 lane_to_slot_fsm1[] = {
- 0, 0, 0, 0, 0, 0, 0, 0
-};
-
-/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
- * housed.
- */
-
-static int xqsgii_riser_phy_addr[] = {
- XQSGMII_CARD_PHY1_PORT0_ADDR,
- XQSGMII_CARD_PHY2_PORT0_ADDR,
- XQSGMII_CARD_PHY3_PORT0_ADDR,
- XQSGMII_CARD_PHY4_PORT0_ADDR,
- XQSGMII_CARD_PHY3_PORT2_ADDR,
- XQSGMII_CARD_PHY1_PORT2_ADDR,
- XQSGMII_CARD_PHY4_PORT2_ADDR,
- XQSGMII_CARD_PHY2_PORT2_ADDR,
-};
-
-static int sgmii_riser_phy_addr[] = {
- SGMII_CARD_PORT1_PHY_ADDR,
- SGMII_CARD_PORT2_PHY_ADDR,
- SGMII_CARD_PORT3_PHY_ADDR,
- SGMII_CARD_PORT4_PHY_ADDR,
-};
-
-/* Slot2 does not have EMI connections */
-#define EMI_NONE 0xFF
-#define EMI1_RGMII1 0
-#define EMI1_RGMII2 1
-#define EMI1_SLOT1 2
-
-static const char * const mdio_names[] = {
- "LS1088A_QDS_MDIO0",
- "LS1088A_QDS_MDIO1",
- "LS1088A_QDS_MDIO2",
- DEFAULT_WRIOP_MDIO2_NAME,
-};
-
-struct ls1088a_qds_mdio {
- u8 muxval;
- struct mii_dev *realbus;
-};
-
-struct reg_pair {
- uint addr;
- u8 *val;
-};
-
-static void sgmii_configure_repeater(int dpmac)
-{
- struct mii_dev *bus;
- uint8_t a = 0xf;
- int i, j, k, ret;
- unsigned short value;
- const char *dev = "LS1088A_QDS_MDIO2";
- int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
- int i2c_phy_addr = 0;
- int phy_addr = 0;
-
- uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
- uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
- uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
- uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
-
- u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
- struct reg_pair reg_pair[10] = {
- {6, ®_val[0]}, {4, ®_val[1]},
- {8, ®_val[2]}, {0xf, NULL},
- {0x11, NULL}, {0x16, NULL},
- {0x18, NULL}, {0x23, ®_val[3]},
- {0x2d, ®_val[4]}, {4, ®_val[5]},
- };
-#if CONFIG_IS_ENABLED(DM_I2C)
- struct udevice *udev;
-#endif
-
- /* Set I2c to Slot 1 */
-#if !CONFIG_IS_ENABLED(DM_I2C)
- ret = i2c_write(0x77, 0, 0, &a, 1);
-#else
- ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
- if (!ret)
- ret = dm_i2c_write(udev, 0, &a, 1);
-#endif
- if (ret)
- goto error;
-
- switch (dpmac) {
- case 1:
- i2c_phy_addr = i2c_addr[1];
- phy_addr = 4;
- break;
- case 2:
- i2c_phy_addr = i2c_addr[0];
- phy_addr = 0;
- break;
- case 3:
- i2c_phy_addr = i2c_addr[3];
- phy_addr = 0xc;
- break;
- case 7:
- i2c_phy_addr = i2c_addr[2];
- phy_addr = 8;
- break;
- }
-
- /* Check the PHY status */
- ret = miiphy_set_current_dev(dev);
- if (ret > 0)
- goto error;
-
- bus = mdio_get_current_dev();
- debug("Reading from bus %s\n", bus->name);
-
- ret = miiphy_write(dev, phy_addr, 0x1f, 3);
- if (ret > 0)
- goto error;
-
- mdelay(10);
- ret = miiphy_read(dev, phy_addr, 0x11, &value);
- if (ret > 0)
- goto error;
-
- mdelay(10);
-
- if ((value & 0xfff) == 0x401) {
- miiphy_write(dev, phy_addr, 0x1f, 0);
- printf("DPMAC %d:PHY is ..... Configured\n", dpmac);
- return;
- }
-
-#if CONFIG_IS_ENABLED(DM_I2C)
- i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev);
-#endif
-
- for (i = 0; i < 4; i++) {
- for (j = 0; j < 4; j++) {
- reg_pair[3].val = &ch_a_eq[i];
- reg_pair[4].val = &ch_a_ctl2[j];
- reg_pair[5].val = &ch_b_eq[i];
- reg_pair[6].val = &ch_b_ctl2[j];
- for (k = 0; k < 10; k++) {
-#if !CONFIG_IS_ENABLED(DM_I2C)
- ret = i2c_write(i2c_phy_addr,
- reg_pair[k].addr,
- 1, reg_pair[k].val, 1);
-#else
- ret = i2c_get_chip_for_busnum(0,
- i2c_phy_addr,
- 1, &udev);
- if (!ret)
- ret = dm_i2c_write(udev,
- reg_pair[k].addr,
- reg_pair[k].val, 1);
-#endif
- if (ret)
- goto error;
- }
-
- mdelay(100);
- ret = miiphy_read(dev, phy_addr, 0x11, &value);
- if (ret > 0)
- goto error;
-
- mdelay(100);
- ret = miiphy_read(dev, phy_addr, 0x11, &value);
- if (ret > 0)
- goto error;
-
- if ((value & 0xfff) == 0x401) {
- printf("DPMAC %d :PHY is configured ",
- dpmac);
- printf("after setting repeater 0x%x\n",
- value);
- i = 5;
- j = 5;
- } else {
- printf("DPMAC %d :PHY is failed to ",
- dpmac);
- printf("configure the repeater 0x%x\n", value);
- }
- }
- }
- miiphy_write(dev, phy_addr, 0x1f, 0);
-error:
- if (ret)
- printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac);
- return;
-}
-
-static void qsgmii_configure_repeater(int dpmac)
-{
- uint8_t a = 0xf;
- int i, j, k;
- int i2c_phy_addr = 0;
- int phy_addr = 0;
- int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
-
- uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
- uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
- uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
- uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
-
- u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
- struct reg_pair reg_pair[10] = {
- {6, ®_val[0]}, {4, ®_val[1]},
- {8, ®_val[2]}, {0xf, NULL},
- {0x11, NULL}, {0x16, NULL},
- {0x18, NULL}, {0x23, ®_val[3]},
- {0x2d, ®_val[4]}, {4, ®_val[5]},
- };
-
- const char *dev = mdio_names[EMI1_SLOT1];
- int ret = 0;
- unsigned short value;
-#if CONFIG_IS_ENABLED(DM_I2C)
- struct udevice *udev;
-#endif
-
- /* Set I2c to Slot 1 */
-#if !CONFIG_IS_ENABLED(DM_I2C)
- ret = i2c_write(0x77, 0, 0, &a, 1);
-#else
- ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
- if (!ret)
- ret = dm_i2c_write(udev, 0, &a, 1);
-#endif
- if (ret)
- goto error;
-
- switch (dpmac) {
- case 7:
- case 8:
- case 9:
- case 10:
- i2c_phy_addr = i2c_addr[2];
- phy_addr = 8;
- break;
-
- case 3:
- case 4:
- case 5:
- case 6:
- i2c_phy_addr = i2c_addr[3];
- phy_addr = 0xc;
- break;
- }
-
- /* Check the PHY status */
- ret = miiphy_set_current_dev(dev);
- ret = miiphy_write(dev, phy_addr, 0x1f, 3);
- mdelay(10);
- ret = miiphy_read(dev, phy_addr, 0x11, &value);
- mdelay(10);
- ret = miiphy_read(dev, phy_addr, 0x11, &value);
- mdelay(10);
- if ((value & 0xf) == 0xf) {
- miiphy_write(dev, phy_addr, 0x1f, 0);
- printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
- return;
- }
-
-#if CONFIG_IS_ENABLED(DM_I2C)
- i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev);
-#endif
-
- for (i = 0; i < 4; i++) {
- for (j = 0; j < 4; j++) {
- reg_pair[3].val = &ch_a_eq[i];
- reg_pair[4].val = &ch_a_ctl2[j];
- reg_pair[5].val = &ch_b_eq[i];
- reg_pair[6].val = &ch_b_ctl2[j];
-
- for (k = 0; k < 10; k++) {
-#if !CONFIG_IS_ENABLED(DM_I2C)
- ret = i2c_write(i2c_phy_addr,
- reg_pair[k].addr,
- 1, reg_pair[k].val, 1);
-#else
- ret = i2c_get_chip_for_busnum(0,
- i2c_addr[dpmac],
- 1, &udev);
- if (!ret)
- ret = dm_i2c_write(udev,
- reg_pair[k].addr,
- reg_pair[k].val, 1);
-#endif
- if (ret)
- goto error;
- }
-
- ret = miiphy_read(dev, phy_addr, 0x11, &value);
- if (ret > 0)
- goto error;
- mdelay(1);
- ret = miiphy_read(dev, phy_addr, 0x11, &value);
- if (ret > 0)
- goto error;
- mdelay(10);
- if ((value & 0xf) == 0xf) {
- miiphy_write(dev, phy_addr, 0x1f, 0);
- printf("DPMAC %d :PHY is ..... Configured\n",
- dpmac);
- return;
- }
- }
- }
-error:
- printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
- return;
-}
-
-static const char *ls1088a_qds_mdio_name_for_muxval(u8 muxval)
-{
- return mdio_names[muxval];
-}
-
-struct mii_dev *mii_dev_for_muxval(u8 muxval)
-{
- struct mii_dev *bus;
- const char *name = ls1088a_qds_mdio_name_for_muxval(muxval);
-
- if (!name) {
- printf("No bus for muxval %x\n", muxval);
- return NULL;
- }
-
- bus = miiphy_get_dev_by_name(name);
-
- if (!bus) {
- printf("No bus by name %s\n", name);
- return NULL;
- }
-
- return bus;
-}
-
-static void ls1088a_qds_enable_SFP_TX(u8 muxval)
-{
- u8 brdcfg9;
-
- brdcfg9 = QIXIS_READ(brdcfg[9]);
- brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
- brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
- QIXIS_WRITE(brdcfg[9], brdcfg9);
-}
-
-static void ls1088a_qds_mux_mdio(u8 muxval)
-{
- u8 brdcfg4;
-
- if (muxval <= 5) {
- brdcfg4 = QIXIS_READ(brdcfg[4]);
- brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
- brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
- QIXIS_WRITE(brdcfg[4], brdcfg4);
- }
-}
-
-static int ls1088a_qds_mdio_read(struct mii_dev *bus, int addr,
- int devad, int regnum)
-{
- struct ls1088a_qds_mdio *priv = bus->priv;
-
- ls1088a_qds_mux_mdio(priv->muxval);
-
- return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int ls1088a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
- int regnum, u16 value)
-{
- struct ls1088a_qds_mdio *priv = bus->priv;
-
- ls1088a_qds_mux_mdio(priv->muxval);
-
- return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
-}
-
-static int ls1088a_qds_mdio_reset(struct mii_dev *bus)
-{
- struct ls1088a_qds_mdio *priv = bus->priv;
-
- return priv->realbus->reset(priv->realbus);
-}
-
-static int ls1088a_qds_mdio_init(char *realbusname, u8 muxval)
-{
- struct ls1088a_qds_mdio *pmdio;
- struct mii_dev *bus = mdio_alloc();
-
- if (!bus) {
- printf("Failed to allocate ls1088a_qds MDIO bus\n");
- return -1;
- }
-
- pmdio = malloc(sizeof(*pmdio));
- if (!pmdio) {
- printf("Failed to allocate ls1088a_qds private data\n");
- free(bus);
- return -1;
- }
-
- bus->read = ls1088a_qds_mdio_read;
- bus->write = ls1088a_qds_mdio_write;
- bus->reset = ls1088a_qds_mdio_reset;
- sprintf(bus->name, ls1088a_qds_mdio_name_for_muxval(muxval));
-
- pmdio->realbus = miiphy_get_dev_by_name(realbusname);
-
- if (!pmdio->realbus) {
- printf("No bus with name %s\n", realbusname);
- free(bus);
- free(pmdio);
- return -1;
- }
-
- pmdio->muxval = muxval;
- bus->priv = pmdio;
-
- return mdio_register(bus);
-}
-
-/*
- * Initialize the dpmac_info array.
- *
- */
-static void initialize_dpmac_to_slot(void)
-{
- struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
- u32 serdes1_prtcl, cfg;
-
- cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
- FSL_CHASSIS3_SRDS1_PRTCL_MASK;
- cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
- serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
-
- switch (serdes1_prtcl) {
- case 0x12:
- printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
- serdes1_prtcl);
- lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
- lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
- lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
- lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;
- break;
- case 0x15:
- case 0x1D:
- printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
- serdes1_prtcl);
- lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
- lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
- lane_to_slot_fsm1[2] = EMI_NONE;
- lane_to_slot_fsm1[3] = EMI_NONE;
- break;
- case 0x1E:
- printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
- serdes1_prtcl);
- lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
- lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
- lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
- lane_to_slot_fsm1[3] = EMI_NONE;
- break;
- case 0x3A:
- printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
- serdes1_prtcl);
- lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
- lane_to_slot_fsm1[1] = EMI_NONE;
- lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
- lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;
- break;
-
- default:
- printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
- __func__, serdes1_prtcl);
- break;
- }
-}
-
-void ls1088a_handle_phy_interface_sgmii(int dpmac_id)
-{
- struct mii_dev *bus;
- struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
- u32 serdes1_prtcl, cfg;
-
- cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
- FSL_CHASSIS3_SRDS1_PRTCL_MASK;
- cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
- serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
-
- int *riser_phy_addr;
- char *env_hwconfig = env_get("hwconfig");
-
- if (hwconfig_f("xqsgmii", env_hwconfig))
- riser_phy_addr = &xqsgii_riser_phy_addr[0];
- else
- riser_phy_addr = &sgmii_riser_phy_addr[0];
-
- switch (serdes1_prtcl) {
- case 0x12:
- case 0x15:
- case 0x1E:
- case 0x3A:
- switch (dpmac_id) {
- case 1:
- wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[1]);
- break;
- case 2:
- wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[0]);
- break;
- case 3:
- wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[3]);
- break;
- case 7:
- wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[2]);
- break;
- default:
- printf("WRIOP: Wrong DPMAC%d set to SGMII", dpmac_id);
- break;
- }
- break;
- default:
- printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
- __func__, serdes1_prtcl);
- return;
- }
- dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
- bus = mii_dev_for_muxval(EMI1_SLOT1);
- wriop_set_mdio(dpmac_id, bus);
-}
-
-void ls1088a_handle_phy_interface_qsgmii(int dpmac_id)
-{
- struct mii_dev *bus;
- struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
- u32 serdes1_prtcl, cfg;
-
- cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
- FSL_CHASSIS3_SRDS1_PRTCL_MASK;
- cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
- serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
-
- switch (serdes1_prtcl) {
- case 0x1D:
- case 0x1E:
- switch (dpmac_id) {
- case 3:
- case 4:
- case 5:
- case 6:
- wriop_set_phy_address(dpmac_id, 0, dpmac_id + 9);
- break;
- case 7:
- case 8:
- case 9:
- case 10:
- wriop_set_phy_address(dpmac_id, 0, dpmac_id + 1);
- break;
- }
-
- dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
- bus = mii_dev_for_muxval(EMI1_SLOT1);
- wriop_set_mdio(dpmac_id, bus);
- break;
- default:
- printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
- serdes1_prtcl);
- break;
- }
-}
-
-void ls1088a_handle_phy_interface_xsgmii(int i)
-{
- struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
- u32 serdes1_prtcl, cfg;
-
- cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
- FSL_CHASSIS3_SRDS1_PRTCL_MASK;
- cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
- serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
-
- switch (serdes1_prtcl) {
- case 0x15:
- case 0x1D:
- case 0x1E:
- wriop_set_phy_address(i, 0, i + 26);
- ls1088a_qds_enable_SFP_TX(SFP_TX);
- break;
- default:
- printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
- serdes1_prtcl);
- break;
- }
-}
-
-static void ls1088a_handle_phy_interface_rgmii(int dpmac_id)
-{
- struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
- u32 serdes1_prtcl, cfg;
- struct mii_dev *bus;
-
- cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
- FSL_CHASSIS3_SRDS1_PRTCL_MASK;
- cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
- serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
-
- switch (dpmac_id) {
- case 4:
- wriop_set_phy_address(dpmac_id, 0, RGMII_PHY1_ADDR);
- dpmac_info[dpmac_id].board_mux = EMI1_RGMII1;
- bus = mii_dev_for_muxval(EMI1_RGMII1);
- wriop_set_mdio(dpmac_id, bus);
- break;
- case 5:
- wriop_set_phy_address(dpmac_id, 0, RGMII_PHY2_ADDR);
- dpmac_info[dpmac_id].board_mux = EMI1_RGMII2;
- bus = mii_dev_for_muxval(EMI1_RGMII2);
- wriop_set_mdio(dpmac_id, bus);
- break;
- default:
- printf("qds: WRIOP: Unsupported RGMII SerDes Protocol 0x%02x\n",
- serdes1_prtcl);
- break;
- }
-}
-#endif
-
-int board_eth_init(struct bd_info *bis)
-{
- int error = 0, i;
-#ifdef CONFIG_FSL_MC_ENET
- struct memac_mdio_info *memac_mdio0_info;
- char *env_hwconfig = env_get("hwconfig");
-
- initialize_dpmac_to_slot();
-
- memac_mdio0_info = (struct memac_mdio_info *)malloc(
- sizeof(struct memac_mdio_info));
- memac_mdio0_info->regs =
- (struct memac_mdio_controller *)
- CFG_SYS_FSL_WRIOP1_MDIO1;
- memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
-
- /* Register the real MDIO1 bus */
- fm_memac_mdio_init(bis, memac_mdio0_info);
- /* Register the muxing front-ends to the MDIO buses */
- ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII1);
- ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII2);
- ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
-
- for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
- switch (wriop_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_RGMII:
- case PHY_INTERFACE_MODE_RGMII_ID:
- ls1088a_handle_phy_interface_rgmii(i);
- break;
- case PHY_INTERFACE_MODE_QSGMII:
- ls1088a_handle_phy_interface_qsgmii(i);
- break;
- case PHY_INTERFACE_MODE_SGMII:
- ls1088a_handle_phy_interface_sgmii(i);
- break;
- case PHY_INTERFACE_MODE_XGMII:
- ls1088a_handle_phy_interface_xsgmii(i);
- break;
- default:
- break;
-
- if (i == 16)
- i = NUM_WRIOP_PORTS;
- }
- }
-
- error = cpu_eth_init(bis);
-
- if (hwconfig_f("xqsgmii", env_hwconfig)) {
- for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
- switch (wriop_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_QSGMII:
- qsgmii_configure_repeater(i);
- break;
- case PHY_INTERFACE_MODE_SGMII:
- sgmii_configure_repeater(i);
- break;
- default:
- break;
- }
-
- if (i == 16)
- i = NUM_WRIOP_PORTS;
- }
- }
-#endif
- error = pci_eth_init(bis);
- return error;
-}
-#endif // !CONFIG_DM_ETH
#if defined(CONFIG_RESET_PHY_R)
void reset_phy(void)
@@ -747,10 +14,10 @@
}
#endif /* CONFIG_RESET_PHY_R */
-#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
+#if defined(CONFIG_MULTI_DTB_FIT)
-/* Structure to hold SERDES protocols supported in case of
- * CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
+/* Structure to hold SERDES protocols supported (network interfaces are
+ * described in the DTS).
*
* @serdes_block: the index of the SERDES block
* @serdes_protocol: the decimal value of the protocol supported
diff --git a/board/freescale/ls1088a/eth_ls1088ardb.c b/board/freescale/ls1088a/eth_ls1088ardb.c
index 5792070..fb6f9c1 100644
--- a/board/freescale/ls1088a/eth_ls1088ardb.c
+++ b/board/freescale/ls1088a/eth_ls1088ardb.c
@@ -3,100 +3,7 @@
* Copyright 2017 NXP
*/
-#include <common.h>
-#include <command.h>
-#include <net.h>
-#include <netdev.h>
-#include <malloc.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fm_eth.h>
-#include <asm/io.h>
-#include <exports.h>
-#include <asm/arch/fsl_serdes.h>
#include <fsl-mc/fsl_mc.h>
-#include <fsl-mc/ldpaa_wriop.h>
-
-#ifndef CONFIG_DM_ETH
-int board_eth_init(struct bd_info *bis)
-{
-#if defined(CONFIG_FSL_MC_ENET)
- int i, interface;
- struct memac_mdio_info mdio_info;
- struct mii_dev *dev;
- struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
- struct memac_mdio_controller *reg;
- u32 srds_s1, cfg;
-
- cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
- FSL_CHASSIS3_SRDS1_PRTCL_MASK;
- cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
-
- srds_s1 = serdes_get_number(FSL_SRDS_1, cfg);
-
- reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO1;
- mdio_info.regs = reg;
- mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
-
- /* Register the EMI 1 */
- fm_memac_mdio_init(bis, &mdio_info);
-
- reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO2;
- mdio_info.regs = reg;
- mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
-
- /* Register the EMI 2 */
- fm_memac_mdio_init(bis, &mdio_info);
-
- switch (srds_s1) {
- case 0x1D:
- /*
- * 10GBase-R does not need a PHY to work, but to avoid U-boot
- * use default PHY address which is zero to a MAC when it found
- * a MAC has no PHY address, we give a PHY address to 10GBase-R
- * MAC error.
- */
- wriop_set_phy_address(WRIOP1_DPMAC1, 0, 0x0a);
- wriop_set_phy_address(WRIOP1_DPMAC2, 0, AQ_PHY_ADDR1);
- wriop_set_phy_address(WRIOP1_DPMAC3, 0, QSGMII1_PORT1_PHY_ADDR);
- wriop_set_phy_address(WRIOP1_DPMAC4, 0, QSGMII1_PORT2_PHY_ADDR);
- wriop_set_phy_address(WRIOP1_DPMAC5, 0, QSGMII1_PORT3_PHY_ADDR);
- wriop_set_phy_address(WRIOP1_DPMAC6, 0, QSGMII1_PORT4_PHY_ADDR);
- wriop_set_phy_address(WRIOP1_DPMAC7, 0, QSGMII2_PORT1_PHY_ADDR);
- wriop_set_phy_address(WRIOP1_DPMAC8, 0, QSGMII2_PORT2_PHY_ADDR);
- wriop_set_phy_address(WRIOP1_DPMAC9, 0, QSGMII2_PORT3_PHY_ADDR);
- wriop_set_phy_address(WRIOP1_DPMAC10, 0,
- QSGMII2_PORT4_PHY_ADDR);
-
- break;
- default:
- printf("SerDes1 protocol 0x%x is not supported on LS1088ARDB\n",
- srds_s1);
- break;
- }
-
- for (i = WRIOP1_DPMAC3; i <= WRIOP1_DPMAC10; i++) {
- interface = wriop_get_enet_if(i);
- switch (interface) {
- case PHY_INTERFACE_MODE_QSGMII:
- dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
- wriop_set_mdio(i, dev);
- break;
- default:
- break;
- }
- }
-
- dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
- wriop_set_mdio(WRIOP1_DPMAC2, dev);
-
- cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
-
- return pci_eth_init(bis);
-}
-#endif
#if defined(CONFIG_RESET_PHY_R)
void reset_phy(void)
diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c
index 0d3f22c..7a1047a 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -824,7 +824,7 @@
ppa_init();
#endif
-#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
+#if !defined(CONFIG_SYS_EARLY_PCI_INIT)
pci_init();
#endif
diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c
index 6da6e5c..0d0d5de 100644
--- a/board/freescale/ls2080aqds/eth.c
+++ b/board/freescale/ls2080aqds/eth.c
@@ -3,987 +3,12 @@
* Copyright 2015 Freescale Semiconductor, Inc.
*/
-#include <common.h>
-#include <env.h>
-#include <log.h>
-#include <net.h>
-#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/fsl_serdes.h>
-#include <hwconfig.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <fm_eth.h>
-#include <i2c.h>
-#include <miiphy.h>
#include <fsl-mc/fsl_mc.h>
-#include <fsl-mc/ldpaa_wriop.h>
-#include <linux/delay.h>
-
-#include "../common/qixis.h"
-
-#include "ls2080aqds_qixis.h"
#define MC_BOOT_ENV_VAR "mcinitcmd"
-#ifndef CONFIG_DM_ETH
-
-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
- /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
- * Bank 1 -> Lanes A, B, C, D, E, F, G, H
- * Bank 2 -> Lanes A,B, C, D, E, F, G, H
- */
-
- /* Mapping of 16 SERDES lanes to LS2080A QDS board slots. A value of '0' here
- * means that the mapping must be determined dynamically, or that the lane
- * maps to something other than a board slot.
- */
-
-static u8 lane_to_slot_fsm1[] = {
- 0, 0, 0, 0, 0, 0, 0, 0
-};
-
-static u8 lane_to_slot_fsm2[] = {
- 0, 0, 0, 0, 0, 0, 0, 0
-};
-
-/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
- * housed.
- */
-
-static int xqsgii_riser_phy_addr[] = {
- XQSGMII_CARD_PHY1_PORT0_ADDR,
- XQSGMII_CARD_PHY2_PORT0_ADDR,
- XQSGMII_CARD_PHY3_PORT0_ADDR,
- XQSGMII_CARD_PHY4_PORT0_ADDR,
- XQSGMII_CARD_PHY3_PORT2_ADDR,
- XQSGMII_CARD_PHY1_PORT2_ADDR,
- XQSGMII_CARD_PHY4_PORT2_ADDR,
- XQSGMII_CARD_PHY2_PORT2_ADDR,
-};
-
-static int sgmii_riser_phy_addr[] = {
- SGMII_CARD_PORT1_PHY_ADDR,
- SGMII_CARD_PORT2_PHY_ADDR,
- SGMII_CARD_PORT3_PHY_ADDR,
- SGMII_CARD_PORT4_PHY_ADDR,
-};
-
-/* Slot2 does not have EMI connections */
-#define EMI_NONE 0xFF
-#define EMI1_SLOT1 0
-#define EMI1_SLOT2 1
-#define EMI1_SLOT3 2
-#define EMI1_SLOT4 3
-#define EMI1_SLOT5 4
-#define EMI1_SLOT6 5
-#define EMI2 6
-#define SFP_TX 0
-
-static const char * const mdio_names[] = {
- "LS2080A_QDS_MDIO0",
- "LS2080A_QDS_MDIO1",
- "LS2080A_QDS_MDIO2",
- "LS2080A_QDS_MDIO3",
- "LS2080A_QDS_MDIO4",
- "LS2080A_QDS_MDIO5",
- DEFAULT_WRIOP_MDIO2_NAME,
-};
-
-struct ls2080a_qds_mdio {
- u8 muxval;
- struct mii_dev *realbus;
-};
-
-struct reg_pair {
- uint addr;
- u8 *val;
-};
-
-static void sgmii_configure_repeater(int serdes_port)
-{
- struct mii_dev *bus;
- uint8_t a = 0xf;
- int i, j, k, ret;
- int dpmac_id = 0, dpmac, mii_bus = 0;
- unsigned short value;
- char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
- uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60};
-
- uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
- uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
- uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
- uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
-
- u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
- struct reg_pair reg_pair[10] = {
- {6, ®_val[0]}, {4, ®_val[1]},
- {8, ®_val[2]}, {0xf, NULL},
- {0x11, NULL}, {0x16, NULL},
- {0x18, NULL}, {0x23, ®_val[3]},
- {0x2d, ®_val[4]}, {4, ®_val[5]},
- };
-
- int *riser_phy_addr = &xqsgii_riser_phy_addr[0];
-#if CONFIG_IS_ENABLED(DM_I2C)
- struct udevice *udev;
-#endif
-
- /* Set I2c to Slot 1 */
-#if !CONFIG_IS_ENABLED(DM_I2C)
- ret = i2c_write(0x77, 0, 0, &a, 1);
-#else
- ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
- if (!ret)
- ret = dm_i2c_write(udev, 0, &a, 1);
-#endif
- if (ret)
- goto error;
-
- for (dpmac = 0; dpmac < 8; dpmac++) {
- /* Check the PHY status */
- switch (serdes_port) {
- case 1:
- mii_bus = 0;
- dpmac_id = dpmac + 1;
- break;
- case 2:
- mii_bus = 1;
- dpmac_id = dpmac + 9;
- a = 0xb;
-#if !CONFIG_IS_ENABLED(DM_I2C)
- ret = i2c_write(0x76, 0, 0, &a, 1);
-#else
- ret = i2c_get_chip_for_busnum(0, 0x76, 1, &udev);
- if (!ret)
- ret = dm_i2c_write(udev, 0, &a, 1);
-#endif
- if (ret)
- goto error;
- break;
- }
-
- ret = miiphy_set_current_dev(dev[mii_bus]);
- if (ret > 0)
- goto error;
-
- bus = mdio_get_current_dev();
- debug("Reading from bus %s\n", bus->name);
-
- ret = miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f,
- 3);
- if (ret > 0)
- goto error;
-
- mdelay(10);
- ret = miiphy_read(dev[mii_bus], riser_phy_addr[dpmac], 0x11,
- &value);
- if (ret > 0)
- goto error;
-
- mdelay(10);
-
- if ((value & 0xfff) == 0x401) {
- printf("DPMAC %d:PHY is ..... Configured\n", dpmac_id);
- miiphy_write(dev[mii_bus], riser_phy_addr[dpmac],
- 0x1f, 0);
- continue;
- }
-
- for (i = 0; i < 4; i++) {
- for (j = 0; j < 4; j++) {
- reg_pair[3].val = &ch_a_eq[i];
- reg_pair[4].val = &ch_a_ctl2[j];
- reg_pair[5].val = &ch_b_eq[i];
- reg_pair[6].val = &ch_b_ctl2[j];
-
- for (k = 0; k < 10; k++) {
-#if !CONFIG_IS_ENABLED(DM_I2C)
- ret = i2c_write(i2c_addr[dpmac],
- reg_pair[k].addr,
- 1, reg_pair[k].val, 1);
-#else
- ret = i2c_get_chip_for_busnum(0,
- i2c_addr[dpmac],
- 1, &udev);
- if (!ret)
- ret = dm_i2c_write(udev,
- reg_pair[k].addr,
- reg_pair[k].val, 1);
-#endif
- if (ret)
- goto error;
- }
-
- mdelay(100);
- ret = miiphy_read(dev[mii_bus],
- riser_phy_addr[dpmac],
- 0x11, &value);
- if (ret > 0)
- goto error;
-
- mdelay(100);
- ret = miiphy_read(dev[mii_bus],
- riser_phy_addr[dpmac],
- 0x11, &value);
- if (ret > 0)
- goto error;
-
- if ((value & 0xfff) == 0x401) {
- printf("DPMAC %d :PHY is configured ",
- dpmac_id);
- printf("after setting repeater 0x%x\n",
- value);
- i = 5;
- j = 5;
- } else {
- printf("DPMAC %d :PHY is failed to ",
- dpmac_id);
- printf("configure the repeater 0x%x\n",
- value);
- }
- }
- }
- miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f, 0);
- }
-error:
- if (ret)
- printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac_id);
- return;
-}
-
-static void qsgmii_configure_repeater(int dpmac)
-{
- uint8_t a = 0xf;
- int i, j, k;
- int i2c_phy_addr = 0;
- int phy_addr = 0;
- int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
-
- uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
- uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
- uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
- uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
-
- u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
- struct reg_pair reg_pair[10] = {
- {6, ®_val[0]}, {4, ®_val[1]},
- {8, ®_val[2]}, {0xf, NULL},
- {0x11, NULL}, {0x16, NULL},
- {0x18, NULL}, {0x23, ®_val[3]},
- {0x2d, ®_val[4]}, {4, ®_val[5]},
- };
-
- const char *dev = "LS2080A_QDS_MDIO0";
- int ret = 0;
- unsigned short value;
-#if CONFIG_IS_ENABLED(DM_I2C)
- struct udevice *udev;
-#endif
-
- /* Set I2c to Slot 1 */
-#if !CONFIG_IS_ENABLED(DM_I2C)
- ret = i2c_write(0x77, 0, 0, &a, 1);
-#else
- ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
- if (!ret)
- ret = dm_i2c_write(udev, 0, &a, 1);
-#endif
- if (ret)
- goto error;
-
- switch (dpmac) {
- case 1:
- case 2:
- case 3:
- case 4:
- i2c_phy_addr = i2c_addr[0];
- phy_addr = 0;
- break;
-
- case 5:
- case 6:
- case 7:
- case 8:
- i2c_phy_addr = i2c_addr[1];
- phy_addr = 4;
- break;
-
- case 9:
- case 10:
- case 11:
- case 12:
- i2c_phy_addr = i2c_addr[2];
- phy_addr = 8;
- break;
-
- case 13:
- case 14:
- case 15:
- case 16:
- i2c_phy_addr = i2c_addr[3];
- phy_addr = 0xc;
- break;
- }
-
- /* Check the PHY status */
- ret = miiphy_set_current_dev(dev);
- ret = miiphy_write(dev, phy_addr, 0x1f, 3);
- mdelay(10);
- ret = miiphy_read(dev, phy_addr, 0x11, &value);
- mdelay(10);
- ret = miiphy_read(dev, phy_addr, 0x11, &value);
- mdelay(10);
- if ((value & 0xf) == 0xf) {
- printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
- return;
- }
-
- for (i = 0; i < 4; i++) {
- for (j = 0; j < 4; j++) {
- reg_pair[3].val = &ch_a_eq[i];
- reg_pair[4].val = &ch_a_ctl2[j];
- reg_pair[5].val = &ch_b_eq[i];
- reg_pair[6].val = &ch_b_ctl2[j];
-
- for (k = 0; k < 10; k++) {
-#if !CONFIG_IS_ENABLED(DM_I2C)
- ret = i2c_write(i2c_phy_addr,
- reg_pair[k].addr,
- 1, reg_pair[k].val, 1);
-#else
- ret = i2c_get_chip_for_busnum(0,
- i2c_phy_addr,
- 1, &udev);
- if (!ret)
- ret = dm_i2c_write(udev,
- reg_pair[k].addr,
- reg_pair[k].val, 1);
-#endif
- if (ret)
- goto error;
- }
-
- mdelay(100);
- ret = miiphy_read(dev, phy_addr, 0x11, &value);
- if (ret > 0)
- goto error;
- mdelay(1);
- ret = miiphy_read(dev, phy_addr, 0x11, &value);
- if (ret > 0)
- goto error;
- mdelay(10);
- if ((value & 0xf) == 0xf) {
- printf("DPMAC %d :PHY is ..... Configured\n",
- dpmac);
- return;
- }
- }
- }
-error:
- printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
- return;
-}
-
-static const char *ls2080a_qds_mdio_name_for_muxval(u8 muxval)
-{
- return mdio_names[muxval];
-}
-
-struct mii_dev *mii_dev_for_muxval(u8 muxval)
-{
- struct mii_dev *bus;
- const char *name = ls2080a_qds_mdio_name_for_muxval(muxval);
-
- if (!name) {
- printf("No bus for muxval %x\n", muxval);
- return NULL;
- }
-
- bus = miiphy_get_dev_by_name(name);
-
- if (!bus) {
- printf("No bus by name %s\n", name);
- return NULL;
- }
-
- return bus;
-}
-
-static void ls2080a_qds_enable_SFP_TX(u8 muxval)
-{
- u8 brdcfg9;
-
- brdcfg9 = QIXIS_READ(brdcfg[9]);
- brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
- brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
- QIXIS_WRITE(brdcfg[9], brdcfg9);
-}
-
-static void ls2080a_qds_mux_mdio(u8 muxval)
-{
- u8 brdcfg4;
-
- if (muxval <= 5) {
- brdcfg4 = QIXIS_READ(brdcfg[4]);
- brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
- brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
- QIXIS_WRITE(brdcfg[4], brdcfg4);
- }
-}
-
-static int ls2080a_qds_mdio_read(struct mii_dev *bus, int addr,
- int devad, int regnum)
-{
- struct ls2080a_qds_mdio *priv = bus->priv;
-
- ls2080a_qds_mux_mdio(priv->muxval);
-
- return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int ls2080a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
- int regnum, u16 value)
-{
- struct ls2080a_qds_mdio *priv = bus->priv;
-
- ls2080a_qds_mux_mdio(priv->muxval);
-
- return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
-}
-
-static int ls2080a_qds_mdio_reset(struct mii_dev *bus)
-{
- struct ls2080a_qds_mdio *priv = bus->priv;
-
- return priv->realbus->reset(priv->realbus);
-}
-
-static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval)
-{
- struct ls2080a_qds_mdio *pmdio;
- struct mii_dev *bus = mdio_alloc();
-
- if (!bus) {
- printf("Failed to allocate ls2080a_qds MDIO bus\n");
- return -1;
- }
-
- pmdio = malloc(sizeof(*pmdio));
- if (!pmdio) {
- printf("Failed to allocate ls2080a_qds private data\n");
- free(bus);
- return -1;
- }
-
- bus->read = ls2080a_qds_mdio_read;
- bus->write = ls2080a_qds_mdio_write;
- bus->reset = ls2080a_qds_mdio_reset;
- strcpy(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval));
-
- pmdio->realbus = miiphy_get_dev_by_name(realbusname);
-
- if (!pmdio->realbus) {
- printf("No bus with name %s\n", realbusname);
- free(bus);
- free(pmdio);
- return -1;
- }
-
- pmdio->muxval = muxval;
- bus->priv = pmdio;
-
- return mdio_register(bus);
-}
-
-/*
- * Initialize the dpmac_info array.
- *
- */
-static void initialize_dpmac_to_slot(void)
-{
- struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
- int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
- FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
- >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
- int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
- FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
- >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
-
- char *env_hwconfig;
- env_hwconfig = env_get("hwconfig");
-
- switch (serdes1_prtcl) {
- case 0x07:
- case 0x09:
- case 0x33:
- printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
- serdes1_prtcl);
- lane_to_slot_fsm1[0] = EMI1_SLOT1;
- lane_to_slot_fsm1[1] = EMI1_SLOT1;
- lane_to_slot_fsm1[2] = EMI1_SLOT1;
- lane_to_slot_fsm1[3] = EMI1_SLOT1;
- if (hwconfig_f("xqsgmii", env_hwconfig)) {
- lane_to_slot_fsm1[4] = EMI1_SLOT1;
- lane_to_slot_fsm1[5] = EMI1_SLOT1;
- lane_to_slot_fsm1[6] = EMI1_SLOT1;
- lane_to_slot_fsm1[7] = EMI1_SLOT1;
- } else {
- lane_to_slot_fsm1[4] = EMI1_SLOT2;
- lane_to_slot_fsm1[5] = EMI1_SLOT2;
- lane_to_slot_fsm1[6] = EMI1_SLOT2;
- lane_to_slot_fsm1[7] = EMI1_SLOT2;
- }
- break;
-
- case 0x39:
- printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
- serdes1_prtcl);
- if (hwconfig_f("xqsgmii", env_hwconfig)) {
- lane_to_slot_fsm1[0] = EMI1_SLOT3;
- lane_to_slot_fsm1[1] = EMI1_SLOT3;
- lane_to_slot_fsm1[2] = EMI1_SLOT3;
- lane_to_slot_fsm1[3] = EMI_NONE;
- } else {
- lane_to_slot_fsm1[0] = EMI_NONE;
- lane_to_slot_fsm1[1] = EMI_NONE;
- lane_to_slot_fsm1[2] = EMI_NONE;
- lane_to_slot_fsm1[3] = EMI_NONE;
- }
- lane_to_slot_fsm1[4] = EMI1_SLOT3;
- lane_to_slot_fsm1[5] = EMI1_SLOT3;
- lane_to_slot_fsm1[6] = EMI1_SLOT3;
- lane_to_slot_fsm1[7] = EMI_NONE;
- break;
-
- case 0x4D:
- printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
- serdes1_prtcl);
- if (hwconfig_f("xqsgmii", env_hwconfig)) {
- lane_to_slot_fsm1[0] = EMI1_SLOT3;
- lane_to_slot_fsm1[1] = EMI1_SLOT3;
- lane_to_slot_fsm1[2] = EMI_NONE;
- lane_to_slot_fsm1[3] = EMI_NONE;
- } else {
- lane_to_slot_fsm1[0] = EMI_NONE;
- lane_to_slot_fsm1[1] = EMI_NONE;
- lane_to_slot_fsm1[2] = EMI_NONE;
- lane_to_slot_fsm1[3] = EMI_NONE;
- }
- lane_to_slot_fsm1[4] = EMI1_SLOT3;
- lane_to_slot_fsm1[5] = EMI1_SLOT3;
- lane_to_slot_fsm1[6] = EMI_NONE;
- lane_to_slot_fsm1[7] = EMI_NONE;
- break;
-
- case 0x2A:
- case 0x4B:
- case 0x4C:
- printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
- serdes1_prtcl);
- break;
- default:
- printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
- __func__, serdes1_prtcl);
- break;
- }
-
- switch (serdes2_prtcl) {
- case 0x07:
- case 0x08:
- case 0x09:
- case 0x49:
- printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
- serdes2_prtcl);
- lane_to_slot_fsm2[0] = EMI1_SLOT4;
- lane_to_slot_fsm2[1] = EMI1_SLOT4;
- lane_to_slot_fsm2[2] = EMI1_SLOT4;
- lane_to_slot_fsm2[3] = EMI1_SLOT4;
-
- if (hwconfig_f("xqsgmii", env_hwconfig)) {
- lane_to_slot_fsm2[4] = EMI1_SLOT4;
- lane_to_slot_fsm2[5] = EMI1_SLOT4;
- lane_to_slot_fsm2[6] = EMI1_SLOT4;
- lane_to_slot_fsm2[7] = EMI1_SLOT4;
- } else {
- /* No MDIO physical connection */
- lane_to_slot_fsm2[4] = EMI1_SLOT6;
- lane_to_slot_fsm2[5] = EMI1_SLOT6;
- lane_to_slot_fsm2[6] = EMI1_SLOT6;
- lane_to_slot_fsm2[7] = EMI1_SLOT6;
- }
- break;
-
- case 0x47:
- printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
- serdes2_prtcl);
- lane_to_slot_fsm2[0] = EMI_NONE;
- lane_to_slot_fsm2[1] = EMI1_SLOT5;
- lane_to_slot_fsm2[2] = EMI1_SLOT5;
- lane_to_slot_fsm2[3] = EMI1_SLOT5;
-
- if (hwconfig_f("xqsgmii", env_hwconfig)) {
- lane_to_slot_fsm2[4] = EMI_NONE;
- lane_to_slot_fsm2[5] = EMI1_SLOT5;
- lane_to_slot_fsm2[6] = EMI1_SLOT5;
- lane_to_slot_fsm2[7] = EMI1_SLOT5;
- }
- break;
-
- case 0x57:
- printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
- serdes2_prtcl);
- if (hwconfig_f("xqsgmii", env_hwconfig)) {
- lane_to_slot_fsm2[0] = EMI_NONE;
- lane_to_slot_fsm2[1] = EMI_NONE;
- lane_to_slot_fsm2[2] = EMI_NONE;
- lane_to_slot_fsm2[3] = EMI_NONE;
- }
- lane_to_slot_fsm2[4] = EMI_NONE;
- lane_to_slot_fsm2[5] = EMI_NONE;
- lane_to_slot_fsm2[6] = EMI1_SLOT5;
- lane_to_slot_fsm2[7] = EMI1_SLOT5;
- break;
-
- default:
- printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
- __func__ , serdes2_prtcl);
- break;
- }
-}
-
-void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
-{
- int lane, slot;
- struct mii_dev *bus;
- struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
- int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
- FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
- >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
- int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
- FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
- >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
-
- int *riser_phy_addr;
- char *env_hwconfig = env_get("hwconfig");
-
- if (hwconfig_f("xqsgmii", env_hwconfig))
- riser_phy_addr = &xqsgii_riser_phy_addr[0];
- else
- riser_phy_addr = &sgmii_riser_phy_addr[0];
-
- if (dpmac_id > WRIOP1_DPMAC9)
- goto serdes2;
-
- switch (serdes1_prtcl) {
- case 0x07:
- case 0x39:
- case 0x4D:
- lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id - 1);
-
- slot = lane_to_slot_fsm1[lane];
-
- switch (++slot) {
- case 1:
- /* Slot housing a SGMII riser card? */
- wriop_set_phy_address(dpmac_id, 0,
- riser_phy_addr[dpmac_id - 1]);
- dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
- bus = mii_dev_for_muxval(EMI1_SLOT1);
- wriop_set_mdio(dpmac_id, bus);
- break;
- case 2:
- /* Slot housing a SGMII riser card? */
- wriop_set_phy_address(dpmac_id, 0,
- riser_phy_addr[dpmac_id - 1]);
- dpmac_info[dpmac_id].board_mux = EMI1_SLOT2;
- bus = mii_dev_for_muxval(EMI1_SLOT2);
- wriop_set_mdio(dpmac_id, bus);
- break;
- case 3:
- if (slot == EMI_NONE)
- return;
- if (serdes1_prtcl == 0x39) {
- wriop_set_phy_address(dpmac_id, 0,
- riser_phy_addr[dpmac_id - 2]);
- if (dpmac_id >= 6 && hwconfig_f("xqsgmii",
- env_hwconfig))
- wriop_set_phy_address(dpmac_id, 0,
- riser_phy_addr[dpmac_id - 3]);
- } else {
- wriop_set_phy_address(dpmac_id, 0,
- riser_phy_addr[dpmac_id - 2]);
- if (dpmac_id >= 7 && hwconfig_f("xqsgmii",
- env_hwconfig))
- wriop_set_phy_address(dpmac_id, 0,
- riser_phy_addr[dpmac_id - 3]);
- }
- dpmac_info[dpmac_id].board_mux = EMI1_SLOT3;
- bus = mii_dev_for_muxval(EMI1_SLOT3);
- wriop_set_mdio(dpmac_id, bus);
- break;
- case 4:
- break;
- case 5:
- break;
- case 6:
- break;
- }
- break;
- default:
- printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
- __func__ , serdes1_prtcl);
- break;
- }
-
-serdes2:
- switch (serdes2_prtcl) {
- case 0x07:
- case 0x08:
- case 0x49:
- case 0x47:
- case 0x57:
- lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 +
- (dpmac_id - 9));
- slot = lane_to_slot_fsm2[lane];
-
- switch (++slot) {
- case 1:
- break;
- case 3:
- break;
- case 4:
- /* Slot housing a SGMII riser card? */
- wriop_set_phy_address(dpmac_id, 0,
- riser_phy_addr[dpmac_id - 9]);
- dpmac_info[dpmac_id].board_mux = EMI1_SLOT4;
- bus = mii_dev_for_muxval(EMI1_SLOT4);
- wriop_set_mdio(dpmac_id, bus);
- break;
- case 5:
- if (slot == EMI_NONE)
- return;
- if (serdes2_prtcl == 0x47) {
- wriop_set_phy_address(dpmac_id, 0,
- riser_phy_addr[dpmac_id - 10]);
- if (dpmac_id >= 14 && hwconfig_f("xqsgmii",
- env_hwconfig))
- wriop_set_phy_address(dpmac_id, 0,
- riser_phy_addr[dpmac_id - 11]);
- } else {
- wriop_set_phy_address(dpmac_id, 0,
- riser_phy_addr[dpmac_id - 11]);
- }
- dpmac_info[dpmac_id].board_mux = EMI1_SLOT5;
- bus = mii_dev_for_muxval(EMI1_SLOT5);
- wriop_set_mdio(dpmac_id, bus);
- break;
- case 6:
- /* Slot housing a SGMII riser card? */
- wriop_set_phy_address(dpmac_id, 0,
- riser_phy_addr[dpmac_id - 13]);
- dpmac_info[dpmac_id].board_mux = EMI1_SLOT6;
- bus = mii_dev_for_muxval(EMI1_SLOT6);
- wriop_set_mdio(dpmac_id, bus);
- break;
- }
- break;
- default:
- printf("%s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
- __func__, serdes2_prtcl);
- break;
- }
-}
-
-void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
-{
- int lane = 0, slot;
- struct mii_dev *bus;
- struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
- int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
- FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
- >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
-
- switch (serdes1_prtcl) {
- case 0x33:
- switch (dpmac_id) {
- case 1:
- case 2:
- case 3:
- case 4:
- lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_A);
- break;
- case 5:
- case 6:
- case 7:
- case 8:
- lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_B);
- break;
- case 9:
- case 10:
- case 11:
- case 12:
- lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_C);
- break;
- case 13:
- case 14:
- case 15:
- case 16:
- lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_D);
- break;
- }
-
- slot = lane_to_slot_fsm1[lane];
-
- switch (++slot) {
- case 1:
- /* Slot housing a QSGMII riser card? */
- wriop_set_phy_address(dpmac_id, 0, dpmac_id - 1);
- dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
- bus = mii_dev_for_muxval(EMI1_SLOT1);
- wriop_set_mdio(dpmac_id, bus);
- break;
- case 3:
- break;
- case 4:
- break;
- case 5:
- break;
- case 6:
- break;
- }
- break;
- default:
- printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
- serdes1_prtcl);
- break;
- }
-
- qsgmii_configure_repeater(dpmac_id);
-}
-
-void ls2080a_handle_phy_interface_xsgmii(int i)
-{
- struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
- int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
- FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
- >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
-
- switch (serdes1_prtcl) {
- case 0x2A:
- case 0x4B:
- case 0x4C:
- /*
- * 10GBase-R does not need a PHY to work, but to avoid U-Boot
- * use default PHY address which is zero to a MAC when it found
- * a MAC has no PHY address, we give a PHY address to 10GBase-R
- * MAC, and should not use a real XAUI PHY address, since MDIO
- * can access it successfully, and then MDIO thinks the XAUI
- * card is used for the 10GBase-R MAC, which will cause error.
- */
- wriop_set_phy_address(i, 0, i + 4);
- ls2080a_qds_enable_SFP_TX(SFP_TX);
-
- break;
- default:
- printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
- serdes1_prtcl);
- break;
- }
-}
-#endif
-#endif // !CONFIG_DM_ETH
-
-int board_eth_init(struct bd_info *bis)
-{
-#ifndef CONFIG_DM_ETH
-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
- struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
- int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
- FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
- >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
- int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
- FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
- >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
-
- struct memac_mdio_info *memac_mdio0_info;
- struct memac_mdio_info *memac_mdio1_info;
- unsigned int i;
- char *env_hwconfig;
- int error;
-
- env_hwconfig = env_get("hwconfig");
-
- initialize_dpmac_to_slot();
-
- memac_mdio0_info = (struct memac_mdio_info *)malloc(
- sizeof(struct memac_mdio_info));
- memac_mdio0_info->regs =
- (struct memac_mdio_controller *)
- CFG_SYS_FSL_WRIOP1_MDIO1;
- memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
-
- /* Register the real MDIO1 bus */
- fm_memac_mdio_init(bis, memac_mdio0_info);
-
- memac_mdio1_info = (struct memac_mdio_info *)malloc(
- sizeof(struct memac_mdio_info));
- memac_mdio1_info->regs =
- (struct memac_mdio_controller *)
- CFG_SYS_FSL_WRIOP1_MDIO2;
- memac_mdio1_info->name = DEFAULT_WRIOP_MDIO2_NAME;
-
- /* Register the real MDIO2 bus */
- fm_memac_mdio_init(bis, memac_mdio1_info);
-
- /* Register the muxing front-ends to the MDIO buses */
- ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
- ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
- ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
- ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
- ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
- ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
-
- ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
-
- for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
- switch (wriop_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_QSGMII:
- ls2080a_handle_phy_interface_qsgmii(i);
- break;
- case PHY_INTERFACE_MODE_SGMII:
- ls2080a_handle_phy_interface_sgmii(i);
- break;
- case PHY_INTERFACE_MODE_XGMII:
- ls2080a_handle_phy_interface_xsgmii(i);
- break;
- default:
- break;
-
- if (i == 16)
- i = NUM_WRIOP_PORTS;
- }
- }
-
- error = cpu_eth_init(bis);
-
- if (hwconfig_f("xqsgmii", env_hwconfig)) {
- if (serdes1_prtcl == 0x7)
- sgmii_configure_repeater(1);
- if (serdes2_prtcl == 0x7 || serdes2_prtcl == 0x8 ||
- serdes2_prtcl == 0x49)
- sgmii_configure_repeater(2);
- }
-#endif
-#endif // !CONFIG_DM_ETH
-
-#ifdef CONFIG_DM_ETH
- return 0;
-#else
- return pci_eth_init(bis);
-#endif
-}
-
#if defined(CONFIG_RESET_PHY_R)
void reset_phy(void)
{
@@ -991,10 +16,10 @@
}
#endif /* CONFIG_RESET_PHY_R */
-#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
+#if defined(CONFIG_MULTI_DTB_FIT)
-/* Structure to hold SERDES protocols supported in case of
- * CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
+/* Structure to hold SERDES protocols supported (network interfaces are
+ * described in the DTS).
*
* @serdes_block: the index of the SERDES block
* @serdes_protocol: the decimal value of the protocol supported
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index 91db618..ab5ff6f 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -227,7 +227,7 @@
ppa_init();
#endif
-#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
+#if !defined(CONFIG_SYS_EARLY_PCI_INIT)
pci_init();
#endif
diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c
index 7034bc6..44d9782 100644
--- a/board/freescale/ls2080ardb/eth_ls2080rdb.c
+++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c
@@ -4,104 +4,13 @@
*
*/
-#include <common.h>
-#include <command.h>
-#include <net.h>
-#include <netdev.h>
-#include <malloc.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fm_eth.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
#include <exports.h>
-#include <asm/arch/fsl_serdes.h>
#include <fsl-mc/fsl_mc.h>
-#include <fsl-mc/ldpaa_wriop.h>
DECLARE_GLOBAL_DATA_PTR;
int board_eth_init(struct bd_info *bis)
{
-#ifndef CONFIG_DM_ETH
-#if defined(CONFIG_FSL_MC_ENET)
- int i, interface;
- struct memac_mdio_info mdio_info;
- struct mii_dev *dev;
- struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
- u32 srds_s1;
- struct memac_mdio_controller *reg;
-
- srds_s1 = in_le32(&gur->rcwsr[28]) &
- FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
- srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
-
- reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO1;
- mdio_info.regs = reg;
- mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
-
- /* Register the EMI 1 */
- fm_memac_mdio_init(bis, &mdio_info);
-
- reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO2;
- mdio_info.regs = reg;
- mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
-
- /* Register the EMI 2 */
- fm_memac_mdio_init(bis, &mdio_info);
-
- switch (srds_s1) {
- case 0x2A:
- wriop_set_phy_address(WRIOP1_DPMAC1, 0, CORTINA_PHY_ADDR1);
- wriop_set_phy_address(WRIOP1_DPMAC2, 0, CORTINA_PHY_ADDR2);
- wriop_set_phy_address(WRIOP1_DPMAC3, 0, CORTINA_PHY_ADDR3);
- wriop_set_phy_address(WRIOP1_DPMAC4, 0, CORTINA_PHY_ADDR4);
- wriop_set_phy_address(WRIOP1_DPMAC5, 0, AQ_PHY_ADDR1);
- wriop_set_phy_address(WRIOP1_DPMAC6, 0, AQ_PHY_ADDR2);
- wriop_set_phy_address(WRIOP1_DPMAC7, 0, AQ_PHY_ADDR3);
- wriop_set_phy_address(WRIOP1_DPMAC8, 0, AQ_PHY_ADDR4);
-
- break;
- case 0x4B:
- wriop_set_phy_address(WRIOP1_DPMAC1, 0, CORTINA_PHY_ADDR1);
- wriop_set_phy_address(WRIOP1_DPMAC2, 0, CORTINA_PHY_ADDR2);
- wriop_set_phy_address(WRIOP1_DPMAC3, 0, CORTINA_PHY_ADDR3);
- wriop_set_phy_address(WRIOP1_DPMAC4, 0, CORTINA_PHY_ADDR4);
-
- break;
- default:
- printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n",
- srds_s1);
- break;
- }
-
- for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) {
- interface = wriop_get_enet_if(i);
- switch (interface) {
- case PHY_INTERFACE_MODE_XGMII:
- dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
- wriop_set_mdio(i, dev);
- break;
- default:
- break;
- }
- }
-
- for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) {
- switch (wriop_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_XGMII:
- dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
- wriop_set_mdio(i, dev);
- break;
- default:
- break;
- }
- }
-
- cpu_eth_init(bis);
-#endif /* CONFIG_FSL_MC_ENET */
-#endif /* !CONFIG_DM_ETH */
#ifdef CONFIG_PHY_AQUANTIA
/*
@@ -116,11 +25,7 @@
gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
#endif
-#ifdef CONFIG_DM_ETH
return 0;
-#else
- return pci_eth_init(bis);
-#endif
}
#if defined(CONFIG_RESET_PHY_R)
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index aa2d65b..a7fc2b2 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -297,7 +297,7 @@
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
#endif
-#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
+#if !defined(CONFIG_SYS_EARLY_PCI_INIT)
pci_init();
#endif
diff --git a/board/freescale/lx2160a/eth_lx2160aqds.c b/board/freescale/lx2160a/eth_lx2160aqds.c
index 374d052..9939bb6 100644
--- a/board/freescale/lx2160a/eth_lx2160aqds.c
+++ b/board/freescale/lx2160a/eth_lx2160aqds.c
@@ -4,575 +4,15 @@
*
*/
-#include <common.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <hwconfig.h>
-#include <command.h>
-#include <log.h>
-#include <net.h>
-#include <netdev.h>
-#include <malloc.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fm_eth.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <exports.h>
-#include <asm/arch/fsl_serdes.h>
#include <fsl-mc/fsl_mc.h>
-#include <fsl-mc/ldpaa_wriop.h>
-#include <linux/libfdt.h>
-
-#include "../common/qixis.h"
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_DM_ETH
-#define EMI_NONE 0
-#define EMI1 1 /* Mdio Bus 1 */
-#define EMI2 2 /* Mdio Bus 2 */
-
-#if defined(CONFIG_FSL_MC_ENET)
-enum io_slot {
- IO_SLOT_NONE = 0,
- IO_SLOT_1,
- IO_SLOT_2,
- IO_SLOT_3,
- IO_SLOT_4,
- IO_SLOT_5,
- IO_SLOT_6,
- IO_SLOT_7,
- IO_SLOT_8,
- EMI1_RGMII1,
- EMI1_RGMII2,
- IO_SLOT_MAX
-};
-
-struct lx2160a_qds_mdio {
- enum io_slot ioslot : 4;
- u8 realbusnum : 4;
- struct mii_dev *realbus;
-};
-
-/* structure explaining the phy configuration on 8 lanes of a serdes*/
-struct serdes_phy_config {
- u8 serdes; /* serdes protocol */
- struct phy_config {
- u8 dpmacid;
- /* -1 terminated array */
- int phy_address[WRIOP_MAX_PHY_NUM + 1];
- u8 mdio_bus;
- enum io_slot ioslot;
- } phy_config[SRDS_MAX_LANES];
-};
-
-/* Table defining the phy configuration on 8 lanes of a serdes.
- * Various assumptions have been made while defining this table.
- * e.g. for serdes1 protocol 19 it is being assumed that X-M11-USXGMII
- * card is being used for dpmac 3-4. (X-M12-XFI could also have been used)
- * And also that this card is connected to IO Slot 1 (could have been connected
- * to any of the 8 IO slots (IO slot 1 - IO slot 8)).
- * similarly, it is also being assumed that MDIO 1 is selected on X-M7-40G card
- * used in serdes1 protocol 19 (could have selected MDIO 2)
- * To override these settings "dpmac" environment variable can be used after
- * defining "dpmac_override" in hwconfig environment variable.
- * This table has limited serdes protocol entries. It can be expanded as per
- * requirement.
- */
-static const struct serdes_phy_config serdes1_phy_config[] = {
- {3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
- EMI1, IO_SLOT_1},
- {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
- EMI1, IO_SLOT_1},
- {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
- EMI1, IO_SLOT_1},
- {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
- EMI1, IO_SLOT_1} } },
- {7, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
- EMI1, IO_SLOT_1},
- {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
- EMI1, IO_SLOT_1},
- {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
- EMI1, IO_SLOT_1},
- {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
- EMI1, IO_SLOT_1},
- {WRIOP1_DPMAC7, {SGMII_CARD_PORT1_PHY_ADDR, -1},
- EMI1, IO_SLOT_2},
- {WRIOP1_DPMAC8, {SGMII_CARD_PORT2_PHY_ADDR, -1},
- EMI1, IO_SLOT_2},
- {WRIOP1_DPMAC9, {SGMII_CARD_PORT3_PHY_ADDR, -1},
- EMI1, IO_SLOT_2},
- {WRIOP1_DPMAC10, {SGMII_CARD_PORT4_PHY_ADDR, -1},
- EMI1, IO_SLOT_2} } },
- {8, {} },
- {13, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
- EMI1, IO_SLOT_1},
- {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
- EMI1, IO_SLOT_2} } },
- {14, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
- EMI1, IO_SLOT_1} } },
- {15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
- EMI1, IO_SLOT_1},
- {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
- EMI1, IO_SLOT_1} } },
- {17, {{WRIOP1_DPMAC3, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
- EMI1, IO_SLOT_1},
- {WRIOP1_DPMAC4, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
- EMI1, IO_SLOT_1},
- {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
- EMI1, IO_SLOT_1},
- {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
- EMI1, IO_SLOT_1} } },
- {19, {{WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
- EMI1, IO_SLOT_2},
- {WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
- EMI1, IO_SLOT_1},
- {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
- EMI1, IO_SLOT_1},
- {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
- EMI1, IO_SLOT_6},
- {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
- EMI1, IO_SLOT_6} } },
- {20, {{WRIOP1_DPMAC1, {CORTINA_PHY_ADDR1, -1},
- EMI1, IO_SLOT_1},
- {WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
- EMI1, IO_SLOT_2} } }
-};
-
-static const struct serdes_phy_config serdes2_phy_config[] = {
- {2, {} },
- {3, {} },
- {5, {} },
- {11, {{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
- EMI1, IO_SLOT_7},
- {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
- EMI1, IO_SLOT_7},
- {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
- EMI1, IO_SLOT_7},
- {WRIOP1_DPMAC16, {SGMII_CARD_PORT2_PHY_ADDR, -1},
- EMI1, IO_SLOT_8},
- {WRIOP1_DPMAC13, {SGMII_CARD_PORT3_PHY_ADDR, -1},
- EMI1, IO_SLOT_8},
- {WRIOP1_DPMAC14, {SGMII_CARD_PORT4_PHY_ADDR, -1},
- EMI1, IO_SLOT_8} } },
-};
-
-static const struct serdes_phy_config serdes3_phy_config[] = {
- {2, {} },
- {3, {} }
-};
-
-static inline
-const struct phy_config *get_phy_config(u8 serdes,
- const struct serdes_phy_config *table,
- u8 table_size)
-{
- int i;
-
- for (i = 0; i < table_size; i++) {
- if (table[i].serdes == serdes)
- return table[i].phy_config;
- }
-
- return NULL;
-}
-
-/* BRDCFG4 controls EMI routing for the board.
- * Bits Function
- * 7-6 EMI Interface #1 Primary Routing (CFG_MUX1_EMI1) (1.8V):
- * EMI1 00= On-board PHY #1
- * 01= On-board PHY #2
- * 10= (reserved)
- * 11= Slots 1..8 multiplexer and translator.
- * 5-3 EMI Interface #1 Secondary Routing (CFG_MUX2_EMI1) (2.5V):
- * EMI1X 000= Slot #1
- * 001= Slot #2
- * 010= Slot #3
- * 011= Slot #4
- * 100= Slot #5
- * 101= Slot #6
- * 110= Slot #7
- * 111= Slot #8
- * 2-0 EMI Interface #2 Routing (CFG_MUX_EMI2):
- * EMI2 000= Slot #1 (secondary EMI)
- * 001= Slot #2 (secondary EMI)
- * 010= Slot #3 (secondary EMI)
- * 011= Slot #4 (secondary EMI)
- * 100= Slot #5 (secondary EMI)
- * 101= Slot #6 (secondary EMI)
- * 110= Slot #7 (secondary EMI)
- * 111= Slot #8 (secondary EMI)
- */
-static int lx2160a_qds_get_mdio_mux_val(u8 realbusnum, enum io_slot ioslot)
-{
- switch (realbusnum) {
- case EMI1:
- switch (ioslot) {
- case EMI1_RGMII1:
- return 0;
- case EMI1_RGMII2:
- return 0x40;
- default:
- return (((ioslot - 1) << BRDCFG4_EMI1SEL_SHIFT) | 0xC0);
- }
- break;
- case EMI2:
- return ((ioslot - 1) << BRDCFG4_EMI2SEL_SHIFT);
- default:
- return -1;
- }
-}
-
-static void lx2160a_qds_mux_mdio(struct lx2160a_qds_mdio *priv)
-{
- u8 brdcfg4, mux_val, reg;
-
- brdcfg4 = QIXIS_READ(brdcfg[4]);
- reg = brdcfg4;
- mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
-
- switch (priv->realbusnum) {
- case EMI1:
- brdcfg4 &= ~BRDCFG4_EMI1SEL_MASK;
- brdcfg4 |= mux_val;
- break;
- case EMI2:
- brdcfg4 &= ~BRDCFG4_EMI2SEL_MASK;
- brdcfg4 |= mux_val;
- break;
- }
-
- if (brdcfg4 ^ reg)
- QIXIS_WRITE(brdcfg[4], brdcfg4);
-}
-
-static int lx2160a_qds_mdio_read(struct mii_dev *bus, int addr,
- int devad, int regnum)
-{
- struct lx2160a_qds_mdio *priv = bus->priv;
-
- lx2160a_qds_mux_mdio(priv);
-
- return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int lx2160a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
- int regnum, u16 value)
-{
- struct lx2160a_qds_mdio *priv = bus->priv;
-
- lx2160a_qds_mux_mdio(priv);
-
- return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
-}
-
-static int lx2160a_qds_mdio_reset(struct mii_dev *bus)
-{
- struct lx2160a_qds_mdio *priv = bus->priv;
-
- return priv->realbus->reset(priv->realbus);
-}
-
-static struct mii_dev *lx2160a_qds_mdio_init(u8 realbusnum, enum io_slot ioslot)
-{
- struct lx2160a_qds_mdio *pmdio;
- struct mii_dev *bus;
- /*should be within MDIO_NAME_LEN*/
- char dummy_mdio_name[] = "LX2160A_QDS_MDIO1_IOSLOT1";
-
- if (realbusnum == EMI2) {
- if (ioslot < IO_SLOT_1 || ioslot > IO_SLOT_8) {
- printf("invalid ioslot %d\n", ioslot);
- return NULL;
- }
- } else if (realbusnum == EMI1) {
- if (ioslot < IO_SLOT_1 || ioslot > EMI1_RGMII2) {
- printf("invalid ioslot %d\n", ioslot);
- return NULL;
- }
- } else {
- printf("not supported real mdio bus %d\n", realbusnum);
- return NULL;
- }
-
- if (ioslot == EMI1_RGMII1)
- strcpy(dummy_mdio_name, "LX2160A_QDS_MDIO1_RGMII1");
- else if (ioslot == EMI1_RGMII2)
- strcpy(dummy_mdio_name, "LX2160A_QDS_MDIO1_RGMII2");
- else
- sprintf(dummy_mdio_name, "LX2160A_QDS_MDIO%d_IOSLOT%d",
- realbusnum, ioslot);
- bus = miiphy_get_dev_by_name(dummy_mdio_name);
-
- if (bus)
- return bus;
-
- bus = mdio_alloc();
- if (!bus) {
- printf("Failed to allocate %s bus\n", dummy_mdio_name);
- return NULL;
- }
-
- pmdio = malloc(sizeof(*pmdio));
- if (!pmdio) {
- printf("Failed to allocate %s private data\n", dummy_mdio_name);
- free(bus);
- return NULL;
- }
-
- switch (realbusnum) {
- case EMI1:
- pmdio->realbus =
- miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
- break;
- case EMI2:
- pmdio->realbus =
- miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
- break;
- }
-
- if (!pmdio->realbus) {
- printf("No real mdio bus num %d found\n", realbusnum);
- free(bus);
- free(pmdio);
- return NULL;
- }
-
- pmdio->realbusnum = realbusnum;
- pmdio->ioslot = ioslot;
- bus->read = lx2160a_qds_mdio_read;
- bus->write = lx2160a_qds_mdio_write;
- bus->reset = lx2160a_qds_mdio_reset;
- strcpy(bus->name, dummy_mdio_name);
- bus->priv = pmdio;
-
- if (!mdio_register(bus))
- return bus;
-
- printf("No bus with name %s\n", dummy_mdio_name);
- free(bus);
- free(pmdio);
- return NULL;
-}
-
-static inline void do_phy_config(const struct phy_config *phy_config)
-{
- struct mii_dev *bus;
- int i, phy_num, phy_address;
-
- for (i = 0; i < SRDS_MAX_LANES; i++) {
- if (!phy_config[i].dpmacid)
- continue;
-
- for (phy_num = 0;
- phy_num < ARRAY_SIZE(phy_config[i].phy_address);
- phy_num++) {
- phy_address = phy_config[i].phy_address[phy_num];
- if (phy_address == -1)
- break;
- wriop_set_phy_address(phy_config[i].dpmacid,
- phy_num, phy_address);
- }
- /*Register the muxing front-ends to the MDIO buses*/
- bus = lx2160a_qds_mdio_init(phy_config[i].mdio_bus,
- phy_config[i].ioslot);
- if (!bus)
- printf("could not get bus for mdio %d ioslot %d\n",
- phy_config[i].mdio_bus,
- phy_config[i].ioslot);
- else
- wriop_set_mdio(phy_config[i].dpmacid, bus);
- }
-}
-
-static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid,
- char *env_dpmac)
-{
- const char *ret;
- size_t len;
- u8 realbusnum, ioslot;
- struct mii_dev *bus;
- int phy_num;
- char *phystr = "phy00";
-
- /*search phy in dpmac arg*/
- for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
- sprintf(phystr, "phy%d", phy_num + 1);
- ret = hwconfig_subarg_f(arg_dpmacid, phystr, &len, env_dpmac);
- if (!ret) {
- /*look for phy instead of phy1*/
- if (!phy_num)
- ret = hwconfig_subarg_f(arg_dpmacid, "phy",
- &len, env_dpmac);
- if (!ret)
- continue;
- }
-
- if (len != 4 || strncmp(ret, "0x", 2))
- printf("invalid phy format in %s variable.\n"
- "specify phy%d for %s in hex format e.g. 0x12\n",
- env_dpmac, phy_num + 1, arg_dpmacid);
- else
- wriop_set_phy_address(dpmac, phy_num,
- hextoul(ret, NULL));
- }
-
- /*search mdio in dpmac arg*/
- ret = hwconfig_subarg_f(arg_dpmacid, "mdio", &len, env_dpmac);
- if (ret)
- realbusnum = *ret - '0';
- else
- realbusnum = EMI_NONE;
-
- if (realbusnum) {
- /*search io in dpmac arg*/
- ret = hwconfig_subarg_f(arg_dpmacid, "io", &len, env_dpmac);
- if (ret)
- ioslot = *ret - '0';
- else
- ioslot = IO_SLOT_NONE;
- /*Register the muxing front-ends to the MDIO buses*/
- bus = lx2160a_qds_mdio_init(realbusnum, ioslot);
- if (!bus)
- printf("could not get bus for mdio %d ioslot %d\n",
- realbusnum, ioslot);
- else
- wriop_set_mdio(dpmac, bus);
- }
-}
-
-#endif
-#endif /* !CONFIG_DM_ETH */
-
int board_eth_init(struct bd_info *bis)
{
-#ifndef CONFIG_DM_ETH
-#if defined(CONFIG_FSL_MC_ENET)
- struct memac_mdio_info mdio_info;
- struct memac_mdio_controller *regs;
- int i;
- const char *ret;
- char *env_dpmac;
- char dpmacid[] = "dpmac00", srds[] = "00_00_00";
- size_t len;
- struct mii_dev *bus;
- const struct phy_config *phy_config;
- struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
- u32 srds_s1, srds_s2, srds_s3;
-
- srds_s1 = in_le32(&gur->rcwsr[28]) &
- FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
- srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
-
- srds_s2 = in_le32(&gur->rcwsr[28]) &
- FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
- srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
-
- srds_s3 = in_le32(&gur->rcwsr[28]) &
- FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK;
- srds_s3 >>= FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT;
-
- sprintf(srds, "%d_%d_%d", srds_s1, srds_s2, srds_s3);
-
- regs = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO1;
- mdio_info.regs = regs;
- mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
-
- /*Register the EMI 1*/
- fm_memac_mdio_init(bis, &mdio_info);
-
- regs = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO2;
- mdio_info.regs = regs;
- mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
-
- /*Register the EMI 2*/
- fm_memac_mdio_init(bis, &mdio_info);
-
- /* "dpmac" environment variable can be used after
- * defining "dpmac_override" in hwconfig environment variable.
- */
- if (hwconfig("dpmac_override")) {
- env_dpmac = env_get("dpmac");
- if (env_dpmac) {
- ret = hwconfig_arg_f("srds", &len, env_dpmac);
- if (ret) {
- if (strncmp(ret, srds, strlen(srds))) {
- printf("SERDES configuration changed.\n"
- "previous: %.*s, current: %s.\n"
- "update dpmac variable.\n",
- (int)len, ret, srds);
- }
- } else {
- printf("SERDES configuration not found.\n"
- "Please add srds:%s in dpmac variable\n",
- srds);
- }
-
- for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
- /* Look for dpmac1 to dpmac24(current max) arg
- * in dpmac environment variable
- */
- sprintf(dpmacid, "dpmac%d", i);
- ret = hwconfig_arg_f(dpmacid, &len, env_dpmac);
- if (ret)
- do_dpmac_config(i, dpmacid, env_dpmac);
- }
- } else {
- printf("Warning: environment dpmac not found.\n"
- "DPAA network interfaces may not work\n");
- }
- } else {
- /*Look for phy config for serdes1 in phy config table*/
- phy_config = get_phy_config(srds_s1, serdes1_phy_config,
- ARRAY_SIZE(serdes1_phy_config));
- if (!phy_config) {
- printf("%s WRIOP: Unsupported SerDes1 Protocol %d\n",
- __func__, srds_s1);
- } else {
- do_phy_config(phy_config);
- }
- phy_config = get_phy_config(srds_s2, serdes2_phy_config,
- ARRAY_SIZE(serdes2_phy_config));
- if (!phy_config) {
- printf("%s WRIOP: Unsupported SerDes2 Protocol %d\n",
- __func__, srds_s2);
- } else {
- do_phy_config(phy_config);
- }
- phy_config = get_phy_config(srds_s3, serdes3_phy_config,
- ARRAY_SIZE(serdes3_phy_config));
- if (!phy_config) {
- printf("%s WRIOP: Unsupported SerDes3 Protocol %d\n",
- __func__, srds_s3);
- } else {
- do_phy_config(phy_config);
- }
- }
-
- if (wriop_get_enet_if(WRIOP1_DPMAC17) == PHY_INTERFACE_MODE_RGMII_ID) {
- wriop_set_phy_address(WRIOP1_DPMAC17, 0, RGMII_PHY_ADDR1);
- bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII1);
- if (!bus)
- printf("could not get bus for RGMII1\n");
- else
- wriop_set_mdio(WRIOP1_DPMAC17, bus);
- }
-
- if (wriop_get_enet_if(WRIOP1_DPMAC18) == PHY_INTERFACE_MODE_RGMII_ID) {
- wriop_set_phy_address(WRIOP1_DPMAC18, 0, RGMII_PHY_ADDR2);
- bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII2);
- if (!bus)
- printf("could not get bus for RGMII2\n");
- else
- wriop_set_mdio(WRIOP1_DPMAC18, bus);
- }
-
- cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
-#endif /* !CONFIG_DM_ETH */
-
#ifdef CONFIG_PHY_AQUANTIA
/*
* Export functions to be used by AQ firmware
@@ -586,11 +26,7 @@
gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
#endif
-#ifdef CONFIG_DM_ETH
return 0;
-#else
- return pci_eth_init(bis);
-#endif
}
#if defined(CONFIG_RESET_PHY_R)
@@ -602,265 +38,10 @@
}
#endif /* CONFIG_RESET_PHY_R */
-#ifndef CONFIG_DM_ETH
-#if defined(CONFIG_FSL_MC_ENET)
-int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)
-{
- int offset;
- int ret;
- char dpmac_str[] = "dpmacs@00";
- const char *phy_string;
-
- offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs");
-
- if (offset < 0)
- offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs");
-
- if (offset < 0) {
- printf("dpmacs node not found in device tree\n");
- return offset;
- }
-
- sprintf(dpmac_str, "dpmac@%x", dpmac_id);
- debug("dpmac_str = %s\n", dpmac_str);
-
- offset = fdt_subnode_offset(fdt, offset, dpmac_str);
- if (offset < 0) {
- printf("%s node not found in device tree\n", dpmac_str);
- return offset;
- }
-
- phy_string = fdt_getprop(fdt, offset, "phy-connection-type", NULL);
- if (is_backplane_mode(phy_string)) {
- /* Backplane KR mode: skip fixups */
- printf("Interface %d in backplane KR mode\n", dpmac_id);
- return 0;
- }
-
- ret = fdt_appendprop_cell(fdt, offset, "phy-handle", node_phandle);
- if (ret)
- printf("%d@%s %d\n", __LINE__, __func__, ret);
-
- phy_string = phy_string_for_interface(wriop_get_enet_if(dpmac_id));
- ret = fdt_setprop_string(fdt, offset, "phy-connection-type",
- phy_string);
- if (ret)
- printf("%d@%s %d\n", __LINE__, __func__, ret);
-
- return ret;
-}
-
-int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
-{
- char mdio_ioslot_str[] = "mdio@00";
- struct lx2160a_qds_mdio *priv;
- u64 reg;
- u32 phandle;
- int offset, mux_val;
-
- /*Test if the MDIO bus is real mdio bus or muxing front end ?*/
- if (strncmp(mii_dev->name, "LX2160A_QDS_MDIO",
- strlen("LX2160A_QDS_MDIO")))
- return -1;
-
- /*Get the real MDIO bus num and ioslot info from bus's priv data*/
- priv = mii_dev->priv;
-
- debug("real_bus_num = %d, ioslot = %d\n",
- priv->realbusnum, priv->ioslot);
-
- if (priv->realbusnum == EMI1)
- reg = CFG_SYS_FSL_WRIOP1_MDIO1;
- else
- reg = CFG_SYS_FSL_WRIOP1_MDIO2;
-
- offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg);
- if (offset < 0) {
- printf("mdio@%llx node not found in device tree\n", reg);
- return offset;
- }
-
- phandle = fdt_get_phandle(fdt, offset);
- phandle = cpu_to_fdt32(phandle);
- offset = fdt_node_offset_by_prop_value(fdt, -1, "mdio-parent-bus",
- &phandle, 4);
- if (offset < 0) {
- printf("mdio-mux-%d node not found in device tree\n",
- priv->realbusnum == EMI1 ? 1 : 2);
- return offset;
- }
-
- mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
- if (priv->realbusnum == EMI1)
- mux_val >>= BRDCFG4_EMI1SEL_SHIFT;
- else
- mux_val >>= BRDCFG4_EMI2SEL_SHIFT;
- sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val);
-
- offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str);
- if (offset < 0) {
- printf("%s node not found in device tree\n", mdio_ioslot_str);
- return offset;
- }
-
- return offset;
-}
-
-int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset,
- struct phy_device *phy_dev, int phandle)
-{
- char phy_node_name[] = "ethernet-phy@00";
- char phy_id_compatible_str[] = "ethernet-phy-id0000.0000,";
- int ret;
-
- sprintf(phy_node_name, "ethernet-phy@%x", phyaddr);
- debug("phy_node_name = %s\n", phy_node_name);
-
- *subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name);
- if (*subnodeoffset <= 0) {
- printf("Could not add subnode %s inside node %s err = %s\n",
- phy_node_name, fdt_get_name(fdt, offset, NULL),
- fdt_strerror(*subnodeoffset));
- return *subnodeoffset;
- }
-
- sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x,",
- phy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF);
- debug("phy_id_compatible_str %s\n", phy_id_compatible_str);
-
- ret = fdt_setprop_string(fdt, *subnodeoffset, "compatible",
- phy_id_compatible_str);
- if (ret) {
- printf("%d@%s %d\n", __LINE__, __func__, ret);
- goto out;
- }
-
- if (phy_dev->is_c45) {
- ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
- "ethernet-phy-ieee802.3-c45");
- if (ret) {
- printf("%d@%s %d\n", __LINE__, __func__, ret);
- goto out;
- }
- } else {
- ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
- "ethernet-phy-ieee802.3-c22");
- if (ret) {
- printf("%d@%s %d\n", __LINE__, __func__, ret);
- goto out;
- }
- }
-
- ret = fdt_setprop_cell(fdt, *subnodeoffset, "reg", phyaddr);
- if (ret) {
- printf("%d@%s %d\n", __LINE__, __func__, ret);
- goto out;
- }
-
- ret = fdt_set_phandle(fdt, *subnodeoffset, phandle);
- if (ret) {
- printf("%d@%s %d\n", __LINE__, __func__, ret);
- goto out;
- }
-
-out:
- if (ret)
- fdt_del_node(fdt, *subnodeoffset);
-
- return ret;
-}
-
-int fdt_fixup_board_phy(void *fdt)
-{
- int fpga_offset, offset, subnodeoffset;
- struct mii_dev *mii_dev;
- struct list_head *mii_devs, *entry;
- int ret, dpmac_id, i;
- struct phy_device *phy_dev;
- char ethname[ETH_NAME_LEN];
- phy_interface_t phy_iface;
- uint32_t phandle;
-
- ret = 0;
- /* we know FPGA is connected to i2c0, therefore search path directly,
- * instead of compatible property, as it saves time
- */
- fpga_offset = fdt_path_offset(fdt, "/soc/i2c@2000000/fpga");
-
- if (fpga_offset < 0)
- fpga_offset = fdt_path_offset(fdt, "/i2c@2000000/fpga");
-
- if (fpga_offset < 0) {
- printf("i2c@2000000/fpga node not found in device tree\n");
- return fpga_offset;
- }
-
- ret = fdt_generate_phandle(fdt, &phandle);
- if (ret < 0)
- return ret;
-
- mii_devs = mdio_get_list_head();
-
- list_for_each(entry, mii_devs) {
- mii_dev = list_entry(entry, struct mii_dev, link);
- debug("mii_dev name : %s\n", mii_dev->name);
- offset = fdt_get_ioslot_offset(fdt, mii_dev, fpga_offset);
- if (offset < 0)
- continue;
-
- // Look for phy devices attached to MDIO bus muxing front end
- // and create their entries with compatible being the device id
- for (i = 0; i < PHY_MAX_ADDR; i++) {
- phy_dev = mii_dev->phymap[i];
- if (!phy_dev)
- continue;
-
- // TODO: use sscanf instead of loop
- dpmac_id = WRIOP1_DPMAC1;
- while (dpmac_id < NUM_WRIOP_PORTS) {
- phy_iface = wriop_get_enet_if(dpmac_id);
- snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s",
- dpmac_id,
- phy_string_for_interface(phy_iface));
- if (strcmp(ethname, phy_dev->dev->name) == 0)
- break;
- dpmac_id++;
- }
- if (dpmac_id == NUM_WRIOP_PORTS)
- continue;
- ret = fdt_create_phy_node(fdt, offset, i,
- &subnodeoffset,
- phy_dev, phandle);
- if (ret)
- break;
-
- ret = fdt_fixup_dpmac_phy_handle(fdt,
- dpmac_id, phandle);
- if (ret) {
- fdt_del_node(fdt, subnodeoffset);
- break;
- }
- /* calculate offset again as new node addition may have
- * changed offset;
- */
- offset = fdt_get_ioslot_offset(fdt, mii_dev,
- fpga_offset);
- phandle++;
- }
-
- if (ret)
- break;
- }
-
- return ret;
-}
-#endif // CONFIG_FSL_MC_ENET
-#endif
-
-#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
+#if defined(CONFIG_MULTI_DTB_FIT)
-/* Structure to hold SERDES protocols supported in case of
- * CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
+/* Structure to hold SERDES protocols supported (network interfaces are
+ * described in the DTS).
*
* @serdes_block: the index of the SERDES block
* @serdes_protocol: the decimal value of the protocol supported
diff --git a/board/freescale/lx2160a/eth_lx2160ardb.c b/board/freescale/lx2160a/eth_lx2160ardb.c
index 8a9c60f..533f606 100644
--- a/board/freescale/lx2160a/eth_lx2160ardb.c
+++ b/board/freescale/lx2160a/eth_lx2160ardb.c
@@ -5,158 +5,14 @@
*/
#include <common.h>
-#include <command.h>
-#include <fdt_support.h>
-#include <net.h>
#include <netdev.h>
-#include <malloc.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fm_eth.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
#include <exports.h>
-#include <asm/arch/fsl_serdes.h>
#include <fsl-mc/fsl_mc.h>
-#include <fsl-mc/ldpaa_wriop.h>
-#include "lx2160a.h"
DECLARE_GLOBAL_DATA_PTR;
-static bool get_inphi_phy_id(struct mii_dev *bus, int addr, int devad)
-{
- int phy_reg;
- u32 phy_id;
-
- phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
- phy_id = (phy_reg & 0xffff) << 16;
-
- phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
- phy_id |= (phy_reg & 0xffff);
-
- if (phy_id == PHY_UID_IN112525_S03)
- return true;
- else
- return false;
-}
-
int board_eth_init(struct bd_info *bis)
{
-#if defined(CONFIG_FSL_MC_ENET)
- struct memac_mdio_info mdio_info;
- struct memac_mdio_controller *reg;
- int i, interface;
- struct mii_dev *dev;
- struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
- u32 srds_s1;
-
- srds_s1 = in_le32(&gur->rcwsr[28]) &
- FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
- srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
-
- reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO1;
- mdio_info.regs = reg;
- mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
-
- /* Register the EMI 1 */
- fm_memac_mdio_init(bis, &mdio_info);
-
- reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO2;
- mdio_info.regs = reg;
- mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
-
- /* Register the EMI 2 */
- fm_memac_mdio_init(bis, &mdio_info);
-
- dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
- switch (srds_s1) {
- case 19:
- wriop_set_phy_address(WRIOP1_DPMAC2, 0,
- CORTINA_PHY_ADDR1);
- wriop_set_phy_address(WRIOP1_DPMAC3, 0,
- AQR107_PHY_ADDR1);
- wriop_set_phy_address(WRIOP1_DPMAC4, 0,
- AQR107_PHY_ADDR2);
- if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
- wriop_set_phy_address(WRIOP1_DPMAC5, 0,
- INPHI_PHY_ADDR1);
- wriop_set_phy_address(WRIOP1_DPMAC6, 0,
- INPHI_PHY_ADDR1);
- }
- wriop_set_phy_address(WRIOP1_DPMAC17, 0,
- RGMII_PHY_ADDR1);
- wriop_set_phy_address(WRIOP1_DPMAC18, 0,
- RGMII_PHY_ADDR2);
- break;
-
- case 18:
- wriop_set_phy_address(WRIOP1_DPMAC7, 0,
- CORTINA_PHY_ADDR1);
- wriop_set_phy_address(WRIOP1_DPMAC8, 0,
- CORTINA_PHY_ADDR1);
- wriop_set_phy_address(WRIOP1_DPMAC9, 0,
- CORTINA_PHY_ADDR1);
- wriop_set_phy_address(WRIOP1_DPMAC10, 0,
- CORTINA_PHY_ADDR1);
- wriop_set_phy_address(WRIOP1_DPMAC3, 0,
- AQR107_PHY_ADDR1);
- wriop_set_phy_address(WRIOP1_DPMAC4, 0,
- AQR107_PHY_ADDR2);
- if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
- wriop_set_phy_address(WRIOP1_DPMAC5, 0,
- INPHI_PHY_ADDR1);
- wriop_set_phy_address(WRIOP1_DPMAC6, 0,
- INPHI_PHY_ADDR1);
- }
- wriop_set_phy_address(WRIOP1_DPMAC17, 0,
- RGMII_PHY_ADDR1);
- wriop_set_phy_address(WRIOP1_DPMAC18, 0,
- RGMII_PHY_ADDR2);
- break;
-
- default:
- printf("SerDes1 protocol 0x%x is not supported on LX2160ARDB\n",
- srds_s1);
- goto next;
- }
-
- for (i = WRIOP1_DPMAC2; i <= WRIOP1_DPMAC10; i++) {
- interface = wriop_get_enet_if(i);
- switch (interface) {
- case PHY_INTERFACE_MODE_XGMII:
- dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
- wriop_set_mdio(i, dev);
- break;
- case PHY_INTERFACE_MODE_25G_AUI:
- dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
- wriop_set_mdio(i, dev);
- break;
- case PHY_INTERFACE_MODE_XLAUI:
- dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
- wriop_set_mdio(i, dev);
- break;
- default:
- break;
- }
- }
- for (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC18; i++) {
- interface = wriop_get_enet_if(i);
- switch (interface) {
- case PHY_INTERFACE_MODE_RGMII:
- case PHY_INTERFACE_MODE_RGMII_ID:
- dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
- wriop_set_mdio(i, dev);
- break;
- default:
- break;
- }
- }
-
-next:
- cpu_eth_init(bis);
-#endif /* CONFIG_FSL_MC_ENET */
-
#ifdef CONFIG_PHY_AQUANTIA
/*
* Export functions to be used by AQ firmware
@@ -180,35 +36,3 @@
#endif
}
#endif /* CONFIG_RESET_PHY_R */
-
-int fdt_fixup_board_phy(void *fdt)
-{
- int mdio_offset;
- int ret;
- struct mii_dev *dev;
-
- ret = 0;
-
- dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
- if (!get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
- mdio_offset = fdt_path_offset(fdt, "/soc/mdio@0x8B97000");
-
- if (mdio_offset < 0)
- mdio_offset = fdt_path_offset(fdt, "/mdio@0x8B97000");
-
- if (mdio_offset < 0) {
- printf("mdio@0x8B9700 node not found in dts\n");
- return mdio_offset;
- }
-
- ret = fdt_setprop_string(fdt, mdio_offset, "status",
- "disabled");
- if (ret) {
- printf("Could not set disable mdio@0x8B97000 %s\n",
- fdt_strerror(ret));
- return ret;
- }
- }
-
- return ret;
-}
diff --git a/board/freescale/lx2160a/eth_lx2162aqds.c b/board/freescale/lx2160a/eth_lx2162aqds.c
index 25fee89..805aa70 100644
--- a/board/freescale/lx2160a/eth_lx2162aqds.c
+++ b/board/freescale/lx2160a/eth_lx2162aqds.c
@@ -4,584 +4,15 @@
*
*/
-#include <common.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <hwconfig.h>
-#include <command.h>
-#include <log.h>
-#include <net.h>
-#include <netdev.h>
-#include <malloc.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fm_eth.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <exports.h>
-#include <asm/global_data.h>
-#include <asm/arch/fsl_serdes.h>
#include <fsl-mc/fsl_mc.h>
-#include <fsl-mc/ldpaa_wriop.h>
-#include <linux/libfdt.h>
-
-#include "../common/qixis.h"
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_DM_ETH
-#define EMI_NONE 0
-#define EMI1 1 /* Mdio Bus 1 */
-#define EMI2 2 /* Mdio Bus 2 */
-
-#if defined(CONFIG_FSL_MC_ENET)
-enum io_slot {
- IO_SLOT_NONE = 0,
- IO_SLOT_1,
- IO_SLOT_2,
- IO_SLOT_3,
- IO_SLOT_4,
- IO_SLOT_5,
- IO_SLOT_6,
- IO_SLOT_7,
- IO_SLOT_8,
- EMI1_RGMII1,
- EMI1_RGMII2,
- IO_SLOT_MAX
-};
-
-struct lx2162a_qds_mdio {
- enum io_slot ioslot : 4;
- u8 realbusnum : 4;
- struct mii_dev *realbus;
-};
-
-/* structure explaining the phy configuration on 8 lanes of a serdes*/
-struct serdes_phy_config {
- u8 serdes; /* serdes protocol */
- struct phy_config {
- u8 dpmacid;
- /* -1 terminated array */
- int phy_address[WRIOP_MAX_PHY_NUM + 1];
- u8 mdio_bus;
- enum io_slot ioslot;
- } phy_config[SRDS_MAX_LANES];
-};
-
-/* Table defining the phy configuration on 8 lanes of a serdes.
- * Various assumptions have been made while defining this table.
- * e.g. for serdes1 protocol 19 it is being assumed that X-M11-USXGMII
- * card is being used for dpmac 3-4. (X-M12-XFI could also have been used)
- * And also that this card is connected to IO Slot 1 (could have been connected
- * to any of the 8 IO slots (IO slot 1 - IO slot 8)).
- * similarly, it is also being assumed that MDIO 1 is selected on X-M7-40G card
- * used in serdes1 protocol 19 (could have selected MDIO 2)
- * To override these settings "dpmac" environment variable can be used after
- * defining "dpmac_override" in hwconfig environment variable.
- * This table has limited serdes protocol entries. It can be expanded as per
- * requirement.
- */
-/*****************************************************************
- *| SERDES_1 PROTOCOL | IO_SLOT | CARD |
- ******************************************************************
- *| 2 | IO_SLOT_1 | M4-PCIE-SGMII |
- *| 3 | IO_SLOT_1 | M11-USXGMII |
- *| 15 | IO_SLOT_1 | M13-25G |
- *| 17 | IO_SLOT_1 | M13-25G |
- *| 18 | IO_SLOT_1 | M11-USXGMII |
- *| | IO_SLOT_6 | M13-25G |
- *| 20 | IO_SLOT_1 | M7-40G |
- *****************************************************************
- */
-static const struct serdes_phy_config serdes1_phy_config[] = {
- {1, {} },
- {2, {{WRIOP1_DPMAC3, {SGMII_CARD_PORT1_PHY_ADDR, -1},
- EMI1, IO_SLOT_1},
- {WRIOP1_DPMAC4, {SGMII_CARD_PORT2_PHY_ADDR, -1},
- EMI1, IO_SLOT_1},
- {WRIOP1_DPMAC5, {SGMII_CARD_PORT3_PHY_ADDR, -1},
- EMI1, IO_SLOT_1},
- {WRIOP1_DPMAC6, {SGMII_CARD_PORT4_PHY_ADDR, -1},
- EMI1, IO_SLOT_1} } },
- {3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
- EMI1, IO_SLOT_1},
- {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
- EMI1, IO_SLOT_1},
- {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
- EMI1, IO_SLOT_1},
- {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
- EMI1, IO_SLOT_1} } },
- {15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
- EMI1, IO_SLOT_1},
- {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
- EMI1, IO_SLOT_1} } },
- {17, {{WRIOP1_DPMAC3, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
- EMI1, IO_SLOT_1},
- {WRIOP1_DPMAC4, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
- EMI1, IO_SLOT_1},
- {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
- EMI1, IO_SLOT_1},
- {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
- EMI1, IO_SLOT_1} } },
- {18, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
- EMI1, IO_SLOT_1},
- {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
- EMI1, IO_SLOT_1},
- {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
- EMI1, IO_SLOT_6},
- {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
- EMI1, IO_SLOT_6} } },
- {20, {{WRIOP1_DPMAC1, {CORTINA_PHY_ADDR1, -1},
- EMI1, IO_SLOT_1} } }
-};
-
-/*****************************************************************
- *| SERDES_2 PROTOCOL | IO_SLOT | CARD |
- ******************************************************************
- *| 2 | IO_SLOT_7 | M4-PCIE-SGMII |
- *| | IO_SLOT_8 | M4-PCIE-SGMII |
- *| 3 | IO_SLOT_7 | M4-PCIE-SGMII |
- *| | IO_SLOT_8 | M4-PCIE-SGMII |
- *| 5 | IO_SLOT_7 | M4-PCIE-SGMII |
- *| 10 | IO_SLOT_7 | M4-PCIE-SGMII |
- *| | IO_SLOT_8 | M4-PCIE-SGMII |
- *| 11 | IO_SLOT_7 | M4-PCIE-SGMII |
- *| | IO_SLOT_8 | M4-PCIE-SGMII |
- *| 12 | IO_SLOT_7 | M4-PCIE-SGMII |
- *| | IO_SLOT_8 | M4-PCIE-SGMII |
- ******************************************************************
- */
-static const struct serdes_phy_config serdes2_phy_config[] = {
- {2, {} },
- {3, {} },
- {5, {} },
- {10, {{WRIOP1_DPMAC11, {SGMII_CARD_PORT1_PHY_ADDR, -1},
- EMI1, IO_SLOT_7},
- {WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
- EMI1, IO_SLOT_7},
- {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
- EMI1, IO_SLOT_7},
- {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
- EMI1, IO_SLOT_7} } },
- {11, {{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
- EMI1, IO_SLOT_7},
- {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
- EMI1, IO_SLOT_7},
- {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
- EMI1, IO_SLOT_7},
- {WRIOP1_DPMAC16, {SGMII_CARD_PORT2_PHY_ADDR, -1},
- EMI1, IO_SLOT_8},
- {WRIOP1_DPMAC13, {SGMII_CARD_PORT3_PHY_ADDR, -1},
- EMI1, IO_SLOT_8},
- {WRIOP1_DPMAC14, {SGMII_CARD_PORT4_PHY_ADDR, -1},
- EMI1, IO_SLOT_8} } },
- {12, {{WRIOP1_DPMAC11, {SGMII_CARD_PORT1_PHY_ADDR, -1},
- EMI1, IO_SLOT_7},
- {WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
- EMI1, IO_SLOT_7},
- {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
- EMI1, IO_SLOT_7},
- {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
- EMI1, IO_SLOT_7} } }
-};
-
-static inline
-const struct phy_config *get_phy_config(u8 serdes,
- const struct serdes_phy_config *table,
- u8 table_size)
-{
- int i;
-
- for (i = 0; i < table_size; i++) {
- if (table[i].serdes == serdes)
- return table[i].phy_config;
- }
-
- return NULL;
-}
-
-/* BRDCFG4 controls EMI routing for the board.
- * Bits Function
- * 7-6 EMI Interface #1 Primary Routing (CFG_MUX1_EMI1) (1.8V):
- * EMI1 00= On-board PHY #1
- * 01= On-board PHY #2
- * 10= (reserved)
- * 11= Slots 1..8 multiplexer and translator.
- * 5-3 EMI Interface #1 Secondary Routing (CFG_MUX2_EMI1) (2.5V):
- * EMI1X 000= Slot #1
- * 001= Slot #2
- * 010= Slot #3
- * 011= Slot #4
- * 100= Slot #5
- * 101= Slot #6
- * 110= Slot #7
- * 111= Slot #8
- * 2-0 EMI Interface #2 Routing (CFG_MUX_EMI2):
- * EMI2 000= Slot #1 (secondary EMI)
- * 001= Slot #2 (secondary EMI)
- * 010= Slot #3 (secondary EMI)
- * 011= Slot #4 (secondary EMI)
- * 100= Slot #5 (secondary EMI)
- * 101= Slot #6 (secondary EMI)
- * 110= Slot #7 (secondary EMI)
- * 111= Slot #8 (secondary EMI)
- */
-static int lx2162a_qds_get_mdio_mux_val(u8 realbusnum, enum io_slot ioslot)
-{
- switch (realbusnum) {
- case EMI1:
- switch (ioslot) {
- case EMI1_RGMII1:
- return 0;
- case EMI1_RGMII2:
- return 0x40;
- default:
- return (((ioslot - 1) << BRDCFG4_EMI1SEL_SHIFT) | 0xC0);
- }
- break;
- case EMI2:
- return ((ioslot - 1) << BRDCFG4_EMI2SEL_SHIFT);
- default:
- return -1;
- }
-}
-
-static void lx2162a_qds_mux_mdio(struct lx2162a_qds_mdio *priv)
-{
- u8 brdcfg4, mux_val, reg;
-
- brdcfg4 = QIXIS_READ(brdcfg[4]);
- reg = brdcfg4;
- mux_val = lx2162a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
-
- switch (priv->realbusnum) {
- case EMI1:
- brdcfg4 &= ~BRDCFG4_EMI1SEL_MASK;
- brdcfg4 |= mux_val;
- break;
- case EMI2:
- brdcfg4 &= ~BRDCFG4_EMI2SEL_MASK;
- brdcfg4 |= mux_val;
- break;
- }
-
- if (brdcfg4 ^ reg)
- QIXIS_WRITE(brdcfg[4], brdcfg4);
-}
-
-static int lx2162a_qds_mdio_read(struct mii_dev *bus, int addr,
- int devad, int regnum)
-{
- struct lx2162a_qds_mdio *priv = bus->priv;
-
- lx2162a_qds_mux_mdio(priv);
-
- return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int lx2162a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
- int regnum, u16 value)
-{
- struct lx2162a_qds_mdio *priv = bus->priv;
-
- lx2162a_qds_mux_mdio(priv);
-
- return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
-}
-
-static int lx2162a_qds_mdio_reset(struct mii_dev *bus)
-{
- struct lx2162a_qds_mdio *priv = bus->priv;
-
- return priv->realbus->reset(priv->realbus);
-}
-
-static struct mii_dev *lx2162a_qds_mdio_init(u8 realbusnum, enum io_slot ioslot)
-{
- struct lx2162a_qds_mdio *pmdio;
- struct mii_dev *bus;
- /*should be within MDIO_NAME_LEN*/
- char dummy_mdio_name[] = "LX2162A_QDS_MDIO1_IOSLOT1";
-
- if (realbusnum == EMI2) {
- if (ioslot < IO_SLOT_1 || ioslot > IO_SLOT_8) {
- printf("invalid ioslot %d\n", ioslot);
- return NULL;
- }
- } else if (realbusnum == EMI1) {
- if (ioslot < IO_SLOT_1 || ioslot > EMI1_RGMII2) {
- printf("invalid ioslot %d\n", ioslot);
- return NULL;
- }
- } else {
- printf("not supported real mdio bus %d\n", realbusnum);
- return NULL;
- }
-
- if (ioslot == EMI1_RGMII1)
- strcpy(dummy_mdio_name, "LX2162A_QDS_MDIO1_RGMII1");
- else if (ioslot == EMI1_RGMII2)
- strcpy(dummy_mdio_name, "LX2162A_QDS_MDIO1_RGMII2");
- else
- sprintf(dummy_mdio_name, "LX2162A_QDS_MDIO%d_IOSLOT%d",
- realbusnum, ioslot);
- bus = miiphy_get_dev_by_name(dummy_mdio_name);
-
- if (bus)
- return bus;
-
- bus = mdio_alloc();
- if (!bus) {
- printf("Failed to allocate %s bus\n", dummy_mdio_name);
- return NULL;
- }
-
- pmdio = malloc(sizeof(*pmdio));
- if (!pmdio) {
- printf("Failed to allocate %s private data\n", dummy_mdio_name);
- free(bus);
- return NULL;
- }
-
- switch (realbusnum) {
- case EMI1:
- pmdio->realbus =
- miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
- break;
- case EMI2:
- pmdio->realbus =
- miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
- break;
- }
-
- if (!pmdio->realbus) {
- printf("No real mdio bus num %d found\n", realbusnum);
- free(bus);
- free(pmdio);
- return NULL;
- }
-
- pmdio->realbusnum = realbusnum;
- pmdio->ioslot = ioslot;
- bus->read = lx2162a_qds_mdio_read;
- bus->write = lx2162a_qds_mdio_write;
- bus->reset = lx2162a_qds_mdio_reset;
- strcpy(bus->name, dummy_mdio_name);
- bus->priv = pmdio;
-
- if (!mdio_register(bus))
- return bus;
-
- printf("No bus with name %s\n", dummy_mdio_name);
- free(bus);
- free(pmdio);
- return NULL;
-}
-
-static inline void do_phy_config(const struct phy_config *phy_config)
-{
- struct mii_dev *bus;
- int i, phy_num, phy_address;
-
- for (i = 0; i < SRDS_MAX_LANES; i++) {
- if (!phy_config[i].dpmacid)
- continue;
-
- for (phy_num = 0;
- phy_num < ARRAY_SIZE(phy_config[i].phy_address);
- phy_num++) {
- phy_address = phy_config[i].phy_address[phy_num];
- if (phy_address == -1)
- break;
- wriop_set_phy_address(phy_config[i].dpmacid,
- phy_num, phy_address);
- }
- /*Register the muxing front-ends to the MDIO buses*/
- bus = lx2162a_qds_mdio_init(phy_config[i].mdio_bus,
- phy_config[i].ioslot);
- if (!bus)
- printf("could not get bus for mdio %d ioslot %d\n",
- phy_config[i].mdio_bus,
- phy_config[i].ioslot);
- else
- wriop_set_mdio(phy_config[i].dpmacid, bus);
- }
-}
-
-static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid,
- char *env_dpmac)
-{
- const char *ret;
- size_t len;
- u8 realbusnum, ioslot;
- struct mii_dev *bus;
- int phy_num;
- char *phystr = "phy00";
-
- /*search phy in dpmac arg*/
- for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
- sprintf(phystr, "phy%d", phy_num + 1);
- ret = hwconfig_subarg_f(arg_dpmacid, phystr, &len, env_dpmac);
- if (!ret) {
- /*look for phy instead of phy1*/
- if (!phy_num)
- ret = hwconfig_subarg_f(arg_dpmacid, "phy",
- &len, env_dpmac);
- if (!ret)
- continue;
- }
-
- if (len != 4 || strncmp(ret, "0x", 2))
- printf("invalid phy format in %s variable.\n"
- "specify phy%d for %s in hex format e.g. 0x12\n",
- env_dpmac, phy_num + 1, arg_dpmacid);
- else
- wriop_set_phy_address(dpmac, phy_num,
- hextoul(ret, NULL));
- }
-
- /*search mdio in dpmac arg*/
- ret = hwconfig_subarg_f(arg_dpmacid, "mdio", &len, env_dpmac);
- if (ret)
- realbusnum = *ret - '0';
- else
- realbusnum = EMI_NONE;
-
- if (realbusnum) {
- /*search io in dpmac arg*/
- ret = hwconfig_subarg_f(arg_dpmacid, "io", &len, env_dpmac);
- if (ret)
- ioslot = *ret - '0';
- else
- ioslot = IO_SLOT_NONE;
- /*Register the muxing front-ends to the MDIO buses*/
- bus = lx2162a_qds_mdio_init(realbusnum, ioslot);
- if (!bus)
- printf("could not get bus for mdio %d ioslot %d\n",
- realbusnum, ioslot);
- else
- wriop_set_mdio(dpmac, bus);
- }
-}
-
-#endif
-#endif /* !CONFIG_DM_ETH */
-
int board_eth_init(struct bd_info *bis)
{
-#ifndef CONFIG_DM_ETH
-#if defined(CONFIG_FSL_MC_ENET)
- struct memac_mdio_info mdio_info;
- struct memac_mdio_controller *regs;
- int i;
- const char *ret;
- char *env_dpmac;
- char dpmacid[] = "dpmac00", srds[] = "00_00_00";
- size_t len;
- struct mii_dev *bus;
- const struct phy_config *phy_config;
- struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
- u32 srds_s1, srds_s2;
-
- srds_s1 = in_le32(&gur->rcwsr[28]) &
- FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
- srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
-
- srds_s2 = in_le32(&gur->rcwsr[28]) &
- FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
- srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
-
- sprintf(srds, "%d_%d", srds_s1, srds_s2);
-
- regs = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO1;
- mdio_info.regs = regs;
- mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
-
- /*Register the EMI 1*/
- fm_memac_mdio_init(bis, &mdio_info);
-
- regs = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO2;
- mdio_info.regs = regs;
- mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
-
- /*Register the EMI 2*/
- fm_memac_mdio_init(bis, &mdio_info);
-
- /* "dpmac" environment variable can be used after
- * defining "dpmac_override" in hwconfig environment variable.
- */
- if (hwconfig("dpmac_override")) {
- env_dpmac = env_get("dpmac");
- if (env_dpmac) {
- ret = hwconfig_arg_f("srds", &len, env_dpmac);
- if (ret) {
- if (strncmp(ret, srds, strlen(srds))) {
- printf("SERDES configuration changed.\n"
- "previous: %.*s, current: %s.\n"
- "update dpmac variable.\n",
- (int)len, ret, srds);
- }
- } else {
- printf("SERDES configuration not found.\n"
- "Please add srds:%s in dpmac variable\n",
- srds);
- }
-
- for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
- /* Look for dpmac1 to dpmac24(current max) arg
- * in dpmac environment variable
- */
- sprintf(dpmacid, "dpmac%d", i);
- ret = hwconfig_arg_f(dpmacid, &len, env_dpmac);
- if (ret)
- do_dpmac_config(i, dpmacid, env_dpmac);
- }
- } else {
- printf("Warning: environment dpmac not found.\n"
- "DPAA network interfaces may not work\n");
- }
- } else {
- /*Look for phy config for serdes1 in phy config table*/
- phy_config = get_phy_config(srds_s1, serdes1_phy_config,
- ARRAY_SIZE(serdes1_phy_config));
- if (!phy_config) {
- printf("%s WRIOP: Unsupported SerDes1 Protocol %d\n",
- __func__, srds_s1);
- } else {
- do_phy_config(phy_config);
- }
- phy_config = get_phy_config(srds_s2, serdes2_phy_config,
- ARRAY_SIZE(serdes2_phy_config));
- if (!phy_config) {
- printf("%s WRIOP: Unsupported SerDes2 Protocol %d\n",
- __func__, srds_s2);
- } else {
- do_phy_config(phy_config);
- }
- }
-
- if (wriop_get_enet_if(WRIOP1_DPMAC17) == PHY_INTERFACE_MODE_RGMII_ID) {
- wriop_set_phy_address(WRIOP1_DPMAC17, 0, RGMII_PHY_ADDR1);
- bus = lx2162a_qds_mdio_init(EMI1, EMI1_RGMII1);
- if (!bus)
- printf("could not get bus for RGMII1\n");
- else
- wriop_set_mdio(WRIOP1_DPMAC17, bus);
- }
-
- if (wriop_get_enet_if(WRIOP1_DPMAC18) == PHY_INTERFACE_MODE_RGMII_ID) {
- wriop_set_phy_address(WRIOP1_DPMAC18, 0, RGMII_PHY_ADDR2);
- bus = lx2162a_qds_mdio_init(EMI1, EMI1_RGMII2);
- if (!bus)
- printf("could not get bus for RGMII2\n");
- else
- wriop_set_mdio(WRIOP1_DPMAC18, bus);
- }
-
- cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
-#endif /* !CONFIG_DM_ETH */
-
#ifdef CONFIG_PHY_AQUANTIA
/*
* Export functions to be used by AQ firmware
@@ -595,11 +26,7 @@
gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
#endif
-#ifdef CONFIG_DM_ETH
return 0;
-#else
- return pci_eth_init(bis);
-#endif
}
#if defined(CONFIG_RESET_PHY_R)
@@ -611,273 +38,10 @@
}
#endif /* CONFIG_RESET_PHY_R */
-#ifndef CONFIG_DM_ETH
-#if defined(CONFIG_FSL_MC_ENET)
-int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)
-{
- int offset;
- int ret;
- char dpmac_str[] = "dpmacs@00";
- const char *phy_string;
-
- offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs");
-
- if (offset < 0)
- offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs");
-
- if (offset < 0) {
- printf("dpmacs node not found in device tree\n");
- return offset;
- }
-
- sprintf(dpmac_str, "dpmac@%x", dpmac_id);
- debug("dpmac_str = %s\n", dpmac_str);
-
- offset = fdt_subnode_offset(fdt, offset, dpmac_str);
- if (offset < 0) {
- printf("%s node not found in device tree\n", dpmac_str);
- return offset;
- }
-
- phy_string = fdt_getprop(fdt, offset, "phy-connection-type", NULL);
- if (is_backplane_mode(phy_string)) {
- /* Backplane KR mode: skip fixups */
- printf("Interface %d in backplane KR mode\n", dpmac_id);
- return 0;
- }
-
- ret = fdt_appendprop_cell(fdt, offset, "phy-handle", node_phandle);
- if (ret)
- printf("%d@%s %d\n", __LINE__, __func__, ret);
-
- phy_string = phy_string_for_interface(wriop_get_enet_if(dpmac_id));
- ret = fdt_setprop_string(fdt, offset, "phy-connection-type",
- phy_string);
- if (ret)
- printf("%d@%s %d\n", __LINE__, __func__, ret);
-
- return ret;
-}
-
-int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
-{
- char mdio_ioslot_str[] = "mdio@00";
- struct lx2162a_qds_mdio *priv;
- u64 reg;
- u32 phandle;
- int offset, mux_val;
-
- /*Test if the MDIO bus is real mdio bus or muxing front end ?*/
- if (strncmp(mii_dev->name, "LX2162A_QDS_MDIO",
- strlen("LX2162A_QDS_MDIO")))
- return -1;
-
- /*Get the real MDIO bus num and ioslot info from bus's priv data*/
- priv = mii_dev->priv;
-
- debug("real_bus_num = %d, ioslot = %d\n",
- priv->realbusnum, priv->ioslot);
-
- if (priv->realbusnum == EMI1)
- reg = CFG_SYS_FSL_WRIOP1_MDIO1;
- else
- reg = CFG_SYS_FSL_WRIOP1_MDIO2;
-
- offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg);
- if (offset < 0) {
- printf("mdio@%llx node not found in device tree\n", reg);
- return offset;
- }
-
- phandle = fdt_get_phandle(fdt, offset);
- phandle = cpu_to_fdt32(phandle);
- offset = fdt_node_offset_by_prop_value(fdt, -1, "mdio-parent-bus",
- &phandle, 4);
- if (offset < 0) {
- printf("mdio-mux-%d node not found in device tree\n",
- priv->realbusnum == EMI1 ? 1 : 2);
- return offset;
- }
-
- mux_val = lx2162a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
- if (priv->realbusnum == EMI1)
- mux_val >>= BRDCFG4_EMI1SEL_SHIFT;
- else
- mux_val >>= BRDCFG4_EMI2SEL_SHIFT;
- sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val);
-
- offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str);
- if (offset < 0) {
- printf("%s node not found in device tree\n", mdio_ioslot_str);
- return offset;
- }
-
- return offset;
-}
-
-int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset,
- struct phy_device *phy_dev, int phandle)
-{
- char phy_node_name[] = "ethernet-phy@00";
- char phy_id_compatible_str[] = "ethernet-phy-id0000.0000,";
- int ret;
-
- sprintf(phy_node_name, "ethernet-phy@%x", phyaddr);
- debug("phy_node_name = %s\n", phy_node_name);
-
- *subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name);
- if (*subnodeoffset <= 0) {
- printf("Could not add subnode %s inside node %s err = %s\n",
- phy_node_name, fdt_get_name(fdt, offset, NULL),
- fdt_strerror(*subnodeoffset));
- return *subnodeoffset;
- }
-
- sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x,",
- phy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF);
- debug("phy_id_compatible_str %s\n", phy_id_compatible_str);
-
- ret = fdt_setprop_string(fdt, *subnodeoffset, "compatible",
- phy_id_compatible_str);
- if (ret) {
- printf("%d@%s %d\n", __LINE__, __func__, ret);
- goto out;
- }
-
- if (phy_dev->is_c45) {
- ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
- "ethernet-phy-ieee802.3-c45");
- if (ret) {
- printf("%d@%s %d\n", __LINE__, __func__, ret);
- goto out;
- }
- } else {
- ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
- "ethernet-phy-ieee802.3-c22");
- if (ret) {
- printf("%d@%s %d\n", __LINE__, __func__, ret);
- goto out;
- }
- }
-
- ret = fdt_setprop_cell(fdt, *subnodeoffset, "reg", phyaddr);
- if (ret) {
- printf("%d@%s %d\n", __LINE__, __func__, ret);
- goto out;
- }
-
- ret = fdt_set_phandle(fdt, *subnodeoffset, phandle);
- if (ret) {
- printf("%d@%s %d\n", __LINE__, __func__, ret);
- goto out;
- }
-
-out:
- if (ret)
- fdt_del_node(fdt, *subnodeoffset);
-
- return ret;
-}
-
-#define is_rgmii(dpmac_id) \
- wriop_get_enet_if((dpmac_id)) == PHY_INTERFACE_MODE_RGMII_ID
-
-int fdt_fixup_board_phy(void *fdt)
-{
- int fpga_offset, offset, subnodeoffset;
- struct mii_dev *mii_dev;
- struct list_head *mii_devs, *entry;
- int ret, dpmac_id, i;
- struct phy_device *phy_dev;
- char ethname[ETH_NAME_LEN];
- phy_interface_t phy_iface;
- uint32_t phandle;
-
- ret = 0;
- /* we know FPGA is connected to i2c0, therefore search path directly,
- * instead of compatible property, as it saves time
- */
- fpga_offset = fdt_path_offset(fdt, "/soc/i2c@2000000/fpga");
-
- if (fpga_offset < 0)
- fpga_offset = fdt_path_offset(fdt, "/i2c@2000000/fpga");
-
- if (fpga_offset < 0) {
- printf("i2c@2000000/fpga node not found in device tree\n");
- return fpga_offset;
- }
-
- ret = fdt_generate_phandle(fdt, &phandle);
- if (ret < 0)
- return ret;
-
- mii_devs = mdio_get_list_head();
-
- list_for_each(entry, mii_devs) {
- mii_dev = list_entry(entry, struct mii_dev, link);
- debug("mii_dev name : %s\n", mii_dev->name);
- offset = fdt_get_ioslot_offset(fdt, mii_dev, fpga_offset);
- if (offset < 0)
- continue;
-
- // Look for phy devices attached to MDIO bus muxing front end
- // and create their entries with compatible being the device id
- for (i = 0; i < PHY_MAX_ADDR; i++) {
- phy_dev = mii_dev->phymap[i];
- if (!phy_dev)
- continue;
-
- // TODO: use sscanf instead of loop
- dpmac_id = WRIOP1_DPMAC1;
- while (dpmac_id < NUM_WRIOP_PORTS) {
- phy_iface = wriop_get_enet_if(dpmac_id);
- snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s",
- dpmac_id,
- phy_string_for_interface(phy_iface));
- if (strcmp(ethname, phy_dev->dev->name) == 0)
- break;
- dpmac_id++;
- }
- if (dpmac_id == NUM_WRIOP_PORTS)
- continue;
-
- if ((dpmac_id == 17 || dpmac_id == 18) &&
- is_rgmii(dpmac_id))
- continue;
-
- ret = fdt_create_phy_node(fdt, offset, i,
- &subnodeoffset,
- phy_dev, phandle);
- if (ret)
- break;
-
- ret = fdt_fixup_dpmac_phy_handle(fdt,
- dpmac_id, phandle);
- if (ret) {
- fdt_del_node(fdt, subnodeoffset);
- break;
- }
- /* calculate offset again as new node addition may have
- * changed offset;
- */
- offset = fdt_get_ioslot_offset(fdt, mii_dev,
- fpga_offset);
- phandle++;
- }
-
- if (ret)
- break;
- }
-
- return ret;
-}
-#endif // CONFIG_FSL_MC_ENET
-#endif
-
-#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
+#if defined(CONFIG_MULTI_DTB_FIT)
-/* Structure to hold SERDES protocols supported in case of
- * CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
+/* Structure to hold SERDES protocols supported (network interfaces are
+ * described in the DTS).
*
* @serdes_block: the index of the SERDES block
* @serdes_protocol: the decimal value of the protocol supported
diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index d8a86cd..33842d0 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -572,7 +572,7 @@
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
#endif
-#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
+#if !defined(CONFIG_SYS_EARLY_PCI_INIT)
pci_init();
#endif
return 0;
@@ -642,7 +642,6 @@
#endif
#ifdef CONFIG_FSL_MC_ENET
-extern int fdt_fixup_board_phy(void *fdt);
void fdt_fixup_board_enet(void *fdt)
{
@@ -662,9 +661,6 @@
if (get_mc_boot_status() == 0 &&
(is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
fdt_status_okay(fdt, offset);
-#ifndef CONFIG_DM_ETH
- fdt_fixup_board_phy(fdt);
-#endif
} else {
fdt_status_fail(fdt, offset);
}
diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig
index a9faa15..9f10dd2 100644
--- a/configs/ls2088aqds_tfa_defconfig
+++ b/configs/ls2088aqds_tfa_defconfig
@@ -18,7 +18,6 @@
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_REMAKE_ELF=y
CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_MP=y
@@ -113,7 +112,9 @@
CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
CONFIG_RTC_DS3231=y
CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
index 1dd7c1d..f110bee 100644
--- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
@@ -100,8 +100,10 @@
CONFIG_DM_RTC=y
CONFIG_RTC_DS3231=y
CONFIG_DM_SCSI=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_CONS_INDEX=2
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig
index 246ab40..6ff4e49 100644
--- a/configs/ls2088ardb_tfa_defconfig
+++ b/configs/ls2088ardb_tfa_defconfig
@@ -108,8 +108,10 @@
CONFIG_DM_RTC=y
CONFIG_RTC_DS3231=y
CONFIG_DM_SCSI=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_CONS_INDEX=2
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y