Merge branch 'master' of git://git.denx.de/u-boot-tegra
The bulk of these changes are an effort to unify Tegra186 builds with
builds of prior 64-bit Tegra generations. On top of that there are
various improvements that allow data (such as the MAC address and boot
arguments) to be passed through from early firmware to the kernel on
boot.
diff --git a/Makefile b/Makefile
index 0710613..8de3d41 100644
--- a/Makefile
+++ b/Makefile
@@ -337,6 +337,19 @@
# KBUILD_MODULES := 1
#endif
+define size_check
+ actual=$$( wc -c $1 | awk '{print $$1}'); \
+ limit=$$( printf "%d" $2 ); \
+ if test $$actual -gt $$limit; then \
+ echo "$1 exceeds file size limit:" >&2; \
+ echo " limit: $$limit bytes" >&2; \
+ echo " actual: $$actual bytes" >&2; \
+ echo " excess: $$((actual - limit)) bytes" >&2; \
+ exit 1; \
+ fi
+endef
+export size_check
+
export KBUILD_MODULES KBUILD_BUILTIN
export KBUILD_CHECKSRC KBUILD_SRC KBUILD_EXTMOD
@@ -778,20 +791,17 @@
#########################################################################
ifneq ($(CONFIG_BOARD_SIZE_LIMIT),)
-BOARD_SIZE_CHECK = \
- @actual=`wc -c $@ | awk '{print $$1}'`; \
- limit=`printf "%d" $(CONFIG_BOARD_SIZE_LIMIT)`; \
- if test $$actual -gt $$limit; then \
- echo "$@ exceeds file size limit:" >&2 ; \
- echo " limit: $$limit bytes" >&2 ; \
- echo " actual: $$actual bytes" >&2 ; \
- echo " excess: $$((actual - limit)) bytes" >&2; \
- exit 1; \
- fi
+BOARD_SIZE_CHECK= @ $(call size_check,$@,$(CONFIG_BOARD_SIZE_LIMIT))
else
BOARD_SIZE_CHECK =
endif
+ifneq ($(CONFIG_SPL_SIZE_LIMIT),0)
+SPL_SIZE_CHECK = @$(call size_check,$@,$$(tools/spl_size_limit))
+else
+SPL_SIZE_CHECK =
+endif
+
# Statically apply RELA-style relocations (currently arm64 only)
# This is useful for arm64 where static relocation needs to be performed on
# the raw binary, but certain simulators only accept an ELF file (but don't
@@ -1090,6 +1100,7 @@
%.imx: %.bin
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
+ $(BOARD_SIZE_CHECK)
%.vyb: %.imx
$(Q)$(MAKE) $(build)=arch/arm/cpu/armv7/vf610 $@
@@ -1707,6 +1718,8 @@
spl/u-boot-spl.bin: spl/u-boot-spl
@:
+ $(SPL_SIZE_CHECK)
+
spl/u-boot-spl: tools prepare \
$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) \
$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATDATA),dts/dt.dtb)
@@ -1769,6 +1782,7 @@
envtools: scripts_basic $(version_h) $(timestamp_h)
$(Q)$(MAKE) $(build)=tools/env
+tools-only: export TOOLS_ONLY=y
tools-only: scripts_basic $(version_h) $(timestamp_h)
$(Q)$(MAKE) $(build)=tools
diff --git a/arch/arm/dts/imx6-logicpd-baseboard.dtsi b/arch/arm/dts/imx6-logicpd-baseboard.dtsi
index 303c093..c40a7af 100644
--- a/arch/arm/dts/imx6-logicpd-baseboard.dtsi
+++ b/arch/arm/dts/imx6-logicpd-baseboard.dtsi
@@ -1,45 +1,6 @@
-/*
- * Copyright 2018 Logic PD, Inc.
- * Based on SabreSD, Copyright 2016 Freescale Semiconductor, Inc.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2019 Logic PD, Inc.
/ {
keyboard {
@@ -68,6 +29,7 @@
debounce-interval = <10>;
wakeup-source;
};
+
btn3 {
gpios = <&pcf8575 3 GPIO_ACTIVE_LOW>;
label = "btn3";
@@ -81,7 +43,7 @@
leds {
compatible = "gpio-leds";
- gen_led0 {
+ gen-led0 {
label = "led0";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led0>;
@@ -89,25 +51,27 @@
linux,default-trigger = "cpu0";
};
- gen_led1 {
+ gen-led1 {
label = "led1";
gpios = <&pcf8575 8 GPIO_ACTIVE_HIGH>;
};
- gen_led2 {
+ gen-led2 {
label = "led2";
gpios = <&pcf8575 9 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
- gen_led3 {
+ gen-led3 {
label = "led3";
gpios = <&pcf8575 10 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
};
- reg_usb_otg_vbus: regulator-otg-vbus@0 {
+ reg_usb_otg_vbus: regulator-otg-vbus {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb_otg>;
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
@@ -116,14 +80,19 @@
enable-active-high;
};
- reg_usb_h1_vbus: regulator-usbh1vbus@1 {
+ reg_usb_h1_vbus: regulator-usb-h1-vbus {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>;
compatible = "regulator-fixed";
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
+ gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <70000>;
+ enable-active-high;
};
- reg_3v3: regulator-3v3@2 {
+ reg_3v3: regulator-3v3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_3v3>;
compatible = "regulator-fixed";
@@ -131,13 +100,14 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <70000>;
enable-active-high;
regulator-always-on;
};
- reg_enet: regulator-ethernet@3 {
+ reg_enet: regulator-ethernet {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet_pwr>;
+ pinctrl-0 = <&pinctrl_reg_enet>;
compatible = "regulator-fixed";
regulator-name = "ethernet-supply";
regulator-min-microvolt = <3300000>;
@@ -148,7 +118,7 @@
vin-supply = <&sw4_reg>;
};
- reg_audio: regulator-audio@4 {
+ reg_audio: regulator-audio {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_audio>;
compatible = "regulator-fixed";
@@ -157,11 +127,10 @@
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
enable-active-high;
- regulator-always-on;
vin-supply = <®_3v3>;
};
- reg_hdmi: regulator-hdmi@5 {
+ reg_hdmi: regulator-hdmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_hdmi>;
compatible = "regulator-fixed";
@@ -173,7 +142,7 @@
vin-supply = <®_3v3>;
};
- reg_uart3: regulator-uart3@6 {
+ reg_uart3: regulator-uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_uart3>;
compatible = "regulator-fixed";
@@ -184,7 +153,7 @@
vin-supply = <®_3v3>;
};
- reg_1v8: regulator-1v8@7 {
+ reg_1v8: regulator-1v8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_1v8>;
compatible = "regulator-fixed";
@@ -195,21 +164,21 @@
vin-supply = <®_3v3>;
};
- reg_pcie: regulator@8 {
+ reg_pcie: regulator-pcie {
compatible = "regulator-fixed";
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie_reg>;
- regulator-name = "MPCIE_3V3";
+ pinctrl-0 = <&pinctrl_reg_pcie>;
+ regulator-name = "mpcie_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
- mipi_pwr: regulator@9 {
+ reg_mipi: regulator-mipi {
compatible = "regulator-fixed";
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_mipi_pwr>;
+ pinctrl-0 = <&pinctrl_reg_mipi>;
regulator-name = "mipi_pwr_en";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
@@ -221,7 +190,7 @@
compatible = "fsl,imx-audio-wm8962";
model = "wm8962-audio";
ssi-controller = <&ssi2>;
- audio-codec = <&codec>;
+ audio-codec = <&wm8962>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
@@ -246,34 +215,10 @@
status = "disabled";
};
-&pwm3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm3>;
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- status = "okay";
-};
-
-&usbh1 {
- vbus-supply = <®_usb_h1_vbus>;
- status = "okay";
-};
-
-&usbotg {
- vbus-supply = <®_usb_otg_vbus>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg>;
- disable-over-current;
- status = "okay";
-};
-
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
phy-reset-duration = <10>;
phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
phy-supply = <®_enet>;
@@ -282,23 +227,13 @@
status = "okay";
};
-&usdhc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
- no-1-8-v;
- keep-power-in-suspend;
- status = "okay";
-};
-
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clock-frequency = <400000>;
status = "okay";
- codec: wm8962@1a {
+ wm8962: audio-codec@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clks IMX6QDL_CLK_CKO>;
@@ -330,9 +265,9 @@
reg = <0x10>;
clocks = <&clks IMX6QDL_CLK_CKO>;
clock-names = "xclk";
- DOVDD-supply = <&mipi_pwr>;
- AVDD-supply = <&mipi_pwr>;
- DVDD-supply = <&mipi_pwr>;
+ DOVDD-supply = <®_mipi>;
+ AVDD-supply = <®_mipi>;
+ DVDD-supply = <®_mipi>;
reset-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
powerdown-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
@@ -361,6 +296,11 @@
};
};
+&ipu1_csi1_from_mipi_vc1 {
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+};
+
&mipi_csi {
status = "okay";
@@ -379,17 +319,52 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
- status = "okay";
vpcie-supply = <®_pcie>;
- /* fsl,max-link-speed = <2>; */
+ status = "okay";
};
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+};
+
&ssi2 {
status = "okay";
};
-&iomuxc {
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+&usbh1 {
+ vbus-supply = <®_usb_h1_vbus>;
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <®_usb_otg_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ vmmc-supply = <®_3v3>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&iomuxc {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
@@ -399,23 +374,51 @@
>;
};
- pinctrl_i2c1: i2c1 {
+ pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x100b1
>;
};
- pinctrl_enet_pwr: enet_pwr {
+ pinctrl_enet: enetgrp {
fsl,pins = <
- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
+ MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* ENET_INT */
+ MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1b0b0 /* ETHR_nRST */
>;
};
- pinctrl_mipi_pwr: pwr_mipi {
- fsl,pins = <MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b1>;
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
};
+ pinctrl_led0: led0grp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
+ >;
+ };
+
pinctrl_ov5640: ov5640grp {
fsl,pins = <
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b1
@@ -423,174 +426,132 @@
>;
};
- pinctrl_reg_hdmi: reg_hdmi {
+ pinctrl_pcf8574: pcf8575grp {
fsl,pins = <
- MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
+ MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
>;
};
- pinctrl_uart3: uart3grp {
+ pinctrl_pcie: pciegrp {
fsl,pins = <
- MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
+ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
>;
};
- pinctrl_usbotg: usbotggrp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0xd17059
- MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x130b0
- >;
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
+ >;
};
- pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
- MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
- MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
- MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x100b1
- >;
+ pinctrl_reg_1v8: reg1v8grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0
+ >;
};
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17069
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17069
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17069
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17069
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17069
- >;
- };
-
- pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz {
- fsl,pins = <
- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
- >;
+ pinctrl_reg_3v3: reg3v3grp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0
+ >;
};
- pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz {
+ pinctrl_reg_audio: reg-audiogrp {
fsl,pins = <
- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
+ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
>;
};
- pinctrl_enet: enetgrp {
+ pinctrl_reg_enet: reg-enetgrp {
fsl,pins = <
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
- MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* ENET_INT */
- MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1b0b0 /* ETHR_nRST */
+ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0
>;
};
- pinctrl_reg_audio: audio-reg {
+ pinctrl_reg_hdmi: reg-hdmigrp {
fsl,pins = <
- MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
+ MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
>;
};
- pinctrl_pcie: pcie {
- fsl,pins = <
- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
- >;
+ pinctrl_reg_mipi: reg-mipigrp {
+ fsl,pins = <MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b1>;
};
- pinctrl_pcie_reg: pciereggrp {
+ pinctrl_reg_pcie: reg-pciegrp {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
>;
};
+ pinctrl_reg_uart3: reguart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
+ >;
+ };
+
- pinctrl_pcf8574: pcf8575-pins {
+ pinctrl_reg_usb_h1_vbus: usbh1grp {
fsl,pins = <
- MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
>;
};
- pinctrl_lcd: lcdgrp {
+ pinctrl_reg_usb_otg: reg-usb-otggrp {
fsl,pins = <
- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* R_LCD_DCLK */
- MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x100b0 /* R_LCD_PANEL_PWR */
- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* R_LCD_HSYNC */
- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* R_LCD_VSYNC */
- MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 /* R_LCD_MDISP */
- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
>;
};
- pinctrl_pwm3: pwm3grp {
+ pinctrl_uart3: uart3grp {
fsl,pins = <
- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
+ MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
>;
};
- pinctrl_reg_uart3: uart3reg {
+ pinctrl_usbotg: usbotggrp {
fsl,pins = <
- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0xd17059
>;
};
- pinctrl_reg_3v3: reg-3v3 {
+ pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
- MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17069
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17069
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17069
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17069
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17069
>;
};
- pinctrl_reg_1v8: reg-1v8 {
+ pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz {
fsl,pins = <
- MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
>;
};
- pinctrl_led0: led0 {
+ pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz {
fsl,pins = <
- MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
>;
};
+
};
diff --git a/arch/arm/dts/imx6-logicpd-som.dtsi b/arch/arm/dts/imx6-logicpd-som.dtsi
index 3fc50ba..7ceae35 100644
--- a/arch/arm/dts/imx6-logicpd-som.dtsi
+++ b/arch/arm/dts/imx6-logicpd-som.dtsi
@@ -1,16 +1,6 @@
-/*
- * Copyright 2018 Logic PD
- * This file is adapted from imx6qdl-sabresd.dtsi.
- * Copyright 2012 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2019 Logic PD, Inc.
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
@@ -20,7 +10,8 @@
stdout-path = &uart1;
};
- memory {
+ memory@10000000 {
+ device_type = "memory";
reg = <0x10000000 0x80000000>;
};
@@ -35,17 +26,6 @@
};
};
-/* Reroute power feeding the CPU to come from the external PMIC */
-®_arm
-{
- vin-supply = <&sw1a_reg>;
-};
-
-®_soc
-{
- vin-supply = <&sw1c_reg>;
-};
-
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
@@ -56,8 +36,8 @@
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
- status = "okay";
nand-on-flash-bbt;
+ status = "okay";
};
&i2c3 {
@@ -66,7 +46,7 @@
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
- pmic: pfuze100@08 {
+ pfuze100: pmic@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
@@ -94,20 +74,19 @@
regulator-max-microvolt = <3300000>;
regulator-name = "gen_3v3";
regulator-boot-on;
- /* regulator-always-on; */
};
sw3a_reg: sw3a {
- regulator-min-microvolt = <400000>;
- regulator-max-microvolt = <1975000>;
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
regulator-name = "sw3a_vddr";
regulator-boot-on;
regulator-always-on;
};
sw3b_reg: sw3b {
- regulator-min-microvolt = <400000>;
- regulator-max-microvolt = <1975000>;
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
regulator-name = "sw3b_vddr";
regulator-boot-on;
regulator-always-on;
@@ -152,8 +131,8 @@
vgen3_reg: vgen3 {
regulator-name = "gen_vadj_0";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
};
vgen4_reg: vgen4 {
@@ -164,8 +143,8 @@
};
vgen5_reg: vgen5 {
- regulator-name = "gen_adj_1";
- regulator-min-microvolt = <3300000>;
+ regulator-name = "gen_vadj_1";
+ regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
@@ -185,44 +164,75 @@
};
};
- temp_sense0: tmp102@4a {
+ temperature-sensor@49 {
compatible = "ti,tmp102";
- reg = <0x4a>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_tempsense>;
+ reg = <0x49>;
interrupt-parent = <&gpio6>;
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
#thermal-sensor-cells = <1>;
};
- temp_sense1: tmp102@49 {
+ temperature-sensor@4a {
compatible = "ti,tmp102";
- reg = <0x49>;
+ reg = <0x4a>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tempsense>;
interrupt-parent = <&gpio6>;
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
#thermal-sensor-cells = <1>;
};
- mfg_eeprom: at24@51 {
+ eeprom@51 {
compatible = "atmel,24c64";
pagesize = <32>;
- read-only;
+ read-only; /* Manufacturing EEPROM programmed at factory */
reg = <0x51>;
};
- user_eeprom: at24@52 {
+ eeprom@52 {
compatible = "atmel,24c64";
pagesize = <32>;
reg = <0x52>;
};
};
+/* Reroute power feeding the CPU to come from the external PMIC */
+®_arm
+{
+ vin-supply = <&sw1a_reg>;
+};
+
+®_soc
+{
+ vin-supply = <&sw1c_reg>;
+};
+
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
- pinctrl_hog: hoggrp {
+ pinctrl_gpmi_nand: gpmi-nandgrp {
fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
+ >;
+ };
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = < /* Enable ARM Debugger */
MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x1b0b0
MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x1b0b0
MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x1b0b0
@@ -246,30 +256,16 @@
>;
};
- pinctrl_gpmi_nand: gpminandgrp {
+ pinctrl_i2c3: i2c3grp {
fsl,pins = <
- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
+ MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
>;
};
- pinctrl_i2c3: i2c3grp {
+ pinctrl_tempsense: tempsensegrp {
fsl,pins = <
- MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0
>;
};
@@ -282,7 +278,7 @@
pinctrl_uart2: uart2grp {
fsl,pins = <
- MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x13059 /* BT_EN */
+ MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x13059 /* BT_EN */
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
@@ -313,12 +309,6 @@
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* WLAN_EN */
>;
};
-
- pinctrl_tempsense: tempsensegrp {
- fsl,pins = <
- MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Temp Sense Alert */
- >;
- };
};
&snvs_poweroff {
@@ -334,8 +324,9 @@
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
uart-has-rtscts;
+ status = "okay";
+
bluetooth {
compatible = "ti,wl1837-st";
enable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
@@ -347,9 +338,9 @@
pinctrl-0 = <&pinctrl_usdhc1>;
non-removable;
keep-power-in-suspend;
- enable-sdio-wakeup;
- status = "okay";
+ wakeup-source;
vmmc-supply = <&sw2_reg>;
+ status = "okay";
};
&usdhc3 {
@@ -360,9 +351,10 @@
keep-power-in-suspend;
wakeup-source;
vmmc-supply = <®_wl18xx_vmmc>;
- status = "okay";
#address-cells = <1>;
#size-cells = <0>;
+ status = "okay";
+
wlcore: wlcore@2 {
compatible = "ti,wl1837";
reg = <2>;
diff --git a/arch/arm/dts/imx6q-logicpd.dts b/arch/arm/dts/imx6q-logicpd.dts
index dcea784..45eb0b7 100644
--- a/arch/arm/dts/imx6q-logicpd.dts
+++ b/arch/arm/dts/imx6q-logicpd.dts
@@ -1,45 +1,6 @@
-/*
- * Copyright 2018 Logic PD, Inc.
- * Based on SabreSD, Copyright 2016 Freescale Semiconductor, Inc.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2019 Logic PD, Inc.
/dts-v1/;
#include "imx6q.dtsi"
@@ -47,10 +8,10 @@
#include "imx6-logicpd-baseboard.dtsi"
/ {
- model = "Logic PD i.MX6QD SOM-M3 (HDMI)";
+ model = "Logic PD i.MX6QD SOM-M3";
compatible = "fsl,imx6q";
- backlight: backlight_lvds {
+ backlight: backlight-lvds {
compatible = "pwm-backlight";
pwms = <&pwm3 0 20000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -58,6 +19,16 @@
power-supply = <®_lcd>;
};
+ panel-lvds0 {
+ compatible = "okaya,rs800480t-7x0gp";
+
+ port {
+ panel_in_lvds0: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+
reg_lcd: regulator-lcd {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_reg>;
@@ -72,7 +43,7 @@
startup-delay-us = <500000>;
};
- lcd_reset: lcd_reset {
+ reg_lcd_reset: regulator-lcd-reset {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_reset>;
compatible = "regulator-fixed";
@@ -84,17 +55,17 @@
regulator-always-on;
vin-supply = <®_lcd>;
};
-
- panel-lvds0 {
- compatible = "ampire,am800480b3tmqw";
- backlight = <&backlight>;
+};
- port {
- panel_in_lvds0: endpoint {
- remote-endpoint = <&lvds0_out>;
- };
- };
- };
+&clks {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
+ <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
+ <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
+ <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
+ <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+ <&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
};
&hdmi {
@@ -102,22 +73,6 @@
status = "okay";
};
-&i2c1 {
- ili_touch: ilitouch@26 {
- compatible = "ili,ili2117a";
- reg = <0x26>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_touchscreen>;
- interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_RISING>;
- ili2117a,poll-period = <10>;
- ili2117a,max-touch = <2>;
- };
-};
-
-®_hdmi {
- regulator-always-on;
-};
-
&ldb {
status = "okay";
@@ -128,32 +83,20 @@
port@4 {
reg = <4>;
-
lvds0_out: endpoint {
remote-endpoint = <&panel_in_lvds0>;
};
};
};
-};
-
-&clks {
- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
- <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
- <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
- <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
- <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
- <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
- <&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
};
&pwm3 {
status = "okay";
};
-&usdhc2 {
- cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+®_hdmi {
+ regulator-always-on; /* Without this, the level shifter on HDMI doesn't turn on */
};
&iomuxc {
@@ -165,7 +108,7 @@
pinctrl_lcd_reset: lcdreset {
fsl,pins = <
- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 /* LCD_nRESET */
+ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 /* LCD_nRESET */
>;
};
@@ -175,4 +118,3 @@
>;
};
};
-
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 61e84e5..adc5092 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -134,7 +134,6 @@
source "board/lego/ev3/Kconfig"
config SPL_LDSCRIPT
- default "board/$(BOARDDIR)/u-boot-spl-ipam390.lds" if TARGET_IPAM390
default "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
endif
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 6887fe0..ed88274 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -18,7 +18,3 @@
obj-$(CONFIG_SOC_DM365) += dm365_lowlevel.o
obj-$(CONFIG_SOC_DA8XX) += da850_lowlevel.o
endif
-
-ifndef CONFIG_SKIP_LOWLEVEL_INIT
-obj-y += lowlevel_init.o
-endif
diff --git a/arch/arm/mach-davinci/lowlevel_init.S b/arch/arm/mach-davinci/lowlevel_init.S
deleted file mode 100644
index b82dafa..0000000
--- a/arch/arm/mach-davinci/lowlevel_init.S
+++ /dev/null
@@ -1,692 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Low-level board setup code for TI DaVinci SoC based boards.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Partially based on TI sources, original copyrights follow:
- */
-
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
- *
- * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
- *
- * Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005
- *
- * Modified for DV-EVM board by Swaminathan S, Nov 2005
- */
-
-#include <config.h>
-
-#define MDSTAT_STATE 0x3f
-
-.globl lowlevel_init
-lowlevel_init:
-#ifdef CONFIG_SOC_DM644X
-
- /*-------------------------------------------------------*
- * Mask all IRQs by setting all bits in the EINT default *
- *-------------------------------------------------------*/
- mov r1, $0
- ldr r0, =EINT_ENABLE0
- str r1, [r0]
- ldr r0, =EINT_ENABLE1
- str r1, [r0]
-
- /*------------------------------------------------------*
- * Put the GEM in reset *
- *------------------------------------------------------*/
-
- /* Put the GEM in reset */
- ldr r8, PSC_GEM_FLAG_CLEAR
- ldr r6, MDCTL_GEM
- ldr r7, [r6]
- and r7, r7, r8
- str r7, [r6]
-
- /* Enable the Power Domain Transition Command */
- ldr r6, PTCMD
- ldr r7, [r6]
- orr r7, r7, $0x02
- str r7, [r6]
-
- /* Check for Transition Complete(PTSTAT) */
-checkStatClkStopGem:
- ldr r6, PTSTAT
- ldr r7, [r6]
- ands r7, r7, $0x02
- bne checkStatClkStopGem
-
- /* Check for GEM Reset Completion */
-checkGemStatClkStop:
- ldr r6, MDSTAT_GEM
- ldr r7, [r6]
- ands r7, r7, $0x100
- bne checkGemStatClkStop
-
- /* Do this for enabling a WDT initiated reset this is a workaround
- for a chip bug. Not required under normal situations */
- ldr r6, P1394
- mov r10, $0
- str r10, [r6]
-
- /*------------------------------------------------------*
- * Enable L1 & L2 Memories in Fast mode *
- *------------------------------------------------------*/
- ldr r6, DFT_ENABLE
- mov r10, $0x01
- str r10, [r6]
-
- ldr r6, MMARG_BRF0
- ldr r10, MMARG_BRF0_VAL
- str r10, [r6]
-
- ldr r6, DFT_ENABLE
- mov r10, $0
- str r10, [r6]
-
- /*------------------------------------------------------*
- * DDR2 PLL Initialization *
- *------------------------------------------------------*/
-
- /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
- mov r10, $0
- ldr r6, PLL2_CTL
- ldr r7, PLL_CLKSRC_MASK
- ldr r8, [r6]
- and r8, r8, r7
- mov r9, r10, lsl $8
- orr r8, r8, r9
- str r8, [r6]
-
- /* Select the PLLEN source */
- ldr r7, PLL_ENSRC_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Bypass the PLL */
- ldr r7, PLL_BYPASS_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
- mov r10, $0x20
-WaitPPL2Loop:
- subs r10, r10, $1
- bne WaitPPL2Loop
-
- /* Reset the PLL */
- ldr r7, PLL_RESET_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Power up the PLL */
- ldr r7, PLL_PWRUP_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Enable the PLL from Disable Mode */
- ldr r7, PLL_DISABLE_ENABLE_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Program the PLL Multiplier */
- ldr r6, PLL2_PLLM
- mov r2, $0x17 /* 162 MHz */
- str r2, [r6]
-
- /* Program the PLL2 Divisor Value */
- ldr r6, PLL2_DIV2
- mov r3, $0x01
- str r3, [r6]
-
- /* Program the PLL2 Divisor Value */
- ldr r6, PLL2_DIV1
- mov r4, $0x0b /* 54 MHz */
- str r4, [r6]
-
- /* PLL2 DIV2 MMR */
- ldr r8, PLL2_DIV_MASK
- ldr r6, PLL2_DIV2
- ldr r9, [r6]
- and r8, r8, r9
- mov r9, $0x01
- mov r9, r9, lsl $15
- orr r8, r8, r9
- str r8, [r6]
-
- /* Program the GOSET bit to take new divider values */
- ldr r6, PLL2_PLLCMD
- ldr r7, [r6]
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Wait for Done */
- ldr r6, PLL2_PLLSTAT
-doneLoop_0:
- ldr r7, [r6]
- ands r7, r7, $0x01
- bne doneLoop_0
-
- /* PLL2 DIV1 MMR */
- ldr r8, PLL2_DIV_MASK
- ldr r6, PLL2_DIV1
- ldr r9, [r6]
- and r8, r8, r9
- mov r9, $0x01
- mov r9, r9, lsl $15
- orr r8, r8, r9
- str r8, [r6]
-
- /* Program the GOSET bit to take new divider values */
- ldr r6, PLL2_PLLCMD
- ldr r7, [r6]
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Wait for Done */
- ldr r6, PLL2_PLLSTAT
-doneLoop:
- ldr r7, [r6]
- ands r7, r7, $0x01
- bne doneLoop
-
- /* Wait for PLL to Reset Properly */
- mov r10, $0x218
-ResetPPL2Loop:
- subs r10, r10, $1
- bne ResetPPL2Loop
-
- /* Bring PLL out of Reset */
- ldr r6, PLL2_CTL
- ldr r8, [r6]
- orr r8, r8, $0x08
- str r8, [r6]
-
- /* Wait for PLL to Lock */
- ldr r10, PLL_LOCK_COUNT
-PLL2Lock:
- subs r10, r10, $1
- bne PLL2Lock
-
- /* Enable the PLL */
- ldr r6, PLL2_CTL
- ldr r8, [r6]
- orr r8, r8, $0x01
- str r8, [r6]
-
- /*------------------------------------------------------*
- * Issue Soft Reset to DDR Module *
- *------------------------------------------------------*/
-
- /* Shut down the DDR2 LPSC Module */
- ldr r8, PSC_FLAG_CLEAR
- ldr r6, MDCTL_DDR2
- ldr r7, [r6]
- and r7, r7, r8
- orr r7, r7, $0x03
- str r7, [r6]
-
- /* Enable the Power Domain Transition Command */
- ldr r6, PTCMD
- ldr r7, [r6]
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Check for Transition Complete(PTSTAT) */
-checkStatClkStop:
- ldr r6, PTSTAT
- ldr r7, [r6]
- ands r7, r7, $0x01
- bne checkStatClkStop
-
- /* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkStop:
- ldr r6, MDSTAT_DDR2
- ldr r7, [r6]
- and r7, r7, $MDSTAT_STATE
- cmp r7, $0x03
- bne checkDDRStatClkStop
-
- /*------------------------------------------------------*
- * Program DDR2 MMRs for 162MHz Setting *
- *------------------------------------------------------*/
-
- /* Program PHY Control Register */
- ldr r6, DDRCTL
- ldr r7, DDRCTL_VAL
- str r7, [r6]
-
- /* Program SDRAM Bank Config Register */
- ldr r6, SDCFG
- ldr r7, SDCFG_VAL
- str r7, [r6]
-
- /* Program SDRAM TIM-0 Config Register */
- ldr r6, SDTIM0
- ldr r7, SDTIM0_VAL_162MHz
- str r7, [r6]
-
- /* Program SDRAM TIM-1 Config Register */
- ldr r6, SDTIM1
- ldr r7, SDTIM1_VAL_162MHz
- str r7, [r6]
-
- /* Program the SDRAM Bank Config Control Register */
- ldr r10, MASK_VAL
- ldr r8, SDCFG
- ldr r9, SDCFG_VAL
- and r9, r9, r10
- str r9, [r8]
-
- /* Program SDRAM SDREF Config Register */
- ldr r6, SDREF
- ldr r7, SDREF_VAL
- str r7, [r6]
-
- /*------------------------------------------------------*
- * Issue Soft Reset to DDR Module *
- *------------------------------------------------------*/
-
- /* Issue a Dummy DDR2 read/write */
- ldr r8, DDR2_START_ADDR
- ldr r7, DUMMY_VAL
- str r7, [r8]
- ldr r7, [r8]
-
- /* Shut down the DDR2 LPSC Module */
- ldr r8, PSC_FLAG_CLEAR
- ldr r6, MDCTL_DDR2
- ldr r7, [r6]
- and r7, r7, r8
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Enable the Power Domain Transition Command */
- ldr r6, PTCMD
- ldr r7, [r6]
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Check for Transition Complete(PTSTAT) */
-checkStatClkStop2:
- ldr r6, PTSTAT
- ldr r7, [r6]
- ands r7, r7, $0x01
- bne checkStatClkStop2
-
- /* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkStop2:
- ldr r6, MDSTAT_DDR2
- ldr r7, [r6]
- and r7, r7, $MDSTAT_STATE
- cmp r7, $0x01
- bne checkDDRStatClkStop2
-
- /*------------------------------------------------------*
- * Turn DDR2 Controller Clocks On *
- *------------------------------------------------------*/
-
- /* Enable the DDR2 LPSC Module */
- ldr r6, MDCTL_DDR2
- ldr r7, [r6]
- orr r7, r7, $0x03
- str r7, [r6]
-
- /* Enable the Power Domain Transition Command */
- ldr r6, PTCMD
- ldr r7, [r6]
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Check for Transition Complete(PTSTAT) */
-checkStatClkEn2:
- ldr r6, PTSTAT
- ldr r7, [r6]
- ands r7, r7, $0x01
- bne checkStatClkEn2
-
- /* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkEn2:
- ldr r6, MDSTAT_DDR2
- ldr r7, [r6]
- and r7, r7, $MDSTAT_STATE
- cmp r7, $0x03
- bne checkDDRStatClkEn2
-
- /* DDR Writes and Reads */
- ldr r6, CFGTEST
- mov r3, $0x01
- str r3, [r6]
-
- /*------------------------------------------------------*
- * System PLL Initialization *
- *------------------------------------------------------*/
-
- /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
- mov r2, $0
- ldr r6, PLL1_CTL
- ldr r7, PLL_CLKSRC_MASK
- ldr r8, [r6]
- and r8, r8, r7
- mov r9, r2, lsl $8
- orr r8, r8, r9
- str r8, [r6]
-
- /* Select the PLLEN source */
- ldr r7, PLL_ENSRC_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Bypass the PLL */
- ldr r7, PLL_BYPASS_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
- mov r10, $0x20
-
-WaitLoop:
- subs r10, r10, $1
- bne WaitLoop
-
- /* Reset the PLL */
- ldr r7, PLL_RESET_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Disable the PLL */
- orr r8, r8, $0x10
- str r8, [r6]
-
- /* Power up the PLL */
- ldr r7, PLL_PWRUP_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Enable the PLL from Disable Mode */
- ldr r7, PLL_DISABLE_ENABLE_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Program the PLL Multiplier */
- ldr r6, PLL1_PLLM
- mov r3, $0x15 /* For 594MHz */
- str r3, [r6]
-
- /* Wait for PLL to Reset Properly */
- mov r10, $0xff
-
-ResetLoop:
- subs r10, r10, $1
- bne ResetLoop
-
- /* Bring PLL out of Reset */
- ldr r6, PLL1_CTL
- orr r8, r8, $0x08
- str r8, [r6]
-
- /* Wait for PLL to Lock */
- ldr r10, PLL_LOCK_COUNT
-
-PLL1Lock:
- subs r10, r10, $1
- bne PLL1Lock
-
- /* Enable the PLL */
- orr r8, r8, $0x01
- str r8, [r6]
-
- nop
- nop
- nop
- nop
-
- /*------------------------------------------------------*
- * AEMIF configuration for NOR Flash (double check) *
- *------------------------------------------------------*/
- ldr r0, _PINMUX0
- ldr r1, _DEV_SETTING
- str r1, [r0]
-
- ldr r0, WAITCFG
- ldr r1, WAITCFG_VAL
- ldr r2, [r0]
- orr r2, r2, r1
- str r2, [r0]
-
- ldr r0, ACFG3
- ldr r1, ACFG3_VAL
- ldr r2, [r0]
- and r1, r2, r1
- str r1, [r0]
-
- ldr r0, ACFG4
- ldr r1, ACFG4_VAL
- ldr r2, [r0]
- and r1, r2, r1
- str r1, [r0]
-
- ldr r0, ACFG5
- ldr r1, ACFG5_VAL
- ldr r2, [r0]
- and r1, r2, r1
- str r1, [r0]
-
- /*--------------------------------------*
- * VTP manual Calibration *
- *--------------------------------------*/
- ldr r0, VTPIOCR
- ldr r1, VTP_MMR0
- str r1, [r0]
-
- ldr r0, VTPIOCR
- ldr r1, VTP_MMR1
- str r1, [r0]
-
- /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
- ldr r10, VTP_LOCK_COUNT
-VTPLock:
- subs r10, r10, $1
- bne VTPLock
-
- ldr r6, DFT_ENABLE
- mov r10, $0x01
- str r10, [r6]
-
- ldr r6, DDRVTPR
- ldr r7, [r6]
- mov r8, r7, LSL #32-10
- mov r8, r8, LSR #32-10 /* grab low 10 bits */
- ldr r7, VTP_RECAL
- orr r8, r7, r8
- ldr r7, VTP_EN
- orr r8, r7, r8
- str r8, [r0]
-
-
- /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
- ldr r10, VTP_LOCK_COUNT
-VTP1Lock:
- subs r10, r10, $1
- bne VTP1Lock
-
- ldr r1, [r0]
- ldr r2, VTP_MASK
- and r2, r1, r2
- str r2, [r0]
-
- ldr r6, DFT_ENABLE
- mov r10, $0
- str r10, [r6]
-
- /*
- * Call board-specific lowlevel init.
- * That MUST be present and THAT returns
- * back to arch calling code with "mov pc, lr."
- */
- b dv_board_init
-
-.ltorg
-
-_PINMUX0:
- .word 0x01c40000 /* Device Configuration Registers */
-_PINMUX1:
- .word 0x01c40004 /* Device Configuration Registers */
-
-_DEV_SETTING:
- .word 0x00000c1f
-
-WAITCFG:
- .word 0x01e00004
-WAITCFG_VAL:
- .word 0
-ACFG3:
- .word 0x01e00014
-ACFG3_VAL:
- .word 0x3ffffffd
-ACFG4:
- .word 0x01e00018
-ACFG4_VAL:
- .word 0x3ffffffd
-ACFG5:
- .word 0x01e0001c
-ACFG5_VAL:
- .word 0x3ffffffd
-
-MDCTL_DDR2:
- .word 0x01c41a34
-MDSTAT_DDR2:
- .word 0x01c41834
-
-PTCMD:
- .word 0x01c41120
-PTSTAT:
- .word 0x01c41128
-
-EINT_ENABLE0:
- .word 0x01c48018
-EINT_ENABLE1:
- .word 0x01c4801c
-
-PSC_FLAG_CLEAR:
- .word 0xffffffe0
-PSC_GEM_FLAG_CLEAR:
- .word 0xfffffeff
-
-/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
-DDRCTL:
- .word 0x200000e4
-DDRCTL_VAL:
- .word 0x50006405
-SDREF:
- .word 0x2000000c
-SDREF_VAL:
- .word 0x000005c3
-SDCFG:
- .word 0x20000008
-SDCFG_VAL:
-#ifdef DDR_4BANKS
- .word 0x00178622
-#elif defined DDR_8BANKS
- .word 0x00178632
-#else
-#error "Unknown DDR configuration!!!"
-#endif
-SDTIM0:
- .word 0x20000010
-SDTIM0_VAL_162MHz:
- .word 0x28923211
-SDTIM1:
- .word 0x20000014
-SDTIM1_VAL_162MHz:
- .word 0x0016c722
-VTPIOCR:
- .word 0x200000f0 /* VTP IO Control register */
-DDRVTPR:
- .word 0x01c42030 /* DDR VPTR MMR */
-VTP_MMR0:
- .word 0x201f
-VTP_MMR1:
- .word 0xa01f
-DFT_ENABLE:
- .word 0x01c4004c
-VTP_LOCK_COUNT:
- .word 0x5b0
-VTP_MASK:
- .word 0xffffdfff
-VTP_RECAL:
- .word 0x08000
-VTP_EN:
- .word 0x02000
-CFGTEST:
- .word 0x80010000
-MASK_VAL:
- .word 0x00000fff
-
-/* GEM Power Up & LPSC Control Register */
-MDCTL_GEM:
- .word 0x01c41a9c
-MDSTAT_GEM:
- .word 0x01c4189c
-
-/* For WDT reset chip bug */
-P1394:
- .word 0x01c41a20
-
-PLL_CLKSRC_MASK:
- .word 0xfffffeff /* Mask the Clock Mode bit */
-PLL_ENSRC_MASK:
- .word 0xffffffdf /* Select the PLLEN source */
-PLL_BYPASS_MASK:
- .word 0xfffffffe /* Put the PLL in BYPASS */
-PLL_RESET_MASK:
- .word 0xfffffff7 /* Put the PLL in Reset Mode */
-PLL_PWRUP_MASK:
- .word 0xfffffffd /* PLL Power up Mask Bit */
-PLL_DISABLE_ENABLE_MASK:
- .word 0xffffffef /* Enable the PLL from Disable */
-PLL_LOCK_COUNT:
- .word 0x2000
-
-/* PLL1-SYSTEM PLL MMRs */
-PLL1_CTL:
- .word 0x01c40900
-PLL1_PLLM:
- .word 0x01c40910
-
-/* PLL2-SYSTEM PLL MMRs */
-PLL2_CTL:
- .word 0x01c40d00
-PLL2_PLLM:
- .word 0x01c40d10
-PLL2_DIV1:
- .word 0x01c40d18
-PLL2_DIV2:
- .word 0x01c40d1c
-PLL2_PLLCMD:
- .word 0x01c40d38
-PLL2_PLLSTAT:
- .word 0x01c40d3c
-PLL2_DIV_MASK:
- .word 0xffff7fff
-
-MMARG_BRF0:
- .word 0x01c42010 /* BRF margin mode 0 (R/W)*/
-MMARG_BRF0_VAL:
- .word 0x00444400
-
-DDR2_START_ADDR:
- .word 0x80000000
-DUMMY_VAL:
- .word 0xa55aa55a
-#else /* CONFIG_SOC_DM644X */
- mov pc, lr
-#endif
diff --git a/arch/arm/mach-davinci/spl.c b/arch/arm/mach-davinci/spl.c
index 103639e..be3daa9 100644
--- a/arch/arm/mach-davinci/spl.c
+++ b/arch/arm/mach-davinci/spl.c
@@ -31,9 +31,12 @@
}
#endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */
-void spl_board_init(void)
+void board_init_f(ulong dummy)
{
arch_cpu_init();
+
+ spl_early_init();
+
preloader_console_init();
}
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 37675d0..c469849 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -61,21 +61,6 @@
obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o
endif
-ifneq ($(CONFIG_BOARD_SIZE_LIMIT),)
-BOARD_SIZE_CHECK = \
- @actual=`wc -c $@ | awk '{print $$1}'`; \
- limit=`printf "%d" $(CONFIG_BOARD_SIZE_LIMIT)`; \
- if test $$actual -gt $$limit; then \
- echo "$@ exceeds file size limit:" >&2 ; \
- echo " limit: $$limit bytes" >&2 ; \
- echo " actual: $$actual bytes" >&2 ; \
- echo " excess: $$((actual - limit)) bytes" >&2; \
- exit 1; \
- fi
-else
-BOARD_SIZE_CHECK =
-endif
-
PLUGIN = board/$(BOARDDIR)/plugin
ifeq ($(CONFIG_USE_IMXIMG_PLUGIN),y)
@@ -124,7 +109,6 @@
u-boot.imx: u-boot.bin u-boot.cfgout $(PLUGIN).bin FORCE
$(call if_changed,mkimage)
- $(BOARD_SIZE_CHECK)
ifeq ($(CONFIG_OF_SEPARATE),y)
MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \
diff --git a/arch/arm/mach-omap2/omap3/board.c b/arch/arm/mach-omap2/omap3/board.c
index 2d25fc6..658ef8c 100644
--- a/arch/arm/mach-omap2/omap3/board.c
+++ b/arch/arm/mach-omap2/omap3/board.c
@@ -34,6 +34,8 @@
#endif
#ifdef CONFIG_DM_GPIO
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+/* Manually initialize GPIO banks when OF_CONTROL doesn't */
static const struct omap_gpio_platdata omap34xx_gpio[] = {
{ 0, OMAP34XX_GPIO1_BASE },
{ 1, OMAP34XX_GPIO2_BASE },
@@ -51,7 +53,7 @@
{ "gpio_omap", &omap34xx_gpio[4] },
{ "gpio_omap", &omap34xx_gpio[5] },
};
-
+#endif
#else
static const struct gpio_bank gpio_bank_34xx[6] = {
diff --git a/arch/arm/mach-rockchip/rk_timer.c b/arch/arm/mach-rockchip/rk_timer.c
index f20e64f..29d379f 100644
--- a/arch/arm/mach-rockchip/rk_timer.c
+++ b/arch/arm/mach-rockchip/rk_timer.c
@@ -20,13 +20,6 @@
return timebase_h << 32 | timebase_l;
}
-static uint64_t usec_to_tick(unsigned int usec)
-{
- uint64_t tick = usec;
- tick *= CONFIG_SYS_TIMER_RATE / (1000 * 1000);
- return tick;
-}
-
void rockchip_udelay(unsigned int usec)
{
uint64_t tmp;
diff --git a/board/BuR/common/br_resetc.c b/board/BuR/common/br_resetc.c
index 190f141..c8cc73a 100644
--- a/board/BuR/common/br_resetc.c
+++ b/board/BuR/common/br_resetc.c
@@ -64,6 +64,7 @@
return -1;
}
+ resetc.is_psoc = 1;
rc = dm_i2c_probe(i2cbus,
RSTCTRL_ADDR_PSOC, 0, &resetc.i2cdev);
if (rc) {
diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c
index 1bc2682..a90b7a3 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -62,7 +62,7 @@
return -1;
}
- ret = spi_flash_read(flash, (CFG_MAC_ADDR_OFFSET) + 1, 7, addr);
+ ret = spi_flash_read(flash, (CFG_MAC_ADDR_OFFSET), 6, addr);
if (ret) {
printf("Error - unable to read MAC address from SPI flash.\n");
return -1;
diff --git a/board/davinci/da8xxevm/omapl138_lcdk.c b/board/davinci/da8xxevm/omapl138_lcdk.c
index 2c2f885..fe1bf44 100644
--- a/board/davinci/da8xxevm/omapl138_lcdk.c
+++ b/board/davinci/da8xxevm/omapl138_lcdk.c
@@ -353,7 +353,7 @@
return 0;
}
-#ifndef CONFIG_DM_MMC
+#if !CONFIG_IS_ENABLED(DM_MMC)
#ifdef CONFIG_MMC_DAVINCI
static struct davinci_mmc mmc_sd0 = {
.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
diff --git a/board/keymile/km83xx/MAINTAINERS b/board/keymile/km83xx/MAINTAINERS
index 63b0651..94e0d57 100644
--- a/board/keymile/km83xx/MAINTAINERS
+++ b/board/keymile/km83xx/MAINTAINERS
@@ -1,5 +1,5 @@
KM83XX BOARD
-M: Holger Brunck <holger.brunck@keymile.com>
+M: Holger Brunck <holger.brunck@ch.abb.com>
S: Maintained
F: board/keymile/km83xx/
F: include/configs/km8360.h
diff --git a/board/keymile/km_arm/MAINTAINERS b/board/keymile/km_arm/MAINTAINERS
index 079c803..d156e85 100644
--- a/board/keymile/km_arm/MAINTAINERS
+++ b/board/keymile/km_arm/MAINTAINERS
@@ -1,5 +1,5 @@
KM_ARM BOARD
-M: Valentin Longchamp <valentin.longchamp@keymile.com>
+M: Valentin Longchamp <valentin.longchamp@ch.abb.com>
S: Maintained
F: board/keymile/km_arm/
F: include/configs/km_kirkwood.h
diff --git a/board/keymile/kmp204x/MAINTAINERS b/board/keymile/kmp204x/MAINTAINERS
index 93b6bad..c5170c9 100644
--- a/board/keymile/kmp204x/MAINTAINERS
+++ b/board/keymile/kmp204x/MAINTAINERS
@@ -1,5 +1,5 @@
KMP204X BOARD
-M: Valentin Longchamp <valentin.longchamp@keymile.com>
+M: Valentin Longchamp <valentin.longchamp@ch.abb.com>
S: Maintained
F: board/keymile/kmp204x/
F: include/configs/kmp204x.h
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index 37a5997..6e1ede3 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -93,6 +93,10 @@
};
static struct module_pin_mux mmc1_pin_mux[] = {
+ {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
+ {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
+ {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
+ {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
diff --git a/cmd/efidebug.c b/cmd/efidebug.c
index c4ac9dd..e657226 100644
--- a/cmd/efidebug.c
+++ b/cmd/efidebug.c
@@ -558,6 +558,7 @@
}
ret = EFI_CALL(RT->set_variable(var_name16, &guid,
+ EFI_VARIABLE_NON_VOLATILE |
EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS,
size, data));
@@ -909,6 +910,7 @@
guid = efi_global_variable_guid;
size = sizeof(u16);
ret = EFI_CALL(RT->set_variable(L"BootNext", &guid,
+ EFI_VARIABLE_NON_VOLATILE |
EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS,
size, &bootnext));
@@ -964,6 +966,7 @@
guid = efi_global_variable_guid;
ret = EFI_CALL(RT->set_variable(L"BootOrder", &guid,
+ EFI_VARIABLE_NON_VOLATILE |
EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS,
size, bootorder));
diff --git a/cmd/led.c b/cmd/led.c
index fc07ca9..403abbc 100644
--- a/cmd/led.c
+++ b/cmd/led.c
@@ -85,7 +85,7 @@
if (argc < 2)
return CMD_RET_USAGE;
led_label = argv[1];
- if (*led_label == 'l')
+ if (strncmp(led_label, "list", 4) == 0)
return list_leds();
cmd = argc > 2 ? get_led_cmd(argv[2]) : LEDST_COUNT;
@@ -137,6 +137,6 @@
led, 4, 1, do_led,
"manage LEDs",
"<led_label> on|off|toggle" BLINK "\tChange LED state\n"
- "led [<led_label>\tGet LED state\n"
+ "led [<led_label>]\tGet LED state\n"
"led list\t\tshow a list of LEDs"
);
diff --git a/cmd/nvedit.c b/cmd/nvedit.c
index 24a6cf7..52c242b 100644
--- a/cmd/nvedit.c
+++ b/cmd/nvedit.c
@@ -1344,8 +1344,9 @@
setenv, CONFIG_SYS_MAXARGS, 0, do_env_set,
"set environment variables",
#if defined(CONFIG_CMD_NVEDIT_EFI)
- "-e name [value ...]\n"
+ "-e [-nv] name [value ...]\n"
" - set UEFI variable 'name' to 'value' ...'\n"
+ " 'nv' option makes the variable non-volatile\n"
" - delete UEFI variable 'name' if 'value' not specified\n"
#endif
"setenv [-f] name value ...\n"
diff --git a/cmd/nvedit_efi.c b/cmd/nvedit_efi.c
index ff8eaa1..60a8ac8 100644
--- a/cmd/nvedit_efi.c
+++ b/cmd/nvedit_efi.c
@@ -349,6 +349,7 @@
u16 *var_name16 = NULL, *p;
size_t len;
efi_guid_t guid;
+ u32 attributes;
efi_status_t ret;
if (argc == 1)
@@ -362,6 +363,16 @@
return CMD_RET_FAILURE;
}
+ attributes = EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_RUNTIME_ACCESS;
+ if (!strcmp(argv[1], "-nv")) {
+ attributes |= EFI_VARIABLE_NON_VOLATILE;
+ argc--;
+ argv++;
+ if (argc == 1)
+ return CMD_RET_SUCCESS;
+ }
+
var_name = argv[1];
if (argc == 2) {
/* delete */
@@ -391,9 +402,7 @@
utf8_utf16_strncpy(&p, var_name, len + 1);
guid = efi_global_variable_guid;
- ret = EFI_CALL(efi_set_variable(var_name16, &guid,
- EFI_VARIABLE_BOOTSERVICE_ACCESS |
- EFI_VARIABLE_RUNTIME_ACCESS,
+ ret = EFI_CALL(efi_set_variable(var_name16, &guid, attributes,
size, value));
if (ret == EFI_SUCCESS) {
ret = CMD_RET_SUCCESS;
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index c7cd344..ac2f470 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -25,6 +25,42 @@
supports MMC, NAND and YMODEM and other methods loading of U-Boot
and the Linux Kernel. If unsure, say Y.
+config SPL_SIZE_LIMIT
+ int "Maximum size of SPL image"
+ depends on SPL
+ default 0
+ help
+ Specifies the maximum length of the U-Boot SPL image.
+ If this value is zero, it is ignored.
+
+config SPL_SIZE_LIMIT_SUBTRACT_GD
+ bool "SPL image size check: provide space for global data"
+ depends on SPL_SIZE_LIMIT > 0
+ help
+ If enabled, aligned size of global data is reserved in
+ SPL_SIZE_LIMIT check to ensure such an image does not overflow SRAM
+ if SPL_SIZE_LIMIT describes the size of SRAM available for SPL when
+ pre-reloc global data is put into this SRAM, too.
+
+config SPL_SIZE_LIMIT_SUBTRACT_MALLOC
+ bool "SPL image size check: provide space for malloc() pool before relocation"
+ depends on SPL_SIZE_LIMIT > 0
+ help
+ If enabled, SPL_SYS_MALLOC_F_LEN is reserved in SPL_SIZE_LIMIT check
+ to ensure such an image does not overflow SRAM if SPL_SIZE_LIMIT
+ describes the size of SRAM available for SPL when pre-reloc malloc
+ pool is put into this SRAM, too.
+
+config SPL_SIZE_LIMIT_PROVIDE_STACK
+ hex "SPL image size check: provide stack space before relocation"
+ depends on SPL_SIZE_LIMIT > 0
+ default 0
+ help
+ If set, this size is reserved in SPL_SIZE_LIMIT check to ensure such
+ an image does not overflow SRAM if SPL_SIZE_LIMIT describes the size
+ of SRAM available for SPL when the stack required before reolcation
+ uses this SRAM, too.
+
config HANDOFF
bool "Pass hand-off information from SPL to U-Boot proper"
depends on BLOBLIST
diff --git a/configs/da850_am18xxevm_defconfig b/configs/da850_am18xxevm_defconfig
index f098222..7ecdc36 100644
--- a/configs/da850_am18xxevm_defconfig
+++ b/configs/da850_am18xxevm_defconfig
@@ -20,7 +20,6 @@
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_TEXT_BASE=0x80000000
-CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig
index 8c16d5c..c095058 100644
--- a/configs/da850evm_defconfig
+++ b/configs/da850evm_defconfig
@@ -21,7 +21,6 @@
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_TEXT_BASE=0x80000000
-CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_SPI_LOAD=y
diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig
index b8eac0e..7271016 100644
--- a/configs/da850evm_nand_defconfig
+++ b/configs/da850evm_nand_defconfig
@@ -19,7 +19,6 @@
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_TEXT_BASE=0x80000000
-CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_NAND_SUPPORT=y
diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index e431418..48f251e 100644
--- a/configs/omapl138_lcdk_defconfig
+++ b/configs/omapl138_lcdk_defconfig
@@ -18,7 +18,6 @@
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_TEXT_BASE=0x80000000
-CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xb5
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
index 07e0d45..4b48689 100644
--- a/configs/tinker-rk3288_defconfig
+++ b/configs/tinker-rk3288_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
+CONFIG_SPL_SIZE_LIMIT=30720
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_TARGET_TINKER_RK3288=y
CONFIG_NR_DRAM_BANKS=1
diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h
index 1e239ec..36ca3b2 100644
--- a/include/configs/legoev3.h
+++ b/include/configs/legoev3.h
@@ -22,6 +22,7 @@
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SKIP_LOWLEVEL_INIT
/*
* Memory Info
diff --git a/include/time.h b/include/time.h
index 9fd0d73..1e9b369 100644
--- a/include/time.h
+++ b/include/time.h
@@ -4,6 +4,7 @@
#define _TIME_H
#include <linux/typecheck.h>
+#include <linux/types.h>
unsigned long get_timer(unsigned long base);
@@ -21,6 +22,14 @@
*/
void timer_test_add_offset(unsigned long offset);
+/**
+ * usec_to_tick() - convert microseconds to clock ticks
+ *
+ * @usec: duration in microseconds
+ * Return: duration in clock ticks
+ */
+uint64_t usec_to_tick(unsigned long usec);
+
/*
* These inlines deal with timer wrapping correctly. You are
* strongly encouraged to use them
diff --git a/include/uuid.h b/include/uuid.h
index 124bbce..abcc325 100644
--- a/include/uuid.h
+++ b/include/uuid.h
@@ -6,6 +6,8 @@
#ifndef __UUID_H__
#define __UUID_H__
+#include <linux/bitops.h>
+
/* This is structure is in big-endian */
struct uuid {
unsigned int time_low;
@@ -16,10 +18,10 @@
unsigned char node[6];
} __packed;
-enum {
- UUID_STR_FORMAT_STD,
- UUID_STR_FORMAT_GUID
-};
+/* Bits of a bitmask specifying the output format for GUIDs */
+#define UUID_STR_FORMAT_STD 0
+#define UUID_STR_FORMAT_GUID BIT(0)
+#define UUID_STR_UPPER_CASE BIT(1)
#define UUID_STR_LEN 36
#define UUID_BIN_LEN sizeof(struct uuid)
diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
index 4379142..b2102c5 100644
--- a/lib/efi_loader/efi_bootmgr.c
+++ b/lib/efi_loader/efi_bootmgr.c
@@ -210,7 +210,8 @@
ret = EFI_CALL(efi_set_variable(
L"BootNext",
(efi_guid_t *)&efi_global_variable_guid,
- 0, 0, &bootnext));
+ EFI_VARIABLE_NON_VOLATILE, 0,
+ &bootnext));
/* load BootNext */
if (ret == EFI_SUCCESS) {
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index 5c6bc69..7d1d6e9 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -1153,11 +1153,15 @@
++count;
}
}
+ *number_of_drivers = 0;
+ if (!count) {
+ *driver_handle_buffer = NULL;
+ return EFI_SUCCESS;
+ }
/*
* Create buffer. In case of duplicate driver assignments the buffer
* will be too large. But that does not harm.
*/
- *number_of_drivers = 0;
*driver_handle_buffer = calloc(count, sizeof(efi_handle_t));
if (!*driver_handle_buffer)
return EFI_OUT_OF_RESOURCES;
@@ -1213,7 +1217,8 @@
&driver_handle_buffer);
if (ret != EFI_SUCCESS)
return ret;
-
+ if (!number_of_drivers)
+ return EFI_SUCCESS;
ret = EFI_NOT_FOUND;
while (number_of_drivers) {
r = EFI_CALL(efi_disconnect_controller(
@@ -1985,8 +1990,14 @@
*/
static efi_status_t EFIAPI efi_stall(unsigned long microseconds)
{
+ u64 end_tick;
+
EFI_ENTRY("%ld", microseconds);
- udelay(microseconds);
+
+ end_tick = get_ticks() + usec_to_tick(microseconds);
+ while (get_ticks() < end_tick)
+ efi_timer_check();
+
return EFI_EXIT(EFI_SUCCESS);
}
@@ -2868,12 +2879,46 @@
* @image_obj: handle of the loaded image
* @loaded_image_protocol: loaded image protocol
*/
-static void efi_delete_image(struct efi_loaded_image_obj *image_obj,
- struct efi_loaded_image *loaded_image_protocol)
+static efi_status_t efi_delete_image
+ (struct efi_loaded_image_obj *image_obj,
+ struct efi_loaded_image *loaded_image_protocol)
{
+ struct efi_object *efiobj;
+ efi_status_t r, ret = EFI_SUCCESS;
+
+close_next:
+ list_for_each_entry(efiobj, &efi_obj_list, link) {
+ struct efi_handler *protocol;
+
+ list_for_each_entry(protocol, &efiobj->protocols, link) {
+ struct efi_open_protocol_info_item *info;
+
+ list_for_each_entry(info, &protocol->open_infos, link) {
+ if (info->info.agent_handle !=
+ (efi_handle_t)image_obj)
+ continue;
+ r = EFI_CALL(efi_close_protocol
+ (efiobj, protocol->guid,
+ info->info.agent_handle,
+ info->info.controller_handle
+ ));
+ if (r != EFI_SUCCESS)
+ ret = r;
+ /*
+ * Closing protocols may results in further
+ * items being deleted. To play it safe loop
+ * over all elements again.
+ */
+ goto close_next;
+ }
+ }
+ }
+
efi_free_pages((uintptr_t)loaded_image_protocol->image_base,
efi_size_in_pages(loaded_image_protocol->image_size));
efi_delete_handle(&image_obj->header);
+
+ return ret;
}
/**
diff --git a/lib/efi_loader/efi_console.c b/lib/efi_loader/efi_console.c
index b2cb18e..3b7578f 100644
--- a/lib/efi_loader/efi_console.c
+++ b/lib/efi_loader/efi_console.c
@@ -430,6 +430,7 @@
EFI_ENTRY("%p, %d", this, enable);
printf(ESC"[?25%c", enable ? 'h' : 'l');
+ efi_con_mode.cursor_visible = !!enable;
return EFI_EXIT(EFI_SUCCESS);
}
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index 76dcaa4..386cf92 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -230,6 +230,7 @@
struct efi_mem_list *newlist;
bool carve_again;
uint64_t carved_pages = 0;
+ struct efi_event *evt;
EFI_PRINT("%s: 0x%llx 0x%llx %d %s\n", __func__,
start, pages, memory_type, overlap_only_ram ? "yes" : "no");
@@ -315,6 +316,16 @@
/* And make sure memory is listed in descending order */
efi_mem_sort();
+ /* Notify that the memory map was changed */
+ list_for_each_entry(evt, &efi_events, link) {
+ if (evt->group &&
+ !guidcmp(evt->group,
+ &efi_guid_event_group_memory_map_change)) {
+ efi_signal_event(evt, false);
+ break;
+ }
+ }
+
return start;
}
diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
index 50bc105..e560531 100644
--- a/lib/efi_loader/efi_variable.c
+++ b/lib/efi_loader/efi_variable.c
@@ -125,6 +125,8 @@
if ((s = prefix(str, "ro"))) {
attr |= READ_ONLY;
+ } else if ((s = prefix(str, "nv"))) {
+ attr |= EFI_VARIABLE_NON_VOLATILE;
} else if ((s = prefix(str, "boot"))) {
attr |= EFI_VARIABLE_BOOTSERVICE_ACCESS;
} else if ((s = prefix(str, "run"))) {
@@ -468,7 +470,7 @@
}
}
- val = malloc(2 * data_size + strlen("{ro,run,boot}(blob)") + 1);
+ val = malloc(2 * data_size + strlen("{ro,run,boot,nv}(blob)") + 1);
if (!val) {
ret = EFI_OUT_OF_RESOURCES;
goto out;
@@ -480,12 +482,16 @@
* store attributes
* TODO: several attributes are not supported
*/
- attributes &= (EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS);
+ attributes &= (EFI_VARIABLE_NON_VOLATILE |
+ EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_RUNTIME_ACCESS);
s += sprintf(s, "{");
while (attributes) {
u32 attr = 1 << (ffs(attributes) - 1);
- if (attr == EFI_VARIABLE_BOOTSERVICE_ACCESS)
+ if (attr == EFI_VARIABLE_NON_VOLATILE)
+ s += sprintf(s, "nv");
+ else if (attr == EFI_VARIABLE_BOOTSERVICE_ACCESS)
s += sprintf(s, "boot");
else if (attr == EFI_VARIABLE_RUNTIME_ACCESS)
s += sprintf(s, "run");
diff --git a/lib/time.c b/lib/time.c
index 9c55da6..f5751ab 100644
--- a/lib/time.c
+++ b/lib/time.c
@@ -139,7 +139,7 @@
return tick_to_time(get_ticks() * 1000);
}
-static uint64_t usec_to_tick(unsigned long usec)
+uint64_t usec_to_tick(unsigned long usec)
{
uint64_t tick = usec;
tick *= get_tbclk();
diff --git a/lib/uuid.c b/lib/uuid.c
index 2d4d6ef7..7d7a274 100644
--- a/lib/uuid.c
+++ b/lib/uuid.c
@@ -187,9 +187,10 @@
/*
* uuid_bin_to_str() - convert big endian binary data to string UUID or GUID.
*
- * @param uuid_bin - pointer to binary data of UUID (big endian) [16B]
- * @param uuid_str - pointer to allocated array for output string [37B]
- * @str_format - UUID string format: 0 - UUID; 1 - GUID
+ * @param uuid_bin: pointer to binary data of UUID (big endian) [16B]
+ * @param uuid_str: pointer to allocated array for output string [37B]
+ * @str_format: bit 0: 0 - UUID; 1 - GUID
+ * bit 1: 0 - lower case; 2 - upper case
*/
void uuid_bin_to_str(unsigned char *uuid_bin, char *uuid_str, int str_format)
{
@@ -198,6 +199,7 @@
const u8 guid_char_order[UUID_BIN_LEN] = {3, 2, 1, 0, 5, 4, 7, 6, 8,
9, 10, 11, 12, 13, 14, 15};
const u8 *char_order;
+ const char *format;
int i;
/*
@@ -205,13 +207,17 @@
* 4B-2B-2B-2B-6B
* be be be be be
*/
- if (str_format == UUID_STR_FORMAT_STD)
+ if (str_format & UUID_STR_FORMAT_GUID)
+ char_order = guid_char_order;
+ else
char_order = uuid_char_order;
+ if (str_format & UUID_STR_UPPER_CASE)
+ format = "%02X";
else
- char_order = guid_char_order;
+ format = "%02x";
for (i = 0; i < 16; i++) {
- sprintf(uuid_str, "%02x", uuid_bin[char_order[i]]);
+ sprintf(uuid_str, format, uuid_bin[char_order[i]]);
uuid_str += 2;
switch (i) {
case 3:
diff --git a/lib/vsprintf.c b/lib/vsprintf.c
index 8bbbd48..425f2f5 100644
--- a/lib/vsprintf.c
+++ b/lib/vsprintf.c
@@ -383,29 +383,31 @@
#ifdef CONFIG_LIB_UUID
/*
- * This works (roughly) the same way as linux's, but we currently always
- * print lower-case (ie. we just keep %pUB and %pUL for compat with linux),
- * mostly just because that is what uuid_bin_to_str() supports.
+ * This works (roughly) the same way as Linux's.
*
* %pUb: 01020304-0506-0708-090a-0b0c0d0e0f10
+ * %pUB: 01020304-0506-0708-090A-0B0C0D0E0F10
* %pUl: 04030201-0605-0807-090a-0b0c0d0e0f10
+ * %pUL: 04030201-0605-0807-090A-0B0C0D0E0F10
*/
static char *uuid_string(char *buf, char *end, u8 *addr, int field_width,
int precision, int flags, const char *fmt)
{
char uuid[UUID_STR_LEN + 1];
- int str_format = UUID_STR_FORMAT_STD;
+ int str_format;
switch (*(++fmt)) {
case 'L':
+ str_format = UUID_STR_FORMAT_GUID | UUID_STR_UPPER_CASE;
+ break;
case 'l':
str_format = UUID_STR_FORMAT_GUID;
break;
case 'B':
- case 'b':
- /* this is the default */
+ str_format = UUID_STR_FORMAT_STD | UUID_STR_UPPER_CASE;
break;
default:
+ str_format = UUID_STR_FORMAT_STD;
break;
}
diff --git a/test/print_ut.c b/test/print_ut.c
index 0bc548d..a3b9974 100644
--- a/test/print_ut.c
+++ b/test/print_ut.c
@@ -15,6 +15,26 @@
#define FAKE_BUILD_TAG "jenkins-u-boot-denx_uboot_dm-master-build-aarch64" \
"and a lot more text to come"
+/* Test printing GUIDs */
+static void guid_ut_print(void)
+{
+#if CONFIG_IS_ENABLED(LIB_UUID)
+ unsigned char guid[16] = {
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
+ };
+ char str[40];
+
+ sprintf(str, "%pUb", guid);
+ assert(!strcmp("01020304-0506-0708-090a-0b0c0d0e0f10", str));
+ sprintf(str, "%pUB", guid);
+ assert(!strcmp("01020304-0506-0708-090A-0B0C0D0E0F10", str));
+ sprintf(str, "%pUl", guid);
+ assert(!strcmp("04030201-0605-0807-090a-0b0c0d0e0f10", str));
+ sprintf(str, "%pUL", guid);
+ assert(!strcmp("04030201-0605-0807-090A-0B0C0D0E0F10", str));
+#endif
+}
+
/* Test efi_loader specific printing */
static void efi_ut_print(void)
{
@@ -117,6 +137,9 @@
/* Test efi_loader specific printing */
efi_ut_print();
+ /* Test printing GUIDs */
+ guid_ut_print();
+
printf("%s: Everything went swimmingly\n", __func__);
return 0;
}
diff --git a/tools/Makefile b/tools/Makefile
index e2f572c..33e90a8 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -199,6 +199,10 @@
hostprogs-y += fdtgrep
fdtgrep-objs += $(LIBFDT_OBJS) fdtgrep.o
+ifneq ($(TOOLS_ONLY),y)
+hostprogs-y += spl_size_limit
+endif
+
hostprogs-$(CONFIG_MIPS) += mips-relocs
# We build some files with extra pedantic flags to try to minimize things
diff --git a/tools/spl_size_limit.c b/tools/spl_size_limit.c
new file mode 100644
index 0000000..98ff491
--- /dev/null
+++ b/tools/spl_size_limit.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019, Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
+ *
+ * This tool helps to return the size available for SPL image during build
+ */
+
+#include <generated/autoconf.h>
+#include <generated/generic-asm-offsets.h>
+
+int main(int argc, char *argv[])
+{
+ int spl_size_limit = 0;
+
+#ifdef CONFIG_SPL_SIZE_LIMIT
+ spl_size_limit = CONFIG_SPL_SIZE_LIMIT;
+#ifdef CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD
+ spl_size_limit -= GENERATED_GBL_DATA_SIZE;
+#endif
+#ifdef CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC
+ spl_size_limit -= CONFIG_SPL_SYS_MALLOC_F_LEN;
+#endif
+#ifdef CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK
+ spl_size_limit -= CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK;
+#endif
+#endif
+
+ printf("%d", spl_size_limit);
+ return 0;
+}