Gitiles
Code Review
Sign In
git01.mediatek.com
/
filogic
/
uboot
/
ca68c296ea31f48b801aeaa5c3863894a7128894
/
.
/
doc
/
README.fsl-esdhc
blob: b70f271d1a473d283a0e9ae632e6901b9e65d455 [
file
] [
log
] [
blame
]
CONFIG_SYS_FSL_ESDHC_LE means ESDHC IP
is
in
little
-
endian mode
.
CONFIG_SYS_FSL_ESDHC_BE means ESDHC IP
is
in
big
-
endian mode
.
Accessing
ESDHC registers can be determined
by
ESDHC IP
's endian
mode or processor'
s endian mode
.