rk3399: add basic soc driver
This patch add driver for:
- clock driver including set_rate for cpu, mmc, vop, I2C.
- sysreset driver
- grf syscon driver
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
new file mode 100644
index 0000000..c919f47
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CRU_RK3399_H_
+#define __ASM_ARCH_CRU_RK3399_H_
+
+#include <common.h>
+
+struct rk3399_pmucru {
+ u32 ppll_con[6];
+ u32 reserved[0x1a];
+ u32 pmucru_clksel[6];
+ u32 pmucru_clkfrac_con[2];
+ u32 reserved2[0x18];
+ u32 pmucru_clkgate_con[3];
+ u32 reserved3;
+ u32 pmucru_softrst_con[2];
+ u32 reserved4[2];
+ u32 pmucru_rstnhold_con[2];
+ u32 reserved5[2];
+ u32 pmucru_gatedis_con[2];
+};
+check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134);
+
+struct rk3399_cru {
+ u32 apll_l_con[6];
+ u32 reserved[2];
+ u32 apll_b_con[6];
+ u32 reserved1[2];
+ u32 dpll_con[6];
+ u32 reserved2[2];
+ u32 cpll_con[6];
+ u32 reserved3[2];
+ u32 gpll_con[6];
+ u32 reserved4[2];
+ u32 npll_con[6];
+ u32 reserved5[2];
+ u32 vpll_con[6];
+ u32 reserved6[0x0a];
+ u32 clksel_con[108];
+ u32 reserved7[0x14];
+ u32 clkgate_con[35];
+ u32 reserved8[0x1d];
+ u32 softrst_con[21];
+ u32 reserved9[0x2b];
+ u32 glb_srst_fst_value;
+ u32 glb_srst_snd_value;
+ u32 glb_cnt_th;
+ u32 misc_con;
+ u32 glb_rst_con;
+ u32 glb_rst_st;
+ u32 reserved10[0x1a];
+ u32 sdmmc_con[2];
+ u32 sdio0_con[2];
+ u32 sdio1_con[2];
+};
+check_member(rk3399_cru, sdio1_con[1], 0x594);
+#define MHz 1000000
+#define KHz 1000
+#define OSC_HZ (24*MHz)
+#define APLL_HZ (600*MHz)
+#define GPLL_HZ (594*MHz)
+#define CPLL_HZ (384*MHz)
+#define PPLL_HZ (594*MHz)
+
+#define PMU_PCLK_HZ (99*MHz)
+
+#define ACLKM_CORE_HZ (300*MHz)
+#define ATCLK_CORE_HZ (300*MHz)
+#define PCLK_DBG_HZ (100*MHz)
+
+#define PERIHP_ACLK_HZ (148500*KHz)
+#define PERIHP_HCLK_HZ (148500*KHz)
+#define PERIHP_PCLK_HZ (37125*KHz)
+
+#define PERILP0_ACLK_HZ (99000*KHz)
+#define PERILP0_HCLK_HZ (99000*KHz)
+#define PERILP0_PCLK_HZ (49500*KHz)
+
+#define PERILP1_HCLK_HZ (99000*KHz)
+#define PERILP1_PCLK_HZ (49500*KHz)
+
+#define PWM_CLOCK_HZ PMU_PCLK_HZ
+
+enum apll_l_frequencies {
+ APLL_L_1600_MHZ,
+ APLL_L_600_MHZ,
+};
+
+#endif /* __ASM_ARCH_CRU_RK3399_H_ */
diff --git a/arch/arm/mach-rockchip/rk3399/Makefile b/arch/arm/mach-rockchip/rk3399/Makefile
index 3f219ac..3ca2028 100644
--- a/arch/arm/mach-rockchip/rk3399/Makefile
+++ b/arch/arm/mach-rockchip/rk3399/Makefile
@@ -5,3 +5,5 @@
#
obj-y += rk3399.o
+obj-y += reset_rk3399.o
+obj-y += syscon_rk3399.o
diff --git a/arch/arm/mach-rockchip/rk3399/reset_rk3399.c b/arch/arm/mach-rockchip/rk3399/reset_rk3399.c
new file mode 100644
index 0000000..9a55546
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3399/reset_rk3399.c
@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3399.h>
+#include <asm/arch/hardware.h>
+#include <linux/err.h>
+
+int rk3399_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct rk3399_cru *cru = rockchip_get_cru();
+
+ if (IS_ERR(cru))
+ return PTR_ERR(cru);
+ switch (type) {
+ case SYSRESET_WARM:
+ writel(0xeca8, &cru->glb_srst_snd_value);
+ break;
+ case SYSRESET_COLD:
+ writel(0xfdb9, &cru->glb_srst_fst_value);
+ break;
+ default:
+ return -EPROTONOSUPPORT;
+ }
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops rk3399_sysreset = {
+ .request = rk3399_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_rk3399) = {
+ .name = "rk3399_sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops = &rk3399_sysreset,
+};
diff --git a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c
new file mode 100644
index 0000000..2d81c55
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c
@@ -0,0 +1,20 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+
+static const struct udevice_id rk3399_syscon_ids[] = {
+ { .compatible = "rockchip,rk3399-grf", .data = ROCKCHIP_SYSCON_GRF },
+};
+
+U_BOOT_DRIVER(syscon_rk3399) = {
+ .name = "rk3399_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3399_syscon_ids,
+};