tree 99a4b5a26fa904d1852b9662f9643add3ffa806e
parent 4e07e33e49db0141689aeb820e754f1f0db76191
author Rupjyoti Sarmah <rsarmah@appliedmicro.com> 1269429722 +0530
committer Stefan Roese <sr@denx.de> 1269437221 +0100

ppc4xx fix unstable 440EPx bootstrap options

440EPx fixed bootstrap options A, B, D, and E sets PLL FWDVA to a value = 1.
This results in the PLLOUTB being greater than the CPU clock frequency
resulting unstable 440EPx operation resulting in various software hang
conditions.

This patch reprograms the FWDVA satisfying the requirement of setting FWDVB
to a value greater than 1 while using one of the four deafult bootstrap options.

Signed-off-by: Rupjyoti Sarmah <rsarmah@amcc.com>
Acked-by : Victor Gallardo <vgallardo@appliedmicro.com>
Signed-off-by: Stefan Roese <sr@denx.de>