tree 9b3ef41d80f6bdc93586996f987597035fe2d0ea
parent a358789174d1a7ab0b5e4a82d765cc28f4f8ae4a
author Yu Chien Peter Lin <peterlin@andestech.com> 1688469200 +0800
committer Leo Yu-Chi Liang <ycliang@andestech.com> 1688635688 +0800

riscv: andes_plicsw: Fix IPI during OpenSBI invocation

On some AE350 boards, we need to explicitly initialize the priority
registers to a non-zero value so the boot hart can instruct secondary
harts to jump to OpenSBI.

This patch also updates the information about PLICSW.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>