commit c943c53d0a5b8697cad399a9bf56549b37799c3a
author Lei Wen <[leiwen@marvell.com]> Tue Nov 01 16:25:56 2011 +0530
committer Albert ARIBAUD <albert.u.boot@aribaud.net> Thu Nov 03 22:56:22 2011 +0100
tree b591517ea82849ff240017312972bfc0daf3fe42
parent 41ba02e88b0564ef16c01bc0d987860b27f342df

armada100: define CONFIG_SYS_CACHELINE_SIZE

By default, on Armada100 SoC DCache Lnd ICache line
lengths are 32 bytes long

Signed-off-by: Lei Wen <leiwen@marvell.com>

arch/arm/include/asm/arch-armada100/config.h

diff --git a/arch/arm/include/asm/arch-armada100/config.h b/arch/arm/include/asm/arch-armada100/config.h
index d2094e5..637f313 100644
--- a/arch/arm/include/asm/arch-armada100/config.h
+++ b/arch/arm/include/asm/arch-armada100/config.h
@@ -33,6 +33,8 @@
 
 #include <asm/arch/armada100.h>
 #define CONFIG_ARM926EJS	1	/* Basic Architecture */
+/* default Dcache Line length for armada100 */
+#define CONFIG_SYS_CACHELINE_SIZE       32
 
 #define CONFIG_SYS_TCLK		(14745600)	/* NS16550 clk config */
 #define CONFIG_SYS_HZ_CLOCK	(3250000)	/* Timer Freq. 3.25MHZ */