ARM: tegra: clock: support get and set rate for simple PLL
Simple PLL clocks like PLLD2 were omitted since they do not share common
4 register structure with main clocks. Such clocks are containd in simple
PLL group. Only clock_start_pll function supported them. This patch expands
this support on clock_set_rate and clock_get_rate which should make
simple PLL clocks equal to main PLL clocks.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c
index ca9549a..ed8b6d9 100644
--- a/arch/arm/mach-tegra/tegra124/clock.c
+++ b/arch/arm/mach-tegra/tegra124/clock.c
@@ -1189,10 +1189,16 @@
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- if (clkid == CLOCK_ID_DP)
+ switch (clkid) {
+ case CLOCK_ID_XCPU:
+ case CLOCK_ID_EPCI:
+ case CLOCK_ID_SFROM32KHZ:
+ return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE];
+ case CLOCK_ID_DP:
return &clkrst->plldp;
-
- return NULL;
+ default:
+ return NULL;
+ }
}
struct periph_clk_init periph_clk_init_table[] = {