| commit | 6a9d516f934856e9a73074568359fef173093e17 | [log] [tgz] |
|---|---|---|
| author | Wang Huan <b18965@freescale.com> | Fri Sep 05 13:52:39 2014 +0800 |
| committer | York Sun <yorksun@freescale.com> | Mon Sep 08 10:30:33 2014 -0700 |
| tree | 7da71ffa7005b4a59dd53aeb27e7df17be952c51 | |
| parent | 32cc59136c924bf2549120d89aca1b15cbc8d3cb [diff] |
esdhc: Add CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE macros For LS102xA, the processor is in little-endian mode, while esdhc IP is in big-endian mode. CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE are added. So accessing ESDHC registers can be determined by ESDHC IP's endian mode. Signed-off-by: Alison Wang <alison.wang@freescale.com>