| commit | 9ae964b6e64261a3bacda5545c9005cb04967f42 | [log] [tgz] |
|---|---|---|
| author | Yu Chien Peter Lin <peterlin@andestech.com> | Thu Apr 11 17:29:45 2024 +0800 |
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | Wed May 01 22:40:00 2024 +0800 |
| tree | 445bc82a325414cb4597c6ab1f4f0c775aad3a1f | |
| parent | 6a1e1bef301a56eac241b01fe6ee70ce0f03f0fa [diff] |
riscv: andesv5: Set default cache line size to 64-bytes The instruction and data cache line sizes of Andes core are 64-byte. Select SYS_CACHE_SHIFT_6 for RISCV_NDS so the SYS_CACHELINE_SIZE is enabled with a default value. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>