Merge patch series "Qualcomm: cleanup OF_LIVE fixup and fix RB1/2"
Caleb Connolly <caleb.connolly@linaro.org> says:
Introduce a new event to signal that the live tree has been built,
allowing boards to perform fixups on the tree before devices are bound.
Crucially this allows for devices to be enabled or disabled, but also
allows for properties that are parsed during the bind stage to be
modified (such as dr_mode for dwc3).
With this in place, mach-snapdragon is switched over to use the event
and some hacky U-Boot specific DT overrides (which had to be undone
prior to booting an image) are removed in favour of fixing up the
livetree (which is not passed on to further boot stages).
Finally, some minor fixes are made for the QCM2290 RB1 board, the sdcard
is enabled and it now uses USB host mode in U-Boot like it's bigger
sibling the RB2.
Link: https://lore.kernel.org/r/20250411-livetree-fixup-v2-0-1236823377bb@linaro.org
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index 7a33d40..5e1938b 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -2,7 +2,7 @@
windows_vm: windows-2022
ubuntu_vm: ubuntu-24.04
macos_vm: macOS-14
- ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20240911.1-08Dec2024
+ ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20250404-29Apr2025
# Add '-u 0' options for Azure pipelines, otherwise we get "permission
# denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
# since our $(ci_runner_image) user is not root.
@@ -90,7 +90,7 @@
steps:
- script: |
set -e
- virtualenv -p /usr/bin/python3 /tmp/venvhtml
+ python3 -m venv /tmp/venvhtml
. /tmp/venvhtml/bin/activate
pip install -r doc/sphinx/requirements.txt
make htmldocs KDOC_WERROR=1
@@ -132,7 +132,7 @@
git config --global user.email bmeng.cn@gmail.com
git config --global --add safe.directory $(work_dir)
export USER=azure
- virtualenv -p /usr/bin/python3 /tmp/venv
+ python3 -m venv /tmp/venv
. /tmp/venv/bin/activate
pip install -r test/py/requirements.txt \
-r tools/binman/requirements.txt \
@@ -144,7 +144,11 @@
export PATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}
./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w --board tools-only
set -ex
- ./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test
+ export TOOLPATH="--toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools --toolpath /opt/coreboot"
+ ./tools/binman/binman ${TOOLPATH} tool -f missing
+ ./tools/binman/binman ${TOOLPATH} test
+ # Avoid "Permission denied: 'cov'" error by using a temporary file
+ COVERAGE_FILE=/tmp/.coverage ./tools/binman/binman ${TOOLPATH} test -T
./tools/buildman/buildman -t
./tools/dtoc/dtoc -t
./tools/patman/patman test
@@ -166,7 +170,7 @@
- script: |
git config --global --add safe.directory $(work_dir)
export USER=azure
- virtualenv -p /usr/bin/python3 /tmp/venv
+ python3 -m venv /tmp/venv
. /tmp/venv/bin/activate
pip install -r test/py/requirements.txt \
-r tools/binman/requirements.txt \
@@ -273,7 +277,7 @@
if [ -n "\${BUILD_ENV}" ]; then
export \${BUILD_ENV};
fi
- virtualenv -p /usr/bin/python3 /tmp/venv
+ python3 -m venv /tmp/venv
. /tmp/venv/bin/activate
pip install -r tools/binman/requirements.txt \
-r tools/buildman/requirements.txt \
@@ -303,6 +307,13 @@
/opt/coreboot/cbfstool \${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom remove -n fallback/payload;
/opt/coreboot/cbfstool \${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f \${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
fi
+ # If we have TF-A binaries, we need to use them.
+ if [[ -d /opt/tf-a/"\${TEST_PY_BD}" ]]; then
+ cp /opt/tf-a/"\${TEST_PY_BD}"/fip.bin /opt/tf-a/"\${TEST_PY_BD}"/bl1.bin /tmp;
+ export fip=/tmp/fip.bin;
+ export bl1=/tmp/bl1.bin;
+ export PATH=/opt/Base_RevC_AEMvA_pkg/models/Linux64_GCC-9.3:\${PATH};
+ fi
export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:\${PATH}
export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci
# "\${var:+"-k \$var"}" expands to "" if \$var is empty, "-k \$var" if not
@@ -336,16 +347,18 @@
TEST_PY_TEST_SPEC: "version"
sandbox_clang:
TEST_PY_BD: "sandbox"
- OVERRIDE: "-O clang-17"
+ OVERRIDE: "-O clang-18"
sandbox_clang_asan:
TEST_PY_BD: "sandbox"
- OVERRIDE: "-O clang-17 -a ASAN"
+ OVERRIDE: "-O clang-18 -a ASAN"
TEST_PY_TEST_SPEC: "version"
sandbox64:
TEST_PY_BD: "sandbox64"
sandbox64_clang:
TEST_PY_BD: "sandbox64"
- OVERRIDE: "-O clang-17"
+ OVERRIDE: "-O clang-18"
+ sandbox64_lwip:
+ TEST_PY_BD: "sandbox64_lwip"
sandbox_spl:
TEST_PY_BD: "sandbox_spl"
TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
@@ -424,6 +437,12 @@
TEST_PY_BD: "vexpress_ca9x4"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep"
+ vexpress_fvp:
+ TEST_PY_BD: "vexpress_fvp"
+ TEST_PY_TEST_SPEC: "not sleep and not hostfs"
+ vexpress_fvp_bloblist:
+ TEST_PY_BD: "vexpress_fvp_bloblist"
+ TEST_PY_TEST_SPEC: "not sleep and not hostfs"
integratorcp_cm926ejs:
TEST_PY_BD: "integratorcp_cm926ejs"
TEST_PY_ID: "--id qemu"
@@ -588,7 +607,7 @@
# make environment variables available as tests are running inside a container
export BUILDMAN="${BUILDMAN}"
git config --global --add safe.directory ${WORK_DIR}
- virtualenv -p /usr/bin/python3 /tmp/venv
+ python3 -m venv /tmp/venv
. /tmp/venv/bin/activate
pip install -r tools/binman/requirements.txt \
-r tools/buildman/requirements.txt
diff --git a/.gitignore b/.gitignore
index e93c33d..272257a 100644
--- a/.gitignore
+++ b/.gitignore
@@ -78,6 +78,7 @@
/drivers/video/u_boot_logo.S
/test/overlay/test-fdt-overlay.dtbo.S
/test/overlay/test-fdt-overlay-stacked.dtbo.S
+capsule_esl_file
#
# Generated include files
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 42ec28a..6f11331 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -20,7 +20,7 @@
# Grab our configured image. The source for this is found
# in the u-boot tree at tools/docker/Dockerfile
-image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20240911.1-08Dec2024
+image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20250404-29Apr2025
# We run some tests in different order, to catch some failures quicker.
stages:
@@ -57,7 +57,7 @@
export BINMAN_INDIRS=/tmp;
fi
# Prepare python environment
- - virtualenv -p /usr/bin/python3 /tmp/venv;
+ - python3 -m venv /tmp/venv;
. /tmp/venv/bin/activate;
pip install -r test/py/requirements.txt -r tools/binman/requirements.txt
-r tools/buildman/requirements.txt -r tools/u_boot_pylib/requirements.txt
@@ -96,6 +96,13 @@
/opt/coreboot/cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom remove -n fallback/payload;
/opt/coreboot/cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
fi
+ # If we have TF-A binaries, we need to use them.
+ - if [[ -d /opt/tf-a/"${TEST_PY_BD}" ]]; then
+ cp /opt/tf-a/"${TEST_PY_BD}"/fip.bin /opt/tf-a/"${TEST_PY_BD}"/bl1.bin /tmp/;
+ export fip=/tmp/fip.bin;
+ export bl1=/tmp/bl1.bin;
+ export PATH=/opt/Base_RevC_AEMvA_pkg/models/Linux64_GCC-9.3:${PATH};
+ fi
# "${var:+"-k $var"}" expands to "" if $var is empty, "-k $var" if not
- export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:${PATH};
export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci;
@@ -124,7 +131,7 @@
- ${HOST}
script:
# Prepare python environment
- - virtualenv -p /usr/bin/python3 /tmp/venv;
+ - python3 -m venv /tmp/venv;
. /tmp/venv/bin/activate;
pip install -r tools/binman/requirements.txt
-r tools/buildman/requirements.txt
@@ -155,7 +162,7 @@
docs:
extends: .testsuites
script:
- - virtualenv -p /usr/bin/python3 /tmp/venvhtml
+ - python3 -m venv /tmp/venvhtml
- . /tmp/venvhtml/bin/activate
- pip install -r doc/sphinx/requirements.txt
- make htmldocs KDOC_WERROR=1
@@ -184,7 +191,7 @@
git config --global user.email trini@konsulko.com;
git config --global --add safe.directory "${CI_PROJECT_DIR}";
export USER=gitlab;
- virtualenv -p /usr/bin/python3 /tmp/venv;
+ python3 -m venv /tmp/venv;
. /tmp/venv/bin/activate;
pip install -r test/py/requirements.txt -r tools/binman/requirements.txt
-r tools/buildman/requirements.txt -r tools/patman/requirements.txt
@@ -196,7 +203,10 @@
./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w
--board tools-only;
set -e;
- ./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test;
+ export TOOLPATH="--toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools --toolpath /opt/coreboot";
+ ./tools/binman/binman ${TOOLPATH} tool -f missing;
+ ./tools/binman/binman ${TOOLPATH} test;
+ ./tools/binman/binman ${TOOLPATH} test -T;
./tools/buildman/buildman -t;
./tools/dtoc/dtoc -t;
./tools/patman/patman test;
@@ -207,7 +217,7 @@
extends: .testsuites
script:
- git config --global --add safe.directory "${CI_PROJECT_DIR}"
- - virtualenv -p /usr/bin/python3 /tmp/venv
+ - python3 -m venv /tmp/venv
- . /tmp/venv/bin/activate
- pip install -r test/py/requirements.txt -r tools/binman/requirements.txt
-r tools/buildman/requirements.txt -r tools/patman/requirements.txt
@@ -261,7 +271,7 @@
- ${HOST}
variables:
TEST_PY_BD: "sandbox"
- OVERRIDE: "-O clang-17"
+ OVERRIDE: "-O clang-18"
<<: *buildman_and_testpy_dfn
sandbox64 test.py:
@@ -284,7 +294,18 @@
- ${HOST}
variables:
TEST_PY_BD: "sandbox64"
- OVERRIDE: "-O clang-17"
+ OVERRIDE: "-O clang-18"
+ <<: *buildman_and_testpy_dfn
+
+sandbox64_lwip test.py:
+ parallel:
+ matrix:
+ - HOST: "fast arm64"
+ - HOST: "fast amd64"
+ tags:
+ - ${HOST}
+ variables:
+ TEST_PY_BD: "sandbox64_lwip"
<<: *buildman_and_testpy_dfn
sandbox_spl test.py:
@@ -501,6 +522,22 @@
TEST_PY_ID: "--id spi-nor_qemu"
<<: *buildman_and_testpy_dfn
+vexpress_fvp test.py:
+ variables:
+ TEST_PY_BD: "vexpress_fvp"
+ TEST_PY_TEST_SPEC: "not sleep and not hostfs"
+ tags:
+ - ${DEFAULT_AMD64_TAG}
+ <<: *buildman_and_testpy_dfn
+
+vexpress_fvp_bloblist test.py:
+ variables:
+ TEST_PY_BD: "vexpress_fvp_bloblist"
+ TEST_PY_TEST_SPEC: "not sleep and not hostfs"
+ tags:
+ - ${DEFAULT_AMD64_TAG}
+ <<: *buildman_and_testpy_dfn
+
xilinx_zynq_virt test.py:
variables:
TEST_PY_BD: "xilinx_zynq_virt"
diff --git a/.mailmap b/.mailmap
index 8508660..5c48114 100644
--- a/.mailmap
+++ b/.mailmap
@@ -35,6 +35,7 @@
Bin Meng <bmeng.cn@gmail.com> <bin.meng@windriver.com>
Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@bootlin.com>
Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com>
+Casey Connolly <casey.connolly@linaro.org> <caleb.connolly@linaro.org>
Christian Kohn <chris.kohn@amd.com> <christian.kohn@xilinx.com>
Christopher Obbard <christopher.obbard@linaro.org> <chris.obbard@collabora.com>
Dirk Behme <dirk.behme@googlemail.com>
@@ -95,7 +96,8 @@
Padmarao Begari <padmarao.begari@amd.com> <padmarao.begari@microchip.com>
Patrice Chotard <patrice.chotard@foss.st.com> <patrice.chotard@st.com>
Patrick Delaunay <patrick.delaunay@foss.st.com> <patrick.delaunay@st.com>
-Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
+Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com>
+Paul Burton <paulburton@kernel.org> <paul.burton@mips.com>
Philipp Tomsich <philipp.tomsich@vrull.eu> <philipp.tomsich@theobroma-systems.com>
Piyush Mehta <piyush.mehta@amd.com> <piyush.mehta@xilinx.com>
Prabhakar Kushwaha <prabhakar@freescale.com>
@@ -123,7 +125,7 @@
Srinivas Goud <srinivas.goud@amd.com> <srinivas.goud@xilinx.com>
Srinivas Neeli <srinivas.neeli@amd.com> <srinivas.neeli@xilinx.com>
Stefan Roese <sr@denx.de> <stroese>
-Stefano Babic <sbabic@denx.de>
+Stefano Babic <sbabic@nabladev.com>
Stefano Stabellini <stefano.stabellini@amd.com> <stefano.stabellini@xilinx.com>
Sumit Garg <sumit.garg@kernel.org> <sumit.garg@linaro.org>
Tom Rini <trini@konsulko.com> <trini@ti.com>
diff --git a/Kconfig b/Kconfig
index a508c54..5135863 100644
--- a/Kconfig
+++ b/Kconfig
@@ -454,6 +454,12 @@
it is possible to set breakpoints on particular lines, single-step
debug through the source code, etc.
+config SKIP_RELOCATE
+ bool "Skips relocation of U-Boot to end of RAM"
+ help
+ Skips relocation of U-Boot allowing for systems that have extremely
+ limited RAM to run U-Boot.
+
endif # EXPERT
config PHYS_64BIT
diff --git a/MAINTAINERS b/MAINTAINERS
index a0b06e9..d62dd35 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -157,6 +157,7 @@
T: git https://source.denx.de/u-boot/custodians/u-boot-socfpga.git
F: drivers/ddr/altera/
F: arch/arm/mach-socfpga/
+F: configs/socfpga_agilex5_vab_defconfig
F: drivers/sysreset/sysreset_socfpga*
ARM AMLOGIC SOC SUPPORT
@@ -296,7 +297,7 @@
F: test/dm/ffa.c
ARM FREESCALE IMX
-M: Stefano Babic <sbabic@denx.de>
+M: Stefano Babic <sbabic@nabladev.com>
M: Fabio Estevam <festevam@gmail.com>
R: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
S: Maintained
@@ -1824,6 +1825,15 @@
F: drivers/usb/host/xhci*
F: include/usb/xhci.h
+UTHREAD
+M: Jerome Forissier <jerome.forissier@linaro.org>
+S: Maintained
+F: cmd/spawn.c
+F: include/uthread.h
+F: lib/uthread.c
+F: test/cmd/spawn.c
+F: test/lib/uthread.c
+
UUID testing
M: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
S: Maintained
diff --git a/Makefile b/Makefile
index e83672b..7451d7a 100644
--- a/Makefile
+++ b/Makefile
@@ -1,9 +1,9 @@
# SPDX-License-Identifier: GPL-2.0+
VERSION = 2025
-PATCHLEVEL = 04
+PATCHLEVEL = 07
SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
NAME =
# *DOCUMENTATION*
@@ -837,7 +837,7 @@
-I$(srctree)/lib/mbedtls/port \
-I$(srctree)/lib/mbedtls/external/mbedtls \
-I$(srctree)/lib/mbedtls/external/mbedtls/include) \
- $(if $(CONFIG_$(XPL_)SYS_THUMB_BUILD), \
+ $(if $(CONFIG_$(PHASE_)SYS_THUMB_BUILD), \
$(if $(CONFIG_HAS_THUMB2), \
$(if $(CONFIG_CPU_V7M), \
-I$(srctree)/arch/arm/thumb1/include), \
@@ -874,7 +874,7 @@
libs-y += drivers/
libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/
-libs-$(CONFIG_$(XPL_)ALTERA_SDRAM) += drivers/ddr/altera/
+libs-$(CONFIG_$(PHASE_)ALTERA_SDRAM) += drivers/ddr/altera/
libs-y += drivers/usb/cdns3/
libs-y += drivers/usb/dwc3/
libs-y += drivers/usb/common/
diff --git a/arch/Kconfig b/arch/Kconfig
index 35b19f9..ea33d07 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -13,6 +13,13 @@
help
The architecture supports setjmp() and longjmp().
+config HAVE_INITJMP
+ bool
+ depends on HAVE_SETJMP
+ help
+ The architecture supports initjmp(), a non-standard companion to
+ setjmp() and longjmp().
+
config SUPPORT_BIG_ENDIAN
bool
@@ -88,6 +95,7 @@
config ARM
bool "ARM architecture"
select HAVE_SETJMP
+ select HAVE_INITJMP
select ARCH_SUPPORTS_LTO
select CREATE_ARCH_SYMLINK
select HAVE_PRIVATE_LIBGCC if !ARM64
@@ -145,6 +153,7 @@
bool "RISC-V architecture"
select CREATE_ARCH_SYMLINK
select HAVE_SETJMP
+ select HAVE_INITJMP
select SUPPORT_ACPI
select SUPPORT_LITTLE_ENDIAN
select SUPPORT_OF_CONTROL
@@ -171,6 +180,7 @@
config SANDBOX
bool "Sandbox"
select HAVE_SETJMP
+ select HAVE_INITJMP
select ARCH_SUPPORTS_LTO
select BOARD_LATE_INIT
select BZIP2
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6e234af..fedfdb2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1120,7 +1120,7 @@
select SPMI
select BOARD_LATE_INIT
select OF_BOARD
- select SAVE_PREV_BL_FDT_ADDR
+ select SAVE_PREV_BL_FDT_ADDR if !ENABLE_ARM_SOC_BOOT0_HOOK
select LINUX_KERNEL_IMAGE_HEADER if !ENABLE_ARM_SOC_BOOT0_HOOK
select SYSRESET
select SYSRESET_PSCI
@@ -1138,6 +1138,7 @@
select DM_SERIAL
select GPIO_EXTRA_HEADER
select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
+ select LMB_ARCH_MEM_MAP if TARGET_SOCFPGA_SOC64
select OF_CONTROL
select SPL_DM_RESET if DM_RESET
select SPL_DM_SERIAL
@@ -1171,8 +1172,6 @@
imply SPL_DM_SPI_FLASH
imply SPL_LIBDISK_SUPPORT
imply SPL_MMC
- imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
- imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
imply SPL_SPI_FLASH_SUPPORT
imply SPL_SPI
imply L2X0_CACHE
@@ -1191,6 +1190,7 @@
select DM_SPI_FLASH if SPI && MTD
select DM_KEYBOARD
select DM_SERIAL
+ select MMU_PGPROT if ARM64
select OF_BOARD_SETUP
select OF_CONTROL
select PINCTRL
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index e0045e2..6e725ba 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -40,7 +40,7 @@
endif
# Choose between ARM/Thumb instruction sets
-ifeq ($(CONFIG_$(XPL_)SYS_THUMB_BUILD),y)
+ifeq ($(CONFIG_$(PHASE_)SYS_THUMB_BUILD),y)
AFLAGS_IMPLICIT_IT := $(call as-option,-Wa$(comma)-mimplicit-it=always)
PF_CPPFLAGS_ARM := $(AFLAGS_IMPLICIT_IT) \
$(call cc-option, -mthumb -mthumb-interwork,\
@@ -53,7 +53,7 @@
endif
# Only test once
-ifeq ($(CONFIG_$(XPL_)SYS_THUMB_BUILD),y)
+ifeq ($(CONFIG_$(PHASE_)SYS_THUMB_BUILD),y)
archprepare: checkthumb checkgcc6
checkthumb:
@@ -116,7 +116,7 @@
#
# http://sourceware.org/bugzilla/show_bug.cgi?id=12532
#
-ifeq ($(CONFIG_$(XPL_)SYS_THUMB_BUILD),y)
+ifeq ($(CONFIG_$(PHASE_)SYS_THUMB_BUILD),y)
ifeq ($(GAS_BUG_12532),)
export GAS_BUG_12532:=$(shell if [ $(call binutils-version) -lt 0222 ] ; \
then echo y; else echo n; fi)
diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile
index 06456fe..9929b5a 100644
--- a/arch/arm/cpu/arm920t/Makefile
+++ b/arch/arm/cpu/arm920t/Makefile
@@ -9,6 +9,6 @@
# some files can only build in ARM mode
-ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD
+ifdef CONFIG_$(PHASE_)SYS_THUMB_BUILD
CFLAGS_cpu.o := -marm
endif
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index 750cb94..41d8af5 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -17,7 +17,7 @@
# some files can only build in ARM or THUMB2, not THUMB1
-ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD
+ifdef CONFIG_$(PHASE_)SYS_THUMB_BUILD
ifndef CONFIG_HAS_THUMB2
CFLAGS_cpu.o := -marm
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 6461f5f..318a71f 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -17,7 +17,7 @@
obj-$(CONFIG_ARMV7_NONSEC) += exception_level.o
endif
-ifneq ($(CONFIG_$(XPL_)SKIP_LOWLEVEL_INIT),y)
+ifneq ($(CONFIG_$(PHASE_)SKIP_LOWLEVEL_INIT),y)
obj-y += lowlevel_init.o
endif
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index b4126c6..dd0191a 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -9,7 +9,7 @@
ifndef CONFIG_$(PHASE_)TIMER
obj-$(CONFIG_SYS_ARCH_TIMER) += generic_timer.o
endif
-ifndef CONFIG_$(XPL_)SYS_DCACHE_OFF
+ifndef CONFIG_$(PHASE_)SYS_DCACHE_OFF
obj-y += cache_v8.o
obj-y += cache.o
endif
@@ -33,7 +33,7 @@
else
obj-$(CONFIG_ARCH_SUNXI) += fel_utils.o
endif
-obj-$(CONFIG_$(XPL_)ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_asm.o
+obj-$(CONFIG_$(PHASE_)ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_asm.o
ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_SPL_RECOVER_DATA_SECTION) += spl_data.o
diff --git a/arch/arm/cpu/armv8/fel_utils.S b/arch/arm/cpu/armv8/fel_utils.S
index f7707ac..044a7c1 100644
--- a/arch/arm/cpu/armv8/fel_utils.S
+++ b/arch/arm/cpu/armv8/fel_utils.S
@@ -74,10 +74,19 @@
.word 0xf57ff06f // isb
.word 0xe590d000 // ldr sp, [r0]
.word 0xe590e004 // ldr lr, [r0, #4]
+ .word 0xe5901014 // ldr r1, [r0, #20]
+ .word 0xe121f301 // msr SP_irq, r1
.word 0xe5901010 // ldr r1, [r0, #16]
.word 0xee0c1f10 // mcr 15, 0, r1, cr12, cr0, {0} ; VBAR
.word 0xe590100c // ldr r1, [r0, #12]
.word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0} ; SCTLR
.word 0xf57ff06f // isb
+#ifdef CONFIG_MACH_SUN55I_A523
+ .word 0xe5901018 // ldr r1, [r0, #24]
+ .word 0xee041f16 // mcr 15, 0, r1, cr4, cr6, {0}; ICC_PMR
+ .word 0xe590101c // ldr r1, [r0, #28]
+ .word 0xee0c1ffc // mcr 15, 0, r1, cr12, cr12, {7}; ICC_IGRPEN1
+#endif
+
.word 0xe12fff1e // bx lr ; return to FEL
ENDPROC(return_to_fel)
diff --git a/arch/arm/cpu/armv8/spin_table.c b/arch/arm/cpu/armv8/spin_table.c
index 485294b..5ba20ef 100644
--- a/arch/arm/cpu/armv8/spin_table.c
+++ b/arch/arm/cpu/armv8/spin_table.c
@@ -4,6 +4,7 @@
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*/
+#include <errno.h>
#include <linux/libfdt.h>
#include <asm/spin_table.h>
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index d3a8a7c..829a620 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -334,6 +334,9 @@
/*
* All slaves will enter EL2 and optionally EL1.
*/
+#if defined(CONFIG_ARMV8_PSCI) && !defined(CONFIG_XPL_BUILD)
+ bl psci_setup_vectors
+#endif
adr x4, lowlevel_in_el2
ldr x5, =ES_TO_AARCH64
bl armv8_switch_to_el2
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 080ea52..82f5c37 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -87,6 +87,8 @@
tegra20-asus-tf101g.dtb \
tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
+ tegra20-motorola-daytona.dtb \
+ tegra20-motorola-olympus.dtb \
tegra20-paz00.dtb \
tegra20-plutux.dtb \
tegra20-seaboard.dtb \
@@ -116,7 +118,9 @@
tegra30-ouya.dtb \
tegra30-tec-ng.dtb \
tegra30-wexler-qc750.dtb \
+ tegra114-asus-tf701t.dtb \
tegra114-dalmore.dtb \
+ tegra114-nvidia-tegratab.dtb \
tegra124-apalis.dtb \
tegra124-jetson-tk1.dtb \
tegra124-nyan-big.dtb \
@@ -299,6 +303,13 @@
zynqmp-zc1751-xm017-dc3.dtb \
zynqmp-zc1751-xm018-dc4.dtb \
zynqmp-zc1751-xm019-dc5.dtb
+dtb-$(CONFIG_TARGET_ZYNQ_BR) += \
+ zynq-brcp1_2r.dtb \
+ zynq-brcp1_1r.dtb \
+ zynq-brcp1_1r_switch.dtb \
+ zynq-brsmarc2.dtb \
+ zynq-brcp150.dtb \
+ zynq-brcp170.dtb
zynqmp-p-a2197-00-revA-x-prc-01-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-01-revA.dtbo
zynqmp-p-a2197-00-revA-x-prc-02-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-02-revA.dtbo
@@ -519,17 +530,6 @@
dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb
-dtb-$(CONFIG_STM32F4) += stm32f429-disco.dtb \
- stm32429i-eval.dtb \
- stm32f469-disco.dtb
-
-dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \
- stm32f769-disco.dtb \
- stm32746g-eval.dtb
-dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
- stm32h743i-eval.dtb \
- stm32h750i-art-pi.dtb
-
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-inet-3f.dtb \
sun4i-a10-inet-3w.dtb
@@ -1076,29 +1076,9 @@
ast2600-sbp1.dtb \
ast2600-x4tf.dtb
-dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
-
-dtb-$(CONFIG_STM32MP13X) += \
- stm32mp135f-dk.dtb
-
dtb-$(CONFIG_STM32MP15X) += \
- stm32mp157a-dk1.dtb \
- stm32mp157a-dk1-scmi.dtb \
- stm32mp157a-icore-stm32mp1-ctouch2.dtb \
- stm32mp157a-icore-stm32mp1-edimm2.2.dtb \
- stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
- stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \
- stm32mp157c-dk2.dtb \
- stm32mp157c-dk2-scmi.dtb \
- stm32mp157c-ed1.dtb \
- stm32mp157c-ed1-scmi.dtb \
- stm32mp157c-ev1.dtb \
- stm32mp157c-ev1-scmi.dtb \
stm32mp157c-odyssey.dtb
-dtb-$(CONFIG_STM32MP25X) += \
- stm32mp257f-ev1.dtb
-
dtb-$(CONFIG_SOC_K3_AM654) += \
k3-am654-r5-base-board.dtb
diff --git a/arch/arm/dts/an7581-u-boot.dtsi b/arch/arm/dts/an7581-u-boot.dtsi
index 0316b73..a9297ca 100644
--- a/arch/arm/dts/an7581-u-boot.dtsi
+++ b/arch/arm/dts/an7581-u-boot.dtsi
@@ -1,5 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
+#include <dt-bindings/reset/airoha,en7581-reset.h>
+
/ {
reserved-memory {
#address-cells = <2>;
@@ -11,8 +13,96 @@
reg = <0x0 0x80000000 0x0 0x40000>;
};
};
+
+ clk25m: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ clock-output-names = "clkxtal";
+ };
+
+ vmmc_3v3: regulator-vmmc-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ soc {
+ chip_scu: syscon@1fa20000 {
+ compatible = "airoha,en7581-chip-scu", "syscon";
+ reg = <0x0 0x1fa20000 0x0 0x388>;
+ };
+
+ eth: ethernet@1fb50000 {
+ compatible = "airoha,en7581-eth";
+ reg = <0 0x1fb50000 0 0x2600>,
+ <0 0x1fb54000 0 0x2000>,
+ <0 0x1fb56000 0 0x2000>;
+ reg-names = "fe", "qdma0", "qdma1";
+
+ resets = <&scuclk EN7581_FE_RST>,
+ <&scuclk EN7581_FE_PDMA_RST>,
+ <&scuclk EN7581_FE_QDMA_RST>,
+ <&scuclk EN7581_DUAL_HSI0_MAC_RST>,
+ <&scuclk EN7581_DUAL_HSI1_MAC_RST>,
+ <&scuclk EN7581_HSI_MAC_RST>,
+ <&scuclk EN7581_XFP_MAC_RST>;
+ reset-names = "fe", "pdma", "qdma",
+ "hsi0-mac", "hsi1-mac", "hsi-mac",
+ "xfp-mac";
+ };
+
+ switch: switch@1fb58000 {
+ compatible = "airoha,en7581-switch";
+ reg = <0 0x1fb58000 0 0x8000>;
+ };
+
+ snfi: spi@1fa10000 {
+ compatible = "airoha,en7581-snand";
+ reg = <0x0 0x1fa10000 0x0 0x140>,
+ <0x0 0x1fa11000 0x0 0x600>;
+
+ clocks = <&scuclk EN7523_CLK_SPI>;
+ clock-names = "spi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ spi_nand: nand@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <2>;
+ };
+ };
+
+ mmc0: mmc@1fa0e000 {
+ compatible = "mediatek,mt7622-mmc";
+ reg = <0x0 0x1fa0e000 0x0 0x1000>,
+ <0x0 0x1fa0c000 0x0 0x60>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scuclk EN7581_CLK_EMMC>, <&clk25m>;
+ clock-names = "source", "hclk";
+ bus-width = <4>;
+ max-frequency = <52000000>;
+ vmmc-supply = <&vmmc_3v3>;
+ disable-wp;
+ cap-mmc-highspeed;
+ non-removable;
+
+ assigned-clocks = <&scuclk EN7581_CLK_EMMC>;
+ assigned-clock-rates = <200000000>;
+ };
+ };
};
+&scuclk {
+ compatible = "airoha,en7581-scu", "syscon";
+};
+
&uart1 {
bootph-all;
};
diff --git a/arch/arm/dts/apq8016-sbc-u-boot.dtsi b/arch/arm/dts/apq8016-sbc-u-boot.dtsi
index 585d54d..c8a46ed 100644
--- a/arch/arm/dts/apq8016-sbc-u-boot.dtsi
+++ b/arch/arm/dts/apq8016-sbc-u-boot.dtsi
@@ -6,7 +6,7 @@
/ {
/* When running as a first-stage bootloader this isn't filled in automatically */
memory@80000000 {
- reg = <0 0x80000000 0 0x3da00000>;
+ reg = <0 0x80000000 0 0x40000000>;
};
};
diff --git a/arch/arm/dts/at91-sam9x60_curiosity.dts b/arch/arm/dts/at91-sam9x60_curiosity.dts
index 7f00014..1c7f0fa 100644
--- a/arch/arm/dts/at91-sam9x60_curiosity.dts
+++ b/arch/arm/dts/at91-sam9x60_curiosity.dts
@@ -319,6 +319,10 @@
pinctrl-0 = <&pinctrl_sdhci1>;
};
+&usb0 {
+ status = "okay";
+};
+
&usb1 {
num-ports = <3>;
atmel,vbus-gpio = <0
diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi
index abb3aa5..59453dc 100644
--- a/arch/arm/dts/imx8mm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-u-boot.dtsi
@@ -240,6 +240,11 @@
bootph-pre-ram;
};
+&osc_32k {
+ bootph-all;
+ bootph-pre-ram;
+};
+
#ifdef CONFIG_FSL_CAAM
&sec_jr0 {
bootph-pre-ram;
diff --git a/arch/arm/dts/imx8mp-toradex-smarc-dev-u-boot.dtsi b/arch/arm/dts/imx8mp-toradex-smarc-dev-u-boot.dtsi
new file mode 100644
index 0000000..a94e48e
--- /dev/null
+++ b/arch/arm/dts/imx8mp-toradex-smarc-dev-u-boot.dtsi
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/* Copyright (C) 2024 Toradex */
+
+#include "imx8mp-u-boot.dtsi"
+
+/ {
+ sysinfo {
+ compatible = "toradex,sysinfo";
+ };
+};
+
+&gpio1 {
+ bootph-pre-ram;
+};
+
+&gpio2 {
+ bt_uart_gpio {
+ gpio-hog;
+ gpios = <9 GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BT_UART_RXD_GPIO";
+ };
+};
+
+&gpio3 {
+ wifi_en_gpio {
+ gpio-hog;
+ gpios = <14 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "CTRL_EN_WIFI";
+ };
+};
+
+&gpio5 {
+ bootph-pre-ram;
+};
+
+&i2c1 {
+ bootph-pre-ram;
+};
+
+&pca9450 {
+ bootph-pre-ram;
+
+ regulators {
+ bootph-pre-ram;
+ };
+};
+
+&pinctrl_i2c1 {
+ bootph-pre-ram;
+};
+
+&pinctrl_i2c1_gpio {
+ bootph-pre-ram;
+};
+
+&pinctrl_pmic {
+ bootph-pre-ram;
+};
+
+&pinctrl_uart4 {
+ bootph-pre-ram;
+};
+
+&uart3 {
+ status = "disabled";
+};
+
+&uart4 {
+ bootph-pre-ram;
+};
+
+&usdhc1 {
+ status = "disabled";
+};
+
+&usdhc3 {
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/imx8mp-toradex-smarc-dev.dts b/arch/arm/dts/imx8mp-toradex-smarc-dev.dts
new file mode 100644
index 0000000..581f221
--- /dev/null
+++ b/arch/arm/dts/imx8mp-toradex-smarc-dev.dts
@@ -0,0 +1,297 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/* Copyright (C) 2025 Toradex */
+
+/dts-v1/;
+
+#include "imx8mp-toradex-smarc.dtsi"
+
+/ {
+ model = "Toradex SMARC iMX8M Plus on Toradex SMARC Development Board";
+ compatible = "toradex,smarc-imx8mp-dev",
+ "toradex,smarc-imx8mp",
+ "fsl,imx8mp";
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ label = "J64";
+ type = "a";
+
+ port {
+ native_hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_out>;
+ };
+ };
+ };
+
+ reg_carrier_1p8v: regulator-carrier-1p8v {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "On-carrier 1V8";
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,bitclock-master = <&codec_dai>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,frame-master = <&codec_dai>;
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,name = "tdx-smarc-wm8904";
+ simple-audio-card,routing =
+ "Headphone Jack", "HPOUTL",
+ "Headphone Jack", "HPOUTR",
+ "IN2L", "Line In Jack",
+ "IN2R", "Line In Jack",
+ "Microphone Jack", "MICBIAS",
+ "IN1L", "Microphone Jack";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Headphone", "Headphone Jack",
+ "Line", "Line In Jack";
+
+ codec_dai: simple-audio-card,codec {
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>;
+ sound-dai = <&wm8904_1a>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai1>;
+ };
+ };
+};
+
+&aud2htx {
+ status = "okay";
+};
+
+/* SMARC SPI0 */
+&ecspi1 {
+ status = "okay";
+};
+
+/* SMARC GBE0 */
+&eqos {
+ status = "okay";
+};
+
+/* SMARC GBE1 */
+&fec {
+ status = "okay";
+};
+
+/* SMARC CAN1 */
+&flexcan1 {
+ status = "okay";
+};
+
+/* SMARC CAN0 */
+&flexcan2 {
+ status = "okay";
+};
+
+&gpio1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio7>,
+ <&pinctrl_gpio8>,
+ <&pinctrl_gpio9>,
+ <&pinctrl_gpio10>,
+ <&pinctrl_gpio11>,
+ <&pinctrl_gpio12>,
+ <&pinctrl_gpio13>;
+};
+
+&gpio3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lvds_dsi_sel>;
+};
+
+&gpio4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio4>, <&pinctrl_gpio6>;
+};
+
+&hdmi_pvi {
+ status = "okay";
+};
+
+/* SMARC HDMI */
+&hdmi_tx {
+ status = "okay";
+
+ ports {
+ port@1 {
+ hdmi_tx_out: endpoint {
+ remote-endpoint = <&native_hdmi_connector_in>;
+ };
+ };
+ };
+};
+
+&hdmi_tx_phy {
+ status = "okay";
+};
+
+/* SMARC I2C_LCD */
+&i2c2 {
+ status = "okay";
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9543";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* I2C on DSI Connector Pins 4/6 */
+ i2c_dsi_0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ /* I2C on DSI Connector Pins 52/54 */
+ i2c_dsi_1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+/* SMARC I2C_CAM0 */
+&i2c3 {
+ status = "okay";
+};
+
+/* SMARC I2C_GP */
+&i2c4 {
+ /* Audio Codec */
+ wm8904_1a: audio-codec@1a {
+ compatible = "wlf,wm8904";
+ reg = <0x1a>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai1>, <&pinctrl_sai1_mclk>;
+ #sound-dai-cells = <0>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>;
+ clock-names = "mclk";
+ AVDD-supply = <®_carrier_1p8v>;
+ CPVDD-supply = <®_carrier_1p8v>;
+ DBVDD-supply = <®_carrier_1p8v>;
+ DCVDD-supply = <®_carrier_1p8v>;
+ MICVDD-supply = <®_carrier_1p8v>;
+ };
+
+ /* On-Carrier Temperature Sensor */
+ temperature-sensor@4f {
+ compatible = "ti,tmp1075";
+ reg = <0x4f>;
+ };
+
+ /* On-Carrier EEPROM */
+ eeprom@57 {
+ compatible = "st,24c02", "atmel,24c02";
+ reg = <0x57>;
+ pagesize = <16>;
+ };
+};
+
+/* SMARC I2C_CAM1 */
+&i2c5 {
+ status = "okay";
+};
+
+/* SMARC I2C_PM */
+&i2c6 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ /* Fan controller */
+ fan@18 {
+ compatible = "ti,amc6821";
+ reg = <0x18>;
+ };
+
+ /* Current measurement into module VDD */
+ hwmon@40 {
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
+};
+
+&lcdif3 {
+ status = "okay";
+};
+
+/* SMARC PCIE_A, M2 Key B */
+&pcie {
+ status = "okay";
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
+/* SMARC LCD1_BKLT_PWM */
+&pwm1 {
+ status = "okay";
+};
+
+/* SMARC LCD0_BKLT_PWM */
+&pwm2 {
+ status = "okay";
+};
+
+/* SMARC I2S0 */
+&sai1 {
+ assigned-clocks = <&clk IMX8MP_CLK_SAI1>;
+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <24576000>;
+ fsl,sai-mclk-direction-output;
+ status = "okay";
+};
+
+/* SMARC HDMI Audio */
+&sound_hdmi {
+ status = "okay";
+};
+
+/* SMARC SER0, RS485. Optional M.2 KEY E */
+&uart1 {
+ linux,rs485-enabled-at-boot-time;
+ rs485-rts-active-low;
+ rs485-rx-during-tx;
+ status = "okay";
+};
+
+/* SMARC SER2 */
+&uart2 {
+ status = "okay";
+};
+
+/* SMARC SER1, used as the Linux Console */
+&uart4 {
+ status = "okay";
+};
+
+/* SMARC USB0 */
+&usb3_0 {
+ status = "okay";
+};
+
+/* SMARC USB1..4 */
+&usb3_1 {
+ status = "okay";
+};
+
+&usb3_phy0 {
+ status = "okay";
+};
+
+&usb3_phy1 {
+ status = "okay";
+};
+
+/* SMARC SDIO */
+&usdhc2 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/imx8mp-toradex-smarc.dtsi b/arch/arm/dts/imx8mp-toradex-smarc.dtsi
new file mode 100644
index 0000000..0a8b9ee
--- /dev/null
+++ b/arch/arm/dts/imx8mp-toradex-smarc.dtsi
@@ -0,0 +1,1284 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/* Copyright (C) 2025 Toradex */
+
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include "imx8mp.dtsi"
+
+/ {
+ aliases {
+ can0 = &flexcan2;
+ can1 = &flexcan1;
+ ethernet0 = &eqos;
+ ethernet1 = &fec;
+ mmc0 = &usdhc3;
+ mmc1 = &usdhc2;
+ mmc2 = &usdhc1;
+ rtc0 = &rtc_i2c;
+ rtc1 = &snvs_rtc;
+ serial0 = &uart1;
+ serial1 = &uart4;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ };
+
+ chosen {
+ stdout-path = &uart4;
+ };
+
+ connector {
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_id>;
+ id-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+ label = "USB0";
+ self-powered;
+ type = "micro";
+ vbus-supply = <®_usb0_vbus>;
+
+ port {
+ usb_dr_connector: endpoint {
+ remote-endpoint = <&usb3_0_dwc>;
+ };
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sleep>;
+
+ smarc_key_sleep: key-sleep {
+ gpios = <&gpio3 1 GPIO_ACTIVE_LOW>;
+ label = "SMARC_SLEEP#";
+ wakeup-source;
+ linux,code = <KEY_SLEEP>;
+ };
+ };
+
+ reg_usb0_vbus: regulator-usb0-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_en_oc>;
+ gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-name = "USB0_EN_OC#";
+ };
+
+ reg_usb1_vbus: regulator-usb1-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1_en_oc>;
+ gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-name = "USB2_EN_OC#";
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
+ gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ off-on-delay-us = <100000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "3V3_SD";
+ startup-delay-us = <20000>;
+ };
+
+ reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
+ compatible = "regulator-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2_vsel>;
+ gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
+ states = <1800000 0x1>,
+ <3300000 0x0>;
+ regulator-name = "PMIC_USDHC_VSELECT";
+ vin-supply = <®_sd_3v3_1v8>;
+ };
+
+ reg_wifi_en: regulator-wifi-en {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi_pwr_en>;
+ gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "CTRL_EN_WIFI";
+ startup-delay-us = <2000>;
+ };
+
+ reserved-memory {
+ linux,cma {
+ size = <0 0x20000000>;
+ alloc-ranges = <0 0x40000000 0 0x80000000>;
+ };
+ };
+
+ sound_hdmi: sound-hdmi {
+ compatible = "fsl,imx-audio-hdmi";
+ model = "audio-hdmi";
+ audio-cpu = <&aud2htx>;
+ hdmi-out;
+ status = "disabled";
+ };
+};
+
+&A53_0 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&A53_1 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&A53_2 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&A53_3 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+/* SMARC SPI0 */
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, <&gpio4 28 GPIO_ACTIVE_LOW>;
+};
+
+/* SMARC SPI1 */
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>, <&pinctrl_tpm_cs>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
+ <&gpio4 3 GPIO_ACTIVE_LOW>,
+ <&gpio3 6 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ tpm@2 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ reg = <2>;
+ spi-max-frequency = <18500000>;
+ };
+};
+
+/* SMARC GBE0 */
+&eqos {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>,
+ <&pinctrl_eth_mdio>,
+ <&pinctrl_eqos_1588_event>;
+ phy-handle = <&eqos_phy>;
+ phy-mode = "rgmii-id";
+ snps,force_thresh_dma_mode;
+ snps,mtl-rx-config = <&mtl_rx_setup>;
+ snps,mtl-tx-config = <&mtl_tx_setup>;
+
+ mdio: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <5>;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,priority = <0x1>;
+ snps,map-to-dma-channel = <0>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,priority = <0x2>;
+ snps,map-to-dma-channel = <1>;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ snps,priority = <0x4>;
+ snps,map-to-dma-channel = <2>;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ snps,priority = <0x8>;
+ snps,map-to-dma-channel = <3>;
+ };
+
+ queue4 {
+ snps,dcb-algorithm;
+ snps,priority = <0xf0>;
+ snps,map-to-dma-channel = <4>;
+ };
+ };
+
+ mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <5>;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,priority = <0x1>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,priority = <0x2>;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ snps,priority = <0x4>;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ snps,priority = <0x8>;
+ };
+
+ queue4 {
+ snps,dcb-algorithm;
+ snps,priority = <0xf0>;
+ };
+ };
+};
+
+/* SMARC GBE1 */
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec>, <&pinctrl_fec_1588_event>;
+ phy-handle = <&fec_phy>;
+ phy-mode = "rgmii-id";
+ fsl,magic-packet;
+};
+
+/* SMARC CAN1 */
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+};
+
+/* SMARC CAN0 */
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+};
+
+&gpio1 {
+ gpio-line-names = "SMARC_GPIO7", /* 0 */
+ "SMARC_GPIO8",
+ "",
+ "PMIC_INT#",
+ "PMIC_USDHC_VSELECT",
+ "SMARC_GPIO9",
+ "SMARC_GPIO10",
+ "SMARC_GPIO11",
+ "SMARC_GPIO12",
+ "",
+ "SMARC_GPIO5", /* 10 */
+ "",
+ "SMARC_USB0_EN_OC#",
+ "SMARC_GPIO13",
+ "SMARC_USB2_EN_OC#";
+};
+
+&gpio2 {
+ gpio-line-names = "", /* 0 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 10 */
+ "",
+ "SMARC_SDIO_CD#",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SMARC_SDIO_PWR_EN",
+ "SMARC_SDIO_WP"; /* 20 */
+};
+
+&gpio3 {
+ gpio-line-names = "ETH_0_INT#", /* 0 */
+ "SLEEP#",
+ "",
+ "",
+ "",
+ "",
+ "TPM_CS#",
+ "LVDS_DSI_SEL",
+ "MCU_INT#",
+ "GPIO_EX_INT#",
+ "", /* 10 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SMARC_SMB_ALERT#",
+ "",
+ "",
+ "",
+ "SMARC_I2C_PM_DAT", /* 20 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SMARC_I2C_PM_CK";
+
+ lvds_dsi_mux_hog: lvds-dsi-mux-hog {
+ gpio-hog;
+ gpios = <7 GPIO_ACTIVE_HIGH>;
+ line-name = "LVDS_DSI_SEL";
+ /* LVDS_DSI_SEL as DSI */
+ output-low;
+ };
+};
+
+&gpio4 {
+ gpio-line-names = "SMARC_PCIE_WAKE#", /* 0 */
+ "",
+ "",
+ "SMARC_SPI1_CS1#",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 10 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SMARC_GPIO4",
+ "SMARC_PCIE_A_RST#",
+ "", /* 20 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SMARC_SPI0_CS1#",
+ "SMARC_GPIO6";
+};
+
+&gpio5 {
+ gpio-line-names = "", /* 0 */
+ "",
+ "SMARC_USB0_OTG_ID",
+ "SMARC_I2C_CAM1_CK",
+ "SMARC_I2C_CAM1_DAT",
+ "",
+ "",
+ "",
+ "",
+ "SMARC_SPI0_CS0#",
+ "", /* 10 */
+ "",
+ "",
+ "SMARC_SPI1_CS0#",
+ "CTRL_I2C_SCL",
+ "CTRL_I2C_SDA",
+ "SMARC_I2C_LCD_CK",
+ "SMARC_I2C_LCD_DAT",
+ "SMARC_I2C_CAM0_CK",
+ "SMARC_I2C_CAM0_DAT",
+ "SMARC_I2C_GP_CK", /* 20 */
+ "SMARC_I2C_GP_DAT";
+};
+
+/* SMARC HDMI */
+&hdmi_tx {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hdmi>;
+};
+
+/* On-module I2C */
+&i2c1 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ clock-frequency = <400000>;
+ scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ single-master;
+ status = "okay";
+
+ som_gpio_expander: gpio-expander@21 {
+ compatible = "nxp,pcal6408";
+ reg = <0x21>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcal6408>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&gpio3>;
+ interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-line-names =
+ "SMARC_GPIO0",
+ "SMARC_GPIO1",
+ "SMARC_GPIO2",
+ "SMARC_GPIO3",
+ "SMARC_LCD0_VDD_EN",
+ "SMARC_LCD0_BKLT_EN",
+ "SMARC_LCD1_VDD_EN",
+ "SMARC_LCD1_BKLT_EN";
+ };
+
+ pca9450: pmic@25 {
+ compatible = "nxp,pca9450c";
+ reg = <0x25>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+
+ regulators {
+ BUCK1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1000000>;
+ regulator-min-microvolt = <805000>;
+ regulator-name = "+VDD_SOC (PMIC BUCK1)";
+ regulator-ramp-delay = <3125>;
+ };
+
+ reg_vdd_arm: BUCK2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1000000>;
+ regulator-min-microvolt = <805000>;
+ regulator-name = "+VDD_ARM (PMIC BUCK2)";
+ regulator-ramp-delay = <3125>;
+ nxp,dvs-run-voltage = <950000>;
+ nxp,dvs-standby-voltage = <850000>;
+ };
+
+ reg_3v3: BUCK4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "+V3.3 (PMIC BUCK4)";
+ };
+
+ reg_1v8: BUCK5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "+V1.8 (PMIC BUCK5)";
+ };
+
+ BUCK6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1155000>;
+ regulator-min-microvolt = <1045000>;
+ regulator-name = "+VDD_DDR (PMIC BUCK6)";
+ };
+
+ LDO1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1950000>;
+ regulator-min-microvolt = <1710000>;
+ regulator-name = "+V1.8_SNVS (PMIC LDO1)";
+ };
+
+ LDO3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "+V1.8A (PMIC LDO3)";
+ };
+
+ LDO4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "+V3.3_ADC (PMIC LDO4)";
+ };
+
+ reg_sd_3v3_1v8: LDO5 {
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "+V3.3_1.8_SD (PMIC LDO5)";
+ };
+ };
+ };
+
+ rtc_i2c: rtc@32 {
+ compatible = "epson,rx8130";
+ reg = <0x32>;
+ };
+
+ temperature-sensor@48 {
+ compatible = "ti,tmp1075";
+ reg = <0x48>;
+ };
+
+ eeprom@50 {
+ compatible = "st,24c02", "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+/* SMARC I2C_LCD */
+&i2c2 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ clock-frequency = <100000>;
+ scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ single-master;
+};
+
+/* SMARC I2C_CAM0 */
+&i2c3 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ clock-frequency = <400000>;
+ scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ single-master;
+};
+
+/* SMARC I2C_GP */
+&i2c4 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4_gpio>;
+ clock-frequency = <400000>;
+ scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ single-master;
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "st,24c32", "atmel,24c32";
+ reg = <0x50>;
+ pagesize = <32>;
+ };
+};
+
+/* SMARC I2C_CAM1 */
+&i2c5 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c5>;
+ pinctrl-1 = <&pinctrl_i2c5_gpio>;
+ clock-frequency = <400000>;
+ scl-gpios = <&gpio5 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ single-master;
+};
+
+/* SMARC I2C_PM */
+&i2c6 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c6>;
+ pinctrl-1 = <&pinctrl_i2c6_gpio>;
+ clock-frequency = <400000>;
+ scl-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio3 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ single-master;
+};
+
+&mdio {
+ eqos_phy: ethernet-phy@1 {
+ reg = <1>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ };
+
+ fec_phy: ethernet-phy@2 {
+ reg = <2>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ };
+};
+
+/* SMARC PCIE_A */
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
+};
+
+&pcie_phy {
+ clocks = <&hsio_blk_ctrl>;
+ clock-names = "ref";
+ fsl,clkreq-unsupported;
+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
+};
+
+/* SMARC LCD1_BKLT_PWM */
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcd1_bklt_pwm1>;
+};
+
+/* SMARC LCD0_BKLT_PWM */
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcd0_bklt_pwm2>;
+};
+
+/* SMARC GPIO5 as PWM */
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio5_pwm>;
+};
+
+&snvs_pwrkey {
+ status = "okay";
+};
+
+/* SMARC SER0 */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ uart-has-rtscts;
+};
+
+/* SMARC SER2 */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ uart-has-rtscts;
+};
+
+/* On-module Bluetooth, optional SMARC SER3 */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_bt_uart>;
+ uart-has-rtscts;
+ status = "okay";
+
+ som_bt: bluetooth {
+ compatible = "mrvl,88w8997";
+ max-speed = <921600>;
+ };
+};
+
+/* SMARC SER1, used as the Linux Console */
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+};
+
+/* SMARC USB0 */
+&usb3_0 {
+ fsl,disable-port-power-control;
+};
+
+/* SMARC USB1..4 */
+&usb3_1 {
+ fsl,disable-port-power-control;
+};
+
+&usb3_phy1 {
+ vbus-supply = <®_usb1_vbus>;
+};
+
+&usb_dwc3_0 {
+ adp-disable;
+ dr_mode = "otg";
+ hnp-disable;
+ maximum-speed = "high-speed";
+ srp-disable;
+ usb-role-switch;
+
+ port {
+ usb3_0_dwc: endpoint {
+ remote-endpoint = <&usb_dr_connector>;
+ };
+ };
+};
+
+&usb_dwc3_1 {
+ dr_mode = "host";
+};
+
+/* On-module Wi-Fi */
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ keep-power-in-suspend;
+ non-removable;
+ vmmc-supply = <®_wifi_en>;
+ status = "okay";
+};
+
+/* SMARC SDIO */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc2>,
+ <&pinctrl_usdhc2_cd>,
+ <&pinctrl_usdhc2_wp>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>,
+ <&pinctrl_usdhc2_cd>,
+ <&pinctrl_usdhc2_wp>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>,
+ <&pinctrl_usdhc2_cd>,
+ <&pinctrl_usdhc2_wp>;
+ pinctrl-3 = <&pinctrl_usdhc2_sleep>,
+ <&pinctrl_usdhc2_cd_sleep>,
+ <&pinctrl_usdhc2_wp>;
+ assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
+ assigned-clock-rates = <400000000>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ vqmmc-supply = <®_usdhc2_vqmmc>;
+ wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+};
+
+/* On-module eMMC */
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
+ assigned-clock-rates = <400000000>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ /* On-module Bluetooth */
+ pinctrl_bt_uart: btuartgrp {
+ fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x1c4>, /* WiFi_UART_TXD */
+ <MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x1c4>, /* WiFi_UART_RXD */
+ <MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x1c4>, /* WiFi_UART_RTS */
+ <MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS 0x1c4>; /* WiFi_UART_CTS */
+ };
+
+ /* SMARC CAM_MCK */
+ pinctrl_csi_mclk: csimclkgrp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x16>; /* SMARC S6 - CAM_MCK */
+ };
+
+ /* SMARC SPI0 */
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c4>, /* SMARC P45 - SPI0_DIN */
+ <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x4>, /* SMARC P46 - SPI0_DO */
+ <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x4>, /* SMARC P44 - SPI0_CK */
+ <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c4>, /* SMARC P43 - SPI0_CS0# */
+ <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1c4>; /* SMARC P31 - SPI0_CS1# */
+ };
+
+ /* SMARC SPI1 */
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1c4>, /* SMARC P56 - SPI1_DIN */
+ <MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x4>, /* SMARC P57 - SPI1_DO */
+ <MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x4>, /* SMARC P58 - SPI1_CK */
+ <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c4>, /* SMARC P54 - SPI1_CS0# */
+ <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x1c4>; /* SMARC P55 - SPI1_CS1# */
+ };
+
+ /* ETH_0 RGMII (On-module PHY) */
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90>, /* ETH0_RGMII_RXD0 */
+ <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90>, /* ETH0_RGMII_RXD1 */
+ <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90>, /* ETH0_RGMII_RXD2 */
+ <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90>, /* ETH0_RGMII_RXD3 */
+ <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90>, /* ETH0_RGMII_RXC */
+ <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90>, /* ETH0_RGMII_RX_CTL */
+ <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16>, /* ETH0_RGMII_TXD0 */
+ <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16>, /* ETH0_RGMII_TXD1 */
+ <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16>, /* ETH0_RGMII_TXD2 */
+ <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16>, /* ETH0_RGMII_TXD3 */
+ <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16>, /* ETH0_RGMII_TX_CTL */
+ <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16>; /* ETH0_RGMII_TXC */
+ };
+
+ /* SMARC GBE0_SDP */
+ pinctrl_eqos_1588_event: eqos1588eventgrp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO09__ENET_QOS_1588_EVENT0_OUT 0x4>; /* SMARC P6 - GBE0_SDP */
+ };
+
+ /* ETH_0_MDIO and ETH_0_INT# shared between ETH_PHY0 and ETH_PHY1 */
+ pinctrl_eth_mdio: ethmdiogrp {
+ fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2>, /* ETH_0_MDC */
+ <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2>, /* ETH_0_MDIO */
+ <MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x80>; /* ETH_0_INT# */
+ };
+
+ /* ETH_1 RGMII (On-module PHY) */
+ pinctrl_fec: fecgrp {
+ fsl,pins = <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90>, /* ETH1_RGMII_RXD0 */
+ <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90>, /* ETH1_RGMII_RXD1 */
+ <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90>, /* ETH1_RGMII_RXD2 */
+ <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90>, /* ETH1_RGMII_RXD3 */
+ <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90>, /* ETH1_RGMII_RXC */
+ <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90>, /* ETH1_RGMII_RX_CTL */
+ <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16>, /* ETH1_RGMII_TXD0 */
+ <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16>, /* ETH1_RGMII_TXD1 */
+ <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16>, /* ETH1_RGMII_TXD2 */
+ <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16>, /* ETH1_RGMII_TXD3 */
+ <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16>, /* ETH1_RGMII_TX_CTL */
+ <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16>; /* ETH1_RGMII_TXC */
+ };
+
+ /* SMARC GBE1_SDP */
+ pinctrl_fec_1588_event: fec1588eventgrp {
+ fsl,pins = <MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x4>; /* SMARC P5 - GBE1_SDP */
+ };
+
+ /* SMARC CAN1 */
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x154>, /* SMARC P146 - CAN1_RX */
+ <MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x154>; /* SMARC P145 - CAN1_TX */
+ };
+
+ /* SMARC CAN0 */
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154>, /* SMARC P144 - CAN0_RX */
+ <MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154>; /* SMARC P143 - CAN0_TX */
+ };
+
+ /* SMARC GPIO4 */
+ pinctrl_gpio4: gpio4grp {
+ fsl,pins = <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x144>; /* SMARC P112 - GPIO4 */
+ };
+
+ /* SMARC GPIO5 */
+ pinctrl_gpio5: gpio5grp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x144>; /* SMARC P113 - GPIO5 */
+ };
+
+ /* SMARC GPIO5 as PWM */
+ pinctrl_gpio5_pwm: gpio5pwmgrp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT 0x12>; /* SMARC P113 - PWM_OUT */
+ };
+
+ /* SMARC GPIO6 */
+ pinctrl_gpio6: gpio6grp {
+ fsl,pins = <MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x144>; /* SMARC P114 - GPIO6 */
+ };
+
+ /* SMARC GPIO7 */
+ pinctrl_gpio7: gpio7grp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x144>; /* SMARC P115 - GPIO7 */
+ };
+
+ /* SMARC GPIO8 */
+ pinctrl_gpio8: gpio8grp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x144>; /* SMARC P116 - GPIO8 */
+ };
+
+ /* SMARC GPIO9 */
+ pinctrl_gpio9: gpio9grp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x144>; /* SMARC P117 - GPIO9 */
+ };
+
+ /* SMARC GPIO10 */
+ pinctrl_gpio10: gpio10grp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x144>; /* SMARC P118 - GPIO10 */
+ };
+
+ /* SMARC GPIO11 */
+ pinctrl_gpio11: gpio11grp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x144>; /* SMARC P119 - GPIO11 */
+ };
+
+ /* SMARC GPIO12 */
+ pinctrl_gpio12: gpio12grp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x144>; /* SMARC S142 - GPIO12 */
+ };
+
+ /* SMARC GPIO13 */
+ pinctrl_gpio13: gpio13grp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144>; /* SMARC S123 - GPIO13 */
+ };
+
+ /* SMARC HDMI */
+ pinctrl_hdmi: hdmigrp {
+ fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c6>, /* SMARC P105 - HDMI_CTRL_CK */
+ <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c6>, /* SMARC P106 - HDMI_CTRL_DAT */
+ <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x180>; /* SMARC P104 - HDMI_HPD */
+ };
+
+ /* On-module I2C */
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c6>, /* CTRL_I2C_SCL */
+ <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c6>; /* CTRL_I2C_SDA */
+ };
+
+ /* On-module I2C as GPIOs */
+ pinctrl_i2c1_gpio: i2c1gpiogrp {
+ fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c6>, /* CTRL_I2C_SCL */
+ <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c6>; /* CTRL_I2C_SDA */
+ };
+
+ /* SMARC I2C_LCD */
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c6>, /* SMARC S139 - I2C_LCD_CK */
+ <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c6>; /* SMARC S140 - I2C_LCD_DAT */
+ };
+
+ /* SMARC I2C_LCD as GPIOs */
+ pinctrl_i2c2_gpio: i2c2gpiogrp {
+ fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c6>, /* SMARC S139 - I2C_LCD_CK */
+ <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c6>; /* SMARC S140 - I2C_LCD_DAT */
+ };
+
+ /* SMARC I2C_CAM0 */
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c6>, /* SMARC S5 - I2C_CAM0_CK */
+ <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c6>; /* SMARC S7 - I2C_CAM0_DAT */
+ };
+
+ /* SMARC I2C_CAM0 as GPIOs */
+ pinctrl_i2c3_gpio: i2c3gpiogrp {
+ fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c6>, /* SMARC S5 - I2C_CAM0_CK */
+ <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c6>; /* SMARC S7 - I2C_CAM0_DAT */
+ };
+
+ /* SMARC I2C_GP */
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c6>, /* SMARC S48 - I2C_GP_CK */
+ <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c6>; /* SMARC S49 - I2C_GP_DAT */
+ };
+
+ /* SMARC I2C_GP as GPIOs */
+ pinctrl_i2c4_gpio: i2c4gpiogrp {
+ fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c6>, /* SMARC S48 - I2C_GP_CK */
+ <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c6>; /* SMARC S49 - I2C_GP_DAT */
+ };
+
+ /* SMARC I2C_CAM1 */
+ pinctrl_i2c5: i2c5grp {
+ fsl,pins = <MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c6>, /* SMARC S2 - I2C_CAM1_DAT */
+ <MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c6>; /* SMARC S1 - I2C_CAM1_CK */
+ };
+
+ /* SMARC I2C_CAM1 as GPIOs */
+ pinctrl_i2c5_gpio: i2c5gpiogrp {
+ fsl,pins = <MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x400001c6>, /* SMARC S2 - I2C_CAM1_DAT */
+ <MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x400001c6>; /* SMARC S1 - I2C_CAM1_CK */
+ };
+
+ /* SMARC I2C_PM */
+ pinctrl_i2c6: i2c6grp {
+ fsl,pins = <MX8MP_IOMUXC_HDMI_CEC__I2C6_SCL 0x400001c6>, /* SMARC P121 - I2C_PM_CK */
+ <MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c6>; /* SMARC P122 - I2C_PM_DAT */
+ };
+
+ /* SMARC I2C_PM as GPIOs */
+ pinctrl_i2c6_gpio: i2c6gpiogrp {
+ fsl,pins = <MX8MP_IOMUXC_HDMI_CEC__GPIO3_IO28 0x400001c6>, /* SMARC P121 - I2C_PM_CK */
+ <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x400001c6>; /* SMARC P122 - I2C_PM_DAT */
+ };
+
+ pinctrl_lvds_dsi_sel: lvdsdsiselgrp {
+ fsl,pins = <MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x104>; /* LVDS_DSI_SEL */
+ };
+
+ pinctrl_mcu_int: mcuintgrp {
+ fsl,pins = <MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x1C0>; /* MCU_INT# */
+ };
+
+ /* SMARC LCD1_BKLT_PWM */
+ pinctrl_lcd1_bklt_pwm1: pwm1grp {
+ fsl,pins = <MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x12>; /* SMARC S122 - LCD1_BKLT_PWM */
+ };
+
+ /* SMARC LCD0_BKLT_PWM */
+ pinctrl_lcd0_bklt_pwm2: pwm2grp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x12>; /* SMARC S141 - LCD0_BKLT_PWM */
+ };
+
+ /* PCAL6408 Interrupt */
+ pinctrl_pcal6408: pcal6408intgrp {
+ fsl,pins = <MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x1c4>; /* GPIO_EX_INT# */
+ };
+
+ /* SMARC PCIE_A */
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x1c0>, /* SMARC S146 - PCIE_WAKE# */
+ <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x04>; /* SMARC P75 - PCIE_A_RST# */
+ };
+
+ /* PMIC Interrupt */
+ pinctrl_pmic: pmicintgrp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c4>; /* PMIC_INT# */
+ };
+
+ /* SMARC I2S0 */
+ pinctrl_sai1: sai1grp {
+ fsl,pins = <MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x94>, /* SMARC S42 - I2S0_CK */
+ <MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x94>, /* SMARC S39 - I2S0_LRCLK */
+ <MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x94>, /* SMARC S41 - I2S0_SDIN */
+ <MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x94>; /* SMARC S40 - I2S0_SDOUT */
+ };
+
+ /* SMARC AUDIO_MCK */
+ pinctrl_sai1_mclk: sai1mclkgrp {
+ fsl,pins = <MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x96>; /* SMARC S38 - AUDIO_MCK */
+ };
+
+ /* SMARC I2S2 */
+ pinctrl_sai3: sai3grp {
+ fsl,pins = <MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x94>, /* SMARC S52 - I2S2_SDIN */
+ <MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x94>, /* SMARC S53 - I2S2_CK */
+ <MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x94>, /* SMARC S51 - I2S2_SDOUT */
+ <MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x94>; /* SMARC S50 - I2S2_LRCLK */
+ };
+
+ /* SMARC SLEEP# */
+ pinctrl_sleep: sleepgrp {
+ fsl,pins = <MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x1C0>; /* SMARC S149 - SLEEP# */
+ };
+
+ /* SMARC SMB_ALERT# */
+ pinctrl_smb_alert: smbalertgrp {
+ fsl,pins = <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x1C0>; /* SMARC P1 - SMB_ALERT# */
+ };
+
+ /* TPM_CS# */
+ pinctrl_tpm_cs: tpmcsgrp {
+ fsl,pins = <MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x82>; /* TPM_CS# */
+ };
+
+ /* WIFI_BT_WKUP_HOST/TPM_INT# */
+ pinctrl_tpm_irq_wifi_bt_wkup: tpmirq-wifibtwkupgrp {
+ fsl,pins = <MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x16>; /* WIFI_BT_WKUP_HOST/TPM_INT# */
+ };
+
+ /* SMARC SER0 */
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1c4>, /* SMARC P132 - SER2_CTS */
+ <MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1c4>, /* SMARC P131 - SER2_RTS */
+ <MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x1c4>, /* SMARC P130 - SER2_RX */
+ <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x1c4>; /* SMARC P139 - SER2_TX */
+ };
+
+ /* SMARC SER2 */
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x1c4>, /* SMARC P139 - SER2_CTS */
+ <MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x1c4>, /* SMARC P138 - SER2_RTS */
+ <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x1c4>, /* SMARC P137 - SER2_RX */
+ <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x1c4>; /* SMARC P136 - SER2_TX */
+ };
+
+ /* SMARC SER3 */
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x1c4>, /* SMARC P141 - SER3_RX */
+ <MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x1c4>; /* SMARC P140 - SER3_TX */
+ };
+
+ /* SMARC SER1 */
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x1c4>, /* SMARC P135 - SER1_RX */
+ <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x1c4>; /* SMARC P134 - SER1_TX */
+ };
+
+ /* SMARC USB0_OTG_ID */
+ pinctrl_usb0_id: usb0idgrp {
+ fsl,pins = <MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1c4>; /* SMARC P64 - USB0_OTG_ID */
+ };
+
+ /* SMARC USB0_EN_OC# */
+ pinctrl_usb0_en_oc: usb0enocgrp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x04>; /* SMARC P62 - USB0_EN_OC# */
+ };
+
+ /* On module USB Hub VBUS, or SMARC USB2_EN_OC# depending on assembling */
+ pinctrl_usb1_en_oc: usb1enocgrp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x04>; /* SMARC P71 - USB2_EN_OC# */
+ };
+
+ /* On-module Wi-Fi */
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190>, /* WiFi_SDIO_CLK */
+ <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0>, /* WiFi_SDIO_CMD */
+ <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0>, /* WiFi_SDIO_DATA0 */
+ <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0>, /* WiFi_SDIO_DATA1 */
+ <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0>, /* WiFi_SDIO_DATA2 */
+ <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0>; /* WiFi_SDIO_DATA3 */
+ };
+
+ /* On-module Wi-Fi */
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194>, /* WiFi_SDIO_CLK */
+ <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4>, /* WiFi_SDIO_CMD */
+ <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4>, /* WiFi_SDIO_DATA0 */
+ <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4>, /* WiFi_SDIO_DATA1 */
+ <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4>, /* WiFi_SDIO_DATA2 */
+ <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4>; /* WiFi_SDIO_DATA3 */
+ };
+
+ /* On-module Wi-Fi */
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196>, /* WiFi_SDIO_CLK */
+ <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6>, /* WiFi_SDIO_CMD */
+ <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6>, /* WiFi_SDIO_DATA0 */
+ <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6>, /* WiFi_SDIO_DATA1 */
+ <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6>, /* WiFi_SDIO_DATA2 */
+ <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6>; /* WiFi_SDIO_DATA3 */
+ };
+
+ /* SMARC SDIO */
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190>, /* SMARC P36 - SDIO_CK */
+ <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0>, /* SMARC P34 - SDIO_CMD */
+ <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0>, /* SMARC P39 - SDIO_DO */
+ <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0>, /* SMARC P40 - SDIO_D1 */
+ <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0>, /* SMARC P41 - SDIO_D2 */
+ <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0>; /* SMARC P42 - SDIO_D3 */
+ };
+
+ /* SMARC SDIO 100MHz */
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, /* SMARC P36 - SDIO_CK */
+ <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, /* SMARC P34 - SDIO_CMD */
+ <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, /* SMARC P39 - SDIO_DO */
+ <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, /* SMARC P40 - SDIO_D1 */
+ <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, /* SMARC P41 - SDIO_D2 */
+ <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; /* SMARC P42 - SDIO_D3 */
+ };
+
+ /* SMARC SDIO 200MHz */
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196>, /* SMARC P36 - SDIO_CK */
+ <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6>, /* SMARC P34 - SDIO_CMD */
+ <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6>, /* SMARC P39 - SDIO_DO */
+ <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6>, /* SMARC P40 - SDIO_D1 */
+ <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6>, /* SMARC P41 - SDIO_D2 */
+ <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6>; /* SMARC P42 - SDIO_D3 */
+ };
+
+ /* SMARC SDIO_CD# */
+ pinctrl_usdhc2_cd: usdhc2cdgrp {
+ fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4>; /* SMARC P35 - SDIO_CD# */
+ };
+
+ /* SMARC SDIO_CD# */
+ pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
+ fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0>; /* SMARC P35 - SDIO_CD# */
+ };
+
+ /* SMARC SDIO_PWR_EN */
+ pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
+ fsl,pins = <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x1c4>; /* SMARC P37 - SDIO_PWR_EN */
+ };
+
+ /* SMARC SDIO Sleep - Avoid backfeeding with removed card power */
+ pinctrl_usdhc2_sleep: usdhc2slpgrp {
+ fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x100>, /* SMARC P36 - SDIO_CK */
+ <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x100>, /* SMARC P34 - SDIO_CMD */
+ <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x100>, /* SMARC P39 - SDIO_DO */
+ <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x100>, /* SMARC P39 - SDIO_D1 */
+ <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x100>, /* SMARC P39 - SDIO_D2 */
+ <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x100>; /* SMARC P39 - SDIO_D3 */
+ };
+
+ pinctrl_usdhc2_vsel: usdhc2vselgrp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x4>; /* PMIC_USDHC_VSELECT */
+ };
+
+ /* SMARC SDIO_WP */
+ pinctrl_usdhc2_wp: usdhc2wpgrp {
+ fsl,pins = <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x144>; /* SMARC P33 - SDIO_WP */
+ };
+
+ /* On-module eMMC */
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190>, /* eMMC_STROBE */
+ <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0>, /* eMMC_DATA5 */
+ <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0>, /* eMMC_DATA6 */
+ <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0>, /* eMMC_DATA7 */
+ <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0>, /* eMMC_DATA0 */
+ <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0>, /* eMMC_DATA1 */
+ <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0>, /* eMMC_DATA2 */
+ <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0>, /* eMMC_DATA3 */
+ <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0>, /* eMMC_DATA4 */
+ <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190>, /* eMMC_CLK */
+ <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0>; /* eMMC_CMD */
+ };
+
+ /* On-module eMMC */
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194>, /* eMMC_STROBE */
+ <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, /* eMMC_DATA5 */
+ <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, /* eMMC_DATA6 */
+ <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, /* eMMC_DATA7 */
+ <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, /* eMMC_DATA0 */
+ <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, /* eMMC_DATA1 */
+ <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, /* eMMC_DATA2 */
+ <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, /* eMMC_DATA3 */
+ <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, /* eMMC_DATA4 */
+ <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, /* eMMC_CLK */
+ <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>; /* eMMC_CMD */
+ };
+
+ /* On-module eMMC */
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196>, /* eMMC_STROBE */
+ <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2>, /* eMMC_DATA5 */
+ <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2>, /* eMMC_DATA6 */
+ <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2>, /* eMMC_DATA7 */
+ <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2>, /* eMMC_DATA0 */
+ <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2>, /* eMMC_DATA1 */
+ <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2>, /* eMMC_DATA2 */
+ <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2>, /* eMMC_DATA3 */
+ <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2>, /* eMMC_DATA4 */
+ <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196>, /* eMMC_CLK */
+ <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6>; /* eMMC_CMD */
+ };
+
+ /* SoC Watchdog */
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x4>; /* CTRL_SOC_WDOG */
+ };
+
+ /* On-module Wi-Fi power enable */
+ pinctrl_wifi_pwr_en: wifipwrengrp {
+ fsl,pins = <MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x104>; /* CTRL_EN_WIFI */
+ };
+};
diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
index c9a610b..ce6793b 100644
--- a/arch/arm/dts/imx8mp.dtsi
+++ b/arch/arm/dts/imx8mp.dtsi
@@ -47,6 +47,20 @@
#address-cells = <1>;
#size-cells = <0>;
+ idle-states {
+ entry-method = "psci";
+
+ cpu_pd_wait: cpu-pd-wait {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010033>;
+ local-timer-stop;
+ entry-latency-us = <1000>;
+ exit-latency-us = <700>;
+ min-residency-us = <2700>;
+ wakeup-latency-us = <1500>;
+ };
+ };
+
A53_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
@@ -65,6 +79,7 @@
nvmem-cell-names = "speed_grade";
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
+ cpu-idle-states = <&cpu_pd_wait>;
};
A53_1: cpu@1 {
@@ -83,6 +98,7 @@
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
+ cpu-idle-states = <&cpu_pd_wait>;
};
A53_2: cpu@2 {
@@ -101,6 +117,7 @@
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
+ cpu-idle-states = <&cpu_pd_wait>;
};
A53_3: cpu@3 {
@@ -119,6 +136,7 @@
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
+ cpu-idle-states = <&cpu_pd_wait>;
};
A53_L2: l2-cache0 {
@@ -264,6 +282,7 @@
dsp_reserved: dsp@92400000 {
reg = <0 0x92400000 0 0x2000000>;
no-map;
+ status = "disabled";
};
};
@@ -726,6 +745,8 @@
clk: clock-controller@30380000 {
compatible = "fsl,imx8mp-ccm";
reg = <0x30380000 0x10000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#clock-cells = <1>;
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
<&clk_ext3>, <&clk_ext4>;
@@ -786,6 +807,23 @@
reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
};
+ pgc_mlmix: power-domain@4 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MP_POWER_DOMAIN_MLMIX>;
+ clocks = <&clk IMX8MP_CLK_ML_AXI>,
+ <&clk IMX8MP_CLK_ML_AHB>,
+ <&clk IMX8MP_CLK_NPU_ROOT>;
+ assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>,
+ <&clk IMX8MP_CLK_ML_AXI>,
+ <&clk IMX8MP_CLK_ML_AHB>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
+ <&clk IMX8MP_SYS_PLL1_800M>,
+ <&clk IMX8MP_SYS_PLL1_800M>;
+ assigned-clock-rates = <1000000000>,
+ <800000000>,
+ <400000000>;
+ };
+
pgc_audio: power-domain@5 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>;
@@ -793,10 +831,10 @@
<&clk IMX8MP_CLK_AUDIO_AXI>;
assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>,
<&clk IMX8MP_CLK_AUDIO_AXI_SRC>;
- assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
- <&clk IMX8MP_SYS_PLL1_800M>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
+ <&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <400000000>,
- <600000000>;
+ <800000000>;
};
pgc_gpu2d: power-domain@6 {
@@ -818,6 +856,12 @@
assigned-clock-rates = <800000000>, <400000000>;
};
+ pgc_vpumix: power-domain@8 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MP_POWER_DOMAIN_VPUMIX>;
+ clocks = <&clk IMX8MP_CLK_VPU_ROOT>;
+ };
+
pgc_gpu3d: power-domain@9 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_GPU3D>;
@@ -833,60 +877,64 @@
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
};
- pgc_mipi_phy2: power-domain@16 {
+ pgc_vpu_g1: power-domain@11 {
#power-domain-cells = <0>;
- reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
+ power-domains = <&pgc_vpumix>;
+ reg = <IMX8MP_POWER_DOMAIN_VPU_G1>;
+ clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
};
- pgc_hsiomix: power-domain@17 {
+ pgc_vpu_g2: power-domain@12 {
#power-domain-cells = <0>;
- reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
- clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
- <&clk IMX8MP_CLK_HSIO_ROOT>;
- assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
- assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
- assigned-clock-rates = <500000000>;
+ power-domains = <&pgc_vpumix>;
+ reg = <IMX8MP_POWER_DOMAIN_VPU_G2>;
+ clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
+
};
- pgc_ispdwp: power-domain@18 {
+ pgc_vpu_vc8000e: power-domain@13 {
#power-domain-cells = <0>;
- reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
- clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>;
+ power-domains = <&pgc_vpumix>;
+ reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
+ clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
};
- pgc_vpumix: power-domain@19 {
+ pgc_hdmimix: power-domain@14 {
#power-domain-cells = <0>;
- reg = <IMX8MP_POWER_DOMAIN_VPUMIX>;
- clocks = <&clk IMX8MP_CLK_VPU_ROOT>;
+ reg = <IMX8MP_POWER_DOMAIN_HDMIMIX>;
+ clocks = <&clk IMX8MP_CLK_HDMI_ROOT>,
+ <&clk IMX8MP_CLK_HDMI_APB>;
+ assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>,
+ <&clk IMX8MP_CLK_HDMI_APB>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>,
+ <&clk IMX8MP_SYS_PLL1_133M>;
+ assigned-clock-rates = <500000000>, <133000000>;
};
- pgc_vpu_g1: power-domain@20 {
+ pgc_hdmi_phy: power-domain@15 {
#power-domain-cells = <0>;
- power-domains = <&pgc_vpumix>;
- reg = <IMX8MP_POWER_DOMAIN_VPU_G1>;
- clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
+ reg = <IMX8MP_POWER_DOMAIN_HDMI_PHY>;
};
- pgc_vpu_g2: power-domain@21 {
+ pgc_mipi_phy2: power-domain@16 {
#power-domain-cells = <0>;
- power-domains = <&pgc_vpumix>;
- reg = <IMX8MP_POWER_DOMAIN_VPU_G2>;
- clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
+ reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
};
- pgc_vpu_vc8000e: power-domain@22 {
+ pgc_hsiomix: power-domain@17 {
#power-domain-cells = <0>;
- power-domains = <&pgc_vpumix>;
- reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
- clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
+ reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
+ clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
+ <&clk IMX8MP_CLK_HSIO_ROOT>;
+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
+ assigned-clock-rates = <500000000>;
};
- pgc_mlmix: power-domain@24 {
+ pgc_ispdwp: power-domain@18 {
#power-domain-cells = <0>;
- reg = <IMX8MP_POWER_DOMAIN_MLMIX>;
- clocks = <&clk IMX8MP_CLK_ML_AXI>,
- <&clk IMX8MP_CLK_ML_AHB>,
- <&clk IMX8MP_CLK_NPU_ROOT>;
+ reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
+ clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>;
};
};
};
@@ -1231,7 +1279,7 @@
compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b40000 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MP_CLK_DUMMY>,
+ clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
<&clk IMX8MP_CLK_NAND_USDHC_BUS>,
<&clk IMX8MP_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per";
@@ -1245,7 +1293,7 @@
compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b50000 0x10000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MP_CLK_DUMMY>,
+ clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
<&clk IMX8MP_CLK_NAND_USDHC_BUS>,
<&clk IMX8MP_CLK_USDHC2_ROOT>;
clock-names = "ipg", "ahb", "per";
@@ -1259,7 +1307,7 @@
compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b60000 0x10000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MP_CLK_DUMMY>,
+ clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
<&clk IMX8MP_CLK_NAND_USDHC_BUS>,
<&clk IMX8MP_CLK_USDHC3_ROOT>;
clock-names = "ipg", "ahb", "per";
@@ -1501,6 +1549,41 @@
status = "disabled";
};
+ aud2htx: aud2htx@30cb0000 {
+ compatible = "fsl,imx8mp-aud2htx";
+ reg = <0x30cb0000 0x10000>;
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG>;
+ clock-names = "bus";
+ dmas = <&sdma2 26 2 0>;
+ dma-names = "tx";
+ status = "disabled";
+ };
+
+ xcvr: xcvr@30cc0000 {
+ compatible = "fsl,imx8mp-xcvr";
+ reg = <0x30cc0000 0x800>,
+ <0x30cc0800 0x400>,
+ <0x30cc0c00 0x080>,
+ <0x30cc0e00 0x080>;
+ reg-names = "ram", "regs", "rxfifo",
+ "txfifo";
+ interrupts = /* XCVR IRQ 0 */
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ /* XCVR IRQ 1 */
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ /* XCVR PHY - SPDIF wakeup IRQ */
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_EARC_IPG>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_EARC_PHY>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT>;
+ clock-names = "ipg", "phy", "spba", "pll_ipg";
+ dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>;
+ dma-names = "rx", "tx";
+ resets = <&audio_blk_ctrl 0>;
+ status = "disabled";
+ };
};
sdma3: dma-controller@30e00000 {
@@ -1529,17 +1612,22 @@
compatible = "fsl,imx8mp-audio-blk-ctrl";
reg = <0x30e20000 0x10000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
<&clk IMX8MP_CLK_SAI1>,
<&clk IMX8MP_CLK_SAI2>,
<&clk IMX8MP_CLK_SAI3>,
<&clk IMX8MP_CLK_SAI5>,
<&clk IMX8MP_CLK_SAI6>,
- <&clk IMX8MP_CLK_SAI7>;
+ <&clk IMX8MP_CLK_SAI7>,
+ <&clk IMX8MP_CLK_AUDIO_AXI_ROOT>;
clock-names = "ahb",
"sai1", "sai2", "sai3",
- "sai5", "sai6", "sai7";
+ "sai5", "sai6", "sai7", "axi";
power-domains = <&pgc_audio>;
+ assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>,
+ <&clk IMX8MP_AUDIO_PLL2>;
+ assigned-clock-rates = <393216000>, <361267200>;
};
};
@@ -1604,6 +1692,50 @@
};
};
+ isp_0: isp@32e10000 {
+ compatible = "fsl,imx8mp-isp";
+ reg = <0x32e10000 0x10000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
+ clock-names = "isp", "aclk", "hclk";
+ power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
+ fsl,blk-ctrl = <&media_blk_ctrl 0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ isp_1: isp@32e20000 {
+ compatible = "fsl,imx8mp-isp";
+ reg = <0x32e20000 0x10000>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
+ clock-names = "isp", "aclk", "hclk";
+ power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
+ fsl,blk-ctrl = <&media_blk_ctrl 1>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
dewarp: dwe@32e30000 {
compatible = "nxp,imx8mp-dw100";
reg = <0x32e30000 0x10000>;
@@ -1618,15 +1750,16 @@
compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
reg = <0x32e40000 0x10000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <500000000>;
+ clock-frequency = <250000000>;
clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
<&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
clock-names = "pclk", "wrap", "phy", "axi";
- assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>;
- assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
- assigned-clock-rates = <500000000>;
+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>,
+ <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>,
+ <&clk IMX8MP_CLK_24M>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
status = "disabled";
@@ -1652,15 +1785,16 @@
compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
reg = <0x32e50000 0x10000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <266000000>;
+ clock-frequency = <250000000>;
clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
<&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
clock-names = "pclk", "wrap", "phy", "axi";
- assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>;
- assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
- assigned-clock-rates = <266000000>;
+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>,
+ <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>,
+ <&clk IMX8MP_CLK_24M>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>;
status = "disabled";
@@ -1709,6 +1843,13 @@
remote-endpoint = <&lcdif1_to_dsim>;
};
};
+
+ port@1 {
+ reg = <1>;
+
+ mipi_dsi_out: endpoint {
+ };
+ };
};
};
@@ -1791,24 +1932,33 @@
clock-names = "apb", "axi", "cam1", "cam2",
"disp1", "disp2", "isp", "phy";
+ /*
+ * The ISP maximum frequency is 400MHz in normal mode
+ * and 500MHz in overdrive mode. The 400MHz operating
+ * point hasn't been successfully tested yet, so set
+ * IMX8MP_CLK_MEDIA_ISP to 500MHz for the time being.
+ */
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
<&clk IMX8MP_CLK_MEDIA_APB>,
<&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
<&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
+ <&clk IMX8MP_CLK_MEDIA_ISP>,
<&clk IMX8MP_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_VIDEO_PLL1_OUT>,
- <&clk IMX8MP_VIDEO_PLL1_OUT>;
+ <&clk IMX8MP_VIDEO_PLL1_OUT>,
+ <&clk IMX8MP_SYS_PLL2_500M>;
assigned-clock-rates = <500000000>, <200000000>,
- <0>, <0>, <1039500000>;
+ <0>, <0>, <500000000>,
+ <1039500000>;
#power-domain-cells = <1>;
lvds_bridge: bridge@5c {
compatible = "fsl,imx8mp-ldb";
reg = <0x5c 0x4>, <0x128 0x4>;
reg-names = "ldb", "lvds";
- clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
+ clocks = <&clk IMX8MP_CLK_MEDIA_LDB_ROOT>;
clock-names = "ldb";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
@@ -1873,6 +2023,136 @@
#power-domain-cells = <1>;
#clock-cells = <0>;
};
+
+ hdmi_blk_ctrl: blk-ctrl@32fc0000 {
+ compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon";
+ reg = <0x32fc0000 0x1000>;
+ clocks = <&clk IMX8MP_CLK_HDMI_APB>,
+ <&clk IMX8MP_CLK_HDMI_ROOT>,
+ <&clk IMX8MP_CLK_HDMI_REF_266M>,
+ <&clk IMX8MP_CLK_HDMI_24M>,
+ <&clk IMX8MP_CLK_HDMI_FDCC_TST>;
+ clock-names = "apb", "axi", "ref_266m", "ref_24m", "fdcc";
+ power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>,
+ <&pgc_hdmimix>, <&pgc_hdmimix>,
+ <&pgc_hdmimix>, <&pgc_hdmimix>,
+ <&pgc_hdmimix>, <&pgc_hdmi_phy>,
+ <&pgc_hdmimix>, <&pgc_hdmimix>;
+ power-domain-names = "bus", "irqsteer", "lcdif",
+ "pai", "pvi", "trng",
+ "hdmi-tx", "hdmi-tx-phy",
+ "hdcp", "hrv";
+ #power-domain-cells = <1>;
+ };
+
+ irqsteer_hdmi: interrupt-controller@32fc2000 {
+ compatible = "fsl,imx8mp-irqsteer", "fsl,imx-irqsteer";
+ reg = <0x32fc2000 0x1000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ fsl,channel = <1>;
+ fsl,num-irqs = <64>;
+ clocks = <&clk IMX8MP_CLK_HDMI_APB>;
+ clock-names = "ipg";
+ power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>;
+ };
+
+ hdmi_pvi: display-bridge@32fc4000 {
+ compatible = "fsl,imx8mp-hdmi-pvi";
+ reg = <0x32fc4000 0x1000>;
+ interrupt-parent = <&irqsteer_hdmi>;
+ interrupts = <12>;
+ power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ pvi_from_lcdif3: endpoint {
+ remote-endpoint = <&lcdif3_to_pvi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ pvi_to_hdmi_tx: endpoint {
+ remote-endpoint = <&hdmi_tx_from_pvi>;
+ };
+ };
+ };
+ };
+
+ lcdif3: display-controller@32fc6000 {
+ compatible = "fsl,imx8mp-lcdif";
+ reg = <0x32fc6000 0x1000>;
+ interrupt-parent = <&irqsteer_hdmi>;
+ interrupts = <8>;
+ clocks = <&hdmi_tx_phy>,
+ <&clk IMX8MP_CLK_HDMI_APB>,
+ <&clk IMX8MP_CLK_HDMI_ROOT>;
+ clock-names = "pix", "axi", "disp_axi";
+ power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_LCDIF>;
+ status = "disabled";
+
+ port {
+ lcdif3_to_pvi: endpoint {
+ remote-endpoint = <&pvi_from_lcdif3>;
+ };
+ };
+ };
+
+ hdmi_tx: hdmi@32fd8000 {
+ compatible = "fsl,imx8mp-hdmi-tx";
+ reg = <0x32fd8000 0x7eff>;
+ interrupt-parent = <&irqsteer_hdmi>;
+ interrupts = <0>;
+ clocks = <&clk IMX8MP_CLK_HDMI_APB>,
+ <&clk IMX8MP_CLK_HDMI_REF_266M>,
+ <&clk IMX8MP_CLK_32K>,
+ <&hdmi_tx_phy>;
+ clock-names = "iahb", "isfr", "cec", "pix";
+ assigned-clocks = <&clk IMX8MP_CLK_HDMI_REF_266M>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>;
+ power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>;
+ reg-io-width = <1>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hdmi_tx_from_pvi: endpoint {
+ remote-endpoint = <&pvi_to_hdmi_tx>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ /* Point endpoint to the HDMI connector */
+ };
+ };
+ };
+
+ hdmi_tx_phy: phy@32fdff00 {
+ compatible = "fsl,imx8mp-hdmi-phy";
+ reg = <0x32fdff00 0x100>;
+ clocks = <&clk IMX8MP_CLK_HDMI_APB>,
+ <&clk IMX8MP_CLK_HDMI_24M>;
+ clock-names = "apb", "ref";
+ assigned-clocks = <&clk IMX8MP_CLK_HDMI_24M>;
+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+ power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>;
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
};
pcie: pcie@33800000 {
@@ -1915,8 +2195,11 @@
pcie_ep: pcie-ep@33800000 {
compatible = "fsl,imx8mp-pcie-ep";
- reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>;
- reg-names = "dbi", "addr_space";
+ reg = <0x33800000 0x100000>,
+ <0x18000000 0x8000000>,
+ <0x33900000 0x100000>,
+ <0x33b00000 0x100000>;
+ reg-names = "dbi", "addr_space", "dbi2", "atu";
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_HSIO_AXI>,
<&clk IMX8MP_CLK_PCIE_ROOT>;
@@ -1950,9 +2233,9 @@
clock-names = "core", "shader", "bus", "reg";
assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
<&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
- assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
- <&clk IMX8MP_SYS_PLL1_800M>;
- assigned-clock-rates = <800000000>, <800000000>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
+ <&clk IMX8MP_SYS_PLL2_1000M>;
+ assigned-clock-rates = <1000000000>, <1000000000>;
power-domains = <&pgc_gpu3d>;
};
@@ -1965,8 +2248,8 @@
<&clk IMX8MP_CLK_GPU_AHB>;
clock-names = "core", "bus", "reg";
assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
- assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
- assigned-clock-rates = <800000000>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
+ assigned-clock-rates = <1000000000>;
power-domains = <&pgc_gpu2d>;
};
@@ -2012,6 +2295,18 @@
interconnect-names = "g1", "g2", "vc8000e";
};
+ npu: npu@38500000 {
+ compatible = "vivante,gc";
+ reg = <0x38500000 0x200000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MP_CLK_NPU_ROOT>,
+ <&clk IMX8MP_CLK_NPU_ROOT>,
+ <&clk IMX8MP_CLK_ML_AXI>,
+ <&clk IMX8MP_CLK_ML_AHB>;
+ clock-names = "core", "shader", "bus", "reg";
+ power-domains = <&pgc_mlmix>;
+ };
+
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";
reg = <0x38800000 0x10000>,
@@ -2072,6 +2367,7 @@
phys = <&usb3_phy0>, <&usb3_phy0>;
phy-names = "usb2-phy", "usb3-phy";
snps,gfladj-refclk-lpm-sel-quirk;
+ snps,parkmode-disable-ss-quirk;
};
};
@@ -2114,6 +2410,7 @@
phys = <&usb3_phy1>, <&usb3_phy1>;
phy-names = "usb2-phy", "usb3-phy";
snps,gfladj-refclk-lpm-sel-quirk;
+ snps,parkmode-disable-ss-quirk;
};
};
diff --git a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
index 52c9caf..c001e2c 100644
--- a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
@@ -42,6 +42,10 @@
bootph-all;
};
+&phy_gmii_sel {
+ bootph-all;
+};
+
&fss {
bootph-all;
};
@@ -86,16 +90,6 @@
&main_pktdma {
bootph-all;
- reg = <0x00 0x485c0000 0x00 0x100>,
- <0x00 0x4a800000 0x00 0x20000>,
- <0x00 0x4aa00000 0x00 0x20000>,
- <0x00 0x4b800000 0x00 0x200000>,
- <0x00 0x485e0000 0x00 0x10000>,
- <0x00 0x484a0000 0x00 0x2000>,
- <0x00 0x484c0000 0x00 0x2000>,
- <0x00 0x48430000 0x00 0x1000>;
- reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
- "cfg", "tchan", "rchan", "rflow";
};
&main_rgmii1_pins_default {
diff --git a/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi
index 5a52f3d..f922f4b 100644
--- a/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi
@@ -66,7 +66,7 @@
};
&cpsw_port2 {
- bootph-all;
+ status = "disabled";
};
&dmsc {
diff --git a/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi b/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi
index 7dfbeb1..a70fc88 100644
--- a/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi
@@ -100,6 +100,10 @@
bootph-all;
};
+&sdhci0 {
+ bootph-all;
+};
+
&sdhci1 {
bootph-all;
};
diff --git a/arch/arm/dts/px30-evb-u-boot.dtsi b/arch/arm/dts/px30-evb-u-boot.dtsi
deleted file mode 100644
index 61b1433..0000000
--- a/arch/arm/dts/px30-evb-u-boot.dtsi
+++ /dev/null
@@ -1,10 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * (C) Copyright 2020 Rockchip Electronics Co., Ltd
- */
-
-#include "px30-u-boot.dtsi"
-
-&rng {
- status = "okay";
-};
diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi
index abc6b49..157d0ea 100644
--- a/arch/arm/dts/px30-u-boot.dtsi
+++ b/arch/arm/dts/px30-u-boot.dtsi
@@ -24,7 +24,6 @@
rng: rng@ff0b0000 {
compatible = "rockchip,cryptov2-rng";
reg = <0x0 0xff0b0000 0x0 0x4000>;
- status = "disabled";
};
};
diff --git a/arch/arm/dts/rk3328-generic-u-boot.dtsi b/arch/arm/dts/rk3328-generic-u-boot.dtsi
new file mode 100644
index 0000000..af890e9
--- /dev/null
+++ b/arch/arm/dts/rk3328-generic-u-boot.dtsi
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3328-u-boot.dtsi"
+
+&gpio0 {
+ /delete-property/ bootph-pre-ram;
+};
+
+&pcfg_pull_down_4ma {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&spi0 {
+ flash@0 {
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+};
+
+&spi0m2_clk {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&spi0m2_cs0 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&spi0m2_rx {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&spi0m2_tx {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
diff --git a/arch/arm/dts/rk3328-generic.dts b/arch/arm/dts/rk3328-generic.dts
new file mode 100644
index 0000000..af0da84
--- /dev/null
+++ b/arch/arm/dts/rk3328-generic.dts
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Minimal generic DT for RK3328 with eMMC, SD-card, SPI flash and USB OTG enabled
+ */
+
+/dts-v1/;
+#include "rk3328.dtsi"
+
+/ {
+ model = "Generic RK3328";
+ compatible = "rockchip,rk3328";
+
+ aliases {
+ mmc0 = &emmc;
+ mmc1 = &sdmmc;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ no-sd;
+ no-sdio;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ status = "okay";
+};
+
+&sdmmc0m1_pin {
+ rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_down_4ma>;
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ no-mmc;
+ no-sdio;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4 &sdmmc0m1_pin>;
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+ };
+};
+
+&u2phy {
+ status = "okay";
+};
+
+&u2phy_otg {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb20_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3399-generic-u-boot.dtsi b/arch/arm/dts/rk3399-generic-u-boot.dtsi
new file mode 100644
index 0000000..d977b64
--- /dev/null
+++ b/arch/arm/dts/rk3399-generic-u-boot.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3399-u-boot.dtsi"
+
+&spi1 {
+ flash@0 {
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+};
diff --git a/arch/arm/dts/rk3399-generic.dts b/arch/arm/dts/rk3399-generic.dts
new file mode 100644
index 0000000..c698f59
--- /dev/null
+++ b/arch/arm/dts/rk3399-generic.dts
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Minimal generic DT for RK3399 with eMMC, SD-card, SPI flash and USB OTG enabled
+ */
+
+/dts-v1/;
+#include "rk3399.dtsi"
+
+/ {
+ model = "Generic RK3399";
+ compatible = "rockchip,rk3399";
+
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+};
+
+&emmc_phy {
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ max-frequency = <150000000>;
+ mmc-hs200-1_8v;
+ mmc-ddr-1_8v;
+ no-sd;
+ no-sdio;
+ non-removable;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ max-frequency = <150000000>;
+ no-mmc;
+ no-sdio;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>;
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+ };
+};
+
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usbdrd3_0 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ dr_mode = "peripheral";
+ maximum-speed = "high-speed";
+ phys = <&u2phy0_otg>;
+ phy-names = "usb2-phy";
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3528-generic-u-boot.dtsi b/arch/arm/dts/rk3528-generic-u-boot.dtsi
new file mode 100644
index 0000000..cc830b5
--- /dev/null
+++ b/arch/arm/dts/rk3528-generic-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3528-u-boot.dtsi"
+
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ no-mmc;
+ no-sdio;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3528-generic.dts b/arch/arm/dts/rk3528-generic.dts
new file mode 100644
index 0000000..792d3e0
--- /dev/null
+++ b/arch/arm/dts/rk3528-generic.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Minimal generic DT for RK3528 with eMMC enabled
+ */
+
+/dts-v1/;
+#include "rk3528.dtsi"
+
+/ {
+ model = "Generic RK3528";
+ compatible = "rockchip,rk3528";
+
+ chosen {
+ stdout-path = "serial0:1500000n8";
+ };
+};
+
+&sdhci {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ no-sd;
+ no-sdio;
+ non-removable;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0m0_xfer>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
new file mode 100644
index 0000000..9c2f03a
--- /dev/null
+++ b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3528-u-boot.dtsi"
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ vmmc-supply = <&vcc_3v3>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3528-u-boot.dtsi b/arch/arm/dts/rk3528-u-boot.dtsi
new file mode 100644
index 0000000..eb6a55c
--- /dev/null
+++ b/arch/arm/dts/rk3528-u-boot.dtsi
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rockchip-u-boot.dtsi"
+
+/ {
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ };
+
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
+ };
+
+ dmc {
+ compatible = "rockchip,rk3528-dmc";
+ bootph-all;
+ };
+
+ soc {
+ rng: rng@ffc50000 {
+ compatible = "rockchip,rkrng";
+ reg = <0x0 0xffc50000 0x0 0x200>;
+ };
+
+ otp: nvmem@ffce0000 {
+ compatible = "rockchip,rk3528-otp";
+ reg = <0x0 0xffce0000 0x0 0x4000>;
+ };
+
+ sdmmc: mmc@ffc30000 {
+ compatible = "rockchip,rk3528-dw-mshc",
+ "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xffc30000 0x0 0x4000>;
+ clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>,
+ <&sdmmc_det>;
+ resets = <&cru SRST_H_SDMMC0>;
+ reset-names = "reset";
+ rockchip,default-sample-phase = <90>;
+ status = "disabled";
+ };
+ };
+};
+
+&cru {
+ bootph-all;
+};
+
+&emmc_bus8 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&emmc_clk {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&emmc_cmd {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&emmc_strb {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gmac0_clk {
+ bootph-all;
+};
+
+&ioc_grf {
+ bootph-all;
+};
+
+&otp {
+ bootph-some-ram;
+};
+
+&pcfg_pull_none {
+ bootph-all;
+};
+
+&pcfg_pull_up {
+ bootph-all;
+};
+
+&pcfg_pull_up_drv_level_2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pinctrl {
+ bootph-all;
+};
+
+&sdhci {
+ bootph-pre-ram;
+ bootph-some-ram;
+ u-boot,spl-fifo-mode;
+};
+
+&sdmmc {
+ bootph-pre-ram;
+ bootph-some-ram;
+ u-boot,spl-fifo-mode;
+};
+
+&sdmmc_bus4 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdmmc_clk {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdmmc_cmd {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdmmc_det {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&uart0 {
+ bootph-all;
+ clock-frequency = <24000000>;
+};
+
+&uart0m0_xfer {
+ bootph-pre-sram;
+ bootph-pre-ram;
+};
+
+&xin24m {
+ bootph-all;
+};
diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi
index 24a976c..8718697 100644
--- a/arch/arm/dts/rk356x-u-boot.dtsi
+++ b/arch/arm/dts/rk356x-u-boot.dtsi
@@ -21,11 +21,6 @@
bootph-all;
};
- rng: rng@fe388000 {
- compatible = "rockchip,cryptov2-rng";
- reg = <0x0 0xfe388000 0x0 0x2000>;
- };
-
otp: nvmem@fe38c000 {
compatible = "rockchip,rk3568-otp";
reg = <0x0 0xfe38c000 0x0 0x4000>;
@@ -121,6 +116,10 @@
bootph-all;
};
+&rng {
+ status = "okay";
+};
+
&sdhci {
bootph-pre-ram;
bootph-some-ram;
diff --git a/arch/arm/dts/rk3576-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3576-roc-pc-u-boot.dtsi
new file mode 100644
index 0000000..9724034
--- /dev/null
+++ b/arch/arm/dts/rk3576-roc-pc-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Joshua Riek <jjriek@verizon.net>
+ *
+ */
+
+#include "rk3576-u-boot.dtsi"
+
+&sdhci {
+ cap-mmc-highspeed;
+};
diff --git a/arch/arm/dts/rk3576-u-boot.dtsi b/arch/arm/dts/rk3576-u-boot.dtsi
new file mode 100644
index 0000000..be99a48
--- /dev/null
+++ b/arch/arm/dts/rk3576-u-boot.dtsi
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * (C) Copyright 2025 Rockchip Electronics Co., Ltd
+ */
+
+#include "rockchip-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
+ };
+
+ dmc {
+ compatible = "rockchip,rk3576-dmc";
+ bootph-all;
+ };
+};
+
+&cru {
+ bootph-all;
+};
+
+&emmc_bus8 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&emmc_clk {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&emmc_cmd {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&emmc_rstnout {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&emmc_strb {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&ioc_grf {
+ bootph-all;
+};
+
+&pcfg_pull_none {
+ bootph-all;
+};
+
+&pcfg_pull_up {
+ bootph-all;
+};
+
+&pcfg_pull_up_drv_level_2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pcfg_pull_up_drv_level_3 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pinctrl {
+ bootph-all;
+};
+
+&pmu1_grf {
+ bootph-all;
+};
+
+&sdhci {
+ bootph-pre-ram;
+ bootph-some-ram;
+ u-boot,spl-fifo-mode;
+};
+
+&sdmmc {
+ bootph-pre-ram;
+ bootph-some-ram;
+ u-boot,spl-fifo-mode;
+};
+
+&sdmmc0_bus4 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdmmc0_clk {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdmmc0_cmd {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdmmc0_det {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdmmc0_pwren {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sys_grf {
+ bootph-all;
+};
+
+&uart0 {
+ bootph-all;
+ clock-frequency = <24000000>;
+};
+
+&uart0m0_xfer {
+ bootph-pre-sram;
+ bootph-pre-ram;
+};
+
+&xin24m {
+ bootph-all;
+};
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index 8880d16..5eeb138 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -18,11 +18,6 @@
compatible = "rockchip,rk3588-dmc";
bootph-all;
};
-
- rng: rng@fe378000 {
- compatible = "rockchip,trngv1";
- reg = <0x0 0xfe378000 0x0 0x200>;
- };
};
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi
index 60de914..7631dfa 100644
--- a/arch/arm/dts/sam9x60.dtsi
+++ b/arch/arm/dts/sam9x60.dtsi
@@ -70,6 +70,19 @@
#size-cells = <1>;
ranges;
+ usb0: gadget@500000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "microchip,sam9x60-udc";
+ reg = <0x500000 0x100000>,
+ <0xf803c000 0x400>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE 8>;
+ clock-names = "pclk", "hclk";
+ assigned-clocks = <&pmc PMC_TYPE_CORE 8>;
+ assigned-clock-rates = <480000000>;
+ status = "disabled";
+ };
+
usb1: usb@600000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00600000 0x100000>;
diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi
index 7b62fff..62191ff 100644
--- a/arch/arm/dts/sama5d2.dtsi
+++ b/arch/arm/dts/sama5d2.dtsi
@@ -778,6 +778,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xf8048030 0x10>;
clocks = <&h32ck>;
+ bootph-all;
};
watchdog: watchdog@f8048040 {
diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
index 8d6503d..874e71b 100644
--- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
@@ -208,7 +208,8 @@
intel,offset-settings =
/* DMIUSMCTCR */
<0x00000300 0x00000001 0x00000003>,
- <0x00000300 0x00000003 0x00000003>;
+ <0x00000300 0x00000003 0x00000003>,
+ <0x00000308 0x00000004 0x0000001F>;
bootph-all;
};
@@ -218,7 +219,8 @@
intel,offset-settings =
/* DMIUSMCTCR */
<0x00000300 0x00000001 0x00000003>,
- <0x00000300 0x00000003 0x00000003>;
+ <0x00000300 0x00000003 0x00000003>,
+ <0x00000308 0x00000004 0x0000001F>;
bootph-all;
};
};
@@ -673,6 +675,17 @@
bootph-all;
};
+&gpio1 {
+ /* Configure GPIO 1 pin 3 as output pin with value 0 during GPIO probe */
+ portb: gpio-controller@0{
+ sdio_sel {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+ };
+};
+
&i2c0 {
reset-names = "i2c";
};
diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
index d7ab582..8d7dc09 100644
--- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
@@ -25,34 +25,44 @@
/*
* Both Memory base address and size default info is retrieved from HW setting.
* Reconfiguration / Overwrite these info can be done with examples below.
- */
- /*
+ *
+ * When LPDDR ECC is enabled, the last 1/8 of the memory region must
+ * be reserved for the Inline ECC buffer.
+ *
* Example for memory size with 2GB:
* memory {
* reg = <0x0 0x80000000 0x0 0x80000000>;
* };
- */
- /*
+ *
* Example for memory size with 8GB:
* memory {
* reg = <0x0 0x80000000 0x0 0x80000000>,
* <0x8 0x80000000 0x1 0x80000000>;
* };
- */
- /*
+ *
* Example for memory size with 32GB:
* memory {
* reg = <0x0 0x80000000 0x0 0x80000000>,
* <0x8 0x80000000 0x7 0x80000000>;
* };
- */
- /*
+ *
* Example for memory size with 512GB:
* memory {
* reg = <0x0 0x80000000 0x0 0x80000000>,
* <0x8 0x80000000 0x7 0x80000000>,
* <0x88 0x00000000 0x78 0x00000000>;
* };
+ *
+ * Example for memory size with 2GB with LPDDR Inline ECC ON:
+ * memory {
+ * reg = <0x0 0x80000000 0x0 0x70000000>;
+ * };
+ *
+ * Example for memory size with 8GB with LPDDR Inline ECC ON:
+ * memory {
+ * reg = <0x0 0x80000000 0x0 0x80000000>,
+ * <0x8 0x80000000 0x1 0x40000000>;
+ * };
*/
chosen {
diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
index 15306db..93a8e06 100644
--- a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
@@ -106,8 +106,13 @@
arch = "arm64";
os = "linux";
compression = "none";
+ #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+ load = <0x86000000>;
+ entry = <0x86000000>;
+ #else
load = <0x6000000>;
entry = <0x6000000>;
+ #endif
kernel_blob: blob-ext {
filename = "Image";
};
diff --git a/arch/arm/dts/st-pincfg.h b/arch/arm/dts/st-pincfg.h
deleted file mode 100644
index d805512..0000000
--- a/arch/arm/dts/st-pincfg.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ST_PINCFG_H_
-#define _ST_PINCFG_H_
-
-/* Alternate functions */
-#define ALT1 1
-#define ALT2 2
-#define ALT3 3
-#define ALT4 4
-#define ALT5 5
-#define ALT6 6
-#define ALT7 7
-
-/* Output enable */
-#define OE (1 << 27)
-/* Pull Up */
-#define PU (1 << 26)
-/* Open Drain */
-#define OD (1 << 25)
-#define RT (1 << 23)
-#define INVERTCLK (1 << 22)
-#define CLKNOTDATA (1 << 21)
-#define DOUBLE_EDGE (1 << 20)
-#define CLK_A (0 << 18)
-#define CLK_B (1 << 18)
-#define CLK_C (2 << 18)
-#define CLK_D (3 << 18)
-
-/* User-frendly defines for Pin Direction */
- /* oe = 0, pu = 0, od = 0 */
-#define IN (0)
- /* oe = 0, pu = 1, od = 0 */
-#define IN_PU (PU)
- /* oe = 1, pu = 0, od = 0 */
-#define OUT (OE)
- /* oe = 1, pu = 0, od = 1 */
-#define BIDIR (OE | OD)
- /* oe = 1, pu = 1, od = 1 */
-#define BIDIR_PU (OE | PU | OD)
-
-/* RETIME_TYPE */
-/*
- * B Mode
- * Bypass retime with optional delay parameter
- */
-#define BYPASS (0)
-/*
- * R0, R1, R0D, R1D modes
- * single-edge data non inverted clock, retime data with clk
- */
-#define SE_NICLK_IO (RT)
-/*
- * RIV0, RIV1, RIV0D, RIV1D modes
- * single-edge data inverted clock, retime data with clk
- */
-#define SE_ICLK_IO (RT | INVERTCLK)
-/*
- * R0E, R1E, R0ED, R1ED modes
- * double-edge data, retime data with clk
- */
-#define DE_IO (RT | DOUBLE_EDGE)
-/*
- * CIV0, CIV1 modes with inverted clock
- * Retiming the clk pins will park clock & reduce the noise within the core.
- */
-#define ICLK (RT | CLKNOTDATA | INVERTCLK)
-/*
- * CLK0, CLK1 modes with non-inverted clock
- * Retiming the clk pins will park clock & reduce the noise within the core.
- */
-#define NICLK (RT | CLKNOTDATA)
-#endif /* _ST_PINCFG_H_ */
diff --git a/arch/arm/dts/stih407-clock.dtsi b/arch/arm/dts/stih407-clock.dtsi
deleted file mode 100644
index 1ab40db..0000000
--- a/arch/arm/dts/stih407-clock.dtsi
+++ /dev/null
@@ -1,323 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2014 STMicroelectronics R&D Limited
- */
-#include <dt-bindings/clock/stih407-clks.h>
-/ {
- /*
- * Fixed 30MHz oscillator inputs to SoC
- */
- clk_sysin: clk-sysin {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <30000000>;
- };
-
- clk_tmdsout_hdmi: clk-tmdsout-hdmi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- /*
- * A9 PLL.
- */
- clockgen-a9@92b0000 {
- compatible = "st,clkgen-c32";
- reg = <0x92b0000 0xffff>;
-
- clockgen_a9_pll: clockgen-a9-pll {
- #clock-cells = <1>;
- compatible = "st,stih407-clkgen-plla9";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clockgen-a9-pll-odf";
- };
- };
-
- /*
- * ARM CPU related clocks.
- */
- clk_m_a9: clk-m-a9@92b0000 {
- #clock-cells = <0>;
- compatible = "st,stih407-clkgen-a9-mux";
- reg = <0x92b0000 0x10000>;
-
- clocks = <&clockgen_a9_pll 0>,
- <&clockgen_a9_pll 0>,
- <&clk_s_c0_flexgen 13>,
- <&clk_m_a9_ext2f_div2>;
-
-
- /*
- * ARM Peripheral clock for timers
- */
- arm_periph_clk: clk-m-a9-periphs {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
-
- clocks = <&clk_m_a9>;
- clock-div = <2>;
- clock-mult = <1>;
- };
- };
-
- clockgen-a@90ff000 {
- compatible = "st,clkgen-c32";
- reg = <0x90ff000 0x1000>;
-
- clk_s_a0_pll: clk-s-a0-pll {
- #clock-cells = <1>;
- compatible = "st,clkgen-pll0";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-a0-pll-ofd-0";
- clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
- };
-
- clk_s_a0_flexgen: clk-s-a0-flexgen {
- compatible = "st,flexgen";
-
- #clock-cells = <1>;
-
- clocks = <&clk_s_a0_pll 0>,
- <&clk_sysin>;
-
- clock-output-names = "clk-ic-lmi0";
- clock-critical = <CLK_IC_LMI0>;
- };
- };
-
- clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
- #clock-cells = <1>;
- compatible = "st,quadfs-pll";
- reg = <0x9103000 0x1000>;
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-fs0-ch0",
- "clk-s-c0-fs0-ch1",
- "clk-s-c0-fs0-ch2",
- "clk-s-c0-fs0-ch3";
- clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
- };
-
- clk_s_c0: clockgen-c@9103000 {
- compatible = "st,clkgen-c32";
- reg = <0x9103000 0x1000>;
-
- clk_s_c0_pll0: clk-s-c0-pll0 {
- #clock-cells = <1>;
- compatible = "st,clkgen-pll0";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-pll0-odf-0";
- clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
- };
-
- clk_s_c0_pll1: clk-s-c0-pll1 {
- #clock-cells = <1>;
- compatible = "st,clkgen-pll1";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-pll1-odf-0";
- };
-
- clk_s_c0_flexgen: clk-s-c0-flexgen {
- #clock-cells = <1>;
- compatible = "st,flexgen";
-
- clocks = <&clk_s_c0_pll0 0>,
- <&clk_s_c0_pll1 0>,
- <&clk_s_c0_quadfs 0>,
- <&clk_s_c0_quadfs 1>,
- <&clk_s_c0_quadfs 2>,
- <&clk_s_c0_quadfs 3>,
- <&clk_sysin>;
-
- clock-output-names = "clk-icn-gpu",
- "clk-fdma",
- "clk-nand",
- "clk-hva",
- "clk-proc-stfe",
- "clk-proc-tp",
- "clk-rx-icn-dmu",
- "clk-rx-icn-hva",
- "clk-icn-cpu",
- "clk-tx-icn-dmu",
- "clk-mmc-0",
- "clk-mmc-1",
- "clk-jpegdec",
- "clk-ext2fa9",
- "clk-ic-bdisp-0",
- "clk-ic-bdisp-1",
- "clk-pp-dmu",
- "clk-vid-dmu",
- "clk-dss-lpc",
- "clk-st231-aud-0",
- "clk-st231-gp-1",
- "clk-st231-dmu",
- "clk-icn-lmi",
- "clk-tx-icn-disp-1",
- "clk-icn-sbc",
- "clk-stfe-frc2",
- "clk-eth-phy",
- "clk-eth-ref-phyclk",
- "clk-flash-promip",
- "clk-main-disp",
- "clk-aux-disp",
- "clk-compo-dvp";
- clock-critical = <CLK_PROC_STFE>,
- <CLK_ICN_CPU>,
- <CLK_TX_ICN_DMU>,
- <CLK_EXT2F_A9>,
- <CLK_ICN_LMI>,
- <CLK_ICN_SBC>;
-
- /*
- * ARM Peripheral clock for timers
- */
- clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
-
- clocks = <&clk_s_c0_flexgen 13>;
-
- clock-output-names = "clk-m-a9-ext2f-div2";
-
- clock-div = <2>;
- clock-mult = <1>;
- };
- };
- };
-
- clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
- #clock-cells = <1>;
- compatible = "st,quadfs";
- reg = <0x9104000 0x1000>;
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d0-fs0-ch0",
- "clk-s-d0-fs0-ch1",
- "clk-s-d0-fs0-ch2",
- "clk-s-d0-fs0-ch3";
- };
-
- clockgen-d0@9104000 {
- compatible = "st,clkgen-c32";
- reg = <0x9104000 0x1000>;
-
- clk_s_d0_flexgen: clk-s-d0-flexgen {
- #clock-cells = <1>;
- compatible = "st,flexgen-audio", "st,flexgen";
-
- clocks = <&clk_s_d0_quadfs 0>,
- <&clk_s_d0_quadfs 1>,
- <&clk_s_d0_quadfs 2>,
- <&clk_s_d0_quadfs 3>,
- <&clk_sysin>;
-
- clock-output-names = "clk-pcm-0",
- "clk-pcm-1",
- "clk-pcm-2",
- "clk-spdiff";
- };
- };
-
- clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
- #clock-cells = <1>;
- compatible = "st,quadfs";
- reg = <0x9106000 0x1000>;
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d2-fs0-ch0",
- "clk-s-d2-fs0-ch1",
- "clk-s-d2-fs0-ch2",
- "clk-s-d2-fs0-ch3";
- };
-
- clockgen-d2@9106000 {
- compatible = "st,clkgen-c32";
- reg = <0x9106000 0x1000>;
-
- clk_s_d2_flexgen: clk-s-d2-flexgen {
- #clock-cells = <1>;
- compatible = "st,flexgen-video", "st,flexgen";
-
- clocks = <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 1>,
- <&clk_s_d2_quadfs 2>,
- <&clk_s_d2_quadfs 3>,
- <&clk_sysin>,
- <&clk_sysin>,
- <&clk_tmdsout_hdmi>;
-
- clock-output-names = "clk-pix-main-disp",
- "clk-pix-pip",
- "clk-pix-gdp1",
- "clk-pix-gdp2",
- "clk-pix-gdp3",
- "clk-pix-gdp4",
- "clk-pix-aux-disp",
- "clk-denc",
- "clk-pix-hddac",
- "clk-hddac",
- "clk-sddac",
- "clk-pix-dvo",
- "clk-dvo",
- "clk-pix-hdmi",
- "clk-tmds-hdmi",
- "clk-ref-hdmiphy";
- };
- };
-
- clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
- #clock-cells = <1>;
- compatible = "st,quadfs";
- reg = <0x9107000 0x1000>;
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d3-fs0-ch0",
- "clk-s-d3-fs0-ch1",
- "clk-s-d3-fs0-ch2",
- "clk-s-d3-fs0-ch3";
- };
-
- clockgen-d3@9107000 {
- compatible = "st,clkgen-c32";
- reg = <0x9107000 0x1000>;
-
- clk_s_d3_flexgen: clk-s-d3-flexgen {
- #clock-cells = <1>;
- compatible = "st,flexgen";
-
- clocks = <&clk_s_d3_quadfs 0>,
- <&clk_s_d3_quadfs 1>,
- <&clk_s_d3_quadfs 2>,
- <&clk_s_d3_quadfs 3>,
- <&clk_sysin>;
-
- clock-output-names = "clk-stfe-frc1",
- "clk-tsout-0",
- "clk-tsout-1",
- "clk-mchi",
- "clk-vsens-compo",
- "clk-frc1-remote",
- "clk-lpc-0",
- "clk-lpc-1";
- };
- };
- };
-};
diff --git a/arch/arm/dts/stih407-family.dtsi b/arch/arm/dts/stih407-family.dtsi
deleted file mode 100644
index 7c36c37..0000000
--- a/arch/arm/dts/stih407-family.dtsi
+++ /dev/null
@@ -1,1000 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2014 STMicroelectronics Limited.
- * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
- */
-#include "stih407-pinctrl.dtsi"
-#include <dt-bindings/mfd/st-lpc.h>
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/reset/stih407-resets.h>
-#include <dt-bindings/interrupt-controller/irq-st.h>
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- gp0_reserved: rproc@45000000 {
- compatible = "shared-dma-pool";
- reg = <0x45000000 0x00400000>;
- no-map;
- };
-
- delta_reserved: rproc@44000000 {
- compatible = "shared-dma-pool";
- reg = <0x44000000 0x01000000>;
- no-map;
- };
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0>;
-
- /* u-boot puts hpen in SBC dmem at 0xa4 offset */
- cpu-release-addr = <0x94100A4>;
-
- /* kHz uV */
- operating-points = <1500000 0
- 1200000 0
- 800000 0
- 500000 0>;
-
- clocks = <&clk_m_a9>;
- clock-names = "cpu";
- clock-latency = <100000>;
- cpu0-supply = <&pwm_regulator>;
- st,syscfg = <&syscfg_core 0x8e0>;
- };
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <1>;
-
- /* u-boot puts hpen in SBC dmem at 0xa4 offset */
- cpu-release-addr = <0x94100A4>;
-
- /* kHz uV */
- operating-points = <1500000 0
- 1200000 0
- 800000 0
- 500000 0>;
- };
- };
-
- intc: interrupt-controller@8761000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x08761000 0x1000>, <0x08760100 0x100>;
- };
-
- scu@8760000 {
- compatible = "arm,cortex-a9-scu";
- reg = <0x08760000 0x1000>;
- };
-
- timer@8760200 {
- interrupt-parent = <&intc>;
- compatible = "arm,cortex-a9-global-timer";
- reg = <0x08760200 0x100>;
- interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&arm_periph_clk>;
- };
-
- l2: cache-controller@8762000 {
- compatible = "arm,pl310-cache";
- reg = <0x08762000 0x1000>;
- arm,data-latency = <3 3 3>;
- arm,tag-latency = <2 2 2>;
- cache-unified;
- cache-level = <2>;
- };
-
- arm-pmu {
- interrupt-parent = <&intc>;
- compatible = "arm,cortex-a9-pmu";
- interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- pwm_regulator: pwm-regulator {
- compatible = "pwm-regulator";
- pwms = <&pwm1 3 8448>;
- regulator-name = "CPU_1V0_AVS";
- regulator-min-microvolt = <784000>;
- regulator-max-microvolt = <1299000>;
- regulator-always-on;
- max-duty-cycle = <255>;
- status = "okay";
- };
-
- soc {
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&intc>;
- ranges;
- compatible = "simple-bus";
-
- restart: restart-controller@0 {
- compatible = "st,stih407-restart";
- reg = <0 0>;
- st,syscfg = <&syscfg_sbc_reg>;
- status = "okay";
- };
-
- powerdown: powerdown-controller@0 {
- compatible = "st,stih407-powerdown";
- reg = <0 0>;
- #reset-cells = <1>;
- };
-
- softreset: softreset-controller@0 {
- compatible = "st,stih407-softreset";
- reg = <0 0>;
- #reset-cells = <1>;
- };
-
- picophyreset: picophyreset-controller@0 {
- compatible = "st,stih407-picophyreset";
- reg = <0 0>;
- #reset-cells = <1>;
- };
-
- syscfg_sbc: sbc-syscfg@9620000 {
- compatible = "st,stih407-sbc-syscfg", "syscon";
- reg = <0x9620000 0x1000>;
- };
-
- syscfg_front: front-syscfg@9280000 {
- compatible = "st,stih407-front-syscfg", "syscon";
- reg = <0x9280000 0x1000>;
- };
-
- syscfg_rear: rear-syscfg@9290000 {
- compatible = "st,stih407-rear-syscfg", "syscon";
- reg = <0x9290000 0x1000>;
- };
-
- syscfg_flash: flash-syscfg@92a0000 {
- compatible = "st,stih407-flash-syscfg", "syscon";
- reg = <0x92a0000 0x1000>;
- };
-
- syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
- compatible = "st,stih407-sbc-reg-syscfg", "syscon";
- reg = <0x9600000 0x1000>;
- };
-
- syscfg_core: core-syscfg@92b0000 {
- compatible = "st,stih407-core-syscfg", "syscon";
- reg = <0x92b0000 0x1000>;
-
- sti_sasg_codec: sti-sasg-codec {
- compatible = "st,stih407-sas-codec";
- #sound-dai-cells = <1>;
- status = "disabled";
- st,syscfg = <&syscfg_core>;
- };
- };
-
- syscfg_lpm: lpm-syscfg@94b5100 {
- compatible = "st,stih407-lpm-syscfg", "syscon";
- reg = <0x94b5100 0x1000>;
- };
-
- irq-syscfg@0 {
- compatible = "st,stih407-irq-syscfg";
- reg = <0 0>;
- st,syscfg = <&syscfg_core>;
- st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
- <ST_IRQ_SYSCFG_PMU_1>;
- st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
- <ST_IRQ_SYSCFG_DISABLED>;
- };
-
- /* Display */
- vtg_main: sti-vtg-main@8d02800 {
- compatible = "st,vtg";
- reg = <0x8d02800 0x200>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- vtg_aux: sti-vtg-aux@8d00200 {
- compatible = "st,vtg";
- reg = <0x8d00200 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- serial@9830000 {
- compatible = "st,asc";
- reg = <0x9830000 0x2c>;
- interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- /* Pinctrl moved out to a per-board configuration */
-
- status = "disabled";
- };
-
- serial@9831000 {
- compatible = "st,asc";
- reg = <0x9831000 0x2c>;
- interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_serial1>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
-
- status = "disabled";
- };
-
- serial@9832000 {
- compatible = "st,asc";
- reg = <0x9832000 0x2c>;
- interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_serial2>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
-
- status = "disabled";
- };
-
- /* SBC_ASC0 - UART10 */
- sbc_serial0: serial@9530000 {
- compatible = "st,asc";
- reg = <0x9530000 0x2c>;
- interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sbc_serial0>;
- clocks = <&clk_sysin>;
-
- status = "disabled";
- };
-
- serial@9531000 {
- compatible = "st,asc";
- reg = <0x9531000 0x2c>;
- interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sbc_serial1>;
- clocks = <&clk_sysin>;
-
- status = "disabled";
- };
-
- i2c@9840000 {
- compatible = "st,comms-ssc4-i2c";
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x9840000 0x110>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- i2c@9841000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0x9841000 0x110>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- i2c@9842000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0x9842000 0x110>;
- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- i2c@9843000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0x9843000 0x110>;
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- i2c@9844000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0x9844000 0x110>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c4_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- i2c@9845000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0x9845000 0x110>;
- interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c5_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
-
- /* SSCs on SBC */
- i2c@9540000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0x9540000 0x110>;
- interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_sysin>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c10_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- i2c@9541000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0x9541000 0x110>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_sysin>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c11_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- usb2_picophy0: phy1@0 {
- compatible = "st,stih407-usb2-phy";
- reg = <0 0>;
- #phy-cells = <0>;
- st,syscfg = <&syscfg_core 0x100 0xf4>;
- resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
- <&picophyreset STIH407_PICOPHY2_RESET>;
- reset-names = "global", "port";
- };
-
- miphy28lp_phy: miphy28lp@0 {
- compatible = "st,miphy28lp-phy";
- st,syscfg = <&syscfg_core>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- reg = <0 0>;
-
- phy_port0: port@9b22000 {
- reg = <0x9b22000 0xff>,
- <0x9b09000 0xff>,
- <0x9b04000 0xff>;
- reg-names = "sata-up",
- "pcie-up",
- "pipew";
-
- st,syscfg = <0x114 0x818 0xe0 0xec>;
- #phy-cells = <1>;
-
- reset-names = "miphy-sw-rst";
- resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
- };
-
- phy_port1: port@9b2a000 {
- reg = <0x9b2a000 0xff>,
- <0x9b19000 0xff>,
- <0x9b14000 0xff>;
- reg-names = "sata-up",
- "pcie-up",
- "pipew";
-
- st,syscfg = <0x118 0x81c 0xe4 0xf0>;
-
- #phy-cells = <1>;
-
- reset-names = "miphy-sw-rst";
- resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
- };
-
- phy_port2: port@8f95000 {
- reg = <0x8f95000 0xff>,
- <0x8f90000 0xff>;
- reg-names = "pipew",
- "usb3-up";
-
- st,syscfg = <0x11c 0x820>;
-
- #phy-cells = <1>;
-
- reset-names = "miphy-sw-rst";
- resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
- };
- };
-
- spi@9840000 {
- compatible = "st,comms-ssc4-spi";
- reg = <0x9840000 0x110>;
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- pinctrl-0 = <&pinctrl_spi0_default>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- spi@9841000 {
- compatible = "st,comms-ssc4-spi";
- reg = <0x9841000 0x110>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi1_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- spi@9842000 {
- compatible = "st,comms-ssc4-spi";
- reg = <0x9842000 0x110>;
- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi2_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- spi@9843000 {
- compatible = "st,comms-ssc4-spi";
- reg = <0x9843000 0x110>;
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi3_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- spi@9844000 {
- compatible = "st,comms-ssc4-spi";
- reg = <0x9844000 0x110>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi4_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- /* SBC SSC */
- spi@9540000 {
- compatible = "st,comms-ssc4-spi";
- reg = <0x9540000 0x110>;
- interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_sysin>;
- clock-names = "ssc";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi10_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- spi@9541000 {
- compatible = "st,comms-ssc4-spi";
- reg = <0x9541000 0x110>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_sysin>;
- clock-names = "ssc";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi11_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- spi@9542000 {
- compatible = "st,comms-ssc4-spi";
- reg = <0x9542000 0x110>;
- interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_sysin>;
- clock-names = "ssc";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi12_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- mmc0: sdhci@9060000 {
- compatible = "st,sdhci-stih407", "st,sdhci";
- status = "disabled";
- reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
- reg-names = "mmc", "top-mmc-delay";
- interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "mmcirq";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_mmc0>;
- clock-names = "mmc", "icn";
- clocks = <&clk_s_c0_flexgen CLK_MMC_0>,
- <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
- bus-width = <8>;
- };
-
- mmc1: sdhci@9080000 {
- compatible = "st,sdhci-stih407", "st,sdhci";
- status = "disabled";
- reg = <0x09080000 0x7ff>;
- reg-names = "mmc";
- interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "mmcirq";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sd1>;
- clock-names = "mmc", "icn";
- clocks = <&clk_s_c0_flexgen CLK_MMC_1>,
- <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
- resets = <&softreset STIH407_MMC1_SOFTRESET>;
- bus-width = <4>;
- };
-
- /* Watchdog and Real-Time Clock */
- lpc@8787000 {
- compatible = "st,stih407-lpc";
- reg = <0x8787000 0x1000>;
- interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
- timeout-sec = <120>;
- st,syscfg = <&syscfg_core>;
- st,lpc-mode = <ST_LPC_MODE_WDT>;
- };
-
- lpc@8788000 {
- compatible = "st,stih407-lpc";
- reg = <0x8788000 0x1000>;
- interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
- st,lpc-mode = <ST_LPC_MODE_CLKSRC>;
- };
-
- sata0: sata@9b20000 {
- compatible = "st,ahci";
- reg = <0x9b20000 0x1000>;
-
- interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hostc";
-
- phys = <&phy_port0 PHY_TYPE_SATA>;
- phy-names = "ahci_phy";
-
- resets = <&powerdown STIH407_SATA0_POWERDOWN>,
- <&softreset STIH407_SATA0_SOFTRESET>,
- <&softreset STIH407_SATA0_PWR_SOFTRESET>;
- reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
-
- clock-names = "ahci_clk";
- clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
-
- ports-implemented = <0x1>;
-
- status = "disabled";
- };
-
- sata1: sata@9b28000 {
- compatible = "st,ahci";
- reg = <0x9b28000 0x1000>;
-
- interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hostc";
-
- phys = <&phy_port1 PHY_TYPE_SATA>;
- phy-names = "ahci_phy";
-
- resets = <&powerdown STIH407_SATA1_POWERDOWN>,
- <&softreset STIH407_SATA1_SOFTRESET>,
- <&softreset STIH407_SATA1_PWR_SOFTRESET>;
- reset-names = "pwr-dwn",
- "sw-rst",
- "pwr-rst";
-
- clock-names = "ahci_clk";
- clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
-
- ports-implemented = <0x1>;
-
- status = "disabled";
- };
-
-
- st_dwc3: dwc3@8f94000 {
- compatible = "st,stih407-dwc3";
- reg = <0x08f94000 0x1000>, <0x110 0x4>;
- reg-names = "reg-glue", "syscfg-reg";
- st,syscfg = <&syscfg_core>;
- resets = <&powerdown STIH407_USB3_POWERDOWN>,
- <&softreset STIH407_MIPHY2_SOFTRESET>;
- reset-names = "powerdown", "softreset";
- #address-cells = <1>;
- #size-cells = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb3>;
- ranges;
-
- status = "disabled";
-
- dwc3: dwc3@9900000 {
- compatible = "snps,dwc3";
- reg = <0x09900000 0x100000>;
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- phy-names = "usb2-phy", "usb3-phy";
- phys = <&usb2_picophy0>,
- <&phy_port2 PHY_TYPE_USB3>;
- snps,dis_u3_susphy_quirk;
- };
- };
-
- /* COMMS PWM Module */
- pwm0: pwm@9810000 {
- compatible = "st,sti-pwm";
- #pwm-cells = <2>;
- reg = <0x9810000 0x68>;
- interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm0_chan0_default>;
- clock-names = "pwm";
- clocks = <&clk_sysin>;
- st,pwm-num-chan = <1>;
-
- status = "disabled";
- };
-
- /* SBC PWM Module */
- pwm1: pwm@9510000 {
- compatible = "st,sti-pwm";
- #pwm-cells = <2>;
- reg = <0x9510000 0x68>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm1_chan0_default
- &pinctrl_pwm1_chan1_default
- &pinctrl_pwm1_chan2_default
- &pinctrl_pwm1_chan3_default>;
- clock-names = "pwm";
- clocks = <&clk_sysin>;
- st,pwm-num-chan = <4>;
-
- status = "disabled";
- };
-
- rng10: rng@8a89000 {
- compatible = "st,rng";
- reg = <0x08a89000 0x1000>;
- clocks = <&clk_sysin>;
- status = "okay";
- };
-
- rng11: rng@8a8a000 {
- compatible = "st,rng";
- reg = <0x08a8a000 0x1000>;
- clocks = <&clk_sysin>;
- status = "okay";
- };
-
- ethernet0: dwmac@9630000 {
- device_type = "network";
- status = "disabled";
- compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
- reg = <0x9630000 0x8000>, <0x80 0x4>;
- reg-names = "stmmaceth", "sti-ethconf";
-
- st,syscon = <&syscfg_sbc_reg 0x80>;
- st,gmac_en;
- resets = <&softreset STIH407_ETH1_SOFTRESET>;
- reset-names = "stmmaceth";
-
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq", "eth_wake_irq";
-
- /* DMA Bus Mode */
- snps,pbl = <8>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_rgmii1>;
-
- clock-names = "stmmaceth", "sti-ethclk";
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>,
- <&clk_s_c0_flexgen CLK_ETH_PHY>;
- };
-
- rng10: rng@8a89000 {
- compatible = "st,rng";
- reg = <0x08a89000 0x1000>;
- clocks = <&clk_sysin>;
- status = "okay";
- };
-
- rng11: rng@8a8a000 {
- compatible = "st,rng";
- reg = <0x08a8a000 0x1000>;
- clocks = <&clk_sysin>;
- status = "okay";
- };
-
- mailbox0: mailbox@8f00000 {
- compatible = "st,stih407-mailbox";
- reg = <0x8f00000 0x1000>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <2>;
- mbox-name = "a9";
- status = "okay";
- };
-
- mailbox1: mailbox@8f01000 {
- compatible = "st,stih407-mailbox";
- reg = <0x8f01000 0x1000>;
- #mbox-cells = <2>;
- mbox-name = "st231_gp_1";
- status = "okay";
- };
-
- mailbox2: mailbox@8f02000 {
- compatible = "st,stih407-mailbox";
- reg = <0x8f02000 0x1000>;
- #mbox-cells = <2>;
- mbox-name = "st231_gp_0";
- status = "okay";
- };
-
- mailbox3: mailbox@8f03000 {
- compatible = "st,stih407-mailbox";
- reg = <0x8f03000 0x1000>;
- #mbox-cells = <2>;
- mbox-name = "st231_audio_video";
- status = "okay";
- };
-
- st231_gp0: st231-gp0@0 {
- compatible = "st,st231-rproc";
- reg = <0 0>;
- memory-region = <&gp0_reserved>;
- resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
- reset-names = "sw_reset";
- clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>;
- clock-frequency = <600000000>;
- st,syscfg = <&syscfg_core 0x22c>;
- #mbox-cells = <1>;
- mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
- mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>;
- };
-
- st231_delta: st231-delta@0 {
- compatible = "st,st231-rproc";
- reg = <0 0>;
- memory-region = <&delta_reserved>;
- resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
- reset-names = "sw_reset";
- clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>;
- clock-frequency = <600000000>;
- st,syscfg = <&syscfg_core 0x224>;
- #mbox-cells = <1>;
- mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
- mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>;
- };
-
- /* fdma audio */
- fdma0: dma-controller@8e20000 {
- compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc";
- reg = <0x8e20000 0x8000>,
- <0x8e30000 0x3000>,
- <0x8e37000 0x1000>,
- <0x8e38000 0x8000>;
- reg-names = "slimcore", "dmem", "peripherals", "imem";
- clocks = <&clk_s_c0_flexgen CLK_FDMA>,
- <&clk_s_c0_flexgen CLK_EXT2F_A9>,
- <&clk_s_c0_flexgen CLK_EXT2F_A9>,
- <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- dma-channels = <16>;
- #dma-cells = <3>;
- };
-
- /* fdma app */
- fdma1: dma-controller@8e40000 {
- compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc";
- reg = <0x8e40000 0x8000>,
- <0x8e50000 0x3000>,
- <0x8e57000 0x1000>,
- <0x8e58000 0x8000>;
- reg-names = "slimcore", "dmem", "peripherals", "imem";
- clocks = <&clk_s_c0_flexgen CLK_FDMA>,
- <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
- <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
- <&clk_s_c0_flexgen CLK_EXT2F_A9>;
-
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- dma-channels = <16>;
- #dma-cells = <3>;
-
- status = "disabled";
- };
-
- /* fdma free running */
- fdma2: dma-controller@8e60000 {
- compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc";
- reg = <0x8e60000 0x8000>,
- <0x8e70000 0x3000>,
- <0x8e77000 0x1000>,
- <0x8e78000 0x8000>;
- reg-names = "slimcore", "dmem", "peripherals", "imem";
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- dma-channels = <16>;
- #dma-cells = <3>;
- clocks = <&clk_s_c0_flexgen CLK_FDMA>,
- <&clk_s_c0_flexgen CLK_EXT2F_A9>,
- <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
- <&clk_s_c0_flexgen CLK_EXT2F_A9>;
-
- status = "disabled";
- };
-
- sti_uni_player0: sti-uni-player@8d80000 {
- compatible = "st,stih407-uni-player-hdmi";
- #sound-dai-cells = <0>;
- st,syscfg = <&syscfg_core>;
- clocks = <&clk_s_d0_flexgen CLK_PCM_0>;
- assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>;
- assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>;
- assigned-clock-rates = <50000000>;
- reg = <0x8d80000 0x158>;
- interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&fdma0 2 0 1>;
- dma-names = "tx";
-
- status = "disabled";
- };
-
- sti_uni_player1: sti-uni-player@8d81000 {
- compatible = "st,stih407-uni-player-pcm-out";
- #sound-dai-cells = <0>;
- st,syscfg = <&syscfg_core>;
- clocks = <&clk_s_d0_flexgen CLK_PCM_1>;
- assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>;
- assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>;
- assigned-clock-rates = <50000000>;
- reg = <0x8d81000 0x158>;
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&fdma0 3 0 1>;
- dma-names = "tx";
-
- status = "disabled";
- };
-
- sti_uni_player2: sti-uni-player@8d82000 {
- compatible = "st,stih407-uni-player-dac";
- #sound-dai-cells = <0>;
- st,syscfg = <&syscfg_core>;
- clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
- assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>;
- assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>;
- assigned-clock-rates = <50000000>;
- reg = <0x8d82000 0x158>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&fdma0 4 0 1>;
- dma-names = "tx";
-
- status = "disabled";
- };
-
- sti_uni_player3: sti-uni-player@8d85000 {
- compatible = "st,stih407-uni-player-spdif";
- #sound-dai-cells = <0>;
- st,syscfg = <&syscfg_core>;
- clocks = <&clk_s_d0_flexgen CLK_SPDIFF>;
- assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>;
- assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>;
- assigned-clock-rates = <50000000>;
- reg = <0x8d85000 0x158>;
- interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&fdma0 7 0 1>;
- dma-names = "tx";
-
- status = "disabled";
- };
-
- sti_uni_reader0: sti-uni-reader@8d83000 {
- compatible = "st,stih407-uni-reader-pcm_in";
- #sound-dai-cells = <0>;
- st,syscfg = <&syscfg_core>;
- reg = <0x8d83000 0x158>;
- interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&fdma0 5 0 1>;
- dma-names = "rx";
-
- status = "disabled";
- };
-
- sti_uni_reader1: sti-uni-reader@8d84000 {
- compatible = "st,stih407-uni-reader-hdmi";
- #sound-dai-cells = <0>;
- st,syscfg = <&syscfg_core>;
- reg = <0x8d84000 0x158>;
- interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&fdma0 6 0 1>;
- dma-names = "rx";
-
- status = "disabled";
- };
-
- delta0@0 {
- compatible = "st,st-delta";
- reg = <0 0>;
- clock-names = "delta",
- "delta-st231",
- "delta-flash-promip";
- clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
- <&clk_s_c0_flexgen CLK_ST231_DMU>,
- <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
- };
- };
-};
diff --git a/arch/arm/dts/stih407-pinctrl.dtsi b/arch/arm/dts/stih407-pinctrl.dtsi
deleted file mode 100644
index 2cf3357..0000000
--- a/arch/arm/dts/stih407-pinctrl.dtsi
+++ /dev/null
@@ -1,1262 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2014 STMicroelectronics Limited.
- * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
- */
-#include "st-pincfg.h"
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-/ {
-
- aliases {
- /* 0-5: PIO_SBC */
- gpio0 = &pio0;
- gpio1 = &pio1;
- gpio2 = &pio2;
- gpio3 = &pio3;
- gpio4 = &pio4;
- gpio5 = &pio5;
- /* 10-19: PIO_FRONT0 */
- gpio6 = &pio10;
- gpio7 = &pio11;
- gpio8 = &pio12;
- gpio9 = &pio13;
- gpio10 = &pio14;
- gpio11 = &pio15;
- gpio12 = &pio16;
- gpio13 = &pio17;
- gpio14 = &pio18;
- gpio15 = &pio19;
- /* 20: PIO_FRONT1 */
- gpio16 = &pio20;
- /* 30-35: PIO_REAR */
- gpio17 = &pio30;
- gpio18 = &pio31;
- gpio19 = &pio32;
- gpio20 = &pio33;
- gpio21 = &pio34;
- gpio22 = &pio35;
- /* 40-42: PIO_FLASH */
- gpio23 = &pio40;
- gpio24 = &pio41;
- gpio25 = &pio42;
- };
-
- soc {
- pin-controller-sbc@961f080 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stih407-sbc-pinctrl";
- st,syscfg = <&syscfg_sbc>;
- reg = <0x0961f080 0x4>;
- reg-names = "irqmux";
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irqmux";
- ranges = <0 0x09610000 0x6000>;
-
- pio0: gpio@9610000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x0 0x100>;
- st,bank-name = "PIO0";
- };
- pio1: gpio@9611000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x100>;
- st,bank-name = "PIO1";
- };
- pio2: gpio@9612000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x100>;
- st,bank-name = "PIO2";
- };
- pio3: gpio@9613000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x3000 0x100>;
- st,bank-name = "PIO3";
- };
- pio4: gpio@9614000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x4000 0x100>;
- st,bank-name = "PIO4";
- };
-
- pio5: gpio@9615000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x5000 0x100>;
- st,bank-name = "PIO5";
- st,retime-pin-mask = <0x3f>;
- };
-
- cec0 {
- pinctrl_cec0_default: cec0-default {
- st,pins {
- hdmi_cec = <&pio2 4 ALT1 BIDIR>;
- };
- };
- };
-
- rc {
- pinctrl_ir: ir0 {
- st,pins {
- ir = <&pio4 0 ALT2 IN>;
- };
- };
-
- pinctrl_uhf: uhf0 {
- st,pins {
- ir = <&pio4 1 ALT2 IN>;
- };
- };
-
- pinctrl_tx: tx0 {
- st,pins {
- tx = <&pio4 2 ALT2 OUT>;
- };
- };
-
- pinctrl_tx_od: tx_od0 {
- st,pins {
- tx_od = <&pio4 3 ALT2 OUT>;
- };
- };
- };
-
- /* SBC_ASC0 - UART10 */
- sbc_serial0 {
- pinctrl_sbc_serial0: sbc_serial0-0 {
- st,pins {
- tx = <&pio3 4 ALT1 OUT>;
- rx = <&pio3 5 ALT1 IN>;
- };
- };
- };
- /* SBC_ASC1 - UART11 */
- sbc_serial1 {
- pinctrl_sbc_serial1: sbc_serial1-0 {
- st,pins {
- tx = <&pio2 6 ALT3 OUT>;
- rx = <&pio2 7 ALT3 IN>;
- };
- };
- };
-
- i2c10 {
- pinctrl_i2c10_default: i2c10-default {
- st,pins {
- sda = <&pio4 6 ALT1 BIDIR>;
- scl = <&pio4 5 ALT1 BIDIR>;
- };
- };
- };
-
- i2c11 {
- pinctrl_i2c11_default: i2c11-default {
- st,pins {
- sda = <&pio5 1 ALT1 BIDIR>;
- scl = <&pio5 0 ALT1 BIDIR>;
- };
- };
- };
-
- keyscan {
- pinctrl_keyscan: keyscan {
- st,pins {
- keyin0 = <&pio4 0 ALT6 IN>;
- keyin1 = <&pio4 5 ALT4 IN>;
- keyin2 = <&pio0 4 ALT2 IN>;
- keyin3 = <&pio2 6 ALT2 IN>;
-
- keyout0 = <&pio4 6 ALT4 OUT>;
- keyout1 = <&pio1 7 ALT2 OUT>;
- keyout2 = <&pio0 6 ALT2 OUT>;
- keyout3 = <&pio2 7 ALT2 OUT>;
- };
- };
- };
-
- gmac1 {
- /*
- * Almost all the boards based on STiH407 SoC have an embedded
- * switch where the mdio/mdc have been used for managing the SMI
- * iface via I2C. For this reason these lines can be allocated
- * by using dedicated configuration (in case of there will be a
- * standard PHY transceiver on-board).
- */
- pinctrl_rgmii1: rgmii1-0 {
- st,pins {
-
- txd0 = <&pio0 0 ALT1 OUT DE_IO 0 CLK_A>;
- txd1 = <&pio0 1 ALT1 OUT DE_IO 0 CLK_A>;
- txd2 = <&pio0 2 ALT1 OUT DE_IO 0 CLK_A>;
- txd3 = <&pio0 3 ALT1 OUT DE_IO 0 CLK_A>;
- txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>;
- txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
- rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>;
- rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>;
- rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>;
- rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>;
- rxdv = <&pio2 0 ALT1 IN DE_IO 0 CLK_A>;
- rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
- clk125 = <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
- phyclk = <&pio2 3 ALT4 OUT NICLK 1250 CLK_B>;
- };
- };
-
- pinctrl_rgmii1_mdio: rgmii1-mdio {
- st,pins {
- mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
- mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
- mdint = <&pio1 3 ALT1 IN BYPASS 0>;
- };
- };
-
- pinctrl_rgmii1_mdio_1: rgmii1-mdio-1 {
- st,pins {
- mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
- mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
- };
- };
-
- pinctrl_mii1: mii1 {
- st,pins {
- txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
- col = <&pio0 7 ALT1 IN BYPASS 1000>;
-
- mdio = <&pio1 0 ALT1 OUT BYPASS 1500>;
- mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
- crs = <&pio1 2 ALT1 IN BYPASS 1000>;
- mdint = <&pio1 3 ALT1 IN BYPASS 0>;
- rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
-
- rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
- phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
- };
- };
-
- pinctrl_rmii1: rmii1-0 {
- st,pins {
- txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
- mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
- mdint = <&pio1 3 ALT1 IN BYPASS 0>;
- rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_B>;
- rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_B>;
- rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_B>;
- rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- };
- };
-
- pinctrl_rmii1_phyclk: rmii1_phyclk {
- st,pins {
- phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
- };
- };
-
- pinctrl_rmii1_phyclk_ext: rmii1_phyclk_ext {
- st,pins {
- phyclk = <&pio2 3 ALT2 IN NICLK 0 CLK_A>;
- };
- };
- };
-
- pwm1 {
- pinctrl_pwm1_chan0_default: pwm1-0-default {
- st,pins {
- pwm-out = <&pio3 0 ALT1 OUT>;
- pwm-capturein = <&pio3 2 ALT1 IN>;
- };
- };
- pinctrl_pwm1_chan1_default: pwm1-1-default {
- st,pins {
- pwm-capturein = <&pio4 3 ALT1 IN>;
- pwm-out = <&pio4 4 ALT1 OUT>;
- };
- };
- pinctrl_pwm1_chan2_default: pwm1-2-default {
- st,pins {
- pwm-out = <&pio4 6 ALT3 OUT>;
- };
- };
- pinctrl_pwm1_chan3_default: pwm1-3-default {
- st,pins {
- pwm-out = <&pio4 7 ALT3 OUT>;
- };
- };
- };
-
- spi10 {
- pinctrl_spi10_default: spi10-4w-alt1-0 {
- st,pins {
- mtsr = <&pio4 6 ALT1 OUT>;
- mrst = <&pio4 7 ALT1 IN>;
- scl = <&pio4 5 ALT1 OUT>;
- };
- };
-
- pinctrl_spi10_3w_alt1_0: spi10-3w-alt1-0 {
- st,pins {
- mtsr = <&pio4 6 ALT1 BIDIR_PU>;
- scl = <&pio4 5 ALT1 OUT>;
- };
- };
- };
-
- spi11 {
- pinctrl_spi11_default: spi11-4w-alt2-0 {
- st,pins {
- mtsr = <&pio3 1 ALT2 OUT>;
- mrst = <&pio3 0 ALT2 IN>;
- scl = <&pio3 2 ALT2 OUT>;
- };
- };
-
- pinctrl_spi11_3w_alt2_0: spi11-3w-alt2-0 {
- st,pins {
- mtsr = <&pio3 1 ALT2 BIDIR_PU>;
- scl = <&pio3 2 ALT2 OUT>;
- };
- };
- };
-
- spi12 {
- pinctrl_spi12_default: spi12-4w-alt2-0 {
- st,pins {
- mtsr = <&pio3 6 ALT2 OUT>;
- mrst = <&pio3 4 ALT2 IN>;
- scl = <&pio3 7 ALT2 OUT>;
- };
- };
-
- pinctrl_spi12_3w_alt2_0: spi12-3w-alt2-0 {
- st,pins {
- mtsr = <&pio3 6 ALT2 BIDIR_PU>;
- scl = <&pio3 7 ALT2 OUT>;
- };
- };
- };
- };
-
- pin-controller-front0@920f080 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stih407-front-pinctrl";
- st,syscfg = <&syscfg_front>;
- reg = <0x0920f080 0x4>;
- reg-names = "irqmux";
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irqmux";
- ranges = <0 0x09200000 0x10000>;
-
- pio10: pio@9200000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x0 0x100>;
- st,bank-name = "PIO10";
- };
- pio11: pio@9201000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x100>;
- st,bank-name = "PIO11";
- };
- pio12: pio@9202000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x100>;
- st,bank-name = "PIO12";
- };
- pio13: pio@9203000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x3000 0x100>;
- st,bank-name = "PIO13";
- };
- pio14: pio@9204000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x4000 0x100>;
- st,bank-name = "PIO14";
- };
- pio15: pio@9205000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x5000 0x100>;
- st,bank-name = "PIO15";
- };
- pio16: pio@9206000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x6000 0x100>;
- st,bank-name = "PIO16";
- };
- pio17: pio@9207000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x7000 0x100>;
- st,bank-name = "PIO17";
- };
- pio18: pio@9208000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x8000 0x100>;
- st,bank-name = "PIO18";
- };
- pio19: pio@9209000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x9000 0x100>;
- st,bank-name = "PIO19";
- };
-
- /* Comms */
- serial0 {
- pinctrl_serial0: serial0-0 {
- st,pins {
- tx = <&pio17 0 ALT1 OUT>;
- rx = <&pio17 1 ALT1 IN>;
- };
- };
- pinctrl_serial0_hw_flowctrl: serial0-0_hw_flowctrl {
- st,pins {
- tx = <&pio17 0 ALT1 OUT>;
- rx = <&pio17 1 ALT1 IN>;
- cts = <&pio17 2 ALT1 IN>;
- rts = <&pio17 3 ALT1 OUT>;
- };
- };
- };
-
- serial1 {
- pinctrl_serial1: serial1-0 {
- st,pins {
- tx = <&pio16 0 ALT1 OUT>;
- rx = <&pio16 1 ALT1 IN>;
- };
- };
- };
-
- serial2 {
- pinctrl_serial2: serial2-0 {
- st,pins {
- tx = <&pio15 0 ALT1 OUT>;
- rx = <&pio15 1 ALT1 IN>;
- };
- };
- };
-
- mmc1 {
- pinctrl_sd1: sd1-0 {
- st,pins {
- sd_clk = <&pio19 3 ALT5 BIDIR NICLK 0 CLK_B>;
- sd_cmd = <&pio19 2 ALT5 BIDIR_PU BYPASS 0>;
- sd_dat0 = <&pio19 4 ALT5 BIDIR_PU BYPASS 0>;
- sd_dat1 = <&pio19 5 ALT5 BIDIR_PU BYPASS 0>;
- sd_dat2 = <&pio19 6 ALT5 BIDIR_PU BYPASS 0>;
- sd_dat3 = <&pio19 7 ALT5 BIDIR_PU BYPASS 0>;
- sd_led = <&pio16 6 ALT6 OUT>;
- sd_pwren = <&pio16 7 ALT6 OUT>;
- sd_cd = <&pio19 0 ALT6 IN>;
- sd_wp = <&pio19 1 ALT6 IN>;
- };
- };
- };
-
-
- i2c0 {
- pinctrl_i2c0_default: i2c0-default {
- st,pins {
- sda = <&pio10 6 ALT2 BIDIR>;
- scl = <&pio10 5 ALT2 BIDIR>;
- };
- };
- };
-
- i2c1 {
- pinctrl_i2c1_default: i2c1-default {
- st,pins {
- sda = <&pio11 1 ALT2 BIDIR>;
- scl = <&pio11 0 ALT2 BIDIR>;
- };
- };
- };
-
- i2c2 {
- pinctrl_i2c2_default: i2c2-default {
- st,pins {
- sda = <&pio15 6 ALT2 BIDIR>;
- scl = <&pio15 5 ALT2 BIDIR>;
- };
- };
-
- pinctrl_i2c2_alt2_1: i2c2-alt2-1 {
- st,pins {
- sda = <&pio12 6 ALT2 BIDIR>;
- scl = <&pio12 5 ALT2 BIDIR>;
- };
- };
- };
-
- i2c3 {
- pinctrl_i2c3_default: i2c3-alt1-0 {
- st,pins {
- sda = <&pio18 6 ALT1 BIDIR>;
- scl = <&pio18 5 ALT1 BIDIR>;
- };
- };
- pinctrl_i2c3_alt1_1: i2c3-alt1-1 {
- st,pins {
- sda = <&pio17 7 ALT1 BIDIR>;
- scl = <&pio17 6 ALT1 BIDIR>;
- };
- };
- pinctrl_i2c3_alt3_0: i2c3-alt3-0 {
- st,pins {
- sda = <&pio13 6 ALT3 BIDIR>;
- scl = <&pio13 5 ALT3 BIDIR>;
- };
- };
- };
-
- spi0 {
- pinctrl_spi0_default: spi0-4w-alt2-0 {
- st,pins {
- mtsr = <&pio10 6 ALT2 OUT>;
- mrst = <&pio10 7 ALT2 IN>;
- scl = <&pio10 5 ALT2 OUT>;
- };
- };
-
- pinctrl_spi0_3w_alt2_0: spi0-3w-alt2-0 {
- st,pins {
- mtsr = <&pio10 6 ALT2 BIDIR_PU>;
- scl = <&pio10 5 ALT2 OUT>;
- };
- };
-
- pinctrl_spi0_4w_alt1_0: spi0-4w-alt1-0 {
- st,pins {
- mtsr = <&pio19 7 ALT1 OUT>;
- mrst = <&pio19 5 ALT1 IN>;
- scl = <&pio19 6 ALT1 OUT>;
- };
- };
-
- pinctrl_spi0_3w_alt1_0: spi0-3w-alt1-0 {
- st,pins {
- mtsr = <&pio19 7 ALT1 BIDIR_PU>;
- scl = <&pio19 6 ALT1 OUT>;
- };
- };
- };
-
- spi1 {
- pinctrl_spi1_default: spi1-4w-alt2-0 {
- st,pins {
- mtsr = <&pio11 1 ALT2 OUT>;
- mrst = <&pio11 2 ALT2 IN>;
- scl = <&pio11 0 ALT2 OUT>;
- };
- };
-
- pinctrl_spi1_3w_alt2_0: spi1-3w-alt2-0 {
- st,pins {
- mtsr = <&pio11 1 ALT2 BIDIR_PU>;
- scl = <&pio11 0 ALT2 OUT>;
- };
- };
-
- pinctrl_spi1_4w_alt1_0: spi1-4w-alt1-0 {
- st,pins {
- mtsr = <&pio14 3 ALT1 OUT>;
- mrst = <&pio14 4 ALT1 IN>;
- scl = <&pio14 2 ALT1 OUT>;
- };
- };
-
- pinctrl_spi1_3w_alt1_0: spi1-3w-alt1-0 {
- st,pins {
- mtsr = <&pio14 3 ALT1 BIDIR_PU>;
- scl = <&pio14 2 ALT1 OUT>;
- };
- };
- };
-
- spi2 {
- pinctrl_spi2_default: spi2-4w-alt2-0 {
- st,pins {
- mtsr = <&pio12 6 ALT2 OUT>;
- mrst = <&pio12 7 ALT2 IN>;
- scl = <&pio12 5 ALT2 OUT>;
- };
- };
-
- pinctrl_spi2_3w_alt2_0: spi2-3w-alt2-0 {
- st,pins {
- mtsr = <&pio12 6 ALT2 BIDIR_PU>;
- scl = <&pio12 5 ALT2 OUT>;
- };
- };
-
- pinctrl_spi2_4w_alt1_0: spi2-4w-alt1-0 {
- st,pins {
- mtsr = <&pio14 6 ALT1 OUT>;
- mrst = <&pio14 7 ALT1 IN>;
- scl = <&pio14 5 ALT1 OUT>;
- };
- };
-
- pinctrl_spi2_3w_alt1_0: spi2-3w-alt1-0 {
- st,pins {
- mtsr = <&pio14 6 ALT1 BIDIR_PU>;
- scl = <&pio14 5 ALT1 OUT>;
- };
- };
-
- pinctrl_spi2_4w_alt2_1: spi2-4w-alt2-1 {
- st,pins {
- mtsr = <&pio15 6 ALT2 OUT>;
- mrst = <&pio15 7 ALT2 IN>;
- scl = <&pio15 5 ALT2 OUT>;
- };
- };
-
- pinctrl_spi2_3w_alt2_1: spi2-3w-alt2-1 {
- st,pins {
- mtsr = <&pio15 6 ALT2 BIDIR_PU>;
- scl = <&pio15 5 ALT2 OUT>;
- };
- };
- };
-
- spi3 {
- pinctrl_spi3_default: spi3-4w-alt3-0 {
- st,pins {
- mtsr = <&pio13 6 ALT3 OUT>;
- mrst = <&pio13 7 ALT3 IN>;
- scl = <&pio13 5 ALT3 OUT>;
- };
- };
-
- pinctrl_spi3_3w_alt3_0: spi3-3w-alt3-0 {
- st,pins {
- mtsr = <&pio13 6 ALT3 BIDIR_PU>;
- scl = <&pio13 5 ALT3 OUT>;
- };
- };
-
- pinctrl_spi3_4w_alt1_0: spi3-4w-alt1-0 {
- st,pins {
- mtsr = <&pio17 7 ALT1 OUT>;
- mrst = <&pio17 5 ALT1 IN>;
- scl = <&pio17 6 ALT1 OUT>;
- };
- };
-
- pinctrl_spi3_3w_alt1_0: spi3-3w-alt1-0 {
- st,pins {
- mtsr = <&pio17 7 ALT1 BIDIR_PU>;
- scl = <&pio17 6 ALT1 OUT>;
- };
- };
-
- pinctrl_spi3_4w_alt1_1: spi3-4w-alt1-1 {
- st,pins {
- mtsr = <&pio18 6 ALT1 OUT>;
- mrst = <&pio18 7 ALT1 IN>;
- scl = <&pio18 5 ALT1 OUT>;
- };
- };
-
- pinctrl_spi3_3w_alt1_1: spi3-3w-alt1-1 {
- st,pins {
- mtsr = <&pio18 6 ALT1 BIDIR_PU>;
- scl = <&pio18 5 ALT1 OUT>;
- };
- };
- };
-
- tsin0 {
- pinctrl_tsin0_parallel: tsin0_parallel {
- st,pins {
- DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA6 = <&pio10 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA5 = <&pio10 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA4 = <&pio10 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA3 = <&pio11 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA2 = <&pio11 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA1 = <&pio11 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA0 = <&pio11 3 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
- VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- };
- };
- pinctrl_tsin0_serial: tsin0_serial {
- st,pins {
- DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
- VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- };
- };
- };
-
- tsin1 {
- pinctrl_tsin1_parallel: tsin1_parallel {
- st,pins {
- DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA6 = <&pio12 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA5 = <&pio12 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA4 = <&pio12 3 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA3 = <&pio12 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA2 = <&pio12 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA1 = <&pio12 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA0 = <&pio12 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>;
- VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- };
- };
- pinctrl_tsin1_serial: tsin1_serial {
- st,pins {
- DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>;
- VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- };
- };
- };
-
- tsin2 {
- pinctrl_tsin2_parallel: tsin2_parallel {
- st,pins {
- DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA6 = <&pio13 5 ALT2 IN SE_NICLK_IO 0 CLK_B>;
- DATA5 = <&pio13 6 ALT2 IN SE_NICLK_IO 0 CLK_B>;
- DATA4 = <&pio13 7 ALT2 IN SE_NICLK_IO 0 CLK_B>;
- DATA3 = <&pio14 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
- DATA2 = <&pio14 1 ALT2 IN SE_NICLK_IO 0 CLK_B>;
- DATA1 = <&pio14 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
- DATA0 = <&pio14 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
- VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- };
- };
- pinctrl_tsin2_serial: tsin2_serial {
- st,pins {
- DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
- VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- };
- };
- };
-
- tsin3 {
- pinctrl_tsin3_serial: tsin3_serial {
- st,pins {
- DATA7 = <&pio14 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio14 0 ALT1 IN CLKNOTDATA 0 CLK_A>;
- VALID = <&pio13 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- ERROR = <&pio13 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- PKCLK = <&pio13 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- };
- };
- };
-
- tsin4 {
- pinctrl_tsin4_serial_alt3: tsin4_serial_alt3 {
- st,pins {
- DATA7 = <&pio14 6 ALT3 IN SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio14 5 ALT3 IN CLKNOTDATA 0 CLK_A>;
- VALID = <&pio14 3 ALT3 IN SE_NICLK_IO 0 CLK_B>;
- ERROR = <&pio14 2 ALT3 IN SE_NICLK_IO 0 CLK_B>;
- PKCLK = <&pio14 4 ALT3 IN SE_NICLK_IO 0 CLK_A>;
- };
- };
- };
-
- tsin5 {
- pinctrl_tsin5_serial_alt1: tsin5_serial_alt1 {
- st,pins {
- DATA7 = <&pio18 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio18 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
- VALID = <&pio18 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- ERROR = <&pio18 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- PKCLK = <&pio18 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- };
- };
- pinctrl_tsin5_serial_alt2: tsin5_serial_alt2 {
- st,pins {
- DATA7 = <&pio19 4 ALT2 IN SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio19 3 ALT2 IN CLKNOTDATA 0 CLK_A>;
- VALID = <&pio19 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
- ERROR = <&pio19 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
- PKCLK = <&pio19 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
- };
- };
- };
-
- tsout0 {
- pinctrl_tsout0_parallel: tsout0_parallel {
- st,pins {
- DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- DATA6 = <&pio12 1 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- DATA5 = <&pio12 2 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- DATA4 = <&pio12 3 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- DATA3 = <&pio12 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- DATA2 = <&pio12 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- DATA1 = <&pio12 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- DATA0 = <&pio12 7 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>;
- VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- };
- };
- pinctrl_tsout0_serial: tsout0_serial {
- st,pins {
- DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>;
- VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- };
- };
- };
-
- tsout1 {
- pinctrl_tsout1_serial: tsout1_serial {
- st,pins {
- DATA7 = <&pio19 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio19 3 ALT1 OUT NICLK 0 CLK_A>;
- VALID = <&pio19 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- ERROR = <&pio19 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- PKCLK = <&pio19 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- };
- };
- };
-
- mtsin0 {
- pinctrl_mtsin0_parallel: mtsin0_parallel {
- st,pins {
- DATA7 = <&pio10 4 ALT3 IN SE_NICLK_IO 0 CLK_A>;
- DATA6 = <&pio10 5 ALT3 IN SE_NICLK_IO 0 CLK_A>;
- DATA5 = <&pio10 6 ALT3 IN SE_NICLK_IO 0 CLK_A>;
- DATA4 = <&pio10 7 ALT3 IN SE_NICLK_IO 0 CLK_A>;
- DATA3 = <&pio11 0 ALT3 IN SE_NICLK_IO 0 CLK_A>;
- DATA2 = <&pio11 1 ALT3 IN SE_NICLK_IO 0 CLK_A>;
- DATA1 = <&pio11 2 ALT3 IN SE_NICLK_IO 0 CLK_A>;
- DATA0 = <&pio11 3 ALT3 IN SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio10 3 ALT3 IN CLKNOTDATA 0 CLK_A>;
- VALID = <&pio10 1 ALT3 IN SE_NICLK_IO 0 CLK_A>;
- ERROR = <&pio10 0 ALT3 IN SE_NICLK_IO 0 CLK_A>;
- PKCLK = <&pio10 2 ALT3 IN SE_NICLK_IO 0 CLK_A>;
- };
- };
- };
-
- systrace {
- pinctrl_systrace_default: systrace-default {
- st,pins {
- trc_data0 = <&pio11 3 ALT5 OUT>;
- trc_data1 = <&pio11 4 ALT5 OUT>;
- trc_data2 = <&pio11 5 ALT5 OUT>;
- trc_data3 = <&pio11 6 ALT5 OUT>;
- trc_clk = <&pio11 7 ALT5 OUT>;
- };
- };
- };
- };
-
- pin-controller-front1@921f080 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stih407-front-pinctrl";
- st,syscfg = <&syscfg_front>;
- reg = <0x0921f080 0x4>;
- reg-names = "irqmux";
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irqmux";
- ranges = <0 0x09210000 0x10000>;
-
- pio20: pio@9210000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x0 0x100>;
- st,bank-name = "PIO20";
- };
-
- tsin4 {
- pinctrl_tsin4_serial_alt1: tsin4_serial_alt1 {
- st,pins {
- DATA7 = <&pio20 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio20 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
- VALID = <&pio20 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- ERROR = <&pio20 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- PKCLK = <&pio20 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- };
- };
- };
- };
-
- pin-controller-rear@922f080 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stih407-rear-pinctrl";
- st,syscfg = <&syscfg_rear>;
- reg = <0x0922f080 0x4>;
- reg-names = "irqmux";
- interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irqmux";
- ranges = <0 0x09220000 0x6000>;
-
- pio30: gpio@9220000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x0 0x100>;
- st,bank-name = "PIO30";
- };
- pio31: gpio@9221000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x100>;
- st,bank-name = "PIO31";
- };
- pio32: gpio@9222000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x100>;
- st,bank-name = "PIO32";
- };
- pio33: gpio@9223000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x3000 0x100>;
- st,bank-name = "PIO33";
- };
- pio34: gpio@9224000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x4000 0x100>;
- st,bank-name = "PIO34";
- };
- pio35: gpio@9225000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x5000 0x100>;
- st,bank-name = "PIO35";
- st,retime-pin-mask = <0x7f>;
- };
-
- i2c4 {
- pinctrl_i2c4_default: i2c4-default {
- st,pins {
- sda = <&pio30 1 ALT1 BIDIR>;
- scl = <&pio30 0 ALT1 BIDIR>;
- };
- };
- };
-
- i2c5 {
- pinctrl_i2c5_default: i2c5-default {
- st,pins {
- sda = <&pio34 4 ALT1 BIDIR>;
- scl = <&pio34 3 ALT1 BIDIR>;
- };
- };
- };
-
- usb3 {
- pinctrl_usb3: usb3-2 {
- st,pins {
- usb-oc-detect = <&pio35 4 ALT1 IN>;
- usb-pwr-enable = <&pio35 5 ALT1 OUT>;
- usb-vbus-valid = <&pio35 6 ALT1 IN>;
- };
- };
- };
-
- pwm0 {
- pinctrl_pwm0_chan0_default: pwm0-0-default {
- st,pins {
- pwm-capturein = <&pio31 0 ALT1 IN>;
- pwm-out = <&pio31 1 ALT1 OUT>;
- };
- };
- };
-
- spi4 {
- pinctrl_spi4_default: spi4-4w-alt1-0 {
- st,pins {
- mtsr = <&pio30 1 ALT1 OUT>;
- mrst = <&pio30 2 ALT1 IN>;
- scl = <&pio30 0 ALT1 OUT>;
- };
- };
-
- pinctrl_spi4_3w_alt1_0: spi4-3w-alt1-0 {
- st,pins {
- mtsr = <&pio30 1 ALT1 BIDIR_PU>;
- scl = <&pio30 0 ALT1 OUT>;
- };
- };
-
- pinctrl_spi4_4w_alt3_0: spi4-4w-alt3-0 {
- st,pins {
- mtsr = <&pio34 1 ALT3 OUT>;
- mrst = <&pio34 2 ALT3 IN>;
- scl = <&pio34 0 ALT3 OUT>;
- };
- };
-
- pinctrl_spi4_3w_alt3_0: spi4-3w-alt3-0 {
- st,pins {
- mtsr = <&pio34 1 ALT3 BIDIR_PU>;
- scl = <&pio34 0 ALT3 OUT>;
- };
- };
- };
-
- i2s_out {
- pinctrl_i2s_8ch_out: i2s_8ch_out{
- st,pins {
- mclk = <&pio33 5 ALT1 OUT>;
- lrclk = <&pio33 7 ALT1 OUT>;
- sclk = <&pio33 6 ALT1 OUT>;
- data0 = <&pio33 4 ALT1 OUT>;
- data1 = <&pio34 0 ALT1 OUT>;
- data2 = <&pio34 1 ALT1 OUT>;
- data3 = <&pio34 2 ALT1 OUT>;
- };
- };
-
- pinctrl_i2s_2ch_out: i2s_2ch_out{
- st,pins {
- mclk = <&pio33 5 ALT1 OUT>;
- lrclk = <&pio33 7 ALT1 OUT>;
- sclk = <&pio33 6 ALT1 OUT>;
- data0 = <&pio33 4 ALT1 OUT>;
- };
- };
- };
-
- i2s_in {
- pinctrl_i2s_8ch_in: i2s_8ch_in{
- st,pins {
- mclk = <&pio32 5 ALT1 IN>;
- lrclk = <&pio32 7 ALT1 IN>;
- sclk = <&pio32 6 ALT1 IN>;
- data0 = <&pio32 4 ALT1 IN>;
- data1 = <&pio33 0 ALT1 IN>;
- data2 = <&pio33 1 ALT1 IN>;
- data3 = <&pio33 2 ALT1 IN>;
- data4 = <&pio33 3 ALT1 IN>;
- };
- };
-
- pinctrl_i2s_2ch_in: i2s_2ch_in{
- st,pins {
- mclk = <&pio32 5 ALT1 IN>;
- lrclk = <&pio32 7 ALT1 IN>;
- sclk = <&pio32 6 ALT1 IN>;
- data0 = <&pio32 4 ALT1 IN>;
- };
- };
- };
-
- spdif_out {
- pinctrl_spdif_out: spdif_out{
- st,pins {
- spdif_out = <&pio34 7 ALT1 OUT>;
- };
- };
- };
-
- serial3 {
- pinctrl_serial3: serial3-0 {
- st,pins {
- tx = <&pio31 3 ALT1 OUT>;
- rx = <&pio31 4 ALT1 IN>;
- };
- };
- };
- };
-
- pin-controller-flash@923f080 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stih407-flash-pinctrl";
- st,syscfg = <&syscfg_flash>;
- reg = <0x0923f080 0x4>;
- reg-names = "irqmux";
- interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irqmux";
- ranges = <0 0x09230000 0x3000>;
-
- pio40: gpio@9230000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0 0x100>;
- st,bank-name = "PIO40";
- };
- pio41: gpio@9231000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x100>;
- st,bank-name = "PIO41";
- };
- pio42: gpio@9232000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x100>;
- st,bank-name = "PIO42";
- };
-
- mmc0 {
- pinctrl_mmc0: mmc0-0 {
- st,pins {
- emmc_clk = <&pio40 6 ALT1 BIDIR>;
- emmc_cmd = <&pio40 7 ALT1 BIDIR_PU>;
- emmc_d0 = <&pio41 0 ALT1 BIDIR_PU>;
- emmc_d1 = <&pio41 1 ALT1 BIDIR_PU>;
- emmc_d2 = <&pio41 2 ALT1 BIDIR_PU>;
- emmc_d3 = <&pio41 3 ALT1 BIDIR_PU>;
- emmc_d4 = <&pio41 4 ALT1 BIDIR_PU>;
- emmc_d5 = <&pio41 5 ALT1 BIDIR_PU>;
- emmc_d6 = <&pio41 6 ALT1 BIDIR_PU>;
- emmc_d7 = <&pio41 7 ALT1 BIDIR_PU>;
- };
- };
- pinctrl_sd0: sd0-0 {
- st,pins {
- sd_clk = <&pio40 6 ALT1 BIDIR>;
- sd_cmd = <&pio40 7 ALT1 BIDIR_PU>;
- sd_dat0 = <&pio41 0 ALT1 BIDIR_PU>;
- sd_dat1 = <&pio41 1 ALT1 BIDIR_PU>;
- sd_dat2 = <&pio41 2 ALT1 BIDIR_PU>;
- sd_dat3 = <&pio41 3 ALT1 BIDIR_PU>;
- sd_led = <&pio42 0 ALT2 OUT>;
- sd_pwren = <&pio42 2 ALT2 OUT>;
- sd_vsel = <&pio42 3 ALT2 OUT>;
- sd_cd = <&pio42 4 ALT2 IN>;
- sd_wp = <&pio42 5 ALT2 IN>;
- };
- };
- };
-
- fsm {
- pinctrl_fsm: fsm {
- st,pins {
- spi-fsm-clk = <&pio40 1 ALT1 OUT>;
- spi-fsm-cs = <&pio40 0 ALT1 OUT>;
- spi-fsm-mosi = <&pio40 2 ALT1 OUT>;
- spi-fsm-miso = <&pio40 3 ALT1 IN>;
- spi-fsm-hol = <&pio40 5 ALT1 OUT>;
- spi-fsm-wp = <&pio40 4 ALT1 OUT>;
- };
- };
- };
-
- nand {
- pinctrl_nand: nand {
- st,pins {
- nand_cs1 = <&pio40 6 ALT3 OUT>;
- nand_cs0 = <&pio40 7 ALT3 OUT>;
- nand_d0 = <&pio41 0 ALT3 BIDIR>;
- nand_d1 = <&pio41 1 ALT3 BIDIR>;
- nand_d2 = <&pio41 2 ALT3 BIDIR>;
- nand_d3 = <&pio41 3 ALT3 BIDIR>;
- nand_d4 = <&pio41 4 ALT3 BIDIR>;
- nand_d5 = <&pio41 5 ALT3 BIDIR>;
- nand_d6 = <&pio41 6 ALT3 BIDIR>;
- nand_d7 = <&pio41 7 ALT3 BIDIR>;
- nand_we = <&pio42 0 ALT3 OUT>;
- nand_dqs = <&pio42 1 ALT3 OUT>;
- nand_ale = <&pio42 2 ALT3 OUT>;
- nand_cle = <&pio42 3 ALT3 OUT>;
- nand_rnb = <&pio42 4 ALT3 IN>;
- nand_oe = <&pio42 5 ALT3 OUT>;
- };
- };
- };
- };
- };
-};
diff --git a/arch/arm/dts/stih410-b2260-u-boot.dtsi b/arch/arm/dts/stih410-b2260-u-boot.dtsi
index e9d7ec9..1aa0a58 100644
--- a/arch/arm/dts/stih410-b2260-u-boot.dtsi
+++ b/arch/arm/dts/stih410-b2260-u-boot.dtsi
@@ -7,37 +7,35 @@
/{
soc {
- st_dwc3: dwc3@8f94000 {
- dwc3: dwc3@9900000 {
- dr_mode = "peripheral";
- phys = <&usb2_picophy0>;
- };
- };
-
clk_usb: clk-usb {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
+ };
+};
- ohci0: usb@9a03c00 {
- compatible = "generic-ohci";
- clocks = <&clk_usb>;
- };
+&dwc3 {
+ dr_mode = "peripheral";
+ phys = <&usb2_picophy0>;
+};
- ehci0: usb@9a03e00 {
- compatible = "generic-ehci";
- clocks = <&clk_usb>;
- };
+&ehci0 {
+ compatible = "st,st-ehci-300x", "generic-ehci";
+ clocks = <&clk_usb>;
+};
- ohci1: usb@9a83c00 {
- compatible = "generic-ohci";
- clocks = <&clk_usb>;
- };
+&ehci1 {
+ compatible = "st,st-ehci-300x", "generic-ehci";
+ clocks = <&clk_usb>;
+};
- ehci1: usb@9a83e00 {
- compatible = "generic-ehci";
- clocks = <&clk_usb>;
- };
- };
+&ohci0 {
+ compatible = "st,st-ehci-300x", "generic-ehci";
+ clocks = <&clk_usb>;
+};
+
+&ohci1 {
+ compatible = "st,st-ehci-300x", "generic-ehci";
+ clocks = <&clk_usb>;
};
diff --git a/arch/arm/dts/stih410-b2260.dts b/arch/arm/dts/stih410-b2260.dts
deleted file mode 100644
index 8c4155b..0000000
--- a/arch/arm/dts/stih410-b2260.dts
+++ /dev/null
@@ -1,214 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2016 STMicroelectronics (R&D) Limited.
- * Author: Patrice Chotard <patrice.chotard@foss.st.com>
- */
-/dts-v1/;
-#include "stih410.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "STiH410 B2260";
- compatible = "st,stih410-b2260", "st,stih410";
-
- chosen {
- bootargs = "clk_ignore_unused";
- stdout-path = &uart1;
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0x40000000 0x40000000>;
- };
-
- aliases {
- serial1 = &uart1;
- ethernet0 = ðernet0;
- };
-
- leds {
- compatible = "gpio-leds";
- user_green_1 {
- label = "User_green_1";
- gpios = <&pio1 3 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- default-state = "off";
- };
-
- user_green_2 {
- label = "User_green_2";
- gpios = <&pio4 1 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- user_green_3 {
- label = "User_green_3";
- gpios = <&pio2 1 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- user_green_4 {
- label = "User_green_4";
- gpios = <&pio2 5 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
- };
-
- sound: sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "STI-B2260";
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
-
- simple-audio-card,dai-link@0 {
- reg = <0>;
- /* DAC */
- format = "i2s";
- mclk-fs = <128>;
- cpu {
- sound-dai = <&sti_uni_player0>;
- };
-
- codec {
- sound-dai = <&sti_hdmi>;
- };
- };
- };
-
- soc {
- /* Low speed expansion connector */
- uart0: serial@9830000 {
- label = "LS-UART0";
- pinctrl-names = "default", "no-hw-flowctrl";
- pinctrl-0 = <&pinctrl_serial0_hw_flowctrl>;
- pinctrl-1 = <&pinctrl_serial0>;
- rts-gpios = <&pio17 3 GPIO_ACTIVE_LOW>;
- uart-has-rtscts;
- status = "okay";
- };
-
- /* Low speed expansion connector */
- uart1: serial@9831000 {
- label = "LS-UART1";
- status = "okay";
- };
-
- /* Low speed expansion connector */
- spi0: spi@9844000 {
- label = "LS-SPI0";
- cs-gpios = <&pio30 3 0>;
- status = "okay";
- };
-
- /* Low speed expansion connector */
- i2c0: i2c@9840000 {
- label = "LS-I2C0";
- status = "okay";
- };
-
- /* Low speed expansion connector */
- i2c1: i2c@9841000 {
- label = "LS-I2C1";
- status = "okay";
- };
-
- /* high speed expansion connector */
- i2c2: i2c@9842000 {
- label = "HS-I2C2";
- pinctrl-0 = <&pinctrl_i2c2_alt2_1>;
- status = "okay";
- };
-
- /* high speed expansion connector */
- i2c3: i2c@9843000 {
- label = "HS-I2C3";
- pinctrl-0 = <&pinctrl_i2c3_alt3_0>;
- status = "okay";
- };
-
- mmc0: sdhci@9060000 {
- pinctrl-0 = <&pinctrl_sd0>;
- bus-width = <4>;
- status = "okay";
- };
-
- /* high speed expansion connector */
- mmc1: sdhci@9080000 {
- status = "okay";
- };
-
- pwm0: pwm@9810000 {
- status = "okay";
- };
-
- pwm1: pwm@9510000 {
- status = "okay";
- };
-
- usb2_picophy1: phy2@0 {
- status = "okay";
- };
-
- usb2_picophy2: phy3@0 {
- status = "okay";
- };
-
- ohci0: usb@9a03c00 {
- status = "okay";
- };
-
- ehci0: usb@9a03e00 {
- status = "okay";
- };
-
- ohci1: usb@9a83c00 {
- status = "okay";
- };
-
- ehci1: usb@9a83e00 {
- status = "okay";
- };
-
- st_dwc3: dwc3@8f94000 {
- status = "okay";
- };
-
- ethernet0: dwmac@9630000 {
- phy-mode = "rgmii";
- pinctrl-0 = <&pinctrl_rgmii1 &pinctrl_rgmii1_mdio_1>;
-
- snps,phy-bus-name = "stmmac";
- snps,phy-bus-id = <0>;
- snps,phy-addr = <0>;
- snps,reset-gpio = <&pio0 7 0>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 1000000>;
-
- status = "okay";
- };
-
- sti_uni_player0: sti-uni-player@8d80000 {
- status = "okay";
- };
- /* SSC11 to HDMI */
- hdmiddc: i2c@9541000 {
- /* HDMI V1.3a supports Standard mode only */
- clock-frequency = <100000>;
- st,i2c-min-scl-pulse-width-us = <0>;
- st,i2c-min-sda-pulse-width-us = <5>;
- status = "okay";
- };
-
- miphy28lp_phy: miphy28lp@0 {
-
- phy_port1: port@9b2a000 {
- st,osc-force-ext;
- };
- };
-
- sata1: sata@9b28000 {
- status = "okay";
- };
- };
-};
diff --git a/arch/arm/dts/stih410-clock.dtsi b/arch/arm/dts/stih410-clock.dtsi
deleted file mode 100644
index 81a8c25..0000000
--- a/arch/arm/dts/stih410-clock.dtsi
+++ /dev/null
@@ -1,333 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2014 STMicroelectronics R&D Limited
- */
-#include <dt-bindings/clock/stih410-clks.h>
-/ {
- /*
- * Fixed 30MHz oscillator inputs to SoC
- */
- clk_sysin: clk-sysin {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <30000000>;
- clock-output-names = "CLK_SYSIN";
- };
-
- clk_tmdsout_hdmi: clk-tmdsout-hdmi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- compatible = "st,stih410-clk", "simple-bus";
-
- /*
- * A9 PLL.
- */
- clockgen-a9@92b0000 {
- compatible = "st,clkgen-c32";
- reg = <0x92b0000 0xffff>;
-
- clockgen_a9_pll: clockgen-a9-pll {
- #clock-cells = <1>;
- compatible = "st,stih407-clkgen-plla9";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clockgen-a9-pll-odf";
- };
- };
-
- /*
- * ARM CPU related clocks.
- */
- clk_m_a9: clk-m-a9@92b0000 {
- #clock-cells = <0>;
- compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
- reg = <0x92b0000 0x10000>;
-
- clocks = <&clockgen_a9_pll 0>,
- <&clockgen_a9_pll 0>,
- <&clk_s_c0_flexgen 13>,
- <&clk_m_a9_ext2f_div2>;
- /*
- * ARM Peripheral clock for timers
- */
- arm_periph_clk: clk-m-a9-periphs {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&clk_m_a9>;
- clock-div = <2>;
- clock-mult = <1>;
- };
- };
-
- clockgen-a@90ff000 {
- compatible = "st,clkgen-c32";
- reg = <0x90ff000 0x1000>;
-
- clk_s_a0_pll: clk-s-a0-pll {
- #clock-cells = <1>;
- compatible = "st,clkgen-pll0";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-a0-pll-ofd-0";
- clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
- };
-
- clk_s_a0_flexgen: clk-s-a0-flexgen {
- compatible = "st,flexgen";
-
- #clock-cells = <1>;
-
- clocks = <&clk_s_a0_pll 0>,
- <&clk_sysin>;
-
- clock-output-names = "clk-ic-lmi0",
- "clk-ic-lmi1";
- clock-critical = <CLK_IC_LMI0>;
- };
- };
-
- clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
- #clock-cells = <1>;
- compatible = "st,quadfs-pll";
- reg = <0x9103000 0x1000>;
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-fs0-ch0",
- "clk-s-c0-fs0-ch1",
- "clk-s-c0-fs0-ch2",
- "clk-s-c0-fs0-ch3";
- clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
- };
-
- clk_s_c0: clockgen-c@9103000 {
- compatible = "st,clkgen-c32";
- reg = <0x9103000 0x1000>;
-
- clk_s_c0_pll0: clk-s-c0-pll0 {
- #clock-cells = <1>;
- compatible = "st,clkgen-pll0";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-pll0-odf-0";
- clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
- };
-
- clk_s_c0_pll1: clk-s-c0-pll1 {
- #clock-cells = <1>;
- compatible = "st,clkgen-pll1";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-pll1-odf-0";
- };
-
- clk_s_c0_flexgen: clk-s-c0-flexgen {
- #clock-cells = <1>;
- compatible = "st,flexgen";
-
- clocks = <&clk_s_c0_pll0 0>,
- <&clk_s_c0_pll1 0>,
- <&clk_s_c0_quadfs 0>,
- <&clk_s_c0_quadfs 1>,
- <&clk_s_c0_quadfs 2>,
- <&clk_s_c0_quadfs 3>,
- <&clk_sysin>;
-
- clock-output-names = "clk-icn-gpu",
- "clk-fdma",
- "clk-nand",
- "clk-hva",
- "clk-proc-stfe",
- "clk-proc-tp",
- "clk-rx-icn-dmu",
- "clk-rx-icn-hva",
- "clk-icn-cpu",
- "clk-tx-icn-dmu",
- "clk-mmc-0",
- "clk-mmc-1",
- "clk-jpegdec",
- "clk-ext2fa9",
- "clk-ic-bdisp-0",
- "clk-ic-bdisp-1",
- "clk-pp-dmu",
- "clk-vid-dmu",
- "clk-dss-lpc",
- "clk-st231-aud-0",
- "clk-st231-gp-1",
- "clk-st231-dmu",
- "clk-icn-lmi",
- "clk-tx-icn-disp-1",
- "clk-icn-sbc",
- "clk-stfe-frc2",
- "clk-eth-phy",
- "clk-eth-ref-phyclk",
- "clk-flash-promip",
- "clk-main-disp",
- "clk-aux-disp",
- "clk-compo-dvp",
- "clk-tx-icn-hades",
- "clk-rx-icn-hades",
- "clk-icn-reg-16",
- "clk-pp-hades",
- "clk-clust-hades",
- "clk-hwpe-hades",
- "clk-fc-hades";
- clock-critical = <CLK_PROC_STFE>,
- <CLK_ICN_CPU>,
- <CLK_TX_ICN_DMU>,
- <CLK_EXT2F_A9>,
- <CLK_ICN_LMI>,
- <CLK_ICN_SBC>;
-
- /*
- * ARM Peripheral clock for timers
- */
- clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
-
- clocks = <&clk_s_c0_flexgen 13>;
-
- clock-output-names = "clk-m-a9-ext2f-div2";
-
- clock-div = <2>;
- clock-mult = <1>;
- };
- };
- };
-
- clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
- #clock-cells = <1>;
- compatible = "st,quadfs";
- reg = <0x9104000 0x1000>;
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d0-fs0-ch0",
- "clk-s-d0-fs0-ch1",
- "clk-s-d0-fs0-ch2",
- "clk-s-d0-fs0-ch3";
- };
-
- clockgen-d0@9104000 {
- compatible = "st,clkgen-c32";
- reg = <0x9104000 0x1000>;
-
- clk_s_d0_flexgen: clk-s-d0-flexgen {
- #clock-cells = <1>;
- compatible = "st,flexgen-audio", "st,flexgen";
-
- clocks = <&clk_s_d0_quadfs 0>,
- <&clk_s_d0_quadfs 1>,
- <&clk_s_d0_quadfs 2>,
- <&clk_s_d0_quadfs 3>,
- <&clk_sysin>;
-
- clock-output-names = "clk-pcm-0",
- "clk-pcm-1",
- "clk-pcm-2",
- "clk-spdiff",
- "clk-pcmr10-master",
- "clk-usb2-phy";
- };
- };
-
- clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
- #clock-cells = <1>;
- compatible = "st,quadfs";
- reg = <0x9106000 0x1000>;
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d2-fs0-ch0",
- "clk-s-d2-fs0-ch1",
- "clk-s-d2-fs0-ch2",
- "clk-s-d2-fs0-ch3";
- };
-
- clockgen-d2@9106000 {
- compatible = "st,clkgen-c32";
- reg = <0x9106000 0x1000>;
-
- clk_s_d2_flexgen: clk-s-d2-flexgen {
- #clock-cells = <1>;
- compatible = "st,flexgen-video", "st,flexgen";
-
- clocks = <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 1>,
- <&clk_s_d2_quadfs 2>,
- <&clk_s_d2_quadfs 3>,
- <&clk_sysin>,
- <&clk_sysin>,
- <&clk_tmdsout_hdmi>;
-
- clock-output-names = "clk-pix-main-disp",
- "clk-pix-pip",
- "clk-pix-gdp1",
- "clk-pix-gdp2",
- "clk-pix-gdp3",
- "clk-pix-gdp4",
- "clk-pix-aux-disp",
- "clk-denc",
- "clk-pix-hddac",
- "clk-hddac",
- "clk-sddac",
- "clk-pix-dvo",
- "clk-dvo",
- "clk-pix-hdmi",
- "clk-tmds-hdmi",
- "clk-ref-hdmiphy";
- };
- };
-
- clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
- #clock-cells = <1>;
- compatible = "st,quadfs";
- reg = <0x9107000 0x1000>;
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d3-fs0-ch0",
- "clk-s-d3-fs0-ch1",
- "clk-s-d3-fs0-ch2",
- "clk-s-d3-fs0-ch3";
- };
-
- clockgen-d3@9107000 {
- compatible = "st,clkgen-c32";
- reg = <0x9107000 0x1000>;
-
- clk_s_d3_flexgen: clk-s-d3-flexgen {
- #clock-cells = <1>;
- compatible = "st,flexgen";
-
- clocks = <&clk_s_d3_quadfs 0>,
- <&clk_s_d3_quadfs 1>,
- <&clk_s_d3_quadfs 2>,
- <&clk_s_d3_quadfs 3>,
- <&clk_sysin>;
-
- clock-output-names = "clk-stfe-frc1",
- "clk-tsout-0",
- "clk-tsout-1",
- "clk-mchi",
- "clk-vsens-compo",
- "clk-frc1-remote",
- "clk-lpc-0",
- "clk-lpc-1";
- };
- };
- };
-};
diff --git a/arch/arm/dts/stih410-pinctrl.dtsi b/arch/arm/dts/stih410-pinctrl.dtsi
deleted file mode 100644
index e6eadd1..0000000
--- a/arch/arm/dts/stih410-pinctrl.dtsi
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2014 STMicroelectronics Limited.
- * Author: Peter Griffin <peter.griffin@linaro.org>
- */
-#include "st-pincfg.h"
-/ {
-
- soc {
- pin-controller-rear@922f080 {
-
- usb0 {
- pinctrl_usb0: usb2-0 {
- st,pins {
- usb-oc-detect = <&pio35 0 ALT1 IN>;
- usb-pwr-enable = <&pio35 1 ALT1 OUT>;
- };
- };
- };
-
- usb1 {
- pinctrl_usb1: usb2-1 {
- st,pins {
- usb-oc-detect = <&pio35 2 ALT1 IN>;
- usb-pwr-enable = <&pio35 3 ALT1 OUT>;
- };
- };
- };
- };
- };
-};
diff --git a/arch/arm/dts/stih410.dtsi b/arch/arm/dts/stih410.dtsi
deleted file mode 100644
index 6d84701..0000000
--- a/arch/arm/dts/stih410.dtsi
+++ /dev/null
@@ -1,300 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2014 STMicroelectronics Limited.
- * Author: Peter Griffin <peter.griffin@linaro.org>
- */
-#include "stih410-clock.dtsi"
-#include "stih407-family.dtsi"
-#include "stih410-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-/ {
- aliases {
- bdisp0 = &bdisp0;
- };
-
- soc {
- usb2_picophy1: phy2@0 {
- compatible = "st,stih407-usb2-phy";
- reg = <0 0>;
- #phy-cells = <0>;
- st,syscfg = <&syscfg_core 0xf8 0xf4>;
- resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
- <&picophyreset STIH407_PICOPHY0_RESET>;
- reset-names = "global", "port";
-
- status = "disabled";
- };
-
- usb2_picophy2: phy3@0 {
- compatible = "st,stih407-usb2-phy";
- reg = <0 0>;
- #phy-cells = <0>;
- st,syscfg = <&syscfg_core 0xfc 0xf4>;
- resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
- <&picophyreset STIH407_PICOPHY1_RESET>;
- reset-names = "global", "port";
-
- status = "disabled";
- };
-
- ohci0: usb@9a03c00 {
- compatible = "st,st-ohci-300x";
- reg = <0x9a03c00 0x100>;
- interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
- <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
- resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
- <&softreset STIH407_USB2_PORT0_SOFTRESET>;
- reset-names = "power", "softreset";
- phys = <&usb2_picophy1>;
- phy-names = "usb";
-
- status = "disabled";
- };
-
- ehci0: usb@9a03e00 {
- compatible = "st,st-ehci-300x";
- reg = <0x9a03e00 0x100>;
- interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>;
- clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
- <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
- resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
- <&softreset STIH407_USB2_PORT0_SOFTRESET>;
- reset-names = "power", "softreset";
- phys = <&usb2_picophy1>;
- phy-names = "usb";
-
- status = "disabled";
- };
-
- ohci1: usb@9a83c00 {
- compatible = "st,st-ohci-300x";
- reg = <0x9a83c00 0x100>;
- interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
- <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
- resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
- <&softreset STIH407_USB2_PORT1_SOFTRESET>;
- reset-names = "power", "softreset";
- phys = <&usb2_picophy2>;
- phy-names = "usb";
-
- status = "disabled";
- };
-
- ehci1: usb@9a83e00 {
- compatible = "st,st-ehci-300x";
- reg = <0x9a83e00 0x100>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>;
- clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
- <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
- resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
- <&softreset STIH407_USB2_PORT1_SOFTRESET>;
- reset-names = "power", "softreset";
- phys = <&usb2_picophy2>;
- phy-names = "usb";
-
- status = "disabled";
- };
-
- sti-display-subsystem@0 {
- compatible = "st,sti-display-subsystem";
- #address-cells = <1>;
- #size-cells = <1>;
-
- reg = <0 0>;
- assigned-clocks = <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 1>,
- <&clk_s_c0_pll1 0>,
- <&clk_s_c0_flexgen CLK_COMPO_DVP>,
- <&clk_s_c0_flexgen CLK_MAIN_DISP>,
- <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
- <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
- <&clk_s_d2_flexgen CLK_PIX_GDP1>,
- <&clk_s_d2_flexgen CLK_PIX_GDP2>,
- <&clk_s_d2_flexgen CLK_PIX_GDP3>,
- <&clk_s_d2_flexgen CLK_PIX_GDP4>;
-
- assigned-clock-parents = <0>,
- <0>,
- <0>,
- <&clk_s_c0_pll1 0>,
- <&clk_s_c0_pll1 0>,
- <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 1>,
- <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 0>;
-
- assigned-clock-rates = <297000000>,
- <297000000>,
- <0>,
- <400000000>,
- <400000000>;
-
- ranges;
-
- sti-compositor@9d11000 {
- compatible = "st,stih407-compositor";
- reg = <0x9d11000 0x1000>;
-
- clock-names = "compo_main",
- "compo_aux",
- "pix_main",
- "pix_aux",
- "pix_gdp1",
- "pix_gdp2",
- "pix_gdp3",
- "pix_gdp4",
- "main_parent",
- "aux_parent";
-
- clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
- <&clk_s_c0_flexgen CLK_COMPO_DVP>,
- <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
- <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
- <&clk_s_d2_flexgen CLK_PIX_GDP1>,
- <&clk_s_d2_flexgen CLK_PIX_GDP2>,
- <&clk_s_d2_flexgen CLK_PIX_GDP3>,
- <&clk_s_d2_flexgen CLK_PIX_GDP4>,
- <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 1>;
-
- reset-names = "compo-main", "compo-aux";
- resets = <&softreset STIH407_COMPO_SOFTRESET>,
- <&softreset STIH407_COMPO_SOFTRESET>;
- st,vtg = <&vtg_main>, <&vtg_aux>;
- };
-
- sti-tvout@8d08000 {
- compatible = "st,stih407-tvout";
- reg = <0x8d08000 0x1000>;
- reg-names = "tvout-reg";
- reset-names = "tvout";
- resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
- #address-cells = <1>;
- #size-cells = <1>;
- assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
- <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
- <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
- <&clk_s_d0_flexgen CLK_PCM_0>,
- <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
- <&clk_s_d2_flexgen CLK_HDDAC>;
-
- assigned-clock-parents = <&clk_s_d2_quadfs 0>,
- <&clk_tmdsout_hdmi>,
- <&clk_s_d2_quadfs 0>,
- <&clk_s_d0_quadfs 0>,
- <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 0>;
- };
-
- sti_hdmi: sti-hdmi@8d04000 {
- compatible = "st,stih407-hdmi";
- reg = <0x8d04000 0x1000>;
- reg-names = "hdmi-reg";
- #sound-dai-cells = <0>;
- interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq";
- clock-names = "pix",
- "tmds",
- "phy",
- "audio",
- "main_parent",
- "aux_parent";
-
- clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
- <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
- <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
- <&clk_s_d0_flexgen CLK_PCM_0>,
- <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 1>;
-
- hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>;
- reset-names = "hdmi";
- resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
- ddc = <&hdmiddc>;
- };
-
- sti-hda@8d02000 {
- compatible = "st,stih407-hda";
- status = "disabled";
- reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
- reg-names = "hda-reg", "video-dacs-ctrl";
- clock-names = "pix",
- "hddac",
- "main_parent",
- "aux_parent";
- clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
- <&clk_s_d2_flexgen CLK_HDDAC>,
- <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 1>;
- };
-
- sti-hqvdp@9c00000 {
- compatible = "st,stih407-hqvdp";
- reg = <0x9C00000 0x100000>;
- clock-names = "hqvdp", "pix_main";
- clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>,
- <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>;
- reset-names = "hqvdp";
- resets = <&softreset STIH407_HDQVDP_SOFTRESET>;
- st,vtg = <&vtg_main>;
- };
- };
-
- bdisp0:bdisp@9f10000 {
- compatible = "st,stih407-bdisp";
- reg = <0x9f10000 0x1000>;
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "bdisp";
- clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>;
- };
-
- hva@8c85000 {
- compatible = "st,st-hva";
- reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
- reg-names = "hva_registers", "hva_esram";
- interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "clk_hva";
- clocks = <&clk_s_c0_flexgen CLK_HVA>;
- };
-
- thermal@91a0000 {
- compatible = "st,stih407-thermal";
- reg = <0x91a0000 0x28>;
- clock-names = "thermal";
- clocks = <&clk_sysin>;
- interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
- };
-
- delta0@0 {
- compatible = "st,st-delta";
- clock-names = "delta",
- "delta-st231",
- "delta-flash-promip";
- clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
- <&clk_s_c0_flexgen CLK_ST231_DMU>,
- <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
- };
-
- sti-cec@94a087c {
- compatible = "st,stih-cec";
- reg = <0x94a087c 0x64>;
- clocks = <&clk_sysin>;
- clock-names = "cec-clk";
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cec-irq";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_cec0_default>;
- resets = <&softreset STIH407_LPM_SOFTRESET>;
- hdmi-phandle = <&sti_hdmi>;
- };
- };
-};
diff --git a/arch/arm/dts/stm32429i-eval.dts b/arch/arm/dts/stm32429i-eval.dts
deleted file mode 100644
index 592b182..0000000
--- a/arch/arm/dts/stm32429i-eval.dts
+++ /dev/null
@@ -1,284 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015, STMicroelectronics - All Rights Reserved
- * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> for STMicroelectronics.
- */
-
-/dts-v1/;
-#include "stm32f429.dtsi"
-#include "stm32f429-pinctrl.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "STMicroelectronics STM32429i-EVAL board";
- compatible = "st,stm32429i-eval", "st,stm32f429";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@00000000 {
- device_type = "memory";
- reg = <0x00000000 0x2000000>;
- };
-
- aliases {
- serial0 = &usart1;
- };
-
- clocks {
- clk_ext_camera: clk-ext-camera {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- };
- };
-
- soc {
- dma-ranges = <0xc0000000 0x0 0x10000000>;
- };
-
- vdda: regulator-vdda {
- compatible = "regulator-fixed";
- regulator-name = "vdda";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vref: regulator-vref {
- compatible = "regulator-fixed";
- regulator-name = "vref";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vdd_panel: vdd-panel {
- compatible = "regulator-fixed";
- regulator-name = "vdd_panel";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- leds {
- compatible = "gpio-leds";
- led-green {
- gpios = <&gpiog 6 1>;
- linux,default-trigger = "heartbeat";
- };
- led-orange {
- gpios = <&gpiog 7 1>;
- };
- led-red {
- gpios = <&gpiog 10 1>;
- };
- led-blue {
- gpios = <&gpiog 12 1>;
- };
- };
-
- gpio_keys {
- compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- autorepeat;
- button@0 {
- label = "Wake up";
- linux,code = <KEY_WAKEUP>;
- gpios = <&gpioa 0 0>;
- };
- button@1 {
- label = "Tamper";
- linux,code = <KEY_RESTART>;
- gpios = <&gpioc 13 0>;
- };
- };
-
- usbotg_hs_phy: usbphy {
- #phy-cells = <0>;
- compatible = "usb-nop-xceiv";
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHSULPI)>;
- clock-names = "main_clk";
- };
-
- panel_rgb: panel-rgb {
- compatible = "ampire,am-480272h3tmqw-t01h";
- power-supply = <&vdd_panel>;
- status = "okay";
- port {
- panel_in_rgb: endpoint {
- remote-endpoint = <<dc_out_rgb>;
- };
- };
- };
-
- mmc_vcard: mmc_vcard {
- compatible = "regulator-fixed";
- regulator-name = "mmc_vcard";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-&adc {
- pinctrl-names = "default";
- pinctrl-0 = <&adc3_in8_pin>;
- vdda-supply = <&vdda>;
- vref-supply = <&vref>;
- status = "okay";
- adc3: adc@200 {
- st,adc-channels = <8>;
- status = "okay";
- };
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&crc {
- status = "okay";
-};
-
-&dcmi {
- status = "okay";
-
- port {
- dcmi_0: endpoint {
- remote-endpoint = <&ov2640_0>;
- bus-width = <8>;
- hsync-active = <0>;
- vsync-active = <0>;
- pclk-sample = <1>;
- };
- };
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- ov2640: camera@30 {
- compatible = "ovti,ov2640";
- reg = <0x30>;
- resetb-gpios = <&stmpegpio 2 GPIO_ACTIVE_HIGH>;
- pwdn-gpios = <&stmpegpio 0 GPIO_ACTIVE_LOW>;
- clocks = <&clk_ext_camera>;
- clock-names = "xvclk";
- status = "okay";
-
- port {
- ov2640_0: endpoint {
- remote-endpoint = <&dcmi_0>;
- };
- };
- };
-
- stmpe1600: stmpe1600@42 {
- compatible = "st,stmpe1600";
- reg = <0x42>;
- interrupts = <8 3>;
- interrupt-parent = <&gpioi>;
- interrupt-controller;
- wakeup-source;
-
- stmpegpio: stmpe_gpio {
- compatible = "st,stmpe-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- };
- };
-};
-
-&iwdg {
- status = "okay";
- timeout-sec = <32>;
-};
-
-<dc {
- status = "okay";
- pinctrl-0 = <<dc_pins_a>;
- pinctrl-names = "default";
-
- port {
- ltdc_out_rgb: endpoint {
- remote-endpoint = <&panel_in_rgb>;
- };
- };
-};
-
-&mac {
- status = "okay";
- pinctrl-0 = <ðernet_mii>;
- pinctrl-names = "default";
- phy-mode = "mii";
- phy-handle = <&phy1>;
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
- };
-};
-
-&rtc {
- status = "okay";
-};
-
-&sdio {
- status = "okay";
- vmmc-supply = <&mmc_vcard>;
- cd-gpios = <&stmpegpio 15 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default", "opendrain";
- pinctrl-0 = <&sdio_pins>;
- pinctrl-1 = <&sdio_pins_od>;
- bus-width = <4>;
- max-frequency = <12500000>;
-};
-
-&timers1 {
- status = "okay";
-
- pwm {
- pinctrl-0 = <&pwm1_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- timer@0 {
- status = "okay";
- };
-};
-
-&timers3 {
- status = "okay";
-
- pwm {
- pinctrl-0 = <&pwm3_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- timer@2 {
- status = "okay";
- };
-};
-
-&usart1 {
- pinctrl-0 = <&usart1_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_hs {
- dr_mode = "host";
- phys = <&usbotg_hs_phy>;
- phy-names = "usb2-phy";
- pinctrl-0 = <&usbotg_hs_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32746g-eval.dts b/arch/arm/dts/stm32746g-eval.dts
deleted file mode 100644
index 0e6445a..0000000
--- a/arch/arm/dts/stm32746g-eval.dts
+++ /dev/null
@@ -1,186 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
- *
- */
-
-/dts-v1/;
-#include "stm32f746.dtsi"
-#include "stm32f746-pinctrl.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
- model = "STMicroelectronics STM32746g-EVAL board";
- compatible = "st,stm32746g-eval", "st,stm32f746";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@c0000000 {
- device_type = "memory";
- reg = <0xc0000000 0x2000000>;
- };
-
- aliases {
- serial0 = &usart1;
- };
-
- leds {
- compatible = "gpio-leds";
- led-green {
- gpios = <&gpiof 10 1>;
- linux,default-trigger = "heartbeat";
- };
- led-orange {
- gpios = <&stmfx_pinctrl 17 1>;
- };
- led-red {
- gpios = <&gpiob 7 1>;
- };
- led-blue {
- gpios = <&stmfx_pinctrl 19 1>;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- button-0 {
- label = "Wake up";
- linux,code = <KEY_WAKEUP>;
- gpios = <&gpioc 13 0>;
- };
- };
-
- joystick {
- compatible = "gpio-keys";
- pinctrl-0 = <&joystick_pins>;
- pinctrl-names = "default";
- button-0 {
- label = "JoySel";
- linux,code = <KEY_ENTER>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
- };
- button-1 {
- label = "JoyDown";
- linux,code = <KEY_DOWN>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
- };
- button-2 {
- label = "JoyLeft";
- linux,code = <KEY_LEFT>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
- };
- button-3 {
- label = "JoyRight";
- linux,code = <KEY_RIGHT>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
- };
- button-4 {
- label = "JoyUp";
- linux,code = <KEY_UP>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
- };
- };
-
- usbotg_hs_phy: usb-phy {
- #phy-cells = <0>;
- compatible = "usb-nop-xceiv";
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
- clock-names = "main_clk";
- };
-
- mmc_vcard: mmc_vcard {
- compatible = "regulator-fixed";
- regulator-name = "mmc_vcard";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&crc {
- status = "okay";
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins_b>;
- pinctrl-names = "default";
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-
- stmfx: stmfx@42 {
- compatible = "st,stmfx-0300";
- reg = <0x42>;
- interrupts = <8 IRQ_TYPE_EDGE_RISING>;
- interrupt-parent = <&gpioi>;
-
- stmfx_pinctrl: pinctrl {
- compatible = "st,stmfx-0300-pinctrl";
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-ranges = <&stmfx_pinctrl 0 0 24>;
-
- joystick_pins: joystick {
- pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
- drive-push-pull;
- bias-pull-up;
- };
- };
- };
-};
-
-&rtc {
- status = "okay";
-};
-
-&sdio1 {
- status = "okay";
- vmmc-supply = <&mmc_vcard>;
- broken-cd;
- pinctrl-names = "default", "opendrain";
- pinctrl-0 = <&sdio_pins_a>;
- pinctrl-1 = <&sdio_pins_od_a>;
- bus-width = <4>;
-};
-
-&timers5 {
- /* Override timer5 to act as clockevent */
- compatible = "st,stm32-timer";
- interrupts = <50>;
- status = "okay";
- /delete-property/#address-cells;
- /delete-property/#size-cells;
- /delete-property/clock-names;
- /delete-node/pwm;
- /delete-node/timer@4;
-};
-
-&usart1 {
- pinctrl-0 = <&usart1_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_hs {
- dr_mode = "otg";
- phys = <&usbotg_hs_phy>;
- phy-names = "usb2-phy";
- pinctrl-0 = <&usbotg_hs_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32f4-pinctrl.dtsi b/arch/arm/dts/stm32f4-pinctrl.dtsi
deleted file mode 100644
index 0adc41b..0000000
--- a/arch/arm/dts/stm32f4-pinctrl.dtsi
+++ /dev/null
@@ -1,447 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
- *
- */
-
-#include <dt-bindings/pinctrl/stm32-pinfunc.h>
-#include <dt-bindings/mfd/stm32f4-rcc.h>
-
-/ {
- soc {
- pinctrl: pinctrl@40020000 {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x40020000 0x3000>;
- interrupt-parent = <&exti>;
- st,syscfg = <&syscfg 0x8>;
- pins-are-numbered;
-
- gpioa: gpio@40020000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x0 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
- st,bank-name = "GPIOA";
- };
-
- gpiob: gpio@40020400 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x400 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
- st,bank-name = "GPIOB";
- };
-
- gpioc: gpio@40020800 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x800 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
- st,bank-name = "GPIOC";
- };
-
- gpiod: gpio@40020c00 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0xc00 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
- st,bank-name = "GPIOD";
- };
-
- gpioe: gpio@40021000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
- st,bank-name = "GPIOE";
- };
-
- gpiof: gpio@40021400 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1400 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
- st,bank-name = "GPIOF";
- };
-
- gpiog: gpio@40021800 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1800 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
- st,bank-name = "GPIOG";
- };
-
- gpioh: gpio@40021c00 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1c00 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
- st,bank-name = "GPIOH";
- };
-
- gpioi: gpio@40022000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
- st,bank-name = "GPIOI";
- };
-
- gpioj: gpio@40022400 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2400 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
- st,bank-name = "GPIOJ";
- };
-
- gpiok: gpio@40022800 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2800 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
- st,bank-name = "GPIOK";
- };
-
- usart1_pins_a: usart1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
- bias-disable;
- };
- };
-
- usart3_pins_a: usart3-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
- bias-disable;
- };
- };
-
- usbotg_fs_pins_a: usbotg-fs-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
- <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
- <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- usbotg_fs_pins_b: usbotg-fs-1 {
- pins {
- pinmux = <STM32_PINMUX('B', 12, AF12)>, /* OTG_HS_ID */
- <STM32_PINMUX('B', 14, AF12)>, /* OTG_HS_DM */
- <STM32_PINMUX('B', 15, AF12)>; /* OTG_HS_DP */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- usbotg_hs_pins_a: usbotg-hs-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT*/
- <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
- <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
- <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
- <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
- <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
- <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
- <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
- <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
- <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
- <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
- <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- ethernet_mii: mii-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_MII_TXD0_ETH_RMII_TXD0 */
- <STM32_PINMUX('G', 14, AF11)>, /* ETH_MII_TXD1_ETH_RMII_TXD1 */
- <STM32_PINMUX('C', 2, AF11)>, /* ETH_MII_TXD2 */
- <STM32_PINMUX('B', 8, AF11)>, /* ETH_MII_TXD3 */
- <STM32_PINMUX('C', 3, AF11)>, /* ETH_MII_TX_CLK */
- <STM32_PINMUX('G', 11,AF11)>, /* ETH_MII_TX_EN_ETH_RMII_TX_EN */
- <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
- <STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
- <STM32_PINMUX('A', 1, AF11)>, /* ETH_MII_RX_CLK_ETH_RMII_REF_CLK */
- <STM32_PINMUX('A', 7, AF11)>, /* ETH_MII_RX_DV_ETH_RMII_CRS_DV */
- <STM32_PINMUX('C', 4, AF11)>, /* ETH_MII_RXD0_ETH_RMII_RXD0 */
- <STM32_PINMUX('C', 5, AF11)>, /* ETH_MII_RXD1_ETH_RMII_RXD1 */
- <STM32_PINMUX('H', 6, AF11)>, /* ETH_MII_RXD2 */
- <STM32_PINMUX('H', 7, AF11)>; /* ETH_MII_RXD3 */
- slew-rate = <2>;
- };
- };
-
- adc3_in8_pin: adc-200 {
- pins {
- pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
- };
- };
-
- pwm1_pins: pwm1-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */
- <STM32_PINMUX('B', 13, AF1)>, /* TIM1_CH1N */
- <STM32_PINMUX('B', 12, AF1)>; /* TIM1_BKIN */
- };
- };
-
- pwm3_pins: pwm3-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 4, AF2)>, /* TIM3_CH1 */
- <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */
- };
- };
-
- i2c1_pins: i2c1-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */
- <STM32_PINMUX('B', 6, AF4)>; /* I2C1_SCL */
- bias-disable;
- drive-open-drain;
- slew-rate = <3>;
- };
- };
-
- ltdc_pins_a: ltdc-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
- <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
- <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
- <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
- <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
- <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
- <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
- <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
- <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
- <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6*/
- <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
- <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
- <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
- <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
- <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
- <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
- <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
- <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
- <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
- <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3*/
- <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
- <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
- <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
- <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
- <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
- <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
- <STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */
- <STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */
- slew-rate = <2>;
- };
- };
-
- ltdc_pins_b: ltdc-1 {
- pins {
- pinmux = <STM32_PINMUX('C', 6, AF14)>,
- /* LCD_HSYNC */
- <STM32_PINMUX('A', 4, AF14)>,
- /* LCD_VSYNC */
- <STM32_PINMUX('G', 7, AF14)>,
- /* LCD_CLK */
- <STM32_PINMUX('C', 10, AF14)>,
- /* LCD_R2 */
- <STM32_PINMUX('B', 0, AF9)>,
- /* LCD_R3 */
- <STM32_PINMUX('A', 11, AF14)>,
- /* LCD_R4 */
- <STM32_PINMUX('A', 12, AF14)>,
- /* LCD_R5 */
- <STM32_PINMUX('B', 1, AF9)>,
- /* LCD_R6*/
- <STM32_PINMUX('G', 6, AF14)>,
- /* LCD_R7 */
- <STM32_PINMUX('A', 6, AF14)>,
- /* LCD_G2 */
- <STM32_PINMUX('G', 10, AF9)>,
- /* LCD_G3 */
- <STM32_PINMUX('B', 10, AF14)>,
- /* LCD_G4 */
- <STM32_PINMUX('D', 6, AF14)>,
- /* LCD_B2 */
- <STM32_PINMUX('G', 11, AF14)>,
- /* LCD_B3*/
- <STM32_PINMUX('B', 11, AF14)>,
- /* LCD_G5 */
- <STM32_PINMUX('C', 7, AF14)>,
- /* LCD_G6 */
- <STM32_PINMUX('D', 3, AF14)>,
- /* LCD_G7 */
- <STM32_PINMUX('G', 12, AF9)>,
- /* LCD_B4 */
- <STM32_PINMUX('A', 3, AF14)>,
- /* LCD_B5 */
- <STM32_PINMUX('B', 8, AF14)>,
- /* LCD_B6 */
- <STM32_PINMUX('B', 9, AF14)>,
- /* LCD_B7 */
- <STM32_PINMUX('F', 10, AF14)>;
- /* LCD_DE */
- slew-rate = <2>;
- };
- };
-
- spi5_pins: spi5-0 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 7, AF5)>,
- /* SPI5_CLK */
- <STM32_PINMUX('F', 9, AF5)>;
- /* SPI5_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('F', 8, AF5)>;
- /* SPI5_MISO */
- bias-disable;
- };
- };
-
- i2c3_pins: i2c3-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 9, AF4)>,
- /* I2C3_SDA */
- <STM32_PINMUX('A', 8, AF4)>;
- /* I2C3_SCL */
- bias-disable;
- drive-open-drain;
- slew-rate = <3>;
- };
- };
-
- dcmi_pins: dcmi-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */
- <STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */
- <STM32_PINMUX('A', 6, AF13)>, /* DCMI_PIXCLK */
- <STM32_PINMUX('C', 6, AF13)>, /* DCMI_D0 */
- <STM32_PINMUX('C', 7, AF13)>, /* DCMI_D1 */
- <STM32_PINMUX('C', 8, AF13)>, /* DCMI_D2 */
- <STM32_PINMUX('C', 9, AF13)>, /* DCMI_D3 */
- <STM32_PINMUX('C', 11, AF13)>, /*DCMI_D4 */
- <STM32_PINMUX('D', 3, AF13)>, /* DCMI_D5 */
- <STM32_PINMUX('B', 8, AF13)>, /* DCMI_D6 */
- <STM32_PINMUX('E', 6, AF13)>, /* DCMI_D7 */
- <STM32_PINMUX('C', 10, AF13)>, /* DCMI_D8 */
- <STM32_PINMUX('C', 12, AF13)>, /* DCMI_D9 */
- <STM32_PINMUX('D', 6, AF13)>, /* DCMI_D10 */
- <STM32_PINMUX('D', 2, AF13)>; /* DCMI_D11 */
- bias-disable;
- drive-push-pull;
- slew-rate = <3>;
- };
- };
-
- sdio_pins: sdio-pins-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
- <STM32_PINMUX('C', 12, AF12)>, /* SDIO_CK */
- <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- sdio_pins_od: sdio-pins-od-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
- <STM32_PINMUX('C', 12, AF12)>; /* SDIO_CK */
- drive-push-pull;
- slew-rate = <2>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
- drive-open-drain;
- slew-rate = <2>;
- };
- };
-
- can1_pins_a: can1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 9, AF9)>; /* CAN1_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 8, AF9)>; /* CAN1_RX */
- bias-pull-up;
- };
- };
-
- can2_pins_a: can2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
- bias-pull-up;
- };
- };
-
- can2_pins_b: can2-1 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 12, AF9)>; /* CAN2_RX */
- bias-pull-up;
- };
- };
- };
- };
-};
diff --git a/arch/arm/dts/stm32f429-disco.dts b/arch/arm/dts/stm32f429-disco.dts
deleted file mode 100644
index 30daabd..0000000
--- a/arch/arm/dts/stm32f429-disco.dts
+++ /dev/null
@@ -1,190 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
- */
-
-/dts-v1/;
-#include "stm32f429.dtsi"
-#include "stm32f429-pinctrl.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "STMicroelectronics STM32F429i-DISCO board";
- compatible = "st,stm32f429i-disco", "st,stm32f429";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@90000000 {
- device_type = "memory";
- reg = <0x90000000 0x800000>;
- };
-
- aliases {
- serial0 = &usart1;
- };
-
- leds {
- compatible = "gpio-leds";
- led-red {
- gpios = <&gpiog 14 0>;
- };
- led-green {
- gpios = <&gpiog 13 0>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- button-0 {
- label = "User";
- linux,code = <KEY_HOME>;
- gpios = <&gpioa 0 0>;
- };
- };
-
- /* This turns on vbus for otg for host mode (dwc2) */
- vcc5v_otg: vcc5v-otg-regulator {
- compatible = "regulator-fixed";
- gpio = <&gpioc 4 0>;
- regulator-name = "vcc5_host1";
- regulator-always-on;
- };
-};
-
-&clk_hse {
- clock-frequency = <8000000>;
-};
-
-&crc {
- status = "okay";
-};
-
-&i2c3 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_pins>;
- clock-frequency = <100000>;
- status = "okay";
-
- stmpe811@41 {
- compatible = "st,stmpe811";
- reg = <0x41>;
- interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
- interrupt-parent = <&gpioa>;
- /* 3.25 MHz ADC clock speed */
- st,adc-freq = <1>;
- /* 12-bit ADC */
- st,mod-12b = <1>;
- /* internal ADC reference */
- st,ref-sel = <0>;
- /* ADC converstion time: 80 clocks */
- st,sample-time = <4>;
-
- stmpe_touchscreen {
- compatible = "st,stmpe-ts";
- /* 8 sample average control */
- st,ave-ctrl = <3>;
- /* 7 length fractional part in z */
- st,fraction-z = <7>;
- /*
- * 50 mA typical 80 mA max touchscreen drivers
- * current limit value
- */
- st,i-drive = <1>;
- /* 1 ms panel driver settling time */
- st,settling = <3>;
- /* 5 ms touch detect interrupt delay */
- st,touch-det-delay = <5>;
- };
-
- stmpe_adc {
- compatible = "st,stmpe-adc";
- /* forbid to use ADC channels 3-0 (touch) */
- st,norequest-mask = <0x0F>;
- };
- };
-};
-
-<dc {
- status = "okay";
- pinctrl-0 = <<dc_pins_b>;
- pinctrl-names = "default";
-
- port {
- ltdc_out_rgb: endpoint {
- remote-endpoint = <&panel_in_rgb>;
- };
- };
-};
-
-&rtc {
- assigned-clocks = <&rcc 1 CLK_RTC>;
- assigned-clock-parents = <&rcc 1 CLK_LSI>;
- status = "okay";
-};
-
-&spi5 {
- status = "okay";
- pinctrl-0 = <&spi5_pins>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- cs-gpios = <&gpioc 1 GPIO_ACTIVE_LOW>, <&gpioc 2 GPIO_ACTIVE_LOW>;
-
- l3gd20: l3gd20@0 {
- compatible = "st,l3gd20-gyro";
- spi-max-frequency = <10000000>;
- st,drdy-int-pin = <2>;
- interrupt-parent = <&gpioa>;
- interrupts = <1 IRQ_TYPE_EDGE_RISING>,
- <2 IRQ_TYPE_EDGE_RISING>;
- reg = <0>;
- status = "okay";
- };
-
- display: display@1{
- /* Connect panel-ilitek-9341 to ltdc */
- compatible = "st,sf-tc240t-9370-t", "ilitek,ili9341";
- reg = <1>;
- spi-3wire;
- spi-max-frequency = <10000000>;
- dc-gpios = <&gpiod 13 0>;
- port {
- panel_in_rgb: endpoint {
- remote-endpoint = <<dc_out_rgb>;
- };
- };
- };
-};
-
-&timers5 {
- /* Override timer5 to act as clockevent */
- compatible = "st,stm32-timer";
- interrupts = <50>;
- status = "okay";
- /delete-property/#address-cells;
- /delete-property/#size-cells;
- /delete-property/clock-names;
- /delete-node/pwm;
- /delete-node/timer@4;
-};
-
-&usart1 {
- pinctrl-0 = <&usart1_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_hs {
- compatible = "st,stm32f4x9-fsotg";
- dr_mode = "host";
- pinctrl-0 = <&usbotg_fs_pins_b>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32f429-pinctrl.dtsi b/arch/arm/dts/stm32f429-pinctrl.dtsi
deleted file mode 100644
index 5be171e..0000000
--- a/arch/arm/dts/stm32f429-pinctrl.dtsi
+++ /dev/null
@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
- *
- */
-
-#include "stm32f4-pinctrl.dtsi"
-
-&pinctrl {
- compatible = "st,stm32f429-pinctrl";
-
- gpioa: gpio@40020000 {
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@40020400 {
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@40020800 {
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@40020c00 {
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@40021000 {
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@40021400 {
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@40021800 {
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@40021c00 {
- gpio-ranges = <&pinctrl 0 112 16>;
- };
-
- gpioi: gpio@40022000 {
- gpio-ranges = <&pinctrl 0 128 16>;
- };
-
- gpioj: gpio@40022400 {
- gpio-ranges = <&pinctrl 0 144 16>;
- };
-
- gpiok: gpio@40022800 {
- gpio-ranges = <&pinctrl 0 160 8>;
- };
-};
diff --git a/arch/arm/dts/stm32f429.dtsi b/arch/arm/dts/stm32f429.dtsi
deleted file mode 100644
index 8133ea1..0000000
--- a/arch/arm/dts/stm32f429.dtsi
+++ /dev/null
@@ -1,758 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
- *
- */
-
-#include "armv7-m.dtsi"
-#include <dt-bindings/clock/stm32fx-clock.h>
-#include <dt-bindings/mfd/stm32f4-rcc.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- clocks {
- clk_hse: clk-hse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- clk_lse: clk-lse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- clk_lsi: clk-lsi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32000>;
- };
-
- clk_i2s_ckin: i2s-ckin {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
- };
-
- soc {
- romem: efuse@1fff7800 {
- compatible = "st,stm32f4-otp";
- reg = <0x1fff7800 0x400>;
- #address-cells = <1>;
- #size-cells = <1>;
- ts_cal1: calib@22c {
- reg = <0x22c 0x2>;
- };
- ts_cal2: calib@22e {
- reg = <0x22e 0x2>;
- };
- };
-
- timers2: timers@40000000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000000 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@1 {
- compatible = "st,stm32-timer-trigger";
- reg = <1>;
- status = "disabled";
- };
- };
-
- timers3: timers@40000400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000400 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@2 {
- compatible = "st,stm32-timer-trigger";
- reg = <2>;
- status = "disabled";
- };
- };
-
- timers4: timers@40000800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000800 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@3 {
- compatible = "st,stm32-timer-trigger";
- reg = <3>;
- status = "disabled";
- };
- };
-
- timers5: timers@40000c00 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000C00 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@4 {
- compatible = "st,stm32-timer-trigger";
- reg = <4>;
- status = "disabled";
- };
- };
-
- timers6: timers@40001000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40001000 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
- clock-names = "int";
- status = "disabled";
-
- timer@5 {
- compatible = "st,stm32-timer-trigger";
- reg = <5>;
- status = "disabled";
- };
- };
-
- timers7: timers@40001400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40001400 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
- clock-names = "int";
- status = "disabled";
-
- timer@6 {
- compatible = "st,stm32-timer-trigger";
- reg = <6>;
- status = "disabled";
- };
- };
-
- timers12: timers@40001800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40001800 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@11 {
- compatible = "st,stm32-timer-trigger";
- reg = <11>;
- status = "disabled";
- };
- };
-
- timers13: timers@40001c00 {
- compatible = "st,stm32-timers";
- reg = <0x40001C00 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- timers14: timers@40002000 {
- compatible = "st,stm32-timers";
- reg = <0x40002000 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- rtc: rtc@40002800 {
- compatible = "st,stm32-rtc";
- reg = <0x40002800 0x400>;
- clocks = <&rcc 1 CLK_RTC>;
- assigned-clocks = <&rcc 1 CLK_RTC>;
- assigned-clock-parents = <&rcc 1 CLK_LSE>;
- interrupt-parent = <&exti>;
- interrupts = <17 1>;
- st,syscfg = <&pwrcfg 0x00 0x100>;
- status = "disabled";
- };
-
- iwdg: watchdog@40003000 {
- compatible = "st,stm32-iwdg";
- reg = <0x40003000 0x400>;
- clocks = <&clk_lsi>;
- clock-names = "lsi";
- status = "disabled";
- };
-
- spi2: spi@40003800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f4-spi";
- reg = <0x40003800 0x400>;
- interrupts = <36>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
- status = "disabled";
- };
-
- spi3: spi@40003c00 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f4-spi";
- reg = <0x40003c00 0x400>;
- interrupts = <51>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
- status = "disabled";
- };
-
- usart2: serial@40004400 {
- compatible = "st,stm32-uart";
- reg = <0x40004400 0x400>;
- interrupts = <38>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
- status = "disabled";
- };
-
- usart3: serial@40004800 {
- compatible = "st,stm32-uart";
- reg = <0x40004800 0x400>;
- interrupts = <39>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
- status = "disabled";
- dmas = <&dma1 1 4 0x400 0x0>,
- <&dma1 3 4 0x400 0x0>;
- dma-names = "rx", "tx";
- };
-
- usart4: serial@40004c00 {
- compatible = "st,stm32-uart";
- reg = <0x40004c00 0x400>;
- interrupts = <52>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
- status = "disabled";
- };
-
- usart5: serial@40005000 {
- compatible = "st,stm32-uart";
- reg = <0x40005000 0x400>;
- interrupts = <53>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
- status = "disabled";
- };
-
- i2c1: i2c@40005400 {
- compatible = "st,stm32f4-i2c";
- reg = <0x40005400 0x400>;
- interrupts = <31>,
- <32>;
- resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c3: i2c@40005c00 {
- compatible = "st,stm32f4-i2c";
- reg = <0x40005c00 0x400>;
- interrupts = <72>,
- <73>;
- resets = <&rcc STM32F4_APB1_RESET(I2C3)>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- can1: can@40006400 {
- compatible = "st,stm32f4-bxcan";
- reg = <0x40006400 0x200>;
- interrupts = <19>, <20>, <21>, <22>;
- interrupt-names = "tx", "rx0", "rx1", "sce";
- resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
- st,can-primary;
- st,gcan = <&gcan>;
- status = "disabled";
- };
-
- gcan: gcan@40006600 {
- compatible = "st,stm32f4-gcan", "syscon";
- reg = <0x40006600 0x200>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
- };
-
- can2: can@40006800 {
- compatible = "st,stm32f4-bxcan";
- reg = <0x40006800 0x200>;
- interrupts = <63>, <64>, <65>, <66>;
- interrupt-names = "tx", "rx0", "rx1", "sce";
- resets = <&rcc STM32F4_APB1_RESET(CAN2)>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>;
- st,can-secondary;
- st,gcan = <&gcan>;
- status = "disabled";
- };
-
- dac: dac@40007400 {
- compatible = "st,stm32f4-dac-core";
- reg = <0x40007400 0x400>;
- resets = <&rcc STM32F4_APB1_RESET(DAC)>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
- clock-names = "pclk";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- dac1: dac@1 {
- compatible = "st,stm32-dac";
- #io-channel-cells = <1>;
- reg = <1>;
- status = "disabled";
- };
-
- dac2: dac@2 {
- compatible = "st,stm32-dac";
- #io-channel-cells = <1>;
- reg = <2>;
- status = "disabled";
- };
- };
-
- usart7: serial@40007800 {
- compatible = "st,stm32-uart";
- reg = <0x40007800 0x400>;
- interrupts = <82>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
- status = "disabled";
- };
-
- usart8: serial@40007c00 {
- compatible = "st,stm32-uart";
- reg = <0x40007c00 0x400>;
- interrupts = <83>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
- status = "disabled";
- };
-
- timers1: timers@40010000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40010000 0x400>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@0 {
- compatible = "st,stm32-timer-trigger";
- reg = <0>;
- status = "disabled";
- };
- };
-
- timers8: timers@40010400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40010400 0x400>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@7 {
- compatible = "st,stm32-timer-trigger";
- reg = <7>;
- status = "disabled";
- };
- };
-
- usart1: serial@40011000 {
- compatible = "st,stm32-uart";
- reg = <0x40011000 0x400>;
- interrupts = <37>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
- status = "disabled";
- dmas = <&dma2 2 4 0x400 0x0>,
- <&dma2 7 4 0x400 0x0>;
- dma-names = "rx", "tx";
- };
-
- usart6: serial@40011400 {
- compatible = "st,stm32-uart";
- reg = <0x40011400 0x400>;
- interrupts = <71>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
- status = "disabled";
- };
-
- adc: adc@40012000 {
- compatible = "st,stm32f4-adc-core";
- reg = <0x40012000 0x400>;
- interrupts = <18>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
- clock-names = "adc";
- interrupt-controller;
- #interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- adc1: adc@0 {
- compatible = "st,stm32f4-adc";
- #io-channel-cells = <1>;
- reg = <0x0>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
- interrupt-parent = <&adc>;
- interrupts = <0>;
- dmas = <&dma2 0 0 0x400 0x0>;
- dma-names = "rx";
- status = "disabled";
- };
-
- adc2: adc@100 {
- compatible = "st,stm32f4-adc";
- #io-channel-cells = <1>;
- reg = <0x100>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
- interrupt-parent = <&adc>;
- interrupts = <1>;
- dmas = <&dma2 3 1 0x400 0x0>;
- dma-names = "rx";
- status = "disabled";
- };
-
- adc3: adc@200 {
- compatible = "st,stm32f4-adc";
- #io-channel-cells = <1>;
- reg = <0x200>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
- interrupt-parent = <&adc>;
- interrupts = <2>;
- dmas = <&dma2 1 2 0x400 0x0>;
- dma-names = "rx";
- status = "disabled";
- };
- };
-
- sdio: mmc@40012c00 {
- compatible = "arm,pl180", "arm,primecell";
- arm,primecell-periphid = <0x00880180>;
- reg = <0x40012c00 0x400>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
- clock-names = "apb_pclk";
- interrupts = <49>;
- max-frequency = <48000000>;
- status = "disabled";
- };
-
- spi1: spi@40013000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f4-spi";
- reg = <0x40013000 0x400>;
- interrupts = <35>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
- status = "disabled";
- };
-
- spi4: spi@40013400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f4-spi";
- reg = <0x40013400 0x400>;
- interrupts = <84>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
- status = "disabled";
- };
-
- syscfg: syscon@40013800 {
- compatible = "st,stm32-syscfg", "syscon";
- reg = <0x40013800 0x400>;
- };
-
- exti: interrupt-controller@40013c00 {
- compatible = "st,stm32-exti";
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x40013C00 0x400>;
- interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
- };
-
- timers9: timers@40014000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40014000 0x400>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@8 {
- compatible = "st,stm32-timer-trigger";
- reg = <8>;
- status = "disabled";
- };
- };
-
- timers10: timers@40014400 {
- compatible = "st,stm32-timers";
- reg = <0x40014400 0x400>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- timers11: timers@40014800 {
- compatible = "st,stm32-timers";
- reg = <0x40014800 0x400>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- spi5: spi@40015000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f4-spi";
- reg = <0x40015000 0x400>;
- interrupts = <85>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
- dmas = <&dma2 3 2 0x400 0x0>,
- <&dma2 4 2 0x400 0x0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- spi6: spi@40015400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f4-spi";
- reg = <0x40015400 0x400>;
- interrupts = <86>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
- status = "disabled";
- };
-
- pwrcfg: power-config@40007000 {
- compatible = "st,stm32-power-config", "syscon";
- reg = <0x40007000 0x400>;
- };
-
- ltdc: display-controller@40016800 {
- compatible = "st,stm32-ltdc";
- reg = <0x40016800 0x200>;
- interrupts = <88>, <89>;
- resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
- clocks = <&rcc 1 CLK_LCD>;
- clock-names = "lcd";
- status = "disabled";
- };
-
- crc: crc@40023000 {
- compatible = "st,stm32f4-crc";
- reg = <0x40023000 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
- status = "disabled";
- };
-
- rcc: rcc@40023800 {
- #reset-cells = <1>;
- #clock-cells = <2>;
- compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
- reg = <0x40023800 0x400>;
- clocks = <&clk_hse>, <&clk_i2s_ckin>;
- st,syscfg = <&pwrcfg>;
- assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
- assigned-clock-rates = <1000000>;
- };
-
- dma1: dma-controller@40026000 {
- compatible = "st,stm32-dma";
- reg = <0x40026000 0x400>;
- interrupts = <11>,
- <12>,
- <13>,
- <14>,
- <15>,
- <16>,
- <17>,
- <47>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
- #dma-cells = <4>;
- };
-
- dma2: dma-controller@40026400 {
- compatible = "st,stm32-dma";
- reg = <0x40026400 0x400>;
- interrupts = <56>,
- <57>,
- <58>,
- <59>,
- <60>,
- <68>,
- <69>,
- <70>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
- #dma-cells = <4>;
- st,mem2mem;
- };
-
- mac: ethernet@40028000 {
- compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
- reg = <0x40028000 0x8000>;
- reg-names = "stmmaceth";
- interrupts = <61>;
- interrupt-names = "macirq";
- clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
- <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
- <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
- st,syscon = <&syscfg 0x4>;
- snps,pbl = <8>;
- snps,mixed-burst;
- status = "disabled";
- };
-
- dma2d: dma2d@4002b000 {
- compatible = "st,stm32-dma2d";
- reg = <0x4002b000 0xc00>;
- interrupts = <90>;
- resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>;
- clock-names = "dma2d";
- status = "disabled";
- };
-
- usbotg_hs: usb@40040000 {
- compatible = "snps,dwc2";
- reg = <0x40040000 0x40000>;
- interrupts = <77>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
- clock-names = "otg";
- status = "disabled";
- };
-
- usbotg_fs: usb@50000000 {
- compatible = "st,stm32f4x9-fsotg";
- reg = <0x50000000 0x40000>;
- interrupts = <67>;
- clocks = <&rcc 0 39>;
- clock-names = "otg";
- status = "disabled";
- };
-
- dcmi: dcmi@50050000 {
- compatible = "st,stm32-dcmi";
- reg = <0x50050000 0x400>;
- interrupts = <78>;
- resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
- clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
- clock-names = "mclk";
- pinctrl-names = "default";
- pinctrl-0 = <&dcmi_pins>;
- dmas = <&dma2 1 1 0x414 0x3>;
- dma-names = "tx";
- status = "disabled";
- };
-
- rng: rng@50060800 {
- compatible = "st,stm32-rng";
- reg = <0x50060800 0x400>;
- clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
-
- };
- };
-};
-
-&systick {
- clocks = <&rcc 1 SYSTICK>;
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32f469-disco.dts b/arch/arm/dts/stm32f469-disco.dts
deleted file mode 100644
index c9acabf..0000000
--- a/arch/arm/dts/stm32f469-disco.dts
+++ /dev/null
@@ -1,213 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright 2016 - Lee Jones <lee.jones@linaro.org>
- *
- */
-
-/dts-v1/;
-#include "stm32f469.dtsi"
-#include "stm32f469-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "STMicroelectronics STM32F469i-DISCO board";
- compatible = "st,stm32f469i-disco", "st,stm32f469";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x00000000 0x1000000>;
- };
-
- aliases {
- serial0 = &usart3;
- };
-
- mmc_vcard: mmc_vcard {
- compatible = "regulator-fixed";
- regulator-name = "mmc_vcard";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vdd_dsi: vdd-dsi {
- compatible = "regulator-fixed";
- regulator-name = "vdd_dsi";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- soc {
- dma-ranges = <0xc0000000 0x0 0x10000000>;
- };
-
- leds {
- compatible = "gpio-leds";
- led-green {
- gpios = <&gpiog 6 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- };
- led-orange {
- gpios = <&gpiod 4 GPIO_ACTIVE_LOW>;
- };
- led-red {
- gpios = <&gpiod 5 GPIO_ACTIVE_LOW>;
- };
- led-blue {
- gpios = <&gpiok 3 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- button-0 {
- label = "User";
- linux,code = <KEY_WAKEUP>;
- gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
- };
- };
-
- /* This turns on vbus for otg for host mode (dwc2) */
- vcc5v_otg: vcc5v-otg-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpiob 2 GPIO_ACTIVE_HIGH>;
- regulator-name = "vcc5_host1";
- regulator-always-on;
- };
-};
-
-&rcc {
- compatible = "st,stm32f469-rcc", "st,stm32f42xx-rcc", "st,stm32-rcc";
-};
-
-&clk_hse {
- clock-frequency = <8000000>;
-};
-
-&dma2d {
- status = "okay";
-};
-
-&dsi {
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- dsi_in: endpoint {
- remote-endpoint = <<dc_out_dsi>;
- };
- };
-
- port@1 {
- reg = <1>;
- dsi_out: endpoint {
- remote-endpoint = <&dsi_panel_in>;
- };
- };
- };
-
- panel@0 {
- compatible = "orisetech,otm8009a";
- reg = <0>; /* dsi virtual channel (0..3) */
- reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>;
- power-supply = <&vdd_dsi>;
- status = "okay";
-
- port {
- dsi_panel_in: endpoint {
- remote-endpoint = <&dsi_out>;
- };
- };
- };
-};
-
-<dc {
- status = "okay";
-
- port {
- ltdc_out_dsi: endpoint {
- remote-endpoint = <&dsi_in>;
- };
- };
-};
-
-&rtc {
- status = "okay";
-};
-
-&timers1 {
- status = "okay";
-
- pwm {
- pinctrl-0 = <&pwm1_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- timer@0 {
- status = "okay";
- };
-};
-
-&timers3 {
- status = "okay";
-
- pwm {
- pinctrl-0 = <&pwm3_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- timer@2 {
- status = "okay";
- };
-};
-
-&sdio {
- status = "okay";
- vmmc-supply = <&mmc_vcard>;
- cd-gpios = <&gpiog 2 GPIO_ACTIVE_LOW>;
- broken-cd;
- pinctrl-names = "default", "opendrain";
- pinctrl-0 = <&sdio_pins>;
- pinctrl-1 = <&sdio_pins_od>;
- bus-width = <4>;
-};
-
-&timers5 {
- /* Override timer5 to act as clockevent */
- compatible = "st,stm32-timer";
- interrupts = <50>;
- status = "okay";
- /delete-property/#address-cells;
- /delete-property/#size-cells;
- /delete-property/clock-names;
- /delete-node/pwm;
- /delete-node/timer@4;
-};
-
-&usart3 {
- pinctrl-0 = <&usart3_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_fs {
- dr_mode = "host";
- pinctrl-0 = <&usbotg_fs_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32f469-pinctrl.dtsi b/arch/arm/dts/stm32f469-pinctrl.dtsi
deleted file mode 100644
index 0610407..0000000
--- a/arch/arm/dts/stm32f469-pinctrl.dtsi
+++ /dev/null
@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
- */
-
-#include "stm32f4-pinctrl.dtsi"
-
-&pinctrl {
- compatible = "st,stm32f469-pinctrl";
-
- gpioa: gpio@40020000 {
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@40020400 {
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@40020800 {
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@40020c00 {
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@40021000 {
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@40021400 {
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@40021800 {
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@40021c00 {
- gpio-ranges = <&pinctrl 0 112 16>;
- };
-
- gpioi: gpio@40022000 {
- gpio-ranges = <&pinctrl 0 128 16>;
- };
-
- gpioj: gpio@40022400 {
- gpio-ranges = <&pinctrl 0 144 6>,
- <&pinctrl 12 156 4>;
- };
-
- gpiok: gpio@40022800 {
- gpio-ranges = <&pinctrl 3 163 5>;
- };
-};
diff --git a/arch/arm/dts/stm32f469.dtsi b/arch/arm/dts/stm32f469.dtsi
deleted file mode 100644
index 5f6a797..0000000
--- a/arch/arm/dts/stm32f469.dtsi
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/* Copyright (C) STMicroelectronics 2017 - All Rights Reserved */
-
-#include "stm32f429.dtsi"
-
-/ {
- soc {
- dsi: dsi@40016c00 {
- compatible = "st,stm32-dsi";
- reg = <0x40016c00 0x800>;
- resets = <&rcc STM32F4_APB2_RESET(DSI)>;
- reset-names = "apb";
- clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
- clock-names = "pclk", "ref";
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/dts/stm32f7-pinctrl.dtsi b/arch/arm/dts/stm32f7-pinctrl.dtsi
deleted file mode 100644
index d3706ee..0000000
--- a/arch/arm/dts/stm32f7-pinctrl.dtsi
+++ /dev/null
@@ -1,415 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-#include <dt-bindings/pinctrl/stm32-pinfunc.h>
-#include <dt-bindings/mfd/stm32f7-rcc.h>
-
-/ {
- soc {
- pinctrl: pinctrl@40020000 {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x40020000 0x3000>;
- interrupt-parent = <&exti>;
- st,syscfg = <&syscfg 0x8>;
- pins-are-numbered;
-
- gpioa: gpio@40020000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x0 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
- st,bank-name = "GPIOA";
- };
-
- gpiob: gpio@40020400 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x400 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
- st,bank-name = "GPIOB";
- };
-
- gpioc: gpio@40020800 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x800 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
- st,bank-name = "GPIOC";
- };
-
- gpiod: gpio@40020c00 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0xc00 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
- st,bank-name = "GPIOD";
- };
-
- gpioe: gpio@40021000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
- st,bank-name = "GPIOE";
- };
-
- gpiof: gpio@40021400 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1400 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
- st,bank-name = "GPIOF";
- };
-
- gpiog: gpio@40021800 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1800 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
- st,bank-name = "GPIOG";
- };
-
- gpioh: gpio@40021c00 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1c00 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
- st,bank-name = "GPIOH";
- };
-
- gpioi: gpio@40022000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
- st,bank-name = "GPIOI";
- };
-
- gpioj: gpio@40022400 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2400 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
- st,bank-name = "GPIOJ";
- };
-
- gpiok: gpio@40022800 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2800 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
- st,bank-name = "GPIOK";
- };
-
- cec_pins_a: cec-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
- slew-rate = <0>;
- drive-open-drain;
- bias-disable;
- };
- };
-
- usart1_pins_a: usart1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
- bias-disable;
- };
- };
-
- usart1_pins_b: usart1-1 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */
- bias-disable;
- };
- };
-
- i2c1_pins_b: i2c1-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
- <STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c3_pins_a: i2c3-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 8, AF4)>, /* I2C3_SDA */
- <STM32_PINMUX('H', 7, AF4)>; /* I2C3_SCL */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- usbotg_hs_pins_a: usbotg-hs-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
- <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
- <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
- <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
- <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
- <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
- <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
- <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
- <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
- <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
- <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
- <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- usbotg_hs_pins_b: usbotg-hs-1 {
- pins {
- pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
- <STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */
- <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
- <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
- <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
- <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
- <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
- <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
- <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
- <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
- <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
- <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- usbotg_fs_pins_a: usbotg-fs-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
- <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
- <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- sdio_pins_a: sdio-pins-a-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
- <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1 CLK */
- <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- sdio_pins_od_a: sdio-pins-od-a-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
- <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1 CLK */
- drive-push-pull;
- slew-rate = <2>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
- drive-open-drain;
- slew-rate = <2>;
- };
- };
-
- sdio_pins_b: sdio-pins-b-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
- <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
- <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
- <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
- <STM32_PINMUX('D', 6, AF11)>, /* SDMMC2 CLK */
- <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- sdio_pins_od_b: sdio-pins-od-b-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
- <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
- <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
- <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
- <STM32_PINMUX('D', 6, AF11)>; /* SDMMC2 CLK */
- drive-push-pull;
- slew-rate = <2>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
- drive-open-drain;
- slew-rate = <2>;
- };
- };
-
- can1_pins_a: can1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */
- bias-pull-up;
- };
- };
-
- can1_pins_b: can1-1 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 9, AF9)>; /* CAN1_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 8, AF9)>; /* CAN1_RX */
- bias-pull-up;
- };
- };
-
- can1_pins_c: can1-2 {
- pins1 {
- pinmux = <STM32_PINMUX('D', 1, AF9)>; /* CAN1_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */
- bias-pull-up;
-
- };
- };
-
- can1_pins_d: can1-3 {
- pins1 {
- pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('H', 14, AF9)>; /* CAN1_RX */
- bias-pull-up;
-
- };
- };
-
- can2_pins_a: can2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 6, AF9)>; /* CAN2_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
- bias-pull-up;
- };
- };
-
- can2_pins_b: can2-1 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 12, AF9)>; /* CAN2_RX */
- bias-pull-up;
- };
- };
-
- can3_pins_a: can3-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 15, AF11)>; /* CAN3_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 8, AF11)>; /* CAN3_RX */
- bias-pull-up;
- };
- };
-
- can3_pins_b: can3-1 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 4, AF11)>; /* CAN3_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 3, AF11)>; /* CAN3_RX */
- bias-pull-up;
- };
- };
-
- ltdc_pins_a: ltdc-0 {
- pins {
- pinmux = <STM32_PINMUX('E', 4, AF14)>, /* LCD_B0 */
- <STM32_PINMUX('G',12, AF9)>, /* LCD_B4 */
- <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
- <STM32_PINMUX('I',10, AF14)>, /* LCD_HSYNC */
- <STM32_PINMUX('I',14, AF14)>, /* LCD_CLK */
- <STM32_PINMUX('I',15, AF14)>, /* LCD_R0 */
- <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
- <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
- <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
- <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
- <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
- <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
- <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
- <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
- <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
- <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
- <STM32_PINMUX('J',10, AF14)>, /* LCD_G3 */
- <STM32_PINMUX('J',11, AF14)>, /* LCD_G4 */
- <STM32_PINMUX('J',13, AF14)>, /* LCD_B1 */
- <STM32_PINMUX('J',14, AF14)>, /* LCD_B2 */
- <STM32_PINMUX('J',15, AF14)>, /* LCD_B3 */
- <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
- <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
- <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
- <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
- <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
- <STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */
- <STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */
- slew-rate = <2>;
- };
- };
- };
- };
-};
diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi
index 38d797e..8ea4ea6 100644
--- a/arch/arm/dts/stm32f746-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi
@@ -24,11 +24,6 @@
};
};
-<dc {
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
- bootph-all;
-};
-
&fmc {
/* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
bank1: bank@0 {
@@ -53,8 +48,14 @@
};
};
+<dc {
+ bootph-all;
+
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
+};
+
&panel_rgb {
- compatible = "simple-panel";
+ compatible = "rocktech,rk043fn48h", "simple-panel";
display-timings {
timing@0 {
diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts
deleted file mode 100644
index 4312751..0000000
--- a/arch/arm/dts/stm32f746-disco.dts
+++ /dev/null
@@ -1,169 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright 2017 - Vikas MANOCHA <vikas.manocha@st.com>
- *
- */
-
-/dts-v1/;
-#include "stm32f746.dtsi"
-#include "stm32f746-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
- model = "STMicroelectronics STM32F746-DISCO board";
- compatible = "st,stm32f746-disco", "st,stm32f746";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@c0000000 {
- device_type = "memory";
- reg = <0xC0000000 0x800000>;
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- linux,cma {
- compatible = "shared-dma-pool";
- no-map;
- size = <0x80000>;
- linux,dma-default;
- };
- };
-
- aliases {
- serial0 = &usart1;
- };
-
- usbotg_hs_phy: usb-phy {
- #phy-cells = <0>;
- compatible = "usb-nop-xceiv";
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
- clock-names = "main_clk";
- };
-
- /* This turns on vbus for otg fs for host mode (dwc2) */
- vcc5v_otg_fs: vcc5v-otg-fs-regulator {
- compatible = "regulator-fixed";
- gpio = <&gpiod 5 0>;
- regulator-name = "vcc5_host1";
- regulator-always-on;
- };
-
- vcc_3v3: vcc-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- backlight: backlight {
- compatible = "gpio-backlight";
- gpios = <&gpiok 3 GPIO_ACTIVE_HIGH>;
- status = "okay";
- };
-
- panel_rgb: panel-rgb {
- compatible = "rocktech,rk043fn48h";
- power-supply = <&vcc_3v3>;
- backlight = <&backlight>;
- enable-gpios = <&gpioi 12 GPIO_ACTIVE_HIGH>;
- status = "okay";
- port {
- panel_in_rgb: endpoint {
- remote-endpoint = <<dc_out_rgb>;
- };
- };
- };
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins_b>;
- pinctrl-names = "default";
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-};
-
-&i2c3 {
- pinctrl-0 = <&i2c3_pins_a>;
- pinctrl-names = "default";
- clock-frequency = <400000>;
- status = "okay";
-
- touchscreen@38 {
- compatible = "edt,edt-ft5306";
- reg = <0x38>;
- interrupt-parent = <&gpioi>;
- interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
- touchscreen-size-x = <480>;
- touchscreen-size-y = <272>;
- };
-};
-
-<dc {
- pinctrl-0 = <<dc_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-
- port {
- ltdc_out_rgb: endpoint {
- remote-endpoint = <&panel_in_rgb>;
- };
- };
-};
-
-&sdio1 {
- status = "okay";
- vmmc-supply = <&vcc_3v3>;
- cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default", "opendrain";
- pinctrl-0 = <&sdio_pins_a>;
- pinctrl-1 = <&sdio_pins_od_a>;
- bus-width = <4>;
-};
-
-&timers5 {
- /* Override timer5 to act as clockevent */
- compatible = "st,stm32-timer";
- interrupts = <50>;
- status = "okay";
- /delete-property/#address-cells;
- /delete-property/#size-cells;
- /delete-property/clock-names;
- /delete-node/pwm;
- /delete-node/timer@4;
-};
-
-&usart1 {
- pinctrl-0 = <&usart1_pins_b>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_fs {
- dr_mode = "host";
- pinctrl-0 = <&usbotg_fs_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_hs {
- dr_mode = "host";
- phys = <&usbotg_hs_phy>;
- phy-names = "usb2-phy";
- pinctrl-0 = <&usbotg_hs_pins_b>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32f746-pinctrl.dtsi b/arch/arm/dts/stm32f746-pinctrl.dtsi
deleted file mode 100644
index fcfd2ac..0000000
--- a/arch/arm/dts/stm32f746-pinctrl.dtsi
+++ /dev/null
@@ -1,11 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-#include "stm32f7-pinctrl.dtsi"
-
-&pinctrl{
- compatible = "st,stm32f746-pinctrl";
-};
diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
deleted file mode 100644
index 79dad31..0000000
--- a/arch/arm/dts/stm32f746.dtsi
+++ /dev/null
@@ -1,613 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
- *
- */
-
-#include "armv7-m.dtsi"
-#include <dt-bindings/clock/stm32fx-clock.h>
-#include <dt-bindings/mfd/stm32f7-rcc.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- clocks {
- clk_hse: clk-hse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- clk-lse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- clk-lsi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32000>;
- };
-
- clk_i2s_ckin: clk-i2s-ckin {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <48000000>;
- };
- };
-
- soc {
- timers2: timers@40000000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000000 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@1 {
- compatible = "st,stm32-timer-trigger";
- reg = <1>;
- status = "disabled";
- };
- };
-
- timers3: timers@40000400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000400 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@2 {
- compatible = "st,stm32-timer-trigger";
- reg = <2>;
- status = "disabled";
- };
- };
-
- timers4: timers@40000800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000800 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@3 {
- compatible = "st,stm32-timer-trigger";
- reg = <3>;
- status = "disabled";
- };
- };
-
- timers5: timers@40000c00 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000C00 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@4 {
- compatible = "st,stm32-timer-trigger";
- reg = <4>;
- status = "disabled";
- };
- };
-
- timers6: timers@40001000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40001000 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
- clock-names = "int";
- status = "disabled";
-
- timer@5 {
- compatible = "st,stm32-timer-trigger";
- reg = <5>;
- status = "disabled";
- };
- };
-
- timers7: timers@40001400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40001400 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
- clock-names = "int";
- status = "disabled";
-
- timer@6 {
- compatible = "st,stm32-timer-trigger";
- reg = <6>;
- status = "disabled";
- };
- };
-
- timers12: timers@40001800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40001800 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@11 {
- compatible = "st,stm32-timer-trigger";
- reg = <11>;
- status = "disabled";
- };
- };
-
- timers13: timers@40001c00 {
- compatible = "st,stm32-timers";
- reg = <0x40001C00 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- timers14: timers@40002000 {
- compatible = "st,stm32-timers";
- reg = <0x40002000 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- rtc: rtc@40002800 {
- compatible = "st,stm32-rtc";
- reg = <0x40002800 0x400>;
- clocks = <&rcc 1 CLK_RTC>;
- assigned-clocks = <&rcc 1 CLK_RTC>;
- assigned-clock-parents = <&rcc 1 CLK_LSE>;
- interrupt-parent = <&exti>;
- interrupts = <17 1>;
- st,syscfg = <&pwrcfg 0x00 0x100>;
- status = "disabled";
- };
-
- can3: can@40003400 {
- compatible = "st,stm32f4-bxcan";
- reg = <0x40003400 0x200>;
- interrupts = <104>, <105>, <106>, <107>;
- interrupt-names = "tx", "rx0", "rx1", "sce";
- resets = <&rcc STM32F7_APB1_RESET(CAN3)>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
- st,gcan = <&gcan3>;
- status = "disabled";
- };
-
- gcan3: gcan@40003600 {
- compatible = "st,stm32f4-gcan", "syscon";
- reg = <0x40003600 0x200>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
- };
-
- usart2: serial@40004400 {
- compatible = "st,stm32f7-uart";
- reg = <0x40004400 0x400>;
- interrupts = <38>;
- clocks = <&rcc 1 CLK_USART2>;
- status = "disabled";
- };
-
- usart3: serial@40004800 {
- compatible = "st,stm32f7-uart";
- reg = <0x40004800 0x400>;
- interrupts = <39>;
- clocks = <&rcc 1 CLK_USART3>;
- status = "disabled";
- };
-
- usart4: serial@40004c00 {
- compatible = "st,stm32f7-uart";
- reg = <0x40004c00 0x400>;
- interrupts = <52>;
- clocks = <&rcc 1 CLK_UART4>;
- status = "disabled";
- };
-
- usart5: serial@40005000 {
- compatible = "st,stm32f7-uart";
- reg = <0x40005000 0x400>;
- interrupts = <53>;
- clocks = <&rcc 1 CLK_UART5>;
- status = "disabled";
- };
-
- i2c1: i2c@40005400 {
- compatible = "st,stm32f7-i2c";
- reg = <0x40005400 0x400>;
- interrupts = <31>,
- <32>;
- resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
- clocks = <&rcc 1 CLK_I2C1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@40005800 {
- compatible = "st,stm32f7-i2c";
- reg = <0x40005800 0x400>;
- interrupts = <33>,
- <34>;
- resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
- clocks = <&rcc 1 CLK_I2C2>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c3: i2c@40005c00 {
- compatible = "st,stm32f7-i2c";
- reg = <0x40005c00 0x400>;
- interrupts = <72>,
- <73>;
- resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
- clocks = <&rcc 1 CLK_I2C3>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c4: i2c@40006000 {
- compatible = "st,stm32f7-i2c";
- reg = <0x40006000 0x400>;
- interrupts = <95>,
- <96>;
- resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
- clocks = <&rcc 1 CLK_I2C4>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- can1: can@40006400 {
- compatible = "st,stm32f4-bxcan";
- reg = <0x40006400 0x200>;
- interrupts = <19>, <20>, <21>, <22>;
- interrupt-names = "tx", "rx0", "rx1", "sce";
- resets = <&rcc STM32F7_APB1_RESET(CAN1)>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
- st,can-primary;
- st,gcan = <&gcan1>;
- status = "disabled";
- };
-
- gcan1: gcan@40006600 {
- compatible = "st,stm32f4-gcan", "syscon";
- reg = <0x40006600 0x200>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
- };
-
- can2: can@40006800 {
- compatible = "st,stm32f4-bxcan";
- reg = <0x40006800 0x200>;
- interrupts = <63>, <64>, <65>, <66>;
- interrupt-names = "tx", "rx0", "rx1", "sce";
- resets = <&rcc STM32F7_APB1_RESET(CAN2)>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>;
- st,can-secondary;
- st,gcan = <&gcan1>;
- status = "disabled";
- };
-
- cec: cec@40006c00 {
- compatible = "st,stm32-cec";
- reg = <0x40006C00 0x400>;
- interrupts = <94>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
- clock-names = "cec", "hdmi-cec";
- status = "disabled";
- };
-
- usart7: serial@40007800 {
- compatible = "st,stm32f7-uart";
- reg = <0x40007800 0x400>;
- interrupts = <82>;
- clocks = <&rcc 1 CLK_UART7>;
- status = "disabled";
- };
-
- usart8: serial@40007c00 {
- compatible = "st,stm32f7-uart";
- reg = <0x40007c00 0x400>;
- interrupts = <83>;
- clocks = <&rcc 1 CLK_UART8>;
- status = "disabled";
- };
-
- timers1: timers@40010000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40010000 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@0 {
- compatible = "st,stm32-timer-trigger";
- reg = <0>;
- status = "disabled";
- };
- };
-
- timers8: timers@40010400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40010400 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@7 {
- compatible = "st,stm32-timer-trigger";
- reg = <7>;
- status = "disabled";
- };
- };
-
- usart1: serial@40011000 {
- compatible = "st,stm32f7-uart";
- reg = <0x40011000 0x400>;
- interrupts = <37>;
- clocks = <&rcc 1 CLK_USART1>;
- status = "disabled";
- };
-
- usart6: serial@40011400 {
- compatible = "st,stm32f7-uart";
- reg = <0x40011400 0x400>;
- interrupts = <71>;
- clocks = <&rcc 1 CLK_USART6>;
- status = "disabled";
- };
-
- sdio2: mmc@40011c00 {
- compatible = "arm,pl180", "arm,primecell";
- arm,primecell-periphid = <0x00880180>;
- reg = <0x40011c00 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
- clock-names = "apb_pclk";
- interrupts = <103>;
- max-frequency = <48000000>;
- status = "disabled";
- };
-
- sdio1: mmc@40012c00 {
- compatible = "arm,pl180", "arm,primecell";
- arm,primecell-periphid = <0x00880180>;
- reg = <0x40012c00 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
- clock-names = "apb_pclk";
- interrupts = <49>;
- max-frequency = <48000000>;
- status = "disabled";
- };
-
- syscfg: syscon@40013800 {
- compatible = "st,stm32-syscfg", "syscon";
- reg = <0x40013800 0x400>;
- };
-
- exti: interrupt-controller@40013c00 {
- compatible = "st,stm32-exti";
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x40013C00 0x400>;
- interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
- };
-
- timers9: timers@40014000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40014000 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@8 {
- compatible = "st,stm32-timer-trigger";
- reg = <8>;
- status = "disabled";
- };
- };
-
- timers10: timers@40014400 {
- compatible = "st,stm32-timers";
- reg = <0x40014400 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- timers11: timers@40014800 {
- compatible = "st,stm32-timers";
- reg = <0x40014800 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- ltdc: display-controller@40016800 {
- compatible = "st,stm32-ltdc";
- reg = <0x40016800 0x200>;
- interrupts = <88>, <89>;
- resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
- clocks = <&rcc 1 CLK_LCD>;
- clock-names = "lcd";
- status = "disabled";
- };
-
- pwrcfg: power-config@40007000 {
- compatible = "st,stm32-power-config", "syscon";
- reg = <0x40007000 0x400>;
- };
-
- crc: crc@40023000 {
- compatible = "st,stm32f7-crc";
- reg = <0x40023000 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>;
- status = "disabled";
- };
-
- rcc: rcc@40023800 {
- #reset-cells = <1>;
- #clock-cells = <2>;
- compatible = "st,stm32f746-rcc", "st,stm32-rcc";
- reg = <0x40023800 0x400>;
- clocks = <&clk_hse>, <&clk_i2s_ckin>;
- st,syscfg = <&pwrcfg>;
- assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
- assigned-clock-rates = <1000000>;
- };
-
- dma1: dma-controller@40026000 {
- compatible = "st,stm32-dma";
- reg = <0x40026000 0x400>;
- interrupts = <11>,
- <12>,
- <13>,
- <14>,
- <15>,
- <16>,
- <17>,
- <47>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
- #dma-cells = <4>;
- status = "disabled";
- };
-
- dma2: dma-controller@40026400 {
- compatible = "st,stm32-dma";
- reg = <0x40026400 0x400>;
- interrupts = <56>,
- <57>,
- <58>,
- <59>,
- <60>,
- <68>,
- <69>,
- <70>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
- #dma-cells = <4>;
- st,mem2mem;
- status = "disabled";
- };
-
- usbotg_hs: usb@40040000 {
- compatible = "st,stm32f7-hsotg";
- reg = <0x40040000 0x40000>;
- interrupts = <77>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
- clock-names = "otg";
- g-rx-fifo-size = <256>;
- g-np-tx-fifo-size = <32>;
- g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- usbotg_fs: usb@50000000 {
- compatible = "st,stm32f4x9-fsotg";
- reg = <0x50000000 0x40000>;
- interrupts = <67>;
- clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
- clock-names = "otg";
- status = "disabled";
- };
- };
-};
-
-&systick {
- clocks = <&rcc 1 0>;
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32f769-disco-u-boot.dtsi b/arch/arm/dts/stm32f769-disco-u-boot.dtsi
index 7c99a6e..8413264 100644
--- a/arch/arm/dts/stm32f769-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f769-disco-u-boot.dtsi
@@ -23,57 +23,13 @@
spi0 = &qspi;
};
- panel: panel {
- compatible = "orisetech,otm8009a";
- reset-gpios = <&gpioj 15 1>;
- status = "okay";
-
- port {
- panel_in: endpoint {
- remote-endpoint = <&dsi_out>;
- };
- };
- };
-
- soc {
- dsi: dsi@40016c00 {
- compatible = "st,stm32-dsi";
- reg = <0x40016c00 0x800>;
- resets = <&rcc STM32F7_APB2_RESET(DSI)>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(DSI)>,
- <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>,
- <&clk_hse>;
- clock-names = "pclk", "px_clk", "ref";
- bootph-all;
- status = "okay";
-
- ports {
- port@0 {
- dsi_out: endpoint {
- remote-endpoint = <&panel_in>;
- };
- };
- port@1 {
- dsi_in: endpoint {
- remote-endpoint = <&dp_out>;
- };
- };
- };
- };
- };
};
-<dc {
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
- bootph-all;
-
- ports {
- port@0 {
- dp_out: endpoint {
- remote-endpoint = <&dsi_in>;
- };
- };
- };
+&dsi {
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(DSI)>,
+ <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>,
+ <&clk_hse>;
+ clock-names = "pclk", "px_clk", "ref";
};
&fmc {
@@ -100,6 +56,12 @@
};
};
+<dc {
+ bootph-all;
+
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
+};
+
&pinctrl {
ethernet_mii: mii@0 {
pins {
diff --git a/arch/arm/dts/stm32f769-disco.dts b/arch/arm/dts/stm32f769-disco.dts
deleted file mode 100644
index d63cd2b..0000000
--- a/arch/arm/dts/stm32f769-disco.dts
+++ /dev/null
@@ -1,133 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright 2017 - Vikas MANOCHA <vikas.manocha@st.com>
- *
- */
-
-/dts-v1/;
-#include "stm32f746.dtsi"
-#include "stm32f769-pinctrl.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "STMicroelectronics STM32F769-DISCO board";
- compatible = "st,stm32f769-disco", "st,stm32f769";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@c0000000 {
- device_type = "memory";
- reg = <0xC0000000 0x1000000>;
- };
-
- aliases {
- serial0 = &usart1;
- };
-
- leds {
- compatible = "gpio-leds";
- led-green {
- gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- led-red {
- gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- button-0 {
- label = "User";
- linux,code = <KEY_HOME>;
- gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
- };
- };
-
- usbotg_hs_phy: usb-phy {
- #phy-cells = <0>;
- compatible = "usb-nop-xceiv";
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
- clock-names = "main_clk";
- };
-
- mmc_vcard: mmc_vcard {
- compatible = "regulator-fixed";
- regulator-name = "mmc_vcard";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-&rcc {
- compatible = "st,stm32f769-rcc", "st,stm32f746-rcc", "st,stm32-rcc";
-};
-
-&cec {
- pinctrl-0 = <&cec_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins_b>;
- pinctrl-names = "default";
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-};
-
-<dc {
- status = "okay";
-};
-
-&rtc {
- status = "okay";
-};
-
-&sdio2 {
- status = "okay";
- vmmc-supply = <&mmc_vcard>;
- cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>;
- broken-cd;
- pinctrl-names = "default", "opendrain";
- pinctrl-0 = <&sdio_pins_b>;
- pinctrl-1 = <&sdio_pins_od_b>;
- bus-width = <4>;
-};
-
-&timers5 {
- /* Override timer5 to act as clockevent */
- compatible = "st,stm32-timer";
- interrupts = <50>;
- status = "okay";
- /delete-property/#address-cells;
- /delete-property/#size-cells;
- /delete-property/clock-names;
- /delete-node/pwm;
- /delete-node/timer@4;
-};
-
-&usart1 {
- pinctrl-0 = <&usart1_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_hs {
- dr_mode = "otg";
- phys = <&usbotg_hs_phy>;
- phy-names = "usb2-phy";
- pinctrl-0 = <&usbotg_hs_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32f769-pinctrl.dtsi b/arch/arm/dts/stm32f769-pinctrl.dtsi
deleted file mode 100644
index 31005dd..0000000
--- a/arch/arm/dts/stm32f769-pinctrl.dtsi
+++ /dev/null
@@ -1,11 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-#include "stm32f7-pinctrl.dtsi"
-
-&pinctrl{
- compatible = "st,stm32f769-pinctrl";
-};
diff --git a/arch/arm/dts/stm32h7-pinctrl.dtsi b/arch/arm/dts/stm32h7-pinctrl.dtsi
deleted file mode 100644
index aefa324..0000000
--- a/arch/arm/dts/stm32h7-pinctrl.dtsi
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <dt-bindings/pinctrl/stm32-pinfunc.h>
-
-&pinctrl {
-
- i2c1_pins_a: i2c1-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */
- <STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- ethernet_rmii: rmii-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 11, AF11)>,
- <STM32_PINMUX('G', 13, AF11)>,
- <STM32_PINMUX('G', 12, AF11)>,
- <STM32_PINMUX('C', 4, AF11)>,
- <STM32_PINMUX('C', 5, AF11)>,
- <STM32_PINMUX('A', 7, AF11)>,
- <STM32_PINMUX('C', 1, AF11)>,
- <STM32_PINMUX('A', 2, AF11)>,
- <STM32_PINMUX('A', 1, AF11)>;
- slew-rate = <2>;
- };
- };
-
- sdmmc1_b4_pins_a: sdmmc1-b4-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
- <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
- <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
- slew-rate = <3>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
- <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
- slew-rate = <3>;
- drive-push-pull;
- bias-disable;
- };
- pins2{
- pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
- slew-rate = <3>;
- drive-open-drain;
- bias-disable;
- };
- };
-
- sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
- <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
- <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
- };
- };
-
- sdmmc1_dir_pins_a: sdmmc1-dir-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 6, AF8)>, /* SDMMC1_D0DIR */
- <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
- <STM32_PINMUX('B', 9, AF7)>; /* SDMMC1_CDIR */
- slew-rate = <3>;
- drive-push-pull;
- bias-pull-up;
- };
- pins2{
- pinmux = <STM32_PINMUX('B', 8, AF7)>; /* SDMMC1_CKIN */
- bias-pull-up;
- };
- };
-
- sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC1_D0DIR */
- <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
- <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
- <STM32_PINMUX('B', 8, ANALOG)>; /* SDMMC1_CKIN */
- };
- };
-
- sdmmc2_b4_pins_a: sdmmc2-b4-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC1_D0 */
- <STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */
- <STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */
- <STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */
- <STM32_PINMUX('D', 6, AF11)>, /* SDMMC1_CK */
- <STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */
- slew-rate = <3>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
- <STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */
- <STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */
- <STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */
- <STM32_PINMUX('D', 6, AF11)>; /* SDMMC1_CK */
- slew-rate = <3>;
- drive-push-pull;
- bias-disable;
- };
- pins2{
- pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */
- slew-rate = <3>;
- drive-open-drain;
- bias-disable;
- };
- };
-
- sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC1_D0 */
- <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC1_D1 */
- <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC1_D2 */
- <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC1_D3 */
- <STM32_PINMUX('D', 6, ANALOG)>, /* SDMMC1_CK */
- <STM32_PINMUX('D', 7, ANALOG)>; /* SDMMC1_CMD */
- };
- };
-
- spi1_pins: spi1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 5, AF5)>,
- /* SPI1_CLK */
- <STM32_PINMUX('B', 5, AF5)>;
- /* SPI1_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('G', 9, AF5)>;
- /* SPI1_MISO */
- bias-disable;
- };
- };
-
- uart4_pins: uart4-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 0, AF8)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('I', 9, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- usart1_pins: usart1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */
- bias-disable;
- };
- };
-
- usart2_pins: usart2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
- bias-disable;
- };
- };
-
- usart3_pins: usart3-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
- <STM32_PINMUX('D', 12, AF7)>; /* USART3_RTS_DE */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 11, AF7)>, /* USART3_RX */
- <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
- bias-disable;
- };
- };
-
- usbotg_hs_pins_a: usbotg-hs-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 4, AF10)>, /* ULPI_NXT */
- <STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */
- <STM32_PINMUX('C', 0, AF10)>, /* ULPI_STP> */
- <STM32_PINMUX('A', 5, AF10)>, /* ULPI_CK> */
- <STM32_PINMUX('A', 3, AF10)>, /* ULPI_D0> */
- <STM32_PINMUX('B', 0, AF10)>, /* ULPI_D1> */
- <STM32_PINMUX('B', 1, AF10)>, /* ULPI_D2> */
- <STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */
- <STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */
- <STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */
- <STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */
- <STM32_PINMUX('B', 5, AF10)>; /* ULPI_D7> */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-};
diff --git a/arch/arm/dts/stm32h7-u-boot.dtsi b/arch/arm/dts/stm32h7-u-boot.dtsi
index dea4db3..9148a1f 100644
--- a/arch/arm/dts/stm32h7-u-boot.dtsi
+++ b/arch/arm/dts/stm32h7-u-boot.dtsi
@@ -53,7 +53,6 @@
bootph-all;
};
-
&fmc {
bootph-all;
};
diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi
deleted file mode 100644
index c490d0a..0000000
--- a/arch/arm/dts/stm32h743.dtsi
+++ /dev/null
@@ -1,695 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
- *
- */
-
-#include "armv7-m.dtsi"
-#include <dt-bindings/clock/stm32h7-clks.h>
-#include <dt-bindings/mfd/stm32h7-rcc.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- clocks {
- clk_hse: clk-hse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- clk_lse: clk-lse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- clk_i2s: i2s_ckin {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
- };
-
- soc {
- timer5: timer@40000c00 {
- compatible = "st,stm32-timer";
- reg = <0x40000c00 0x400>;
- interrupts = <50>;
- clocks = <&rcc TIM5_CK>;
- };
-
- lptimer1: timer@40002400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-lptimer";
- reg = <0x40002400 0x400>;
- clocks = <&rcc LPTIM1_CK>;
- clock-names = "mux";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- trigger@0 {
- compatible = "st,stm32-lptimer-trigger";
- reg = <0>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-lptimer-counter";
- status = "disabled";
- };
- };
-
- spi2: spi@40003800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x40003800 0x400>;
- interrupts = <36>;
- resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
- clocks = <&rcc SPI2_CK>;
- status = "disabled";
-
- };
-
- spi3: spi@40003c00 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x40003c00 0x400>;
- interrupts = <51>;
- resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
- clocks = <&rcc SPI3_CK>;
- status = "disabled";
- };
-
- usart2: serial@40004400 {
- compatible = "st,stm32h7-uart";
- reg = <0x40004400 0x400>;
- interrupts = <38>;
- status = "disabled";
- clocks = <&rcc USART2_CK>;
- };
-
- usart3: serial@40004800 {
- compatible = "st,stm32h7-uart";
- reg = <0x40004800 0x400>;
- interrupts = <39>;
- status = "disabled";
- clocks = <&rcc USART3_CK>;
- };
-
- uart4: serial@40004c00 {
- compatible = "st,stm32h7-uart";
- reg = <0x40004c00 0x400>;
- interrupts = <52>;
- status = "disabled";
- clocks = <&rcc UART4_CK>;
- };
-
- i2c1: i2c@40005400 {
- compatible = "st,stm32f7-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x40005400 0x400>;
- interrupts = <31>,
- <32>;
- resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
- clocks = <&rcc I2C1_CK>;
- status = "disabled";
- };
-
- i2c2: i2c@40005800 {
- compatible = "st,stm32f7-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x40005800 0x400>;
- interrupts = <33>,
- <34>;
- resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
- clocks = <&rcc I2C2_CK>;
- status = "disabled";
- };
-
- i2c3: i2c@40005c00 {
- compatible = "st,stm32f7-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x40005C00 0x400>;
- interrupts = <72>,
- <73>;
- resets = <&rcc STM32H7_APB1L_RESET(I2C3)>;
- clocks = <&rcc I2C3_CK>;
- status = "disabled";
- };
-
- dac: dac@40007400 {
- compatible = "st,stm32h7-dac-core";
- reg = <0x40007400 0x400>;
- clocks = <&rcc DAC12_CK>;
- clock-names = "pclk";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- dac1: dac@1 {
- compatible = "st,stm32-dac";
- #io-channel-cells = <1>;
- reg = <1>;
- status = "disabled";
- };
-
- dac2: dac@2 {
- compatible = "st,stm32-dac";
- #io-channel-cells = <1>;
- reg = <2>;
- status = "disabled";
- };
- };
-
- usart1: serial@40011000 {
- compatible = "st,stm32h7-uart";
- reg = <0x40011000 0x400>;
- interrupts = <37>;
- status = "disabled";
- clocks = <&rcc USART1_CK>;
- };
-
- spi1: spi@40013000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x40013000 0x400>;
- interrupts = <35>;
- resets = <&rcc STM32H7_APB2_RESET(SPI1)>;
- clocks = <&rcc SPI1_CK>;
- status = "disabled";
- };
-
- spi4: spi@40013400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x40013400 0x400>;
- interrupts = <84>;
- resets = <&rcc STM32H7_APB2_RESET(SPI4)>;
- clocks = <&rcc SPI4_CK>;
- status = "disabled";
- };
-
- spi5: spi@40015000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x40015000 0x400>;
- interrupts = <85>;
- resets = <&rcc STM32H7_APB2_RESET(SPI5)>;
- clocks = <&rcc SPI5_CK>;
- status = "disabled";
- };
-
- dma1: dma-controller@40020000 {
- compatible = "st,stm32-dma";
- reg = <0x40020000 0x400>;
- interrupts = <11>,
- <12>,
- <13>,
- <14>,
- <15>,
- <16>,
- <17>,
- <47>;
- clocks = <&rcc DMA1_CK>;
- #dma-cells = <4>;
- st,mem2mem;
- dma-requests = <8>;
- status = "disabled";
- };
-
- dma2: dma-controller@40020400 {
- compatible = "st,stm32-dma";
- reg = <0x40020400 0x400>;
- interrupts = <56>,
- <57>,
- <58>,
- <59>,
- <60>,
- <68>,
- <69>,
- <70>;
- clocks = <&rcc DMA2_CK>;
- #dma-cells = <4>;
- st,mem2mem;
- dma-requests = <8>;
- status = "disabled";
- };
-
- dmamux1: dma-router@40020800 {
- compatible = "st,stm32h7-dmamux";
- reg = <0x40020800 0x40>;
- #dma-cells = <3>;
- dma-channels = <16>;
- dma-requests = <128>;
- dma-masters = <&dma1 &dma2>;
- clocks = <&rcc DMA1_CK>;
- };
-
- adc_12: adc@40022000 {
- compatible = "st,stm32h7-adc-core";
- reg = <0x40022000 0x400>;
- interrupts = <18>;
- clocks = <&rcc ADC12_CK>;
- clock-names = "bus";
- interrupt-controller;
- #interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- adc1: adc@0 {
- compatible = "st,stm32h7-adc";
- #io-channel-cells = <1>;
- reg = <0x0>;
- interrupt-parent = <&adc_12>;
- interrupts = <0>;
- status = "disabled";
- };
-
- adc2: adc@100 {
- compatible = "st,stm32h7-adc";
- #io-channel-cells = <1>;
- reg = <0x100>;
- interrupt-parent = <&adc_12>;
- interrupts = <1>;
- status = "disabled";
- };
- };
-
- usbotg_hs: usb@40040000 {
- compatible = "st,stm32f7-hsotg";
- reg = <0x40040000 0x40000>;
- interrupts = <77>;
- clocks = <&rcc USB1OTG_CK>;
- clock-names = "otg";
- g-rx-fifo-size = <256>;
- g-np-tx-fifo-size = <32>;
- g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- usbotg_fs: usb@40080000 {
- compatible = "st,stm32f4x9-fsotg";
- reg = <0x40080000 0x40000>;
- interrupts = <101>;
- clocks = <&rcc USB2OTG_CK>;
- clock-names = "otg";
- status = "disabled";
- };
-
- ltdc: display-controller@50001000 {
- compatible = "st,stm32-ltdc";
- reg = <0x50001000 0x200>;
- interrupts = <88>, <89>;
- resets = <&rcc STM32H7_APB3_RESET(LTDC)>;
- clocks = <&rcc LTDC_CK>;
- clock-names = "lcd";
- status = "disabled";
- };
-
- mdma1: dma-controller@52000000 {
- compatible = "st,stm32h7-mdma";
- reg = <0x52000000 0x1000>;
- interrupts = <122>;
- clocks = <&rcc MDMA_CK>;
- #dma-cells = <5>;
- dma-channels = <16>;
- dma-requests = <32>;
- };
-
- sdmmc1: mmc@52007000 {
- compatible = "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x10153180>;
- reg = <0x52007000 0x1000>;
- interrupts = <49>;
- clocks = <&rcc SDMMC1_CK>;
- clock-names = "apb_pclk";
- resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- max-frequency = <120000000>;
- };
-
- sdmmc2: mmc@48022400 {
- compatible = "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x10153180>;
- reg = <0x48022400 0x400>;
- interrupts = <124>;
- clocks = <&rcc SDMMC2_CK>;
- clock-names = "apb_pclk";
- resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- max-frequency = <120000000>;
- status = "disabled";
- };
-
- exti: interrupt-controller@58000000 {
- compatible = "st,stm32h7-exti";
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x58000000 0x400>;
- interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>;
- };
-
- syscfg: syscon@58000400 {
- compatible = "st,stm32-syscfg", "syscon";
- reg = <0x58000400 0x400>;
- };
-
- spi6: spi@58001400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x58001400 0x400>;
- interrupts = <86>;
- resets = <&rcc STM32H7_APB4_RESET(SPI6)>;
- clocks = <&rcc SPI6_CK>;
- status = "disabled";
- };
-
- i2c4: i2c@58001c00 {
- compatible = "st,stm32f7-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x58001C00 0x400>;
- interrupts = <95>,
- <96>;
- resets = <&rcc STM32H7_APB4_RESET(I2C4)>;
- clocks = <&rcc I2C4_CK>;
- status = "disabled";
- };
-
- lptimer2: timer@58002400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-lptimer";
- reg = <0x58002400 0x400>;
- clocks = <&rcc LPTIM2_CK>;
- clock-names = "mux";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- trigger@1 {
- compatible = "st,stm32-lptimer-trigger";
- reg = <1>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-lptimer-counter";
- status = "disabled";
- };
- };
-
- lptimer3: timer@58002800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-lptimer";
- reg = <0x58002800 0x400>;
- clocks = <&rcc LPTIM3_CK>;
- clock-names = "mux";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- trigger@2 {
- compatible = "st,stm32-lptimer-trigger";
- reg = <2>;
- status = "disabled";
- };
- };
-
- lptimer4: timer@58002c00 {
- compatible = "st,stm32-lptimer";
- reg = <0x58002c00 0x400>;
- clocks = <&rcc LPTIM4_CK>;
- clock-names = "mux";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- lptimer5: timer@58003000 {
- compatible = "st,stm32-lptimer";
- reg = <0x58003000 0x400>;
- clocks = <&rcc LPTIM5_CK>;
- clock-names = "mux";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- vrefbuf: regulator@58003c00 {
- compatible = "st,stm32-vrefbuf";
- reg = <0x58003C00 0x8>;
- clocks = <&rcc VREF_CK>;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <2500000>;
- status = "disabled";
- };
-
- rtc: rtc@58004000 {
- compatible = "st,stm32h7-rtc";
- reg = <0x58004000 0x400>;
- clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>;
- clock-names = "pclk", "rtc_ck";
- assigned-clocks = <&rcc RTC_CK>;
- assigned-clock-parents = <&rcc LSE_CK>;
- interrupt-parent = <&exti>;
- interrupts = <17 IRQ_TYPE_EDGE_RISING>;
- st,syscfg = <&pwrcfg 0x00 0x100>;
- status = "disabled";
- };
-
- rcc: reset-clock-controller@58024400 {
- compatible = "st,stm32h743-rcc", "st,stm32-rcc";
- reg = <0x58024400 0x400>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
- st,syscfg = <&pwrcfg>;
- };
-
- pwrcfg: power-config@58024800 {
- compatible = "st,stm32-power-config", "syscon";
- reg = <0x58024800 0x400>;
- };
-
- adc_3: adc@58026000 {
- compatible = "st,stm32h7-adc-core";
- reg = <0x58026000 0x400>;
- interrupts = <127>;
- clocks = <&rcc ADC3_CK>;
- clock-names = "bus";
- interrupt-controller;
- #interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- adc3: adc@0 {
- compatible = "st,stm32h7-adc";
- #io-channel-cells = <1>;
- reg = <0x0>;
- interrupt-parent = <&adc_3>;
- interrupts = <0>;
- status = "disabled";
- };
- };
-
- mac: ethernet@40028000 {
- compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
- reg = <0x40028000 0x8000>;
- reg-names = "stmmaceth";
- interrupts = <61>;
- interrupt-names = "macirq";
- clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
- clocks = <&rcc ETH1MAC_CK>, <&rcc ETH1TX_CK>, <&rcc ETH1RX_CK>;
- st,syscon = <&syscfg 0x4>;
- snps,pbl = <8>;
- status = "disabled";
- };
-
- pinctrl: pinctrl@58020000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stm32h743-pinctrl";
- ranges = <0 0x58020000 0x3000>;
- interrupt-parent = <&exti>;
- st,syscfg = <&syscfg 0x8>;
- pins-are-numbered;
-
- gpioa: gpio@58020000 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x0 0x400>;
- clocks = <&rcc GPIOA_CK>;
- st,bank-name = "GPIOA";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@58020400 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x400 0x400>;
- clocks = <&rcc GPIOB_CK>;
- st,bank-name = "GPIOB";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@58020800 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x800 0x400>;
- clocks = <&rcc GPIOC_CK>;
- st,bank-name = "GPIOC";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@58020c00 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0xc00 0x400>;
- clocks = <&rcc GPIOD_CK>;
- st,bank-name = "GPIOD";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@58021000 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x1000 0x400>;
- clocks = <&rcc GPIOE_CK>;
- st,bank-name = "GPIOE";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@58021400 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x1400 0x400>;
- clocks = <&rcc GPIOF_CK>;
- st,bank-name = "GPIOF";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@58021800 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x1800 0x400>;
- clocks = <&rcc GPIOG_CK>;
- st,bank-name = "GPIOG";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@58021c00 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x1c00 0x400>;
- clocks = <&rcc GPIOH_CK>;
- st,bank-name = "GPIOH";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 112 16>;
- };
-
- gpioi: gpio@58022000 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x2000 0x400>;
- clocks = <&rcc GPIOI_CK>;
- st,bank-name = "GPIOI";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 128 16>;
- };
-
- gpioj: gpio@58022400 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x2400 0x400>;
- clocks = <&rcc GPIOJ_CK>;
- st,bank-name = "GPIOJ";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 144 16>;
- };
-
- gpiok: gpio@58022800 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x2800 0x400>;
- clocks = <&rcc GPIOK_CK>;
- st,bank-name = "GPIOK";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <8>;
- gpio-ranges = <&pinctrl 0 160 8>;
- };
- };
- };
-};
-
-&systick {
- clock-frequency = <250000000>;
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32h743i-disco.dts b/arch/arm/dts/stm32h743i-disco.dts
deleted file mode 100644
index b31188f..0000000
--- a/arch/arm/dts/stm32h743i-disco.dts
+++ /dev/null
@@ -1,75 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright 2017 - Patrice Chotard <patrice.chotard@foss.st.com>
- *
- */
-
-/dts-v1/;
-#include "stm32h743.dtsi"
-#include "stm32h7-pinctrl.dtsi"
-
-/ {
- model = "STMicroelectronics STM32H743i-Discovery board";
- compatible = "st,stm32h743i-disco", "st,stm32h743";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@d0000000 {
- device_type = "memory";
- reg = <0xd0000000 0x2000000>;
- };
-
- aliases {
- serial0 = &usart2;
- };
-
- v3v3: regulator-v3v3 {
- compatible = "regulator-fixed";
- regulator-name = "v3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&mac {
- status = "disabled";
- pinctrl-0 = <ðernet_rmii>;
- pinctrl-names = "default";
- phy-mode = "rmii";
- phy-handle = <&phy0>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-};
-
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
- broken-cd;
- st,neg-edge;
- bus-width = <4>;
- vmmc-supply = <&v3v3>;
- status = "okay";
-};
-
-&usart2 {
- pinctrl-0 = <&usart2_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32h743i-eval.dts b/arch/arm/dts/stm32h743i-eval.dts
deleted file mode 100644
index 5c5d805..0000000
--- a/arch/arm/dts/stm32h743i-eval.dts
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-#include "stm32h743.dtsi"
-#include "stm32h7-pinctrl.dtsi"
-
-/ {
- model = "STMicroelectronics STM32H743i-EVAL board";
- compatible = "st,stm32h743i-eval", "st,stm32h743";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@d0000000 {
- device_type = "memory";
- reg = <0xd0000000 0x2000000>;
- };
-
- aliases {
- serial0 = &usart1;
- };
-
- vdda: regulator-vdda {
- compatible = "regulator-fixed";
- regulator-name = "vdda";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- v2v9_sd: regulator-v2v9_sd {
- compatible = "regulator-fixed";
- regulator-name = "v2v9_sd";
- regulator-min-microvolt = <2900000>;
- regulator-max-microvolt = <2900000>;
- regulator-always-on;
- };
-
- usbotg_hs_phy: usb-phy {
- #phy-cells = <0>;
- compatible = "usb-nop-xceiv";
- clocks = <&rcc USB1ULPI_CK>;
- clock-names = "main_clk";
- };
-};
-
-&adc_12 {
- vdda-supply = <&vdda>;
- vref-supply = <&vdda>;
- status = "okay";
- adc1: adc@0 {
- /* potentiometer */
- st,adc-channels = <0>;
- status = "okay";
- };
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins_a>;
- pinctrl-names = "default";
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-};
-
-&rtc {
- status = "okay";
-};
-
-&mac {
- status = "disabled";
- pinctrl-0 = <ðernet_rmii>;
- pinctrl-names = "default";
- phy-mode = "rmii";
- phy-handle = <&phy0>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-};
-
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
- broken-cd;
- st,sig-dir;
- st,neg-edge;
- st,use-ckin;
- bus-width = <4>;
- vmmc-supply = <&v2v9_sd>;
- status = "okay";
-};
-
-&usart1 {
- pinctrl-0 = <&usart1_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_hs {
- pinctrl-0 = <&usbotg_hs_pins_a>;
- pinctrl-names = "default";
- phys = <&usbotg_hs_phy>;
- phy-names = "usb2-phy";
- dr_mode = "otg";
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32h750.dtsi b/arch/arm/dts/stm32h750.dtsi
deleted file mode 100644
index 99533f3..0000000
--- a/arch/arm/dts/stm32h750.dtsi
+++ /dev/null
@@ -1,5 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/* Copyright (C) STMicroelectronics 2021 - All Rights Reserved */
-
-#include "stm32h743.dtsi"
-
diff --git a/arch/arm/dts/stm32h750i-art-pi.dts b/arch/arm/dts/stm32h750i-art-pi.dts
deleted file mode 100644
index c7c7132..0000000
--- a/arch/arm/dts/stm32h750i-art-pi.dts
+++ /dev/null
@@ -1,188 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright 2021 - Dillon Min <dillon.minfei@gmail.com>
- *
- */
-
-/dts-v1/;
-#include "stm32h750.dtsi"
-#include "stm32h7-pinctrl.dtsi"
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "RT-Thread STM32H750i-ART-PI board";
- compatible = "st,stm32h750i-art-pi", "st,stm32h750";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:2000000n8";
- };
-
- memory@c0000000 {
- device_type = "memory";
- reg = <0xc0000000 0x2000000>;
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- linux,cma {
- compatible = "shared-dma-pool";
- no-map;
- size = <0x100000>;
- linux,dma-default;
- };
- };
-
- aliases {
- serial0 = &uart4;
- serial1 = &usart3;
- };
-
- leds {
- compatible = "gpio-leds";
- led-red {
- gpios = <&gpioi 8 0>;
- };
- led-green {
- gpios = <&gpioc 15 0>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- v3v3: regulator-v3v3 {
- compatible = "regulator-fixed";
- regulator-name = "v3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- wlan_pwr: regulator-wlan {
- compatible = "regulator-fixed";
-
- regulator-name = "wl-reg";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&dma1 {
- status = "okay";
-};
-
-&dma2 {
- status = "okay";
-};
-
-&mac {
- status = "disabled";
- pinctrl-0 = <ðernet_rmii>;
- pinctrl-names = "default";
- phy-mode = "rmii";
- phy-handle = <&phy0>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-};
-
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
- broken-cd;
- st,neg-edge;
- bus-width = <4>;
- vmmc-supply = <&v3v3>;
- status = "okay";
-};
-
-&sdmmc2 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc2_b4_pins_a>;
- pinctrl-1 = <&sdmmc2_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
- broken-cd;
- non-removable;
- st,neg-edge;
- bus-width = <4>;
- vmmc-supply = <&wlan_pwr>;
- status = "okay";
-
- #address-cells = <1>;
- #size-cells = <0>;
- brcmf: bcrmf@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
-};
-
-&spi1 {
- status = "okay";
- pinctrl-0 = <&spi1_pins>;
- pinctrl-names = "default";
- cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>;
- dmas = <&dmamux1 37 0x400 0x05>,
- <&dmamux1 38 0x400 0x05>;
- dma-names = "rx", "tx";
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "winbond,w25q128", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <80000000>;
-
- partition@0 {
- label = "root filesystem";
- reg = <0 0x1000000>;
- };
- };
-};
-
-&usart2 {
- pinctrl-0 = <&usart2_pins>;
- pinctrl-names = "default";
- status = "disabled";
-};
-
-&usart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&usart3_pins>;
- dmas = <&dmamux1 45 0x400 0x05>,
- <&dmamux1 46 0x400 0x05>;
- dma-names = "rx", "tx";
- st,hw-flow-ctrl;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- host-wakeup-gpios = <&gpioc 0 GPIO_ACTIVE_HIGH>;
- device-wakeup-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>;
- shutdown-gpios = <&gpioi 11 GPIO_ACTIVE_HIGH>;
- max-speed = <115200>;
- };
-};
-
-&uart4 {
- pinctrl-0 = <&uart4_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi b/arch/arm/dts/stm32mp13-pinctrl.dtsi
deleted file mode 100644
index 52c2a9f..0000000
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ /dev/null
@@ -1,888 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com>
- */
-#include <dt-bindings/pinctrl/stm32-pinfunc.h>
-
-&pinctrl {
- adc1_pins_a: adc1-pins-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */
- };
- };
-
- adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
- <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */
- };
- };
-
- adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 {
- pins {
- pinmux = <STM32_PINMUX('A', 5, ANALOG)>, /* ADC1_INP2 */
- <STM32_PINMUX('F', 13, ANALOG)>; /* ADC1_INP11 */
- };
- };
-
- eth1_rgmii_pins_a: eth1-rgmii-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 5, AF10)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('C', 1, AF11)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
- <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 7, AF11)>, /* ETH_RGMII_RX_CTL */
- <STM32_PINMUX('D', 7, AF10)>; /* ETH_RGMII_RX_CLK */
- bias-disable;
- };
-
- };
-
- eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 5, ANALOG)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
- <STM32_PINMUX('G', 2, ANALOG)>, /* ETH_MDC */
- <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('A', 7, ANALOG)>, /* ETH_RGMII_RX_CTL */
- <STM32_PINMUX('D', 7, ANALOG)>; /* ETH_RGMII_RX_CLK */
- };
- };
-
- eth2_rgmii_pins_a: eth2-rgmii-0 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 11, AF10)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('G', 1, AF10)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 6, AF11)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('F', 6, AF11)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('G', 3, AF10)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('B', 6, AF11)>, /* ETH_MDIO */
- <STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('E', 2, AF10)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('H', 6, AF12)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('A', 8, AF11)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 12, AF11)>, /* ETH_RGMII_RX_CTL */
- <STM32_PINMUX('H', 11, AF11)>; /* ETH_RGMII_RX_CLK */
- bias-disable;
- };
- };
-
- eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('G', 8, ANALOG)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('B', 2, ANALOG)>, /* ETH_MDIO */
- <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_MDC */
- <STM32_PINMUX('F', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 12, ANALOG)>, /* ETH_RGMII_RX_CTL */
- <STM32_PINMUX('H', 11, ANALOG)>; /* ETH_RGMII_RX_CLK */
- };
- };
-
- i2c1_pins_a: i2c1-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
- <STM32_PINMUX('E', 8, AF5)>; /* I2C1_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c1_sleep_pins_a: i2c1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
- <STM32_PINMUX('E', 8, ANALOG)>; /* I2C1_SDA */
- };
- };
-
- i2c5_pins_a: i2c5-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */
- <STM32_PINMUX('H', 6, AF4)>; /* I2C5_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c5_sleep_pins_a: i2c5-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */
- <STM32_PINMUX('H', 6, ANALOG)>; /* I2C5_SDA */
- };
- };
-
- i2c5_pins_b: i2c5-1 {
- pins {
- pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */
- <STM32_PINMUX('E', 13, AF4)>; /* I2C5_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c5_sleep_pins_b: i2c5-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */
- <STM32_PINMUX('E', 13, ANALOG)>; /* I2C5_SDA */
- };
- };
-
- m_can1_pins_a: m-can1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 10, AF9)>; /* CAN1_TX */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */
- bias-disable;
- };
- };
-
- m_can1_sleep_pins_a: m_can1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 10, ANALOG)>, /* CAN1_TX */
- <STM32_PINMUX('D', 0, ANALOG)>; /* CAN1_RX */
- };
- };
-
- m_can2_pins_a: m-can2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 0, AF9)>; /* CAN2_TX */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 0, AF9)>; /* CAN2_RX */
- bias-disable;
- };
- };
-
- m_can2_sleep_pins_a: m_can2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 0, ANALOG)>, /* CAN2_TX */
- <STM32_PINMUX('E', 0, ANALOG)>; /* CAN2_RX */
- };
- };
-
- mcp23017_pins_a: mcp23017-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 12, GPIO)>;
- bias-pull-up;
- };
- };
-
- pwm1_ch3n_pins_a: pwm1-ch3n-0 {
- pins {
- pinmux = <STM32_PINMUX('E', 12, AF1)>; /* TIM1_CH3N */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm1_ch3n_sleep_pins_a: pwm1-ch3n-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('E', 12, ANALOG)>; /* TIM1_CH3N */
- };
- };
-
- pwm3_pins_a: pwm3-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 1, AF2)>; /* TIM3_CH4 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm3_sleep_pins_a: pwm3-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 1, ANALOG)>; /* TIM3_CH4 */
- };
- };
-
- pwm4_pins_a: pwm4-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm4_sleep_pins_a: pwm4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
- };
- };
-
- pwm5_pins_a: pwm5-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 12, AF2)>; /* TIM5_CH3 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm5_sleep_pins_a: pwm5-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 12, ANALOG)>; /* TIM5_CH3 */
- };
- };
-
- pwm8_pins_a: pwm8-0 {
- pins {
- pinmux = <STM32_PINMUX('E', 5, AF3)>; /* TIM8_CH3 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm8_sleep_pins_a: pwm8-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('E', 5, ANALOG)>; /* TIM8_CH3 */
- };
- };
-
- pwm13_pins_a: pwm13-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 6, AF9)>; /* TIM13_CH1 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm13_sleep_pins_a: pwm13-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 6, ANALOG)>; /* TIM13_CH1 */
- };
- };
-
- pwm14_pins_a: pwm14-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 9, AF9)>; /* TIM14_CH1 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm14_sleep_pins_a: pwm14-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 9, ANALOG)>; /* TIM14_CH1 */
- };
- };
-
- qspi_clk_pins_a: qspi-clk-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
- bias-disable;
- drive-push-pull;
- slew-rate = <3>;
- };
- };
-
- qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
- };
- };
-
- qspi_bk1_pins_a: qspi-bk1-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
- <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
- <STM32_PINMUX('D', 11, AF9)>, /* QSPI_BK1_IO2 */
- <STM32_PINMUX('H', 7, AF13)>; /* QSPI_BK1_IO3 */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- };
-
- qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
- <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
- <STM32_PINMUX('D', 11, ANALOG)>, /* QSPI_BK1_IO2 */
- <STM32_PINMUX('H', 7, ANALOG)>; /* QSPI_BK1_IO3 */
- };
- };
-
- qspi_cs1_pins_a: qspi-cs1-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 2, AF9)>; /* QSPI_BK1_NCS */
- bias-pull-up;
- drive-push-pull;
- slew-rate = <1>;
- };
- };
-
- qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 2, ANALOG)>; /* QSPI_BK1_NCS */
- };
- };
-
- sai1a_pins_a: sai1a-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 4, AF12)>, /* SAI1_SCK_A */
- <STM32_PINMUX('D', 6, AF6)>, /* SAI1_SD_A */
- <STM32_PINMUX('E', 11, AF6)>; /* SAI1_FS_A */
- slew-rate = <0>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sai1a_sleep_pins_a: sai1a-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* SAI1_SCK_A */
- <STM32_PINMUX('D', 6, ANALOG)>, /* SAI1_SD_A */
- <STM32_PINMUX('E', 11, ANALOG)>; /* SAI1_FS_A */
- };
- };
-
- sai1b_pins_a: sai1b-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 0, AF6)>; /* SAI1_SD_B */
- bias-disable;
- };
- };
-
- sai1b_sleep_pins_a: sai1b-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 0, ANALOG)>; /* SAI1_SD_B */
- };
- };
-
- sdmmc1_b4_pins_a: sdmmc1-b4-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
- <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
- slew-rate = <1>;
- drive-open-drain;
- bias-disable;
- };
- };
-
- sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
- <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
- <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
- };
- };
-
- sdmmc1_clk_pins_a: sdmmc1-clk-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sdmmc2_b4_pins_a: sdmmc2-b4-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
- <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
- <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
- <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2_D3 */
- <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- };
-
- sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
- <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
- <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
- <STM32_PINMUX('B', 4, AF10)>; /* SDMMC2_D3 */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- pins2 {
- pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
- slew-rate = <1>;
- drive-open-drain;
- bias-pull-up;
- };
- };
-
- sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
- <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
- <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
- <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
- <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
- <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
- };
- };
-
- sdmmc2_clk_pins_a: sdmmc2-clk-0 {
- pins {
- pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- };
-
- sdmmc2_d47_pins_a: sdmmc2-d47-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 0, AF10)>, /* SDMMC2_D4 */
- <STM32_PINMUX('B', 9, AF10)>, /* SDMMC2_D5 */
- <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
- <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- };
-
- sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC2_D4 */
- <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC2_D5 */
- <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
- <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
- };
- };
-
- spi2_pins_a: spi2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, AF6)>, /* SPI2_SCK */
- <STM32_PINMUX('H', 10, AF6)>; /* SPI2_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('B', 5, AF5)>; /* SPI2_MISO */
- bias-disable;
- };
- };
-
- spi2_sleep_pins_a: spi2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* SPI2_SCK */
- <STM32_PINMUX('B', 5, ANALOG)>, /* SPI2_MISO */
- <STM32_PINMUX('H', 10, ANALOG)>; /* SPI2_MOSI */
- };
- };
-
- spi3_pins_a: spi3-0 {
- pins1 {
- pinmux = <STM32_PINMUX('H', 13, AF6)>, /* SPI3_SCK */
- <STM32_PINMUX('F', 1, AF5)>; /* SPI3_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('D', 4, AF5)>; /* SPI3_MISO */
- bias-disable;
- };
- };
-
- spi3_sleep_pins_a: spi3-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* SPI3_SCK */
- <STM32_PINMUX('D', 4, ANALOG)>, /* SPI3_MISO */
- <STM32_PINMUX('F', 1, ANALOG)>; /* SPI3_MOSI */
- };
- };
-
- spi5_pins_a: spi5-0 {
- pins1 {
- pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */
- <STM32_PINMUX('H', 3, AF5)>; /* SPI5_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('A', 8, AF5)>; /* SPI5_MISO */
- bias-disable;
- };
- };
-
- spi5_sleep_pins_a: spi5-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 7, ANALOG)>, /* SPI5_SCK */
- <STM32_PINMUX('A', 8, ANALOG)>, /* SPI5_MISO */
- <STM32_PINMUX('H', 3, ANALOG)>; /* SPI5_MOSI */
- };
- };
-
- stm32g0_intn_pins_a: stm32g0-intn-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 2, GPIO)>;
- bias-pull-up;
- };
- };
-
- uart4_pins_a: uart4-0 {
- pins1 {
- pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- uart4_idle_pins_a: uart4-idle-0 {
- pins1 {
- pinmux = <STM32_PINMUX('D', 6, ANALOG)>; /* UART4_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- uart4_sleep_pins_a: uart4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 6, ANALOG)>, /* UART4_TX */
- <STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */
- };
- };
-
- uart4_pins_b: uart4-1 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 9, AF8)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
- bias-pull-up;
- };
- };
-
- uart4_idle_pins_b: uart4-idle-1 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 9, ANALOG)>; /* UART4_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
- bias-pull-up;
- };
- };
-
- uart4_sleep_pins_b: uart4-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('A', 9, ANALOG)>, /* UART4_TX */
- <STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */
- };
- };
-
- uart7_pins_a: uart7-0 {
- pins1 {
- pinmux = <STM32_PINMUX('H', 2, AF8)>, /* UART7_TX */
- <STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 10, AF7)>, /* UART7_RX */
- <STM32_PINMUX('G', 7, AF8)>; /* UART7_CTS_NSS */
- bias-disable;
- };
- };
-
- uart7_idle_pins_a: uart7-idle-0 {
- pins1 {
- pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */
- <STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins3 {
- pinmux = <STM32_PINMUX('E', 10, AF7)>; /* UART7_RX */
- bias-disable;
- };
- };
-
- uart7_sleep_pins_a: uart7-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */
- <STM32_PINMUX('B', 12, ANALOG)>, /* UART7_RTS */
- <STM32_PINMUX('E', 10, ANALOG)>, /* UART7_RX */
- <STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */
- };
- };
-
- uart8_pins_a: uart8-0 {
- pins1 {
- pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
- bias-pull-up;
- };
- };
-
- uart8_idle_pins_a: uart8-idle-0 {
- pins1 {
- pinmux = <STM32_PINMUX('E', 1, ANALOG)>; /* UART8_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
- bias-pull-up;
- };
- };
-
- uart8_sleep_pins_a: uart8-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('E', 1, ANALOG)>, /* UART8_TX */
- <STM32_PINMUX('F', 9, ANALOG)>; /* UART8_RX */
- };
- };
-
- usart1_pins_a: usart1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */
- <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 0, AF4)>, /* USART1_RX */
- <STM32_PINMUX('A', 7, AF7)>; /* USART1_CTS_NSS */
- bias-pull-up;
- };
- };
-
- usart1_idle_pins_a: usart1-idle-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
- <STM32_PINMUX('A', 7, ANALOG)>; /* USART1_CTS_NSS */
- };
- pins2 {
- pinmux = <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins3 {
- pinmux = <STM32_PINMUX('B', 0, AF4)>; /* USART1_RX */
- bias-pull-up;
- };
- };
-
- usart1_sleep_pins_a: usart1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
- <STM32_PINMUX('C', 2, ANALOG)>, /* USART1_RTS */
- <STM32_PINMUX('A', 7, ANALOG)>, /* USART1_CTS_NSS */
- <STM32_PINMUX('B', 0, ANALOG)>; /* USART1_RX */
- };
- };
-
- usart1_pins_b: usart1-1 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 0, AF7)>; /* USART1_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */
- bias-pull-up;
- };
- };
-
- usart1_idle_pins_b: usart1-idle-1 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* USART1_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */
- bias-pull-up;
- };
- };
-
- usart1_sleep_pins_b: usart1-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
- <STM32_PINMUX('D', 14, ANALOG)>; /* USART1_RX */
- };
- };
-
- usart2_pins_a: usart2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */
- <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */
- <STM32_PINMUX('E', 11, AF2)>; /* USART2_CTS_NSS */
- bias-disable;
- };
- };
-
- usart2_idle_pins_a: usart2-idle-0 {
- pins1 {
- pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
- <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins3 {
- pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */
- bias-disable;
- };
- };
-
- usart2_sleep_pins_a: usart2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
- <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
- <STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */
- <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
- };
- };
-
- usart2_pins_b: usart2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 11, AF1)>, /* USART2_TX */
- <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */
- <STM32_PINMUX('E', 15, AF3)>; /* USART2_CTS_NSS */
- bias-disable;
- };
- };
-
- usart2_idle_pins_b: usart2-idle-0 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */
- <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins3 {
- pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */
- bias-disable;
- };
- };
-
- usart2_sleep_pins_b: usart2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */
- <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */
- <STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */
- <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */
- };
- };
-};
diff --git a/arch/arm/dts/stm32mp13-u-boot.dtsi b/arch/arm/dts/stm32mp13-u-boot.dtsi
index af7edc7..1fe6966 100644
--- a/arch/arm/dts/stm32mp13-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp13-u-boot.dtsi
@@ -48,6 +48,10 @@
bootph-all;
};
+&etzpc {
+ bootph-all;
+};
+
&gpioa {
bootph-all;
};
diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi
deleted file mode 100644
index ad331b7..0000000
--- a/arch/arm/dts/stm32mp131.dtsi
+++ /dev/null
@@ -1,1567 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/stm32mp13-clks.h>
-#include <dt-bindings/reset/stm32mp13-resets.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- compatible = "arm,cortex-a7";
- device_type = "cpu";
- reg = <0>;
- };
- };
-
- arm-pmu {
- compatible = "arm,cortex-a7-pmu";
- interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>;
- interrupt-parent = <&intc>;
- };
-
- firmware {
- optee {
- method = "smc";
- compatible = "linaro,optee-tz";
- interrupt-parent = <&intc>;
- interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- scmi: scmi {
- compatible = "linaro,scmi-optee";
- #address-cells = <1>;
- #size-cells = <0>;
- linaro,optee-channel-id = <0>;
-
- scmi_clk: protocol@14 {
- reg = <0x14>;
- #clock-cells = <1>;
- };
-
- scmi_reset: protocol@16 {
- reg = <0x16>;
- #reset-cells = <1>;
- };
-
- scmi_voltd: protocol@17 {
- reg = <0x17>;
-
- scmi_regu: regulators {
- #address-cells = <1>;
- #size-cells = <0>;
-
- scmi_reg11: regulator@0 {
- reg = <VOLTD_SCMI_REG11>;
- regulator-name = "reg11";
- };
- scmi_reg18: regulator@1 {
- reg = <VOLTD_SCMI_REG18>;
- regulator-name = "reg18";
- };
- scmi_usb33: regulator@2 {
- reg = <VOLTD_SCMI_USB33>;
- regulator-name = "usb33";
- };
- };
- };
- };
- };
-
- intc: interrupt-controller@a0021000 {
- compatible = "arm,cortex-a7-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0xa0021000 0x1000>,
- <0xa0022000 0x2000>;
- };
-
- psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
-
- timer {
- compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
- interrupt-parent = <&intc>;
- always-on;
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&intc>;
- ranges;
-
- timers2: timer@40000000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000000 0x400>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM2_K>;
- clock-names = "int";
- dmas = <&dmamux1 18 0x400 0x1>,
- <&dmamux1 19 0x400 0x1>,
- <&dmamux1 20 0x400 0x1>,
- <&dmamux1 21 0x400 0x1>,
- <&dmamux1 22 0x400 0x1>;
- dma-names = "ch1", "ch2", "ch3", "ch4", "up";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@1 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <1>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-timer-counter";
- status = "disabled";
- };
- };
-
- timers3: timer@40001000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40001000 0x400>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM3_K>;
- clock-names = "int";
- dmas = <&dmamux1 23 0x400 0x1>,
- <&dmamux1 24 0x400 0x1>,
- <&dmamux1 25 0x400 0x1>,
- <&dmamux1 26 0x400 0x1>,
- <&dmamux1 27 0x400 0x1>,
- <&dmamux1 28 0x400 0x1>;
- dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@2 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <2>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-timer-counter";
- status = "disabled";
- };
- };
-
- timers4: timer@40002000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40002000 0x400>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM4_K>;
- clock-names = "int";
- dmas = <&dmamux1 29 0x400 0x1>,
- <&dmamux1 30 0x400 0x1>,
- <&dmamux1 31 0x400 0x1>,
- <&dmamux1 32 0x400 0x1>;
- dma-names = "ch1", "ch2", "ch3", "up";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@3 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <3>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-timer-counter";
- status = "disabled";
- };
- };
-
- timers5: timer@40003000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40003000 0x400>;
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM5_K>;
- clock-names = "int";
- dmas = <&dmamux1 55 0x400 0x1>,
- <&dmamux1 56 0x400 0x1>,
- <&dmamux1 57 0x400 0x1>,
- <&dmamux1 58 0x400 0x1>,
- <&dmamux1 59 0x400 0x1>,
- <&dmamux1 60 0x400 0x1>;
- dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@4 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <4>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-timer-counter";
- status = "disabled";
- };
- };
-
- timers6: timer@40004000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40004000 0x400>;
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM6_K>;
- clock-names = "int";
- dmas = <&dmamux1 69 0x400 0x1>;
- dma-names = "up";
- status = "disabled";
-
- timer@5 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <5>;
- status = "disabled";
- };
- };
-
- timers7: timer@40005000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40005000 0x400>;
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM7_K>;
- clock-names = "int";
- dmas = <&dmamux1 70 0x400 0x1>;
- dma-names = "up";
- status = "disabled";
-
- timer@6 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <6>;
- status = "disabled";
- };
- };
-
- lptimer1: timer@40009000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-lptimer";
- reg = <0x40009000 0x400>;
- interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc LPTIM1_K>;
- clock-names = "mux";
- wakeup-source;
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- trigger@0 {
- compatible = "st,stm32-lptimer-trigger";
- reg = <0>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-lptimer-counter";
- status = "disabled";
- };
-
- timer {
- compatible = "st,stm32-lptimer-timer";
- status = "disabled";
- };
- };
-
- i2s2: audio-controller@4000b000 {
- compatible = "st,stm32h7-i2s";
- reg = <0x4000b000 0x400>;
- #sound-dai-cells = <0>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 39 0x400 0x01>,
- <&dmamux1 40 0x400 0x01>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- spi2: spi@4000b000 {
- compatible = "st,stm32h7-spi";
- reg = <0x4000b000 0x400>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SPI2_K>;
- resets = <&rcc SPI2_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- dmas = <&dmamux1 39 0x400 0x01>,
- <&dmamux1 40 0x400 0x01>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- i2s3: audio-controller@4000c000 {
- compatible = "st,stm32h7-i2s";
- reg = <0x4000c000 0x400>;
- #sound-dai-cells = <0>;
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 61 0x400 0x01>,
- <&dmamux1 62 0x400 0x01>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- spi3: spi@4000c000 {
- compatible = "st,stm32h7-spi";
- reg = <0x4000c000 0x400>;
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SPI3_K>;
- resets = <&rcc SPI3_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- dmas = <&dmamux1 61 0x400 0x01>,
- <&dmamux1 62 0x400 0x01>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- spdifrx: audio-controller@4000d000 {
- compatible = "st,stm32h7-spdifrx";
- reg = <0x4000d000 0x400>;
- #sound-dai-cells = <0>;
- clocks = <&rcc SPDIF_K>;
- clock-names = "kclk";
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 93 0x400 0x01>,
- <&dmamux1 94 0x400 0x01>;
- dma-names = "rx", "rx-ctrl";
- status = "disabled";
- };
-
- usart3: serial@4000f000 {
- compatible = "st,stm32h7-uart";
- reg = <0x4000f000 0x400>;
- interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc USART3_K>;
- resets = <&rcc USART3_R>;
- wakeup-source;
- dmas = <&dmamux1 45 0x400 0x5>,
- <&dmamux1 46 0x400 0x1>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uart4: serial@40010000 {
- compatible = "st,stm32h7-uart";
- reg = <0x40010000 0x400>;
- interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc UART4_K>;
- resets = <&rcc UART4_R>;
- wakeup-source;
- dmas = <&dmamux1 63 0x400 0x5>,
- <&dmamux1 64 0x400 0x1>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uart5: serial@40011000 {
- compatible = "st,stm32h7-uart";
- reg = <0x40011000 0x400>;
- interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc UART5_K>;
- resets = <&rcc UART5_R>;
- wakeup-source;
- dmas = <&dmamux1 65 0x400 0x5>,
- <&dmamux1 66 0x400 0x1>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- i2c1: i2c@40012000 {
- compatible = "st,stm32mp13-i2c";
- reg = <0x40012000 0x400>;
- interrupt-names = "event", "error";
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc I2C1_K>;
- resets = <&rcc I2C1_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- dmas = <&dmamux1 33 0x400 0x1>,
- <&dmamux1 34 0x400 0x1>;
- dma-names = "rx", "tx";
- st,syscfg-fmp = <&syscfg 0x4 0x1>;
- i2c-analog-filter;
- status = "disabled";
- };
-
- i2c2: i2c@40013000 {
- compatible = "st,stm32mp13-i2c";
- reg = <0x40013000 0x400>;
- interrupt-names = "event", "error";
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc I2C2_K>;
- resets = <&rcc I2C2_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- dmas = <&dmamux1 35 0x400 0x1>,
- <&dmamux1 36 0x400 0x1>;
- dma-names = "rx", "tx";
- st,syscfg-fmp = <&syscfg 0x4 0x2>;
- i2c-analog-filter;
- status = "disabled";
- };
-
- uart7: serial@40018000 {
- compatible = "st,stm32h7-uart";
- reg = <0x40018000 0x400>;
- interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc UART7_K>;
- resets = <&rcc UART7_R>;
- wakeup-source;
- dmas = <&dmamux1 79 0x400 0x5>,
- <&dmamux1 80 0x400 0x1>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uart8: serial@40019000 {
- compatible = "st,stm32h7-uart";
- reg = <0x40019000 0x400>;
- interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc UART8_K>;
- resets = <&rcc UART8_R>;
- wakeup-source;
- dmas = <&dmamux1 81 0x400 0x5>,
- <&dmamux1 82 0x400 0x1>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- timers1: timer@44000000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x44000000 0x400>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "brk", "up", "trg-com", "cc";
- clocks = <&rcc TIM1_K>;
- clock-names = "int";
- dmas = <&dmamux1 11 0x400 0x1>,
- <&dmamux1 12 0x400 0x1>,
- <&dmamux1 13 0x400 0x1>,
- <&dmamux1 14 0x400 0x1>,
- <&dmamux1 15 0x400 0x1>,
- <&dmamux1 16 0x400 0x1>,
- <&dmamux1 17 0x400 0x1>;
- dma-names = "ch1", "ch2", "ch3", "ch4",
- "up", "trig", "com";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@0 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <0>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-timer-counter";
- status = "disabled";
- };
- };
-
- timers8: timer@44001000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x44001000 0x400>;
- interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "brk", "up", "trg-com", "cc";
- clocks = <&rcc TIM8_K>;
- clock-names = "int";
- dmas = <&dmamux1 47 0x400 0x1>,
- <&dmamux1 48 0x400 0x1>,
- <&dmamux1 49 0x400 0x1>,
- <&dmamux1 50 0x400 0x1>,
- <&dmamux1 51 0x400 0x1>,
- <&dmamux1 52 0x400 0x1>,
- <&dmamux1 53 0x400 0x1>;
- dma-names = "ch1", "ch2", "ch3", "ch4",
- "up", "trig", "com";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@7 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <7>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-timer-counter";
- status = "disabled";
- };
- };
-
- usart6: serial@44003000 {
- compatible = "st,stm32h7-uart";
- reg = <0x44003000 0x400>;
- interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc USART6_K>;
- resets = <&rcc USART6_R>;
- wakeup-source;
- dmas = <&dmamux1 71 0x400 0x5>,
- <&dmamux1 72 0x400 0x1>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- i2s1: audio-controller@44004000 {
- compatible = "st,stm32h7-i2s";
- reg = <0x44004000 0x400>;
- #sound-dai-cells = <0>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 37 0x400 0x01>,
- <&dmamux1 38 0x400 0x01>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- spi1: spi@44004000 {
- compatible = "st,stm32h7-spi";
- reg = <0x44004000 0x400>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SPI1_K>;
- resets = <&rcc SPI1_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- dmas = <&dmamux1 37 0x400 0x01>,
- <&dmamux1 38 0x400 0x01>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- sai1: sai@4400a000 {
- compatible = "st,stm32h7-sai";
- reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
- ranges = <0 0x4400a000 0x400>;
- #address-cells = <1>;
- #size-cells = <1>;
- interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&rcc SAI1_R>;
- status = "disabled";
-
- sai1a: audio-controller@4400a004 {
- compatible = "st,stm32-sai-sub-a";
- reg = <0x4 0x20>;
- #sound-dai-cells = <0>;
- clocks = <&rcc SAI1_K>;
- clock-names = "sai_ck";
- dmas = <&dmamux1 87 0x400 0x01>;
- status = "disabled";
- };
-
- sai1b: audio-controller@4400a024 {
- compatible = "st,stm32-sai-sub-b";
- reg = <0x24 0x20>;
- #sound-dai-cells = <0>;
- clocks = <&rcc SAI1_K>;
- clock-names = "sai_ck";
- dmas = <&dmamux1 88 0x400 0x01>;
- status = "disabled";
- };
- };
-
- sai2: sai@4400b000 {
- compatible = "st,stm32h7-sai";
- reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
- ranges = <0 0x4400b000 0x400>;
- #address-cells = <1>;
- #size-cells = <1>;
- interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&rcc SAI2_R>;
- status = "disabled";
-
- sai2a: audio-controller@4400b004 {
- compatible = "st,stm32-sai-sub-a";
- reg = <0x4 0x20>;
- #sound-dai-cells = <0>;
- clocks = <&rcc SAI2_K>;
- clock-names = "sai_ck";
- dmas = <&dmamux1 89 0x400 0x01>;
- status = "disabled";
- };
-
- sai2b: audio-controller@4400b024 {
- compatible = "st,stm32-sai-sub-b";
- reg = <0x24 0x20>;
- #sound-dai-cells = <0>;
- clocks = <&rcc SAI2_K>;
- clock-names = "sai_ck";
- dmas = <&dmamux1 90 0x400 0x01>;
- status = "disabled";
- };
- };
-
- dfsdm: dfsdm@4400d000 {
- compatible = "st,stm32mp1-dfsdm";
- reg = <0x4400d000 0x800>;
- clocks = <&rcc DFSDM_K>;
- clock-names = "dfsdm";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- dfsdm0: filter@0 {
- compatible = "st,stm32-dfsdm-adc";
- reg = <0>;
- #io-channel-cells = <1>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 101 0x400 0x01>;
- dma-names = "rx";
- status = "disabled";
- };
-
- dfsdm1: filter@1 {
- compatible = "st,stm32-dfsdm-adc";
- reg = <1>;
- #io-channel-cells = <1>;
- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 102 0x400 0x01>;
- dma-names = "rx";
- status = "disabled";
- };
- };
-
- dma1: dma-controller@48000000 {
- compatible = "st,stm32-dma";
- reg = <0x48000000 0x400>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc DMA1>;
- resets = <&rcc DMA1_R>;
- #dma-cells = <4>;
- st,mem2mem;
- dma-requests = <8>;
- };
-
- dma2: dma-controller@48001000 {
- compatible = "st,stm32-dma";
- reg = <0x48001000 0x400>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc DMA2>;
- resets = <&rcc DMA2_R>;
- #dma-cells = <4>;
- st,mem2mem;
- dma-requests = <8>;
- };
-
- dmamux1: dma-router@48002000 {
- compatible = "st,stm32h7-dmamux";
- reg = <0x48002000 0x40>;
- clocks = <&rcc DMAMUX1>;
- resets = <&rcc DMAMUX1_R>;
- #dma-cells = <3>;
- dma-masters = <&dma1 &dma2>;
- dma-requests = <128>;
- dma-channels = <16>;
- };
-
- adc_2: adc@48004000 {
- compatible = "st,stm32mp13-adc-core";
- reg = <0x48004000 0x400>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc ADC2>, <&rcc ADC2_K>;
- clock-names = "bus", "adc";
- interrupt-controller;
- #interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- adc2: adc@0 {
- compatible = "st,stm32mp13-adc";
- #io-channel-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0>;
- interrupt-parent = <&adc_2>;
- interrupts = <0>;
- dmas = <&dmamux1 10 0x400 0x80000001>;
- dma-names = "rx";
- status = "disabled";
-
- channel@13 {
- reg = <13>;
- label = "vrefint";
- };
- channel@14 {
- reg = <14>;
- label = "vddcore";
- };
- channel@16 {
- reg = <16>;
- label = "vddcpu";
- };
- channel@17 {
- reg = <17>;
- label = "vddq_ddr";
- };
- };
- };
-
- usbotg_hs: usb@49000000 {
- compatible = "st,stm32mp15-hsotg", "snps,dwc2";
- reg = <0x49000000 0x40000>;
- clocks = <&rcc USBO_K>;
- clock-names = "otg";
- resets = <&rcc USBO_R>;
- reset-names = "dwc2";
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- g-rx-fifo-size = <512>;
- g-np-tx-fifo-size = <32>;
- g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
- dr_mode = "otg";
- otg-rev = <0x200>;
- usb33d-supply = <&scmi_usb33>;
- status = "disabled";
- };
-
- usart1: serial@4c000000 {
- compatible = "st,stm32h7-uart";
- reg = <0x4c000000 0x400>;
- interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc USART1_K>;
- resets = <&rcc USART1_R>;
- wakeup-source;
- dmas = <&dmamux1 41 0x400 0x5>,
- <&dmamux1 42 0x400 0x1>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- usart2: serial@4c001000 {
- compatible = "st,stm32h7-uart";
- reg = <0x4c001000 0x400>;
- interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc USART2_K>;
- resets = <&rcc USART2_R>;
- wakeup-source;
- dmas = <&dmamux1 43 0x400 0x5>,
- <&dmamux1 44 0x400 0x1>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- i2s4: audio-controller@4c002000 {
- compatible = "st,stm32h7-i2s";
- reg = <0x4c002000 0x400>;
- #sound-dai-cells = <0>;
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 83 0x400 0x01>,
- <&dmamux1 84 0x400 0x01>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- spi4: spi@4c002000 {
- compatible = "st,stm32h7-spi";
- reg = <0x4c002000 0x400>;
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SPI4_K>;
- resets = <&rcc SPI4_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- dmas = <&dmamux1 83 0x400 0x01>,
- <&dmamux1 84 0x400 0x01>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- spi5: spi@4c003000 {
- compatible = "st,stm32h7-spi";
- reg = <0x4c003000 0x400>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SPI5_K>;
- resets = <&rcc SPI5_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- dmas = <&dmamux1 85 0x400 0x01>,
- <&dmamux1 86 0x400 0x01>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- i2c3: i2c@4c004000 {
- compatible = "st,stm32mp13-i2c";
- reg = <0x4c004000 0x400>;
- interrupt-names = "event", "error";
- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc I2C3_K>;
- resets = <&rcc I2C3_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- dmas = <&dmamux1 73 0x400 0x1>,
- <&dmamux1 74 0x400 0x1>;
- dma-names = "rx", "tx";
- st,syscfg-fmp = <&syscfg 0x4 0x4>;
- i2c-analog-filter;
- status = "disabled";
- };
-
- i2c4: i2c@4c005000 {
- compatible = "st,stm32mp13-i2c";
- reg = <0x4c005000 0x400>;
- interrupt-names = "event", "error";
- interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc I2C4_K>;
- resets = <&rcc I2C4_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- dmas = <&dmamux1 75 0x400 0x1>,
- <&dmamux1 76 0x400 0x1>;
- dma-names = "rx", "tx";
- st,syscfg-fmp = <&syscfg 0x4 0x8>;
- i2c-analog-filter;
- status = "disabled";
- };
-
- i2c5: i2c@4c006000 {
- compatible = "st,stm32mp13-i2c";
- reg = <0x4c006000 0x400>;
- interrupt-names = "event", "error";
- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc I2C5_K>;
- resets = <&rcc I2C5_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- dmas = <&dmamux1 115 0x400 0x1>,
- <&dmamux1 116 0x400 0x1>;
- dma-names = "rx", "tx";
- st,syscfg-fmp = <&syscfg 0x4 0x10>;
- i2c-analog-filter;
- status = "disabled";
- };
-
- timers12: timer@4c007000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x4c007000 0x400>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM12_K>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@11 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <11>;
- status = "disabled";
- };
- };
-
- timers13: timer@4c008000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x4c008000 0x400>;
- interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM13_K>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@12 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <12>;
- status = "disabled";
- };
- };
-
- timers14: timer@4c009000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x4c009000 0x400>;
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM14_K>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@13 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <13>;
- status = "disabled";
- };
- };
-
- timers15: timer@4c00a000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x4c00a000 0x400>;
- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM15_K>;
- clock-names = "int";
- dmas = <&dmamux1 105 0x400 0x1>,
- <&dmamux1 106 0x400 0x1>,
- <&dmamux1 107 0x400 0x1>,
- <&dmamux1 108 0x400 0x1>;
- dma-names = "ch1", "up", "trig", "com";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@14 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <14>;
- status = "disabled";
- };
- };
-
- timers16: timer@4c00b000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x4c00b000 0x400>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM16_K>;
- clock-names = "int";
- dmas = <&dmamux1 109 0x400 0x1>,
- <&dmamux1 110 0x400 0x1>;
- dma-names = "ch1", "up";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@15 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <15>;
- status = "disabled";
- };
- };
-
- timers17: timer@4c00c000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x4c00c000 0x400>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM17_K>;
- clock-names = "int";
- dmas = <&dmamux1 111 0x400 0x1>,
- <&dmamux1 112 0x400 0x1>;
- dma-names = "ch1", "up";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@16 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <16>;
- status = "disabled";
- };
- };
-
- rcc: rcc@50000000 {
- compatible = "st,stm32mp13-rcc", "syscon";
- reg = <0x50000000 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- clock-names = "hse", "hsi", "csi", "lse", "lsi";
- clocks = <&scmi_clk CK_SCMI_HSE>,
- <&scmi_clk CK_SCMI_HSI>,
- <&scmi_clk CK_SCMI_CSI>,
- <&scmi_clk CK_SCMI_LSE>,
- <&scmi_clk CK_SCMI_LSI>;
- };
-
- pwr_regulators: pwr@50001000 {
- compatible = "st,stm32mp1,pwr-reg";
- reg = <0x50001000 0x10>;
- status = "disabled";
-
- reg11: reg11 {
- regulator-name = "reg11";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- };
-
- reg18: reg18 {
- regulator-name = "reg18";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- usb33: usb33 {
- regulator-name = "usb33";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
- };
-
- exti: interrupt-controller@5000d000 {
- compatible = "st,stm32mp13-exti", "syscon";
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x5000d000 0x400>;
- };
-
- syscfg: syscon@50020000 {
- compatible = "st,stm32mp157-syscfg", "syscon";
- reg = <0x50020000 0x400>;
- clocks = <&rcc SYSCFG>;
- };
-
- lptimer2: timer@50021000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-lptimer";
- reg = <0x50021000 0x400>;
- interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc LPTIM2_K>;
- clock-names = "mux";
- wakeup-source;
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- trigger@1 {
- compatible = "st,stm32-lptimer-trigger";
- reg = <1>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-lptimer-counter";
- status = "disabled";
- };
-
- timer {
- compatible = "st,stm32-lptimer-timer";
- status = "disabled";
- };
- };
-
- lptimer3: timer@50022000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-lptimer";
- reg = <0x50022000 0x400>;
- interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc LPTIM3_K>;
- clock-names = "mux";
- wakeup-source;
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- trigger@2 {
- compatible = "st,stm32-lptimer-trigger";
- reg = <2>;
- status = "disabled";
- };
-
- timer {
- compatible = "st,stm32-lptimer-timer";
- status = "disabled";
- };
- };
-
- lptimer4: timer@50023000 {
- compatible = "st,stm32-lptimer";
- reg = <0x50023000 0x400>;
- interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc LPTIM4_K>;
- clock-names = "mux";
- wakeup-source;
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer {
- compatible = "st,stm32-lptimer-timer";
- status = "disabled";
- };
- };
-
- lptimer5: timer@50024000 {
- compatible = "st,stm32-lptimer";
- reg = <0x50024000 0x400>;
- interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc LPTIM5_K>;
- clock-names = "mux";
- wakeup-source;
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer {
- compatible = "st,stm32-lptimer-timer";
- status = "disabled";
- };
- };
-
- rng: rng@54004000 {
- compatible = "st,stm32mp13-rng";
- reg = <0x54004000 0x400>;
- clocks = <&rcc RNG1_K>;
- resets = <&rcc RNG1_R>;
- status = "disabled";
- };
-
- mdma: dma-controller@58000000 {
- compatible = "st,stm32h7-mdma";
- reg = <0x58000000 0x1000>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc MDMA>;
- #dma-cells = <5>;
- dma-channels = <32>;
- dma-requests = <48>;
- };
-
- fmc: memory-controller@58002000 {
- compatible = "st,stm32mp1-fmc2-ebi";
- reg = <0x58002000 0x1000>;
- ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
- <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
- <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
- <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
- <4 0 0x80000000 0x10000000>; /* NAND */
- #address-cells = <2>;
- #size-cells = <1>;
- clocks = <&rcc FMC_K>;
- resets = <&rcc FMC_R>;
- status = "disabled";
-
- nand-controller@4,0 {
- compatible = "st,stm32mp1-fmc2-nfc";
- reg = <4 0x00000000 0x1000>,
- <4 0x08010000 0x1000>,
- <4 0x08020000 0x1000>,
- <4 0x01000000 0x1000>,
- <4 0x09010000 0x1000>,
- <4 0x09020000 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>,
- <&mdma 24 0x2 0x12000a08 0x0 0x0>,
- <&mdma 25 0x2 0x12000a0a 0x0 0x0>;
- dma-names = "tx", "rx", "ecc";
- status = "disabled";
- };
- };
-
- qspi: spi@58003000 {
- compatible = "st,stm32f469-qspi";
- reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
- reg-names = "qspi", "qspi_mm";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>,
- <&mdma 26 0x2 0x10100008 0x0 0x0>;
- dma-names = "tx", "rx";
- clocks = <&rcc QSPI_K>;
- resets = <&rcc QSPI_R>;
- status = "disabled";
- };
-
- sdmmc1: mmc@58005000 {
- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x20253180>;
- reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SDMMC1_K>;
- clock-names = "apb_pclk";
- resets = <&rcc SDMMC1_R>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- max-frequency = <130000000>;
- status = "disabled";
- };
-
- sdmmc2: mmc@58007000 {
- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x20253180>;
- reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SDMMC2_K>;
- clock-names = "apb_pclk";
- resets = <&rcc SDMMC2_R>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- max-frequency = <130000000>;
- status = "disabled";
- };
-
- eth1: eth1@5800a000 {
- compatible = "snps,dwmac-4.20a", "st,stm32mp13-dwmac";
- reg = <0x5800a000 0x2000>;
- reg-names = "stmmaceth";
- interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
- <&exti 68 1>;
- interrupt-names = "macirq", "eth_wake_irq";
- clock-names = "stmmaceth",
- "mac-clk-tx",
- "mac-clk-rx",
- "ethstp",
- "eth-ck";
- clocks = <&rcc ETH1MAC>,
- <&rcc ETH1TX>,
- <&rcc ETH1RX>,
- <&rcc ETH1STP>,
- <&rcc ETH1CK_K>;
- st,syscon = <&syscfg 0x4 0xff0000>;
- snps,mixed-burst;
- snps,pbl = <2>;
- snps,axi-config = <&stmmac_axi_config_1>;
- snps,tso;
- status = "disabled";
-
- stmmac_axi_config_1: stmmac-axi-config {
- snps,wr_osr_lmt = <0x7>;
- snps,rd_osr_lmt = <0x7>;
- snps,blen = <0 0 0 0 16 8 4>;
- };
- };
-
- usbh_ohci: usb@5800c000 {
- compatible = "generic-ohci";
- reg = <0x5800c000 0x1000>;
- clocks = <&usbphyc>, <&rcc USBH>;
- resets = <&rcc USBH_R>;
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- usbh_ehci: usb@5800d000 {
- compatible = "generic-ehci";
- reg = <0x5800d000 0x1000>;
- clocks = <&usbphyc>, <&rcc USBH>;
- resets = <&rcc USBH_R>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
- companion = <&usbh_ohci>;
- status = "disabled";
- };
-
- iwdg2: watchdog@5a002000 {
- compatible = "st,stm32mp1-iwdg";
- reg = <0x5a002000 0x400>;
- clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
- clock-names = "pclk", "lsi";
- status = "disabled";
- };
-
- usbphyc: usbphyc@5a006000 {
- #address-cells = <1>;
- #size-cells = <0>;
- #clock-cells = <0>;
- compatible = "st,stm32mp1-usbphyc";
- reg = <0x5a006000 0x1000>;
- clocks = <&rcc USBPHY_K>;
- resets = <&rcc USBPHY_R>;
- vdda1v1-supply = <&scmi_reg11>;
- vdda1v8-supply = <&scmi_reg18>;
- status = "disabled";
-
- usbphyc_port0: usb-phy@0 {
- #phy-cells = <0>;
- reg = <0>;
- };
-
- usbphyc_port1: usb-phy@1 {
- #phy-cells = <1>;
- reg = <1>;
- };
- };
-
- rtc: rtc@5c004000 {
- compatible = "st,stm32mp1-rtc";
- reg = <0x5c004000 0x400>;
- interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&scmi_clk CK_SCMI_RTCAPB>,
- <&scmi_clk CK_SCMI_RTC>;
- clock-names = "pclk", "rtc_ck";
- status = "disabled";
- };
-
- bsec: efuse@5c005000 {
- compatible = "st,stm32mp13-bsec";
- reg = <0x5c005000 0x400>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- part_number_otp: part_number_otp@4 {
- reg = <0x4 0x2>;
- bits = <0 12>;
- };
- ts_cal1: calib@5c {
- reg = <0x5c 0x2>;
- };
- ts_cal2: calib@5e {
- reg = <0x5e 0x2>;
- };
- ethernet_mac1_address: mac1@e4 {
- reg = <0xe4 0x6>;
- };
- ethernet_mac2_address: mac2@ea {
- reg = <0xea 0x6>;
- };
- };
-
- /*
- * Break node order to solve dependency probe issue between
- * pinctrl and exti.
- */
- pinctrl: pinctrl@50002000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stm32mp135-pinctrl";
- ranges = <0 0x50002000 0x8400>;
- interrupt-parent = <&exti>;
- st,syscfg = <&exti 0x60 0xff>;
-
- gpioa: gpio@50002000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x0 0x400>;
- clocks = <&rcc GPIOA>;
- st,bank-name = "GPIOA";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@50003000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x400>;
- clocks = <&rcc GPIOB>;
- st,bank-name = "GPIOB";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@50004000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x400>;
- clocks = <&rcc GPIOC>;
- st,bank-name = "GPIOC";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@50005000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x3000 0x400>;
- clocks = <&rcc GPIOD>;
- st,bank-name = "GPIOD";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@50006000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x4000 0x400>;
- clocks = <&rcc GPIOE>;
- st,bank-name = "GPIOE";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@50007000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x5000 0x400>;
- clocks = <&rcc GPIOF>;
- st,bank-name = "GPIOF";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@50008000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x6000 0x400>;
- clocks = <&rcc GPIOG>;
- st,bank-name = "GPIOG";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@50009000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x7000 0x400>;
- clocks = <&rcc GPIOH>;
- st,bank-name = "GPIOH";
- ngpios = <15>;
- gpio-ranges = <&pinctrl 0 112 15>;
- };
-
- gpioi: gpio@5000a000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x8000 0x400>;
- clocks = <&rcc GPIOI>;
- st,bank-name = "GPIOI";
- ngpios = <8>;
- gpio-ranges = <&pinctrl 0 128 8>;
- };
- };
- };
-};
diff --git a/arch/arm/dts/stm32mp133.dtsi b/arch/arm/dts/stm32mp133.dtsi
deleted file mode 100644
index 5cd5bde..0000000
--- a/arch/arm/dts/stm32mp133.dtsi
+++ /dev/null
@@ -1,98 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-#include "stm32mp131.dtsi"
-
-/ {
- soc {
- m_can1: can@4400e000 {
- compatible = "bosch,m_can";
- reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
- reg-names = "m_can", "message_ram";
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
- clock-names = "hclk", "cclk";
- bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
- status = "disabled";
- };
-
- m_can2: can@4400f000 {
- compatible = "bosch,m_can";
- reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
- reg-names = "m_can", "message_ram";
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
- clock-names = "hclk", "cclk";
- bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
- status = "disabled";
- };
-
- adc_1: adc@48003000 {
- compatible = "st,stm32mp13-adc-core";
- reg = <0x48003000 0x400>;
- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc ADC1>, <&rcc ADC1_K>;
- clock-names = "bus", "adc";
- interrupt-controller;
- #interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- adc1: adc@0 {
- compatible = "st,stm32mp13-adc";
- #io-channel-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0>;
- interrupt-parent = <&adc_1>;
- interrupts = <0>;
- dmas = <&dmamux1 9 0x400 0x80000001>;
- dma-names = "rx";
- status = "disabled";
-
- channel@18 {
- reg = <18>;
- label = "vrefint";
- };
- };
- };
-
- eth2: eth2@5800e000 {
- compatible = "snps,dwmac-4.20a", "st,stm32mp13-dwmac";
- reg = <0x5800e000 0x2000>;
- reg-names = "stmmaceth";
- interrupts-extended = <&intc GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
- clock-names = "stmmaceth",
- "mac-clk-tx",
- "mac-clk-rx",
- "ethstp",
- "eth-ck";
- clocks = <&rcc ETH2MAC>,
- <&rcc ETH2TX>,
- <&rcc ETH2RX>,
- <&rcc ETH2STP>,
- <&rcc ETH2CK_K>;
- st,syscon = <&syscfg 0x4 0xff000000>;
- snps,mixed-burst;
- snps,pbl = <2>;
- snps,axi-config = <&stmmac_axi_config_2>;
- snps,tso;
- status = "disabled";
-
- stmmac_axi_config_2: stmmac-axi-config {
- snps,wr_osr_lmt = <0x7>;
- snps,rd_osr_lmt = <0x7>;
- snps,blen = <0 0 0 0 16 8 4>;
- };
- };
- };
-};
diff --git a/arch/arm/dts/stm32mp135.dtsi b/arch/arm/dts/stm32mp135.dtsi
deleted file mode 100644
index abf2acd..0000000
--- a/arch/arm/dts/stm32mp135.dtsi
+++ /dev/null
@@ -1,12 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-#include "stm32mp133.dtsi"
-
-/ {
- soc {
- };
-};
diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts
deleted file mode 100644
index 275823d..0000000
--- a/arch/arm/dts/stm32mp135f-dk.dts
+++ /dev/null
@@ -1,376 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pwm/pwm.h>
-#include <dt-bindings/regulator/st,stm32mp13-regulator.h>
-#include "stm32mp135.dtsi"
-#include "stm32mp13xf.dtsi"
-#include "stm32mp13-pinctrl.dtsi"
-
-/ {
- model = "STMicroelectronics STM32MP135F-DK Discovery Board";
- compatible = "st,stm32mp135f-dk", "st,stm32mp135";
-
- aliases {
- serial0 = &uart4;
- serial1 = &usart1;
- serial2 = &uart8;
- serial3 = &usart2;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@c0000000 {
- device_type = "memory";
- reg = <0xc0000000 0x20000000>;
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- optee@dd000000 {
- reg = <0xdd000000 0x3000000>;
- no-map;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- button-user {
- label = "User-PA13";
- linux,code = <BTN_1>;
- gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-blue {
- function = LED_FUNCTION_HEARTBEAT;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- default-state = "off";
- };
- };
-};
-
-&adc_1 {
- pinctrl-names = "default";
- pinctrl-0 = <&adc1_usb_cc_pins_a>;
- vdda-supply = <&scmi_vdd_adc>;
- vref-supply = <&scmi_vdd_adc>;
- status = "okay";
- adc1: adc@0 {
- status = "okay";
- /*
- * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in6 & in12.
- * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
- * 5 * (5.1 + 47kOhms) * 5pF => 1.3us.
- * Use arbitrary margin here (e.g. 5us).
- */
- channel@6 {
- reg = <6>;
- st,min-sample-time-ns = <5000>;
- };
- channel@12 {
- reg = <12>;
- st,min-sample-time-ns = <5000>;
- };
- };
-};
-
-&i2c1 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c1_pins_a>;
- pinctrl-1 = <&i2c1_sleep_pins_a>;
- i2c-scl-rising-time-ns = <96>;
- i2c-scl-falling-time-ns = <3>;
- clock-frequency = <1000000>;
- status = "okay";
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
-
- mcp23017: pinctrl@21 {
- compatible = "microchip,mcp23017";
- reg = <0x21>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpiog>;
- pinctrl-names = "default";
- pinctrl-0 = <&mcp23017_pins_a>;
- interrupt-controller;
- #interrupt-cells = <2>;
- microchip,irq-mirror;
- };
-
- typec@53 {
- compatible = "st,stm32g0-typec";
- reg = <0x53>;
- /* Alert pin on PI2 */
- interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
- interrupt-parent = <&gpioi>;
- /* Internal pull-up on PI2 */
- pinctrl-names = "default";
- pinctrl-0 = <&stm32g0_intn_pins_a>;
- firmware-name = "stm32g0-ucsi.mp135f-dk.fw";
- connector {
- compatible = "usb-c-connector";
- label = "USB-C";
-
- port {
- con_usb_c_g0_ep: endpoint {
- remote-endpoint = <&usbotg_hs_ep>;
- };
- };
- };
- };
-};
-
-&i2c5 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c5_pins_a>;
- pinctrl-1 = <&i2c5_sleep_pins_a>;
- i2c-scl-rising-time-ns = <170>;
- i2c-scl-falling-time-ns = <5>;
- clock-frequency = <400000>;
- status = "okay";
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
-};
-
-&iwdg2 {
- timeout-sec = <32>;
- status = "okay";
-};
-
-&rtc {
- status = "okay";
-};
-
-&scmi_regu {
- scmi_vdd_adc: regulator@10 {
- reg = <VOLTD_SCMI_STPMIC1_LDO1>;
- regulator-name = "vdd_adc";
- };
- scmi_vdd_usb: regulator@13 {
- reg = <VOLTD_SCMI_STPMIC1_LDO4>;
- regulator-name = "vdd_usb";
- };
- scmi_vdd_sd: regulator@14 {
- reg = <VOLTD_SCMI_STPMIC1_LDO5>;
- regulator-name = "vdd_sd";
- };
- scmi_v1v8_periph: regulator@15 {
- reg = <VOLTD_SCMI_STPMIC1_LDO6>;
- regulator-name = "v1v8_periph";
- };
- scmi_v3v3_sw: regulator@19 {
- reg = <VOLTD_SCMI_STPMIC1_PWR_SW2>;
- regulator-name = "v3v3_sw";
- };
-};
-
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
- cd-gpios = <&gpioh 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- disable-wp;
- st,neg-edge;
- bus-width = <4>;
- vmmc-supply = <&scmi_vdd_sd>;
- status = "okay";
-};
-
-&spi5 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&spi5_pins_a>;
- pinctrl-1 = <&spi5_sleep_pins_a>;
- status = "disabled";
-};
-
-&timers1 {
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
- pwm1: pwm {
- pinctrl-0 = <&pwm1_ch3n_pins_a>;
- pinctrl-1 = <&pwm1_ch3n_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
-};
-
-&timers3 {
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm3_pins_a>;
- pinctrl-1 = <&pwm3_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@2 {
- status = "okay";
- };
-};
-
-&timers4 {
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm4_pins_a>;
- pinctrl-1 = <&pwm4_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@3 {
- status = "okay";
- };
-};
-
-&timers8 {
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm8_pins_a>;
- pinctrl-1 = <&pwm8_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@7 {
- status = "okay";
- };
-};
-
-&timers14 {
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm14_pins_a>;
- pinctrl-1 = <&pwm14_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@13 {
- status = "okay";
- };
-};
-
-&uart4 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&uart4_pins_a>;
- pinctrl-1 = <&uart4_sleep_pins_a>;
- pinctrl-2 = <&uart4_idle_pins_a>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
-
-&uart8 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&uart8_pins_a>;
- pinctrl-1 = <&uart8_sleep_pins_a>;
- pinctrl-2 = <&uart8_idle_pins_a>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
-};
-
-&usart1 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&usart1_pins_a>;
- pinctrl-1 = <&usart1_sleep_pins_a>;
- pinctrl-2 = <&usart1_idle_pins_a>;
- uart-has-rtscts;
- status = "disabled";
-};
-
-/* Bluetooth */
-&usart2 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&usart2_pins_a>;
- pinctrl-1 = <&usart2_sleep_pins_a>;
- pinctrl-2 = <&usart2_idle_pins_a>;
- uart-has-rtscts;
- status = "okay";
-};
-
-&usbh_ehci {
- phys = <&usbphyc_port0>;
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
- /* onboard HUB */
- hub@1 {
- compatible = "usb424,2514";
- reg = <1>;
- vdd-supply = <&scmi_v3v3_sw>;
- };
-};
-
-&usbotg_hs {
- phys = <&usbphyc_port1 0>;
- phy-names = "usb2-phy";
- usb-role-switch;
- status = "okay";
- port {
- usbotg_hs_ep: endpoint {
- remote-endpoint = <&con_usb_c_g0_ep>;
- };
- };
-};
-
-&usbphyc {
- status = "okay";
-};
-
-&usbphyc_port0 {
- phy-supply = <&scmi_vdd_usb>;
- st,current-boost-microamp = <1000>;
- st,decrease-hs-slew-rate;
- st,tune-hs-dc-level = <2>;
- st,enable-hs-rftime-reduction;
- st,trim-hs-current = <11>;
- st,trim-hs-impedance = <2>;
- st,tune-squelch-level = <1>;
- st,enable-hs-rx-gain-eq;
- st,no-hs-ftime-ctrl;
- st,no-lsfs-sc;
-};
-
-&usbphyc_port1 {
- phy-supply = <&scmi_vdd_usb>;
- st,current-boost-microamp = <1000>;
- st,decrease-hs-slew-rate;
- st,tune-hs-dc-level = <2>;
- st,enable-hs-rftime-reduction;
- st,trim-hs-current = <11>;
- st,trim-hs-impedance = <2>;
- st,tune-squelch-level = <1>;
- st,enable-hs-rx-gain-eq;
- st,no-hs-ftime-ctrl;
- st,no-lsfs-sc;
-};
diff --git a/arch/arm/dts/stm32mp13xc.dtsi b/arch/arm/dts/stm32mp13xc.dtsi
deleted file mode 100644
index 4d00e75..0000000
--- a/arch/arm/dts/stm32mp13xc.dtsi
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-/ {
- soc {
- cryp: crypto@54002000 {
- compatible = "st,stm32mp1-cryp";
- reg = <0x54002000 0x400>;
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc CRYP1>;
- resets = <&rcc CRYP1_R>;
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/dts/stm32mp13xf.dtsi b/arch/arm/dts/stm32mp13xf.dtsi
deleted file mode 100644
index 4d00e75..0000000
--- a/arch/arm/dts/stm32mp13xf.dtsi
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-/ {
- soc {
- cryp: crypto@54002000 {
- compatible = "st,stm32mp1-cryp";
- reg = <0x54002000 0x400>;
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc CRYP1>;
- resets = <&rcc CRYP1_R>;
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi
deleted file mode 100644
index 098153e..0000000
--- a/arch/arm/dts/stm32mp15-pinctrl.dtsi
+++ /dev/null
@@ -1,2826 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
- * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
- */
-#include <dt-bindings/pinctrl/stm32-pinfunc.h>
-
-&pinctrl {
- adc1_ain_pins_a: adc1-ain-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* ADC1_INP2 */
- <STM32_PINMUX('B', 1, ANALOG)>, /* ADC1_INP5 */
- <STM32_PINMUX('B', 0, ANALOG)>, /* ADC1_INP9 */
- <STM32_PINMUX('C', 0, ANALOG)>, /* ADC1_INP10 */
- <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1_INP13 */
- <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1_INP15 */
- };
- };
-
- adc1_in6_pins_a: adc1-in6-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
- };
- };
-
- adc12_ain_pins_a: adc12-ain-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */
- <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
- <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2 in2 */
- <STM32_PINMUX('F', 14, ANALOG)>; /* ADC2 in6 */
- };
- };
-
- adc12_ain_pins_b: adc12-ain-1 {
- pins {
- pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
- <STM32_PINMUX('F', 13, ANALOG)>; /* ADC2 in2 */
- };
- };
-
- adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */
- <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */
- };
- };
-
- cec_pins_a: cec-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 15, AF4)>;
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- cec_sleep_pins_a: cec-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
- };
- };
-
- cec_pins_b: cec-1 {
- pins {
- pinmux = <STM32_PINMUX('B', 6, AF5)>;
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- cec_sleep_pins_b: cec-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */
- };
- };
-
- dac_ch1_pins_a: dac-ch1-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
- };
- };
-
- dac_ch2_pins_a: dac-ch2-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
- };
- };
-
- dcmi_pins_a: dcmi-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
- <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
- <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
- <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */
- <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
- <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
- <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */
- <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
- <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
- <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */
- <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
- <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
- <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */
- <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */
- <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */
- bias-disable;
- };
- };
-
- dcmi_sleep_pins_a: dcmi-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
- <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
- <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
- <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
- <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
- <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
- <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */
- <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
- <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
- <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */
- <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
- <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
- <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */
- <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */
- <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */
- };
- };
-
- dcmi_pins_b: dcmi-1 {
- pins {
- pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */
- <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
- <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
- <STM32_PINMUX('C', 6, AF13)>,/* DCMI_D0 */
- <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
- <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
- <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */
- <STM32_PINMUX('E', 11, AF13)>,/* DCMI_D4 */
- <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */
- <STM32_PINMUX('E', 13, AF13)>,/* DCMI_D6 */
- <STM32_PINMUX('B', 9, AF13)>;/* DCMI_D7 */
- bias-disable;
- };
- };
-
- dcmi_sleep_pins_b: dcmi-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */
- <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
- <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
- <STM32_PINMUX('C', 6, ANALOG)>,/* DCMI_D0 */
- <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
- <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
- <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */
- <STM32_PINMUX('E', 11, ANALOG)>,/* DCMI_D4 */
- <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */
- <STM32_PINMUX('E', 13, ANALOG)>,/* DCMI_D6 */
- <STM32_PINMUX('B', 9, ANALOG)>;/* DCMI_D7 */
- };
- };
-
- dcmi_pins_c: dcmi-2 {
- pins {
- pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */
- <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
- <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
- <STM32_PINMUX('A', 9, AF13)>,/* DCMI_D0 */
- <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
- <STM32_PINMUX('E', 0, AF13)>,/* DCMI_D2 */
- <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */
- <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
- <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
- <STM32_PINMUX('I', 6, AF13)>,/* DCMI_D6 */
- <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
- <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
- <STM32_PINMUX('H', 7, AF13)>;/* DCMI_D9 */
- bias-pull-up;
- };
- };
-
- dcmi_sleep_pins_c: dcmi-sleep-2 {
- pins {
- pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */
- <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
- <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
- <STM32_PINMUX('A', 9, ANALOG)>,/* DCMI_D0 */
- <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
- <STM32_PINMUX('E', 0, ANALOG)>,/* DCMI_D2 */
- <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */
- <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
- <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
- <STM32_PINMUX('I', 6, ANALOG)>,/* DCMI_D6 */
- <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
- <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
- <STM32_PINMUX('H', 7, ANALOG)>;/* DCMI_D9 */
- };
- };
-
- ethernet0_rgmii_pins_a: rgmii-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
- <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins3 {
- pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
- <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
- bias-disable;
- };
- };
-
- ethernet0_rgmii_sleep_pins_a: rgmii-sleep-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
- <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
- <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
- <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
- <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
- };
- };
-
- ethernet0_rgmii_pins_b: rgmii-1 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
- <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins3 {
- pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
- <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
- bias-disable;
- };
- };
-
- ethernet0_rgmii_sleep_pins_b: rgmii-sleep-1 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
- <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
- <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
- <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('H', 7, ANALOG)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
- <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
- };
- };
-
- ethernet0_rgmii_pins_c: rgmii-2 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
- <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('B', 12, AF11)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('G', 11, AF11)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins3 {
- pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
- <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
- bias-disable;
- };
- };
-
- ethernet0_rgmii_sleep_pins_c: rgmii-sleep-2 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
- <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('B', 12, ANALOG)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
- <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
- <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
- <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
- };
- };
-
- ethernet0_rgmii_pins_d: rgmii-3 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
- <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins3 {
- pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
- <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
- bias-disable;
- };
- };
-
- ethernet0_rgmii_sleep_pins_d: rgmii-sleep-3 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
- <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
- <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
- <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
- <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
- };
- };
-
- ethernet0_rgmii_pins_e: rgmii-4 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('B', 11, AF11)>; /* ETH_RGMII_TX_CTL */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
- <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
- bias-disable;
- };
- };
-
- ethernet0_rgmii_sleep_pins_e: rgmii-sleep-4 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('H', 7, ANALOG)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
- <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
- };
- };
-
- ethernet0_rmii_pins_a: rmii-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
- <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
- <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
- <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */
- <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
- <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
- <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
- <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
- bias-disable;
- };
- };
-
- ethernet0_rmii_sleep_pins_a: rmii-sleep-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
- <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
- <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
- <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
- <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
- <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
- <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
- <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
- <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
- };
- };
-
- ethernet0_rmii_pins_b: rmii-1 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 5, AF0)>, /* ETH1_CLK */
- <STM32_PINMUX('C', 1, AF11)>, /* ETH1_MDC */
- <STM32_PINMUX('G', 13, AF11)>, /* ETH1_TXD0 */
- <STM32_PINMUX('G', 14, AF11)>; /* ETH1_TXD1 */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH1_MDIO */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins3 {
- pinmux = <STM32_PINMUX('A', 7, AF11)>, /* ETH1_CRS_DV */
- <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RXD0 */
- <STM32_PINMUX('C', 5, AF11)>; /* ETH1_RXD1 */
- bias-disable;
- };
- pins4 {
- pinmux = <STM32_PINMUX('B', 11, AF11)>; /* ETH1_TX_EN */
- };
- };
-
- ethernet0_rmii_sleep_pins_b: rmii-sleep-1 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
- <STM32_PINMUX('A', 7, ANALOG)>, /* ETH1_CRS_DV */
- <STM32_PINMUX('B', 5, ANALOG)>, /* ETH1_CLK */
- <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_TX_EN */
- <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
- <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RXD0 */
- <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RXD1 */
- <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_TXD0 */
- <STM32_PINMUX('G', 14, ANALOG)>; /* ETH1_TXD1 */
- };
- };
-
- ethernet0_rmii_pins_c: rmii-2 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
- <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
- <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
- <STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */
- <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
- <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
- <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
- <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
- bias-disable;
- };
- };
-
- ethernet0_rmii_sleep_pins_c: rmii-sleep-2 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
- <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
- <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
- <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
- <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
- <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
- <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
- <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
- <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
- };
- };
-
- fmc_pins_a: fmc-0 {
- pins1 {
- pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
- <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
- <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
- <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
- <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
- <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
- <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
- <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
- <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
- <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
- <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
- <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
- <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
- bias-pull-up;
- };
- };
-
- fmc_sleep_pins_a: fmc-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
- <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
- <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */
- <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */
- <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
- <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
- <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
- <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
- <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
- <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
- <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
- <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
- <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */
- <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */
- };
- };
-
- fmc_pins_b: fmc-1 {
- pins {
- pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
- <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
- <STM32_PINMUX('B', 7, AF12)>, /* FMC_NL */
- <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
- <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
- <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
- <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
- <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
- <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
- <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
- <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
- <STM32_PINMUX('E', 11, AF12)>, /* FMC_D8 */
- <STM32_PINMUX('E', 12, AF12)>, /* FMC_D9 */
- <STM32_PINMUX('E', 13, AF12)>, /* FMC_D10 */
- <STM32_PINMUX('E', 14, AF12)>, /* FMC_D11 */
- <STM32_PINMUX('E', 15, AF12)>, /* FMC_D12 */
- <STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */
- <STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */
- <STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */
- <STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */
- <STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */
- bias-disable;
- drive-push-pull;
- slew-rate = <3>;
- };
- };
-
- fmc_sleep_pins_b: fmc-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
- <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
- <STM32_PINMUX('B', 7, ANALOG)>, /* FMC_NL */
- <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
- <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
- <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
- <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
- <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
- <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
- <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
- <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
- <STM32_PINMUX('E', 11, ANALOG)>, /* FMC_D8 */
- <STM32_PINMUX('E', 12, ANALOG)>, /* FMC_D9 */
- <STM32_PINMUX('E', 13, ANALOG)>, /* FMC_D10 */
- <STM32_PINMUX('E', 14, ANALOG)>, /* FMC_D11 */
- <STM32_PINMUX('E', 15, ANALOG)>, /* FMC_D12 */
- <STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */
- <STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */
- <STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */
- <STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */
- <STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */
- };
- };
-
- i2c1_pins_a: i2c1-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
- <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c1_sleep_pins_a: i2c1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
- <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
- };
- };
-
- i2c1_pins_b: i2c1-1 {
- pins {
- pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */
- <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c1_sleep_pins_b: i2c1-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */
- <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
- };
- };
-
- i2c2_pins_a: i2c2-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
- <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c2_sleep_pins_a: i2c2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */
- <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
- };
- };
-
- i2c2_pins_b1: i2c2-1 {
- pins {
- pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c2_sleep_pins_b1: i2c2-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
- };
- };
-
- i2c2_pins_c: i2c2-2 {
- pins {
- pinmux = <STM32_PINMUX('F', 1, AF4)>, /* I2C2_SCL */
- <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c2_pins_sleep_c: i2c2-sleep-2 {
- pins {
- pinmux = <STM32_PINMUX('F', 1, ANALOG)>, /* I2C2_SCL */
- <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
- };
- };
-
- i2c5_pins_a: i2c5-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
- <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c5_sleep_pins_a: i2c5-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */
- <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */
-
- };
- };
-
- i2c5_pins_b: i2c5-1 {
- pins {
- pinmux = <STM32_PINMUX('D', 0, AF4)>, /* I2C5_SCL */
- <STM32_PINMUX('D', 1, AF4)>; /* I2C5_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c5_sleep_pins_b: i2c5-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('D', 0, ANALOG)>, /* I2C5_SCL */
- <STM32_PINMUX('D', 1, ANALOG)>; /* I2C5_SDA */
- };
- };
-
- i2s2_pins_a: i2s2-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */
- <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */
- <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- i2s2_sleep_pins_a: i2s2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */
- <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */
- <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */
- };
- };
-
- ltdc_pins_a: ltdc-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */
- <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
- <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
- <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */
- <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */
- <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */
- <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */
- <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
- <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */
- <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */
- <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
- <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
- <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */
- <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */
- <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
- <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */
- <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
- <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */
- <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */
- <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */
- <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
- <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
- <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
- <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
- <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */
- <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
- <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */
- <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- };
-
- ltdc_sleep_pins_a: ltdc-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
- <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
- <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
- <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */
- <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */
- <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */
- <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */
- <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
- <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */
- <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */
- <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
- <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
- <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */
- <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */
- <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
- <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */
- <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
- <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */
- <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */
- <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */
- <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
- <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
- <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
- <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
- <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */
- <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
- <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */
- <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */
- };
- };
-
- ltdc_pins_b: ltdc-1 {
- pins {
- pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
- <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
- <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
- <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */
- <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
- <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
- <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
- <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
- <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
- <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
- <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
- <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
- <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
- <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
- <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
- <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
- <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
- <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
- <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
- <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
- <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
- <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
- <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
- <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */
- <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
- <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
- <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
- <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- };
-
- ltdc_sleep_pins_b: ltdc-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
- <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */
- <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */
- <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */
- <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */
- <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */
- <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */
- <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */
- <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */
- <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */
- <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */
- <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */
- <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */
- <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */
- <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */
- <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */
- <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */
- <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */
- <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */
- <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */
- <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */
- <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */
- <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */
- <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */
- <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */
- <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */
- <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */
- <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */
- };
- };
-
- ltdc_pins_c: ltdc-2 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 1, AF9)>, /* LTDC_R6 */
- <STM32_PINMUX('B', 9, AF14)>, /* LTDC_B7 */
- <STM32_PINMUX('C', 0, AF14)>, /* LTDC_R5 */
- <STM32_PINMUX('D', 3, AF14)>, /* LTDC_G7 */
- <STM32_PINMUX('D', 6, AF14)>, /* LTDC_B2 */
- <STM32_PINMUX('D', 10, AF14)>, /* LTDC_B3 */
- <STM32_PINMUX('E', 11, AF14)>, /* LTDC_G3 */
- <STM32_PINMUX('E', 12, AF14)>, /* LTDC_B4 */
- <STM32_PINMUX('E', 13, AF14)>, /* LTDC_DE */
- <STM32_PINMUX('E', 15, AF14)>, /* LTDC_R7 */
- <STM32_PINMUX('H', 4, AF9)>, /* LTDC_G5 */
- <STM32_PINMUX('H', 8, AF14)>, /* LTDC_R2 */
- <STM32_PINMUX('H', 9, AF14)>, /* LTDC_R3 */
- <STM32_PINMUX('H', 10, AF14)>, /* LTDC_R4 */
- <STM32_PINMUX('H', 13, AF14)>, /* LTDC_G2 */
- <STM32_PINMUX('H', 15, AF14)>, /* LTDC_G4 */
- <STM32_PINMUX('I', 1, AF14)>, /* LTDC_G6 */
- <STM32_PINMUX('I', 5, AF14)>, /* LTDC_B5 */
- <STM32_PINMUX('I', 6, AF14)>, /* LTDC_B6 */
- <STM32_PINMUX('I', 9, AF14)>, /* LTDC_VSYNC */
- <STM32_PINMUX('I', 10, AF14)>; /* LTDC_HSYNC */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 14, AF14)>; /* LTDC_CLK */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- };
-
- ltdc_sleep_pins_c: ltdc-sleep-2 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 1, ANALOG)>, /* LTDC_R6 */
- <STM32_PINMUX('B', 9, ANALOG)>, /* LTDC_B7 */
- <STM32_PINMUX('C', 0, ANALOG)>, /* LTDC_R5 */
- <STM32_PINMUX('D', 3, ANALOG)>, /* LTDC_G7 */
- <STM32_PINMUX('D', 6, ANALOG)>, /* LTDC_B2 */
- <STM32_PINMUX('D', 10, ANALOG)>, /* LTDC_B3 */
- <STM32_PINMUX('E', 11, ANALOG)>, /* LTDC_G3 */
- <STM32_PINMUX('E', 12, ANALOG)>, /* LTDC_B4 */
- <STM32_PINMUX('E', 13, ANALOG)>, /* LTDC_DE */
- <STM32_PINMUX('E', 15, ANALOG)>, /* LTDC_R7 */
- <STM32_PINMUX('H', 4, ANALOG)>, /* LTDC_G5 */
- <STM32_PINMUX('H', 8, ANALOG)>, /* LTDC_R2 */
- <STM32_PINMUX('H', 9, ANALOG)>, /* LTDC_R3 */
- <STM32_PINMUX('H', 10, ANALOG)>, /* LTDC_R4 */
- <STM32_PINMUX('H', 13, ANALOG)>, /* LTDC_G2 */
- <STM32_PINMUX('H', 15, ANALOG)>, /* LTDC_G4 */
- <STM32_PINMUX('I', 1, ANALOG)>, /* LTDC_G6 */
- <STM32_PINMUX('I', 5, ANALOG)>, /* LTDC_B5 */
- <STM32_PINMUX('I', 6, ANALOG)>, /* LTDC_B6 */
- <STM32_PINMUX('I', 9, ANALOG)>, /* LTDC_VSYNC */
- <STM32_PINMUX('I', 10, ANALOG)>, /* LTDC_HSYNC */
- <STM32_PINMUX('E', 14, ANALOG)>; /* LTDC_CLK */
- };
- };
-
- ltdc_pins_d: ltdc-3 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 7, AF14)>; /* LCD_CLK */
- bias-disable;
- drive-push-pull;
- slew-rate = <3>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
- <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
- <STM32_PINMUX('E', 13, AF14)>, /* LCD_DE */
- <STM32_PINMUX('G', 13, AF14)>, /* LCD_R0 */
- <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */
- <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */
- <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
- <STM32_PINMUX('A', 5, AF14)>, /* LCD_R4 */
- <STM32_PINMUX('H', 11, AF14)>, /* LCD_R5 */
- <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
- <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
- <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */
- <STM32_PINMUX('B', 0, AF14)>, /* LCD_G1 */
- <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
- <STM32_PINMUX('E', 11, AF14)>, /* LCD_G3 */
- <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
- <STM32_PINMUX('H', 4, AF9)>, /* LCD_G5 */
- <STM32_PINMUX('I', 11, AF9)>, /* LCD_G6 */
- <STM32_PINMUX('G', 8, AF14)>, /* LCD_G7 */
- <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
- <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
- <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
- <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
- <STM32_PINMUX('E', 12, AF14)>, /* LCD_B4 */
- <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
- <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */
- <STM32_PINMUX('I', 7, AF14)>; /* LCD_B7 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- ltdc_sleep_pins_d: ltdc-sleep-3 {
- pins {
- pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
- <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
- <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
- <STM32_PINMUX('E', 13, ANALOG)>, /* LCD_DE */
- <STM32_PINMUX('G', 13, ANALOG)>, /* LCD_R0 */
- <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */
- <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */
- <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
- <STM32_PINMUX('A', 5, ANALOG)>, /* LCD_R4 */
- <STM32_PINMUX('H', 11, ANALOG)>, /* LCD_R5 */
- <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
- <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
- <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */
- <STM32_PINMUX('B', 0, ANALOG)>, /* LCD_G1 */
- <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
- <STM32_PINMUX('E', 11, ANALOG)>, /* LCD_G3 */
- <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
- <STM32_PINMUX('H', 4, ANALOG)>, /* LCD_G5 */
- <STM32_PINMUX('I', 11, ANALOG)>, /* LCD_G6 */
- <STM32_PINMUX('G', 8, ANALOG)>, /* LCD_G7 */
- <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
- <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
- <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
- <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
- <STM32_PINMUX('E', 12, ANALOG)>, /* LCD_B4 */
- <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
- <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */
- <STM32_PINMUX('I', 7, ANALOG)>; /* LCD_B7 */
- };
- };
-
- mco1_pins_a: mco1-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 13, AF2)>; /* MCO1 */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- };
-
- mco1_sleep_pins_a: mco1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* MCO1 */
- };
- };
-
- mco2_pins_a: mco2-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- mco2_sleep_pins_a: mco2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */
- };
- };
-
- m_can1_pins_a: m-can1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
- bias-disable;
- };
- };
-
- m_can1_sleep_pins_a: m_can1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
- <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
- };
- };
-
- m_can1_pins_b: m-can1-1 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */
- bias-disable;
- };
- };
-
- m_can1_sleep_pins_b: m_can1-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* CAN1_TX */
- <STM32_PINMUX('A', 11, ANALOG)>; /* CAN1_RX */
- };
- };
-
- m_can1_pins_c: m-can1-2 {
- pins1 {
- pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('H', 14, AF9)>; /* CAN1_RX */
- bias-disable;
- };
- };
-
- m_can1_sleep_pins_c: m_can1-sleep-2 {
- pins {
- pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
- <STM32_PINMUX('H', 14, ANALOG)>; /* CAN1_RX */
- };
- };
-
- m_can2_pins_a: m-can2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
- bias-disable;
- };
- };
-
- m_can2_sleep_pins_a: m_can2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 13, ANALOG)>, /* CAN2_TX */
- <STM32_PINMUX('B', 5, ANALOG)>; /* CAN2_RX */
- };
- };
-
- pwm1_pins_a: pwm1-0 {
- pins {
- pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */
- <STM32_PINMUX('E', 11, AF1)>, /* TIM1_CH2 */
- <STM32_PINMUX('E', 14, AF1)>; /* TIM1_CH4 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm1_sleep_pins_a: pwm1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */
- <STM32_PINMUX('E', 11, ANALOG)>, /* TIM1_CH2 */
- <STM32_PINMUX('E', 14, ANALOG)>; /* TIM1_CH4 */
- };
- };
-
- pwm1_pins_b: pwm1-1 {
- pins {
- pinmux = <STM32_PINMUX('E', 9, AF1)>; /* TIM1_CH1 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm1_sleep_pins_b: pwm1-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('E', 9, ANALOG)>; /* TIM1_CH1 */
- };
- };
-
- pwm1_pins_c: pwm1-2 {
- pins {
- pinmux = <STM32_PINMUX('E', 11, AF1)>; /* TIM1_CH2 */
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm1_sleep_pins_c: pwm1-sleep-2 {
- pins {
- pinmux = <STM32_PINMUX('E', 11, ANALOG)>; /* TIM1_CH2 */
- };
- };
-
- pwm2_pins_a: pwm2-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm2_sleep_pins_a: pwm2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* TIM2_CH4 */
- };
- };
-
- pwm3_pins_a: pwm3-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 7, AF2)>; /* TIM3_CH2 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm3_sleep_pins_a: pwm3-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* TIM3_CH2 */
- };
- };
-
- pwm3_pins_b: pwm3-1 {
- pins {
- pinmux = <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm3_sleep_pins_b: pwm3-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* TIM3_CH2 */
- };
- };
-
- pwm4_pins_a: pwm4-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */
- <STM32_PINMUX('D', 15, AF2)>; /* TIM4_CH4 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm4_sleep_pins_a: pwm4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */
- <STM32_PINMUX('D', 15, ANALOG)>; /* TIM4_CH4 */
- };
- };
-
- pwm4_pins_b: pwm4-1 {
- pins {
- pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm4_sleep_pins_b: pwm4-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
- };
- };
-
- pwm5_pins_a: pwm5-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 11, AF2)>; /* TIM5_CH2 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm5_sleep_pins_a: pwm5-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 11, ANALOG)>; /* TIM5_CH2 */
- };
- };
-
- pwm5_pins_b: pwm5-1 {
- pins {
- pinmux = <STM32_PINMUX('H', 11, AF2)>, /* TIM5_CH2 */
- <STM32_PINMUX('H', 12, AF2)>, /* TIM5_CH3 */
- <STM32_PINMUX('I', 0, AF2)>; /* TIM5_CH4 */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm5_sleep_pins_b: pwm5-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('H', 11, ANALOG)>, /* TIM5_CH2 */
- <STM32_PINMUX('H', 12, ANALOG)>, /* TIM5_CH3 */
- <STM32_PINMUX('I', 0, ANALOG)>; /* TIM5_CH4 */
- };
- };
-
- pwm8_pins_a: pwm8-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm8_sleep_pins_a: pwm8-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 2, ANALOG)>; /* TIM8_CH4 */
- };
- };
-
- pwm8_pins_b: pwm8-1 {
- pins {
- pinmux = <STM32_PINMUX('I', 5, AF3)>, /* TIM8_CH1 */
- <STM32_PINMUX('I', 6, AF3)>, /* TIM8_CH2 */
- <STM32_PINMUX('I', 7, AF3)>, /* TIM8_CH3 */
- <STM32_PINMUX('C', 9, AF3)>; /* TIM8_CH4 */
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm8_sleep_pins_b: pwm8-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* TIM8_CH1 */
- <STM32_PINMUX('I', 6, ANALOG)>, /* TIM8_CH2 */
- <STM32_PINMUX('I', 7, ANALOG)>, /* TIM8_CH3 */
- <STM32_PINMUX('C', 9, ANALOG)>; /* TIM8_CH4 */
- };
- };
-
- pwm12_pins_a: pwm12-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm12_sleep_pins_a: pwm12-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 6, ANALOG)>; /* TIM12_CH1 */
- };
- };
-
- qspi_clk_pins_a: qspi-clk-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
- bias-disable;
- drive-push-pull;
- slew-rate = <3>;
- };
- };
-
- qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
- };
- };
-
- qspi_bk1_pins_a: qspi-bk1-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
- <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
- <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
- <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- };
-
- qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
- <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
- <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
- <STM32_PINMUX('F', 6, ANALOG)>; /* QSPI_BK1_IO3 */
- };
- };
-
- qspi_bk2_pins_a: qspi-bk2-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
- <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
- <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
- <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- };
-
- qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
- <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
- <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
- <STM32_PINMUX('G', 7, ANALOG)>; /* QSPI_BK2_IO3 */
- };
- };
-
- qspi_cs1_pins_a: qspi-cs1-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
- bias-pull-up;
- drive-push-pull;
- slew-rate = <1>;
- };
- };
-
- qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
- };
- };
-
- qspi_cs2_pins_a: qspi-cs2-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
- bias-pull-up;
- drive-push-pull;
- slew-rate = <1>;
- };
- };
-
- qspi_cs2_sleep_pins_a: qspi-cs2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
- };
- };
-
- sai2a_pins_a: sai2a-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */
- <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
- <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
- <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */
- slew-rate = <0>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sai2a_sleep_pins_a: sai2a-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */
- <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
- <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
- <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */
- };
- };
-
- sai2a_pins_b: sai2a-1 {
- pins1 {
- pinmux = <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
- <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
- <STM32_PINMUX('D', 13, AF10)>; /* SAI2_SCK_A */
- slew-rate = <0>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sai2a_sleep_pins_b: sai2a-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
- <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
- <STM32_PINMUX('D', 13, ANALOG)>; /* SAI2_SCK_A */
- };
- };
-
- sai2a_pins_c: sai2a-2 {
- pins {
- pinmux = <STM32_PINMUX('D', 13, AF10)>, /* SAI2_SCK_A */
- <STM32_PINMUX('D', 11, AF10)>, /* SAI2_SD_A */
- <STM32_PINMUX('D', 12, AF10)>; /* SAI2_FS_A */
- slew-rate = <0>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sai2a_sleep_pins_c: sai2a-sleep-2 {
- pins {
- pinmux = <STM32_PINMUX('D', 13, ANALOG)>, /* SAI2_SCK_A */
- <STM32_PINMUX('D', 11, ANALOG)>, /* SAI2_SD_A */
- <STM32_PINMUX('D', 12, ANALOG)>; /* SAI2_FS_A */
- };
- };
-
- sai2b_pins_a: sai2b-0 {
- pins1 {
- pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */
- <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */
- <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */
- slew-rate = <0>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
- bias-disable;
- };
- };
-
- sai2b_sleep_pins_a: sai2b-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */
- <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */
- <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */
- <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */
- };
- };
-
- sai2b_pins_b: sai2b-1 {
- pins {
- pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
- bias-disable;
- };
- };
-
- sai2b_sleep_pins_b: sai2b-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
- };
- };
-
- sai2b_pins_c: sai2b-2 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
- bias-disable;
- };
- };
-
- sai2b_sleep_pins_c: sai2b-sleep-2 {
- pins {
- pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
- };
- };
-
- sai2b_pins_d: sai2b-3 {
- pins1 {
- pinmux = <STM32_PINMUX('H', 2, AF10)>, /* SAI2_SCK_B */
- <STM32_PINMUX('C', 0, AF8)>, /* SAI2_FS_B */
- <STM32_PINMUX('H', 3, AF10)>; /* SAI2_MCLK_B */
- slew-rate = <0>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
- bias-disable;
- };
- };
-
- sai2b_sleep_pins_d: sai2b-sleep-3 {
- pins1 {
- pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* SAI2_SCK_B */
- <STM32_PINMUX('C', 0, ANALOG)>, /* SAI2_FS_B */
- <STM32_PINMUX('H', 3, ANALOG)>, /* SAI2_MCLK_B */
- <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
- };
- };
-
- sai4a_pins_a: sai4a-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
- slew-rate = <0>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sai4a_sleep_pins_a: sai4a-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */
- };
- };
-
- sdmmc1_b4_pins_a: sdmmc1-b4-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
- <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
- slew-rate = <2>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
- slew-rate = <2>;
- drive-push-pull;
- bias-disable;
- };
- pins3 {
- pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
- slew-rate = <1>;
- drive-open-drain;
- bias-disable;
- };
- };
-
- sdmmc1_b4_init_pins_a: sdmmc1-b4-init-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
- <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
- <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
- };
- };
-
- sdmmc1_b4_pins_b: sdmmc1-b4-1 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
- <STM32_PINMUX('E', 6, AF8)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
- <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
- slew-rate = <2>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sdmmc1_b4_od_pins_b: sdmmc1-b4-od-1 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
- <STM32_PINMUX('E', 6, AF8)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
- slew-rate = <2>;
- drive-push-pull;
- bias-disable;
- };
- pins3 {
- pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
- slew-rate = <1>;
- drive-open-drain;
- bias-disable;
- };
- };
-
- sdmmc1_b4_sleep_pins_b: sdmmc1-b4-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
- <STM32_PINMUX('E', 6, ANALOG)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
- <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
- <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
- };
- };
-
- sdmmc1_dir_pins_a: sdmmc1-dir-0 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
- <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
- <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
- bias-pull-up;
- };
- };
-
- sdmmc1_dir_init_pins_a: sdmmc1-dir-init-0 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
- <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
- <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- };
-
- sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
- <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
- <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
- <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
- };
- };
-
- sdmmc1_dir_pins_b: sdmmc1-dir-1 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
- <STM32_PINMUX('E', 14, AF11)>, /* SDMMC1_D123DIR */
- <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
- bias-pull-up;
- };
- };
-
- sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
- <STM32_PINMUX('E', 14, ANALOG)>, /* SDMMC1_D123DIR */
- <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
- <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
- };
- };
-
- sdmmc2_b4_pins_a: sdmmc2-b4-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
- <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
- <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
- <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
- <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
- slew-rate = <2>;
- drive-push-pull;
- bias-pull-up;
- };
- };
-
- sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
- <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
- <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
- <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
- slew-rate = <2>;
- drive-push-pull;
- bias-pull-up;
- };
- pins3 {
- pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
- slew-rate = <1>;
- drive-open-drain;
- bias-pull-up;
- };
- };
-
- sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
- <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
- <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
- <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
- <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
- <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
- };
- };
-
- sdmmc2_b4_pins_b: sdmmc2-b4-1 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
- <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
- <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
- <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
- <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
- slew-rate = <2>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
- <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
- <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
- <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
- slew-rate = <2>;
- drive-push-pull;
- bias-disable;
- };
- pins3 {
- pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
- slew-rate = <1>;
- drive-open-drain;
- bias-disable;
- };
- };
-
- sdmmc2_d47_pins_a: sdmmc2-d47-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
- <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
- <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
- <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- };
-
- sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
- <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
- <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */
- <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
- };
- };
-
- sdmmc2_d47_pins_b: sdmmc2-d47-1 {
- pins {
- pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
- <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
- <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
- <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
- <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
- <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
- <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
- };
- };
-
- sdmmc2_d47_pins_c: sdmmc2-d47-2 {
- pins {
- pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
- <STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */
- <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
- <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- };
-
- sdmmc2_d47_sleep_pins_c: sdmmc2-d47-sleep-2 {
- pins {
- pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
- <STM32_PINMUX('A', 15, ANALOG)>, /* SDMMC2_D5 */
- <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
- <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
- };
- };
-
- sdmmc2_d47_pins_d: sdmmc2-d47-3 {
- pins {
- pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
- <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
- <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
- <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
- };
- };
-
- sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 {
- pins {
- pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
- <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
- <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */
- <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
- };
- };
-
- sdmmc2_d47_pins_e: sdmmc2-d47-4 {
- pins {
- pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
- <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
- <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
- <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- };
-
- sdmmc2_d47_sleep_pins_e: sdmmc2-d47-sleep-4 {
- pins {
- pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
- <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
- <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
- <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
- };
- };
-
- sdmmc3_b4_pins_a: sdmmc3-b4-0 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
- <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
- <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
- <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
- <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- pins2 {
- pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
- slew-rate = <2>;
- drive-push-pull;
- bias-pull-up;
- };
- };
-
- sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
- <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
- <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
- <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- pins2 {
- pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
- slew-rate = <2>;
- drive-push-pull;
- bias-pull-up;
- };
- pins3 {
- pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */
- slew-rate = <1>;
- drive-open-drain;
- bias-pull-up;
- };
- };
-
- sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */
- <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */
- <STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */
- <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
- <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
- <STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */
- };
- };
-
- sdmmc3_b4_pins_b: sdmmc3-b4-1 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
- <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
- <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
- <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
- <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- pins2 {
- pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
- slew-rate = <2>;
- drive-push-pull;
- bias-pull-up;
- };
- };
-
- sdmmc3_b4_od_pins_b: sdmmc3-b4-od-1 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
- <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
- <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
- <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- pins2 {
- pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
- slew-rate = <2>;
- drive-push-pull;
- bias-pull-up;
- };
- pins3 {
- pinmux = <STM32_PINMUX('D', 0, AF10)>; /* SDMMC2_CMD */
- slew-rate = <1>;
- drive-open-drain;
- bias-pull-up;
- };
- };
-
- sdmmc3_b4_sleep_pins_b: sdmmc3-b4-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */
- <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */
- <STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */
- <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
- <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
- <STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */
- };
- };
-
- spdifrx_pins_a: spdifrx-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
- bias-disable;
- };
- };
-
- spdifrx_sleep_pins_a: spdifrx-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */
- };
- };
-
- spi1_pins_b: spi1-1 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */
- <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */
- bias-disable;
- };
- };
-
- spi2_pins_a: spi2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */
- <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */
- bias-disable;
- };
- };
-
- spi2_pins_b: spi2-1 {
- pins1 {
- pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI2_SCK */
- <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */
- bias-disable;
- };
- };
-
- spi2_pins_c: spi2-2 {
- pins1 {
- pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI2_SCK */
- <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */
- bias-disable;
- drive-push-pull;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */
- bias-pull-down;
- };
- };
-
- spi4_pins_a: spi4-0 {
- pins {
- pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
- <STM32_PINMUX('E', 6, AF5)>; /* SPI4_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */
- bias-disable;
- };
- };
-
- spi5_pins_a: spi5-0 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 7, AF5)>, /* SPI5_SCK */
- <STM32_PINMUX('F', 9, AF5)>; /* SPI5_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('F', 8, AF5)>; /* SPI5_MISO */
- bias-disable;
- };
- };
-
- stusb1600_pins_a: stusb1600-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 11, GPIO)>;
- bias-pull-up;
- };
- };
-
- uart4_pins_a: uart4-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- uart4_idle_pins_a: uart4-idle-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- uart4_sleep_pins_a: uart4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */
- <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
- };
- };
-
- uart4_pins_b: uart4-1 {
- pins1 {
- pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- uart4_pins_c: uart4-2 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- uart4_pins_d: uart4-3 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 13, AF8)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- uart4_idle_pins_d: uart4-idle-3 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* UART4_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- uart4_sleep_pins_d: uart4-sleep-3 {
- pins {
- pinmux = <STM32_PINMUX('A', 13, ANALOG)>, /* UART4_TX */
- <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
- };
- };
-
- uart5_pins_a: uart5-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 13, AF14)>; /* UART5_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 5, AF12)>; /* UART5_RX */
- bias-disable;
- };
- };
-
- uart7_pins_a: uart7-0 {
- pins1 {
- pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART7_RX */
- <STM32_PINMUX('E', 10, AF7)>, /* UART7_CTS */
- <STM32_PINMUX('E', 9, AF7)>; /* UART7_RTS */
- bias-disable;
- };
- };
-
- uart7_pins_b: uart7-1 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */
- bias-disable;
- };
- };
-
- uart7_pins_c: uart7-2 {
- pins1 {
- pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
- bias-pull-up;
- };
- };
-
- uart7_idle_pins_c: uart7-idle-2 {
- pins1 {
- pinmux = <STM32_PINMUX('E', 8, ANALOG)>; /* UART7_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
- bias-pull-up;
- };
- };
-
- uart7_sleep_pins_c: uart7-sleep-2 {
- pins {
- pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* UART7_TX */
- <STM32_PINMUX('E', 7, ANALOG)>; /* UART7_RX */
- };
- };
-
- uart8_pins_a: uart8-0 {
- pins1 {
- pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */
- bias-disable;
- };
- };
-
- uart8_rtscts_pins_a: uart8rtscts-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 7, AF8)>, /* UART8_RTS */
- <STM32_PINMUX('G', 10, AF8)>; /* UART8_CTS */
- bias-disable;
- };
- };
-
- usart1_pins_a: usart1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 12, AF7)>; /* USART1_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 11, AF7)>; /* USART1_CTS_NSS */
- bias-disable;
- };
- };
-
- usart1_idle_pins_a: usart1-idle-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* USART1_RTS */
- <STM32_PINMUX('A', 11, AF7)>; /* USART1_CTS_NSS */
- };
- };
-
- usart1_sleep_pins_a: usart1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* USART1_RTS */
- <STM32_PINMUX('A', 11, ANALOG)>; /* USART1_CTS_NSS */
- };
- };
-
- usart2_pins_a: usart2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
- <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
- <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */
- bias-disable;
- };
- };
-
- usart2_sleep_pins_a: usart2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */
- <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
- <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */
- <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
- };
- };
-
- usart2_pins_b: usart2-1 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
- <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('F', 4, AF7)>, /* USART2_RX */
- <STM32_PINMUX('E', 15, AF7)>; /* USART2_CTS_NSS */
- bias-disable;
- };
- };
-
- usart2_sleep_pins_b: usart2-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */
- <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */
- <STM32_PINMUX('F', 4, ANALOG)>, /* USART2_RX */
- <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */
- };
- };
-
- usart2_pins_c: usart2-2 {
- pins1 {
- pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */
- <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
- <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */
- bias-disable;
- };
- };
-
- usart2_idle_pins_c: usart2-idle-2 {
- pins1 {
- pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */
- <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins3 {
- pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
- bias-disable;
- };
- };
-
- usart2_sleep_pins_c: usart2-sleep-2 {
- pins {
- pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */
- <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
- <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */
- <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
- };
- };
-
- usart3_pins_a: usart3-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
- bias-disable;
- };
- };
-
- usart3_idle_pins_a: usart3-idle-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, ANALOG)>; /* USART3_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
- bias-disable;
- };
- };
-
- usart3_sleep_pins_a: usart3-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
- <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
- };
- };
-
- usart3_pins_b: usart3-1 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
- <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
- <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */
- bias-pull-up;
- };
- };
-
- usart3_idle_pins_b: usart3-idle-1 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
- <STM32_PINMUX('I', 10, ANALOG)>; /* USART3_CTS_NSS */
- };
- pins2 {
- pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins3 {
- pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
- bias-pull-up;
- };
- };
-
- usart3_sleep_pins_b: usart3-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
- <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
- <STM32_PINMUX('I', 10, ANALOG)>, /* USART3_CTS_NSS */
- <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
- };
- };
-
- usart3_pins_c: usart3-2 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
- <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
- <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
- bias-pull-up;
- };
- };
-
- usart3_idle_pins_c: usart3-idle-2 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
- <STM32_PINMUX('B', 13, ANALOG)>; /* USART3_CTS_NSS */
- };
- pins2 {
- pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins3 {
- pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
- bias-pull-up;
- };
- };
-
- usart3_sleep_pins_c: usart3-sleep-2 {
- pins {
- pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
- <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
- <STM32_PINMUX('B', 13, ANALOG)>, /* USART3_CTS_NSS */
- <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
- };
- };
-
- usart3_pins_d: usart3-3 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
- <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 9, AF7)>, /* USART3_RX */
- <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
- bias-disable;
- };
- };
-
- usart3_idle_pins_d: usart3-idle-3 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
- <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
- <STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 9, AF7)>; /* USART3_RX */
- bias-disable;
- };
- };
-
- usart3_sleep_pins_d: usart3-sleep-3 {
- pins {
- pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
- <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
- <STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */
- <STM32_PINMUX('D', 9, ANALOG)>; /* USART3_RX */
- };
- };
-
- usart3_pins_e: usart3-4 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
- <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 11, AF7)>, /* USART3_RX */
- <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
- bias-pull-up;
- };
- };
-
- usart3_idle_pins_e: usart3-idle-4 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
- <STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */
- };
- pins2 {
- pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins3 {
- pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
- bias-pull-up;
- };
- };
-
- usart3_sleep_pins_e: usart3-sleep-4 {
- pins {
- pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
- <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
- <STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */
- <STM32_PINMUX('B', 11, ANALOG)>; /* USART3_RX */
- };
- };
-
- usart3_pins_f: usart3-5 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
- <STM32_PINMUX('D', 12, AF7)>; /* USART3_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
- <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
- bias-disable;
- };
- };
-
- usbotg_hs_pins_a: usbotg-hs-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
- };
- };
-
- usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */
- <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */
- };
- };
-};
-
-&pinctrl_z {
- i2c2_pins_b2: i2c2-0 {
- pins {
- pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c2_sleep_pins_b2: i2c2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */
- };
- };
-
- i2c4_pins_a: i2c4-0 {
- pins {
- pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
- <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c4_sleep_pins_a: i2c4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
- <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
- };
- };
-
- i2c6_pins_a: i2c6-0 {
- pins {
- pinmux = <STM32_PINMUX('Z', 6, AF2)>, /* I2C6_SCL */
- <STM32_PINMUX('Z', 7, AF2)>; /* I2C6_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c6_sleep_pins_a: i2c6-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('Z', 6, ANALOG)>, /* I2C6_SCL */
- <STM32_PINMUX('Z', 7, ANALOG)>; /* I2C6_SDA */
- };
- };
-
- spi1_pins_a: spi1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
- <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
- bias-disable;
- };
- };
-
- spi1_sleep_pins_a: spi1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('Z', 0, ANALOG)>, /* SPI1_SCK */
- <STM32_PINMUX('Z', 1, ANALOG)>, /* SPI1_MISO */
- <STM32_PINMUX('Z', 2, ANALOG)>; /* SPI1_MOSI */
- };
- };
-
- usart1_pins_b: usart1-1 {
- pins1 {
- pinmux = <STM32_PINMUX('Z', 7, AF7)>; /* USART1_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('Z', 6, AF7)>; /* USART1_RX */
- bias-disable;
- };
- };
-
- usart1_idle_pins_b: usart1-idle-1 {
- pins1 {
- pinmux = <STM32_PINMUX('Z', 7, ANALOG)>; /* USART1_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('Z', 6, AF7)>; /* USART1_RX */
- bias-disable;
- };
- };
-
- usart1_sleep_pins_b: usart1-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('Z', 7, ANALOG)>, /* USART1_TX */
- <STM32_PINMUX('Z', 6, ANALOG)>; /* USART1_RX */
- };
- };
-};
diff --git a/arch/arm/dts/stm32mp15-scmi.dtsi b/arch/arm/dts/stm32mp15-scmi.dtsi
deleted file mode 100644
index dc3b09f..0000000
--- a/arch/arm/dts/stm32mp15-scmi.dtsi
+++ /dev/null
@@ -1,88 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-/ {
- firmware {
- optee: optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
-
- scmi: scmi {
- compatible = "linaro,scmi-optee";
- #address-cells = <1>;
- #size-cells = <0>;
- linaro,optee-channel-id = <0>;
-
- scmi_clk: protocol@14 {
- reg = <0x14>;
- #clock-cells = <1>;
- };
-
- scmi_reset: protocol@16 {
- reg = <0x16>;
- #reset-cells = <1>;
- };
-
- scmi_voltd: protocol@17 {
- reg = <0x17>;
-
- scmi_reguls: regulators {
- #address-cells = <1>;
- #size-cells = <0>;
-
- scmi_reg11: regulator@0 {
- reg = <0>;
- regulator-name = "reg11";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- };
-
- scmi_reg18: regulator@1 {
- reg = <1>;
- regulator-name = "reg18";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- scmi_usb33: regulator@2 {
- reg = <2>;
- regulator-name = "usb33";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
- };
- };
- };
- };
-};
-
-®11 {
- status = "disabled";
-};
-
-®18 {
- status = "disabled";
-};
-
-&usb33 {
- status = "disabled";
-};
-
-&usbotg_hs {
- usb33d-supply = <&scmi_usb33>;
-};
-
-&usbphyc {
- vdda1v1-supply = <&scmi_reg11>;
- vdda1v8-supply = <&scmi_reg18>;
-};
-
-/delete-node/ &clk_hse;
-/delete-node/ &clk_hsi;
-/delete-node/ &clk_lse;
-/delete-node/ &clk_lsi;
-/delete-node/ &clk_csi;
diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi
index 3f57bd5..327d776 100644
--- a/arch/arm/dts/stm32mp15-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15-u-boot.dtsi
@@ -106,6 +106,10 @@
operating-points-v2 = <&cpu0_opp_table>;
};
+&etzpc {
+ bootph-all;
+};
+
&gpioa {
bootph-all;
};
diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi
deleted file mode 100644
index e277140..0000000
--- a/arch/arm/dts/stm32mp151.dtsi
+++ /dev/null
@@ -1,1868 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
- * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
- */
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/stm32mp1-clks.h>
-#include <dt-bindings/reset/stm32mp1-resets.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- compatible = "arm,cortex-a7";
- clock-frequency = <650000000>;
- device_type = "cpu";
- reg = <0>;
- operating-points-v2 = <&cpu0_opp_table>;
- nvmem-cells = <&part_number_otp>;
- nvmem-cell-names = "part_number";
- };
- };
-
- cpu0_opp_table: cpu0-opp-table {
- compatible = "operating-points-v2";
- opp-shared;
- opp-650000000 {
- opp-hz = /bits/ 64 <650000000>;
- opp-microvolt = <1200000>;
- opp-supported-hw = <0x1>;
- };
- opp-800000000 {
- opp-hz = /bits/ 64 <800000000>;
- opp-microvolt = <1350000>;
- opp-supported-hw = <0x2>;
- };
- };
-
- arm-pmu {
- compatible = "arm,cortex-a7-pmu";
- interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>;
- interrupt-parent = <&intc>;
- };
-
- psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
-
- intc: interrupt-controller@a0021000 {
- compatible = "arm,cortex-a7-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0xa0021000 0x1000>,
- <0xa0022000 0x2000>;
- };
-
- timer {
- compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
- interrupt-parent = <&intc>;
- };
-
- clocks {
- clk_hse: clk-hse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- };
-
- clk_hsi: clk-hsi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <64000000>;
- };
-
- clk_lse: clk-lse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- clk_lsi: clk-lsi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32000>;
- };
-
- clk_csi: clk-csi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <4000000>;
- };
- };
-
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
- thermal-sensors = <&dts>;
-
- trips {
- cpu_alert1: cpu-alert1 {
- temperature = <85000>;
- hysteresis = <0>;
- type = "passive";
- };
-
- cpu-crit {
- temperature = <120000>;
- hysteresis = <0>;
- type = "critical";
- };
- };
-
- cooling-maps {
- };
- };
- };
-
- booster: regulator-booster {
- compatible = "st,stm32mp1-booster";
- st,syscfg = <&syscfg>;
- status = "disabled";
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&intc>;
- ranges;
-
- timers2: timer@40000000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000000 0x400>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM2_K>;
- clock-names = "int";
- dmas = <&dmamux1 18 0x400 0x1>,
- <&dmamux1 19 0x400 0x1>,
- <&dmamux1 20 0x400 0x1>,
- <&dmamux1 21 0x400 0x1>,
- <&dmamux1 22 0x400 0x1>;
- dma-names = "ch1", "ch2", "ch3", "ch4", "up";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@1 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <1>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-timer-counter";
- status = "disabled";
- };
- };
-
- timers3: timer@40001000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40001000 0x400>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM3_K>;
- clock-names = "int";
- dmas = <&dmamux1 23 0x400 0x1>,
- <&dmamux1 24 0x400 0x1>,
- <&dmamux1 25 0x400 0x1>,
- <&dmamux1 26 0x400 0x1>,
- <&dmamux1 27 0x400 0x1>,
- <&dmamux1 28 0x400 0x1>;
- dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@2 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <2>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-timer-counter";
- status = "disabled";
- };
- };
-
- timers4: timer@40002000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40002000 0x400>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM4_K>;
- clock-names = "int";
- dmas = <&dmamux1 29 0x400 0x1>,
- <&dmamux1 30 0x400 0x1>,
- <&dmamux1 31 0x400 0x1>,
- <&dmamux1 32 0x400 0x1>;
- dma-names = "ch1", "ch2", "ch3", "ch4";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@3 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <3>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-timer-counter";
- status = "disabled";
- };
- };
-
- timers5: timer@40003000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40003000 0x400>;
- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM5_K>;
- clock-names = "int";
- dmas = <&dmamux1 55 0x400 0x1>,
- <&dmamux1 56 0x400 0x1>,
- <&dmamux1 57 0x400 0x1>,
- <&dmamux1 58 0x400 0x1>,
- <&dmamux1 59 0x400 0x1>,
- <&dmamux1 60 0x400 0x1>;
- dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@4 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <4>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-timer-counter";
- status = "disabled";
- };
- };
-
- timers6: timer@40004000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40004000 0x400>;
- interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM6_K>;
- clock-names = "int";
- dmas = <&dmamux1 69 0x400 0x1>;
- dma-names = "up";
- status = "disabled";
-
- timer@5 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <5>;
- status = "disabled";
- };
- };
-
- timers7: timer@40005000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40005000 0x400>;
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM7_K>;
- clock-names = "int";
- dmas = <&dmamux1 70 0x400 0x1>;
- dma-names = "up";
- status = "disabled";
-
- timer@6 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <6>;
- status = "disabled";
- };
- };
-
- timers12: timer@40006000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40006000 0x400>;
- interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM12_K>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@11 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <11>;
- status = "disabled";
- };
- };
-
- timers13: timer@40007000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40007000 0x400>;
- interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM13_K>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@12 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <12>;
- status = "disabled";
- };
- };
-
- timers14: timer@40008000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40008000 0x400>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM14_K>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@13 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <13>;
- status = "disabled";
- };
- };
-
- lptimer1: timer@40009000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-lptimer";
- reg = <0x40009000 0x400>;
- interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc LPTIM1_K>;
- clock-names = "mux";
- wakeup-source;
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- trigger@0 {
- compatible = "st,stm32-lptimer-trigger";
- reg = <0>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-lptimer-counter";
- status = "disabled";
- };
- };
-
- spi2: spi@4000b000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x4000b000 0x400>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SPI2_K>;
- resets = <&rcc SPI2_R>;
- dmas = <&dmamux1 39 0x400 0x05>,
- <&dmamux1 40 0x400 0x05>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- i2s2: audio-controller@4000b000 {
- compatible = "st,stm32h7-i2s";
- #sound-dai-cells = <0>;
- reg = <0x4000b000 0x400>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 39 0x400 0x01>,
- <&dmamux1 40 0x400 0x01>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- spi3: spi@4000c000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x4000c000 0x400>;
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SPI3_K>;
- resets = <&rcc SPI3_R>;
- dmas = <&dmamux1 61 0x400 0x05>,
- <&dmamux1 62 0x400 0x05>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- i2s3: audio-controller@4000c000 {
- compatible = "st,stm32h7-i2s";
- #sound-dai-cells = <0>;
- reg = <0x4000c000 0x400>;
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 61 0x400 0x01>,
- <&dmamux1 62 0x400 0x01>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- spdifrx: audio-controller@4000d000 {
- compatible = "st,stm32h7-spdifrx";
- #sound-dai-cells = <0>;
- reg = <0x4000d000 0x400>;
- clocks = <&rcc SPDIF_K>;
- clock-names = "kclk";
- interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 93 0x400 0x01>,
- <&dmamux1 94 0x400 0x01>;
- dma-names = "rx", "rx-ctrl";
- status = "disabled";
- };
-
- usart2: serial@4000e000 {
- compatible = "st,stm32h7-uart";
- reg = <0x4000e000 0x400>;
- interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc USART2_K>;
- wakeup-source;
- dmas = <&dmamux1 43 0x400 0x15>,
- <&dmamux1 44 0x400 0x11>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- usart3: serial@4000f000 {
- compatible = "st,stm32h7-uart";
- reg = <0x4000f000 0x400>;
- interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc USART3_K>;
- wakeup-source;
- dmas = <&dmamux1 45 0x400 0x15>,
- <&dmamux1 46 0x400 0x11>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uart4: serial@40010000 {
- compatible = "st,stm32h7-uart";
- reg = <0x40010000 0x400>;
- interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc UART4_K>;
- wakeup-source;
- dmas = <&dmamux1 63 0x400 0x15>,
- <&dmamux1 64 0x400 0x11>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uart5: serial@40011000 {
- compatible = "st,stm32h7-uart";
- reg = <0x40011000 0x400>;
- interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc UART5_K>;
- wakeup-source;
- dmas = <&dmamux1 65 0x400 0x15>,
- <&dmamux1 66 0x400 0x11>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- i2c1: i2c@40012000 {
- compatible = "st,stm32mp15-i2c";
- reg = <0x40012000 0x400>;
- interrupt-names = "event", "error";
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc I2C1_K>;
- resets = <&rcc I2C1_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- st,syscfg-fmp = <&syscfg 0x4 0x1>;
- wakeup-source;
- i2c-analog-filter;
- status = "disabled";
- };
-
- i2c2: i2c@40013000 {
- compatible = "st,stm32mp15-i2c";
- reg = <0x40013000 0x400>;
- interrupt-names = "event", "error";
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc I2C2_K>;
- resets = <&rcc I2C2_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- st,syscfg-fmp = <&syscfg 0x4 0x2>;
- wakeup-source;
- i2c-analog-filter;
- status = "disabled";
- };
-
- i2c3: i2c@40014000 {
- compatible = "st,stm32mp15-i2c";
- reg = <0x40014000 0x400>;
- interrupt-names = "event", "error";
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc I2C3_K>;
- resets = <&rcc I2C3_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- st,syscfg-fmp = <&syscfg 0x4 0x4>;
- wakeup-source;
- i2c-analog-filter;
- status = "disabled";
- };
-
- i2c5: i2c@40015000 {
- compatible = "st,stm32mp15-i2c";
- reg = <0x40015000 0x400>;
- interrupt-names = "event", "error";
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc I2C5_K>;
- resets = <&rcc I2C5_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- st,syscfg-fmp = <&syscfg 0x4 0x10>;
- wakeup-source;
- i2c-analog-filter;
- status = "disabled";
- };
-
- cec: cec@40016000 {
- compatible = "st,stm32-cec";
- reg = <0x40016000 0x400>;
- interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc CEC_K>, <&rcc CEC>;
- clock-names = "cec", "hdmi-cec";
- status = "disabled";
- };
-
- dac: dac@40017000 {
- compatible = "st,stm32h7-dac-core";
- reg = <0x40017000 0x400>;
- clocks = <&rcc DAC12>;
- clock-names = "pclk";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- dac1: dac@1 {
- compatible = "st,stm32-dac";
- #io-channel-cells = <1>;
- reg = <1>;
- status = "disabled";
- };
-
- dac2: dac@2 {
- compatible = "st,stm32-dac";
- #io-channel-cells = <1>;
- reg = <2>;
- status = "disabled";
- };
- };
-
- uart7: serial@40018000 {
- compatible = "st,stm32h7-uart";
- reg = <0x40018000 0x400>;
- interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc UART7_K>;
- wakeup-source;
- dmas = <&dmamux1 79 0x400 0x15>,
- <&dmamux1 80 0x400 0x11>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uart8: serial@40019000 {
- compatible = "st,stm32h7-uart";
- reg = <0x40019000 0x400>;
- interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc UART8_K>;
- wakeup-source;
- dmas = <&dmamux1 81 0x400 0x15>,
- <&dmamux1 82 0x400 0x11>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- timers1: timer@44000000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x44000000 0x400>;
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "brk", "up", "trg-com", "cc";
- clocks = <&rcc TIM1_K>;
- clock-names = "int";
- dmas = <&dmamux1 11 0x400 0x1>,
- <&dmamux1 12 0x400 0x1>,
- <&dmamux1 13 0x400 0x1>,
- <&dmamux1 14 0x400 0x1>,
- <&dmamux1 15 0x400 0x1>,
- <&dmamux1 16 0x400 0x1>,
- <&dmamux1 17 0x400 0x1>;
- dma-names = "ch1", "ch2", "ch3", "ch4",
- "up", "trig", "com";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@0 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <0>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-timer-counter";
- status = "disabled";
- };
- };
-
- timers8: timer@44001000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x44001000 0x400>;
- interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "brk", "up", "trg-com", "cc";
- clocks = <&rcc TIM8_K>;
- clock-names = "int";
- dmas = <&dmamux1 47 0x400 0x1>,
- <&dmamux1 48 0x400 0x1>,
- <&dmamux1 49 0x400 0x1>,
- <&dmamux1 50 0x400 0x1>,
- <&dmamux1 51 0x400 0x1>,
- <&dmamux1 52 0x400 0x1>,
- <&dmamux1 53 0x400 0x1>;
- dma-names = "ch1", "ch2", "ch3", "ch4",
- "up", "trig", "com";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@7 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <7>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-timer-counter";
- status = "disabled";
- };
- };
-
- usart6: serial@44003000 {
- compatible = "st,stm32h7-uart";
- reg = <0x44003000 0x400>;
- interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc USART6_K>;
- wakeup-source;
- dmas = <&dmamux1 71 0x400 0x15>,
- <&dmamux1 72 0x400 0x11>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- spi1: spi@44004000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x44004000 0x400>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SPI1_K>;
- resets = <&rcc SPI1_R>;
- dmas = <&dmamux1 37 0x400 0x05>,
- <&dmamux1 38 0x400 0x05>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- i2s1: audio-controller@44004000 {
- compatible = "st,stm32h7-i2s";
- #sound-dai-cells = <0>;
- reg = <0x44004000 0x400>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 37 0x400 0x01>,
- <&dmamux1 38 0x400 0x01>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- spi4: spi@44005000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x44005000 0x400>;
- interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SPI4_K>;
- resets = <&rcc SPI4_R>;
- dmas = <&dmamux1 83 0x400 0x05>,
- <&dmamux1 84 0x400 0x05>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- timers15: timer@44006000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x44006000 0x400>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM15_K>;
- clock-names = "int";
- dmas = <&dmamux1 105 0x400 0x1>,
- <&dmamux1 106 0x400 0x1>,
- <&dmamux1 107 0x400 0x1>,
- <&dmamux1 108 0x400 0x1>;
- dma-names = "ch1", "up", "trig", "com";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@14 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <14>;
- status = "disabled";
- };
- };
-
- timers16: timer@44007000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x44007000 0x400>;
- interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM16_K>;
- clock-names = "int";
- dmas = <&dmamux1 109 0x400 0x1>,
- <&dmamux1 110 0x400 0x1>;
- dma-names = "ch1", "up";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- timer@15 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <15>;
- status = "disabled";
- };
- };
-
- timers17: timer@44008000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x44008000 0x400>;
- interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM17_K>;
- clock-names = "int";
- dmas = <&dmamux1 111 0x400 0x1>,
- <&dmamux1 112 0x400 0x1>;
- dma-names = "ch1", "up";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@16 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <16>;
- status = "disabled";
- };
- };
-
- spi5: spi@44009000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x44009000 0x400>;
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SPI5_K>;
- resets = <&rcc SPI5_R>;
- dmas = <&dmamux1 85 0x400 0x05>,
- <&dmamux1 86 0x400 0x05>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- sai1: sai@4400a000 {
- compatible = "st,stm32h7-sai";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x4400a000 0x400>;
- reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
- interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&rcc SAI1_R>;
- status = "disabled";
-
- sai1a: audio-controller@4400a004 {
- #sound-dai-cells = <0>;
-
- compatible = "st,stm32-sai-sub-a";
- reg = <0x4 0x20>;
- clocks = <&rcc SAI1_K>;
- clock-names = "sai_ck";
- dmas = <&dmamux1 87 0x400 0x01>;
- status = "disabled";
- };
-
- sai1b: audio-controller@4400a024 {
- #sound-dai-cells = <0>;
- compatible = "st,stm32-sai-sub-b";
- reg = <0x24 0x20>;
- clocks = <&rcc SAI1_K>;
- clock-names = "sai_ck";
- dmas = <&dmamux1 88 0x400 0x01>;
- status = "disabled";
- };
- };
-
- sai2: sai@4400b000 {
- compatible = "st,stm32h7-sai";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x4400b000 0x400>;
- reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&rcc SAI2_R>;
- status = "disabled";
-
- sai2a: audio-controller@4400b004 {
- #sound-dai-cells = <0>;
- compatible = "st,stm32-sai-sub-a";
- reg = <0x4 0x20>;
- clocks = <&rcc SAI2_K>;
- clock-names = "sai_ck";
- dmas = <&dmamux1 89 0x400 0x01>;
- status = "disabled";
- };
-
- sai2b: audio-controller@4400b024 {
- #sound-dai-cells = <0>;
- compatible = "st,stm32-sai-sub-b";
- reg = <0x24 0x20>;
- clocks = <&rcc SAI2_K>;
- clock-names = "sai_ck";
- dmas = <&dmamux1 90 0x400 0x01>;
- status = "disabled";
- };
- };
-
- sai3: sai@4400c000 {
- compatible = "st,stm32h7-sai";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x4400c000 0x400>;
- reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&rcc SAI3_R>;
- status = "disabled";
-
- sai3a: audio-controller@4400c004 {
- #sound-dai-cells = <0>;
- compatible = "st,stm32-sai-sub-a";
- reg = <0x04 0x20>;
- clocks = <&rcc SAI3_K>;
- clock-names = "sai_ck";
- dmas = <&dmamux1 113 0x400 0x01>;
- status = "disabled";
- };
-
- sai3b: audio-controller@4400c024 {
- #sound-dai-cells = <0>;
- compatible = "st,stm32-sai-sub-b";
- reg = <0x24 0x20>;
- clocks = <&rcc SAI3_K>;
- clock-names = "sai_ck";
- dmas = <&dmamux1 114 0x400 0x01>;
- status = "disabled";
- };
- };
-
- dfsdm: dfsdm@4400d000 {
- compatible = "st,stm32mp1-dfsdm";
- reg = <0x4400d000 0x800>;
- clocks = <&rcc DFSDM_K>;
- clock-names = "dfsdm";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- dfsdm0: filter@0 {
- compatible = "st,stm32-dfsdm-adc";
- #io-channel-cells = <1>;
- reg = <0>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 101 0x400 0x01>;
- dma-names = "rx";
- status = "disabled";
- };
-
- dfsdm1: filter@1 {
- compatible = "st,stm32-dfsdm-adc";
- #io-channel-cells = <1>;
- reg = <1>;
- interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 102 0x400 0x01>;
- dma-names = "rx";
- status = "disabled";
- };
-
- dfsdm2: filter@2 {
- compatible = "st,stm32-dfsdm-adc";
- #io-channel-cells = <1>;
- reg = <2>;
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 103 0x400 0x01>;
- dma-names = "rx";
- status = "disabled";
- };
-
- dfsdm3: filter@3 {
- compatible = "st,stm32-dfsdm-adc";
- #io-channel-cells = <1>;
- reg = <3>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 104 0x400 0x01>;
- dma-names = "rx";
- status = "disabled";
- };
-
- dfsdm4: filter@4 {
- compatible = "st,stm32-dfsdm-adc";
- #io-channel-cells = <1>;
- reg = <4>;
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 91 0x400 0x01>;
- dma-names = "rx";
- status = "disabled";
- };
-
- dfsdm5: filter@5 {
- compatible = "st,stm32-dfsdm-adc";
- #io-channel-cells = <1>;
- reg = <5>;
- interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 92 0x400 0x01>;
- dma-names = "rx";
- status = "disabled";
- };
- };
-
- dma1: dma-controller@48000000 {
- compatible = "st,stm32-dma";
- reg = <0x48000000 0x400>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc DMA1>;
- resets = <&rcc DMA1_R>;
- #dma-cells = <4>;
- st,mem2mem;
- dma-requests = <8>;
- };
-
- dma2: dma-controller@48001000 {
- compatible = "st,stm32-dma";
- reg = <0x48001000 0x400>;
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc DMA2>;
- resets = <&rcc DMA2_R>;
- #dma-cells = <4>;
- st,mem2mem;
- dma-requests = <8>;
- };
-
- dmamux1: dma-router@48002000 {
- compatible = "st,stm32h7-dmamux";
- reg = <0x48002000 0x40>;
- #dma-cells = <3>;
- dma-requests = <128>;
- dma-masters = <&dma1 &dma2>;
- dma-channels = <16>;
- clocks = <&rcc DMAMUX>;
- resets = <&rcc DMAMUX_R>;
- };
-
- adc: adc@48003000 {
- compatible = "st,stm32mp1-adc-core";
- reg = <0x48003000 0x400>;
- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc ADC12>, <&rcc ADC12_K>;
- clock-names = "bus", "adc";
- interrupt-controller;
- st,syscfg = <&syscfg>;
- #interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- adc1: adc@0 {
- compatible = "st,stm32mp1-adc";
- #io-channel-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0>;
- interrupt-parent = <&adc>;
- interrupts = <0>;
- dmas = <&dmamux1 9 0x400 0x01>;
- dma-names = "rx";
- status = "disabled";
- };
-
- adc2: adc@100 {
- compatible = "st,stm32mp1-adc";
- #io-channel-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x100>;
- interrupt-parent = <&adc>;
- interrupts = <1>;
- dmas = <&dmamux1 10 0x400 0x01>;
- dma-names = "rx";
- nvmem-cells = <&vrefint>;
- nvmem-cell-names = "vrefint";
- status = "disabled";
- channel@13 {
- reg = <13>;
- label = "vrefint";
- };
- channel@14 {
- reg = <14>;
- label = "vddcore";
- };
- };
- };
-
- sdmmc3: mmc@48004000 {
- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x00253180>;
- reg = <0x48004000 0x400>;
- interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SDMMC3_K>;
- clock-names = "apb_pclk";
- resets = <&rcc SDMMC3_R>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- max-frequency = <120000000>;
- status = "disabled";
- };
-
- usbotg_hs: usb-otg@49000000 {
- compatible = "st,stm32mp15-hsotg", "snps,dwc2";
- reg = <0x49000000 0x10000>;
- clocks = <&rcc USBO_K>, <&usbphyc>;
- clock-names = "otg", "utmi";
- resets = <&rcc USBO_R>;
- reset-names = "dwc2";
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- g-rx-fifo-size = <512>;
- g-np-tx-fifo-size = <32>;
- g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
- dr_mode = "otg";
- otg-rev = <0x200>;
- usb33d-supply = <&usb33>;
- status = "disabled";
- };
-
- ipcc: mailbox@4c001000 {
- compatible = "st,stm32mp1-ipcc";
- #mbox-cells = <1>;
- reg = <0x4c001000 0x400>;
- st,proc-id = <0>;
- interrupts-extended =
- <&exti 61 1>,
- <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "rx", "tx";
- clocks = <&rcc IPCC>;
- wakeup-source;
- status = "disabled";
- };
-
- dcmi: dcmi@4c006000 {
- compatible = "st,stm32-dcmi";
- reg = <0x4c006000 0x400>;
- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&rcc CAMITF_R>;
- clocks = <&rcc DCMI>;
- clock-names = "mclk";
- dmas = <&dmamux1 75 0x400 0x01>;
- dma-names = "tx";
- status = "disabled";
- };
-
- rcc: rcc@50000000 {
- compatible = "st,stm32mp1-rcc", "syscon";
- reg = <0x50000000 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
-
- clock-names = "hse", "hsi", "csi", "lse", "lsi";
- clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>,
- <&clk_lse>, <&clk_lsi>;
- };
-
- pwr_regulators: pwr@50001000 {
- compatible = "st,stm32mp1,pwr-reg";
- reg = <0x50001000 0x10>;
-
- reg11: reg11 {
- regulator-name = "reg11";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- };
-
- reg18: reg18 {
- regulator-name = "reg18";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- usb33: usb33 {
- regulator-name = "usb33";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
- };
-
- pwr_mcu: pwr_mcu@50001014 {
- compatible = "st,stm32mp151-pwr-mcu", "syscon";
- reg = <0x50001014 0x4>;
- };
-
- exti: interrupt-controller@5000d000 {
- compatible = "st,stm32mp1-exti", "syscon";
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x5000d000 0x400>;
- };
-
- syscfg: syscon@50020000 {
- compatible = "st,stm32mp157-syscfg", "syscon";
- reg = <0x50020000 0x400>;
- clocks = <&rcc SYSCFG>;
- };
-
- lptimer2: timer@50021000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-lptimer";
- reg = <0x50021000 0x400>;
- interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc LPTIM2_K>;
- clock-names = "mux";
- wakeup-source;
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- trigger@1 {
- compatible = "st,stm32-lptimer-trigger";
- reg = <1>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-lptimer-counter";
- status = "disabled";
- };
- };
-
- lptimer3: timer@50022000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-lptimer";
- reg = <0x50022000 0x400>;
- interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc LPTIM3_K>;
- clock-names = "mux";
- wakeup-source;
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- trigger@2 {
- compatible = "st,stm32-lptimer-trigger";
- reg = <2>;
- status = "disabled";
- };
- };
-
- lptimer4: timer@50023000 {
- compatible = "st,stm32-lptimer";
- reg = <0x50023000 0x400>;
- interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc LPTIM4_K>;
- clock-names = "mux";
- wakeup-source;
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- lptimer5: timer@50024000 {
- compatible = "st,stm32-lptimer";
- reg = <0x50024000 0x400>;
- interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc LPTIM5_K>;
- clock-names = "mux";
- wakeup-source;
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- vrefbuf: vrefbuf@50025000 {
- compatible = "st,stm32-vrefbuf";
- reg = <0x50025000 0x8>;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <2500000>;
- clocks = <&rcc VREF>;
- status = "disabled";
- };
-
- sai4: sai@50027000 {
- compatible = "st,stm32h7-sai";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x50027000 0x400>;
- reg = <0x50027000 0x4>, <0x500273f0 0x10>;
- interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&rcc SAI4_R>;
- status = "disabled";
-
- sai4a: audio-controller@50027004 {
- #sound-dai-cells = <0>;
- compatible = "st,stm32-sai-sub-a";
- reg = <0x04 0x20>;
- clocks = <&rcc SAI4_K>;
- clock-names = "sai_ck";
- dmas = <&dmamux1 99 0x400 0x01>;
- status = "disabled";
- };
-
- sai4b: audio-controller@50027024 {
- #sound-dai-cells = <0>;
- compatible = "st,stm32-sai-sub-b";
- reg = <0x24 0x20>;
- clocks = <&rcc SAI4_K>;
- clock-names = "sai_ck";
- dmas = <&dmamux1 100 0x400 0x01>;
- status = "disabled";
- };
- };
-
- dts: thermal@50028000 {
- compatible = "st,stm32-thermal";
- reg = <0x50028000 0x100>;
- interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc TMPSENS>;
- clock-names = "pclk";
- #thermal-sensor-cells = <0>;
- status = "disabled";
- };
-
- hash1: hash@54002000 {
- compatible = "st,stm32f756-hash";
- reg = <0x54002000 0x400>;
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc HASH1>;
- resets = <&rcc HASH1_R>;
- dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
- dma-names = "in";
- dma-maxburst = <2>;
- status = "disabled";
- };
-
- rng1: rng@54003000 {
- compatible = "st,stm32-rng";
- reg = <0x54003000 0x400>;
- clocks = <&rcc RNG1_K>;
- resets = <&rcc RNG1_R>;
- status = "disabled";
- };
-
- mdma1: dma-controller@58000000 {
- compatible = "st,stm32h7-mdma";
- reg = <0x58000000 0x1000>;
- interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc MDMA>;
- resets = <&rcc MDMA_R>;
- #dma-cells = <5>;
- dma-channels = <32>;
- dma-requests = <48>;
- };
-
- fmc: memory-controller@58002000 {
- #address-cells = <2>;
- #size-cells = <1>;
- compatible = "st,stm32mp1-fmc2-ebi";
- reg = <0x58002000 0x1000>;
- clocks = <&rcc FMC_K>;
- resets = <&rcc FMC_R>;
- status = "disabled";
-
- ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
- <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
- <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
- <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
- <4 0 0x80000000 0x10000000>; /* NAND */
-
- nand-controller@4,0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32mp1-fmc2-nfc";
- reg = <4 0x00000000 0x1000>,
- <4 0x08010000 0x1000>,
- <4 0x08020000 0x1000>,
- <4 0x01000000 0x1000>,
- <4 0x09010000 0x1000>,
- <4 0x09020000 0x1000>;
- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
- <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
- <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
- dma-names = "tx", "rx", "ecc";
- status = "disabled";
- };
- };
-
- qspi: spi@58003000 {
- compatible = "st,stm32f469-qspi";
- reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
- reg-names = "qspi", "qspi_mm";
- interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
- <&mdma1 22 0x2 0x10100008 0x0 0x0>;
- dma-names = "tx", "rx";
- clocks = <&rcc QSPI_K>;
- resets = <&rcc QSPI_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- sdmmc1: mmc@58005000 {
- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x00253180>;
- reg = <0x58005000 0x1000>;
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SDMMC1_K>;
- clock-names = "apb_pclk";
- resets = <&rcc SDMMC1_R>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- max-frequency = <120000000>;
- status = "disabled";
- };
-
- sdmmc2: mmc@58007000 {
- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x00253180>;
- reg = <0x58007000 0x1000>;
- interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SDMMC2_K>;
- clock-names = "apb_pclk";
- resets = <&rcc SDMMC2_R>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- max-frequency = <120000000>;
- status = "disabled";
- };
-
- crc1: crc@58009000 {
- compatible = "st,stm32f7-crc";
- reg = <0x58009000 0x400>;
- clocks = <&rcc CRC1>;
- status = "disabled";
- };
-
- ethernet0: ethernet@5800a000 {
- compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
- reg = <0x5800a000 0x2000>;
- reg-names = "stmmaceth";
- interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
- clock-names = "stmmaceth",
- "mac-clk-tx",
- "mac-clk-rx",
- "eth-ck",
- "ptp_ref",
- "ethstp";
- clocks = <&rcc ETHMAC>,
- <&rcc ETHTX>,
- <&rcc ETHRX>,
- <&rcc ETHCK_K>,
- <&rcc ETHPTP_K>,
- <&rcc ETHSTP>;
- st,syscon = <&syscfg 0x4>;
- snps,mixed-burst;
- snps,pbl = <2>;
- snps,en-tx-lpi-clockgating;
- snps,axi-config = <&stmmac_axi_config_0>;
- snps,tso;
- status = "disabled";
-
- stmmac_axi_config_0: stmmac-axi-config {
- snps,wr_osr_lmt = <0x7>;
- snps,rd_osr_lmt = <0x7>;
- snps,blen = <0 0 0 0 16 8 4>;
- };
- };
-
- usbh_ohci: usb@5800c000 {
- compatible = "generic-ohci";
- reg = <0x5800c000 0x1000>;
- clocks = <&usbphyc>, <&rcc USBH>;
- resets = <&rcc USBH_R>;
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- usbh_ehci: usb@5800d000 {
- compatible = "generic-ehci";
- reg = <0x5800d000 0x1000>;
- clocks = <&usbphyc>, <&rcc USBH>;
- resets = <&rcc USBH_R>;
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- companion = <&usbh_ohci>;
- status = "disabled";
- };
-
- ltdc: display-controller@5a001000 {
- compatible = "st,stm32-ltdc";
- reg = <0x5a001000 0x400>;
- interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc LTDC_PX>;
- clock-names = "lcd";
- resets = <&rcc LTDC_R>;
- status = "disabled";
- };
-
- iwdg2: watchdog@5a002000 {
- compatible = "st,stm32mp1-iwdg";
- reg = <0x5a002000 0x400>;
- clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
- clock-names = "pclk", "lsi";
- status = "disabled";
- };
-
- usbphyc: usbphyc@5a006000 {
- #address-cells = <1>;
- #size-cells = <0>;
- #clock-cells = <0>;
- compatible = "st,stm32mp1-usbphyc";
- reg = <0x5a006000 0x1000>;
- clocks = <&rcc USBPHY_K>;
- resets = <&rcc USBPHY_R>;
- vdda1v1-supply = <®11>;
- vdda1v8-supply = <®18>;
- status = "disabled";
-
- usbphyc_port0: usb-phy@0 {
- #phy-cells = <0>;
- reg = <0>;
- };
-
- usbphyc_port1: usb-phy@1 {
- #phy-cells = <1>;
- reg = <1>;
- };
- };
-
- usart1: serial@5c000000 {
- compatible = "st,stm32h7-uart";
- reg = <0x5c000000 0x400>;
- interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc USART1_K>;
- wakeup-source;
- status = "disabled";
- };
-
- spi6: spi@5c001000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x5c001000 0x400>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SPI6_K>;
- resets = <&rcc SPI6_R>;
- dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
- <&mdma1 35 0x0 0x40002 0x0 0x0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- i2c4: i2c@5c002000 {
- compatible = "st,stm32mp15-i2c";
- reg = <0x5c002000 0x400>;
- interrupt-names = "event", "error";
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc I2C4_K>;
- resets = <&rcc I2C4_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- st,syscfg-fmp = <&syscfg 0x4 0x8>;
- wakeup-source;
- i2c-analog-filter;
- status = "disabled";
- };
-
- rtc: rtc@5c004000 {
- compatible = "st,stm32mp1-rtc";
- reg = <0x5c004000 0x400>;
- clocks = <&rcc RTCAPB>, <&rcc RTC>;
- clock-names = "pclk", "rtc_ck";
- interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- bsec: efuse@5c005000 {
- compatible = "st,stm32mp15-bsec";
- reg = <0x5c005000 0x400>;
- #address-cells = <1>;
- #size-cells = <1>;
- part_number_otp: part-number-otp@4 {
- reg = <0x4 0x1>;
- };
- vrefint: vrefin-cal@52 {
- reg = <0x52 0x2>;
- };
- ts_cal1: calib@5c {
- reg = <0x5c 0x2>;
- };
- ts_cal2: calib@5e {
- reg = <0x5e 0x2>;
- };
- };
-
- i2c6: i2c@5c009000 {
- compatible = "st,stm32mp15-i2c";
- reg = <0x5c009000 0x400>;
- interrupt-names = "event", "error";
- interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc I2C6_K>;
- resets = <&rcc I2C6_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- st,syscfg-fmp = <&syscfg 0x4 0x20>;
- wakeup-source;
- i2c-analog-filter;
- status = "disabled";
- };
-
- tamp: tamp@5c00a000 {
- compatible = "st,stm32-tamp", "syscon", "simple-mfd";
- reg = <0x5c00a000 0x400>;
- };
-
- /*
- * Break node order to solve dependency probe issue between
- * pinctrl and exti.
- */
- pinctrl: pinctrl@50002000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stm32mp157-pinctrl";
- ranges = <0 0x50002000 0xa400>;
- interrupt-parent = <&exti>;
- st,syscfg = <&exti 0x60 0xff>;
-
- gpioa: gpio@50002000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x0 0x400>;
- clocks = <&rcc GPIOA>;
- st,bank-name = "GPIOA";
- status = "disabled";
- };
-
- gpiob: gpio@50003000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x400>;
- clocks = <&rcc GPIOB>;
- st,bank-name = "GPIOB";
- status = "disabled";
- };
-
- gpioc: gpio@50004000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x400>;
- clocks = <&rcc GPIOC>;
- st,bank-name = "GPIOC";
- status = "disabled";
- };
-
- gpiod: gpio@50005000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x3000 0x400>;
- clocks = <&rcc GPIOD>;
- st,bank-name = "GPIOD";
- status = "disabled";
- };
-
- gpioe: gpio@50006000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x4000 0x400>;
- clocks = <&rcc GPIOE>;
- st,bank-name = "GPIOE";
- status = "disabled";
- };
-
- gpiof: gpio@50007000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x5000 0x400>;
- clocks = <&rcc GPIOF>;
- st,bank-name = "GPIOF";
- status = "disabled";
- };
-
- gpiog: gpio@50008000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x6000 0x400>;
- clocks = <&rcc GPIOG>;
- st,bank-name = "GPIOG";
- status = "disabled";
- };
-
- gpioh: gpio@50009000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x7000 0x400>;
- clocks = <&rcc GPIOH>;
- st,bank-name = "GPIOH";
- status = "disabled";
- };
-
- gpioi: gpio@5000a000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x8000 0x400>;
- clocks = <&rcc GPIOI>;
- st,bank-name = "GPIOI";
- status = "disabled";
- };
-
- gpioj: gpio@5000b000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x9000 0x400>;
- clocks = <&rcc GPIOJ>;
- st,bank-name = "GPIOJ";
- status = "disabled";
- };
-
- gpiok: gpio@5000c000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0xa000 0x400>;
- clocks = <&rcc GPIOK>;
- st,bank-name = "GPIOK";
- status = "disabled";
- };
- };
-
- pinctrl_z: pinctrl@54004000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stm32mp157-z-pinctrl";
- ranges = <0 0x54004000 0x400>;
- interrupt-parent = <&exti>;
- st,syscfg = <&exti 0x60 0xff>;
-
- gpioz: gpio@54004000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0 0x400>;
- clocks = <&rcc GPIOZ>;
- st,bank-name = "GPIOZ";
- st,bank-ioport = <11>;
- status = "disabled";
- };
- };
- };
-
- mlahb: ahb {
- compatible = "st,mlahb", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- dma-ranges = <0x00000000 0x38000000 0x10000>,
- <0x10000000 0x10000000 0x60000>,
- <0x30000000 0x30000000 0x60000>;
-
- m4_rproc: m4@10000000 {
- compatible = "st,stm32mp1-m4";
- reg = <0x10000000 0x40000>,
- <0x30000000 0x40000>,
- <0x38000000 0x10000>;
- resets = <&rcc MCU_R>;
- reset-names = "mcu_rst";
- st,syscfg-holdboot = <&rcc 0x10C 0x1>;
- st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
- st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
- st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/dts/stm32mp153.dtsi b/arch/arm/dts/stm32mp153.dtsi
deleted file mode 100644
index 486084e..0000000
--- a/arch/arm/dts/stm32mp153.dtsi
+++ /dev/null
@@ -1,59 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-#include "stm32mp151.dtsi"
-
-/ {
- cpus {
- cpu1: cpu@1 {
- compatible = "arm,cortex-a7";
- clock-frequency = <650000000>;
- device_type = "cpu";
- reg = <1>;
- };
- };
-
- arm-pmu {
- interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>, <&cpu1>;
- };
-
- timer {
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- soc {
- m_can1: can@4400e000 {
- compatible = "bosch,m_can";
- reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
- reg-names = "m_can", "message_ram";
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
- clock-names = "hclk", "cclk";
- bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
- status = "disabled";
- };
-
- m_can2: can@4400f000 {
- compatible = "bosch,m_can";
- reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
- reg-names = "m_can", "message_ram";
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
- clock-names = "hclk", "cclk";
- bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/dts/stm32mp157.dtsi b/arch/arm/dts/stm32mp157.dtsi
deleted file mode 100644
index 6197d87..0000000
--- a/arch/arm/dts/stm32mp157.dtsi
+++ /dev/null
@@ -1,48 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-#include "stm32mp153.dtsi"
-
-/ {
- soc {
- gpu: gpu@59000000 {
- compatible = "vivante,gc";
- reg = <0x59000000 0x800>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc GPU>, <&rcc GPU_K>;
- clock-names = "bus" ,"core";
- resets = <&rcc GPU_R>;
- };
-
- dsi: dsi@5a000000 {
- compatible = "st,stm32-dsi";
- reg = <0x5a000000 0x800>;
- clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
- clock-names = "pclk", "ref", "px_clk";
- phy-dsi-supply = <®18>;
- resets = <&rcc DSI_R>;
- reset-names = "apb";
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- dsi_in: endpoint {
- };
- };
-
- port@1 {
- reg = <1>;
- dsi_out: endpoint {
- };
- };
- };
- };
- };
-};
diff --git a/arch/arm/dts/stm32mp157a-dk1-scmi.dts b/arch/arm/dts/stm32mp157a-dk1-scmi.dts
deleted file mode 100644
index afcd628..0000000
--- a/arch/arm/dts/stm32mp157a-dk1-scmi.dts
+++ /dev/null
@@ -1,82 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-/dts-v1/;
-
-#include "stm32mp157a-dk1.dts"
-#include "stm32mp15-scmi.dtsi"
-
-/ {
- model = "STMicroelectronics STM32MP157A-DK1 SCMI Discovery Board";
- compatible = "st,stm32mp157a-dk1-scmi", "st,stm32mp157a-dk1", "st,stm32mp157";
-
- reserved-memory {
- optee@de000000 {
- reg = <0xde000000 0x2000000>;
- no-map;
- };
- };
-};
-
-&cpu0 {
- clocks = <&scmi_clk CK_SCMI_MPU>;
-};
-
-&cpu1 {
- clocks = <&scmi_clk CK_SCMI_MPU>;
-};
-
-&dsi {
- clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
-};
-
-&gpioz {
- clocks = <&scmi_clk CK_SCMI_GPIOZ>;
-};
-
-&hash1 {
- clocks = <&scmi_clk CK_SCMI_HASH1>;
- resets = <&scmi_reset RST_SCMI_HASH1>;
-};
-
-&i2c4 {
- clocks = <&scmi_clk CK_SCMI_I2C4>;
- resets = <&scmi_reset RST_SCMI_I2C4>;
-};
-
-&iwdg2 {
- clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
-};
-
-&mdma1 {
- resets = <&scmi_reset RST_SCMI_MDMA>;
-};
-
-&m4_rproc {
- /delete-property/ st,syscfg-holdboot;
- resets = <&scmi_reset RST_SCMI_MCU>,
- <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
- reset-names = "mcu_rst", "hold_boot";
-};
-
-&rcc {
- compatible = "st,stm32mp1-rcc-secure", "syscon";
- clock-names = "hse", "hsi", "csi", "lse", "lsi";
- clocks = <&scmi_clk CK_SCMI_HSE>,
- <&scmi_clk CK_SCMI_HSI>,
- <&scmi_clk CK_SCMI_CSI>,
- <&scmi_clk CK_SCMI_LSE>,
- <&scmi_clk CK_SCMI_LSI>;
-};
-
-&rng1 {
- clocks = <&scmi_clk CK_SCMI_RNG1>;
- resets = <&scmi_reset RST_SCMI_RNG1>;
-};
-
-&rtc {
- clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
-};
diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts
deleted file mode 100644
index 0da3667..0000000
--- a/arch/arm/dts/stm32mp157a-dk1.dts
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-/dts-v1/;
-
-#include "stm32mp157.dtsi"
-#include "stm32mp15-pinctrl.dtsi"
-#include "stm32mp15xxac-pinctrl.dtsi"
-#include "stm32mp15xx-dkx.dtsi"
-
-/ {
- model = "STMicroelectronics STM32MP157A-DK1 Discovery Board";
- compatible = "st,stm32mp157a-dk1", "st,stm32mp157";
-
- aliases {
- ethernet0 = ðernet0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
diff --git a/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts b/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts
deleted file mode 100644
index 1f75f1d..0000000
--- a/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts
+++ /dev/null
@@ -1,49 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
- * Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutons(India)
- */
-
-/dts-v1/;
-#include "stm32mp157.dtsi"
-#include "stm32mp157a-icore-stm32mp1.dtsi"
-#include "stm32mp15-pinctrl.dtsi"
-#include "stm32mp15xxaa-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "Engicam i.Core STM32MP1 C.TOUCH 2.0";
- compatible = "engicam,icore-stm32mp1-ctouch2",
- "engicam,icore-stm32mp1", "st,stm32mp157";
-
- aliases {
- serial0 = &uart4;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&sdmmc1 {
- bus-width = <4>;
- disable-wp;
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
- st,neg-edge;
- vmmc-supply = <&v3v3>;
- status = "okay";
-};
-
-&uart4 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&uart4_pins_a>;
- pinctrl-1 = <&uart4_sleep_pins_a>;
- pinctrl-2 = <&uart4_idle_pins_a>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
deleted file mode 100644
index f4a4942..0000000
--- a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
+++ /dev/null
@@ -1,161 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
- * Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutons(India)
- */
-
-/dts-v1/;
-#include "stm32mp157.dtsi"
-#include "stm32mp157a-microgea-stm32mp1.dtsi"
-#include "stm32mp15-pinctrl.dtsi"
-#include "stm32mp15xxaa-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 7\" Open Frame";
- compatible = "engicam,microgea-stm32mp1-microdev2.0-of7",
- "engicam,microgea-stm32mp1", "st,stm32mp157";
-
- aliases {
- serial0 = &uart4;
- serial1 = &uart8;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- backlight: backlight {
- compatible = "gpio-backlight";
- gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>;
- default-on;
- };
-
- lcd_3v3: regulator-lcd-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "lcd_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpiof 10 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-always-on;
- power-supply = <&panel_pwr>;
- };
-
- panel_pwr: regulator-panel-pwr {
- compatible = "regulator-fixed";
- regulator-name = "panel_pwr";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpiob 10 GPIO_ACTIVE_HIGH>;
- regulator-always-on;
- };
-
- panel {
- compatible = "auo,b101aw03";
- backlight = <&backlight>;
- enable-gpios = <&gpiof 2 GPIO_ACTIVE_HIGH>;
- power-supply = <&lcd_3v3>;
-
- port {
- panel_in: endpoint {
- remote-endpoint = <<dc_ep0_out>;
- };
- };
- };
-};
-
-&i2c2 {
- i2c-scl-falling-time-ns = <20>;
- i2c-scl-rising-time-ns = <185>;
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c2_pins_a>;
- pinctrl-1 = <&i2c2_sleep_pins_a>;
- status = "okay";
-};
-
-<dc {
- pinctrl-names = "default";
- pinctrl-0 = <<dc_pins>;
- status = "okay";
-
- port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ltdc_ep0_out: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&panel_in>;
- };
- };
-};
-
-&pinctrl {
- ltdc_pins: ltdc-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 10, AF14)>, /* LTDC_B2 */
- <STM32_PINMUX('H', 12, AF14)>, /* LTDC_R6 */
- <STM32_PINMUX('H', 11, AF14)>, /* LTDC_R5 */
- <STM32_PINMUX('D', 10, AF14)>, /* LTDC_B3 */
- <STM32_PINMUX('D', 9, AF14)>, /* LTDC_B0 */
- <STM32_PINMUX('E', 5, AF14)>, /* LTDC_G0 */
- <STM32_PINMUX('E', 6, AF14)>, /* LTDC_G1 */
- <STM32_PINMUX('E', 13, AF14)>, /* LTDC_DE */
- <STM32_PINMUX('E', 15, AF14)>, /* LTDC_R7 */
- <STM32_PINMUX('G', 7, AF14)>, /* LTDC_CLK */
- <STM32_PINMUX('G', 12, AF14)>, /* LTDC_B1 */
- <STM32_PINMUX('H', 2, AF14)>, /* LTDC_R0 */
- <STM32_PINMUX('H', 3, AF14)>, /* LTDC_R1 */
- <STM32_PINMUX('H', 8, AF14)>, /* LTDC_R2 */
- <STM32_PINMUX('H', 9, AF14)>, /* LTDC_R3 */
- <STM32_PINMUX('H', 10, AF14)>, /* LTDC_R4 */
- <STM32_PINMUX('H', 13, AF14)>, /* LTDC_G2 */
- <STM32_PINMUX('H', 14, AF14)>, /* LTDC_G3 */
- <STM32_PINMUX('H', 15, AF14)>, /* LTDC_G4 */
- <STM32_PINMUX('I', 0, AF14)>, /* LTDC_G5 */
- <STM32_PINMUX('I', 1, AF14)>, /* LTDC_G6 */
- <STM32_PINMUX('I', 2, AF14)>, /* LTDC_G7 */
- <STM32_PINMUX('I', 4, AF14)>, /* LTDC_B4 */
- <STM32_PINMUX('I', 5, AF14)>, /* LTDC_B5 */
- <STM32_PINMUX('B', 8, AF14)>, /* LTDC_B6 */
- <STM32_PINMUX('I', 7, AF14)>, /* LTDC_B7 */
- <STM32_PINMUX('I', 9, AF14)>, /* LTDC_VSYNC */
- <STM32_PINMUX('I', 10, AF14)>; /* LTDC_HSYNC */
- bias-disable;
- drive-push-pull;
- slew-rate = <3>;
- };
- };
-};
-
-&sdmmc1 {
- bus-width = <4>;
- disable-wp;
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
- st,neg-edge;
- vmmc-supply = <&vdd>;
- status = "okay";
-};
-
-&uart4 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&uart4_pins_a>;
- pinctrl-1 = <&uart4_sleep_pins_a>;
- pinctrl-2 = <&uart4_idle_pins_a>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
-
-/* J31: RS323 */
-&uart8 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart8_pins_a>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
deleted file mode 100644
index b9d0d3d..0000000
--- a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
+++ /dev/null
@@ -1,59 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
- * Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutons(India)
- */
-
-/dts-v1/;
-#include "stm32mp157.dtsi"
-#include "stm32mp157a-microgea-stm32mp1.dtsi"
-#include "stm32mp15-pinctrl.dtsi"
-#include "stm32mp15xxaa-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 Carrier Board";
- compatible = "engicam,microgea-stm32mp1-microdev2.0",
- "engicam,microgea-stm32mp1", "st,stm32mp157";
-
- aliases {
- serial0 = &uart4;
- serial1 = &uart8;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&sdmmc1 {
- bus-width = <4>;
- disable-wp;
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
- st,neg-edge;
- vmmc-supply = <&vdd>;
- status = "okay";
-};
-
-&uart4 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&uart4_pins_a>;
- pinctrl-1 = <&uart4_sleep_pins_a>;
- pinctrl-2 = <&uart4_idle_pins_a>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
-
-/* J31: RS323 */
-&uart8 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart8_pins_a>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi b/arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi
deleted file mode 100644
index 0b85175..0000000
--- a/arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi
+++ /dev/null
@@ -1,148 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
- * Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutons(India)
- */
-
-/ {
- compatible = "engicam,microgea-stm32mp1", "st,stm32mp157";
-
- memory@c0000000 {
- device_type = "memory";
- reg = <0xc0000000 0x10000000>;
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- mcuram2: mcuram2@10000000 {
- compatible = "shared-dma-pool";
- reg = <0x10000000 0x40000>;
- no-map;
- };
-
- vdev0vring0: vdev0vring0@10040000 {
- compatible = "shared-dma-pool";
- reg = <0x10040000 0x1000>;
- no-map;
- };
-
- vdev0vring1: vdev0vring1@10041000 {
- compatible = "shared-dma-pool";
- reg = <0x10041000 0x1000>;
- no-map;
- };
-
- vdev0buffer: vdev0buffer@10042000 {
- compatible = "shared-dma-pool";
- reg = <0x10042000 0x4000>;
- no-map;
- };
-
- mcuram: mcuram@30000000 {
- compatible = "shared-dma-pool";
- reg = <0x30000000 0x40000>;
- no-map;
- };
-
- retram: retram@38000000 {
- compatible = "shared-dma-pool";
- reg = <0x38000000 0x10000>;
- no-map;
- };
- };
-
- vin: regulator-vin {
- compatible = "regulator-fixed";
- regulator-name = "vin";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- vddcore: regulator-vddcore {
- compatible = "regulator-fixed";
- regulator-name = "vddcore";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- vin-supply = <&vin>;
- };
-
- vdd: regulator-vdd {
- compatible = "regulator-fixed";
- regulator-name = "vdd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- vin-supply = <&vin>;
- };
-
- vddq_ddr: regulator-vddq-ddr {
- compatible = "regulator-fixed";
- regulator-name = "vddq_ddr";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- vin-supply = <&vin>;
- };
-};
-
-&dts {
- status = "okay";
-};
-
-&fmc {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&fmc_pins_a>;
- pinctrl-1 = <&fmc_sleep_pins_a>;
- status = "okay";
-
- nand-controller@4,0 {
- status = "okay";
-
- nand@0 {
- reg = <0>;
- nand-on-flash-bbt;
- #address-cells = <1>;
- #size-cells = <1>;
- };
- };
-};
-
-&ipcc {
- status = "okay";
-};
-
-&iwdg2{
- timeout-sec = <32>;
- status = "okay";
-};
-
-&m4_rproc{
- memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
- <&vdev0vring1>, <&vdev0buffer>;
- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
- mbox-names = "vq0", "vq1", "shutdown";
- interrupt-parent = <&exti>;
- interrupts = <68 1>;
- status = "okay";
-};
-
-&rng1 {
- status = "okay";
-};
-
-&rtc{
- status = "okay";
-};
-
-&vrefbuf {
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <2500000>;
- vdda-supply = <&vdd>;
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp157c-dk2-scmi.dts b/arch/arm/dts/stm32mp157c-dk2-scmi.dts
deleted file mode 100644
index 39358d9..0000000
--- a/arch/arm/dts/stm32mp157c-dk2-scmi.dts
+++ /dev/null
@@ -1,88 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-/dts-v1/;
-
-#include "stm32mp157c-dk2.dts"
-#include "stm32mp15-scmi.dtsi"
-
-/ {
- model = "STMicroelectronics STM32MP157C-DK2 SCMI Discovery Board";
- compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157c-dk2", "st,stm32mp157";
-
- reserved-memory {
- optee@de000000 {
- reg = <0xde000000 0x2000000>;
- no-map;
- };
- };
-};
-
-&cpu0 {
- clocks = <&scmi_clk CK_SCMI_MPU>;
-};
-
-&cpu1 {
- clocks = <&scmi_clk CK_SCMI_MPU>;
-};
-
-&cryp1 {
- clocks = <&scmi_clk CK_SCMI_CRYP1>;
- resets = <&scmi_reset RST_SCMI_CRYP1>;
-};
-
-&dsi {
- phy-dsi-supply = <&scmi_reg18>;
- clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
-};
-
-&gpioz {
- clocks = <&scmi_clk CK_SCMI_GPIOZ>;
-};
-
-&hash1 {
- clocks = <&scmi_clk CK_SCMI_HASH1>;
- resets = <&scmi_reset RST_SCMI_HASH1>;
-};
-
-&i2c4 {
- clocks = <&scmi_clk CK_SCMI_I2C4>;
- resets = <&scmi_reset RST_SCMI_I2C4>;
-};
-
-&iwdg2 {
- clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
-};
-
-&mdma1 {
- resets = <&scmi_reset RST_SCMI_MDMA>;
-};
-
-&m4_rproc {
- /delete-property/ st,syscfg-holdboot;
- resets = <&scmi_reset RST_SCMI_MCU>,
- <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
- reset-names = "mcu_rst", "hold_boot";
-};
-
-&rcc {
- compatible = "st,stm32mp1-rcc-secure", "syscon";
- clock-names = "hse", "hsi", "csi", "lse", "lsi";
- clocks = <&scmi_clk CK_SCMI_HSE>,
- <&scmi_clk CK_SCMI_HSI>,
- <&scmi_clk CK_SCMI_CSI>,
- <&scmi_clk CK_SCMI_LSE>,
- <&scmi_clk CK_SCMI_LSI>;
-};
-
-&rng1 {
- clocks = <&scmi_clk CK_SCMI_RNG1>;
- resets = <&scmi_reset RST_SCMI_RNG1>;
-};
-
-&rtc {
- clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
-};
diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts
deleted file mode 100644
index 510cca5..0000000
--- a/arch/arm/dts/stm32mp157c-dk2.dts
+++ /dev/null
@@ -1,94 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-/dts-v1/;
-
-#include "stm32mp157.dtsi"
-#include "stm32mp15xc.dtsi"
-#include "stm32mp15-pinctrl.dtsi"
-#include "stm32mp15xxac-pinctrl.dtsi"
-#include "stm32mp15xx-dkx.dtsi"
-
-/ {
- model = "STMicroelectronics STM32MP157C-DK2 Discovery Board";
- compatible = "st,stm32mp157c-dk2", "st,stm32mp157";
-
- aliases {
- ethernet0 = ðernet0;
- serial3 = &usart2;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&cryp1 {
- status = "okay";
-};
-
-&dsi {
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- panel@0 {
- compatible = "orisetech,otm8009a";
- reg = <0>;
- reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
- power-supply = <&v3v3>;
- status = "okay";
-
- port {
- panel_in: endpoint {
- remote-endpoint = <&dsi_out>;
- };
- };
- };
-};
-
-&dsi_in {
- remote-endpoint = <<dc_ep1_out>;
-};
-
-&dsi_out {
- remote-endpoint = <&panel_in>;
-};
-
-&i2c1 {
- touchscreen@38 {
- compatible = "focaltech,ft6236";
- reg = <0x38>;
- interrupts = <2 2>;
- interrupt-parent = <&gpiof>;
- interrupt-controller;
- touchscreen-size-x = <480>;
- touchscreen-size-y = <800>;
- status = "okay";
- };
-};
-
-<dc {
- status = "okay";
-
- port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ltdc_ep1_out: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&dsi_in>;
- };
- };
-};
-
-&usart2 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&usart2_pins_c>;
- pinctrl-1 = <&usart2_sleep_pins_c>;
- pinctrl-2 = <&usart2_idle_pins_c>;
- status = "disabled";
-};
diff --git a/arch/arm/dts/stm32mp157c-ed1-scmi.dts b/arch/arm/dts/stm32mp157c-ed1-scmi.dts
deleted file mode 100644
index 07ea765..0000000
--- a/arch/arm/dts/stm32mp157c-ed1-scmi.dts
+++ /dev/null
@@ -1,87 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-/dts-v1/;
-
-#include "stm32mp157c-ed1.dts"
-#include "stm32mp15-scmi.dtsi"
-
-/ {
- model = "STMicroelectronics STM32MP157C-ED1 SCMI eval daughter";
- compatible = "st,stm32mp157c-ed1-scmi", "st,stm32mp157c-ed1", "st,stm32mp157";
-
- reserved-memory {
- optee@fe000000 {
- reg = <0xfe000000 0x2000000>;
- no-map;
- };
- };
-};
-
-&cpu0 {
- clocks = <&scmi_clk CK_SCMI_MPU>;
-};
-
-&cpu1 {
- clocks = <&scmi_clk CK_SCMI_MPU>;
-};
-
-&cryp1 {
- clocks = <&scmi_clk CK_SCMI_CRYP1>;
- resets = <&scmi_reset RST_SCMI_CRYP1>;
-};
-
-&dsi {
- clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
-};
-
-&gpioz {
- clocks = <&scmi_clk CK_SCMI_GPIOZ>;
-};
-
-&hash1 {
- clocks = <&scmi_clk CK_SCMI_HASH1>;
- resets = <&scmi_reset RST_SCMI_HASH1>;
-};
-
-&i2c4 {
- clocks = <&scmi_clk CK_SCMI_I2C4>;
- resets = <&scmi_reset RST_SCMI_I2C4>;
-};
-
-&iwdg2 {
- clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
-};
-
-&mdma1 {
- resets = <&scmi_reset RST_SCMI_MDMA>;
-};
-
-&m4_rproc {
- /delete-property/ st,syscfg-holdboot;
- resets = <&scmi_reset RST_SCMI_MCU>,
- <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
- reset-names = "mcu_rst", "hold_boot";
-};
-
-&rcc {
- compatible = "st,stm32mp1-rcc-secure", "syscon";
- clock-names = "hse", "hsi", "csi", "lse", "lsi";
- clocks = <&scmi_clk CK_SCMI_HSE>,
- <&scmi_clk CK_SCMI_HSI>,
- <&scmi_clk CK_SCMI_CSI>,
- <&scmi_clk CK_SCMI_LSE>,
- <&scmi_clk CK_SCMI_LSI>;
-};
-
-&rng1 {
- clocks = <&scmi_clk CK_SCMI_RNG1>;
- resets = <&scmi_reset RST_SCMI_RNG1>;
-};
-
-&rtc {
- clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
-};
diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
deleted file mode 100644
index 66ed5f9..0000000
--- a/arch/arm/dts/stm32mp157c-ed1.dts
+++ /dev/null
@@ -1,403 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
- * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
- */
-/dts-v1/;
-
-#include "stm32mp157.dtsi"
-#include "stm32mp15xc.dtsi"
-#include "stm32mp15-pinctrl.dtsi"
-#include "stm32mp15xxaa-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/mfd/st,stpmic1.h>
-
-/ {
- model = "STMicroelectronics STM32MP157C eval daughter";
- compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
-
- aliases {
- serial0 = &uart4;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@c0000000 {
- device_type = "memory";
- reg = <0xC0000000 0x40000000>;
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- mcuram2: mcuram2@10000000 {
- compatible = "shared-dma-pool";
- reg = <0x10000000 0x40000>;
- no-map;
- };
-
- vdev0vring0: vdev0vring0@10040000 {
- compatible = "shared-dma-pool";
- reg = <0x10040000 0x1000>;
- no-map;
- };
-
- vdev0vring1: vdev0vring1@10041000 {
- compatible = "shared-dma-pool";
- reg = <0x10041000 0x1000>;
- no-map;
- };
-
- vdev0buffer: vdev0buffer@10042000 {
- compatible = "shared-dma-pool";
- reg = <0x10042000 0x4000>;
- no-map;
- };
-
- mcuram: mcuram@30000000 {
- compatible = "shared-dma-pool";
- reg = <0x30000000 0x40000>;
- no-map;
- };
-
- retram: retram@38000000 {
- compatible = "shared-dma-pool";
- reg = <0x38000000 0x10000>;
- no-map;
- };
- };
-
- sd_switch: regulator-sd_switch {
- compatible = "regulator-gpio";
- regulator-name = "sd_switch";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2900000>;
- regulator-type = "voltage";
- regulator-always-on;
-
- gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>;
- gpios-states = <0>;
- states = <1800000 0x1>,
- <2900000 0x0>;
- };
-
- vin: vin {
- compatible = "regulator-fixed";
- regulator-name = "vin";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-};
-
-&adc {
- /* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */
- pinctrl-0 = <&adc1_in6_pins_a>;
- pinctrl-names = "default";
- vdd-supply = <&vdd>;
- vdda-supply = <&vdda>;
- vref-supply = <&vdda>;
- status = "disabled";
- adc1: adc@0 {
- status = "okay";
- channel@0 {
- reg = <0>;
- /* 16.5 ck_cycles sampling time */
- st,min-sample-time-ns = <400>;
- };
- channel@1 {
- reg = <1>;
- st,min-sample-time-ns = <400>;
- };
- channel@6 {
- reg = <6>;
- st,min-sample-time-ns = <400>;
- };
- };
-};
-
-&crc1 {
- status = "okay";
-};
-
-&cryp1 {
- status = "okay";
-};
-
-&dac {
- pinctrl-names = "default";
- pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
- vref-supply = <&vdda>;
- status = "disabled";
- dac1: dac@1 {
- status = "okay";
- };
- dac2: dac@2 {
- status = "okay";
- };
-};
-
-&dts {
- status = "okay";
-};
-
-&hash1 {
- status = "okay";
-};
-
-&i2c4 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c4_pins_a>;
- pinctrl-1 = <&i2c4_sleep_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- clock-frequency = <400000>;
- status = "okay";
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
-
- pmic: stpmic@33 {
- compatible = "st,stpmic1";
- reg = <0x33>;
- interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <2>;
- status = "okay";
-
- regulators {
- compatible = "st,stpmic1-regulators";
- buck1-supply = <&vin>;
- buck2-supply = <&vin>;
- buck3-supply = <&vin>;
- buck4-supply = <&vin>;
- ldo1-supply = <&v3v3>;
- ldo2-supply = <&v3v3>;
- ldo3-supply = <&vdd_ddr>;
- ldo4-supply = <&vin>;
- ldo5-supply = <&v3v3>;
- ldo6-supply = <&v3v3>;
- vref_ddr-supply = <&vin>;
- boost-supply = <&vin>;
- pwr_sw1-supply = <&bst_out>;
- pwr_sw2-supply = <&bst_out>;
-
- vddcore: buck1 {
- regulator-name = "vddcore";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- vdd_ddr: buck2 {
- regulator-name = "vdd_ddr";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- vdd: buck3 {
- regulator-name = "vdd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- st,mask-reset;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- v3v3: buck4 {
- regulator-name = "v3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-over-current-protection;
- regulator-initial-mode = <0>;
- };
-
- vdda: ldo1 {
- regulator-name = "vdda";
- regulator-min-microvolt = <2900000>;
- regulator-max-microvolt = <2900000>;
- interrupts = <IT_CURLIM_LDO1 0>;
- };
-
- v2v8: ldo2 {
- regulator-name = "v2v8";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- interrupts = <IT_CURLIM_LDO2 0>;
- };
-
- vtt_ddr: ldo3 {
- regulator-name = "vtt_ddr";
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <750000>;
- regulator-always-on;
- regulator-over-current-protection;
- };
-
- vdd_usb: ldo4 {
- regulator-name = "vdd_usb";
- interrupts = <IT_CURLIM_LDO4 0>;
- };
-
- vdd_sd: ldo5 {
- regulator-name = "vdd_sd";
- regulator-min-microvolt = <2900000>;
- regulator-max-microvolt = <2900000>;
- interrupts = <IT_CURLIM_LDO5 0>;
- regulator-boot-on;
- };
-
- v1v8: ldo6 {
- regulator-name = "v1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- interrupts = <IT_CURLIM_LDO6 0>;
- };
-
- vref_ddr: vref_ddr {
- regulator-name = "vref_ddr";
- regulator-always-on;
- };
-
- bst_out: boost {
- regulator-name = "bst_out";
- interrupts = <IT_OCP_BOOST 0>;
- };
-
- vbus_otg: pwr_sw1 {
- regulator-name = "vbus_otg";
- interrupts = <IT_OCP_OTG 0>;
- };
-
- vbus_sw: pwr_sw2 {
- regulator-name = "vbus_sw";
- interrupts = <IT_OCP_SWOUT 0>;
- regulator-active-discharge = <1>;
- };
- };
-
- onkey {
- compatible = "st,stpmic1-onkey";
- interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
- interrupt-names = "onkey-falling", "onkey-rising";
- power-off-time-sec = <10>;
- status = "okay";
- };
-
- watchdog {
- compatible = "st,stpmic1-wdt";
- status = "disabled";
- };
- };
-};
-
-&ipcc {
- status = "okay";
-};
-
-&iwdg2 {
- timeout-sec = <32>;
- status = "okay";
-};
-
-&m4_rproc {
- memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
- <&vdev0vring1>, <&vdev0buffer>;
- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
- mbox-names = "vq0", "vq1", "shutdown", "detach";
- interrupt-parent = <&exti>;
- interrupts = <68 1>;
- status = "okay";
-};
-
-&pwr_regulators {
- vdd-supply = <&vdd>;
- vdd_3v3_usbfs-supply = <&vdd_usb>;
-};
-
-&rng1 {
- status = "okay";
-};
-
-&rtc {
- status = "okay";
-};
-
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
- cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- disable-wp;
- st,sig-dir;
- st,neg-edge;
- st,use-ckin;
- bus-width = <4>;
- vmmc-supply = <&vdd_sd>;
- vqmmc-supply = <&sd_switch>;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-ddr50;
- status = "okay";
-};
-
-&sdmmc2 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
- pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
- pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
- non-removable;
- no-sd;
- no-sdio;
- st,neg-edge;
- bus-width = <8>;
- vmmc-supply = <&v3v3>;
- vqmmc-supply = <&vdd>;
- mmc-ddr-3_3v;
- status = "okay";
-};
-
-&timers6 {
- status = "okay";
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
- timer@5 {
- status = "okay";
- };
-};
-
-&uart4 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&uart4_pins_a>;
- pinctrl-1 = <&uart4_sleep_pins_a>;
- pinctrl-2 = <&uart4_idle_pins_a>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
-
-&usbotg_hs {
- vbus-supply = <&vbus_otg>;
-};
-
-&usbphyc_port0 {
- phy-supply = <&vdd_usb>;
-};
-
-&usbphyc_port1 {
- phy-supply = <&vdd_usb>;
-};
diff --git a/arch/arm/dts/stm32mp157c-ev1-scmi.dts b/arch/arm/dts/stm32mp157c-ev1-scmi.dts
deleted file mode 100644
index 813086e..0000000
--- a/arch/arm/dts/stm32mp157c-ev1-scmi.dts
+++ /dev/null
@@ -1,93 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-/dts-v1/;
-
-#include "stm32mp157c-ev1.dts"
-#include "stm32mp15-scmi.dtsi"
-
-/ {
- model = "STMicroelectronics STM32MP157C-EV1 SCMI eval daughter on eval mother";
- compatible = "st,stm32mp157c-ev1-scmi", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1",
- "st,stm32mp157";
-
- reserved-memory {
- optee@fe000000 {
- reg = <0xfe000000 0x2000000>;
- no-map;
- };
- };
-};
-
-&cpu0 {
- clocks = <&scmi_clk CK_SCMI_MPU>;
-};
-
-&cpu1 {
- clocks = <&scmi_clk CK_SCMI_MPU>;
-};
-
-&cryp1 {
- clocks = <&scmi_clk CK_SCMI_CRYP1>;
- resets = <&scmi_reset RST_SCMI_CRYP1>;
-};
-
-&dsi {
- phy-dsi-supply = <&scmi_reg18>;
- clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
-};
-
-&gpioz {
- clocks = <&scmi_clk CK_SCMI_GPIOZ>;
-};
-
-&hash1 {
- clocks = <&scmi_clk CK_SCMI_HASH1>;
- resets = <&scmi_reset RST_SCMI_HASH1>;
-};
-
-&i2c4 {
- clocks = <&scmi_clk CK_SCMI_I2C4>;
- resets = <&scmi_reset RST_SCMI_I2C4>;
-};
-
-&iwdg2 {
- clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
-};
-
-&m_can1 {
- clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
-};
-
-&mdma1 {
- resets = <&scmi_reset RST_SCMI_MDMA>;
-};
-
-&m4_rproc {
- /delete-property/ st,syscfg-holdboot;
- resets = <&scmi_reset RST_SCMI_MCU>,
- <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
- reset-names = "mcu_rst", "hold_boot";
-};
-
-&rcc {
- compatible = "st,stm32mp1-rcc-secure", "syscon";
- clock-names = "hse", "hsi", "csi", "lse", "lsi";
- clocks = <&scmi_clk CK_SCMI_HSE>,
- <&scmi_clk CK_SCMI_HSI>,
- <&scmi_clk CK_SCMI_CSI>,
- <&scmi_clk CK_SCMI_LSE>,
- <&scmi_clk CK_SCMI_LSI>;
-};
-
-&rng1 {
- clocks = <&scmi_clk CK_SCMI_RNG1>;
- resets = <&scmi_reset RST_SCMI_RNG1>;
-};
-
-&rtc {
- clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
-};
diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts
deleted file mode 100644
index cd9c3ff..0000000
--- a/arch/arm/dts/stm32mp157c-ev1.dts
+++ /dev/null
@@ -1,414 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
- * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
- */
-/dts-v1/;
-
-#include "stm32mp157c-ed1.dts"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/media/video-interfaces.h>
-
-/ {
- model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
- compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
-
- aliases {
- serial1 = &usart3;
- ethernet0 = ðernet0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- clocks {
- clk_ext_camera: clk-ext-camera {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- };
- };
-
- joystick {
- compatible = "gpio-keys";
- pinctrl-0 = <&joystick_pins>;
- pinctrl-names = "default";
- button-0 {
- label = "JoySel";
- linux,code = <KEY_ENTER>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <0 IRQ_TYPE_EDGE_RISING>;
- };
- button-1 {
- label = "JoyDown";
- linux,code = <KEY_DOWN>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <1 IRQ_TYPE_EDGE_RISING>;
- };
- button-2 {
- label = "JoyLeft";
- linux,code = <KEY_LEFT>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <2 IRQ_TYPE_EDGE_RISING>;
- };
- button-3 {
- label = "JoyRight";
- linux,code = <KEY_RIGHT>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <3 IRQ_TYPE_EDGE_RISING>;
- };
- button-4 {
- label = "JoyUp";
- linux,code = <KEY_UP>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <4 IRQ_TYPE_EDGE_RISING>;
- };
- };
-
- panel_backlight: panel-backlight {
- compatible = "gpio-backlight";
- gpios = <&gpiod 13 GPIO_ACTIVE_LOW>;
- default-on;
- status = "okay";
- };
-};
-
-&cec {
- pinctrl-names = "default";
- pinctrl-0 = <&cec_pins_a>;
- status = "okay";
-};
-
-&dcmi {
- status = "okay";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&dcmi_pins_a>;
- pinctrl-1 = <&dcmi_sleep_pins_a>;
-
- port {
- dcmi_0: endpoint {
- remote-endpoint = <&ov5640_0>;
- bus-type = <MEDIA_BUS_TYPE_PARALLEL>;
- bus-width = <8>;
- hsync-active = <0>;
- vsync-active = <0>;
- pclk-sample = <1>;
- };
- };
-};
-
-&dsi {
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- panel@0 {
- compatible = "raydium,rm68200";
- reg = <0>;
- reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
- backlight = <&panel_backlight>;
- power-supply = <&v3v3>;
- status = "okay";
-
- port {
- dsi_panel_in: endpoint {
- remote-endpoint = <&dsi_out>;
- };
- };
- };
-};
-
-&dsi_in {
- remote-endpoint = <<dc_ep0_out>;
-};
-
-&dsi_out {
- remote-endpoint = <&dsi_panel_in>;
-};
-
-ðernet0 {
- status = "okay";
- pinctrl-0 = <ðernet0_rgmii_pins_a>;
- pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- phy-mode = "rgmii-id";
- max-speed = <1000>;
- phy-handle = <&phy0>;
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-};
-
-&fmc {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&fmc_pins_a>;
- pinctrl-1 = <&fmc_sleep_pins_a>;
- status = "okay";
-
- nand-controller@4,0 {
- status = "okay";
-
- nand@0 {
- reg = <0>;
- nand-on-flash-bbt;
- #address-cells = <1>;
- #size-cells = <1>;
- };
- };
-};
-
-&i2c2 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c2_pins_a>;
- pinctrl-1 = <&i2c2_sleep_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-
- ov5640: camera@3c {
- compatible = "ovti,ov5640";
- reg = <0x3c>;
- clocks = <&clk_ext_camera>;
- clock-names = "xclk";
- AVDD-supply = <&v2v8>;
- DOVDD-supply = <&v2v8>;
- DVDD-supply = <&v2v8>;
- powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>;
- reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
- rotation = <180>;
- status = "okay";
-
- port {
- ov5640_0: endpoint {
- remote-endpoint = <&dcmi_0>;
- bus-width = <8>;
- data-shift = <2>; /* lines 9:2 are used */
- hsync-active = <0>;
- vsync-active = <0>;
- pclk-sample = <1>;
- };
- };
- };
-
- stmfx: stmfx@42 {
- compatible = "st,stmfx-0300";
- reg = <0x42>;
- interrupts = <8 IRQ_TYPE_EDGE_RISING>;
- interrupt-parent = <&gpioi>;
- vdd-supply = <&v3v3>;
-
- stmfx_pinctrl: pinctrl {
- compatible = "st,stmfx-0300-pinctrl";
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-ranges = <&stmfx_pinctrl 0 0 24>;
-
- joystick_pins: joystick-pins {
- pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
- bias-pull-down;
- };
- };
- };
-};
-
-&i2c5 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c5_pins_a>;
- pinctrl-1 = <&i2c5_sleep_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-};
-
-<dc {
- status = "okay";
-
- port {
- ltdc_ep0_out: endpoint {
- remote-endpoint = <&dsi_in>;
- };
- };
-};
-
-&m_can1 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&m_can1_pins_a>;
- pinctrl-1 = <&m_can1_sleep_pins_a>;
- status = "okay";
-};
-
-&qspi {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&qspi_clk_pins_a
- &qspi_bk1_pins_a
- &qspi_cs1_pins_a
- &qspi_bk2_pins_a
- &qspi_cs2_pins_a>;
- pinctrl-1 = <&qspi_clk_sleep_pins_a
- &qspi_bk1_sleep_pins_a
- &qspi_cs1_sleep_pins_a
- &qspi_bk2_sleep_pins_a
- &qspi_cs2_sleep_pins_a>;
- reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- flash0: flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <108000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-
- flash1: flash@1 {
- compatible = "jedec,spi-nor";
- reg = <1>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <108000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-};
-
-&sdmmc3 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc3_b4_pins_a>;
- pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
- broken-cd;
- st,neg-edge;
- bus-width = <4>;
- vmmc-supply = <&v3v3>;
- status = "disabled";
-};
-
-&spi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi1_pins_a>;
- status = "disabled";
-};
-
-&timers2 {
- /* spare dmas for other usage (un-delete to enable pwm capture) */
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm2_pins_a>;
- pinctrl-1 = <&pwm2_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@1 {
- status = "okay";
- };
-};
-
-&timers8 {
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm8_pins_a>;
- pinctrl-1 = <&pwm8_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@7 {
- status = "okay";
- };
-};
-
-&timers12 {
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm12_pins_a>;
- pinctrl-1 = <&pwm12_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@11 {
- status = "okay";
- };
-};
-
-&usart3 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&usart3_pins_b>;
- pinctrl-1 = <&usart3_sleep_pins_b>;
- pinctrl-2 = <&usart3_idle_pins_b>;
- /*
- * HW flow control USART3_RTS is optional, and isn't default wired to
- * the connector. SB23 needs to be soldered in order to use it, and R77
- * (ETH_CLK) should be removed.
- */
- uart-has-rtscts;
- status = "disabled";
-};
-
-&usbh_ehci {
- phys = <&usbphyc_port0>;
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
- /* onboard HUB */
- hub@1 {
- compatible = "usb424,2514";
- reg = <1>;
- vdd-supply = <&v3v3>;
- };
-};
-
-&usbotg_hs {
- pinctrl-0 = <&usbotg_hs_pins_a>;
- pinctrl-names = "default";
- phys = <&usbphyc_port1 0>;
- phy-names = "usb2-phy";
- status = "okay";
-};
-
-&usbphyc {
- status = "okay";
-};
-
-&usbphyc_port0 {
- st,tune-hs-dc-level = <2>;
- st,enable-fs-rftime-tuning;
- st,enable-hs-rftime-reduction;
- st,trim-hs-current = <15>;
- st,trim-hs-impedance = <1>;
- st,tune-squelch-level = <3>;
- st,tune-hs-rx-offset = <2>;
- st,no-lsfs-sc;
-
- connector {
- compatible = "usb-a-connector";
- vbus-supply = <&vbus_sw>;
- };
-};
-
-&usbphyc_port1 {
- st,tune-hs-dc-level = <2>;
- st,enable-fs-rftime-tuning;
- st,enable-hs-rftime-reduction;
- st,trim-hs-current = <15>;
- st,trim-hs-impedance = <1>;
- st,tune-squelch-level = <3>;
- st,tune-hs-rx-offset = <2>;
- st,no-lsfs-sc;
-};
diff --git a/arch/arm/dts/stm32mp15xc.dtsi b/arch/arm/dts/stm32mp15xc.dtsi
deleted file mode 100644
index b06a55a..0000000
--- a/arch/arm/dts/stm32mp15xc.dtsi
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-/ {
- soc {
- cryp1: cryp@54001000 {
- compatible = "st,stm32mp1-cryp";
- reg = <0x54001000 0x400>;
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc CRYP1>;
- resets = <&rcc CRYP1_R>;
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi
deleted file mode 100644
index 511113f..0000000
--- a/arch/arm/dts/stm32mp15xx-dkx.dtsi
+++ /dev/null
@@ -1,741 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/mfd/st,stpmic1.h>
-
-/ {
- aliases {
- serial0 = &uart4;
- serial1 = &usart3;
- serial2 = &uart7;
- };
-
- memory@c0000000 {
- device_type = "memory";
- reg = <0xc0000000 0x20000000>;
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- mcuram2: mcuram2@10000000 {
- compatible = "shared-dma-pool";
- reg = <0x10000000 0x40000>;
- no-map;
- };
-
- vdev0vring0: vdev0vring0@10040000 {
- compatible = "shared-dma-pool";
- reg = <0x10040000 0x1000>;
- no-map;
- };
-
- vdev0vring1: vdev0vring1@10041000 {
- compatible = "shared-dma-pool";
- reg = <0x10041000 0x1000>;
- no-map;
- };
-
- vdev0buffer: vdev0buffer@10042000 {
- compatible = "shared-dma-pool";
- reg = <0x10042000 0x4000>;
- no-map;
- };
-
- mcuram: mcuram@30000000 {
- compatible = "shared-dma-pool";
- reg = <0x30000000 0x40000>;
- no-map;
- };
-
- retram: retram@38000000 {
- compatible = "shared-dma-pool";
- reg = <0x38000000 0x10000>;
- no-map;
- };
- };
-
- led {
- compatible = "gpio-leds";
- led-blue {
- label = "heartbeat";
- gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- default-state = "off";
- };
- };
-
- sound {
- compatible = "audio-graph-card";
- label = "STM32MP15-DK";
- routing =
- "Playback" , "MCLK",
- "Capture" , "MCLK",
- "MICL" , "Mic Bias";
- dais = <&sai2a_port &sai2b_port &i2s2_port>;
- status = "okay";
- };
-
- vin: vin {
- compatible = "regulator-fixed";
- regulator-name = "vin";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-};
-
-&adc {
- pinctrl-names = "default";
- pinctrl-0 = <&adc12_usb_cc_pins_a>;
- vdd-supply = <&vdd>;
- vdda-supply = <&vdd>;
- vref-supply = <&vrefbuf>;
- status = "okay";
- adc1: adc@0 {
- status = "okay";
- /*
- * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19.
- * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
- * 5 * (56 + 47kOhms) * 5pF => 2.5us.
- * Use arbitrary margin here (e.g. 5us).
- */
- channel@18 {
- reg = <18>;
- st,min-sample-time-ns = <5000>;
- };
- channel@19 {
- reg = <19>;
- st,min-sample-time-ns = <5000>;
- };
- };
- adc2: adc@100 {
- status = "okay";
- /* USB Type-C CC1 & CC2 */
- channel@18 {
- reg = <18>;
- st,min-sample-time-ns = <5000>;
- };
- channel@19 {
- reg = <19>;
- st,min-sample-time-ns = <5000>;
- };
- };
-};
-
-&cec {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&cec_pins_b>;
- pinctrl-1 = <&cec_sleep_pins_b>;
- status = "okay";
-};
-
-&crc1 {
- status = "okay";
-};
-
-&dts {
- status = "okay";
-};
-
-ðernet0 {
- status = "okay";
- pinctrl-0 = <ðernet0_rgmii_pins_a>;
- pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- phy-mode = "rgmii-id";
- max-speed = <1000>;
- phy-handle = <&phy0>;
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-};
-
-&hash1 {
- status = "okay";
-};
-
-&i2c1 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c1_pins_a>;
- pinctrl-1 = <&i2c1_sleep_pins_a>;
- i2c-scl-rising-time-ns = <100>;
- i2c-scl-falling-time-ns = <7>;
- status = "okay";
- /delete-property/dmas;
- /delete-property/dma-names;
-
- hdmi-transmitter@39 {
- compatible = "sil,sii9022";
- reg = <0x39>;
- iovcc-supply = <&v3v3_hdmi>;
- cvcc12-supply = <&v1v2_hdmi>;
- reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>;
- interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
- interrupt-parent = <&gpiog>;
- #sound-dai-cells = <0>;
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- sii9022_in: endpoint {
- remote-endpoint = <<dc_ep0_out>;
- };
- };
-
- port@3 {
- reg = <3>;
- sii9022_tx_endpoint: endpoint {
- remote-endpoint = <&i2s2_endpoint>;
- };
- };
- };
- };
-
- cs42l51: cs42l51@4a {
- compatible = "cirrus,cs42l51";
- reg = <0x4a>;
- #sound-dai-cells = <0>;
- VL-supply = <&v3v3>;
- VD-supply = <&v1v8_audio>;
- VA-supply = <&v1v8_audio>;
- VAHP-supply = <&v1v8_audio>;
- reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>;
- clocks = <&sai2a>;
- clock-names = "MCLK";
- status = "okay";
-
- cs42l51_port: port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cs42l51_tx_endpoint: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&sai2a_endpoint>;
- frame-master = <&cs42l51_tx_endpoint>;
- bitclock-master = <&cs42l51_tx_endpoint>;
- };
-
- cs42l51_rx_endpoint: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&sai2b_endpoint>;
- frame-master = <&cs42l51_rx_endpoint>;
- bitclock-master = <&cs42l51_rx_endpoint>;
- };
- };
- };
-};
-
-&i2c4 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c4_pins_a>;
- pinctrl-1 = <&i2c4_sleep_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- clock-frequency = <400000>;
- status = "okay";
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
-
- stusb1600@28 {
- compatible = "st,stusb1600";
- reg = <0x28>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpioi>;
- pinctrl-names = "default";
- pinctrl-0 = <&stusb1600_pins_a>;
- status = "okay";
- vdd-supply = <&vin>;
-
- connector {
- compatible = "usb-c-connector";
- label = "USB-C";
- power-role = "dual";
- typec-power-opmode = "default";
-
- port {
- con_usbotg_hs_ep: endpoint {
- remote-endpoint = <&usbotg_hs_ep>;
- };
- };
- };
- };
-
- pmic: stpmic@33 {
- compatible = "st,stpmic1";
- reg = <0x33>;
- interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <2>;
- status = "okay";
-
- regulators {
- compatible = "st,stpmic1-regulators";
- buck1-supply = <&vin>;
- buck2-supply = <&vin>;
- buck3-supply = <&vin>;
- buck4-supply = <&vin>;
- ldo1-supply = <&v3v3>;
- ldo2-supply = <&vin>;
- ldo3-supply = <&vdd_ddr>;
- ldo4-supply = <&vin>;
- ldo5-supply = <&vin>;
- ldo6-supply = <&v3v3>;
- vref_ddr-supply = <&vin>;
- boost-supply = <&vin>;
- pwr_sw1-supply = <&bst_out>;
- pwr_sw2-supply = <&bst_out>;
-
- vddcore: buck1 {
- regulator-name = "vddcore";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- vdd_ddr: buck2 {
- regulator-name = "vdd_ddr";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- vdd: buck3 {
- regulator-name = "vdd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- st,mask-reset;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- v3v3: buck4 {
- regulator-name = "v3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-over-current-protection;
- regulator-initial-mode = <0>;
- };
-
- v1v8_audio: ldo1 {
- regulator-name = "v1v8_audio";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- interrupts = <IT_CURLIM_LDO1 0>;
- };
-
- v3v3_hdmi: ldo2 {
- regulator-name = "v3v3_hdmi";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- interrupts = <IT_CURLIM_LDO2 0>;
- };
-
- vtt_ddr: ldo3 {
- regulator-name = "vtt_ddr";
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <750000>;
- regulator-always-on;
- regulator-over-current-protection;
- };
-
- vdd_usb: ldo4 {
- regulator-name = "vdd_usb";
- interrupts = <IT_CURLIM_LDO4 0>;
- };
-
- vdda: ldo5 {
- regulator-name = "vdda";
- regulator-min-microvolt = <2900000>;
- regulator-max-microvolt = <2900000>;
- interrupts = <IT_CURLIM_LDO5 0>;
- regulator-boot-on;
- };
-
- v1v2_hdmi: ldo6 {
- regulator-name = "v1v2_hdmi";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- interrupts = <IT_CURLIM_LDO6 0>;
- };
-
- vref_ddr: vref_ddr {
- regulator-name = "vref_ddr";
- regulator-always-on;
- };
-
- bst_out: boost {
- regulator-name = "bst_out";
- interrupts = <IT_OCP_BOOST 0>;
- };
-
- vbus_otg: pwr_sw1 {
- regulator-name = "vbus_otg";
- interrupts = <IT_OCP_OTG 0>;
- };
-
- vbus_sw: pwr_sw2 {
- regulator-name = "vbus_sw";
- interrupts = <IT_OCP_SWOUT 0>;
- regulator-active-discharge = <1>;
- };
- };
-
- onkey {
- compatible = "st,stpmic1-onkey";
- interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
- interrupt-names = "onkey-falling", "onkey-rising";
- power-off-time-sec = <10>;
- status = "okay";
- };
-
- watchdog {
- compatible = "st,stpmic1-wdt";
- status = "disabled";
- };
- };
-};
-
-&i2c5 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c5_pins_a>;
- pinctrl-1 = <&i2c5_sleep_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- clock-frequency = <400000>;
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
-};
-
-&i2s2 {
- clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
- clock-names = "pclk", "i2sclk", "x8k", "x11k";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2s2_pins_a>;
- pinctrl-1 = <&i2s2_sleep_pins_a>;
- status = "okay";
-
- i2s2_port: port {
- i2s2_endpoint: endpoint {
- remote-endpoint = <&sii9022_tx_endpoint>;
- dai-format = "i2s";
- mclk-fs = <256>;
- };
- };
-};
-
-&ipcc {
- status = "okay";
-};
-
-&iwdg2 {
- timeout-sec = <32>;
- status = "okay";
-};
-
-<dc {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <<dc_pins_a>;
- pinctrl-1 = <<dc_sleep_pins_a>;
- status = "okay";
-
- port {
- ltdc_ep0_out: endpoint {
- remote-endpoint = <&sii9022_in>;
- };
- };
-};
-
-&m4_rproc {
- memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
- <&vdev0vring1>, <&vdev0buffer>;
- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
- mbox-names = "vq0", "vq1", "shutdown", "detach";
- interrupt-parent = <&exti>;
- interrupts = <68 1>;
- status = "okay";
-};
-
-&pwr_regulators {
- vdd-supply = <&vdd>;
- vdd_3v3_usbfs-supply = <&vdd_usb>;
-};
-
-&rng1 {
- status = "okay";
-};
-
-&rtc {
- status = "okay";
-};
-
-&sai2 {
- clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
- clock-names = "pclk", "x8k", "x11k";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_b>;
- pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_b>;
- status = "okay";
-
- sai2a: audio-controller@4400b004 {
- #clock-cells = <0>;
- dma-names = "tx";
- status = "okay";
-
- sai2a_port: port {
- sai2a_endpoint: endpoint {
- remote-endpoint = <&cs42l51_tx_endpoint>;
- dai-format = "i2s";
- mclk-fs = <256>;
- dai-tdm-slot-num = <2>;
- dai-tdm-slot-width = <32>;
- };
- };
- };
-
- sai2b: audio-controller@4400b024 {
- dma-names = "rx";
- st,sync = <&sai2a 2>;
- clocks = <&rcc SAI2_K>, <&sai2a>;
- clock-names = "sai_ck", "MCLK";
- status = "okay";
-
- sai2b_port: port {
- sai2b_endpoint: endpoint {
- remote-endpoint = <&cs42l51_rx_endpoint>;
- dai-format = "i2s";
- mclk-fs = <256>;
- dai-tdm-slot-num = <2>;
- dai-tdm-slot-width = <32>;
- };
- };
- };
-};
-
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
- cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- disable-wp;
- st,neg-edge;
- bus-width = <4>;
- vmmc-supply = <&v3v3>;
- status = "okay";
-};
-
-&sdmmc3 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc3_b4_pins_a>;
- pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
- broken-cd;
- st,neg-edge;
- bus-width = <4>;
- vmmc-supply = <&v3v3>;
- status = "disabled";
-};
-
-&timers1 {
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm1_pins_a>;
- pinctrl-1 = <&pwm1_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@0 {
- status = "okay";
- };
-};
-
-&timers3 {
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm3_pins_a>;
- pinctrl-1 = <&pwm3_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@2 {
- status = "okay";
- };
-};
-
-&timers4 {
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm4_pins_a &pwm4_pins_b>;
- pinctrl-1 = <&pwm4_sleep_pins_a &pwm4_sleep_pins_b>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@3 {
- status = "okay";
- };
-};
-
-&timers5 {
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm5_pins_a>;
- pinctrl-1 = <&pwm5_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@4 {
- status = "okay";
- };
-};
-
-&timers6 {
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- timer@5 {
- status = "okay";
- };
-};
-
-&timers12 {
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm12_pins_a>;
- pinctrl-1 = <&pwm12_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@11 {
- status = "okay";
- };
-};
-
-&uart4 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&uart4_pins_a>;
- pinctrl-1 = <&uart4_sleep_pins_a>;
- pinctrl-2 = <&uart4_idle_pins_a>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
-
-&uart7 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&uart7_pins_c>;
- pinctrl-1 = <&uart7_sleep_pins_c>;
- pinctrl-2 = <&uart7_idle_pins_c>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
-};
-
-&usart3 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&usart3_pins_c>;
- pinctrl-1 = <&usart3_sleep_pins_c>;
- pinctrl-2 = <&usart3_idle_pins_c>;
- uart-has-rtscts;
- status = "disabled";
-};
-
-&usbh_ehci {
- phys = <&usbphyc_port0>;
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
- /* onboard HUB */
- hub@1 {
- compatible = "usb424,2514";
- reg = <1>;
- vdd-supply = <&v3v3>;
- };
-};
-
-&usbotg_hs {
- phys = <&usbphyc_port1 0>;
- phy-names = "usb2-phy";
- usb-role-switch;
- status = "okay";
-
- port {
- usbotg_hs_ep: endpoint {
- remote-endpoint = <&con_usbotg_hs_ep>;
- };
- };
-};
-
-&usbphyc {
- status = "okay";
-};
-
-&usbphyc_port0 {
- phy-supply = <&vdd_usb>;
- st,tune-hs-dc-level = <2>;
- st,enable-fs-rftime-tuning;
- st,enable-hs-rftime-reduction;
- st,trim-hs-current = <15>;
- st,trim-hs-impedance = <1>;
- st,tune-squelch-level = <3>;
- st,tune-hs-rx-offset = <2>;
- st,no-lsfs-sc;
-};
-
-&usbphyc_port1 {
- phy-supply = <&vdd_usb>;
- st,tune-hs-dc-level = <2>;
- st,enable-fs-rftime-tuning;
- st,enable-hs-rftime-reduction;
- st,trim-hs-current = <15>;
- st,trim-hs-impedance = <1>;
- st,tune-squelch-level = <3>;
- st,tune-hs-rx-offset = <2>;
- st,no-lsfs-sc;
-};
-
-&vrefbuf {
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <2500000>;
- vdda-supply = <&vdd>;
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp15xxaa-pinctrl.dtsi b/arch/arm/dts/stm32mp15xxaa-pinctrl.dtsi
deleted file mode 100644
index 04f7a43..0000000
--- a/arch/arm/dts/stm32mp15xxaa-pinctrl.dtsi
+++ /dev/null
@@ -1,85 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-&pinctrl {
- st,package = <STM32MP_PKG_AA>;
-
- gpioa: gpio@50002000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@50003000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@50004000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@50005000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@50006000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@50007000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@50008000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@50009000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 112 16>;
- };
-
- gpioi: gpio@5000a000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 128 16>;
- };
-
- gpioj: gpio@5000b000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 144 16>;
- };
-
- gpiok: gpio@5000c000 {
- status = "okay";
- ngpios = <8>;
- gpio-ranges = <&pinctrl 0 160 8>;
- };
-};
-
-&pinctrl_z {
- st,package = <STM32MP_PKG_AA>;
-
- gpioz: gpio@54004000 {
- status = "okay";
- ngpios = <8>;
- gpio-ranges = <&pinctrl_z 0 400 8>;
- };
-};
diff --git a/arch/arm/dts/stm32mp15xxab-pinctrl.dtsi b/arch/arm/dts/stm32mp15xxab-pinctrl.dtsi
deleted file mode 100644
index 328dad1..0000000
--- a/arch/arm/dts/stm32mp15xxab-pinctrl.dtsi
+++ /dev/null
@@ -1,57 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-&pinctrl {
- st,package = <STM32MP_PKG_AB>;
-
- gpioa: gpio@50002000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@50003000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@50004000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@50005000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@50006000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@50007000 {
- status = "okay";
- ngpios = <6>;
- gpio-ranges = <&pinctrl 6 86 6>;
- };
-
- gpiog: gpio@50008000 {
- status = "okay";
- ngpios = <10>;
- gpio-ranges = <&pinctrl 6 102 10>;
- };
-
- gpioh: gpio@50009000 {
- status = "okay";
- ngpios = <2>;
- gpio-ranges = <&pinctrl 0 112 2>;
- };
-};
diff --git a/arch/arm/dts/stm32mp15xxac-pinctrl.dtsi b/arch/arm/dts/stm32mp15xxac-pinctrl.dtsi
deleted file mode 100644
index 7eaa245..0000000
--- a/arch/arm/dts/stm32mp15xxac-pinctrl.dtsi
+++ /dev/null
@@ -1,73 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-&pinctrl {
- st,package = <STM32MP_PKG_AC>;
-
- gpioa: gpio@50002000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@50003000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@50004000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@50005000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@50006000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@50007000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@50008000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@50009000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 112 16>;
- };
-
- gpioi: gpio@5000a000 {
- status = "okay";
- ngpios = <12>;
- gpio-ranges = <&pinctrl 0 128 12>;
- };
-};
-
-&pinctrl_z {
- st,package = <STM32MP_PKG_AC>;
-
- gpioz: gpio@54004000 {
- status = "okay";
- ngpios = <8>;
- gpio-ranges = <&pinctrl_z 0 400 8>;
- };
-};
diff --git a/arch/arm/dts/stm32mp15xxad-pinctrl.dtsi b/arch/arm/dts/stm32mp15xxad-pinctrl.dtsi
deleted file mode 100644
index b63e207..0000000
--- a/arch/arm/dts/stm32mp15xxad-pinctrl.dtsi
+++ /dev/null
@@ -1,57 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-&pinctrl {
- st,package = <STM32MP_PKG_AD>;
-
- gpioa: gpio@50002000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@50003000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@50004000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@50005000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@50006000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@50007000 {
- status = "okay";
- ngpios = <6>;
- gpio-ranges = <&pinctrl 6 86 6>;
- };
-
- gpiog: gpio@50008000 {
- status = "okay";
- ngpios = <10>;
- gpio-ranges = <&pinctrl 6 102 10>;
- };
-
- gpioh: gpio@50009000 {
- status = "okay";
- ngpios = <2>;
- gpio-ranges = <&pinctrl 0 112 2>;
- };
-};
diff --git a/arch/arm/dts/stm32mp25-pinctrl.dtsi b/arch/arm/dts/stm32mp25-pinctrl.dtsi
deleted file mode 100644
index d34a1d5..0000000
--- a/arch/arm/dts/stm32mp25-pinctrl.dtsi
+++ /dev/null
@@ -1,38 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-#include <dt-bindings/pinctrl/stm32-pinfunc.h>
-
-&pinctrl {
- usart2_pins_a: usart2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 4, AF6)>; /* USART2_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
- bias-disable;
- };
- };
-
- usart2_idle_pins_a: usart2-idle-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 4, ANALOG)>; /* USART2_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
- bias-disable;
- };
- };
-
- usart2_sleep_pins_a: usart2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* USART2_TX */
- <STM32_PINMUX('A', 8, ANALOG)>; /* USART2_RX */
- };
- };
-};
diff --git a/arch/arm/dts/stm32mp251.dtsi b/arch/arm/dts/stm32mp251.dtsi
deleted file mode 100644
index e2d1c88..0000000
--- a/arch/arm/dts/stm32mp251.dtsi
+++ /dev/null
@@ -1,301 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
- #address-cells = <2>;
- #size-cells = <2>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- compatible = "arm,cortex-a35";
- device_type = "cpu";
- reg = <0>;
- enable-method = "psci";
- };
- };
-
- arm-pmu {
- compatible = "arm,cortex-a35-pmu";
- interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>;
- interrupt-parent = <&intc>;
- };
-
- arm_wdt: watchdog {
- compatible = "arm,smc-wdt";
- arm,smc-id = <0xb200005a>;
- status = "disabled";
- };
-
- clocks {
- ck_flexgen_08: ck-flexgen-08 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <64000000>;
- };
-
- ck_flexgen_51: ck-flexgen-51 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <200000000>;
- };
-
- ck_icn_ls_mcu: ck-icn-ls-mcu {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <200000000>;
- };
- };
-
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
-
- scmi {
- compatible = "linaro,scmi-optee";
- #address-cells = <1>;
- #size-cells = <0>;
- linaro,optee-channel-id = <0>;
-
- scmi_clk: protocol@14 {
- reg = <0x14>;
- #clock-cells = <1>;
- };
-
- scmi_reset: protocol@16 {
- reg = <0x16>;
- #reset-cells = <1>;
- };
- };
- };
-
- intc: interrupt-controller@4ac00000 {
- compatible = "arm,cortex-a7-gic";
- #interrupt-cells = <3>;
- #address-cells = <1>;
- interrupt-controller;
- reg = <0x0 0x4ac10000 0x0 0x1000>,
- <0x0 0x4ac20000 0x0 0x2000>,
- <0x0 0x4ac40000 0x0 0x2000>,
- <0x0 0x4ac60000 0x0 0x2000>;
- };
-
- psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupt-parent = <&intc>;
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- always-on;
- };
-
- soc@0 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&intc>;
- ranges = <0x0 0x0 0x0 0x80000000>;
-
- rifsc: rifsc-bus@42080000 {
- compatible = "simple-bus";
- reg = <0x42080000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- usart2: serial@400e0000 {
- compatible = "st,stm32h7-uart";
- reg = <0x400e0000 0x400>;
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ck_flexgen_08>;
- status = "disabled";
- };
- };
-
- bsec: efuse@44000000 {
- compatible = "st,stm32mp25-bsec";
- reg = <0x44000000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- part_number_otp@24 {
- reg = <0x24 0x4>;
- };
-
- package_otp@1e8 {
- reg = <0x1e8 0x1>;
- bits = <0 3>;
- };
- };
-
- syscfg: syscon@44230000 {
- compatible = "st,stm32mp25-syscfg", "syscon";
- reg = <0x44230000 0x10000>;
- };
-
- pinctrl: pinctrl@44240000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stm32mp257-pinctrl";
- ranges = <0 0x44240000 0xa0400>;
- pins-are-numbered;
-
- gpioa: gpio@44240000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x0 0x400>;
- clocks = <&ck_icn_ls_mcu>;
- st,bank-name = "GPIOA";
- status = "disabled";
- };
-
- gpiob: gpio@44250000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x10000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
- st,bank-name = "GPIOB";
- status = "disabled";
- };
-
- gpioc: gpio@44260000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x20000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
- st,bank-name = "GPIOC";
- status = "disabled";
- };
-
- gpiod: gpio@44270000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x30000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
- st,bank-name = "GPIOD";
- status = "disabled";
- };
-
- gpioe: gpio@44280000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x40000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
- st,bank-name = "GPIOE";
- status = "disabled";
- };
-
- gpiof: gpio@44290000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x50000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
- st,bank-name = "GPIOF";
- status = "disabled";
- };
-
- gpiog: gpio@442a0000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x60000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
- st,bank-name = "GPIOG";
- status = "disabled";
- };
-
- gpioh: gpio@442b0000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x70000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
- st,bank-name = "GPIOH";
- status = "disabled";
- };
-
- gpioi: gpio@442c0000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x80000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
- st,bank-name = "GPIOI";
- status = "disabled";
- };
-
- gpioj: gpio@442d0000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x90000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
- st,bank-name = "GPIOJ";
- status = "disabled";
- };
-
- gpiok: gpio@442e0000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0xa0000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
- st,bank-name = "GPIOK";
- status = "disabled";
- };
- };
-
- pinctrl_z: pinctrl@46200000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stm32mp257-z-pinctrl";
- ranges = <0 0x46200000 0x400>;
- pins-are-numbered;
-
- gpioz: gpio@46200000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0 0x400>;
- clocks = <&ck_icn_ls_mcu>;
- st,bank-name = "GPIOZ";
- st,bank-ioport = <11>;
- status = "disabled";
- };
-
- };
- };
-};
diff --git a/arch/arm/dts/stm32mp253.dtsi b/arch/arm/dts/stm32mp253.dtsi
deleted file mode 100644
index af48e82..0000000
--- a/arch/arm/dts/stm32mp253.dtsi
+++ /dev/null
@@ -1,23 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-#include "stm32mp251.dtsi"
-
-/ {
- cpus {
- cpu1: cpu@1 {
- compatible = "arm,cortex-a35";
- device_type = "cpu";
- reg = <1>;
- enable-method = "psci";
- };
- };
-
- arm-pmu {
- interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>, <&cpu1>;
- };
-};
diff --git a/arch/arm/dts/stm32mp255.dtsi b/arch/arm/dts/stm32mp255.dtsi
deleted file mode 100644
index e6fa596..0000000
--- a/arch/arm/dts/stm32mp255.dtsi
+++ /dev/null
@@ -1,9 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-#include "stm32mp253.dtsi"
-
-/ {
-};
diff --git a/arch/arm/dts/stm32mp257.dtsi b/arch/arm/dts/stm32mp257.dtsi
deleted file mode 100644
index 5c5000d..0000000
--- a/arch/arm/dts/stm32mp257.dtsi
+++ /dev/null
@@ -1,9 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-#include "stm32mp255.dtsi"
-
-/ {
-};
diff --git a/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi
index a35a9b9..d778b8d 100644
--- a/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi
@@ -5,8 +5,89 @@
#include "stm32mp25-u-boot.dtsi"
+/ {
+ config {
+ u-boot,boot-led = "led-blue";
+ u-boot,mmc-env-partition = "u-boot-env";
+ };
+
+ clocks {
+ ck_flexgen_08: ck-flexgen-08 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <64000000>;
+ };
+
+ ck_flexgen_51: ck-flexgen-51 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ };
+
+ ck_icn_ls_mcu: ck-icn-ls-mcu {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ };
+ };
+};
+
+&gpioa {
+ clocks = <&ck_icn_ls_mcu>;
+};
+
+&gpiob {
+ clocks = <&ck_icn_ls_mcu>;
+};
+
+&gpioc {
+ clocks = <&ck_icn_ls_mcu>;
+};
+
+&gpiod {
+ clocks = <&ck_icn_ls_mcu>;
+};
+
+&gpioe {
+ clocks = <&ck_icn_ls_mcu>;
+};
+
+&gpiof {
+ clocks = <&ck_icn_ls_mcu>;
+};
+
+&gpiog {
+ clocks = <&ck_icn_ls_mcu>;
+};
+
+&gpioh {
+ clocks = <&ck_icn_ls_mcu>;
+};
+
+&gpioi {
+ clocks = <&ck_icn_ls_mcu>;
+};
+
+&gpioj {
+ clocks = <&ck_icn_ls_mcu>;
+};
+
+&gpiok {
+ clocks = <&ck_icn_ls_mcu>;
+};
+
+&gpioz {
+ clocks = <&ck_icn_ls_mcu>;
+};
+
+&sdmmc1 {
+ clocks = <&ck_flexgen_51>;
+ /delete-property/resets;
+};
+
&usart2 {
bootph-all;
+ clocks = <&ck_flexgen_08>;
};
&usart2_pins_a {
diff --git a/arch/arm/dts/stm32mp257f-ev1.dts b/arch/arm/dts/stm32mp257f-ev1.dts
deleted file mode 100644
index a88494e..0000000
--- a/arch/arm/dts/stm32mp257f-ev1.dts
+++ /dev/null
@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-/dts-v1/;
-
-#include "stm32mp257.dtsi"
-#include "stm32mp25xf.dtsi"
-#include "stm32mp25-pinctrl.dtsi"
-#include "stm32mp25xxai-pinctrl.dtsi"
-
-/ {
- model = "STMicroelectronics STM32MP257F-EV1 Evaluation Board";
- compatible = "st,stm32mp257f-ev1", "st,stm32mp257";
-
- aliases {
- serial0 = &usart2;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x0 0x80000000 0x1 0x0>;
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- fw@80000000 {
- compatible = "shared-dma-pool";
- reg = <0x0 0x80000000 0x0 0x4000000>;
- no-map;
- };
- };
-};
-
-&arm_wdt {
- timeout-sec = <32>;
- status = "okay";
-};
-
-&usart2 {
- pinctrl-names = "default", "idle", "sleep";
- pinctrl-0 = <&usart2_pins_a>;
- pinctrl-1 = <&usart2_idle_pins_a>;
- pinctrl-2 = <&usart2_sleep_pins_a>;
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp25xc.dtsi b/arch/arm/dts/stm32mp25xc.dtsi
deleted file mode 100644
index 5e83a69..0000000
--- a/arch/arm/dts/stm32mp25xc.dtsi
+++ /dev/null
@@ -1,8 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-/ {
-};
diff --git a/arch/arm/dts/stm32mp25xf.dtsi b/arch/arm/dts/stm32mp25xf.dtsi
deleted file mode 100644
index 5e83a69..0000000
--- a/arch/arm/dts/stm32mp25xf.dtsi
+++ /dev/null
@@ -1,8 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-/ {
-};
diff --git a/arch/arm/dts/stm32mp25xxai-pinctrl.dtsi b/arch/arm/dts/stm32mp25xxai-pinctrl.dtsi
deleted file mode 100644
index abdbc7a..0000000
--- a/arch/arm/dts/stm32mp25xxai-pinctrl.dtsi
+++ /dev/null
@@ -1,83 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-&pinctrl {
- st,package = <STM32MP_PKG_AI>;
-
- gpioa: gpio@44240000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@44250000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@44260000 {
- status = "okay";
- ngpios = <14>;
- gpio-ranges = <&pinctrl 0 32 14>;
- };
-
- gpiod: gpio@44270000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@44280000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@44290000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@442a0000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@442b0000 {
- status = "okay";
- ngpios = <12>;
- gpio-ranges = <&pinctrl 2 114 12>;
- };
-
- gpioi: gpio@442c0000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 128 16>;
- };
-
- gpioj: gpio@442d0000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 144 16>;
- };
-
- gpiok: gpio@442e0000 {
- status = "okay";
- ngpios = <8>;
- gpio-ranges = <&pinctrl 0 160 8>;
- };
-};
-
-&pinctrl_z {
- gpioz: gpio@46200000 {
- status = "okay";
- ngpios = <10>;
- gpio-ranges = <&pinctrl_z 0 400 10>;
- };
-};
diff --git a/arch/arm/dts/stm32mp25xxak-pinctrl.dtsi b/arch/arm/dts/stm32mp25xxak-pinctrl.dtsi
deleted file mode 100644
index 2e0d4d3..0000000
--- a/arch/arm/dts/stm32mp25xxak-pinctrl.dtsi
+++ /dev/null
@@ -1,71 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-&pinctrl {
- st,package = <STM32MP_PKG_AK>;
-
- gpioa: gpio@44240000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@44250000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@44260000 {
- status = "okay";
- ngpios = <14>;
- gpio-ranges = <&pinctrl 0 32 14>;
- };
-
- gpiod: gpio@44270000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@44280000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@44290000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@442a0000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@442b0000 {
- status = "okay";
- ngpios = <12>;
- gpio-ranges = <&pinctrl 2 114 12>;
- };
-
- gpioi: gpio@442c0000 {
- status = "okay";
- ngpios = <12>;
- gpio-ranges = <&pinctrl 0 128 12>;
- };
-};
-
-&pinctrl_z {
- gpioz: gpio@46200000 {
- status = "okay";
- ngpios = <10>;
- gpio-ranges = <&pinctrl_z 0 400 10>;
- };
-};
diff --git a/arch/arm/dts/stm32mp25xxal-pinctrl.dtsi b/arch/arm/dts/stm32mp25xxal-pinctrl.dtsi
deleted file mode 100644
index 2406e97..0000000
--- a/arch/arm/dts/stm32mp25xxal-pinctrl.dtsi
+++ /dev/null
@@ -1,71 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-&pinctrl {
- st,package = <STM32MP_PKG_AL>;
-
- gpioa: gpio@44240000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@44250000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@44260000 {
- status = "okay";
- ngpios = <14>;
- gpio-ranges = <&pinctrl 0 32 14>;
- };
-
- gpiod: gpio@44270000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@44280000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@44290000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@442a0000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@442b0000 {
- status = "okay";
- ngpios = <12>;
- gpio-ranges = <&pinctrl 2 114 12>;
- };
-
- gpioi: gpio@442c0000 {
- status = "okay";
- ngpios = <12>;
- gpio-ranges = <&pinctrl 0 128 12>;
- };
-};
-
-&pinctrl_z {
- gpioz: gpio@46200000 {
- status = "okay";
- ngpios = <10>;
- gpio-ranges = <&pinctrl_z 0 400 10>;
- };
-};
diff --git a/arch/arm/dts/tegra114-asus-tf701t.dts b/arch/arm/dts/tegra114-asus-tf701t.dts
new file mode 100644
index 0000000..2505b9b
--- /dev/null
+++ b/arch/arm/dts/tegra114-asus-tf701t.dts
@@ -0,0 +1,1245 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "tegra114.dtsi"
+
+/ {
+ model = "ASUS Transformer Pad TF701T";
+ compatible = "asus,tf701t", "nvidia,tegra114";
+
+ chosen {
+ stdout-path = &uartd;
+ };
+
+ aliases {
+ i2c0 = &pwr_i2c;
+
+ mmc0 = &sdmmc4; /* eMMC */
+ mmc1 = &sdmmc3; /* uSD slot */
+
+ usb0 = &usb1;
+ usb1 = &usb3; /* Dock USB */
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ host1x@50000000 {
+ dsia: dsi@54300000 {
+ status = "okay";
+
+ avdd-dsi-csi-supply = <&avdd_dsi_csi>;
+ nvidia,ganged-mode = <&dsib>;
+
+ panel@0 {
+ compatible = "sharp,lq101r1sx01";
+ reg = <0>;
+
+ link2 = <&panel_secondary>;
+
+ power-supply = <&dvdd_1v8_lcd>;
+ backlight = <&backlight>;
+ };
+ };
+
+ dsib: dsi@54400000 {
+ clocks = <&tegra_car TEGRA114_CLK_DSIB>,
+ <&tegra_car TEGRA114_CLK_DSIBLP>,
+ <&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
+ clock-names = "dsi", "lp", "parent";
+ status = "okay";
+
+ avdd-dsi-csi-supply = <&avdd_dsi_csi>;
+
+ panel_secondary: panel@0 {
+ compatible = "sharp,lq101r1sx01";
+ reg = <0>;
+ };
+ };
+ };
+
+ pinmux@70000868 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ /* WLAN SDIO pinmux */
+ sdmmc1-clk {
+ nvidia,pins = "sdmmc1_clk_pz0";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1-cmd {
+ nvidia,pins = "sdmmc1_cmd_pz1",
+ "sdmmc1_dat0_py7",
+ "sdmmc1_dat1_py6",
+ "sdmmc1_dat2_py5",
+ "sdmmc1_dat3_py4";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ wlan-power {
+ nvidia,pins = "clk2_req_pcc5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ wlan-reset {
+ nvidia,pins = "gpio_x7_aud_px7";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ wlan-host-wake {
+ nvidia,pins = "pu5";
+ nvidia,function = "pwm2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ wlan-3v3-com {
+ nvidia,pins = "pu1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* UART-A pinmux */
+ uarta-cts {
+ nvidia,pins = "kb_row10_ps2";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uarta-rts {
+ nvidia,pins = "kb_row9_ps1";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* GNSS UART-B pinmux */
+ uartb-cts {
+ nvidia,pins = "uart2_cts_n_pj5";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uartb-rts {
+ nvidia,pins = "uart2_rts_n_pj6";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ uartb-rxd {
+ nvidia,pins = "uart2_rxd_pc3";
+ nvidia,function = "irda";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uartb-txd {
+ nvidia,pins = "uart2_txd_pc2";
+ nvidia,function = "irda";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Bluetooth UART-C pinmux */
+ uartc-cts-rxd {
+ nvidia,pins = "uart3_cts_n_pa1",
+ "uart3_rxd_pw7";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uartc-rts-txd {
+ nvidia,pins = "uart3_rts_n_pc0",
+ "uart3_txd_pw6";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ bt-shutdown {
+ nvidia,pins = "kb_col6_pq6",
+ "kb_col7_pq7";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ bt-dev-wake {
+ nvidia,pins = "clk3_req_pee1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ bt-host-wake {
+ nvidia,pins = "pu6";
+ nvidia,function = "pwm3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ bt-pcm-dap4-out {
+ nvidia,pins = "dap4_fs_pp4",
+ "dap4_dout_pp6",
+ "dap4_sclk_pp7";
+ nvidia,function = "i2s3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ bt-pcm-dap4-in {
+ nvidia,pins = "dap4_din_pp5";
+ nvidia,function = "i2s3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* UART-D pinmux */
+ uartd-cts {
+ nvidia,pins = "gmi_a17_pb0";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uartd-rts {
+ nvidia,pins = "gmi_a16_pj7",
+ "gmi_a19_pk7";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* MicroSD pinmux */
+ sdmmc3-clk {
+ nvidia,pins = "sdmmc3_clk_pa6";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3-data {
+ nvidia,pins = "sdmmc3_cmd_pa7",
+ "sdmmc3_dat0_pb7",
+ "sdmmc3_dat1_pb6",
+ "sdmmc3_dat2_pb5",
+ "sdmmc3_dat3_pb4",
+ "kb_col4_pq4",
+ "sdmmc3_cd_n_pv2",
+ "sdmmc3_clk_lb_out_pee4",
+ "sdmmc3_clk_lb_in_pee5";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ microsd-pwr {
+ nvidia,pins = "gmi_clk_pk1";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* EMMC pinmux */
+ sdmmc4-clk-cmd {
+ nvidia,pins = "sdmmc4_clk_pcc4";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4-data {
+ nvidia,pins = "sdmmc4_cmd_pt7",
+ "sdmmc4_dat0_paa0",
+ "sdmmc4_dat1_paa1",
+ "sdmmc4_dat2_paa2",
+ "sdmmc4_dat3_paa3",
+ "sdmmc4_dat4_paa4",
+ "sdmmc4_dat5_paa5",
+ "sdmmc4_dat6_paa6",
+ "sdmmc4_dat7_paa7";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* I2C pinmux */
+ gen1-i2c {
+ nvidia,pins = "gen1_i2c_scl_pc4",
+ "gen1_i2c_sda_pc5";
+ nvidia,function = "i2c1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ };
+ gen2-i2c {
+ nvidia,pins = "gen2_i2c_scl_pt5",
+ "gen2_i2c_sda_pt6";
+ nvidia,function = "i2c2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ };
+ cam-i2c {
+ nvidia,pins = "cam_i2c_scl_pbb1",
+ "cam_i2c_sda_pbb2";
+ nvidia,function = "i2c3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ };
+ ddc-i2c {
+ nvidia,pins = "ddc_scl_pv4",
+ "ddc_sda_pv5";
+ nvidia,function = "i2c4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ };
+ pwr-i2c {
+ nvidia,pins = "pwr_i2c_scl_pz6",
+ "pwr_i2c_sda_pz7";
+ nvidia,function = "i2cpwr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* SPI pinmux */
+ spi1-out {
+ nvidia,pins = "ulpi_clk_py0",
+ "ulpi_nxt_py2",
+ "ulpi_stp_py3";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spi1-in {
+ nvidia,pins = "ulpi_dir_py1";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi2 {
+ nvidia,pins = "ulpi_data4_po5",
+ "ulpi_data7_po0";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi4-out {
+ nvidia,pins = "gmi_ad6_pg6",
+ "gmi_wr_n_pi0";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spi4-in {
+ nvidia,pins = "gmi_ad5_pg5",
+ "gmi_ad7_pg7";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* GPIO keys pinmux */
+ hall-switch {
+ nvidia,pins = "ulpi_data4_po5";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lineout-switch {
+ nvidia,pins = "gpio_x5_aud_px5";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ power-key {
+ nvidia,pins = "kb_col0_pq0";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ volume-keys {
+ nvidia,pins = "kb_row1_pr1",
+ "kb_row2_pr2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Sensors pinmux */
+ nct-irq {
+ nvidia,pins = "ulpi_data3_po4";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ mpu-irq {
+ nvidia,pins = "kb_row3_pr3";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* HDMI pinmux */
+ hdmi-hpd {
+ nvidia,pins = "hdmi_int_pn7";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ hdmi-en {
+ nvidia,pins = "dap3_dout_pp2";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ hdmi-cec {
+ nvidia,pins = "hdmi_cec_pee3";
+ nvidia,function = "cec";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* LED pinmux */
+ backlight-pwm {
+ nvidia,pins = "gmi_ad9_ph1";
+ nvidia,function = "pwm1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ backlight-en {
+ nvidia,pins = "gmi_ad10_ph2";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Touchscreen pinmux */
+ touch-irq {
+ nvidia,pins = "gmi_cs4_n_pk2";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ touch-rst {
+ nvidia,pins = "gmi_cs3_n_pk4";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ touch-pwr {
+ nvidia,pins = "gmi_ad8_ph0";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ touch-vio {
+ nvidia,pins = "gmi_ad12_ph4";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* AUDIO pinmux */
+ audio-ldo1 {
+ nvidia,pins = "sdmmc1_wp_n_pv3";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ hp-detect {
+ nvidia,pins = "kb_row7_pr7";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap-i2s0-in {
+ nvidia,pins = "dap1_din_pn1";
+ nvidia,function = "i2s0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap-i2s0-out {
+ nvidia,pins = "dap1_dout_pn2",
+ "dap1_fs_pn0",
+ "dap1_sclk_pn3";
+ nvidia,function = "i2s0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap-i2s1-in {
+ nvidia,pins = "dap2_din_pa4";
+ nvidia,function = "i2s1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap-i2s1-out {
+ nvidia,pins = "dap2_dout_pa5",
+ "dap2_fs_pa2",
+ "dap2_sclk_pa3";
+ nvidia,function = "i2s1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap-i2s2-in {
+ nvidia,pins = "dap3_fs_pp0",
+ "dap3_sclk_pp3";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap-i2s2-out {
+ nvidia,pins = "dap3_din_pp1";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spdif-in {
+ nvidia,pins = "spdif_in_pk6";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spdif-out {
+ nvidia,pins = "spdif_out_pk5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* AsusEC pinmux */
+ ec-irq {
+ nvidia,pins = "kb_col5_pq5";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ec-req {
+ nvidia,pins = "kb_col2_pq2";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ hotplug-i2c {
+ nvidia,pins = "ulpi_data7_po0";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ps2-irq {
+ nvidia,pins = "gpio_w2_aud_pw2";
+ nvidia,function = "spi6";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kbd-irq {
+ nvidia,pins = "gmi_cs0_n_pj0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ dvfs-pin {
+ nvidia,pins = "dvfs_pwm_px0",
+ "dvfs_clk_px2";
+ nvidia,function = "cldvfs";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Core pinmux */
+ clk-32k-out {
+ nvidia,pins = "clk_32k_out_pa0";
+ nvidia,function = "soc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sys-clk-req {
+ nvidia,pins = "sys_clk_req_pz5";
+ nvidia,function = "sysclk";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ core-pwr-req {
+ nvidia,pins = "core_pwr_req";
+ nvidia,function = "pwron";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ cpu-pwr-req {
+ nvidia,pins = "cpu_pwr_req";
+ nvidia,function = "cpu";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pwr-int-n {
+ nvidia,pins = "pwr_int_n";
+ nvidia,function = "pmi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk-32k-in {
+ nvidia,pins = "clk_32k_in";
+ nvidia,function = "clk";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ owr {
+ nvidia,pins = "owr";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ reset-out-n {
+ nvidia,pins = "reset_out_n";
+ nvidia,function = "reset_out_n";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* ULPI pinmux */
+ ulpi-data0-6 {
+ nvidia,pins = "ulpi_data0_po1",
+ "ulpi_data6_po7";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi-data1-5 {
+ nvidia,pins = "ulpi_data1_po2",
+ "ulpi_data5_po6";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi-data2-3 {
+ nvidia,pins = "ulpi_data2_po3",
+ "ulpi_data3_po4";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT V */
+ pv0-gpio {
+ nvidia,pins = "pv0";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pv1-gpio {
+ nvidia,pins = "pv1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT U */
+ pu0-gpio {
+ nvidia,pins = "pu0";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pu2-gpio {
+ nvidia,pins = "pu2";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PWM pinmux */
+ pwm0 {
+ nvidia,pins = "pu3";
+ nvidia,function = "pwm0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pwm1 {
+ nvidia,pins = "pu4";
+ nvidia,function = "pwm1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* EXTPERIPH pinmux */
+ clk1-out {
+ nvidia,pins = "clk1_out_pw4";
+ nvidia,function = "extperiph1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ clk2-out {
+ nvidia,pins = "clk2_out_pw5";
+ nvidia,function = "extperiph2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ clk3-out {
+ nvidia,pins = "clk3_out_pee0";
+ nvidia,function = "extperiph3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ clk1-req {
+ nvidia,pins = "clk1_req_pee2";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* GMI pinmux */
+ gmi-wp-n {
+ nvidia,pins = "gmi_wp_n_pc7";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-adv {
+ nvidia,pins = "gmi_adv_n_pk0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-ad0-ad1 {
+ nvidia,pins = "gmi_ad0_pg0",
+ "gmi_ad1_pg1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-ad2-ad3 {
+ nvidia,pins = "gmi_ad2_pg2",
+ "gmi_ad3_pg3";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-iordy {
+ nvidia,pins = "gmi_iordy_pi5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-a18 {
+ nvidia,pins = "gmi_a18_pb1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-wait {
+ nvidia,pins = "gmi_wait_pi7";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-cs6-n {
+ nvidia,pins = "gmi_cs6_n_pi3";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-cs7-n {
+ nvidia,pins = "gmi_cs7_n_pi6";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-dqs-p {
+ nvidia,pins = "gmi_dqs_p_pj3";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-cs2-ad {
+ nvidia,pins = "gmi_cs2_n_pk3",
+ "gmi_ad14_ph6",
+ "gmi_ad15_ph7";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-cs4-clk {
+ nvidia,pins = "gmi_cs4_n_pk2",
+ "gmi_clk_lb";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-ad11 {
+ nvidia,pins = "gmi_ad11_ph3";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-cs1-oe {
+ nvidia,pins = "gmi_cs1_n_pj2",
+ "gmi_oe_n_pi1";
+ nvidia,function = "soc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-ad4 {
+ nvidia,pins = "gmi_ad4_pg4";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-ad13 {
+ nvidia,pins = "gmi_ad13_ph5";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-rst-n {
+ nvidia,pins = "gmi_rst_n_pi4";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* PORT CC */
+ pcc-gpio {
+ nvidia,pins = "pcc1", "pcc2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT BB */
+ pbb3-gpio {
+ nvidia,pins = "pbb3";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb4-5-6-gpio {
+ nvidia,pins = "pbb4", "pbb5", "pbb6";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pbb7-gpio {
+ nvidia,pins = "pbb7";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* KBC pinmux */
+ kb-r0-c1 {
+ nvidia,pins = "kb_row0_pr0",
+ "kb_col1_pq1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb-row4 {
+ nvidia,pins = "kb_row4_pr4";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb-row5 {
+ nvidia,pins = "kb_row5_pr5";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb-row6 {
+ nvidia,pins = "kb_row6_pr6";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb-r8-c3 {
+ nvidia,pins = "kb_row8_ps0",
+ "kb_col3_pq3";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* VI pinmux */
+ cam-mclk {
+ nvidia,pins = "cam_mclk_pcc0",
+ "pbb0";
+ nvidia,function = "vi_alt3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* AUD pinmux */
+ gpio-x4-aud {
+ nvidia,pins = "gpio_x4_aud_px4";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gpio-x1-aud {
+ nvidia,pins = "gpio_x1_aud_px1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gpio-x3-aud {
+ nvidia,pins = "gpio_x3_aud_px3";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gpio-x6-aud {
+ nvidia,pins = "gpio_x6_aud_px6";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ usb-vbus {
+ nvidia,pins = "usb_vbus_en0_pn4",
+ "usb_vbus_en1_pn5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* GPIO power/drive control */
+ drive-sdio1 {
+ nvidia,pins = "drive_sdio1";
+ nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,pull-down-strength = <36>;
+ nvidia,pull-up-strength = <20>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
+ };
+ drive-sdio3 {
+ nvidia,pins = "drive_sdio3";
+ nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,pull-down-strength = <22>;
+ nvidia,pull-up-strength = <36>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ };
+ drive-gma {
+ nvidia,pins = "drive_gma";
+ nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,pull-down-strength = <2>;
+ nvidia,pull-up-strength = <2>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ };
+ };
+ };
+
+ uartd: serial@70006300 {
+ status = "okay";
+ };
+
+ pwm: pwm@7000a000 {
+ status = "okay";
+ };
+
+ pwr_i2c: i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* Texas Instruments TPS65913 PMIC */
+ pmic: tps65913@58 {
+ compatible = "ti,tps65913";
+ reg = <0x58>;
+
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ ti,system-power-controller;
+
+ palmas_gpio: gpio {
+ compatible = "ti,palmas-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ pinmux {
+ compatible = "ti,tps65913-pinctrl";
+ ti,palmas-enable-dvfs1;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&palmas_default>;
+
+ palmas_default: pinmux {
+ pin_gpio4 {
+ pins = "gpio4";
+ function = "gpio";
+ };
+ };
+ };
+
+ pmic {
+ compatible = "ti,tps65913-pmic";
+
+ regulators {
+ vdd_1v8_vio: smps8 {
+ regulator-name = "vdd_1v8_gen";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcore_emmc: smps9 {
+ regulator-name = "vdd_sdmmc";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ avdd_dsi_csi: ldo2 {
+ regulator-name = "avdd_dsi_csi";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-boot-on;
+ };
+
+ vddio_usd: ldo9 {
+ regulator-name = "vddio_sdmmc";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ avdd_usb: ldousb {
+ regulator-name = "vdd_usb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+ };
+ };
+
+ sdmmc3: sdhci@78000400 {
+ status = "okay";
+ bus-width = <4>;
+
+ cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+ power-gpios = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
+
+ nvidia,default-tap = <0x3>;
+ nvidia,default-trim = <0x3>;
+
+ vmmc-supply = <&vcore_emmc>;
+ vqmmc-supply = <&vddio_usd>;
+ };
+
+ sdmmc4: sdhci@78000600 {
+ status = "okay";
+ bus-width = <8>;
+ non-removable;
+
+ vmmc-supply = <&vcore_emmc>;
+ vqmmc-supply = <&vdd_1v8_vio>;
+ };
+
+ /* USB via ASUS connector */
+ usb1: usb@7d000000 {
+ status = "okay";
+ dr_mode = "otg";
+ };
+
+ /* Dock's USB port */
+ usb3: usb@7d008000 {
+ status = "okay";
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+
+ enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+ pwms = <&pwm 1 1000000>;
+
+ brightness-levels = <1 35 70 105 140 175 210 255>;
+ default-brightness-level = <5>;
+ };
+
+ clk32k_in: clock-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "ref-oscillator";
+ };
+
+ extcon-keys {
+ compatible = "gpio-keys";
+
+ switch-hall-sensor {
+ label = "Hall Sensor";
+ gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>;
+ linux,code = <SW_LID>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key-power {
+ label = "Power";
+ gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_ENTER>;
+ };
+
+ key-volume-down {
+ label = "Volume Down";
+ gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_DOWN>;
+ };
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_UP>;
+ };
+ };
+
+ dvdd_1v8_lcd: regulator-lcdvio {
+ compatible = "regulator-fixed";
+ regulator-name = "dvdd_lcd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
diff --git a/arch/arm/dts/tegra114-nvidia-tegratab.dts b/arch/arm/dts/tegra114-nvidia-tegratab.dts
new file mode 100644
index 0000000..f65772a
--- /dev/null
+++ b/arch/arm/dts/tegra114-nvidia-tegratab.dts
@@ -0,0 +1,1041 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "tegra114.dtsi"
+
+/ {
+ model = "NVIDIA Tegra Note 7";
+ compatible = "nvidia,tegratab", "nvidia,tegra114";
+
+ chosen {
+ stdout-path = &uartd;
+ };
+
+ aliases {
+ i2c0 = &pwr_i2c;
+
+ mmc0 = &sdmmc4; /* eMMC */
+ mmc1 = &sdmmc3; /* uSD slot */
+
+ usb0 = &usb1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ host1x@50000000 {
+ dc@54200000 {
+ nvidia,180-rotation;
+ };
+
+ dsia: dsi@54300000 {
+ status = "okay";
+
+ avdd-dsi-csi-supply = <&avdd_dsi_csi>;
+
+ panel@0 {
+ compatible = "lg,ld070wx3-sl01";
+ reg = <0>;
+
+ vdd-supply = <&avdd_3v3_lcd>;
+ vcc-supply = <&dvdd_1v8_lcd>;
+
+ backlight = <&backlight>;
+ };
+ };
+ };
+
+ pinmux@70000868 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ /* ULPI pinmux */
+ ulpi-data0 {
+ nvidia,pins = "ulpi_data0_po1",
+ "ulpi_data1_po2",
+ "ulpi_data2_po3",
+ "ulpi_data5_po6",
+ "ulpi_data6_po7",
+ "ulpi_data7_po0";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi-data3 {
+ nvidia,pins = "ulpi_data3_po4",
+ "ulpi_data4_po5";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* SPI1 pinmux */
+ ulpi-clk {
+ nvidia,pins = "ulpi_clk_py0",
+ "ulpi_nxt_py2",
+ "ulpi_stp_py3";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi-dir {
+ nvidia,pins = "ulpi_dir_py1";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* I2S pinmux */
+ dap1-pins {
+ nvidia,pins = "dap1_fs_pn0",
+ "dap1_din_pn1",
+ "dap1_dout_pn2",
+ "dap1_sclk_pn3";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap2-dout {
+ nvidia,pins = "dap2_fs_pa2",
+ "dap2_sclk_pa3",
+ "dap2_dout_pa5";
+ nvidia,function = "i2s1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap2-din {
+ nvidia,pins = "dap2_din_pa4";
+ nvidia,function = "i2s1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap3-fs-pp0 {
+ nvidia,pins = "dap3_fs_pp0",
+ "dap3_din_pp1",
+ "dap3_dout_pp2",
+ "dap3_sclk_pp3";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pv0 {
+ nvidia,pins = "pv0";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pv1 {
+ nvidia,pins = "pv1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap4-din {
+ nvidia,pins = "dap4_din_pp5";
+ nvidia,function = "i2s3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap4-dout {
+ nvidia,pins = "dap4_fs_pp4",
+ "dap4_dout_pp6",
+ "dap4_sclk_pp7";
+ nvidia,function = "i2s3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* SDMMC1 pinmux */
+ sdmmc1-clk {
+ nvidia,pins = "sdmmc1_clk_pz0";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1-cmd {
+ nvidia,pins = "sdmmc1_cmd_pz1",
+ "sdmmc1_dat0_py7",
+ "sdmmc1_dat1_py6",
+ "sdmmc1_dat2_py5",
+ "sdmmc1_dat3_py4";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1-wp-n {
+ nvidia,pins = "sdmmc1_wp_n_pv3";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* SDMMC3 pinmux */
+ sdmmc3-clk {
+ nvidia,pins = "sdmmc3_clk_pa6";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ sdmmc3-cmd {
+ nvidia,pins = "sdmmc3_cmd_pa7",
+ "sdmmc3_dat0_pb7",
+ "sdmmc3_dat1_pb6",
+ "sdmmc3_dat2_pb5",
+ "sdmmc3_dat3_pb4",
+ "sdmmc3_cd_n_pv2";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3-clk-lb {
+ nvidia,pins = "sdmmc3_clk_lb_out_pee4",
+ "sdmmc3_clk_lb_in_pee5";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* SDMMC4 pinmux */
+ sdmmc4-clk {
+ nvidia,pins = "sdmmc4_clk_pcc4";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4-cmd {
+ nvidia,pins = "sdmmc4_cmd_pt7",
+ "sdmmc4_dat0_paa0",
+ "sdmmc4_dat1_paa1",
+ "sdmmc4_dat2_paa2",
+ "sdmmc4_dat3_paa3",
+ "sdmmc4_dat4_paa4",
+ "sdmmc4_dat5_paa5",
+ "sdmmc4_dat6_paa6",
+ "sdmmc4_dat7_paa7";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* EXTPERIPH pinmux */
+ clk1-req {
+ nvidia,pins = "clk1_req_pee2";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ clk1-out {
+ nvidia,pins = "clk1_out_pw4";
+ nvidia,function = "extperiph1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ clk2-req {
+ nvidia,pins = "clk2_req_pcc5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ clk2-out {
+ nvidia,pins = "clk2_out_pw5";
+ nvidia,function = "extperiph2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ clk3-req-pee1 {
+ nvidia,pins = "clk3_req_pee1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ clk3-out {
+ nvidia,pins = "clk3_out_pee0";
+ nvidia,function = "extperiph3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ dvfs-pinmux {
+ nvidia,pins = "dvfs_pwm_px0",
+ "dvfs_clk_px2";
+ nvidia,function = "cldvfs";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* HDMI pinmux */
+ hdmi-irq {
+ nvidia,pins = "hdmi_int_pn7";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+ };
+ hdmi-cec {
+ nvidia,pins = "hdmi_cec_pee3";
+ nvidia,function = "cec";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* I2C pinmux */
+ gen1-i2c {
+ nvidia,pins = "gen1_i2c_scl_pc4",
+ "gen1_i2c_sda_pc5";
+ nvidia,function = "i2c1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ gen2-i2c {
+ nvidia,pins = "gen2_i2c_scl_pt5",
+ "gen2_i2c_sda_pt6";
+ nvidia,function = "i2c2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ cam-i2c {
+ nvidia,pins = "cam_i2c_scl_pbb1",
+ "cam_i2c_sda_pbb2";
+ nvidia,function = "i2c3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ ddc-scl-pv4 {
+ nvidia,pins = "ddc_scl_pv4",
+ "ddc_sda_pv5";
+ nvidia,function = "i2c4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+ };
+ pwr-i2c {
+ nvidia,pins = "pwr_i2c_scl_pz6",
+ "pwr_i2c_sda_pz7";
+ nvidia,function = "i2cpwr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* UARTA pinmux */
+ uarta-out {
+ nvidia,pins = "kb_row9_ps1";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ uarta-in {
+ nvidia,pins = "kb_row10_ps2";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* UARTB pinmux */
+ uart2-cts-rts {
+ nvidia,pins = "uart2_cts_n_pj5",
+ "uart2_rts_n_pj6";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* UARTC pinmux */
+ uart3-cts-rxd {
+ nvidia,pins = "uart3_cts_n_pa1",
+ "uart3_rxd_pw7";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uart3-rts-txd {
+ nvidia,pins = "uart3_rts_n_pc0",
+ "uart3_txd_pw6";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* UARTD pinmux */
+ gmi-a17 {
+ nvidia,pins = "gmi_a17_pb0";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-a18 {
+ nvidia,pins = "gmi_a18_pb1";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uartd-out {
+ nvidia,pins = "gmi_a16_pj7",
+ "gmi_a19_pk7";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* PORT U */
+ pu0 {
+ nvidia,pins = "pu0";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pu1-2 {
+ nvidia,pins = "pu1", "pu2";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pu3 {
+ nvidia,pins = "pu3";
+ nvidia,function = "pwm0";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pu4 {
+ nvidia,pins = "pu4";
+ nvidia,function = "pwm1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pu5 {
+ nvidia,pins = "pu5";
+ nvidia,function = "pwm2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pu6 {
+ nvidia,pins = "pu6";
+ nvidia,function = "pwm3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* GMI section */
+ gmi-wp-n-pc7 {
+ nvidia,pins = "gmi_wp_n_pc7",
+ "gmi_adv_n_pk0",
+ "gmi_cs0_n_pj0",
+ "gmi_wr_n_pi0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-iordy-pi5 {
+ nvidia,pins = "gmi_iordy_pi5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-wait-pi7 {
+ nvidia,pins = "gmi_wait_pi7";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-clk-pk1 {
+ nvidia,pins = "gmi_clk_pk1",
+ "gmi_ad10_ph2",
+ "gmi_ad11_ph3",
+ "gmi_ad14_ph6",
+ "gmi_cs3_n_pk4";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-cs2-n-pk3 {
+ nvidia,pins = "gmi_cs2_n_pk3";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-cs4-n-pk2 {
+ nvidia,pins = "gmi_cs4_n_pk2";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-cs6-n-pi3 {
+ nvidia,pins = "gmi_cs6_n_pi3";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-cs7-n-pi6 {
+ nvidia,pins = "gmi_cs7_n_pi6";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-ad0-pg0 {
+ nvidia,pins = "gmi_ad0_pg0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-ad1-pg1 {
+ nvidia,pins = "gmi_ad1_pg1",
+ "gmi_ad4_pg4",
+ "gmi_ad5_pg5",
+ "gmi_ad6_pg6",
+ "gmi_ad7_pg7";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-ad2-pg2 {
+ nvidia,pins = "gmi_ad2_pg2",
+ "gmi_ad3_pg3",
+ "gmi_oe_n_pi1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-ad8-ph0 {
+ nvidia,pins = "gmi_ad8_ph0";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-ad9 {
+ nvidia,pins = "gmi_ad9_ph1";
+ nvidia,function = "pwm1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-ad12-ph4 {
+ nvidia,pins = "gmi_ad12_ph4";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-ad13-ph5 {
+ nvidia,pins = "gmi_ad13_ph5";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-ad15-ph7 {
+ nvidia,pins = "gmi_ad15_ph7";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-dqs-p-pj3 {
+ nvidia,pins = "gmi_dqs_p_pj3";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-rst-n-pi4 {
+ nvidia,pins = "gmi_rst_n_pi4";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-clk-lb {
+ nvidia,pins = "gmi_clk_lb";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* VI_ALT3 pinmux */
+ cam-mclk {
+ nvidia,pins = "pbb0", "cam_mclk_pcc0";
+ nvidia,function = "vi_alt3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ port-bb {
+ nvidia,pins = "pbb3", "pbb4", "pbb5",
+ "pbb6", "pbb7";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ port-cc {
+ nvidia,pins = "pcc1", "pcc2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ jtag-rtck {
+ nvidia,pins = "jtag_rtck";
+ nvidia,function = "rtck";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* KBC pinmux */
+ kb-row0-pr0 {
+ nvidia,pins = "kb_row0_pr0",
+ "kb_row1_pr1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb-row2-pr2 {
+ nvidia,pins = "kb_row2_pr2",
+ "kb_col0_pq0";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb-row3-pr3 {
+ nvidia,pins = "kb_row3_pr3";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb-row4-pr4 {
+ nvidia,pins = "kb_row4_pr4",
+ "kb_row5_pr5",
+ "kb_row6_pr6",
+ "kb_col3_pq3",
+ "kb_col4_pq4";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb-row7-pr7 {
+ nvidia,pins = "kb_row7_pr7",
+ "kb_col2_pq2",
+ "kb_col5_pq5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb-row8-ps0 {
+ nvidia,pins = "kb_row8_ps0",
+ "kb_col1_pq1",
+ "kb_col6_pq6",
+ "kb_col7_pq7";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* CORE pinmux */
+ sys-clk-req {
+ nvidia,pins = "sys_clk_req_pz5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ clk-32k-out {
+ nvidia,pins = "clk_32k_out_pa0",
+ "gmi_cs1_n_pj2";
+ nvidia,function = "soc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk-32k-in {
+ nvidia,pins = "clk_32k_in";
+ nvidia,function = "clk";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ core-pwr-req {
+ nvidia,pins = "core_pwr_req";
+ nvidia,function = "pwron";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ cpu-pwr-req {
+ nvidia,pins = "cpu_pwr_req";
+ nvidia,function = "cpu";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pwr-int-n {
+ nvidia,pins = "pwr_int_n";
+ nvidia,function = "pmi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ owr {
+ nvidia,pins = "owr";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+ };
+ reset-out-n {
+ nvidia,pins = "reset_out_n";
+ nvidia,function = "reset_out_n";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* AUD pinmux */
+ gpio-x1-aud-px1 {
+ nvidia,pins = "gpio_x1_aud_px1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gpio-x3-aud-px3 {
+ nvidia,pins = "gpio_x3_aud_px3";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gpio-x4-aud-px4 {
+ nvidia,pins = "gpio_x4_aud_px4",
+ "gpio_x5_aud_px5",
+ "gpio_x7_aud_px7";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gpio-x6-aud-px6 {
+ nvidia,pins = "gpio_x6_aud_px6";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gpio-w2-aud-pw2 {
+ nvidia,pins = "gpio_w2_aud_pw2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gpio-w3-aud-pw3 {
+ nvidia,pins = "gpio_w3_aud_pw3";
+ nvidia,function = "spi6";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ usb-vbus-en {
+ nvidia,pins = "usb_vbus_en0_pn4",
+ "usb_vbus_en1_pn5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* GPIO power/drive control */
+ drive-sdio1 {
+ nvidia,pins = "drive_sdio1";
+ nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,pull-down-strength = <36>;
+ nvidia,pull-up-strength = <20>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
+ };
+ drive-sdio3 {
+ nvidia,pins = "drive_sdio3";
+ nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,pull-down-strength = <22>;
+ nvidia,pull-up-strength = <36>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ };
+ drive-gma {
+ nvidia,pins = "drive_gma";
+ nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,pull-down-strength = <2>;
+ nvidia,pull-up-strength = <2>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ };
+ };
+ };
+
+ uartd: serial@70006300 {
+ status = "okay";
+ };
+
+ pwm: pwm@7000a000 {
+ status = "okay";
+ };
+
+ pwr_i2c: i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* Texas Instruments TPS65913 PMIC */
+ pmic: tps65913@58 {
+ compatible = "ti,tps65913";
+ reg = <0x58>;
+
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ ti,system-power-controller;
+
+ palmas_gpio: gpio {
+ compatible = "ti,palmas-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ pinmux {
+ compatible = "ti,tps65913-pinctrl";
+ ti,palmas-enable-dvfs1;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&palmas_default>;
+
+ palmas_default: pinmux {
+ pin_gpio4 {
+ pins = "gpio4";
+ function = "gpio";
+ };
+ };
+ };
+
+ pmic {
+ compatible = "ti,tps65913-pmic";
+
+ regulators {
+ avdd_3v3_lcd: smps6 {
+ regulator-name = "vdd_lcd_hv";
+ regulator-min-microvolt = <3160000>;
+ regulator-max-microvolt = <3160000>;
+ regulator-boot-on;
+ };
+
+ vdd_1v8_vio: smps8 {
+ regulator-name = "vdd_1v8_gen";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcore_emmc: smps9 {
+ regulator-name = "vdd_sdmmc";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ avdd_dsi_csi: ldo2 {
+ regulator-name = "avdd_dsi_csi";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-boot-on;
+ };
+
+ vddio_usd: ldo9 {
+ regulator-name = "vddio_sdmmc";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ avdd_usb: ldousb {
+ regulator-name = "vdd_usb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+ };
+ };
+
+ sdmmc3: sdhci@78000400 {
+ status = "okay";
+ bus-width = <4>;
+
+ cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+ power-gpios = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
+
+ nvidia,default-tap = <0x3>;
+ nvidia,default-trim = <0x3>;
+
+ vmmc-supply = <&vcore_emmc>;
+ vqmmc-supply = <&vddio_usd>;
+ };
+
+ sdmmc4: sdhci@78000600 {
+ status = "okay";
+ bus-width = <8>;
+ non-removable;
+
+ vmmc-supply = <&vcore_emmc>;
+ vqmmc-supply = <&vdd_1v8_vio>;
+ };
+
+ usb1: usb@7d000000 {
+ status = "okay";
+ dr_mode = "otg";
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+
+ enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+ pwms = <&pwm 1 1000000>;
+
+ brightness-levels = <1 35 70 105 140 175 210 255>;
+ default-brightness-level = <5>;
+ };
+
+ clk32k_in: clock-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "ref-oscillator";
+ };
+
+ extcon-keys {
+ compatible = "gpio-keys";
+
+ switch-hall-sensor {
+ label = "Hall Sensor";
+ gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
+ linux,code = <SW_LID>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key-power {
+ label = "Power";
+ gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_ENTER>;
+ };
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_UP>;
+ };
+
+ key-volume-down {
+ label = "Volume Down";
+ gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_DOWN>;
+ };
+ };
+
+ dvdd_1v8_lcd: regulator-lcdvio {
+ compatible = "regulator-fixed";
+ regulator-name = "dvdd_lcd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
diff --git a/arch/arm/dts/tegra20-motorola-daytona.dts b/arch/arm/dts/tegra20-motorola-daytona.dts
new file mode 100644
index 0000000..1be8887
--- /dev/null
+++ b/arch/arm/dts/tegra20-motorola-daytona.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra20-motorola-mot.dtsi"
+
+/ {
+ model = "Motorola Droid X2 (MB870)";
+ compatible = "motorola,daytona", "nvidia,tegra20";
+};
diff --git a/arch/arm/dts/tegra20-motorola-mot.dtsi b/arch/arm/dts/tegra20-motorola-mot.dtsi
new file mode 100644
index 0000000..f00707c
--- /dev/null
+++ b/arch/arm/dts/tegra20-motorola-mot.dtsi
@@ -0,0 +1,490 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/input/input.h>
+#include "tegra20.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uartb;
+ };
+
+ aliases {
+ i2c0 = &gen1_i2c;
+
+ spi0 = &cpcap_spi;
+
+ mmc0 = &sdmmc4; /* eMMC */
+ mmc1 = &sdmmc3; /* uSD slot */
+
+ rtc1 = "/rtc@7000e000";
+
+ usb0 = µ_usb;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000>;
+ };
+
+ host1x@50000000 {
+ dsia: dsi@54300000 {
+ clocks = <&tegra_car TEGRA20_CLK_DSI>,
+ <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
+ clock-names = "dsi", "parent";
+ status = "okay";
+
+ avdd-dsi-csi-supply = <&avdd_dsi_csi>;
+
+ panel {
+ compatible = "motorola,mot-panel";
+
+ reset-gpios = <&gpio TEGRA_GPIO(E, 3) GPIO_ACTIVE_LOW>;
+
+ vdd-supply = <&vdd_5v0_panel>;
+ vddio-supply = <&vdd_1v8_vio>;
+
+ backlight = <&backlight>;
+ };
+ };
+ };
+
+ gpio@6000d000 {
+ volume-buttons-hog {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(Q, 0) GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+
+ usb-mux-hog {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(V, 6) GPIO_ACTIVE_HIGH>;
+ output-high;
+ };
+ };
+
+ pinmux@70000014 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ crt {
+ nvidia,pins = "crtp";
+ nvidia,function = "crt";
+ };
+
+ dap1 {
+ nvidia,pins = "dap1";
+ nvidia,function = "dap1";
+ };
+
+ dap2 {
+ nvidia,pins = "dap2";
+ nvidia,function = "dap2";
+ };
+
+ dap3 {
+ nvidia,pins = "dap3";
+ nvidia,function = "dap3";
+ };
+
+ dap4 {
+ nvidia,pins = "dap4";
+ nvidia,function = "dap4";
+ };
+
+ displaya {
+ nvidia,pins = "lcsn", "ld0", "ld1", "ld3",
+ "ld5", "ld6", "ld7", "ld8",
+ "ld9", "ld12", "ld13", "ld14",
+ "ld15", "ld16", "ld17", "ldi",
+ "lhp0", "lhp1", "lhp2", "lhs",
+ "lpp", "lsc0", "lpw1", "lsda",
+ "lspi";
+ nvidia,function = "displaya";
+ };
+
+ gmi {
+ nvidia,pins = "ata", "atc", "atd", "ate",
+ "gmb", "gmd", "gpu";
+ nvidia,function = "gmi";
+ };
+
+ hdmi {
+ nvidia,pins = "hdint";
+ nvidia,function = "hdmi";
+ };
+
+ i2c1 {
+ nvidia,pins = "i2cp", "rm";
+ nvidia,function = "i2c1";
+ };
+
+ i2c2 {
+ nvidia,pins = "ddc";
+ nvidia,function = "i2c2";
+ };
+
+ i2c3 {
+ nvidia,pins = "dtf";
+ nvidia,function = "i2c3";
+ };
+
+ kbc {
+ nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+ "kbce", "kbcf";
+ nvidia,function = "kbc";
+ };
+
+ osc {
+ nvidia,pins = "cdev1", "cdev2";
+ nvidia,function = "osc";
+ };
+
+ owr {
+ nvidia,pins = "owc", "uac";
+ nvidia,function = "owr";
+ };
+
+ pcie {
+ nvidia,pins = "gpv";
+ nvidia,function = "pcie";
+ };
+
+ pwr-on {
+ nvidia,pins = "pmc";
+ nvidia,function = "pwr_on";
+ };
+
+ rsvd4 {
+ nvidia,pins = "lvp0", "lvp1", "lvs", "lsc0",
+ "ld10", "ld11", "lm1", "ld2",
+ "ld4", "ldc";
+ nvidia,function = "rsvd4";
+ };
+
+ rtck {
+ nvidia,pins = "gpu7";
+ nvidia,function = "rtck";
+ };
+
+ sdio1 {
+ nvidia,pins = "sdio1";
+ nvidia,function = "sdio1";
+ };
+
+ sdio3 {
+ nvidia,pins = "sdb", "sdc", "sdd";
+ nvidia,function = "sdio3";
+ };
+
+ sdio4 {
+ nvidia,pins = "atb", "gma", "gme";
+ nvidia,function = "sdio4";
+ };
+
+ spdif {
+ nvidia,pins = "slxc", "slxd";
+ nvidia,function = "spdif";
+ };
+
+ spi1 {
+ nvidia,pins = "spid", "spie", "spif";
+ nvidia,function = "spi1";
+ };
+
+ spi2 {
+ nvidia,pins = "spia", "spib", "spic", "spig",
+ "spih";
+ nvidia,function = "spi2";
+ };
+
+ spi3 {
+ nvidia,pins = "lm0", "lpw0", "lpw2", "lsc1";
+ nvidia,function = "spi3";
+ };
+
+ uarta {
+ nvidia,pins = "irrx", "irtx";
+ nvidia,function = "uarta";
+ };
+
+ uartc {
+ nvidia,pins = "uca", "ucb";
+ nvidia,function = "uartc";
+ };
+
+ uartd {
+ nvidia,pins = "gmc";
+ nvidia,function = "uartd";
+ };
+
+ ulpi {
+ nvidia,pins = "uab";
+ nvidia,function = "ulpi";
+ };
+
+ vi {
+ nvidia,pins = "dta", "dtb", "dtc", "dtd",
+ "dte";
+ nvidia,function = "vi";
+ };
+
+ vi-sensor-clk {
+ nvidia,pins = "csus";
+ nvidia,function = "vi_sensor_clk";
+ };
+
+ conf-lcsn {
+ nvidia,pins = "lcsn", "lpw1", "lsck", "lsda",
+ "lsdi", "ldc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+
+ conf-ata {
+ nvidia,pins = "ata", "atb", "atc", "ddc",
+ "gmc", "gpu", "kbca", "kbcb",
+ "kbcc", "kbcd", "kbce", "kbcf",
+ "lm1", "lvp0", "owc", "sdb",
+ "sdc", "sdd", "sdio1", "uaa",
+ "uad", "uca", "ucb", "pmce",
+ "lvs";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ conf-cdev1 {
+ nvidia,pins = "cdev1", "crtp", "csus", "pta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ };
+
+ conf-atd {
+ nvidia,pins = "atd", "ate", "cdev2", "dte",
+ "gma", "gmb", "gmd", "gme",
+ "gpu7", "gpv", "hdint", "i2cp",
+ "irrx", "irtx", "pmc", "rm",
+ "slxa", "slxc", "slxd", "slxk",
+ "spdi", "spdo", "spid", "spie",
+ "spif", "uda", "ck32", "ddrc",
+ "pmca", "pmcb", "pmcc", "pmcd",
+ "xm2c", "xm2d";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ conf-ld0 {
+ nvidia,pins = "ld0", "ld1", "ld2", "ld3",
+ "ld4", "ld5", "ld6", "ld7",
+ "ld8", "ld9", "ld10", "ld11",
+ "ld12", "ld13", "ld14", "ld15",
+ "ld16", "ld17", "ldi", "lhp0",
+ "lhp1", "lhp2", "lhs", "lm0",
+ "lpp", "lpw0", "lpw2", "lsc0",
+ "lsc1", "lspi", "lvp1";
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ conf-dap1 {
+ nvidia,pins = "dap1", "dap2", "dap3", "dap4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ };
+
+ conf-dta {
+ nvidia,pins = "dta", "dtb", "dtc", "dtd",
+ "dtf";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ conf-spi2 {
+ nvidia,pins = "spia", "spib", "spic", "spig",
+ "spih";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ };
+ };
+
+ uartb: serial@70006040 {
+ clocks = <&tegra_car 7>;
+ status = "okay";
+ };
+
+ gen1_i2c: i2c@7000c000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ backlight: led-controller@38 {
+ compatible = "ti,lm3532";
+ reg = <0x38>;
+
+ enable-gpios = <&gpio TEGRA_GPIO(E, 0) GPIO_ACTIVE_HIGH>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ backlight_led: led@0 {
+ reg = <0>;
+
+ led-sources = <2>;
+ led-max-microamp = <26600>;
+
+ ti,led-mode = <0>;
+ ti,linear-mapping-mode;
+
+ label = ":backlight";
+ };
+ };
+ };
+
+ cpcap_spi: spi@7000d600 {
+ status = "okay";
+ spi-max-frequency = <25000000>;
+
+ pmic: cpcap@0 {
+ compatible = "motorola,cpcap";
+ reg = <0>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ spi-cs-high;
+ spi-max-frequency = <8000000>;
+
+ power_button: button {
+ compatible = "motorola,cpcap-pwrbutton";
+
+ interrupt-parent = <&pmic>;
+ interrupts = <23 IRQ_TYPE_NONE>;
+
+ linux,code = <KEY_ENTER>;
+ };
+
+ regulator {
+ compatible = "motorola,mot-cpcap-regulator";
+
+ regulators {
+ /* SW1 is vdd_cpu */
+ /* SW2 is vdd_core */
+
+ vdd_1v8_vio: sw3 {
+ regulator-name = "vdd_1v8_vio";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* SW4 is vdd_aon (rtc) */
+
+ vcore_emmc: vsdio {
+ regulator-name = "vcore_emmc";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ avdd_dsi_csi: vcsi {
+ regulator-name = "avdd_dsi_csi";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-boot-on;
+ };
+
+ vddio_usd: vsimcard {
+ regulator-name = "vddio_usd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-boot-on;
+ };
+
+ avdd_3v3_periph: vusb {
+ regulator-name = "avdd_usb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+ };
+ };
+
+ micro_usb: usb@c5000000 {
+ status = "okay";
+ dr_mode = "otg";
+ };
+
+ usb-phy@c5000000 {
+ status = "okay";
+ vbus-supply = <&avdd_3v3_periph>;
+ };
+
+ sdmmc3: sdhci@c8000400 {
+ status = "okay";
+ bus-width = <4>;
+
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+
+ vmmc-supply = <&vdd_usd>;
+ vqmmc-supply = <&vddio_usd>;
+ };
+
+ sdmmc4: sdhci@c8000600 {
+ status = "okay";
+ bus-width = <8>;
+ non-removable;
+
+ vmmc-supply = <&vcore_emmc>;
+ vqmmc-supply = <&vdd_1v8_vio>;
+ };
+
+ /* 32KHz oscillator which is used by PMC */
+ clk32k_in: clock-32k-in {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "ref-oscillator";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key-volume-down {
+ label = "Volume Down";
+ gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_DOWN>;
+ };
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_UP>;
+ };
+ };
+
+ gpio-poweroff {
+ compatible = "gpio-poweroff";
+ gpios = <&gpio TEGRA_GPIO(V, 7) GPIO_ACTIVE_LOW>;
+ timeout-ms = <500>;
+ };
+
+ vdd_5v0_panel: regulator-panel {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v0_disp";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(F, 7) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_usd: regulator-usd {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_usd";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpio TEGRA_GPIO(F, 3) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
diff --git a/arch/arm/dts/tegra20-motorola-olympus.dts b/arch/arm/dts/tegra20-motorola-olympus.dts
new file mode 100644
index 0000000..bba5513
--- /dev/null
+++ b/arch/arm/dts/tegra20-motorola-olympus.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra20-motorola-mot.dtsi"
+
+/ {
+ model = "Motorola Atrix 4G (MB860)";
+ compatible = "motorola,olympus", "nvidia,tegra20";
+};
diff --git a/arch/arm/dts/zynq-binman-brcp1.dtsi b/arch/arm/dts/zynq-binman-brcp1.dtsi
new file mode 100644
index 0000000..3cc8ee8
--- /dev/null
+++ b/arch/arm/dts/zynq-binman-brcp1.dtsi
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 B&R Industrial Automation GmbH
+ */
+
+ #include <config.h>
+
+/ {
+ binman {
+ bootph-all;
+ filename = "flash.bin";
+ pad-byte = <0xff>;
+ align-size = <16>;
+ align = <16>;
+
+ blob@0 {
+ filename = "spl/boot.bin";
+ offset = <0x0>;
+ };
+
+ fit {
+ description = "U-Boot BR Zynq boards";
+ offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
+
+ images {
+ uboot {
+ description = "U-Boot BR Zynq";
+ type = "firmware";
+ os = "u-boot";
+ arch = "arm";
+ compression = "none";
+ load = <CONFIG_TEXT_BASE>;
+ u-boot-nodtb {
+ };
+ };
+
+ fdt-0 {
+ description = "DTB BR Zynq";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ u-boot-dtb {
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "BR Zynq";
+ firmware = "uboot";
+ fdt = "fdt-0";
+ };
+ };
+ };
+
+ blob-ext@0 {
+ filename = "blobs/cfg.img";
+ offset = <0xC0000>;
+ size = <0x10000>;
+ optional;
+ };
+
+ blob-ext@5 {
+ filename = "blobs/cfg_opt.img";
+ offset = <0xD0000>;
+ size = <0x10000>;
+ optional;
+ };
+
+ blob-ext@1 {
+ bootph-all;
+ filename = "blobs/bitstream.bit";
+ offset = <0x100000>;
+ size = <0x200000>;
+ optional;
+ };
+
+ blob-ext@4 {
+ bootph-all;
+ filename = "blobs/bitstream_update.bit";
+ offset = <0x400000>;
+ size = <0x200000>;
+ optional;
+ };
+
+ blob-ext@2 {
+ filename = "blobs/bootar.itb";
+ offset = <0x900000>;
+ size = <0x600000>;
+ optional;
+ };
+
+ blob-ext@3 {
+ filename = "blobs/dtb.bin";
+ offset = <0xF00000>;
+ size = <0x100000>;
+ optional;
+ };
+ };
+};
diff --git a/arch/arm/dts/zynq-brcp1.dtsi b/arch/arm/dts/zynq-brcp1.dtsi
new file mode 100644
index 0000000..ebaf42d
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1.dtsi
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/include/ "zynq-7000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "BRCP1 CPU";
+ compatible = "br,cp1",
+ "xlnx,zynq-7000";
+
+ aliases {
+ i2c0 = &i2c0;
+ serial0 = &uart0;
+ spi0 = &qspi;
+ mmc0 = &sdhci0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x40000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+
+ brd_rst: board_reset {
+ compatible = "br,board-reset";
+ pin = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ se_green {
+ label = "S_E_GREEN";
+ gpios = <&ledgpio 0 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ se_red {
+ label = "S_E_RED";
+ gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ rdy_f_yellow {
+ label = "RDY_F_YELLOW";
+ gpios = <&ledgpio 2 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ re_green {
+ label = "R_E_GREEN";
+ gpios = <&ledgpio 3 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ re_red {
+ label = "R_E_RED";
+ gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ plk_se_green {
+ label = "PLK_S_E_GREEN";
+ gpios = <&ledgpio 5 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ eth_se_green {
+ label = "ETH_S_E_GREEN";
+ gpios = <&ledgpio 6 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ ledgpio: max7320@5d { /* board LED */
+ status = "okay";
+ compatible = "maxim,max7320";
+ reg = <0x5d>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ ngpios = <8>;
+ };
+
+ pmic0: da9062@58 {
+ compatible = "dlg,da9062";
+ reg = <0x58>;
+ };
+};
+
+&sdhci0 {
+ status = "okay";
+ max-frequency = <25000000>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+ spi-max-frequency = <100000000>;
+
+ spi_flash: spiflash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1";
+ spi-max-frequency = <100000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+};
+
+&gpio0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/zynq-brcp150-u-boot.dtsi b/arch/arm/dts/zynq-brcp150-u-boot.dtsi
new file mode 100644
index 0000000..1bfd5f2
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp150-u-boot.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+#include "zynq-binman-brcp1.dtsi"
+
+&i2c0 {
+ bootph-all;
+};
+
+&uart0 {
+ bootph-all;
+};
+
+&qspi {
+ bootph-all;
+};
+
+&spi_flash {
+ bootph-all;
+};
+
+&gpio0 {
+ bootph-all;
+};
+
+&brd_rst {
+ bootph-all;
+};
+
+&rs232_en {
+ bootph-all;
+};
diff --git a/arch/arm/dts/zynq-brcp150.dts b/arch/arm/dts/zynq-brcp150.dts
new file mode 100644
index 0000000..1b22d37
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp150.dts
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "BRCP150 CPU";
+ compatible = "br,cp150",
+ "xlnx,zynq-7000";
+
+ aliases {
+ i2c0 = &i2c0;
+ serial0 = &uart0;
+ spi0 = &qspi;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x20000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+
+ brd_rst: board_reset {
+ compatible = "br,board-reset";
+ pin = <&gpio0 27 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* Put this pin active high to enable RS232 debug serial */
+ rs232_en: rs232_enable {
+ compatible = "br,rs232-en";
+ pin = <&gpio0 52 GPIO_ACTIVE_HIGH>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ re_green {
+ label = "R_E_GREEN";
+ gpios = <&ledgpio 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ re_red {
+ label = "R_E_RED";
+ gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ rdy_f_red {
+ label = "RDY_F_RED";
+ gpios = <&ledgpio 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ rdy_f_yellow {
+ label = "RDY_F_YELLOW";
+ gpios = <&ledgpio 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ se_green {
+ label = "S_E_GREEN";
+ gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ se_red {
+ label = "S_E_RED";
+ gpios = <&ledgpio 5 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ plk_se_green {
+ label = "PLK_S_E_GREEN";
+ gpios = <&ledgpio 6 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ eth_se_green {
+ label = "ETH_S_E_GREEN";
+ gpios = <&ledgpio 7 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ user1_green {
+ label = "USER1_GREEN";
+ gpios = <&ledgpio 12 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ user1_red {
+ label = "USER1_RED";
+ gpios = <&ledgpio 13 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ user2_green {
+ label = "USER2_GREEN";
+ gpios = <&ledgpio 14 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ user2_red {
+ label = "USER2_RED";
+ gpios = <&ledgpio 15 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "mii";
+ phy-handle = <ðernet_phy>;
+
+ ethernet_phy: emio-phy@2 {
+ reg = <2>;
+ max-speed = <100>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ ledgpio: max7320@5d { /* board LED */
+ status = "okay";
+ compatible = "maxim,max7320";
+ reg = <0x5d>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ ngpios = <16>;
+ };
+};
+
+&sdhci0 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+ spi-max-frequency = <100000000>;
+
+ spi_flash: spiflash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1";
+ spi-max-frequency = <100000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+/* Since the gem0 clock is configured EMIO this dummy entry is needed */
+&clkc {
+ clocks = <&clkc 16>;
+ clock-names = "gem0_emio_clk";
+};
diff --git a/arch/arm/dts/zynq-brcp170-u-boot.dtsi b/arch/arm/dts/zynq-brcp170-u-boot.dtsi
new file mode 100644
index 0000000..ceea610
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp170-u-boot.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+#include "zynq-binman-brcp1.dtsi"
+
+&i2c0 {
+ bootph-all;
+};
+
+&uart0 {
+ bootph-all;
+};
+
+&qspi {
+ bootph-all;
+};
+
+&spi_flash {
+ bootph-all;
+};
+
+&gpio0 {
+ bootph-all;
+};
diff --git a/arch/arm/dts/zynq-brcp170.dts b/arch/arm/dts/zynq-brcp170.dts
new file mode 100644
index 0000000..eee19ce
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp170.dts
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "BRCP170 CPU";
+ compatible = "br,cp170",
+ "xlnx,zynq-7000";
+
+ aliases {
+ i2c0 = &i2c0;
+ serial0 = &uart0;
+ spi0 = &qspi;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x20000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ re_green {
+ label = "R_E_GREEN";
+ gpios = <&ledgpio 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ re_red {
+ label = "R_E_RED";
+ gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ rdy_f_red {
+ label = "RDY_F_RED";
+ gpios = <&ledgpio 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ rdy_f_yellow {
+ label = "RDY_F_YELLOW";
+ gpios = <&ledgpio 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ se_green {
+ label = "S_E_GREEN";
+ gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ se_red {
+ label = "S_E_RED";
+ gpios = <&ledgpio 5 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ plk_se_green {
+ label = "PLK_S_E_GREEN";
+ gpios = <&ledgpio 6 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ eth_se_green {
+ label = "ETH_S_E_GREEN";
+ gpios = <&ledgpio 7 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+
+ ethernet_phy: ethernet-phy@0 {
+ reg = <0>;
+ max-speed = <100>;
+ ti,rx-internal-delay = <7>;
+ ti,tx-internal-delay = <7>;
+ ti,fifo-depth = <0>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ ledgpio: max7320@58 { /* board LED */
+ status = "okay";
+ compatible = "maxim,max7320";
+ reg = <0x58>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ ngpios = <8>;
+ };
+};
+
+&sdhci0 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+ spi-max-frequency = <100000000>;
+
+ spi_flash: spiflash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1";
+ spi-max-frequency = <100000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+};
+
+&gpio0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi b/arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi
new file mode 100644
index 0000000..58c4558
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+#include "zynq-binman-brcp1.dtsi"
+
+&i2c0 {
+ bootph-all;
+};
+
+&uart0 {
+ bootph-all;
+};
+
+&qspi {
+ bootph-all;
+};
+
+&spi_flash {
+ bootph-all;
+};
+
+&gpio0 {
+ bootph-all;
+};
+
+&brd_rst {
+ bootph-all;
+};
diff --git a/arch/arm/dts/zynq-brcp1_1r.dts b/arch/arm/dts/zynq-brcp1_1r.dts
new file mode 100644
index 0000000..fd7ae55
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1_1r.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+#include "zynq-brcp1.dtsi"
+
+/ {
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+
+ ethernet_phy: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <7>;
+ ti,tx-internal-delay = <7>;
+ ti,fifo-depth = <0>;
+ max-speed = <1000>;
+ };
+};
diff --git a/arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi b/arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi
new file mode 120000
index 0000000..5a31a05
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi
@@ -0,0 +1 @@
+zynq-brcp1_1r-u-boot.dtsi
\ No newline at end of file
diff --git a/arch/arm/dts/zynq-brcp1_1r_switch.dts b/arch/arm/dts/zynq-brcp1_1r_switch.dts
new file mode 100644
index 0000000..a68d530
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1_1r_switch.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+#include "zynq-brcp1.dtsi"
+
+/ {
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "gmii";
+
+ fixed-link {
+ speed = <100>;
+ full-duplex;
+ };
+};
+
+/* Since the gem0 clock is configured EMIO this dummy entry is needed */
+&clkc {
+ clocks = <&clkc 16>;
+ clock-names = "gem0_emio_clk";
+};
diff --git a/arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi b/arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi
new file mode 120000
index 0000000..5a31a05
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi
@@ -0,0 +1 @@
+zynq-brcp1_1r-u-boot.dtsi
\ No newline at end of file
diff --git a/arch/arm/dts/zynq-brcp1_2r.dts b/arch/arm/dts/zynq-brcp1_2r.dts
new file mode 100644
index 0000000..353d8a1
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1_2r.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+#include "zynq-brcp1.dtsi"
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+
+ ethernet_phy: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <7>;
+ ti,tx-internal-delay = <7>;
+ ti,fifo-depth = <0>;
+ max-speed = <1000>;
+ };
+};
diff --git a/arch/arm/dts/zynq-brsmarc2-u-boot.dtsi b/arch/arm/dts/zynq-brsmarc2-u-boot.dtsi
new file mode 100644
index 0000000..58c4558
--- /dev/null
+++ b/arch/arm/dts/zynq-brsmarc2-u-boot.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+#include "zynq-binman-brcp1.dtsi"
+
+&i2c0 {
+ bootph-all;
+};
+
+&uart0 {
+ bootph-all;
+};
+
+&qspi {
+ bootph-all;
+};
+
+&spi_flash {
+ bootph-all;
+};
+
+&gpio0 {
+ bootph-all;
+};
+
+&brd_rst {
+ bootph-all;
+};
diff --git a/arch/arm/dts/zynq-brsmarc2.dts b/arch/arm/dts/zynq-brsmarc2.dts
new file mode 100644
index 0000000..32f873d
--- /dev/null
+++ b/arch/arm/dts/zynq-brsmarc2.dts
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "BRSMARC2 CPU";
+ compatible = "br,smarc2",
+ "xlnx,zynq-7000";
+
+ aliases {
+ i2c0 = &i2c0;
+ serial0 = &uart0;
+ spi0 = &qspi;
+ mmc0 = &sdhci0;
+ can0 = &can0;
+ can1 = &can1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x10000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+
+ brd_rst: board_reset {
+ compatible = "br,board-reset";
+ pin = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ plk_se_green {
+ label = "PLK_S_E_GREEN";
+ gpios = <&ledgpio 0 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ plk_se_red {
+ label = "PLK_S_E_RED";
+ gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ rdy_f_yellow {
+ label = "RDY_F_YELLOW";
+ gpios = <&ledgpio 2 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ re_green {
+ label = "R_E_GREEN";
+ gpios = <&ledgpio 3 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ re_red {
+ label = "R_E_RED";
+ gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy0>;
+
+ ethernet_phy0: ethernet-phy@1 {
+ ti,ledcr = <0x0480>;
+ ti,rgmii-rxclk-shift;
+ reg = <1>;
+ };
+};
+
+&gem1 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy1>;
+ mac-address = [ 00 00 00 00 00 00 ];
+
+ ethernet_phy1: ethernet-phy@3{
+ ti,ledcr = <0x0480>;
+ reg = <3>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ resetc: rststm@60 { /* reset controller */
+ compatible = "bur,rststm";
+ reg = <0x60>;
+ hit-gpios = <&gpio0 84 GPIO_ACTIVE_HIGH>;
+ cooling-min-state = <0>;
+ cooling-max-state = <1>; /* reset gets fired */
+ #cooling-cells = <2>; /* min followed by max */
+ };
+
+ ledgpio: max7320@5d { /* board LED */
+ status = "okay";
+ compatible = "maxim,max7320";
+ reg = <0x5d>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ ngpios = <8>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&sdhci0 {
+ status = "okay";
+ max-frequency = <25000000>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+ spi-max-frequency = <100000000>;
+
+ spi_flash: spiflash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1";
+ spi-max-frequency = <100000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+};
diff --git a/arch/arm/dts/zynq-topic-miami.dts b/arch/arm/dts/zynq-topic-miami.dts
index 8307a2e..73eea37 100644
--- a/arch/arm/dts/zynq-topic-miami.dts
+++ b/arch/arm/dts/zynq-topic-miami.dts
@@ -11,6 +11,10 @@
model = "Topic Miami Zynq Board";
compatible = "topic,miami", "xlnx,zynq-7000";
+ config {
+ u-boot,spl-payload-offset = <0x20000>;
+ };
+
aliases {
serial0 = &uart0;
spi0 = &qspi;
@@ -35,6 +39,7 @@
status = "okay";
num-cs = <1>;
flash@0 {
+ bootph-all;
compatible = "st,m25p80", "n25q256a", "jedec,spi-nor";
m25p,fast-read;
reg = <0x0>;
@@ -44,24 +49,12 @@
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
- label = "qspi-u-boot-spl";
- reg = <0x00000 0x10000>;
- };
- partition@10000 {
- label = "qspi-u-boot-img";
- reg = <0x10000 0x60000>;
+ label = "qspi-boot-bin";
+ reg = <0x00000 0x100000>;
};
- partition@70000 {
- label = "qspi-device-tree";
- reg = <0x70000 0x10000>;
- };
- partition@80000 {
- label = "qspi-linux";
- reg = <0x80000 0x400000>;
- };
- partition@480000 {
+ partition@100000 {
label = "qspi-rootfs";
- reg = <0x480000 0x1b80000>;
+ reg = <0x100000 0>;
};
};
};
@@ -74,6 +67,14 @@
&i2c1 {
status = "okay";
clock-frequency = <400000>;
+ /* GPIO expander */
+ gpioex: gpio@41 {
+ compatible = "nxp,pca9536";
+ reg = <0x41>;
+ gpio-line-names = "USB_RESET", "VTT_SHDWN_N", "V_PRESENT", "DEBUG_PRESENT";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
};
&clkc {
diff --git a/arch/arm/dts/zynqmp-binman-som.dts b/arch/arm/dts/zynqmp-binman-som.dts
index d5b63ef..a70123f 100644
--- a/arch/arm/dts/zynqmp-binman-som.dts
+++ b/arch/arm/dts/zynqmp-binman-som.dts
@@ -2,13 +2,19 @@
/*
* dts file for Xilinx ZynqMP SOMs (k24/k26)
*
- * (C) Copyright 2024, Advanced Micro Devices, Inc.
+ * (C) Copyright 2024-2025, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
#include <config.h>
+#if defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME)
+#define U_BOOT_ITB_FILENAME CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
+#else
+#define U_BOOT_ITB_FILENAME "u-boot.itb"
+#endif
+
/dts-v1/;
/ {
binman: binman {
@@ -103,9 +109,9 @@
};
};
- /* u-boot.itb generation in a static way */
+ /* Generation in a static way */
itb {
- filename = "u-boot.itb";
+ filename = U_BOOT_ITB_FILENAME;
pad-byte = <0>;
fit {
@@ -227,7 +233,7 @@
};
blob-ext@2 {
offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
- filename = "u-boot.itb";
+ filename = U_BOOT_ITB_FILENAME;
};
fdtmap {
};
diff --git a/arch/arm/dts/zynqmp-binman.dts b/arch/arm/dts/zynqmp-binman.dts
index 252c2ad..59c1388 100644
--- a/arch/arm/dts/zynqmp-binman.dts
+++ b/arch/arm/dts/zynqmp-binman.dts
@@ -2,22 +2,28 @@
/*
* dts file for Xilinx ZynqMP platforms
*
- * (C) Copyright 2024, Advanced Micro Devices, Inc.
+ * (C) Copyright 2024-2025, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
#include <config.h>
+#if defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME)
+#define U_BOOT_ITB_FILENAME CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
+#else
+#define U_BOOT_ITB_FILENAME "u-boot.itb"
+#endif
+
/dts-v1/;
/ {
binman: binman {
multiple-images;
#ifdef CONFIG_SPL
- /* u-boot.itb generation in a static way */
+ /* Generation in a static way */
itb {
- filename = "u-boot.itb";
+ filename = U_BOOT_ITB_FILENAME;
pad-byte = <0>;
fit {
@@ -196,7 +202,7 @@
};
blob-ext@2 {
offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
- filename = "u-boot.itb";
+ filename = U_BOOT_ITB_FILENAME;
};
fdtmap {
};
diff --git a/arch/arm/include/asm/arch-apple/rtkit.h b/arch/arm/include/asm/arch-apple/rtkit.h
index eff18dd..4b11e2a 100644
--- a/arch/arm/include/asm/arch-apple/rtkit.h
+++ b/arch/arm/include/asm/arch-apple/rtkit.h
@@ -12,6 +12,7 @@
u64 dva;
size_t size;
bool is_mapped;
+ int endpoint;
};
typedef int (*apple_rtkit_shmem_setup)(void *cookie,
@@ -26,4 +27,8 @@
apple_rtkit_shmem_destroy shmem_destroy);
void apple_rtkit_free(struct apple_rtkit *rtk);
int apple_rtkit_boot(struct apple_rtkit *rtk);
+int apple_rtkit_set_ap_power(struct apple_rtkit *rtk, int pwrstate);
+int apple_rtkit_poll(struct apple_rtkit *rtk, ulong timeout);
int apple_rtkit_shutdown(struct apple_rtkit *rtk, int pwrstate);
+
+int apple_rtkit_helper_poll(struct udevice *dev, ulong timeout);
diff --git a/arch/arm/include/asm/arch-rk3528/boot0.h b/arch/arm/include/asm/arch-rk3528/boot0.h
new file mode 100644
index 0000000..8ae46f2
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3528/boot0.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* Copyright Contributors to the U-Boot project. */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3528/gpio.h b/arch/arm/include/asm/arch-rk3528/gpio.h
new file mode 100644
index 0000000..5516e64
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3528/gpio.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* Copyright Contributors to the U-Boot project. */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3576/boot0.h b/arch/arm/include/asm/arch-rk3576/boot0.h
new file mode 100644
index 0000000..dea2b20
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3576/boot0.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3576/gpio.h b/arch/arm/include/asm/arch-rk3576/gpio.h
new file mode 100644
index 0000000..b48c0a5
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3576/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
index 73e5283..3c20450 100644
--- a/arch/arm/include/asm/arch-rockchip/clock.h
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -15,6 +15,13 @@
#define RKCLK_PLL_MODE_NORMAL 1
#define RKCLK_PLL_MODE_DEEP 2
+/*
+ * PLL flags
+ */
+#define ROCKCHIP_PLL_SYNC_RATE BIT(0)
+/* normal mode only. now only for pll_rk3036, pll_rk3328 type */
+#define ROCKCHIP_PLL_FIXED_MODE BIT(1)
+
enum {
ROCKCHIP_SYSCON_NOC,
ROCKCHIP_SYSCON_GRF,
@@ -208,6 +215,26 @@
int rockchip_reset_bind_lut(struct udevice *pdev, const int *lookup_table,
u32 reg_offset, u32 reg_number);
/*
+ * rk3528_reset_bind_lut() - Bind soft reset device as child of clock device
+ * using dedicated RK3528 lookup table
+ *
+ * @pdev: clock udevice
+ * @reg_offset: the first offset in cru for softreset registers
+ * @reg_number: the reg numbers of softreset registers
+ * Return: 0 success, or error value
+ */
+int rk3528_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number);
+/*
+ * rk3576_reset_bind_lut() - Bind soft reset device as child of clock device
+ * using dedicated RK3576 lookup table
+ *
+ * @pdev: clock udevice
+ * @reg_offset: the first offset in cru for softreset registers
+ * @reg_number: the reg numbers of softreset registers
+ * Return: 0 success, or error value
+ */
+int rk3576_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number);
+/*
* rk3588_reset_bind_lut() - Bind soft reset device as child of clock device
* using dedicated RK3588 lookup table
*
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3528.h b/arch/arm/include/asm/arch-rockchip/cru_rk3528.h
new file mode 100644
index 0000000..b402095
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3528.h
@@ -0,0 +1,388 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ * Author: Joseph Chen <chenjh@rock-chips.com>
+ */
+
+#ifndef _ASM_ARCH_CRU_RK3528_H
+#define _ASM_ARCH_CRU_RK3528_H
+
+#define MHz 1000000
+#define KHz 1000
+#define OSC_HZ (24 * MHz)
+
+#define CPU_PVTPLL_HZ (1200 * MHz)
+#define APLL_HZ (600 * MHz)
+#define GPLL_HZ (1188 * MHz)
+#define CPLL_HZ (996 * MHz)
+#define PPLL_HZ (1000 * MHz)
+
+/* RK3528 pll id */
+enum rk3528_pll_id {
+ APLL,
+ CPLL,
+ GPLL,
+ PPLL,
+ DPLL,
+ PLL_COUNT,
+};
+
+struct rk3528_clk_priv {
+ struct rk3528_cru *cru;
+ unsigned long ppll_hz;
+ unsigned long gpll_hz;
+ unsigned long cpll_hz;
+ unsigned long armclk_hz;
+ unsigned long armclk_enter_hz;
+ unsigned long armclk_init_hz;
+ bool sync_kernel;
+};
+
+struct rk3528_pll {
+ unsigned int con0;
+ unsigned int con1;
+ unsigned int con2;
+ unsigned int con3;
+ unsigned int con4;
+ unsigned int reserved0[3];
+};
+
+#define RK3528_CRU_BASE ((struct rk3528_cru *)0xff4a0000)
+
+struct rk3528_cru {
+ unsigned int apll_con[5];
+ unsigned int reserved0014[3];
+ unsigned int cpll_con[5];
+ unsigned int reserved0034[11];
+ unsigned int gpll_con[5];
+ unsigned int reserved0074[51 + 32];
+ unsigned int reserved01c0[48];
+ unsigned int mode_con[1];
+ unsigned int reserved0284[31];
+ unsigned int clksel_con[91];
+ unsigned int reserved046c[229];
+ unsigned int gate_con[46];
+ unsigned int reserved08b8[82];
+ unsigned int softrst_con[47];
+ unsigned int reserved0abc[81];
+ unsigned int glb_cnt_th;
+ unsigned int glb_rst_st;
+ unsigned int glb_srst_fst;
+ unsigned int glb_srst_snd;
+ unsigned int glb_rst_con;
+ unsigned int reserved0c14[6];
+ unsigned int corewfi_con;
+ unsigned int reserved0c30[15604];
+
+ /* pmucru */
+ unsigned int reserved10000[192];
+ unsigned int pmuclksel_con[3];
+ unsigned int reserved1030c[317];
+ unsigned int pmugate_con[3];
+ unsigned int reserved1080c[125];
+ unsigned int pmusoftrst_con[3];
+ unsigned int reserved10a08[7550 + 8191];
+
+ /* pciecru */
+ unsigned int reserved20000[32];
+ unsigned int ppll_con[5];
+ unsigned int reserved20094[155];
+ unsigned int pcieclksel_con[2];
+ unsigned int reserved20308[318];
+ unsigned int pciegate_con;
+};
+
+check_member(rk3528_cru, pciegate_con, 0x20800);
+
+struct pll_rate_table {
+ unsigned long rate;
+ unsigned int fbdiv;
+ unsigned int postdiv1;
+ unsigned int refdiv;
+ unsigned int postdiv2;
+ unsigned int dsmpd;
+ unsigned int frac;
+};
+
+#define RK3528_PMU_CRU_BASE 0x10000
+#define RK3528_PCIE_CRU_BASE 0x20000
+#define RK3528_DDRPHY_CRU_BASE 0x28000
+#define RK3528_PLL_CON(x) ((x) * 0x4)
+#define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE)
+#define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE)
+#define RK3528_MODE_CON 0x280
+#define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
+#define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE)
+#define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE)
+#define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE)
+
+#define RK3528_DIV_ACLK_M_CORE_SHIFT 11
+#define RK3528_DIV_ACLK_M_CORE_MASK (0x1f << RK3528_DIV_ACLK_M_CORE_SHIFT)
+#define RK3528_DIV_PCLK_DBG_SHIFT 1
+#define RK3528_DIV_PCLK_DBG_MASK (0x1f << RK3528_DIV_PCLK_DBG_SHIFT)
+
+enum {
+ /* CRU_CLKSEL_CON00 */
+ CLK_MATRIX_50M_SRC_DIV_SHIFT = 2,
+ CLK_MATRIX_50M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_50M_SRC_DIV_SHIFT,
+ CLK_MATRIX_100M_SRC_DIV_SHIFT = 7,
+ CLK_MATRIX_100M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_100M_SRC_DIV_SHIFT,
+
+ /* CRU_CLKSEL_CON01 */
+ CLK_MATRIX_150M_SRC_DIV_SHIFT = 0,
+ CLK_MATRIX_150M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_150M_SRC_DIV_SHIFT,
+ CLK_MATRIX_200M_SRC_DIV_SHIFT = 5,
+ CLK_MATRIX_200M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_200M_SRC_DIV_SHIFT,
+ CLK_MATRIX_250M_SRC_DIV_SHIFT = 10,
+ CLK_MATRIX_250M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_250M_SRC_DIV_SHIFT,
+ CLK_MATRIX_250M_SRC_SEL_SHIFT = 15,
+ CLK_MATRIX_250M_SRC_SEL_MASK = 0x1 << CLK_MATRIX_250M_SRC_SEL_SHIFT,
+
+ /* CRU_CLKSEL_CON02 */
+ CLK_MATRIX_300M_SRC_DIV_SHIFT = 0,
+ CLK_MATRIX_300M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_300M_SRC_DIV_SHIFT,
+ CLK_MATRIX_339M_SRC_DIV_SHIFT = 5,
+ CLK_MATRIX_339M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_339M_SRC_DIV_SHIFT,
+ CLK_MATRIX_400M_SRC_DIV_SHIFT = 10,
+ CLK_MATRIX_400M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_400M_SRC_DIV_SHIFT,
+
+ /* CRU_CLKSEL_CON03 */
+ CLK_MATRIX_500M_SRC_DIV_SHIFT = 6,
+ CLK_MATRIX_500M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_500M_SRC_DIV_SHIFT,
+ CLK_MATRIX_500M_SRC_SEL_SHIFT = 11,
+ CLK_MATRIX_500M_SRC_SEL_MASK = 0x1 << CLK_MATRIX_500M_SRC_SEL_SHIFT,
+
+ /* CRU_CLKSEL_CON04 */
+ CLK_MATRIX_600M_SRC_DIV_SHIFT = 0,
+ CLK_MATRIX_600M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_600M_SRC_DIV_SHIFT,
+ CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX = 0U,
+ CLK_MATRIX_250M_SRC_SEL_CLK_CPLL_MUX = 1U,
+ CLK_MATRIX_500M_SRC_SEL_CLK_GPLL_MUX = 0U,
+ CLK_MATRIX_500M_SRC_SEL_CLK_CPLL_MUX = 1U,
+
+ /* PMUCRU_CLKSEL_CON00 */
+ CLK_I2C2_SEL_SHIFT = 0,
+ CLK_I2C2_SEL_MASK = 0x3 << CLK_I2C2_SEL_SHIFT,
+
+ /* PCIE_CRU_CLKSEL_CON01 */
+ PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT = 7,
+ PCIE_CLK_MATRIX_50M_SRC_DIV_MASK = 0x1f << PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT,
+ PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT = 11,
+ PCIE_CLK_MATRIX_100M_SRC_DIV_MASK = 0x1f << PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT,
+
+ /* CRU_CLKSEL_CON32 */
+ DCLK_VOP_SRC0_SEL_SHIFT = 10,
+ DCLK_VOP_SRC0_SEL_MASK = 0x1 << DCLK_VOP_SRC0_SEL_SHIFT,
+ DCLK_VOP_SRC0_DIV_SHIFT = 2,
+ DCLK_VOP_SRC0_DIV_MASK = 0xFF << DCLK_VOP_SRC0_DIV_SHIFT,
+
+ /* CRU_CLKSEL_CON33 */
+ DCLK_VOP_SRC1_SEL_SHIFT = 8,
+ DCLK_VOP_SRC1_SEL_MASK = 0x1 << DCLK_VOP_SRC1_SEL_SHIFT,
+ DCLK_VOP_SRC1_DIV_SHIFT = 0,
+ DCLK_VOP_SRC1_DIV_MASK = 0xFF << DCLK_VOP_SRC1_DIV_SHIFT,
+
+ /* CRU_CLKSEL_CON43 */
+ CLK_CORE_CRYPTO_SEL_SHIFT = 14,
+ CLK_CORE_CRYPTO_SEL_MASK = 0x3 << CLK_CORE_CRYPTO_SEL_SHIFT,
+ ACLK_BUS_VOPGL_ROOT_DIV_SHIFT = 0U,
+ ACLK_BUS_VOPGL_ROOT_DIV_MASK = 0x7U << ACLK_BUS_VOPGL_ROOT_DIV_SHIFT,
+
+ /* CRU_CLKSEL_CON44 */
+ CLK_PWM0_SEL_SHIFT = 6,
+ CLK_PWM0_SEL_MASK = 0x3 << CLK_PWM0_SEL_SHIFT,
+ CLK_PWM1_SEL_SHIFT = 8,
+ CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT,
+ CLK_PWM0_SEL_CLK_MATRIX_100M_SRC = 0U,
+ CLK_PWM0_SEL_CLK_MATRIX_50M_SRC = 1U,
+ CLK_PWM0_SEL_XIN_OSC0_FUNC = 2U,
+ CLK_PWM1_SEL_CLK_MATRIX_100M_SRC = 0U,
+ CLK_PWM1_SEL_CLK_MATRIX_50M_SRC = 1U,
+ CLK_PWM1_SEL_XIN_OSC0_FUNC = 2U,
+ CLK_PKA_CRYPTO_SEL_SHIFT = 0,
+ CLK_PKA_CRYPTO_SEL_MASK = 0x3 << CLK_PKA_CRYPTO_SEL_SHIFT,
+ CLK_CORE_CRYPTO_SEL_CLK_MATRIX_300M_SRC = 0U,
+ CLK_CORE_CRYPTO_SEL_CLK_MATRIX_200M_SRC = 1U,
+ CLK_CORE_CRYPTO_SEL_CLK_MATRIX_100M_SRC = 2U,
+ CLK_CORE_CRYPTO_SEL_XIN_OSC0_FUNC = 3U,
+ CLK_PKA_CRYPTO_SEL_CLK_MATRIX_300M_SRC = 0U,
+ CLK_PKA_CRYPTO_SEL_CLK_MATRIX_200M_SRC = 1U,
+ CLK_PKA_CRYPTO_SEL_CLK_MATRIX_100M_SRC = 2U,
+ CLK_PKA_CRYPTO_SEL_XIN_OSC0_FUNC = 3U,
+
+ /* CRU_CLKSEL_CON60 */
+ CLK_MATRIX_25M_SRC_DIV_SHIFT = 2,
+ CLK_MATRIX_25M_SRC_DIV_MASK = 0xff << CLK_MATRIX_25M_SRC_DIV_SHIFT,
+ CLK_MATRIX_125M_SRC_DIV_SHIFT = 10,
+ CLK_MATRIX_125M_SRC_DIV_MASK = 0x1f << CLK_MATRIX_125M_SRC_DIV_SHIFT,
+
+ /* CRU_CLKSEL_CON61 */
+ SCLK_SFC_DIV_SHIFT = 6,
+ SCLK_SFC_DIV_MASK = 0x3F << SCLK_SFC_DIV_SHIFT,
+ SCLK_SFC_SEL_SHIFT = 12,
+ SCLK_SFC_SEL_MASK = 0x3 << SCLK_SFC_SEL_SHIFT,
+ SCLK_SFC_SEL_CLK_GPLL_MUX = 0U,
+ SCLK_SFC_SEL_CLK_CPLL_MUX = 1U,
+ SCLK_SFC_SEL_XIN_OSC0_FUNC = 2U,
+
+ /* CRU_CLKSEL_CON62 */
+ CCLK_SRC_EMMC_DIV_SHIFT = 0,
+ CCLK_SRC_EMMC_DIV_MASK = 0x3F << CCLK_SRC_EMMC_DIV_SHIFT,
+ CCLK_SRC_EMMC_SEL_SHIFT = 6,
+ CCLK_SRC_EMMC_SEL_MASK = 0x3 << CCLK_SRC_EMMC_SEL_SHIFT,
+ BCLK_EMMC_SEL_SHIFT = 8,
+ BCLK_EMMC_SEL_MASK = 0x3 << BCLK_EMMC_SEL_SHIFT,
+
+ /* CRU_CLKSEL_CON63 */
+ CLK_I2C3_SEL_SHIFT = 12,
+ CLK_I2C3_SEL_MASK = 0x3 << CLK_I2C3_SEL_SHIFT,
+ CLK_I2C5_SEL_SHIFT = 14,
+ CLK_I2C5_SEL_MASK = 0x3 << CLK_I2C5_SEL_SHIFT,
+ CLK_SPI1_SEL_SHIFT = 10,
+ CLK_SPI1_SEL_MASK = 0x3 << CLK_SPI1_SEL_SHIFT,
+
+ /* CRU_CLKSEL_CON64 */
+ CLK_I2C6_SEL_SHIFT = 0,
+ CLK_I2C6_SEL_MASK = 0x3 << CLK_I2C6_SEL_SHIFT,
+
+ /* CRU_CLKSEL_CON74 */
+ CLK_SARADC_DIV_SHIFT = 0,
+ CLK_SARADC_DIV_MASK = 0x7 << CLK_SARADC_DIV_SHIFT,
+ CLK_TSADC_DIV_SHIFT = 3,
+ CLK_TSADC_DIV_MASK = 0x1F << CLK_TSADC_DIV_SHIFT,
+ CLK_TSADC_TSEN_DIV_SHIFT = 8,
+ CLK_TSADC_TSEN_DIV_MASK = 0x1F << CLK_TSADC_TSEN_DIV_SHIFT,
+
+ /* CRU_CLKSEL_CON79 */
+ CLK_I2C1_SEL_SHIFT = 9,
+ CLK_I2C1_SEL_MASK = 0x3 << CLK_I2C1_SEL_SHIFT,
+ CLK_I2C0_SEL_SHIFT = 11,
+ CLK_I2C0_SEL_MASK = 0x3 << CLK_I2C0_SEL_SHIFT,
+ CLK_SPI0_SEL_SHIFT = 13,
+ CLK_SPI0_SEL_MASK = 0x3 << CLK_SPI0_SEL_SHIFT,
+
+ /* CRU_CLKSEL_CON83 */
+ ACLK_VOP_ROOT_DIV_SHIFT = 12,
+ ACLK_VOP_ROOT_DIV_MASK = 0x7 << ACLK_VOP_ROOT_DIV_SHIFT,
+ ACLK_VOP_ROOT_SEL_SHIFT = 15,
+ ACLK_VOP_ROOT_SEL_MASK = 0x1 << ACLK_VOP_ROOT_SEL_SHIFT,
+
+ /* CRU_CLKSEL_CON84 */
+ DCLK_VOP0_SEL_SHIFT = 0,
+ DCLK_VOP0_SEL_MASK = 0x1 << DCLK_VOP0_SEL_SHIFT,
+ DCLK_VOP_SRC_SEL_CLK_GPLL_MUX = 0U,
+ DCLK_VOP_SRC_SEL_CLK_CPLL_MUX = 1U,
+ ACLK_VOP_ROOT_SEL_CLK_GPLL_MUX = 0U,
+ ACLK_VOP_ROOT_SEL_CLK_CPLL_MUX = 1U,
+ DCLK_VOP0_SEL_DCLK_VOP_SRC0 = 0U,
+ DCLK_VOP0_SEL_CLK_HDMIPHY_PIXEL_IO = 1U,
+
+ /* CRU_CLKSEL_CON85 */
+ CLK_I2C4_SEL_SHIFT = 13,
+ CLK_I2C4_SEL_MASK = 0x3 << CLK_I2C4_SEL_SHIFT,
+ CLK_I2C7_SEL_SHIFT = 0,
+ CLK_I2C7_SEL_MASK = 0x3 << CLK_I2C7_SEL_SHIFT,
+ CLK_I2C3_SEL_CLK_MATRIX_200M_SRC = 0U,
+ CLK_I2C3_SEL_CLK_MATRIX_100M_SRC = 1U,
+ CLK_I2C3_SEL_CLK_MATRIX_50M_SRC = 2U,
+ CLK_I2C3_SEL_XIN_OSC0_FUNC = 3U,
+ CLK_SPI1_SEL_CLK_MATRIX_200M_SRC = 0U,
+ CLK_SPI1_SEL_CLK_MATRIX_100M_SRC = 1U,
+ CLK_SPI1_SEL_CLK_MATRIX_50M_SRC = 2U,
+ CLK_SPI1_SEL_XIN_OSC0_FUNC = 3U,
+ CCLK_SRC_SDMMC0_DIV_SHIFT = 0,
+ CCLK_SRC_SDMMC0_DIV_MASK = 0x3F << CCLK_SRC_SDMMC0_DIV_SHIFT,
+ CCLK_SRC_SDMMC0_SEL_SHIFT = 6,
+ CCLK_SRC_SDMMC0_SEL_MASK = 0x3 << CCLK_SRC_SDMMC0_SEL_SHIFT,
+ CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX = 0U,
+ CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX = 1U,
+ CCLK_SRC_EMMC_SEL_XIN_OSC0_FUNC = 2U,
+ BCLK_EMMC_SEL_CLK_MATRIX_200M_SRC = 0U,
+ BCLK_EMMC_SEL_CLK_MATRIX_100M_SRC = 1U,
+ BCLK_EMMC_SEL_CLK_MATRIX_50M_SRC = 2U,
+ BCLK_EMMC_SEL_XIN_OSC0_FUNC = 3U,
+ CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX = 0U,
+ CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX = 1U,
+ CCLK_SRC_SDMMC0_SEL_XIN_OSC0_FUNC = 2U,
+
+ /* CRU_CLKSEL_CON04 */
+ CLK_UART0_SRC_DIV_SHIFT = 5,
+ CLK_UART0_SRC_DIV_MASK = 0x1F << CLK_UART0_SRC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON05 */
+ CLK_UART0_FRAC_DIV_SHIFT = 0,
+ CLK_UART0_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART0_FRAC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON06 */
+ SCLK_UART0_SRC_SEL_SHIFT = 0,
+ SCLK_UART0_SRC_SEL_MASK = 0x3 << SCLK_UART0_SRC_SEL_SHIFT,
+ CLK_UART1_SRC_DIV_SHIFT = 2,
+ CLK_UART1_SRC_DIV_MASK = 0x1F << CLK_UART1_SRC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON07 */
+ CLK_UART1_FRAC_DIV_SHIFT = 0,
+ CLK_UART1_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART1_FRAC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON08 */
+ SCLK_UART1_SRC_SEL_SHIFT = 0,
+ SCLK_UART1_SRC_SEL_MASK = 0x3 << SCLK_UART1_SRC_SEL_SHIFT,
+ CLK_UART2_SRC_DIV_SHIFT = 2,
+ CLK_UART2_SRC_DIV_MASK = 0x1F << CLK_UART2_SRC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON09 */
+ CLK_UART2_FRAC_DIV_SHIFT = 0,
+ CLK_UART2_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART2_FRAC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON10 */
+ SCLK_UART2_SRC_SEL_SHIFT = 0,
+ SCLK_UART2_SRC_SEL_MASK = 0x3 << SCLK_UART2_SRC_SEL_SHIFT,
+ CLK_UART3_SRC_DIV_SHIFT = 2,
+ CLK_UART3_SRC_DIV_MASK = 0x1F << CLK_UART3_SRC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON11 */
+ CLK_UART3_FRAC_DIV_SHIFT = 0,
+ CLK_UART3_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART3_FRAC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON12 */
+ SCLK_UART3_SRC_SEL_SHIFT = 0,
+ SCLK_UART3_SRC_SEL_MASK = 0x3 << SCLK_UART3_SRC_SEL_SHIFT,
+ CLK_UART4_SRC_DIV_SHIFT = 2,
+ CLK_UART4_SRC_DIV_MASK = 0x1F << CLK_UART4_SRC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON13 */
+ CLK_UART4_FRAC_DIV_SHIFT = 0,
+ CLK_UART4_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART4_FRAC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON14 */
+ SCLK_UART4_SRC_SEL_SHIFT = 0,
+ SCLK_UART4_SRC_SEL_MASK = 0x3 << SCLK_UART4_SRC_SEL_SHIFT,
+ CLK_UART5_SRC_DIV_SHIFT = 2,
+ CLK_UART5_SRC_DIV_MASK = 0x1F << CLK_UART5_SRC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON15 */
+ CLK_UART5_FRAC_DIV_SHIFT = 0,
+ CLK_UART5_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART5_FRAC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON16 */
+ SCLK_UART5_SRC_SEL_SHIFT = 0,
+ SCLK_UART5_SRC_SEL_MASK = 0x3 << SCLK_UART5_SRC_SEL_SHIFT,
+ CLK_UART6_SRC_DIV_SHIFT = 2,
+ CLK_UART6_SRC_DIV_MASK = 0x1F << CLK_UART6_SRC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON17 */
+ CLK_UART6_FRAC_DIV_SHIFT = 0,
+ CLK_UART6_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART6_FRAC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON18 */
+ SCLK_UART6_SRC_SEL_SHIFT = 0,
+ SCLK_UART6_SRC_SEL_MASK = 0x3 << SCLK_UART6_SRC_SEL_SHIFT,
+ CLK_UART7_SRC_DIV_SHIFT = 2,
+ CLK_UART7_SRC_DIV_MASK = 0x1F << CLK_UART7_SRC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON19 */
+ CLK_UART7_FRAC_DIV_SHIFT = 0,
+ CLK_UART7_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART7_FRAC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON20 */
+ SCLK_UART7_SRC_SEL_SHIFT = 0,
+ SCLK_UART7_SRC_SEL_MASK = 0x3 << SCLK_UART7_SRC_SEL_SHIFT,
+ SCLK_UART0_SRC_SEL_CLK_UART0_SRC = 0U,
+ SCLK_UART0_SRC_SEL_CLK_UART0_FRAC = 1U,
+ SCLK_UART0_SRC_SEL_XIN_OSC0_FUNC = 2U,
+
+ /* CRU_CLKSEL_CON60 */
+ CLK_GMAC1_VPU_25M_DIV_SHIFT = 2,
+ CLK_GMAC1_VPU_25M_DIV_MASK = 0xFF << CLK_GMAC1_VPU_25M_DIV_SHIFT,
+ /* CRU_CLKSEL_CON66 */
+ CLK_GMAC1_SRC_VPU_DIV_SHIFT = 0,
+ CLK_GMAC1_SRC_VPU_DIV_MASK = 0x3F << CLK_GMAC1_SRC_VPU_DIV_SHIFT,
+ /* CRU_CLKSEL_CON84 */
+ CLK_GMAC0_SRC_DIV_SHIFT = 3,
+ CLK_GMAC0_SRC_DIV_MASK = 0x3F << CLK_GMAC0_SRC_DIV_SHIFT,
+};
+
+#endif /* _ASM_ARCH_CRU_RK3528_H */
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3576.h b/arch/arm/include/asm/arch-rockchip/cru_rk3576.h
new file mode 100644
index 0000000..c51750b
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3576.h
@@ -0,0 +1,491 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#ifndef _ASM_ARCH_CRU_RK3576_H
+#define _ASM_ARCH_CRU_RK3576_H
+
+#define MHz 1000000
+#define KHz 1000
+#define OSC_HZ (24 * MHz)
+
+#define CPU_PVTPLL_HZ (1008 * MHz)
+#define LPLL_HZ (816 * MHz)
+#define GPLL_HZ (1188 * MHz)
+#define CPLL_HZ (1000 * MHz)
+#define PPLL_HZ (1100 * MHz)
+#define GMAC0_PTP_REFCLK_IN (24 * MHz)
+#define GMAC1_PTP_REFCLK_IN (24 * MHz)
+
+/* RK3576 pll id */
+enum rk3576_pll_id {
+ BPLL,
+ LPLL,
+ DPLL,
+ CPLL,
+ GPLL,
+ VPLL,
+ AUPLL,
+ SPLL,
+ PPLL,
+ PLL_COUNT,
+};
+
+struct rk3576_clk_priv {
+ struct rk3576_cru *cru;
+ ulong ppll_hz;
+ ulong gpll_hz;
+ ulong cpll_hz;
+ ulong vpll_hz;
+ ulong aupll_hz;
+ ulong spll_hz;
+ ulong lpll_hz;
+ ulong bpll_hz;
+ ulong armclk_hz;
+ ulong armclk_enter_hz;
+ ulong armclk_init_hz;
+ bool sync_kernel;
+ bool set_armclk_rate;
+};
+
+struct rk3576_pll {
+ unsigned int con0;
+ unsigned int con1;
+ unsigned int con2;
+ unsigned int con3;
+ unsigned int con4;
+ unsigned int reserved0[3];
+};
+
+struct rk3576_cru {
+ struct rk3576_pll pll[18];
+ unsigned int reserved0[16];/* Address Offset: 0x0240 */
+ unsigned int mode_con00;/* Address Offset: 0x0280 */
+ unsigned int reserved1[31];/* Address Offset: 0x0284 */
+ unsigned int clksel_con[181]; /* Address Offset: 0x0300 */
+ unsigned int reserved2[139];/* Address Offset: 0x05d4 */
+ unsigned int clkgate_con[80];/* Address Offset: 0x0800 */
+ unsigned int reserved3[48];/* Address Offset: 0x0938 */
+ unsigned int softrst_con[80];/* Address Offset: 0x0400 */
+ unsigned int reserved4[48];/* Address Offset: 0x0b38 */
+ unsigned int glb_cnt_th;/* Address Offset: 0x0c00 */
+ unsigned int glb_rst_st;/* Address Offset: 0x0c04 */
+ unsigned int glb_srst_fst;/* Address Offset: 0x0c08 */
+ unsigned int glb_srsr_snd; /* Address Offset: 0x0c0c */
+ unsigned int glb_rst_con;/* Address Offset: 0x0c10 */
+ unsigned int reserved5[43];/* Address Offset: 0x0c14 */
+ unsigned int smoth_divfree_con[3];/* Address Offset: 0x0cc0 */
+ unsigned int fracdiv_high_con[4];/* Address Offset: 0x0ccc */
+ unsigned int reserved8[32137];/* Address Offset: 0x0c38 */
+ unsigned int pmuclksel_con[22]; /* Address Offset: 0x20300 */
+ unsigned int reserved9[298];/* Address Offset: 0x20358 */
+ unsigned int pmuclkgate_con[8]; /* Address Offset: 0x20800 */
+ unsigned int reserved10[32440];/* Address Offset: 0x20820 */
+ unsigned int litclksel_con[4]; /* Address Offset: 0x40300 */
+};
+
+check_member(rk3576_cru, mode_con00, 0x280);
+check_member(rk3576_cru, pmuclksel_con[1], 0x20304);
+
+struct pll_rate_table {
+ unsigned long rate;
+ unsigned int m;
+ unsigned int p;
+ unsigned int s;
+ unsigned int k;
+};
+
+#define RK3576_PHP_CRU_BASE 0x8000
+#define RK3576_PMU_CRU_BASE 0x20000
+#define RK3576_BIGCORE_CRU_BASE 0x38000
+#define RK3576_LITCORE_CRU_BASE 0x40000
+#define RK3576_CCI_CRU_BASE 0x48000
+#define RK3576_CRU_BASE 0x27200000
+#define RK3576_SCRU_BASE 0x27214000
+
+#define RK3576_BIGCORE_GRF_BASE 0x2600C000
+#define RK3576_LITCORE_GRF_BASE 0x2600E000
+#define RK3576_CCI_GRF_BASE 0x26010000
+
+#define RK3576_PLL_CON(x) ((x) * 0x4)
+#define RK3576_MODE_CON0 0x280
+#define RK3576_BPLL_MODE_CON0 (RK3576_BIGCORE_CRU_BASE + 0x280)
+#define RK3576_LPLL_MODE_CON0 (RK3576_LITCORE_CRU_BASE + 0x280)
+#define RK3576_PPLL_MODE_CON0 (RK3576_PHP_CRU_BASE + 0x280)
+#define RK3576_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
+#define RK3576_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
+#define RK3576_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
+#define RK3576_GLB_CNT_TH 0xc00
+#define RK3576_GLB_SRST_FST 0xc08
+#define RK3576_GLB_SRST_SND 0xc0c
+#define RK3576_GLB_RST_CON 0xc10
+#define RK3576_GLB_RST_ST 0xc04
+#define RK3576_SDIO_CON0 0xC24
+#define RK3576_SDIO_CON1 0xC28
+#define RK3576_SDMMC_CON0 0xC30
+#define RK3576_SDMMC_CON1 0xC34
+
+#define RK3576_PHP_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x300)
+#define RK3576_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x800)
+#define RK3576_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0xa00)
+
+#define RK3576_PMU_PLL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE)
+#define RK3576_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x300)
+#define RK3576_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x800)
+#define RK3576_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0xa00)
+
+#define RK3576_CCI_CLKSEL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x300)
+#define RK3576_CCI_CLKGATE_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x800)
+#define RK3576_CCI_SOFTRST_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0xa00)
+
+#define RK3576_BPLL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE)
+#define RK3576_BIGCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x300)
+#define RK3576_BIGCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x800)
+#define RK3576_BIGCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0xa00)
+#define RK3576_LPLL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE)
+#define RK3576_LITCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x300)
+#define RK3576_LITCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x800)
+#define RK3576_LITCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0xa00)
+
+enum {
+ /* CRU_CLK_SEL8_CON */
+ PCLK_TOP_SEL_SHIFT = 7,
+ PCLK_TOP_SEL_MASK = 3 << PCLK_TOP_SEL_SHIFT,
+ PCLK_TOP_SEL_100M = 0,
+ PCLK_TOP_SEL_50M,
+ PCLK_TOP_SEL_OSC,
+
+ /* CRU_CLK_SEL9_CON */
+ ACLK_TOP_SEL_SHIFT = 5,
+ ACLK_TOP_SEL_MASK = 3 << ACLK_TOP_SEL_SHIFT,
+ ACLK_TOP_SEL_GPLL = 0,
+ ACLK_TOP_SEL_CPLL,
+ ACLK_TOP_SEL_AUPLL,
+ ACLK_TOP_DIV_SHIFT = 0,
+ ACLK_TOP_DIV_MASK = 0x1f << ACLK_TOP_DIV_SHIFT,
+
+ /* CRU_CLK_SEL10_CON */
+ ACLK_TOP_MID_SEL_SHIFT = 5,
+ ACLK_TOP_MID_SEL_MASK = 1 << ACLK_TOP_MID_SEL_SHIFT,
+ ACLK_TOP_MID_SEL_GPLL = 0,
+ ACLK_TOP_MID_SEL_CPLL,
+ ACLK_TOP_MID_DIV_SHIFT = 0,
+ ACLK_TOP_MID_DIV_MASK = 0x1f << ACLK_TOP_MID_DIV_SHIFT,
+
+ /* CRU_CLK_SEL19_CON */
+ HCLK_TOP_SEL_SHIFT = 2,
+ HCLK_TOP_SEL_MASK = 3 << HCLK_TOP_SEL_SHIFT,
+ HCLK_TOP_SEL_200M = 0,
+ HCLK_TOP_SEL_100M,
+ HCLK_TOP_SEL_50M,
+ HCLK_TOP_SEL_OSC,
+
+ /* CRU_CLK_SEL25_CON */
+ CLK_UART_FRAC_NUMERATOR_SHIFT = 16,
+ CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16,
+ CLK_UART_FRAC_DENOMINATOR_SHIFT = 0,
+ CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff,
+
+ /* CRU_CLK_SEL26_CON */
+ CLK_UART_SRC_SEL_SHIFT = 0,
+ CLK_UART_SRC_SEL_MASK = 0x3 << CLK_UART_SRC_SEL_SHIFT,
+ CLK_UART_SRC_SEL_GPLL = 0,
+ CLK_UART_SRC_SEL_CPLL,
+ CLK_UART_SRC_SEL_AUPLL,
+ CLK_UART_SRC_SEL_OSC,
+
+ /* CRU_CLK_SEL27_CON */
+ CLK_UART1_SRC_SEL_SHIFT = 13,
+ CLK_UART1_SRC_SEL_MASK = 0x7 << CLK_UART1_SRC_SEL_SHIFT,
+ CLK_UART1_SRC_DIV_SHIFT = 5,
+ CLK_UART1_SRC_DIV_MASK = 0xff << CLK_UART1_SRC_DIV_SHIFT,
+
+ /* CRU_CLK_SEL30_CON */
+ CLK_GMAC0_125M_DIV_SHIFT = 10,
+ CLK_GMAC0_125M_DIV_MASK = 0x1f << CLK_GMAC0_125M_DIV_SHIFT,
+
+ /* CRU_CLK_SEL31_CON */
+ CLK_GMAC1_125M_DIV_SHIFT = 0,
+ CLK_GMAC1_125M_DIV_MASK = 0x1f << CLK_GMAC1_125M_DIV_SHIFT,
+
+ /* CRU_CLK_SEL33_CON */
+ REF_CLK0_OUT_PLL_SEL_SHIFT = 8,
+ REF_CLK0_OUT_PLL_SEL_MASK = 7 << REF_CLK0_OUT_PLL_SEL_SHIFT,
+ REF_CLK0_OUT_PLL_SEL_GPLL = 0,
+ REF_CLK0_OUT_PLL_SEL_CPLL,
+ REF_CLK0_OUT_PLL_SEL_SPLL,
+ REF_CLK0_OUT_PLL_SEL_AUPLL,
+ REF_CLK0_OUT_PLL_SEL_LPLL,
+ REF_CLK0_OUT_PLL_SEL_OSC,
+ REF_CLK0_OUT_PLL_DIV_SHIFT = 0,
+ REF_CLK0_OUT_PLL_DIV_MASK = 0xff << REF_CLK0_OUT_PLL_DIV_SHIFT,
+
+ /* CRU_CLK_SEL55_CON */
+ ACLK_BUS_ROOT_SEL_SHIFT = 9,
+ ACLK_BUS_ROOT_SEL_MASK = 1 << ACLK_BUS_ROOT_SEL_SHIFT,
+ ACLK_BUS_ROOT_SEL_GPLL = 0,
+ ACLK_BUS_ROOT_SEL_CPLL,
+ ACLK_BUS_ROOT_DIV_SHIFT = 4,
+ ACLK_BUS_ROOT_DIV_MASK = 0x1f << ACLK_BUS_ROOT_DIV_SHIFT,
+ PCLK_BUS_ROOT_SEL_SHIFT = 2,
+ PCLK_BUS_ROOT_SEL_MASK = 3 << PCLK_BUS_ROOT_SEL_SHIFT,
+ PCLK_BUS_ROOT_SEL_100M = 0,
+ PCLK_BUS_ROOT_SEL_50M,
+ PCLK_BUS_ROOT_SEL_OSC,
+ HCLK_BUS_ROOT_SEL_SHIFT = 0,
+ HCLK_BUS_ROOT_SEL_MASK = 3 << HCLK_BUS_ROOT_SEL_SHIFT,
+ HCLK_BUS_ROOT_SEL_200M = 0,
+ HCLK_BUS_ROOT_SEL_100M,
+ HCLK_BUS_ROOT_SEL_50M,
+ HCLK_BUS_ROOT_SEL_OSC,
+
+ /* CRU_CLK_SEL57_CON */
+ CLK_I2C8_SEL_SHIFT = 14,
+ CLK_I2C8_SEL_MASK = 3 << CLK_I2C8_SEL_SHIFT,
+ CLK_I2C7_SEL_SHIFT = 12,
+ CLK_I2C7_SEL_MASK = 3 << CLK_I2C7_SEL_SHIFT,
+ CLK_I2C6_SEL_SHIFT = 10,
+ CLK_I2C6_SEL_MASK = 3 << CLK_I2C6_SEL_SHIFT,
+ CLK_I2C5_SEL_SHIFT = 8,
+ CLK_I2C5_SEL_MASK = 3 << CLK_I2C5_SEL_SHIFT,
+ CLK_I2C4_SEL_SHIFT = 6,
+ CLK_I2C4_SEL_MASK = 3 << CLK_I2C4_SEL_SHIFT,
+ CLK_I2C3_SEL_SHIFT = 4,
+ CLK_I2C3_SEL_MASK = 3 << CLK_I2C3_SEL_SHIFT,
+ CLK_I2C2_SEL_SHIFT = 2,
+ CLK_I2C2_SEL_MASK = 3 << CLK_I2C2_SEL_SHIFT,
+ CLK_I2C1_SEL_SHIFT = 0,
+ CLK_I2C1_SEL_MASK = 3 << CLK_I2C1_SEL_SHIFT,
+ CLK_I2C_SEL_200M = 0,
+ CLK_I2C_SEL_100M,
+ CLK_I2C_SEL_50M,
+ CLK_I2C_SEL_OSC,
+
+ /* CRU_CLK_SEL58_CON */
+ CLK_SARADC_SEL_SHIFT = 12,
+ CLK_SARADC_SEL_MASK = 0x1 << CLK_SARADC_SEL_SHIFT,
+ CLK_SARADC_SEL_GPLL = 0,
+ CLK_SARADC_SEL_OSC,
+ CLK_SARADC_DIV_SHIFT = 4,
+ CLK_SARADC_DIV_MASK = 0xff << CLK_SARADC_DIV_SHIFT,
+ CLK_I2C9_SEL_SHIFT = 0,
+ CLK_I2C9_SEL_MASK = 3 << CLK_I2C9_SEL_SHIFT,
+
+ /* CRU_CLK_SEL59_CON */
+ CLK_TSADC_DIV_SHIFT = 0,
+ CLK_TSADC_DIV_MASK = 0xff << CLK_TSADC_DIV_SHIFT,
+
+ /* CRU_CLK_SEL60_CON */
+ CLK_UART_SEL_SHIFT = 8,
+ CLK_UART_SEL_MASK = 7 << CLK_UART_SEL_SHIFT,
+ CLK_UART_SEL_GPLL = 0,
+ CLK_UART_SEL_CPLL,
+ CLK_UART_SEL_AUPLL,
+ CLK_UART_SEL_OSC,
+ CLK_UART_SEL_FRAC0,
+ CLK_UART_SEL_FRAC1,
+ CLK_UART_SEL_FRAC2,
+ CLK_UART_DIV_SHIFT = 0,
+ CLK_UART_DIV_MASK = 0xff << CLK_UART_DIV_SHIFT,
+
+ /* CRU_CLK_SEL70_CON */
+ CLK_SPI0_SEL_SHIFT = 13,
+ CLK_SPI0_SEL_MASK = 3 << CLK_SPI0_SEL_SHIFT,
+ CLK_SPI_SEL_200M = 0,
+ CLK_SPI_SEL_100M,
+ CLK_SPI_SEL_50M,
+ CLK_SPI_SEL_OSC,
+
+ /* CRU_CLK_SEL71_CON */
+ CLK_PWM1_SEL_SHIFT = 8,
+ CLK_PWM1_SEL_MASK = 3 << CLK_PWM1_SEL_SHIFT,
+ CLK_SPI4_SEL_SHIFT = 6,
+ CLK_SPI4_SEL_MASK = 3 << CLK_SPI4_SEL_SHIFT,
+ CLK_SPI3_SEL_SHIFT = 4,
+ CLK_SPI3_SEL_MASK = 3 << CLK_SPI3_SEL_SHIFT,
+ CLK_SPI2_SEL_SHIFT = 2,
+ CLK_SPI2_SEL_MASK = 3 << CLK_SPI2_SEL_SHIFT,
+ CLK_SPI1_SEL_SHIFT = 0,
+ CLK_SPI1_SEL_MASK = 3 << CLK_SPI1_SEL_SHIFT,
+ CLK_PWM_SEL_100M = 0,
+ CLK_PWM_SEL_50M,
+ CLK_PWM_SEL_OSC,
+
+ /* CRU_CLK_SEL72_CON */
+ DCLK_DECOM_SEL_SHIFT = 5,
+ DCLK_DECOM_SEL_MASK = 1 << DCLK_DECOM_SEL_SHIFT,
+ DCLK_DECOM_SEL_GPLL = 0,
+ DCLK_DECOM_SEL_SPLL,
+ DCLK_DECOM_DIV_SHIFT = 0,
+ DCLK_DECOM_DIV_MASK = 0x1f << DCLK_DECOM_DIV_SHIFT,
+
+ /* CRU_CLK_SEL74_CON */
+ CLK_PWM2_SEL_SHIFT = 6,
+ CLK_PWM2_SEL_MASK = 3 << CLK_PWM2_SEL_SHIFT,
+
+ /* CRU_CLK_SEL89_CON */
+ CCLK_EMMC_SEL_SHIFT = 14,
+ CCLK_EMMC_SEL_MASK = 3 << CCLK_EMMC_SEL_SHIFT,
+ CCLK_EMMC_SEL_GPLL = 0,
+ CCLK_EMMC_SEL_CPLL,
+ CCLK_EMMC_SEL_OSC,
+ CCLK_EMMC_DIV_SHIFT = 8,
+ CCLK_EMMC_DIV_MASK = 0x3f << CCLK_EMMC_DIV_SHIFT,
+ SCLK_FSPI_SEL_SHIFT = 6,
+ SCLK_FSPI_SEL_MASK = 3 << SCLK_FSPI_SEL_SHIFT,
+ SCLK_FSPI_SEL_GPLL = 0,
+ SCLK_FSPI_SEL_CPLL,
+ SCLK_FSPI_SEL_OSC,
+ SCLK_FSPI_DIV_SHIFT = 0,
+ SCLK_FSPI_DIV_MASK = 0x3f << SCLK_FSPI_DIV_SHIFT,
+
+ /* CRU_CLK_SEL90_CON */
+ BCLK_EMMC_SEL_SHIFT = 0,
+ BCLK_EMMC_SEL_MASK = 3 << BCLK_EMMC_SEL_SHIFT,
+ BCLK_EMMC_SEL_200M = 0,
+ BCLK_EMMC_SEL_100M,
+ BCLK_EMMC_SEL_50M,
+ BCLK_EMMC_SEL_OSC,
+
+ /* CRU_CLK_SEL104_CON */
+ CLK_GMAC1_PTP_SEL_SHIFT = 13,
+ CLK_GMAC1_PTP_SEL_MASK = 3 << CLK_GMAC1_PTP_SEL_SHIFT,
+ CLK_GMAC1_PTP_SEL_GPLL = 0,
+ CLK_GMAC1_PTP_SEL_CPLL,
+ CLK_GMAC1_PTP_SEL_REFIN,
+ CLK_GMAC1_PTP_DIV_SHIFT = 8,
+ CLK_GMAC1_PTP_DIV_MASK = 0x1f << CLK_GMAC1_PTP_DIV_SHIFT,
+ CCLK_SDIO_SRC_SEL_SHIFT = 6,
+ CCLK_SDIO_SRC_SEL_MASK = 3 << CCLK_SDIO_SRC_SEL_SHIFT,
+ CCLK_SDIO_SRC_SEL_GPLL = 0,
+ CCLK_SDIO_SRC_SEL_CPLL,
+ CCLK_SDIO_SRC_SEL_OSC,
+ CCLK_SDIO_SRC_DIV_SHIFT = 0,
+ CCLK_SDIO_SRC_DIV_MASK = 0x3f << CCLK_SDIO_SRC_DIV_SHIFT,
+
+ /* CRU_CLK_SEL105_CON */
+ CCLK_SDMMC0_SRC_SEL_SHIFT = 13,
+ CCLK_SDMMC0_SRC_SEL_MASK = 3 << CCLK_SDMMC0_SRC_SEL_SHIFT,
+ CCLK_SDMMC0_SRC_SEL_GPLL = 0,
+ CCLK_SDMMC0_SRC_SEL_CPLL,
+ CCLK_SDMMC0_SRC_SEL_OSC,
+ CCLK_SDMMC0_SRC_DIV_SHIFT = 7,
+ CCLK_SDMMC0_SRC_DIV_MASK = 0x3f << CCLK_SDMMC0_SRC_DIV_SHIFT,
+ CLK_GMAC0_PTP_SEL_SHIFT = 5,
+ CLK_GMAC0_PTP_SEL_MASK = 3 << CLK_GMAC0_PTP_SEL_SHIFT,
+ CLK_GMAC0_PTP_SEL_GPLL = 0,
+ CLK_GMAC0_PTP_SEL_CPLL,
+ CLK_GMAC0_PTP_SEL_REFIN,
+ CLK_GMAC0_PTP_DIV_SHIFT = 0,
+ CLK_GMAC0_PTP_DIV_MASK = 0x1f << CLK_GMAC0_PTP_DIV_SHIFT,
+
+ /* CRU_CLK_SEL123_CON */
+ DCLK_EBC_SEL_SHIFT = 12,
+ DCLK_EBC_SEL_MASK = 7 << DCLK_EBC_SEL_SHIFT,
+ DCLK_EBC_SEL_GPLL = 0,
+ DCLK_EBC_SEL_CPLL,
+ DCLK_EBC_SEL_VPLL,
+ DCLK_EBC_SEL_AUPLL,
+ DCLK_EBC_SEL_LPLL,
+ DCLK_EBC_SEL_FRAC_SRC,
+ DCLK_EBC_SEL_OSC,
+ DCLK_EBC_DIV_SHIFT = 3,
+ DCLK_EBC_DIV_MASK = 0x1ff << DCLK_EBC_DIV_SHIFT,
+ DCLK_EBC_FRAC_SRC_SEL_SHIFT = 0,
+ DCLK_EBC_FRAC_SRC_SEL_MASK = 7 << DCLK_EBC_FRAC_SRC_SEL_SHIFT,
+ DCLK_EBC_FRAC_SRC_SEL_GPLL = 0,
+ DCLK_EBC_FRAC_SRC_SEL_CPLL,
+ DCLK_EBC_FRAC_SRC_SEL_VPLL,
+ DCLK_EBC_FRAC_SRC_SEL_AUPLL,
+ DCLK_EBC_FRAC_SRC_SEL_OSC,
+
+ /* CRU_CLK_SEL144_CON */
+ PCLK_VOP_ROOT_SEL_SHIFT = 12,
+ PCLK_VOP_ROOT_SEL_MASK = 3 << PCLK_VOP_ROOT_SEL_SHIFT,
+ PCLK_VOP_ROOT_SEL_100M = 0,
+ PCLK_VOP_ROOT_SEL_50M,
+ PCLK_VOP_ROOT_SEL_OSC,
+ HCLK_VOP_ROOT_SEL_SHIFT = 10,
+ HCLK_VOP_ROOT_SEL_MASK = 3 << HCLK_VOP_ROOT_SEL_SHIFT,
+ HCLK_VOP_ROOT_SEL_200M = 0,
+ HCLK_VOP_ROOT_SEL_100M,
+ HCLK_VOP_ROOT_SEL_50M,
+ HCLK_VOP_ROOT_SEL_OSC,
+ ACLK_VOP_ROOT_SEL_SHIFT = 5,
+ ACLK_VOP_ROOT_SEL_MASK = 7 << ACLK_VOP_ROOT_SEL_SHIFT,
+ ACLK_VOP_ROOT_SEL_GPLL = 0,
+ ACLK_VOP_ROOT_SEL_CPLL,
+ ACLK_VOP_ROOT_SEL_AUPLL,
+ ACLK_VOP_ROOT_SEL_SPLL,
+ ACLK_VOP_ROOT_SEL_LPLL,
+ ACLK_VOP_ROOT_DIV_SHIFT = 0,
+ ACLK_VOP_ROOT_DIV_MASK = 0x1f << ACLK_VOP_ROOT_DIV_SHIFT,
+
+ /* CRU_CLK_SEL145_CON */
+ DCLK0_VOP_SRC_SEL_SHIFT = 8,
+ DCLK0_VOP_SRC_SEL_MASK = 7 << DCLK0_VOP_SRC_SEL_SHIFT,
+ DCLK_VOP_SRC_SEL_GPLL = 0,
+ DCLK_VOP_SRC_SEL_CPLL,
+ DCLK_VOP_SRC_SEL_VPLL,
+ DCLK_VOP_SRC_SEL_BPLL,
+ DCLK_VOP_SRC_SEL_LPLL,
+ DCLK0_VOP_SRC_DIV_SHIFT = 0,
+ DCLK0_VOP_SRC_DIV_MASK = 0xff << DCLK0_VOP_SRC_DIV_SHIFT,
+
+ /* CRU_CLK_SEL147_CON */
+ DCLK2_VOP_SEL_SHIFT = 13,
+ DCLK2_VOP_SEL_MASK = 1 << DCLK2_VOP_SEL_SHIFT,
+ DCLK1_VOP_SEL_SHIFT = 12,
+ DCLK1_VOP_SEL_MASK = 1 << DCLK1_VOP_SEL_SHIFT,
+ DCLK0_VOP_SEL_SHIFT = 11,
+ DCLK0_VOP_SEL_MASK = 1 << DCLK0_VOP_SEL_SHIFT,
+
+ /* CRU_CLK_SEL149_CON */
+ ACLK_VO0_ROOT_SEL_SHIFT = 5,
+ ACLK_VO0_ROOT_SEL_MASK = 3 << ACLK_VO0_ROOT_SEL_SHIFT,
+ ACLK_VO0_ROOT_SEL_GPLL = 0,
+ ACLK_VO0_ROOT_SEL_CPLL,
+ ACLK_VO0_ROOT_SEL_LPLL,
+ ACLK_VO0_ROOT_SEL_BPLL,
+ ACLK_VO0_ROOT_DIV_SHIFT = 0,
+ ACLK_VO0_ROOT_DIV_MASK = 0x1f << ACLK_VO0_ROOT_DIV_SHIFT,
+
+ /* CRU_CLK_SEL151_CON */
+ CLK_DSIHOST0_SEL_SHIFT = 7,
+ CLK_DSIHOST0_SEL_MASK = 7 << CLK_DSIHOST0_SEL_SHIFT,
+ CLK_DSIHOST0_SEL_GPLL = 0,
+ CLK_DSIHOST0_SEL_CPLL,
+ CLK_DSIHOST0_SEL_SPLL,
+ CLK_DSIHOST0_SEL_VPLL,
+ CLK_DSIHOST0_SEL_BPLL,
+ CLK_DSIHOST0_SEL_LPLL,
+ CLK_DSIHOST0_DIV_SHIFT = 0,
+ CLK_DSIHOST0_DIV_MASK = 0x7f << CLK_DSIHOST0_DIV_SHIFT,
+
+ /* PMUCRU_CLK_SEL5_CON */
+ CLK_PMU1PWM_SEL_SHIFT = 2,
+ CLK_PMU1PWM_SEL_MASK = 3 << CLK_PMU1PWM_SEL_SHIFT,
+
+ /* PMUCRU_CLK_SEL6_CON */
+ CLK_I2C0_SEL_SHIFT = 7,
+ CLK_I2C0_SEL_MASK = 3 << CLK_I2C0_SEL_SHIFT,
+
+ /* PMUCRU_CLK_SEL8_CON */
+ CLK_UART1_SEL_SHIFT = 0,
+ CLK_UART1_SEL_MASK = 1 << CLK_UART1_SEL_SHIFT,
+ CLK_UART1_SEL_TOP = 0,
+ CLK_UART1_SEL_OSC,
+
+ /* LITCRU_CLK_SEL0_CON */
+ CLK_LITCORE_SEL_SHIFT = 12,
+ CLK_LITCORE_SEL_MASK = 3 << CLK_LITCORE_SEL_SHIFT,
+ CLK_LITCORE_SEL_LPLL = 0,
+ CLK_LITCORE_SEL_GPLL,
+ CLK_LITCORE_SEL_PVTPLL,
+ CLK_LITCORE_DIV_SHIFT = 7,
+ CLK_LITCORE_DIV_MASK = 0x1f << CLK_LITCORE_DIV_SHIFT,
+
+};
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h
index 24c8139..d79aea9 100644
--- a/arch/arm/include/asm/arch-sunxi/boot0.h
+++ b/arch/arm/include/asm/arch-sunxi/boot0.h
@@ -26,11 +26,21 @@
.word 0xe580e004 // str lr, [r0, #4]
.word 0xe10fe000 // mrs lr, CPSR
.word 0xe580e008 // str lr, [r0, #8]
+ .word 0xe101e300 // mrs lr, SP_irq
+ .word 0xe580e014 // str lr, [r0, #20]
.word 0xee11ef10 // mrc 15, 0, lr, cr1, cr0, {0}
.word 0xe580e00c // str lr, [r0, #12]
.word 0xee1cef10 // mrc 15, 0, lr, cr12, cr0, {0}
.word 0xe580e010 // str lr, [r0, #16]
-
+#ifdef CONFIG_MACH_SUN55I_A523
+ .word 0xee1cefbc // mrc 15, 0, lr, cr12, cr12, {5}
+ .word 0xe31e0001 // tst lr, #1
+ .word 0x0a000003 // beq cc <start32+0x48>
+ .word 0xee14ef16 // mrc 15, 0, lr, cr4, cr6, {0}
+ .word 0xe580e018 // str lr, [r0, #24]
+ .word 0xee1ceffc // mrc 15, 0, lr, cr12, cr12, {7}
+ .word 0xe580e01c // str lr, [r0, #28]
+#endif
.word 0xe59f1034 // ldr r1, [pc, #52] ; RVBAR_ADDRESS
.word 0xe59f0034 // ldr r0, [pc, #52] ; SUNXI_SRAMC_BASE
.word 0xe5900024 // ldr r0, [r0, #36] ; SRAM_VER_REG
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index 2cec91c..00bdd5f 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -10,6 +10,12 @@
#ifndef _SUNXI_CLOCK_SUN4I_H
#define _SUNXI_CLOCK_SUN4I_H
+#define CCU_AHB_GATE0 0x60
+#define CCU_MMC0_CLK_CFG 0x88
+#define CCU_MMC1_CLK_CFG 0x8c
+#define CCU_MMC2_CLK_CFG 0x90
+#define CCU_MMC3_CLK_CFG 0x94
+
struct sunxi_ccm_reg {
u32 pll1_cfg; /* 0x00 pll1 control */
u32 pll1_tun; /* 0x04 pll1 tuning */
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
index 76dd33c..ccacc99 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
@@ -13,218 +13,23 @@
#include <linux/bitops.h>
#endif
-struct sunxi_ccm_reg {
- u32 pll1_cfg; /* 0x000 pll1 (cpux) control */
- u8 reserved_0x004[12];
- u32 pll5_cfg; /* 0x010 pll5 (ddr) control */
- u8 reserved_0x014[12];
- u32 pll6_cfg; /* 0x020 pll6 (periph0) control */
- u8 reserved_0x020[4];
- u32 pll_periph1_cfg; /* 0x028 pll periph1 control */
- u8 reserved_0x028[4];
- u32 pll7_cfg; /* 0x030 pll7 (gpu) control */
- u8 reserved_0x034[12];
- u32 pll3_cfg; /* 0x040 pll3 (video0) control */
- u8 reserved_0x044[4];
- u32 pll_video1_cfg; /* 0x048 pll video1 control */
- u8 reserved_0x04c[12];
- u32 pll4_cfg; /* 0x058 pll4 (ve) control */
- u8 reserved_0x05c[4];
- u32 pll10_cfg; /* 0x060 pll10 (de) control */
- u8 reserved_0x064[12];
- u32 pll9_cfg; /* 0x070 pll9 (hsic) control */
- u8 reserved_0x074[4];
- u32 pll2_cfg; /* 0x078 pll2 (audio) control */
- u8 reserved_0x07c[148];
- u32 pll5_pat; /* 0x110 pll5 (ddr) pattern */
- u8 reserved_0x114[20];
- u32 pll_periph1_pat0; /* 0x128 pll periph1 pattern0 */
- u32 pll_periph1_pat1; /* 0x12c pll periph1 pattern1 */
- u32 pll7_pat0; /* 0x130 pll7 (gpu) pattern0 */
- u32 pll7_pat1; /* 0x134 pll7 (gpu) pattern1 */
- u8 reserved_0x138[8];
- u32 pll3_pat0; /* 0x140 pll3 (video0) pattern0 */
- u32 pll3_pat1; /* 0x144 pll3 (video0) pattern1 */
- u32 pll_video1_pat0; /* 0x148 pll video1 pattern0 */
- u32 pll_video1_pat1; /* 0x14c pll video1 pattern1 */
- u8 reserved_0x150[8];
- u32 pll4_pat0; /* 0x158 pll4 (ve) pattern0 */
- u32 pll4_pat1; /* 0x15c pll4 (ve) pattern1 */
- u32 pll10_pat0; /* 0x160 pll10 (de) pattern0 */
- u32 pll10_pat1; /* 0x164 pll10 (de) pattern1 */
- u8 reserved_0x168[8];
- u32 pll9_pat0; /* 0x170 pll9 (hsic) pattern0 */
- u32 pll9_pat1; /* 0x174 pll9 (hsic) pattern1 */
- u32 pll2_pat0; /* 0x178 pll2 (audio) pattern0 */
- u32 pll2_pat1; /* 0x17c pll2 (audio) pattern1 */
- u8 reserved_0x180[384];
- u32 pll1_bias; /* 0x300 pll1 (cpux) bias */
- u8 reserved_0x304[12];
- u32 pll5_bias; /* 0x310 pll5 (ddr) bias */
- u8 reserved_0x314[12];
- u32 pll6_bias; /* 0x320 pll6 (periph0) bias */
- u8 reserved_0x324[4];
- u32 pll_periph1_bias; /* 0x328 pll periph1 bias */
- u8 reserved_0x32c[4];
- u32 pll7_bias; /* 0x330 pll7 (gpu) bias */
- u8 reserved_0x334[12];
- u32 pll3_bias; /* 0x340 pll3 (video0) bias */
- u8 reserved_0x344[4];
- u32 pll_video1_bias; /* 0x348 pll video1 bias */
- u8 reserved_0x34c[12];
- u32 pll4_bias; /* 0x358 pll4 (ve) bias */
- u8 reserved_0x35c[4];
- u32 pll10_bias; /* 0x360 pll10 (de) bias */
- u8 reserved_0x364[12];
- u32 pll9_bias; /* 0x370 pll9 (hsic) bias */
- u8 reserved_0x374[4];
- u32 pll2_bias; /* 0x378 pll2 (audio) bias */
- u8 reserved_0x37c[132];
- u32 pll1_tun; /* 0x400 pll1 (cpux) tunning */
- u8 reserved_0x404[252];
- u32 cpu_axi_cfg; /* 0x500 CPUX/AXI clock control*/
- u8 reserved_0x504[12];
- u32 psi_ahb1_ahb2_cfg; /* 0x510 PSI/AHB1/AHB2 clock control */
- u8 reserved_0x514[8];
- u32 ahb3_cfg; /* 0x51c AHB3 clock control */
- u32 apb1_cfg; /* 0x520 APB1 clock control */
- u32 apb2_cfg; /* 0x524 APB2 clock control */
- u8 reserved_0x528[24];
- u32 mbus_cfg; /* 0x540 MBUS clock control */
- u8 reserved_0x544[188];
- u32 de_clk_cfg; /* 0x600 DE clock control */
- u8 reserved_0x604[8];
- u32 de_gate_reset; /* 0x60c DE gate/reset control */
- u8 reserved_0x610[16];
- u32 di_clk_cfg; /* 0x620 DI clock control */
- u8 reserved_0x024[8];
- u32 di_gate_reset; /* 0x62c DI gate/reset control */
- u8 reserved_0x630[64];
- u32 gpu_clk_cfg; /* 0x670 GPU clock control */
- u8 reserved_0x674[8];
- u32 gpu_gate_reset; /* 0x67c GPU gate/reset control */
- u32 ce_clk_cfg; /* 0x680 CE clock control */
- u8 reserved_0x684[8];
- u32 ce_gate_reset; /* 0x68c CE gate/reset control */
- u32 ve_clk_cfg; /* 0x690 VE clock control */
- u8 reserved_0x694[8];
- u32 ve_gate_reset; /* 0x69c VE gate/reset control */
- u8 reserved_0x6a0[16];
- u32 emce_clk_cfg; /* 0x6b0 EMCE clock control */
- u8 reserved_0x6b4[8];
- u32 emce_gate_reset; /* 0x6bc EMCE gate/reset control */
- u32 vp9_clk_cfg; /* 0x6c0 VP9 clock control */
- u8 reserved_0x6c4[8];
- u32 vp9_gate_reset; /* 0x6cc VP9 gate/reset control */
- u8 reserved_0x6d0[60];
- u32 dma_gate_reset; /* 0x70c DMA gate/reset control */
- u8 reserved_0x710[12];
- u32 msgbox_gate_reset; /* 0x71c Message Box gate/reset control */
- u8 reserved_0x720[12];
- u32 spinlock_gate_reset;/* 0x72c Spinlock gate/reset control */
- u8 reserved_0x730[12];
- u32 hstimer_gate_reset; /* 0x73c HS Timer gate/reset control */
- u32 avs_gate_reset; /* 0x740 AVS gate/reset control */
- u8 reserved_0x744[72];
- u32 dbgsys_gate_reset; /* 0x78c Debugging system gate/reset control */
- u8 reserved_0x790[12];
- u32 psi_gate_reset; /* 0x79c PSI gate/reset control */
- u8 reserved_0x7a0[12];
- u32 pwm_gate_reset; /* 0x7ac PWM gate/reset control */
- u8 reserved_0x7b0[12];
- u32 iommu_gate_reset; /* 0x7bc IOMMU gate/reset control */
- u8 reserved_0x7c0[64];
- u32 dram_clk_cfg; /* 0x800 DRAM clock control */
- u32 mbus_gate; /* 0x804 MBUS gate control */
- u8 reserved_0x808[4];
- u32 dram_gate_reset; /* 0x80c DRAM gate/reset control */
- u32 nand0_clk_cfg; /* 0x810 NAND0 clock control */
- u32 nand1_clk_cfg; /* 0x814 NAND1 clock control */
- u8 reserved_0x818[20];
- u32 nand_gate_reset; /* 0x82c NAND gate/reset control */
- u32 sd0_clk_cfg; /* 0x830 MMC0 clock control */
- u32 sd1_clk_cfg; /* 0x834 MMC1 clock control */
- u32 sd2_clk_cfg; /* 0x838 MMC2 clock control */
- u8 reserved_0x83c[16];
- u32 sd_gate_reset; /* 0x84c MMC gate/reset control */
- u8 reserved_0x850[188];
- u32 uart_gate_reset; /* 0x90c UART gate/reset control */
- u8 reserved_0x910[12];
- u32 twi_gate_reset; /* 0x91c I2C gate/reset control */
- u8 reserved_0x920[28];
- u32 scr_gate_reset; /* 0x93c SCR gate/reset control */
- u32 spi0_clk_cfg; /* 0x940 SPI0 clock control */
- u32 spi1_clk_cfg; /* 0x944 SPI1 clock control */
- u8 reserved_0x948[36];
- u32 spi_gate_reset; /* 0x96c SPI gate/reset control */
- u8 reserved_0x970[12];
- u32 emac_gate_reset; /* 0x97c EMAC gate/reset control */
- u8 reserved_0x980[48];
- u32 ts_clk_cfg; /* 0x9b0 TS clock control */
- u8 reserved_0x9b4[8];
- u32 ts_gate_reset; /* 0x9bc TS gate/reset control */
- u32 irtx_clk_cfg; /* 0x9c0 IR TX clock control */
- u8 reserved_0x9c4[8];
- u32 irtx_gate_reset; /* 0x9cc IR TX gate/reset control */
- u8 reserved_0x9d0[44];
- u32 ths_gate_reset; /* 0x9fc THS gate/reset control */
- u8 reserved_0xa00[12];
- u32 i2s3_clk_cfg; /* 0xa0c I2S3 clock control */
- u32 i2s0_clk_cfg; /* 0xa10 I2S0 clock control */
- u32 i2s1_clk_cfg; /* 0xa14 I2S1 clock control */
- u32 i2s2_clk_cfg; /* 0xa18 I2S2 clock control */
- u32 i2s_gate_reset; /* 0xa1c I2S gate/reset control */
- u32 spdif_clk_cfg; /* 0xa20 SPDIF clock control */
- u8 reserved_0xa24[8];
- u32 spdif_gate_reset; /* 0xa2c SPDIF gate/reset control */
- u8 reserved_0xa30[16];
- u32 dmic_clk_cfg; /* 0xa40 DMIC clock control */
- u8 reserved_0xa44[8];
- u32 dmic_gate_reset; /* 0xa4c DMIC gate/reset control */
- u8 reserved_0xa50[16];
- u32 ahub_clk_cfg; /* 0xa60 Audio HUB clock control */
- u8 reserved_0xa64[8];
- u32 ahub_gate_reset; /* 0xa6c Audio HUB gate/reset control */
- u32 usb0_clk_cfg; /* 0xa70 USB0(OTG) clock control */
- u32 usb1_clk_cfg; /* 0xa74 USB1(XHCI) clock control */
- u8 reserved_0xa78[4];
- u32 usb3_clk_cfg; /* 0xa78 USB3 clock control */
- u8 reserved_0xa80[12];
- u32 usb_gate_reset; /* 0xa8c USB gate/reset control */
- u8 reserved_0xa90[32];
- u32 pcie_ref_clk_cfg; /* 0xab0 PCIE REF clock control */
- u32 pcie_axi_clk_cfg; /* 0xab4 PCIE AXI clock control */
- u32 pcie_aux_clk_cfg; /* 0xab8 PCIE AUX clock control */
- u32 pcie_gate_reset; /* 0xabc PCIE gate/reset control */
- u8 reserved_0xac0[64];
- u32 hdmi_clk_cfg; /* 0xb00 HDMI clock control */
- u32 hdmi_slow_clk_cfg; /* 0xb04 HDMI slow clock control */
- u8 reserved_0xb08[8];
- u32 hdmi_cec_clk_cfg; /* 0xb10 HDMI CEC clock control */
- u8 reserved_0xb14[8];
- u32 hdmi_gate_reset; /* 0xb1c HDMI gate/reset control */
- u8 reserved_0xb20[60];
- u32 tcon_top_gate_reset;/* 0xb5c TCON TOP gate/reset control */
- u32 tcon_lcd0_clk_cfg; /* 0xb60 TCON LCD0 clock control */
- u8 reserved_0xb64[24];
- u32 tcon_lcd_gate_reset;/* 0xb7c TCON LCD gate/reset control */
- u32 tcon_tv0_clk_cfg; /* 0xb80 TCON TV0 clock control */
- u8 reserved_0xb84[24];
- u32 tcon_tv_gate_reset; /* 0xb9c TCON TV gate/reset control */
- u8 reserved_0xba0[96];
- u32 csi_misc_clk_cfg; /* 0xc00 CSI MISC clock control */
- u32 csi_top_clk_cfg; /* 0xc04 CSI TOP clock control */
- u32 csi_mclk_cfg; /* 0xc08 CSI Master clock control */
- u8 reserved_0xc0c[32];
- u32 csi_gate_reset; /* 0xc2c CSI gate/reset control */
- u8 reserved_0xc30[16];
- u32 hdcp_clk_cfg; /* 0xc40 HDCP clock control */
- u8 reserved_0xc44[8];
- u32 hdcp_gate_reset; /* 0xc4c HDCP gate/reset control */
- u8 reserved_0xc50[688];
- u32 ccu_sec_switch; /* 0xf00 CCU security switch */
- u32 pll_lock_dbg_ctrl; /* 0xf04 PLL lock debugging control */
-};
+#define CCU_H6_PLL1_CFG 0x000
+#define CCU_H6_PLL5_CFG 0x010
+#define CCU_H6_PLL6_CFG 0x020
+#define CCU_H6_CPU_AXI_CFG 0x500
+#define CCU_H6_PSI_AHB1_AHB2_CFG 0x510
+#define CCU_H6_AHB3_CFG 0x51c
+#define CCU_H6_APB1_CFG 0x520
+#define CCU_H6_APB2_CFG 0x524
+#define CCU_H6_MBUS_CFG 0x540
+#define CCU_H6_DRAM_CLK_CFG 0x800
+#define CCU_H6_DRAM_GATE_RESET 0x80c
+#define CCU_MMC0_CLK_CFG 0x830
+#define CCU_MMC1_CLK_CFG 0x834
+#define CCU_MMC2_CLK_CFG 0x838
+#define CCU_H6_MMC_GATE_RESET 0x84c
+#define CCU_H6_UART_GATE_RESET 0x90c
+#define CCU_H6_I2C_GATE_RESET 0x91c
/* pll1 bit field */
#define CCM_PLL1_CTRL_EN BIT(31)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 7fcf340..28c3fac 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -10,6 +10,13 @@
#ifndef _SUNXI_CLOCK_SUN6I_H
#define _SUNXI_CLOCK_SUN6I_H
+#define CCU_AHB_GATE0 0x060
+#define CCU_MMC0_CLK_CFG 0x088
+#define CCU_MMC1_CLK_CFG 0x08c
+#define CCU_MMC2_CLK_CFG 0x090
+#define CCU_MMC3_CLK_CFG 0x094
+#define CCU_AHB_RESET0_CFG 0x2c0
+
struct sunxi_ccm_reg {
u32 pll1_cfg; /* 0x00 pll1 control */
u32 reserved0;
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h
index 35ca049..5ad2163 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h
@@ -13,6 +13,13 @@
#ifndef _SUNXI_CLOCK_SUN8I_A83T_H
#define _SUNXI_CLOCK_SUN8I_A83T_H
+#define CCU_AHB_GATE0 0x060
+#define CCU_MMC0_CLK_CFG 0x088
+#define CCU_MMC1_CLK_CFG 0x08c
+#define CCU_MMC2_CLK_CFG 0x090
+#define CCU_MMC3_CLK_CFG 0x094
+#define CCU_AHB_RESET0_CFG 0x2c0
+
struct sunxi_ccm_reg {
u32 pll1_c0_cfg; /* 0x00 c1cpu# pll control */
u32 pll1_c1_cfg; /* 0x04 c1cpu# pll control */
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
index 006f776..8d696e5 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
@@ -12,6 +12,13 @@
#include <linux/bitops.h>
#endif
+#define CCU_MMC0_CLK_CFG 0x410
+#define CCU_MMC1_CLK_CFG 0x414
+#define CCU_MMC2_CLK_CFG 0x418
+#define CCU_MMC3_CLK_CFG 0x41c
+#define CCU_AHB_GATE0 0x580
+#define CCU_AHB_RESET0_CFG 0x5a0
+
struct sunxi_ccm_reg {
u32 pll1_c0_cfg; /* 0x00 c0cpu# pll configuration */
u32 pll2_c1_cfg; /* 0x04 c1cpu# pll configuration */
diff --git a/arch/arm/include/asm/arch-sunxi/dram_dw_helpers.h b/arch/arm/include/asm/arch-sunxi/dram_dw_helpers.h
new file mode 100644
index 0000000..bc9e0d8
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dram_dw_helpers.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Helpers that are commonly used with DW memory controller.
+ *
+ * (C) Copyright 2025 Jernej Skrabec <jernej.skrabec@gmail.com>
+ *
+ */
+
+#ifndef _DRAM_DW_HELPERS_H
+#define _DRAM_DW_HELPERS_H
+
+#include <asm/arch/dram.h>
+
+bool mctl_core_init(const struct dram_para *para,
+ const struct dram_config *config);
+void mctl_auto_detect_rank_width(const struct dram_para *para,
+ struct dram_config *config);
+void mctl_auto_detect_dram_size(const struct dram_para *para,
+ struct dram_config *config);
+unsigned long mctl_calc_size(const struct dram_config *config);
+
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
index f0caecc..af6cd33 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
@@ -315,12 +315,15 @@
struct dram_para {
u32 clk;
enum sunxi_dram_type type;
+ const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE];
+ const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE];
+};
+
+struct dram_config {
u8 cols;
u8 rows;
u8 ranks;
u8 bus_full_width;
- const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE];
- const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE];
};
static inline int ns_to_t(int nanoseconds)
@@ -330,6 +333,6 @@
return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
}
-void mctl_set_timing_params(struct dram_para *para);
+void mctl_set_timing_params(void);
#endif /* _SUNXI_DRAM_SUN50I_H6_H */
diff --git a/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h b/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h
index fd63d3a..d6653c3 100644
--- a/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h
@@ -9,46 +9,12 @@
#define _SUN50I_PRCM_H
#ifndef __ASSEMBLY__
-#include <linux/compiler.h>
-struct sunxi_prcm_reg {
- u32 cpus_cfg; /* 0x000 */
- u8 res0[0x8]; /* 0x004 */
- u32 apbs1_cfg; /* 0x00c */
- u32 apbs2_cfg; /* 0x010 */
- u8 res1[0x108]; /* 0x014 */
- u32 tmr_gate_reset; /* 0x11c */
- u8 res2[0xc]; /* 0x120 */
- u32 twd_gate_reset; /* 0x12c */
- u8 res3[0xc]; /* 0x130 */
- u32 pwm_gate_reset; /* 0x13c */
- u8 res4[0x4c]; /* 0x140 */
- u32 uart_gate_reset; /* 0x18c */
- u8 res5[0xc]; /* 0x190 */
- u32 twi_gate_reset; /* 0x19c */
- u8 res6[0x1c]; /* 0x1a0 */
- u32 rsb_gate_reset; /* 0x1bc */
- u32 cir_cfg; /* 0x1c0 */
- u8 res7[0x8]; /* 0x1c4 */
- u32 cir_gate_reset; /* 0x1cc */
- u8 res8[0x10]; /* 0x1d0 */
- u32 w1_cfg; /* 0x1e0 */
- u8 res9[0x8]; /* 0x1e4 */
- u32 w1_gate_reset; /* 0x1ec */
- u8 res10[0x1c]; /* 0x1f0 */
- u32 rtc_gate_reset; /* 0x20c */
- u8 res11[0x34]; /* 0x210 */
- u32 pll_ldo_cfg; /* 0x244 */
- u8 res12[0x8]; /* 0x248 */
- u32 sys_pwroff_gating; /* 0x250 */
- u8 res13[0xbc]; /* 0x254 */
- u32 res_cal_ctrl; /* 0x310 */
- u32 ohms200; /* 0x314 */
- u32 ohms240; /* 0x318 */
- u32 res_cal_status; /* 0x31c */
-};
-check_member(sunxi_prcm_reg, rtc_gate_reset, 0x20c);
-check_member(sunxi_prcm_reg, res_cal_status, 0x31c);
+#define CCU_PRCM_I2C_GATE_RESET 0x19c
+#define CCU_PRCM_PLL_LDO_CFG 0x244
+#define CCU_PRCM_SYS_PWROFF_GATING 0x250
+#define CCU_PRCM_RES_CAL_CTRL 0x310
+#define CCU_PRCM_OHMS240 0x318
#define PRCM_TWI_GATE (1 << 0)
#define PRCM_TWI_RESET (1 << 16)
diff --git a/arch/arm/include/asm/arch-tegra20/funcmux.h b/arch/arm/include/asm/arch-tegra20/funcmux.h
index e9e96c1..bafcf85 100644
--- a/arch/arm/include/asm/arch-tegra20/funcmux.h
+++ b/arch/arm/include/asm/arch-tegra20/funcmux.h
@@ -19,6 +19,7 @@
FUNCMUX_UART1_UAA_UAB,
FUNCMUX_UART1_GPU,
FUNCMUX_UART1_SDIO1,
+ FUNCMUX_UART1_SDB_SDD,
FUNCMUX_UART2_UAD = 0,
FUNCMUX_UART4_GMC = 0,
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 849b3d0..4c1b814 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -428,11 +428,21 @@
#define wfi()
#endif
+#if !defined(__thumb2__)
+/*
+ * We will need to switch to ARM mode (.arm) for some instructions such as
+ * mrc p15 etc.
+ */
+#define asm_arm_or_thumb2(insn) asm volatile(".arm\n\t" insn)
+#else
+#define asm_arm_or_thumb2(insn) asm volatile(insn)
+#endif
+
static inline unsigned long read_mpidr(void)
{
unsigned long val;
- asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (val));
+ asm_arm_or_thumb2("mrc p15, 0, %0, c0, c0, 5" : "=r" (val));
return val;
}
@@ -461,11 +471,13 @@
unsigned int val;
if (is_hyp())
- asm volatile("mrc p15, 4, %0, c1, c0, 0 @ get CR" : "=r" (val)
+ asm_arm_or_thumb2("mrc p15, 4, %0, c1, c0, 0 @ get CR"
+ : "=r" (val)
:
: "cc");
else
- asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val)
+ asm_arm_or_thumb2("mrc p15, 0, %0, c1, c0, 0 @ get CR"
+ : "=r" (val)
:
: "cc");
return val;
@@ -474,11 +486,11 @@
static inline void set_cr(unsigned int val)
{
if (is_hyp())
- asm volatile("mcr p15, 4, %0, c1, c0, 0 @ set CR" :
+ asm_arm_or_thumb2("mcr p15, 4, %0, c1, c0, 0 @ set CR" :
: "r" (val)
: "cc");
else
- asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" :
+ asm_arm_or_thumb2("mcr p15, 0, %0, c1, c0, 0 @ set CR" :
: "r" (val)
: "cc");
isb();
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 74cd505..ade42d0 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -97,7 +97,7 @@
# some files can only build in ARM or THUMB2, not THUMB1
-ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD
+ifdef CONFIG_$(PHASE_)SYS_THUMB_BUILD
asflags-$(CONFIG_HAS_THUMB2) += -DCONFIG_THUMB2_KERNEL
ifndef CONFIG_HAS_THUMB2
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index dd19bd3..ed6f15c 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -10,6 +10,7 @@
#include <malloc.h>
#include <asm/cache.h>
#include <asm/global_data.h>
+#include <asm/system.h>
#include <linux/errno.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -126,8 +127,8 @@
{
unsigned int val = 0;
- asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
- : : "r" (val) : "cc");
+ asm_arm_or_thumb2("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
+ : : "r" (val) : "cc");
isb();
}
#endif
diff --git a/arch/arm/lib/setjmp.S b/arch/arm/lib/setjmp.S
index 2f041ae..81bef57 100644
--- a/arch/arm/lib/setjmp.S
+++ b/arch/arm/lib/setjmp.S
@@ -34,3 +34,15 @@
ret lr
ENDPROC(longjmp)
.popsection
+
+.pushsection .text.initjmp, "ax"
+ENTRY(initjmp)
+ stm a1, {v1-v8}
+ /* a2: entry point address, a3: stack base, a4: stack size */
+ add a3, a3, a4
+ str a3, [a1, #32] /* where setjmp would save sp */
+ str a2, [a1, #36] /* where setjmp would save lr */
+ mov a1, #0
+ ret lr
+ENDPROC(initjmp)
+.popsection
diff --git a/arch/arm/lib/setjmp_aarch64.S b/arch/arm/lib/setjmp_aarch64.S
index 1b8d000..01193cc 100644
--- a/arch/arm/lib/setjmp_aarch64.S
+++ b/arch/arm/lib/setjmp_aarch64.S
@@ -39,3 +39,13 @@
ret
ENDPROC(longjmp)
.popsection
+
+.pushsection .text.initjmp, "ax"
+ENTRY(initjmp)
+ /* x1: entry point address, x2: stack base, x3: stack size */
+ add x2, x2, x3
+ stp x1, x2, [x0,#88]
+ mov x0, #0
+ ret
+ENDPROC(initjmp)
+.popsection
diff --git a/arch/arm/mach-apple/Makefile b/arch/arm/mach-apple/Makefile
index 50b465b..d79a3a6 100644
--- a/arch/arm/mach-apple/Makefile
+++ b/arch/arm/mach-apple/Makefile
@@ -3,4 +3,5 @@
obj-y += board.o
obj-y += lowlevel_init.o
obj-y += rtkit.o
+obj-$(CONFIG_APPLE_MTP_KEYB) += rtkit_helper.o
obj-$(CONFIG_NVME_APPLE) += sart.o
diff --git a/arch/arm/mach-apple/rtkit.c b/arch/arm/mach-apple/rtkit.c
index b8f4771..f356154 100644
--- a/arch/arm/mach-apple/rtkit.c
+++ b/arch/arm/mach-apple/rtkit.c
@@ -11,6 +11,7 @@
#include <linux/apple-mailbox.h>
#include <linux/bitfield.h>
#include <linux/errno.h>
+#include <linux/sizes.h>
#include <linux/types.h>
#define APPLE_RTKIT_EP_MGMT 0
@@ -18,6 +19,7 @@
#define APPLE_RTKIT_EP_SYSLOG 2
#define APPLE_RTKIT_EP_DEBUG 3
#define APPLE_RTKIT_EP_IOREPORT 4
+#define APPLE_RTKIT_EP_OSLOG 8
#define APPLE_RTKIT_EP_TRACEKIT 10
/* Messages for management endpoint. */
@@ -36,6 +38,7 @@
#define APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE 6
#define APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE_ACK 7
+#define APPLE_RTKIT_MGMT_SET_AP_PWR_STATE 11
#define APPLE_RTKIT_MGMT_EPMAP 8
#define APPLE_RTKIT_MGMT_EPMAP_LAST BIT(51)
@@ -45,6 +48,11 @@
#define APPLE_RTKIT_MGMT_EPMAP_REPLY 8
#define APPLE_RTKIT_MGMT_EPMAP_REPLY_MORE BIT(0)
+#define APPLE_RTKIT_OSLOG_TYPE GENMASK_ULL(63, 56)
+#define APPLE_RTKIT_OSLOG_BUFFER_REQUEST 1
+#define APPLE_RTKIT_OSLOG_SIZE GENMASK_ULL(55, 36)
+#define APPLE_RTKIT_OSLOG_IOVA GENMASK_ULL(35, 0)
+
#define APPLE_RTKIT_MIN_SUPPORTED_VERSION 11
#define APPLE_RTKIT_MAX_SUPPORTED_VERSION 12
@@ -64,6 +72,10 @@
struct apple_rtkit_buffer syslog_buffer;
struct apple_rtkit_buffer crashlog_buffer;
struct apple_rtkit_buffer ioreport_buffer;
+ struct apple_rtkit_buffer oslog_buffer;
+
+ int iop_pwr;
+ int ap_pwr;
};
struct apple_rtkit *apple_rtkit_init(struct mbox_chan *chan, void *cookie,
@@ -93,6 +105,17 @@
rtk->shmem_destroy(rtk->cookie, &rtk->crashlog_buffer);
if (rtk->ioreport_buffer.buffer)
rtk->shmem_destroy(rtk->cookie, &rtk->ioreport_buffer);
+ if (rtk->oslog_buffer.buffer)
+ rtk->shmem_destroy(rtk->cookie, &rtk->oslog_buffer);
+ } else {
+ if (rtk->syslog_buffer.buffer)
+ free(rtk->syslog_buffer.buffer);
+ if (rtk->crashlog_buffer.buffer)
+ free(rtk->crashlog_buffer.buffer);
+ if (rtk->ioreport_buffer.buffer)
+ free(rtk->ioreport_buffer.buffer);
+ if (rtk->oslog_buffer.buffer)
+ free(rtk->oslog_buffer.buffer);
}
free(rtk);
}
@@ -100,16 +123,8 @@
static int rtkit_handle_buf_req(struct apple_rtkit *rtk, int endpoint, struct apple_mbox_msg *msg)
{
struct apple_rtkit_buffer *buf;
- size_t num_4kpages;
int ret;
- num_4kpages = FIELD_GET(APPLE_RTKIT_BUFFER_REQUEST_SIZE, msg->msg0);
-
- if (num_4kpages == 0) {
- printf("%s: unexpected request for buffer without size\n", __func__);
- return -1;
- }
-
switch (endpoint) {
case APPLE_RTKIT_EP_CRASHLOG:
buf = &rtk->crashlog_buffer;
@@ -120,14 +135,33 @@
case APPLE_RTKIT_EP_IOREPORT:
buf = &rtk->ioreport_buffer;
break;
+ case APPLE_RTKIT_EP_OSLOG:
+ buf = &rtk->oslog_buffer;
+ break;
default:
printf("%s: unexpected endpoint %d\n", __func__, endpoint);
return -1;
}
+ switch (endpoint) {
+ case APPLE_RTKIT_EP_OSLOG:
+ buf->size = FIELD_GET(APPLE_RTKIT_OSLOG_SIZE, msg->msg0);
+ buf->dva = FIELD_GET(APPLE_RTKIT_OSLOG_IOVA, msg->msg0 << 12);
+ break;
+ default:
+ buf->size = FIELD_GET(APPLE_RTKIT_BUFFER_REQUEST_SIZE, msg->msg0) << 12;
+ buf->dva = FIELD_GET(APPLE_RTKIT_BUFFER_REQUEST_IOVA, msg->msg0);
+ break;
+ }
+
+ if (buf->size == 0) {
+ printf("%s: unexpected request for buffer without size\n", __func__);
+ return -1;
+ }
+
buf->dva = FIELD_GET(APPLE_RTKIT_BUFFER_REQUEST_IOVA, msg->msg0);
- buf->size = num_4kpages << 12;
- buf->is_mapped = false;
+ buf->is_mapped = !!buf->dva;
+ buf->endpoint = endpoint;
if (rtk->shmem_setup) {
ret = rtk->shmem_setup(rtk->cookie, buf);
@@ -136,13 +170,27 @@
endpoint);
return ret;
}
+ } else if (!buf->is_mapped){
+ buf->buffer = memalign(SZ_16K, ALIGN(buf->size, SZ_16K));
+ if (!buf->buffer)
+ return -ENOMEM;
+
+ buf->dva = (u64)buf->buffer;
}
if (!buf->is_mapped) {
- msg->msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_BUFFER_REQUEST) |
- FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_SIZE, num_4kpages) |
- FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_IOVA, buf->dva);
- msg->msg1 = endpoint;
+ /* oslog uses different fields */
+ if (endpoint == APPLE_RTKIT_EP_OSLOG) {
+ msg->msg0 = FIELD_PREP(APPLE_RTKIT_OSLOG_TYPE,
+ APPLE_RTKIT_OSLOG_BUFFER_REQUEST);
+ msg->msg0 |= FIELD_PREP(APPLE_RTKIT_OSLOG_SIZE, buf->size);
+ msg->msg0 |= FIELD_PREP(APPLE_RTKIT_OSLOG_IOVA, buf->dva >> 12);
+ } else {
+ msg->msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE,
+ APPLE_RTKIT_BUFFER_REQUEST);
+ msg->msg0 |= FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_SIZE, buf->size >> 12);
+ msg->msg0 |= FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_IOVA, buf->dva);
+ }
return mbox_send(rtk->chan, msg);
}
@@ -150,6 +198,89 @@
return 0;
}
+int apple_rtkit_poll(struct apple_rtkit *rtk, ulong timeout)
+{
+ struct apple_mbox_msg msg;
+ int ret;
+ int endpoint;
+ int msgtype;
+
+ ret = mbox_recv(rtk->chan, &msg, timeout);
+ if (ret < 0)
+ return ret;
+
+ endpoint = msg.msg1;
+ msgtype = FIELD_GET(APPLE_RTKIT_MGMT_TYPE, msg.msg0);
+
+ if (endpoint == APPLE_RTKIT_EP_CRASHLOG ||
+ endpoint == APPLE_RTKIT_EP_SYSLOG ||
+ endpoint == APPLE_RTKIT_EP_IOREPORT) {
+ if (msgtype == APPLE_RTKIT_BUFFER_REQUEST) {
+ ret = rtkit_handle_buf_req(rtk, endpoint, &msg);
+ if (ret < 0)
+ return ret;
+ return 0;
+ }
+ }
+
+ if (endpoint == APPLE_RTKIT_EP_OSLOG) {
+ msgtype = FIELD_GET(APPLE_RTKIT_OSLOG_TYPE, msg.msg0);
+
+ if (msgtype == APPLE_RTKIT_OSLOG_BUFFER_REQUEST) {
+ ret = rtkit_handle_buf_req(rtk, endpoint, &msg);
+ if (ret < 0)
+ return ret;
+ return 0;
+ } else {
+ /* Ignore */
+ return 0;
+ }
+ }
+
+ if (endpoint == APPLE_RTKIT_EP_IOREPORT) {
+ // these two messages have to be ack-ed for proper startup
+ if (msgtype == 0xc || msgtype == 0x8) {
+ ret = mbox_send(rtk->chan, &msg);
+ if (ret < 0)
+ return ret;
+ return 0;
+ }
+ }
+
+ if (endpoint == APPLE_RTKIT_EP_SYSLOG) {
+ /* Ignore init */
+ if (msgtype == 0x8)
+ return 0;
+
+ /* Ack logs */
+ if (msgtype == 0x5) {
+ ret = mbox_send(rtk->chan, &msg);
+ if (ret < 0)
+ return ret;
+ return 0;
+ }
+ }
+
+ if (endpoint != APPLE_RTKIT_EP_MGMT) {
+ printf("%s: unexpected endpoint %d\n", __func__, endpoint);
+ return -EINVAL;
+ }
+
+ switch (msgtype) {
+ case APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE_ACK:
+ rtk->iop_pwr = FIELD_GET(APPLE_RTKIT_MGMT_PWR_STATE, msg.msg0);
+ return 0;
+ case APPLE_RTKIT_MGMT_SET_AP_PWR_STATE:
+ rtk->ap_pwr = FIELD_GET(APPLE_RTKIT_MGMT_PWR_STATE, msg.msg0);
+ return 0;
+ default:
+ printf("%s: unexpected message type %d\n", __func__, msgtype);
+
+ /* Just ignore it */
+ return 0;
+ }
+}
+
int apple_rtkit_boot(struct apple_rtkit *rtk)
{
struct apple_mbox_msg msg;
@@ -157,7 +288,7 @@
int nendpoints = 0;
int endpoint;
int min_ver, max_ver, want_ver;
- int msgtype, pwrstate;
+ int msgtype;
u64 reply;
u32 bitmap, base;
int i, ret;
@@ -276,46 +407,37 @@
return ret;
}
- pwrstate = APPLE_RTKIT_PWR_STATE_SLEEP;
- while (pwrstate != APPLE_RTKIT_PWR_STATE_ON) {
- ret = mbox_recv(rtk->chan, &msg, TIMEOUT_1SEC_US);
+ rtk->iop_pwr = APPLE_RTKIT_PWR_STATE_SLEEP;
+ rtk->ap_pwr = APPLE_RTKIT_PWR_STATE_QUIESCED;
+
+ while (rtk->iop_pwr != APPLE_RTKIT_PWR_STATE_ON) {
+ ret = apple_rtkit_poll(rtk, TIMEOUT_1SEC_US);
if (ret < 0)
return ret;
+ }
- endpoint = msg.msg1;
- msgtype = FIELD_GET(APPLE_RTKIT_MGMT_TYPE, msg.msg0);
+ return 0;
+}
- if (endpoint == APPLE_RTKIT_EP_CRASHLOG ||
- endpoint == APPLE_RTKIT_EP_SYSLOG ||
- endpoint == APPLE_RTKIT_EP_IOREPORT) {
- if (msgtype == APPLE_RTKIT_BUFFER_REQUEST) {
- ret = rtkit_handle_buf_req(rtk, endpoint, &msg);
- if (ret < 0)
- return ret;
- continue;
- }
- }
+int apple_rtkit_set_ap_power(struct apple_rtkit *rtk, int pwrstate)
+{
+ struct apple_mbox_msg msg;
+ int ret;
- if (endpoint == APPLE_RTKIT_EP_IOREPORT) {
- // these two messages have to be ack-ed for proper startup
- if (msgtype == 0xc || msgtype == 0x8) {
- ret = mbox_send(rtk->chan, &msg);
- if (ret < 0)
- return ret;
- continue;
- }
- }
+ if (rtk->ap_pwr == pwrstate)
+ return 0;
- if (endpoint != APPLE_RTKIT_EP_MGMT) {
- printf("%s: unexpected endpoint %d\n", __func__, endpoint);
- return -EINVAL;
- }
- if (msgtype != APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE_ACK) {
- printf("%s: unexpected message type %d\n", __func__, msgtype);
- return -EINVAL;
- }
+ msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_SET_AP_PWR_STATE) |
+ FIELD_PREP(APPLE_RTKIT_MGMT_PWR_STATE, pwrstate);
+ msg.msg1 = APPLE_RTKIT_EP_MGMT;
+ ret = mbox_send(rtk->chan, &msg);
+ if (ret < 0)
+ return ret;
- pwrstate = FIELD_GET(APPLE_RTKIT_MGMT_PWR_STATE, msg.msg0);
+ while (rtk->ap_pwr != pwrstate) {
+ ret = apple_rtkit_poll(rtk, TIMEOUT_1SEC_US);
+ if (ret < 0)
+ return ret;
}
return 0;
@@ -326,6 +448,12 @@
struct apple_mbox_msg msg;
int ret;
+ if (rtk->ap_pwr != APPLE_RTKIT_PWR_STATE_QUIESCED) {
+ ret = apple_rtkit_set_ap_power(rtk, APPLE_RTKIT_PWR_STATE_QUIESCED);
+ if (ret < 0)
+ return ret;
+ }
+
msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE) |
FIELD_PREP(APPLE_RTKIT_MGMT_PWR_STATE, pwrstate);
msg.msg1 = APPLE_RTKIT_EP_MGMT;
@@ -333,9 +461,11 @@
if (ret < 0)
return ret;
- ret = mbox_recv(rtk->chan, &msg, TIMEOUT_1SEC_US);
- if (ret < 0)
- return ret;
+ while (rtk->iop_pwr != pwrstate) {
+ ret = apple_rtkit_poll(rtk, TIMEOUT_1SEC_US);
+ if (ret < 0)
+ return ret;
+ }
return 0;
}
diff --git a/arch/arm/mach-apple/rtkit_helper.c b/arch/arm/mach-apple/rtkit_helper.c
new file mode 100644
index 0000000..b7d60e1
--- /dev/null
+++ b/arch/arm/mach-apple/rtkit_helper.c
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright The Asahi Linux Contributors
+ */
+
+#include <dm.h>
+#include <mailbox.h>
+#include <mapmem.h>
+#include <reset.h>
+
+#include <asm/io.h>
+#include <asm/arch/rtkit.h>
+#include <linux/iopoll.h>
+
+/* ASC registers */
+#define REG_CPU_CTRL 0x0044
+#define REG_CPU_CTRL_RUN BIT(4)
+
+#define APPLE_RTKIT_EP_OSLOG 8
+
+struct rtkit_helper_priv {
+ void *asc; /* ASC registers */
+ struct mbox_chan chan;
+ struct apple_rtkit *rtk;
+ bool sram_stolen;
+};
+
+static int shmem_setup(void *cookie, struct apple_rtkit_buffer *buf) {
+ struct udevice *dev = cookie;
+ struct rtkit_helper_priv *priv = dev_get_priv(dev);
+
+ if (!buf->is_mapped) {
+ /*
+ * Special case: The OSLog buffer on MTP persists on Linux handoff.
+ * Steal some SRAM instead of putting this in DRAM, so we don't
+ * have to hand off DART/DAPF mappings.
+ */
+ if (buf->endpoint == APPLE_RTKIT_EP_OSLOG) {
+ if (priv->sram_stolen) {
+ printf("%s: Tried to map more than one OSLog buffer out of SRAM\n",
+ __func__);
+ } else {
+ fdt_size_t size;
+ fdt_addr_t addr;
+
+ addr = dev_read_addr_size_name(dev, "sram", &size);
+
+ if (addr != FDT_ADDR_T_NONE) {
+ buf->dva = ALIGN_DOWN(addr + size - buf->size, SZ_16K);
+ priv->sram_stolen = true;
+
+ return 0;
+ } else {
+ printf("%s: No SRAM, falling back to DRAM\n", __func__);
+ }
+ }
+ }
+
+ buf->buffer = memalign(SZ_16K, ALIGN(buf->size, SZ_16K));
+ if (!buf->buffer)
+ return -ENOMEM;
+
+ buf->dva = (u64)buf->buffer;
+ }
+ return 0;
+}
+
+static void shmem_destroy(void *cookie, struct apple_rtkit_buffer *buf) {
+ if (buf->buffer)
+ free(buf->buffer);
+}
+
+static int rtkit_helper_probe(struct udevice *dev)
+{
+ struct rtkit_helper_priv *priv = dev_get_priv(dev);
+ u32 ctrl;
+ int ret;
+
+ priv->asc = dev_read_addr_ptr(dev);
+ if (!priv->asc)
+ return -EINVAL;
+
+ ret = mbox_get_by_index(dev, 0, &priv->chan);
+ if (ret < 0)
+ return ret;
+
+ ctrl = readl(priv->asc + REG_CPU_CTRL);
+ writel(ctrl | REG_CPU_CTRL_RUN, priv->asc + REG_CPU_CTRL);
+
+ priv->rtk = apple_rtkit_init(&priv->chan, dev, shmem_setup, shmem_destroy);
+ if (!priv->rtk)
+ return -ENOMEM;
+
+ ret = apple_rtkit_boot(priv->rtk);
+ if (ret < 0) {
+ printf("%s: Helper apple_rtkit_boot returned: %d\n", __func__, ret);
+ return ret;
+ }
+
+ ret = apple_rtkit_set_ap_power(priv->rtk, APPLE_RTKIT_PWR_STATE_ON);
+ if (ret < 0) {
+ printf("%s: Helper apple_rtkit_set_ap_power returned: %d\n", __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int rtkit_helper_remove(struct udevice *dev)
+{
+ struct rtkit_helper_priv *priv = dev_get_priv(dev);
+ u32 ctrl;
+
+ apple_rtkit_shutdown(priv->rtk, APPLE_RTKIT_PWR_STATE_QUIESCED);
+
+ ctrl = readl(priv->asc + REG_CPU_CTRL);
+ writel(ctrl & ~REG_CPU_CTRL_RUN, priv->asc + REG_CPU_CTRL);
+
+ apple_rtkit_free(priv->rtk);
+ priv->rtk = NULL;
+
+ return 0;
+}
+
+int apple_rtkit_helper_poll(struct udevice *dev, ulong timeout)
+{
+ struct rtkit_helper_priv *priv = dev_get_priv(dev);
+
+ return apple_rtkit_poll(priv->rtk, timeout);
+}
+
+static const struct udevice_id rtkit_helper_ids[] = {
+ { .compatible = "apple,rtk-helper-asc4" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(rtkit_helper) = {
+ .name = "rtkit_helper",
+ .id = UCLASS_MISC,
+ .of_match = rtkit_helper_ids,
+ .priv_auto = sizeof(struct rtkit_helper_priv),
+ .probe = rtkit_helper_probe,
+ .remove = rtkit_helper_remove,
+ .flags = DM_FLAG_OS_PREPARE,
+};
diff --git a/arch/arm/mach-at91/arm926ejs/Makefile b/arch/arm/mach-at91/arm926ejs/Makefile
index 8f0bc5d..62c44b9 100644
--- a/arch/arm/mach-at91/arm926ejs/Makefile
+++ b/arch/arm/mach-at91/arm926ejs/Makefile
@@ -32,7 +32,7 @@
endif
endif
-ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD
+ifdef CONFIG_$(PHASE_)SYS_THUMB_BUILD
ifndef CONFIG_HAS_THUMB2
CFLAGS_cache.o := -marm
diff --git a/arch/arm/mach-at91/include/mach/atmel_usba_udc.h b/arch/arm/mach-at91/include/mach/atmel_usba_udc.h
index 835b47d..23c7198 100644
--- a/arch/arm/mach-at91/include/mach/atmel_usba_udc.h
+++ b/arch/arm/mach-at91/include/mach/atmel_usba_udc.h
@@ -20,7 +20,7 @@
}
#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \
- defined(CONFIG_AT91SAM9X5)
+ defined(CONFIG_AT91SAM9X5) || defined(CONFIG_SAM9X60)
static struct usba_ep_data usba_udc_ep[] = {
EP("ep0", 0, 64, 1, 0, 0),
EP("ep1", 1, 1024, 2, 1, 1),
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 011cca5..8bd85e8 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -60,7 +60,7 @@
ifneq ($(CONFIG_XPL_BUILD),y)
obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
endif
-obj-$(CONFIG_$(XPL_)SATA) += sata.o
+obj-$(CONFIG_$(PHASE_)SATA) += sata.o
obj-$(CONFIG_IMX_HAB) += hab.o
obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
endif
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 31f2f00..74416a7 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -291,6 +291,12 @@
select IMX8MQ
select IMX8M_LPDDR4
+config TARGET_TORADEX_SMARC_IMX8MP
+ bool "Support Toradex SMARC iMX8M Plus module"
+ select IMX8MP
+ select SUPPORT_SPL
+ select IMX8M_LPDDR4
+
config TARGET_VERDIN_IMX8MM
bool "Support Toradex Verdin iMX8M Mini module"
select IMX8MM
@@ -410,6 +416,7 @@
source "board/ronetix/imx8mq-cm/Kconfig"
source "board/technexion/pico-imx8mq/Kconfig"
source "board/variscite/imx8mn_var_som/Kconfig"
+source "board/toradex/smarc-imx8mp/Kconfig"
source "board/toradex/verdin-imx8mm/Kconfig"
source "board/toradex/verdin-imx8mp/Kconfig"
diff --git a/arch/arm/mach-k3/am62ax/am62a7_init.c b/arch/arm/mach-k3/am62ax/am62a7_init.c
index 698e6d5..28aee34 100644
--- a/arch/arm/mach-k3/am62ax/am62a7_init.c
+++ b/arch/arm/mach-k3/am62ax/am62a7_init.c
@@ -194,6 +194,15 @@
setup_qos();
+ if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS) &&
+ spl_boot_device() == BOOT_DEVICE_ETHERNET) {
+ struct udevice *cpswdev;
+
+ if (uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(am65_cpsw_nuss),
+ &cpswdev))
+ printf("Failed to probe am65_cpsw_nuss driver\n");
+ }
+
debug("am62a_init: %s done\n", __func__);
}
@@ -207,6 +216,10 @@
switch (bootmode) {
case BOOT_DEVICE_EMMC:
+ if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT))
+ return MMCSD_MODE_EMMCBOOT;
+ if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4))
+ return MMCSD_MODE_FS;
return MMCSD_MODE_EMMCBOOT;
case BOOT_DEVICE_MMC:
if (bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK)
diff --git a/arch/arm/mach-k3/am62px/am62p5_init.c b/arch/arm/mach-k3/am62px/am62p5_init.c
index 01e47de..6e3c66e 100644
--- a/arch/arm/mach-k3/am62px/am62p5_init.c
+++ b/arch/arm/mach-k3/am62px/am62p5_init.c
@@ -262,6 +262,10 @@
switch (bootmode) {
case BOOT_DEVICE_EMMC:
+ if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT))
+ return MMCSD_MODE_EMMCBOOT;
+ if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4))
+ return MMCSD_MODE_FS;
return MMCSD_MODE_EMMCBOOT;
case BOOT_DEVICE_MMC:
if (bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK)
diff --git a/arch/arm/mach-k3/am62x/am625_init.c b/arch/arm/mach-k3/am62x/am625_init.c
index 595fc39..a422919 100644
--- a/arch/arm/mach-k3/am62x/am625_init.c
+++ b/arch/arm/mach-k3/am62x/am625_init.c
@@ -29,6 +29,12 @@
/* TISCI DEV ID for A53 Clock */
#define AM62X_DEV_A53SS0_CORE_0_DEV_ID 135
+struct fwl_data rom_fwls[] = {
+ { "SOC_DEVGRP_MAIN", 641, 1 },
+ { "SOC_DEVGRP_MAIN", 642, 1 },
+ { "SOC_DEVGRP_MAIN", 642, 2 },
+};
+
/*
* This uninitialized global variable would normal end up in the .bss section,
* but the .bss is cleared between writing and reading this variable, so move
@@ -177,6 +183,7 @@
{
struct udevice *dev;
int ret;
+ int i;
if (IS_ENABLED(CONFIG_CPU_V7R)) {
setup_k3_mpu_regions();
@@ -261,6 +268,11 @@
/* Output System Firmware version info */
k3_sysfw_print_ver();
+ /* Disable firewalls ROM has configured. */
+ if (IS_ENABLED(CONFIG_CPU_V7R))
+ for (i = 0; i < ARRAY_SIZE(rom_fwls); i++)
+ remove_fwl_region(&rom_fwls[i]);
+
if (IS_ENABLED(CONFIG_ESM_K3)) {
/* Probe/configure ESM0 */
ret = uclass_get_device_by_name(UCLASS_MISC, "esm@420000", &dev);
diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h
index 7bd72da..2ec60c7 100644
--- a/arch/arm/mach-k3/common.h
+++ b/arch/arm/mach-k3/common.h
@@ -35,6 +35,7 @@
void setup_k3_mpu_regions(void);
int early_console_init(void);
void disable_linefill_optimization(void);
+int remove_fwl_region(struct fwl_data *fwl);
void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size);
int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr);
void k3_sysfw_print_ver(void);
diff --git a/arch/arm/mach-k3/common_fdt.c b/arch/arm/mach-k3/common_fdt.c
index 361b0c0..867ed17 100644
--- a/arch/arm/mach-k3/common_fdt.c
+++ b/arch/arm/mach-k3/common_fdt.c
@@ -119,6 +119,9 @@
{
int nodeoffset, subnode;
int ret;
+ struct fdt_memory carveout = {
+ .start = new_address,
+ };
/* Find reserved-memory */
nodeoffset = fdt_subnode_offset(blob, 0, "reserved-memory");
@@ -153,10 +156,7 @@
}
add_carveout:
- struct fdt_memory carveout = {
- .start = new_address,
- .end = new_address + new_size - 1,
- };
+ carveout.end = new_address + new_size - 1;
ret = fdtdec_add_reserved_memory(blob, name, &carveout, NULL, 0, NULL,
FDTDEC_RESERVED_MEMORY_NO_MAP);
if (ret < 0)
diff --git a/arch/arm/mach-k3/r5/am62ax/clk-data.c b/arch/arm/mach-k3/r5/am62ax/clk-data.c
index d950b35..9d9a43c 100644
--- a/arch/arm/mach-k3/r5/am62ax/clk-data.c
+++ b/arch/arm/mach-k3/r5/am62ax/clk-data.c
@@ -64,9 +64,20 @@
static const char * const clkout0_ctrl_out0_parents[] = {
"hsdiv4_16fft_main_2_hsdivout1_clk",
- "hsdiv4_16fft_main_2_hsdivout1_clk",
+ "hsdiv4_16fft_main_2_hsdivout1_clk10",
};
+static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
+ "postdiv4_16ff_main_2_hsdivout5_clk",
+ "postdiv4_16ff_main_0_hsdivout6_clk",
+ "board_0_cp_gemac_cpts0_rft_clk_out",
+ NULL,
+ "board_0_mcu_ext_refclk0_out",
+ "board_0_ext_refclk1_out",
+ "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
+ "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
"postdiv4_16ff_main_0_hsdivout5_clk",
"hsdiv4_16fft_main_2_hsdivout2_clk",
@@ -137,7 +148,16 @@
CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rgmii1_rxc_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rgmii1_txc_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rgmii2_rxc_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rgmii2_txc_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_tck_out", 0, 0),
+ CLK_FIXED_RATE("cpsw_3guss_main_0_mdio_mdclk_o", 0, 0),
+ CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii1_txc_o", 0, 0),
+ CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii2_txc_o", 0, 0),
CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
CLK_FIXED_RATE("emmcsd8ss_main_0_emmcsdss_io_clk_o", 0, 0),
CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
@@ -180,6 +200,7 @@
CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0),
CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk10", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0),
CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
@@ -187,6 +208,7 @@
CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
+ CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0),
CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
@@ -203,6 +225,29 @@
};
static const struct dev_clk soc_dev_clk_data[] = {
+ DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"),
+ DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"),
+ DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"),
+ DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"),
+ DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"),
+ DEV_CLK(13, 9, "board_0_ext_refclk1_out"),
+ DEV_CLK(13, 10, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
+ DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 19, "board_0_rgmii1_rxc_out"),
+ DEV_CLK(13, 20, "board_0_rgmii1_txc_out"),
+ DEV_CLK(13, 22, "board_0_rgmii2_rxc_out"),
+ DEV_CLK(13, 23, "board_0_rgmii2_txc_out"),
+ DEV_CLK(13, 25, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 26, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 27, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 28, "board_0_rmii1_ref_clk_out"),
+ DEV_CLK(13, 29, "board_0_rmii2_ref_clk_out"),
DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
@@ -272,16 +317,19 @@
DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(157, 20, "clkout0_ctrl_out0"),
DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
- DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk10"),
DEV_CLK(157, 24, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(157, 25, "board_0_ddr0_ck0_out"),
DEV_CLK(157, 40, "mshsi2c_main_0_porscl"),
DEV_CLK(157, 77, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
+ DEV_CLK(157, 82, "cpsw_3guss_main_0_mdio_mdclk_o"),
DEV_CLK(157, 83, "emmcsd8ss_main_0_emmcsdss_io_clk_o"),
DEV_CLK(157, 85, "emmcsd8ss_main_0_emmcsdss_io_clk_o"),
DEV_CLK(157, 87, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
DEV_CLK(157, 89, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
DEV_CLK(157, 130, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
+ DEV_CLK(157, 133, "cpsw_3guss_main_0_rgmii1_txc_o"),
+ DEV_CLK(157, 136, "cpsw_3guss_main_0_rgmii2_txc_o"),
DEV_CLK(157, 146, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"),
DEV_CLK(157, 159, "wkup_clkout_sel_io_out0"),
DEV_CLK(157, 160, "wkup_clkout_sel_out0"),
@@ -311,7 +359,7 @@
const struct ti_k3_clk_platdata am62ax_clk_platdata = {
.clk_list = clk_list,
- .clk_list_cnt = 80,
+ .clk_list_cnt = 90,
.soc_dev_clk_data = soc_dev_clk_data,
- .soc_dev_clk_data_cnt = 104,
+ .soc_dev_clk_data_cnt = 130,
};
diff --git a/arch/arm/mach-k3/r5/am62ax/dev-data.c b/arch/arm/mach-k3/r5/am62ax/dev-data.c
index 6cced9e..fe02592 100644
--- a/arch/arm/mach-k3/r5/am62ax/dev-data.c
+++ b/arch/arm/mach-k3/r5/am62ax/dev-data.c
@@ -17,9 +17,10 @@
static struct ti_pd soc_pd_list[] = {
[0] = PSC_PD(0, &soc_psc_list[1], NULL),
- [1] = PSC_PD(3, &soc_psc_list[1], &soc_pd_list[0]),
- [2] = PSC_PD(4, &soc_psc_list[1], &soc_pd_list[1]),
- [3] = PSC_PD(13, &soc_psc_list[1], &soc_pd_list[0]),
+ [1] = PSC_PD(2, &soc_psc_list[1], &soc_pd_list[0]),
+ [2] = PSC_PD(3, &soc_psc_list[1], &soc_pd_list[0]),
+ [3] = PSC_PD(4, &soc_psc_list[1], &soc_pd_list[2]),
+ [4] = PSC_PD(13, &soc_psc_list[1], &soc_pd_list[0]),
};
static struct ti_lpsc soc_lpsc_list[] = {
@@ -32,11 +33,12 @@
[6] = PSC_LPSC(24, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
[7] = PSC_LPSC(28, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
[8] = PSC_LPSC(34, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
- [9] = PSC_LPSC(43, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[8]),
- [10] = PSC_LPSC(46, &soc_psc_list[1], &soc_pd_list[2], &soc_lpsc_list[9]),
- [11] = PSC_LPSC(60, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[8]),
- [12] = PSC_LPSC(61, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[11]),
- [13] = PSC_LPSC(62, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[12]),
+ [9] = PSC_LPSC(42, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[8]),
+ [10] = PSC_LPSC(43, &soc_psc_list[1], &soc_pd_list[2], &soc_lpsc_list[8]),
+ [11] = PSC_LPSC(46, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[10]),
+ [12] = PSC_LPSC(60, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[8]),
+ [13] = PSC_LPSC(61, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[12]),
+ [14] = PSC_LPSC(62, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[13]),
};
static struct ti_dev soc_dev_list[] = {
@@ -55,11 +57,12 @@
PSC_DEV(36, &soc_lpsc_list[8]),
PSC_DEV(102, &soc_lpsc_list[8]),
PSC_DEV(146, &soc_lpsc_list[8]),
- PSC_DEV(166, &soc_lpsc_list[9]),
- PSC_DEV(135, &soc_lpsc_list[10]),
- PSC_DEV(170, &soc_lpsc_list[11]),
- PSC_DEV(177, &soc_lpsc_list[12]),
- PSC_DEV(55, &soc_lpsc_list[13]),
+ PSC_DEV(13, &soc_lpsc_list[9]),
+ PSC_DEV(166, &soc_lpsc_list[10]),
+ PSC_DEV(135, &soc_lpsc_list[11]),
+ PSC_DEV(170, &soc_lpsc_list[12]),
+ PSC_DEV(177, &soc_lpsc_list[13]),
+ PSC_DEV(55, &soc_lpsc_list[14]),
};
const struct ti_k3_pd_platdata am62ax_pd_platdata = {
diff --git a/arch/arm/mach-k3/r5/am62px/clk-data.c b/arch/arm/mach-k3/r5/am62px/clk-data.c
index 4b9892f..bc62d1d 100644
--- a/arch/arm/mach-k3/r5/am62px/clk-data.c
+++ b/arch/arm/mach-k3/r5/am62px/clk-data.c
@@ -59,7 +59,7 @@
static const char * const clkout0_ctrl_out0_parents[] = {
"hsdiv4_16fft_main_2_hsdivout1_clk",
- "hsdiv4_16fft_main_2_hsdivout1_clk",
+ "hsdiv4_16fft_main_2_hsdivout1_clk10",
};
static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
@@ -193,6 +193,7 @@
CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
CLK_DIV("hsdiv4_16fft_main_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x68108c, 0, 7, 0, 0),
CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk10", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0),
CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
@@ -281,7 +282,7 @@
DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(157, 36, "clkout0_ctrl_out0"),
DEV_CLK(157, 37, "hsdiv4_16fft_main_2_hsdivout1_clk"),
- DEV_CLK(157, 38, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(157, 38, "hsdiv4_16fft_main_2_hsdivout1_clk10"),
DEV_CLK(157, 40, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(157, 54, "mshsi2c_main_0_porscl"),
DEV_CLK(157, 91, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
diff --git a/arch/arm/mach-k3/r5/common.c b/arch/arm/mach-k3/r5/common.c
index 0f6c294..0b66040 100644
--- a/arch/arm/mach-k3/r5/common.c
+++ b/arch/arm/mach-k3/r5/common.c
@@ -144,7 +144,7 @@
int ret, size = 0, shut_cpu = 0;
/* Release all the exclusive devices held by SPL before starting ATF */
- ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);
+ ti_sci->ops.dev_ops.release_exclusive_devices();
ret = rproc_init();
if (ret)
@@ -253,6 +253,31 @@
asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr));
}
+int remove_fwl_region(struct fwl_data *fwl)
+{
+ struct ti_sci_handle *sci = get_ti_sci_handle();
+ struct ti_sci_fwl_ops *ops = &sci->ops.fwl_ops;
+ struct ti_sci_msg_fwl_region region;
+ int ret;
+
+ region.fwl_id = fwl->fwl_id;
+ region.region = fwl->regions;
+ region.n_permission_regs = 3;
+
+ ops->get_fwl_region(sci, ®ion);
+
+ /* zero out the enable field of the firewall */
+ region.control = region.control & ~0xF;
+
+ pr_debug("Disabling firewall id: %d region: %d\n",
+ region.fwl_id, region.region);
+
+ ret = ops->set_fwl_region(sci, ®ion);
+ if (ret)
+ pr_err("Could not disable firewall\n");
+ return ret;
+}
+
static void remove_fwl_regions(struct fwl_data fwl_data, size_t num_regions,
enum k3_firewall_region_type fwl_type)
{
diff --git a/arch/arm/mach-k3/r5/j7200/clk-data.c b/arch/arm/mach-k3/r5/j7200/clk-data.c
index eb8436d..996ba20 100644
--- a/arch/arm/mach-k3/r5/j7200/clk-data.c
+++ b/arch/arm/mach-k3/r5/j7200/clk-data.c
@@ -62,6 +62,16 @@
"gluelogic_hfosc0_clkout",
};
+static const char * const wkupusart_clk_sel_out0_parents[] = {
+ "hsdiv4_16fft_mcu_1_hsdivout3_clk",
+ "postdiv2_16fft_main_1_hsdivout5_clk",
+};
+
+static const char * const wkup_usart_mcupll_bypass_clksel_out0_parents[] = {
+ "wkupusart_clk_sel_out0",
+ "gluelogic_hfosc0_clkout",
+};
+
static const char * const main_pll_hfosc_sel_out0_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
@@ -345,6 +355,8 @@
CLK_MUX("mcuusart_clk_sel_out0", mcuusart_clk_sel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0),
CLK_MUX("wkup_i2c0_mcupll_bypass_clksel_out0", wkup_i2c0_mcupll_bypass_clksel_out0_parents, 2, 0x43008060, 0, 1, 0),
+ CLK_MUX("wkupusart_clk_sel_out0", wkupusart_clk_sel_out0_parents, 2, 0x43008064, 0, 1, 0),
+ CLK_MUX("wkup_usart_mcupll_bypass_clksel_out0", wkup_usart_mcupll_bypass_clksel_out0_parents, 2, 0x43008060, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out14", main_pll_hfosc_sel_out14_parents, 2, 0x430080b8, 0, 1, 0),
@@ -543,6 +555,10 @@
DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
DEV_CLK(278, 2, "usart_programmable_clock_divider_out1"),
DEV_CLK(278, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(287, 2, "wkup_usart_mcupll_bypass_clksel_out0"),
+ DEV_CLK(287, 3, "wkupusart_clk_sel_out0"),
+ DEV_CLK(287, 4, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(287, 5, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(288, 3, "postdiv2_16fft_main_1_hsdivout7_clk"),
DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(288, 6, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
diff --git a/arch/arm/mach-k3/r5/j7200/dev-data.c b/arch/arm/mach-k3/r5/j7200/dev-data.c
index 8ce6796..12a1386 100644
--- a/arch/arm/mach-k3/r5/j7200/dev-data.c
+++ b/arch/arm/mach-k3/r5/j7200/dev-data.c
@@ -66,6 +66,7 @@
PSC_DEV(149, &soc_lpsc_list[12]),
PSC_DEV(113, &soc_lpsc_list[13]),
PSC_DEV(197, &soc_lpsc_list[13]),
+ PSC_DEV(287, &soc_lpsc_list[13]),
PSC_DEV(103, &soc_lpsc_list[14]),
PSC_DEV(104, &soc_lpsc_list[15]),
PSC_DEV(102, &soc_lpsc_list[16]),
diff --git a/arch/arm/mach-kirkwood/include/mach/cpu.h b/arch/arm/mach-kirkwood/include/mach/cpu.h
index 9eec786..dce190d 100644
--- a/arch/arm/mach-kirkwood/include/mach/cpu.h
+++ b/arch/arm/mach-kirkwood/include/mach/cpu.h
@@ -85,8 +85,9 @@
static inline unsigned int readfr_extra_feature_reg(void)
{
unsigned int val;
- asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r"
- (val)::"cc");
+
+ asm_arm_or_thumb2("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r"
+ (val)::"cc");
return val;
}
@@ -96,8 +97,8 @@
*/
static inline void writefr_extra_feature_reg(unsigned int val)
{
- asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r"
- (val):"cc");
+ asm_arm_or_thumb2("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r"
+ (val):"cc");
isb();
}
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index adb8169..b76510a 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -260,7 +260,7 @@
failure, RL, WL errors and other algorithm failure. At level 1,
provides the D-Unit setup (SPD/Static configuration). At level 2,
provides the windows margin as a results of DQS centeralization.
- At level 3, rovides the windows margin of each DQ as a results of
+ At level 3, provides the windows margin of each DQ as a results of
DQS centeralization.
config DDR_IMMUTABLE_DEBUG_SETTINGS
@@ -394,7 +394,6 @@
imply SPL_LIBDISK_SUPPORT
imply SPL_MMC
select SUPPORT_EMMC_BOOT if SPL_MMC
- select SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR if SPL_MMC
select SPL_BOOTROM_SUPPORT
config MVEBU_SPL_BOOT_DEVICE_SATA
@@ -450,7 +449,7 @@
string "VHV_Enable GPIO name for eFuse programming"
depends on MVEBU_EFUSE && !ARMADA_3700
help
- The eFuse programing (burning) phase requires supplying 1.8V to the
+ The eFuse programming (burning) phase requires supplying 1.8V to the
device on the VHV power pin, while for normal operation the VHV power
rail must be left unconnected. See Marvell AN-389: ARMADA VHV Power
document (Doc. No. MV-S302545-00 Rev. C, August 2, 2016) for details.
diff --git a/arch/arm/mach-omap2/am33xx/Makefile b/arch/arm/mach-omap2/am33xx/Makefile
index 6f3587f..233dcc8 100644
--- a/arch/arm/mach-omap2/am33xx/Makefile
+++ b/arch/arm/mach-omap2/am33xx/Makefile
@@ -11,7 +11,7 @@
obj-y += sys_info.o
obj-y += ddr.o
-ifeq ($(CONFIG_$(XPL_)SKIP_LOWLEVEL_INIT),)
+ifeq ($(CONFIG_$(PHASE_)SKIP_LOWLEVEL_INIT),)
obj-y += emif4.o
endif
obj-y += board.o
diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig
index a175e5c..b50b8a5 100644
--- a/arch/arm/mach-omap2/omap3/Kconfig
+++ b/arch/arm/mach-omap2/omap3/Kconfig
@@ -95,6 +95,7 @@
select OMAP3_GPIO_4
select OMAP3_GPIO_6
imply CMD_DM
+ imply VIDEO_DAMAGE
config TARGET_TAO3530
bool "TAO3530"
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index 3c381de..d0769b5 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -11,13 +11,13 @@
obj-y += dram.o
obj-y += timer.o
-ifndef CONFIG_$(XPL_)SKIP_LOWLEVEL_INIT
+ifndef CONFIG_$(PHASE_)SKIP_LOWLEVEL_INIT
obj-y += lowlevel_init.o
endif
# some files can only build in ARM or THUMB2, not THUMB1
-ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD
+ifdef CONFIG_$(PHASE_)SYS_THUMB_BUILD
ifndef CONFIG_HAS_THUMB2
CFLAGS_cpu.o := -marm
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index c6e347b..9210877 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -15,7 +15,9 @@
select TPL_SERIAL
select DEBUG_UART_BOARD_INIT
imply ROCKCHIP_COMMON_BOARD
+ imply ROCKCHIP_COMMON_STACK_ADDR
imply SPL_ROCKCHIP_COMMON_BOARD
+ imply TPL_LIBGENERIC_SUPPORT
imply ARMV8_CRYPTO
imply ARMV8_SET_SMPEN
help
@@ -176,6 +178,8 @@
imply OF_UPSTREAM
imply RNG_ROCKCHIP
imply ROCKCHIP_COMMON_BOARD
+ imply ROCKCHIP_COMMON_STACK_ADDR
+ imply ROCKCHIP_EXTERNAL_TPL
imply ROCKCHIP_OTP
imply SPL_CLK
imply SPL_DM_SEQ_ALIAS
@@ -197,7 +201,6 @@
select SUPPORT_SPL
select SPL
select SUPPORT_TPL
- select TPL
select TPL_HAVE_INIT_STACK if TPL
imply ARMV8_CRYPTO
imply ARMV8_SET_SMPEN
@@ -208,11 +211,14 @@
imply OF_UPSTREAM
imply PRE_CONSOLE_BUFFER
imply ROCKCHIP_COMMON_BOARD
+ imply ROCKCHIP_COMMON_STACK_ADDR
imply ROCKCHIP_EFUSE
imply ROCKCHIP_SDRAM_COMMON
imply SPL_ROCKCHIP_COMMON_BOARD
imply SPL_SEPARATE_BSS
imply SPL_SERIAL
+ imply TPL if !ROCKCHIP_EXTERNAL_TPL
+ imply TPL_ROCKCHIP_COMMON_BOARD
imply TPL_SERIAL
help
The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
@@ -285,6 +291,7 @@
imply PRE_CONSOLE_BUFFER
imply RNG_ROCKCHIP
imply ROCKCHIP_COMMON_BOARD
+ imply ROCKCHIP_COMMON_STACK_ADDR
imply ROCKCHIP_EFUSE
imply ROCKCHIP_SDRAM_COMMON
imply SPL_DM_SEQ_ALIAS
@@ -312,6 +319,56 @@
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
+config ROCKCHIP_RK3528
+ bool "Support Rockchip RK3528"
+ select ARM64
+ select SUPPORT_SPL
+ select SPL
+ select CLK
+ select PINCTRL
+ select RAM
+ select REGMAP
+ select SYSCON
+ select BOARD_LATE_INIT
+ select DM_REGULATOR_FIXED
+ select DM_RESET
+ imply ARMV8_CRYPTO
+ imply ARMV8_SET_SMPEN
+ imply BOOTSTD_FULL
+ imply DM_RNG
+ imply FIT
+ imply LEGACY_IMAGE_FORMAT
+ imply MISC
+ imply MISC_INIT_R
+ imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
+ imply OF_LIBFDT_OVERLAY
+ imply OF_LIVE
+ imply OF_UPSTREAM
+ imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP
+ imply RNG_ROCKCHIP
+ imply ROCKCHIP_COMMON_BOARD
+ imply ROCKCHIP_COMMON_STACK_ADDR
+ imply ROCKCHIP_EXTERNAL_TPL
+ imply ROCKCHIP_OTP
+ imply SPL_ATF
+ imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
+ imply SPL_CLK
+ imply SPL_DM_SEQ_ALIAS
+ imply SPL_FIT_SIGNATURE
+ imply SPL_LOAD_FIT
+ imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
+ imply SPL_OF_CONTROL
+ imply SPL_PINCTRL
+ imply SPL_RAM
+ imply SPL_REGMAP
+ imply SPL_SERIAL
+ imply SPL_SYSCON
+ imply SYS_RELOC_GD_ENV_ADDR
+ imply SYSRESET
+ imply SYSRESET_PSCI if SPL_ATF
+ help
+ The Rockchip RK3528 is a ARM-based SoC with a quad-core Cortex-A53.
+
config ROCKCHIP_RK3568
bool "Support Rockchip RK3568"
select ARM64
@@ -334,6 +391,8 @@
imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP
imply RNG_ROCKCHIP
imply ROCKCHIP_COMMON_BOARD
+ imply ROCKCHIP_COMMON_STACK_ADDR
+ imply ROCKCHIP_EXTERNAL_TPL
imply ROCKCHIP_OTP
imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
@@ -344,6 +403,56 @@
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
+config ROCKCHIP_RK3576
+ bool "Support Rockchip RK3576"
+ select ARM64
+ select SUPPORT_SPL
+ select SPL
+ select CLK
+ select PINCTRL
+ select RAM
+ select REGMAP
+ select SYSCON
+ select BOARD_LATE_INIT
+ select DM_REGULATOR_FIXED
+ select DM_RESET
+ imply ARMV8_CRYPTO
+ imply ARMV8_SET_SMPEN
+ imply BOOTSTD_FULL
+ imply DM_RNG
+ imply FIT
+ imply LEGACY_IMAGE_FORMAT
+ imply MISC
+ imply MISC_INIT_R
+ imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
+ imply OF_LIBFDT_OVERLAY
+ imply OF_LIVE
+ imply OF_UPSTREAM
+ imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP
+ imply RNG_ROCKCHIP
+ imply ROCKCHIP_COMMON_BOARD
+ imply ROCKCHIP_COMMON_STACK_ADDR
+ imply ROCKCHIP_EXTERNAL_TPL
+ imply ROCKCHIP_OTP
+ imply SPL_ATF
+ imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
+ imply SPL_CLK
+ imply SPL_DM_SEQ_ALIAS
+ imply SPL_FIT_SIGNATURE
+ imply SPL_LOAD_FIT
+ imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
+ imply SPL_OF_CONTROL
+ imply SPL_PINCTRL
+ imply SPL_RAM
+ imply SPL_REGMAP
+ imply SPL_SERIAL
+ imply SPL_SYSCON
+ imply SYS_RELOC_GD_ENV_ADDR
+ imply SYSRESET
+ help
+ The Rockchip RK3576 is a ARM-based SoC with quad-core Cortex-A72 and
+ and quad-core Cortex-A53.
+
config ROCKCHIP_RK3588
bool "Support Rockchip RK3588"
select ARM64
@@ -367,6 +476,8 @@
imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP
imply RNG_ROCKCHIP
imply ROCKCHIP_COMMON_BOARD
+ imply ROCKCHIP_COMMON_STACK_ADDR
+ imply ROCKCHIP_EXTERNAL_TPL
imply ROCKCHIP_OTP
imply SCMI_FIRMWARE
imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
@@ -493,7 +604,6 @@
config ROCKCHIP_EXTERNAL_TPL
bool "Use external TPL binary"
- default y if ROCKCHIP_RK3308 || ROCKCHIP_RK3568 || ROCKCHIP_RK3588
help
Some Rockchip SoCs require an external TPL to initialize DRAM.
Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin to
@@ -603,17 +713,17 @@
config ROCKCHIP_COMMON_STACK_ADDR
bool
depends on SPL_SHARES_INIT_SP_ADDR
+ depends on TPL || ROCKCHIP_EXTERNAL_TPL
select HAS_CUSTOM_SYS_INIT_SP_ADDR
imply SPL_LIBCOMMON_SUPPORT if SPL
imply SPL_LIBGENERIC_SUPPORT if SPL
imply SPL_ROCKCHIP_COMMON_BOARD if SPL
imply SPL_SYS_MALLOC_F if SPL
imply SPL_SYS_MALLOC_SIMPLE if SPL
- imply TPL_LIBCOMMON_SUPPORT if TPL
- imply TPL_LIBGENERIC_SUPPORT if TPL
- imply TPL_ROCKCHIP_COMMON_BOARD if TPL
- imply TPL_SYS_MALLOC_F if TPL
- imply TPL_SYS_MALLOC_SIMPLE if TPL
+ imply TPL_LIBCOMMON_SUPPORT if TPL && TPL_ROCKCHIP_COMMON_BOARD
+ imply TPL_LIBGENERIC_SUPPORT if TPL && TPL_ROCKCHIP_COMMON_BOARD
+ imply TPL_SYS_MALLOC_F if TPL && TPL_ROCKCHIP_COMMON_BOARD
+ imply TPL_SYS_MALLOC_SIMPLE if TPL && TPL_ROCKCHIP_COMMON_BOARD
config NR_DRAM_BANKS
default 10 if ROCKCHIP_EXTERNAL_TPL
@@ -629,7 +739,9 @@
source "arch/arm/mach-rockchip/rk3328/Kconfig"
source "arch/arm/mach-rockchip/rk3368/Kconfig"
source "arch/arm/mach-rockchip/rk3399/Kconfig"
+source "arch/arm/mach-rockchip/rk3528/Kconfig"
source "arch/arm/mach-rockchip/rk3568/Kconfig"
+source "arch/arm/mach-rockchip/rk3576/Kconfig"
source "arch/arm/mach-rockchip/rk3588/Kconfig"
source "arch/arm/mach-rockchip/rv1108/Kconfig"
source "arch/arm/mach-rockchip/rv1126/Kconfig"
@@ -637,40 +749,64 @@
if ROCKCHIP_COMMON_STACK_ADDR && SPL_SHARES_INIT_SP_ADDR
config CUSTOM_SYS_INIT_SP_ADDR
- default 0x3f00000
+ default 0x63f00000 if SPL_TEXT_BASE = 0x60000000
+ default 0x43f00000 if SPL_TEXT_BASE = 0x40000000
+ default 0x03f00000 if SPL_TEXT_BASE = 0x00000000
config SYS_MALLOC_F_LEN
- default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
+ default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x63f00000
+ default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x43f00000
+ default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x03f00000
config SPL_SYS_MALLOC_F_LEN
- default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
+ default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x63f00000
+ default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x43f00000
+ default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x03f00000
config TPL_SYS_MALLOC_F_LEN
- default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
+ default 0x0800 if CUSTOM_SYS_INIT_SP_ADDR = 0x63f00000
+ default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x43f00000
+ default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x03f00000
config TEXT_BASE
- default 0x00200000 if ARM64
+ default 0x60200000 if SPL_TEXT_BASE = 0x60000000
+ default 0x40200000 if SPL_TEXT_BASE = 0x40000000
+ default 0x00200000 if SPL_TEXT_BASE = 0x00000000
config SPL_TEXT_BASE
- default 0x0 if ARM64
+ default 0x60000000 if ROCKCHIP_RK3036 || ROCKCHIP_RK3066 || \
+ ROCKCHIP_RK3128 || ROCKCHIP_RK3188 || \
+ ROCKCHIP_RK322X || ROCKCHIP_RV1108
+ default 0x40000000 if ROCKCHIP_RK3576
+ default 0x00000000
config SPL_HAS_BSS_LINKER_SECTION
default y if ARM64
config SPL_BSS_START_ADDR
- default 0x3f80000
+ default 0x63f80000 if SPL_TEXT_BASE = 0x60000000
+ default 0x43f80000 if SPL_TEXT_BASE = 0x40000000
+ default 0x03f80000 if SPL_TEXT_BASE = 0x00000000
config SPL_BSS_MAX_SIZE
- default 0x8000 if SPL_BSS_START_ADDR = 0x3f80000
+ default 0x8000 if SPL_BSS_START_ADDR = 0x63f80000
+ default 0x8000 if SPL_BSS_START_ADDR = 0x43f80000
+ default 0x8000 if SPL_BSS_START_ADDR = 0x03f80000
config SPL_STACK_R
- default y if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
+ default y if CUSTOM_SYS_INIT_SP_ADDR = 0x63f00000
+ default y if CUSTOM_SYS_INIT_SP_ADDR = 0x43f00000
+ default y if CUSTOM_SYS_INIT_SP_ADDR = 0x03f00000
config SPL_STACK_R_ADDR
- default 0x3e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
+ default 0x63e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x63f00000
+ default 0x43e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x43f00000
+ default 0x03e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x03f00000
config SPL_STACK_R_MALLOC_SIMPLE_LEN
- default 0x200000 if SPL_STACK_R_ADDR = 0x3e00000
+ default 0x200000 if SPL_STACK_R_ADDR = 0x63e00000
+ default 0x200000 if SPL_STACK_R_ADDR = 0x43e00000
+ default 0x200000 if SPL_STACK_R_ADDR = 0x03e00000
endif
endif
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 5e7edc9..ae15a9f 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -42,7 +42,9 @@
obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
+obj-$(CONFIG_ROCKCHIP_RK3528) += rk3528/
obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/
+obj-$(CONFIG_ROCKCHIP_RK3576) += rk3576/
obj-$(CONFIG_ROCKCHIP_RK3588) += rk3588/
obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
obj-$(CONFIG_ROCKCHIP_RV1126) += rv1126/
diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig
index dcf9eb8..2b57b16 100644
--- a/arch/arm/mach-rockchip/px30/Kconfig
+++ b/arch/arm/mach-rockchip/px30/Kconfig
@@ -68,9 +68,6 @@
config SYS_SOC
default "px30"
-config ROCKCHIP_COMMON_STACK_ADDR
- default y
-
config SYS_MALLOC_F_LEN
default 0x400 if !SPL_SHARES_INIT_SP_ADDR
diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig b/arch/arm/mach-rockchip/rk3308/Kconfig
index fac9662..06572d5 100644
--- a/arch/arm/mach-rockchip/rk3308/Kconfig
+++ b/arch/arm/mach-rockchip/rk3308/Kconfig
@@ -17,9 +17,6 @@
config SYS_SOC
default "rk3308"
-config ROCKCHIP_COMMON_STACK_ADDR
- default y
-
config TEXT_BASE
default 0x00600000
diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c b/arch/arm/mach-rockchip/rk3308/rk3308.c
index 03d97e1..6916f1a 100644
--- a/arch/arm/mach-rockchip/rk3308/rk3308.c
+++ b/arch/arm/mach-rockchip/rk3308/rk3308.c
@@ -3,15 +3,12 @@
*Copyright (c) 2018 Rockchip Electronics Co., Ltd
*/
#include <init.h>
-#include <malloc.h>
+#include <asm/armv8/mmu.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/grf_rk3308.h>
#include <asm/arch-rockchip/hardware.h>
-#include <asm/gpio.h>
-#include <debug_uart.h>
#include <linux/bitops.h>
-#include <asm/armv8/mmu.h>
static struct mm_region rk3308_mem_map[] = {
{
.virt = 0x0UL,
@@ -38,22 +35,6 @@
#define SGRF_BASE 0xff2b0000
enum {
- GPIO1C7_SHIFT = 8,
- GPIO1C7_MASK = GENMASK(11, 8),
- GPIO1C7_GPIO = 0,
- GPIO1C7_UART1_RTSN,
- GPIO1C7_UART2_TX_M0,
- GPIO1C7_SPI2_MOSI,
- GPIO1C7_JTAG_TMS,
-
- GPIO1C6_SHIFT = 4,
- GPIO1C6_MASK = GENMASK(7, 4),
- GPIO1C6_GPIO = 0,
- GPIO1C6_UART1_CTSN,
- GPIO1C6_UART2_RX_M0,
- GPIO1C6_SPI2_MISO,
- GPIO1C6_JTAG_TCLK,
-
GPIO4D3_SHIFT = 6,
GPIO4D3_MASK = GENMASK(7, 6),
GPIO4D3_GPIO = 0,
@@ -116,60 +97,12 @@
GPIO2A2_SEL_SRC_CTRL_SEL_PLUS = 1,
};
-enum {
- IOVSEL3_CTRL_SHIFT = 8,
- IOVSEL3_CTRL_MASK = BIT(8),
- VCCIO3_SEL_BY_GPIO = 0,
- VCCIO3_SEL_BY_IOVSEL3,
-
- IOVSEL3_SHIFT = 3,
- IOVSEL3_MASK = BIT(3),
- VCCIO3_3V3 = 0,
- VCCIO3_1V8,
-};
-
-/*
- * The voltage of VCCIO3(which is the voltage domain of emmc/flash/sfc
- * interface) can indicated by GPIO0_A4 or io_vsel3. The SOC defaults
- * use GPIO0_A4 to indicate power supply voltage for VCCIO3 by hardware,
- * then we can switch to io_vsel3 after system power on, and release GPIO0_A4
- * for other usage.
- */
-
-#define GPIO0_A4 4
-
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/mmc@ff490000",
[BROM_BOOTSOURCE_SPINOR] = "/spi@ff4c0000/flash@0",
[BROM_BOOTSOURCE_SD] = "/mmc@ff480000",
};
-int rk_board_init(void)
-{
- static struct rk3308_grf * const grf = (void *)GRF_BASE;
- u32 val;
- int ret;
-
- ret = gpio_request(GPIO0_A4, "gpio0_a4");
- if (ret < 0) {
- printf("request for gpio0_a4 failed:%d\n", ret);
- return 0;
- }
-
- gpio_direction_input(GPIO0_A4);
-
- if (gpio_get_value(GPIO0_A4))
- val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT |
- VCCIO3_1V8 << IOVSEL3_SHIFT;
- else
- val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT |
- VCCIO3_3V3 << IOVSEL3_SHIFT;
- rk_clrsetreg(&grf->soc_con0, IOVSEL3_CTRL_MASK | IOVSEL3_MASK, val);
-
- gpio_free(GPIO0_A4);
- return 0;
-}
-
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
__weak void board_debug_uart_init(void)
{
diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig
index 70770da..ec1dae8 100644
--- a/arch/arm/mach-rockchip/rk3328/Kconfig
+++ b/arch/arm/mach-rockchip/rk3328/Kconfig
@@ -21,9 +21,6 @@
config SYS_SOC
default "rk3328"
-config ROCKCHIP_COMMON_STACK_ADDR
- default y
-
config TPL_LDSCRIPT
default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig
index 500cfcd..b243020 100644
--- a/arch/arm/mach-rockchip/rk3399/Kconfig
+++ b/arch/arm/mach-rockchip/rk3399/Kconfig
@@ -143,9 +143,6 @@
config SYS_SOC
default "rk3399"
-config ROCKCHIP_COMMON_STACK_ADDR
- default y
-
config TPL_LDSCRIPT
default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
diff --git a/arch/arm/mach-rockchip/rk3528/Kconfig b/arch/arm/mach-rockchip/rk3528/Kconfig
new file mode 100644
index 0000000..993b2dd
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3528/Kconfig
@@ -0,0 +1,15 @@
+if ROCKCHIP_RK3528
+
+config ROCKCHIP_BOOT_MODE_REG
+ default 0xff370200
+
+config ROCKCHIP_STIMER_BASE
+ default 0xff620000
+
+config SYS_SOC
+ default "rk3528"
+
+config SYS_CONFIG_NAME
+ default "rk3528_common"
+
+endif
diff --git a/arch/arm/mach-rockchip/rk3528/MAINTAINERS b/arch/arm/mach-rockchip/rk3528/MAINTAINERS
new file mode 100644
index 0000000..f343f71
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3528/MAINTAINERS
@@ -0,0 +1,11 @@
+GENERIC-RK3528
+M: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: arch/arm/dts/rk3528-generic*
+F: configs/generic-rk3528_defconfig
+
+RADXA-E20C
+M: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: arch/arm/dts/rk3528-radxa-e20c*
+F: configs/radxa-e20c-rk3528_defconfig
diff --git a/arch/arm/mach-rockchip/rk3528/Makefile b/arch/arm/mach-rockchip/rk3528/Makefile
new file mode 100644
index 0000000..f0c18cd
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3528/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+obj-y += rk3528.o
+obj-y += clk_rk3528.o
+obj-y += syscon_rk3528.o
diff --git a/arch/arm/mach-rockchip/rk3528/clk_rk3528.c b/arch/arm/mach-rockchip/rk3528/clk_rk3528.c
new file mode 100644
index 0000000..6e77f11
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3528/clk_rk3528.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright Contributors to the U-Boot project.
+
+#include <dm.h>
+#include <asm/arch-rockchip/cru_rk3528.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+ return uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(rockchip_rk3528_cru), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+ return RK3528_CRU_BASE;
+}
diff --git a/arch/arm/mach-rockchip/rk3528/rk3528.c b/arch/arm/mach-rockchip/rk3528/rk3528.c
new file mode 100644
index 0000000..4892ff6
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3528/rk3528.c
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright Contributors to the U-Boot project.
+
+#define LOG_CATEGORY LOGC_ARCH
+
+#include <dm.h>
+#include <misc.h>
+#include <asm/armv8/mmu.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/hardware.h>
+
+#define FIREWALL_DDR_BASE 0xff2e0000
+#define FW_DDR_MST6_REG 0x58
+#define FW_DDR_MST7_REG 0x5c
+#define FW_DDR_MST14_REG 0x78
+#define FW_DDR_MST16_REG 0x80
+
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+ [BROM_BOOTSOURCE_EMMC] = "/soc/mmc@ffbf0000",
+ [BROM_BOOTSOURCE_SD] = "/soc/mmc@ffc30000",
+};
+
+static struct mm_region rk3528_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0xfc000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xfc000000UL,
+ .phys = 0xfc000000UL,
+ .size = 0x04000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = rk3528_mem_map;
+
+void board_debug_uart_init(void)
+{
+}
+
+int arch_cpu_init(void)
+{
+ u32 val;
+
+ if (!IS_ENABLED(CONFIG_SPL_BUILD))
+ return 0;
+
+ /* Set the emmc to access ddr memory */
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
+ writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
+
+ /* Set the fspi to access ddr memory */
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
+ writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
+
+ /* Set the sdmmc to access ddr memory */
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST14_REG);
+ writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST14_REG);
+
+ /* Set the usb to access ddr memory */
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
+ writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
+
+ return 0;
+}
+
+#define HP_TIMER_BASE CONFIG_ROCKCHIP_STIMER_BASE
+#define HP_CTRL_REG 0x04
+#define TIMER_EN BIT(0)
+#define HP_LOAD_COUNT0_REG 0x14
+#define HP_LOAD_COUNT1_REG 0x18
+
+void rockchip_stimer_init(void)
+{
+ u32 reg;
+
+ if (!IS_ENABLED(CONFIG_XPL_BUILD))
+ return;
+
+ reg = readl(HP_TIMER_BASE + HP_CTRL_REG);
+ if (reg & TIMER_EN)
+ return;
+
+ asm volatile("msr cntfrq_el0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY));
+ writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT0_REG);
+ writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT1_REG);
+ writel(TIMER_EN, HP_TIMER_BASE + HP_CTRL_REG);
+}
+
+#define RK3528_OTP_CPU_CODE_OFFSET 0x02
+#define RK3528_OTP_CPU_CHIP_TYPE_OFFSET 0x28
+
+int checkboard(void)
+{
+ u8 cpu_code[2], chip_type;
+ struct udevice *dev;
+ char suffix[2];
+ int ret;
+
+ if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC))
+ return 0;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_DRIVER_GET(rockchip_otp), &dev);
+ if (ret) {
+ log_debug("Could not find otp device, ret=%d\n", ret);
+ return 0;
+ }
+
+ /* cpu-code: SoC model, e.g. 0x35 0x28 */
+ ret = misc_read(dev, RK3528_OTP_CPU_CODE_OFFSET, cpu_code, 2);
+ if (ret < 0) {
+ log_debug("Could not read cpu-code, ret=%d\n", ret);
+ return 0;
+ }
+
+ ret = misc_read(dev, RK3528_OTP_CPU_CHIP_TYPE_OFFSET, &chip_type, 1);
+ if (ret < 0) {
+ log_debug("Could not read chip type, ret=%d\n", ret);
+ return 0;
+ }
+
+ suffix[0] = chip_type != 0x1 ? 'A' : '\0';
+ suffix[1] = '\0';
+
+ printf("SoC: RK%02x%02x%s\n", cpu_code[0], cpu_code[1], suffix);
+
+ return 0;
+}
diff --git a/arch/arm/mach-rockchip/rk3528/syscon_rk3528.c b/arch/arm/mach-rockchip/rk3528/syscon_rk3528.c
new file mode 100644
index 0000000..4a32a5f
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3528/syscon_rk3528.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright Contributors to the U-Boot project.
+
+#include <dm.h>
+#include <asm/arch-rockchip/clock.h>
+
+static const struct udevice_id rk3528_syscon_ids[] = {
+ { .compatible = "rockchip,rk3528-grf", .data = ROCKCHIP_SYSCON_GRF },
+ { }
+};
+
+U_BOOT_DRIVER(rockchip_rk3528_syscon) = {
+ .name = "rockchip_rk3528_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3528_syscon_ids,
+#if CONFIG_IS_ENABLED(OF_REAL)
+ .bind = dm_scan_fdt_dev,
+#endif
+};
diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig
index ce327ed..01b53a4 100644
--- a/arch/arm/mach-rockchip/rk3568/Kconfig
+++ b/arch/arm/mach-rockchip/rk3568/Kconfig
@@ -5,7 +5,6 @@
config TARGET_EVB_RK3568
bool "RK3568 evaluation board"
- select BOARD_LATE_INIT
help
RK3568 EVB is a evaluation board for Rockchp RK3568.
@@ -71,9 +70,6 @@
config SYS_SOC
default "rk3568"
-config ROCKCHIP_COMMON_STACK_ADDR
- default y
-
config TEXT_BASE
default 0x00a00000
@@ -87,4 +83,7 @@
source "board/radxa/zero3-rk3566/Kconfig"
source "board/xunlong/orangepi-3b-rk3566/Kconfig"
+config SYS_CONFIG_NAME
+ default "rk3568_common"
+
endif
diff --git a/arch/arm/mach-rockchip/rk3576/Kconfig b/arch/arm/mach-rockchip/rk3576/Kconfig
new file mode 100644
index 0000000..f347caf
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3576/Kconfig
@@ -0,0 +1,23 @@
+if ROCKCHIP_RK3576
+
+config TARGET_ROC_PC_RK3576
+ bool "Firefly ROC-RK3576-PC"
+ help
+ ROC-RK3576-PC is a single board computer from Firefly
+ using the Rockchip RK3576.
+
+config ROCKCHIP_BOOT_MODE_REG
+ default 0x26024040
+
+config ROCKCHIP_STIMER_BASE
+ default 0x27400000
+
+config SYS_SOC
+ default "rk3576"
+
+source board/firefly/roc-pc-rk3576/Kconfig
+
+config SYS_CONFIG_NAME
+ default "rk3576_common"
+
+endif
diff --git a/arch/arm/mach-rockchip/rk3576/Makefile b/arch/arm/mach-rockchip/rk3576/Makefile
new file mode 100644
index 0000000..cbc5825
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3576/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2023 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += rk3576.o
+obj-y += clk_rk3576.o
+obj-y += syscon_rk3576.o
diff --git a/arch/arm/mach-rockchip/rk3576/clk_rk3576.c b/arch/arm/mach-rockchip/rk3576/clk_rk3576.c
new file mode 100644
index 0000000..edda1af
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3576/clk_rk3576.c
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2020 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dm.h>
+#include <asm/arch-rockchip/cru_rk3576.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+ return uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(rockchip_rk3576_cru), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+ return (void *)RK3576_CRU_BASE;
+}
diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c
new file mode 100644
index 0000000..ba5c94b
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3576/rk3576.c
@@ -0,0 +1,155 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd
+ */
+
+#include <asm/armv8/mmu.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/hardware.h>
+
+#define SYS_GRF_BASE 0x2600A000
+#define SYS_GRF_SOC_CON2 0x0008
+#define SYS_GRF_SOC_CON7 0x001c
+#define SYS_GRF_SOC_CON11 0x002c
+#define SYS_GRF_SOC_CON12 0x0030
+
+#define GPIO0_IOC_BASE 0x26040000
+#define GPIO0B_PULL_L 0x0024
+#define GPIO0B_IE_L 0x002C
+
+#define SYS_SGRF_BASE 0x26004000
+#define SYS_SGRF_SOC_CON14 0x0058
+#define SYS_SGRF_SOC_CON15 0x005C
+#define SYS_SGRF_SOC_CON20 0x0070
+
+#define FW_SYS_SGRF_BASE 0x26005000
+#define SGRF_DOMAIN_CON1 0x4
+#define SGRF_DOMAIN_CON2 0x8
+#define SGRF_DOMAIN_CON3 0xc
+#define SGRF_DOMAIN_CON4 0x10
+#define SGRF_DOMAIN_CON5 0x14
+
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+ [BROM_BOOTSOURCE_EMMC] = "/soc/mmc@2a330000",
+ [BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000",
+};
+
+static struct mm_region rk3576_mem_map[] = {
+ {
+ /* I/O area */
+ .virt = 0x20000000UL,
+ .phys = 0x20000000UL,
+ .size = 0xb080000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* PMU_SRAM, CBUF, SYSTEM_SRAM */
+ .virt = 0x3fe70000UL,
+ .phys = 0x3fe70000UL,
+ .size = 0x190000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* MSCH_DDR_PORT */
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x400000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* PCIe 0+1 */
+ .virt = 0x900000000UL,
+ .phys = 0x900000000UL,
+ .size = 0x100800000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = rk3576_mem_map;
+
+void board_debug_uart_init(void)
+{
+}
+
+#define HP_TIMER_BASE CONFIG_ROCKCHIP_STIMER_BASE
+#define HP_CTRL_REG 0x04
+#define TIMER_EN BIT(0)
+#define HP_LOAD_COUNT0_REG 0x14
+#define HP_LOAD_COUNT1_REG 0x18
+
+void rockchip_stimer_init(void)
+{
+ u32 reg;
+
+ if (!IS_ENABLED(CONFIG_XPL_BUILD))
+ return;
+
+ reg = readl(HP_TIMER_BASE + HP_CTRL_REG);
+ if (reg & TIMER_EN)
+ return;
+
+ asm volatile("msr cntfrq_el0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY));
+ writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT0_REG);
+ writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT1_REG);
+ writel((TIMER_EN << 16) | TIMER_EN, HP_TIMER_BASE + HP_CTRL_REG);
+}
+
+int arch_cpu_init(void)
+{
+ u32 val;
+
+ if (!IS_ENABLED(CONFIG_SPL_BUILD))
+ return 0;
+
+ /* Set the emmc to access ddr memory */
+ val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2);
+ writel(val | 0x7, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2);
+
+ /* Set the sdmmc0 to access ddr memory */
+ val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON5);
+ writel(val | 0x700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON5);
+
+ /* Set the UFS to access ddr memory */
+ val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON3);
+ writel(val | 0x70000, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON3);
+
+ /* Set the fspi0 and fspi1 to access ddr memory */
+ val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON4);
+ writel(val | 0x7700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON4);
+
+ /* Set the decom to access ddr memory */
+ val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON1);
+ writel(val | 0x700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON1);
+
+ /*
+ * Set the GPIO0B0~B3 pull up and input enable.
+ * Keep consistent with other IO.
+ */
+ writel(0x00ff00ff, GPIO0_IOC_BASE + GPIO0B_PULL_L);
+ writel(0x000f000f, GPIO0_IOC_BASE + GPIO0B_IE_L);
+
+ /*
+ * Set SYS_GRF_SOC_CON2[12](input of pwm2_ch0) as 0,
+ * keep consistent with other pwm.
+ */
+ writel(0x10000000, SYS_GRF_BASE + SYS_GRF_SOC_CON2);
+
+ /* Enable noc slave response timeout */
+ writel(0x80008000, SYS_GRF_BASE + SYS_GRF_SOC_CON11);
+ writel(0xffffffe0, SYS_GRF_BASE + SYS_GRF_SOC_CON12);
+
+ /*
+ * Enable cci channels for below module AXI R/W
+ * Module: GMAC0/1, MMU0/1(PCIe, SATA, USB3)
+ */
+ writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20);
+
+ return 0;
+}
diff --git a/arch/arm/mach-rockchip/rk3576/syscon_rk3576.c b/arch/arm/mach-rockchip/rk3576/syscon_rk3576.c
new file mode 100644
index 0000000..0dbf8f8
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3576/syscon_rk3576.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2023 Rockchip Electronics Co., Ltd
+ */
+
+#include <dm.h>
+#include <asm/arch-rockchip/clock.h>
+
+static const struct udevice_id rk3576_syscon_ids[] = {
+ { .compatible = "rockchip,rk3576-sys-grf", .data = ROCKCHIP_SYSCON_GRF },
+ { .compatible = "rockchip,rk3576-pmu1-grf", .data = ROCKCHIP_SYSCON_PMUGRF },
+ { }
+};
+
+U_BOOT_DRIVER(rockchip_rk3576_syscon) = {
+ .name = "rockchip_rk3576_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3576_syscon_ids,
+#if CONFIG_IS_ENABLED(OF_REAL)
+ .bind = dm_scan_fdt_dev,
+#endif
+};
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig
index 155b8f0..4e7942a 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -2,13 +2,11 @@
config TARGET_EVB_RK3588
bool "Rockchip EVB1 v10"
- select BOARD_LATE_INIT
help
RK3588 EVB is a evaluation board for Rockchp RK3588.
config TARGET_CM3588_NAS_RK3588
bool "FriendlyElec CM3588 NAS"
- select BOARD_LATE_INIT
help
The CM3588 NAS by FriendlyElec pairs the CM3588 compute module, based
on the Rockchip RK3588 SoC, with the CM3588 NAS Kit carrier board.
@@ -31,7 +29,6 @@
config TARGET_GENBOOK_CM5_RK3588
bool "Cool Pi CM5 GenBook"
- select BOARD_LATE_INIT
help
GeenBook is a notebook based on Rockchip RK3588, and works as a carrier
board connect with CM5 SOM.
@@ -49,7 +46,6 @@
config TARGET_JAGUAR_RK3588
bool "Theobroma Systems SBC-RK3588-AMR (Jaguar)"
- select BOARD_LATE_INIT
help
The SBC-RK3588-AMR is a Single Board Computer designed by
Theobroma Systems for autonomous mobile robots.
@@ -76,7 +72,6 @@
config TARGET_KHADAS_EDGE2_RK3588
bool "Khadas Edge2 RK3588 board"
- select BOARD_LATE_INIT
help
Khadas Edge2 is a Rockchip RK3588S based SBC (Single Board Computer)
by Khadas.
@@ -98,7 +93,6 @@
config TARGET_NANOPCT6_RK3588
bool "FriendlyElec NanoPC-T6 RK3588 board"
- select BOARD_LATE_INIT
help
The NanoPC-T6 is a Rockchip RK3588 based SBC by FriendlyElec.
@@ -143,7 +137,6 @@
config TARGET_NANOPI_R6C_RK3588S
bool "FriendlyElec NanoPi R6C"
- select BOARD_LATE_INIT
help
The NanoPi R6C is a SBC by FriendlyElec based on the Rockchip
RK3588s.
@@ -155,7 +148,6 @@
config TARGET_NANOPI_R6S_RK3588S
bool "FriendlyElec NanoPi R6S"
- select BOARD_LATE_INIT
help
The NanoPi R6S is a SBC by FriendlyElec based on the Rockchip
RK3588s.
@@ -167,7 +159,6 @@
config TARGET_NOVA_RK3588
bool "Indiedroid Nova RK3588"
- select BOARD_LATE_INIT
help
Indiedroid Nova is a Rockchip RK3588s based SBC by Indiedroid.
It comes in configurations from 4GB of RAM to 16GB of RAM,
@@ -176,13 +167,11 @@
config TARGET_ODROID_M2_RK3588S
bool "Hardkernel ODROID-M2"
- select BOARD_LATE_INIT
help
Hardkernel ODROID-M2 single board computer with a RK3588S2 SoC.
config TARGET_RK3588_NEU6
bool "Edgeble Neural Compute Module 6(Neu6) SoM"
- select BOARD_LATE_INIT
help
Neu6A:
Neural Compute Module 6A(Neu6A) is a 96boards SoM-CB compute module
@@ -204,7 +193,6 @@
config TARGET_ROCK5A_RK3588
bool "Radxa ROCK5A RK3588 board"
- select BOARD_LATE_INIT
help
Radxa ROCK5A is a Rockchip RK3588S based SBC (Single Board Computer)
by Radxa.
@@ -231,7 +219,6 @@
config TARGET_ROCK5B_RK3588
bool "Radxa ROCK5B RK3588 board"
- select BOARD_LATE_INIT
help
Radxa ROCK5B is a Rockchip RK3588 based SBC (Single Board Computer)
by Radxa.
@@ -256,7 +243,6 @@
config TARGET_ROCK_5_ITX_RK3588
bool "Radxa ROCK-5-ITX RK3588 board"
- select BOARD_LATE_INIT
help
Radxa ROCK-5-ITX is a Rockchip RK3588 based SBC (Single Board
Computer) by Radxa in the ITX formfactor.
@@ -284,7 +270,6 @@
config TARGET_ROCK_5C_RK3588S
bool "Radxa ROCK 5C RK3588S2 board"
- select BOARD_LATE_INIT
help
Radxa ROCK 5C is a Rockchip RK3588S2 based single board computer.
@@ -304,7 +289,6 @@
config TARGET_SIGE7_RK3588
bool "ArmSoM Sige7 RK3588 board"
- select BOARD_LATE_INIT
help
ArmSoM Sige7 is a Rockchip RK3588 based SBC (Single Board Computer)
by ArmSoM.
@@ -329,14 +313,12 @@
config TARGET_QUARTZPRO64_RK3588
bool "Pine64 QuartzPro64 RK3588 board"
- select BOARD_LATE_INIT
help
Pine64 QuartzPro64 is a Rockchip RK3588 based SBC (Single Board
Computer) by Pine64.
config TARGET_TIGER_RK3588
bool "Theobroma Systems SOM-RK3588-Q7 (Tiger)"
- select BOARD_LATE_INIT
help
The RK3588-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230
connector) system-on-module from Theobroma Systems, featuring the
@@ -366,7 +348,6 @@
config TARGET_TURINGRK1_RK3588
bool "Turing Machines RK1 RK3588 board"
- select BOARD_LATE_INIT
help
The Turing RK1 is a Rockchip RK3588 based SoM from Turing Machines.
@@ -389,7 +370,6 @@
config TARGET_TOYBRICK_RK3588
bool "Toybrick TB-RK3588X board"
- select BOARD_LATE_INIT
help
Rockchip Toybrick TB-RK3588X is a Rockchip RK3588 based development board.
TB-RK3588X adopts core board and mainboard design. The core board is connected
@@ -420,9 +400,6 @@
config SYS_SOC
default "rk3588"
-config ROCKCHIP_COMMON_STACK_ADDR
- default y
-
config TEXT_BASE
default 0x00a00000
@@ -447,4 +424,7 @@
source "board/theobroma-systems/jaguar_rk3588/Kconfig"
source "board/theobroma-systems/tiger_rk3588/Kconfig"
+config SYS_CONFIG_NAME
+ default "rk3588_common"
+
endif
diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c
index c1dce3e..e2278ff 100644
--- a/arch/arm/mach-rockchip/rk3588/rk3588.c
+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -116,18 +116,25 @@
}
#ifdef CONFIG_XPL_BUILD
+
+#define HP_TIMER_BASE CONFIG_ROCKCHIP_STIMER_BASE
+#define HP_CTRL_REG 0x04
+#define TIMER_EN BIT(0)
+#define HP_LOAD_COUNT0_REG 0x14
+#define HP_LOAD_COUNT1_REG 0x18
+
void rockchip_stimer_init(void)
{
/* If Timer already enabled, don't re-init it */
- u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
+ u32 reg = readl(HP_TIMER_BASE + HP_CTRL_REG);
- if (reg & 0x1)
+ if (reg & TIMER_EN)
return;
- asm volatile("msr CNTFRQ_EL0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY));
- writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);
- writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);
- writel(0x1, CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
+ asm volatile("msr cntfrq_el0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY));
+ writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT0_REG);
+ writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT1_REG);
+ writel(TIMER_EN, HP_TIMER_BASE + HP_CTRL_REG);
}
#endif
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index f7d3282..3bc4823 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -110,7 +110,9 @@
u8 i, j;
if (!IS_ENABLED(CONFIG_ROCKCHIP_RK3588) &&
- !IS_ENABLED(CONFIG_ROCKCHIP_RK3568))
+ !IS_ENABLED(CONFIG_ROCKCHIP_RK3576) &&
+ !IS_ENABLED(CONFIG_ROCKCHIP_RK3568) &&
+ !IS_ENABLED(CONFIG_ROCKCHIP_RK3528))
return -ENOTSUPP;
if (!IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL))
@@ -181,9 +183,9 @@
* BL31 (TF-A) reserves the first 2MB but DDR_MEM tag may not
* have it, so force this space as reserved.
*/
- if (start_addr < SZ_2M) {
- size -= SZ_2M - start_addr;
- start_addr = SZ_2M;
+ if (start_addr < CFG_SYS_SDRAM_BASE + SZ_2M) {
+ size -= CFG_SYS_SDRAM_BASE + SZ_2M - start_addr;
+ start_addr = CFG_SYS_SDRAM_BASE + SZ_2M;
}
/*
@@ -228,7 +230,7 @@
return -EINVAL;
}
- size -= rsrv_end - start_addr;
+ size -= rsrv_end - (start_addr - CFG_SYS_SDRAM_BASE);
start_addr = rsrv_end;
break;
}
@@ -301,8 +303,8 @@
debug("Couldn't use ATAG (%d) to detect DDR layout, falling back...\n",
ret);
- /* Reserve 0x200000 for ATF bl31 */
- gd->bd->bi_dram[0].start = 0x200000;
+ /* Reserve 2M for ATF bl31 */
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE + SZ_2M;
gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
/* Add usable memory beyond the blob of space for peripheral near 4GB */
diff --git a/arch/arm/mach-snapdragon/include/mach/gpio.h b/arch/arm/mach-snapdragon/include/mach/gpio.h
index cc8f405..11e8104 100644
--- a/arch/arm/mach-snapdragon/include/mach/gpio.h
+++ b/arch/arm/mach-snapdragon/include/mach/gpio.h
@@ -46,4 +46,19 @@
return pindata->special_pins_start && pin >= pindata->special_pins_start;
}
+struct udevice;
+
+/**
+ * msm_pinctrl_is_reserved() - Check if a pin lies in a reserved range
+ *
+ * @dev: pinctrl device
+ * @pin: Pin number
+ *
+ * Returns: true if pin is reserved, otherwise false
+ *
+ * Call using dev_get_parent() from the GPIO device, it is a child of
+ * the pinctrl device.
+ */
+bool msm_pinctrl_is_reserved(struct udevice *dev, unsigned int pin);
+
#endif /* _QCOM_GPIO_H_ */
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 22d48df..c43fdee 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -68,6 +68,8 @@
obj-y += ccu_ncore3.o
obj-y += system_manager_soc64.o
obj-y += timer_s10.o
+obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
+obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o
endif
ifdef CONFIG_TARGET_SOCFPGA_N5X
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 27072e5..8506d51 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -195,3 +195,16 @@
}
}
#endif
+
+#if CONFIG_IS_ENABLED(LMB_ARCH_MEM_MAP)
+void lmb_arch_add_memory(void)
+{
+ int i;
+ struct bd_info *bd = gd->bd;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ if (bd->bi_dram[i].size)
+ lmb_add(bd->bi_dram[i].start, bd->bi_dram[i].size);
+ }
+}
+#endif
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
index 6572109..5ac868a 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
@@ -51,6 +51,7 @@
#else
#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100
#endif
+#define SOCFPGA_F2SDRAM_MGR_ADDRESS 0xf8024000
#define SOCFPGA_SMMU_ADDRESS 0xfa000000
#define SOCFPGA_MAILBOX_ADDRESS 0xffa30000
#define SOCFPGA_UART0_ADDRESS 0xffc02000
diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
index 45cc991..2099c51 100644
--- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
@@ -128,6 +128,7 @@
#define MBOX_QSPI_CLOSE 51
#define MBOX_QSPI_DIRECT 59
#define MBOX_REBOOT_HPS 71
+#define MBOX_HPS_STAGE_NOTIFY 93
/* Mailbox registers */
#define MBOX_CIN 0 /* command valid offset */
@@ -385,6 +386,8 @@
#define RCF_SOFTFUNC_STATUS_SEU_ERROR BIT(3)
#define RCF_PIN_STATUS_NSTATUS BIT(31)
+#define HPS_EXECUTION_STATE_FSBL 0
+
int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent,
u32 *resp_buf_len, u32 *resp_buf);
int mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
@@ -401,6 +404,7 @@
#endif
int mbox_reset_cold(void);
+int mbox_hps_stage_notify(u32 execution_stage);
int mbox_get_fpga_config_status(u32 cmd);
int mbox_get_fpga_config_status_psci(u32 cmd);
#endif /* _MAILBOX_S10_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
index 058fdd6..4b010be 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
@@ -10,9 +10,12 @@
void reset_deassert_peripherals_handoff(void);
int cpu_has_been_warmreset(void);
void print_reset_info(void);
-void socfpga_bridges_reset(int enable);
+void socfpga_bridges_reset(int enable, unsigned int mask);
#define RSTMGR_SOC64_STATUS 0x00
+#define RSTMGR_SOC64_HDSKEN 0x10
+#define RSTMGR_SOC64_HDSKREQ 0x14
+#define RSTMGR_SOC64_HDSKACK 0x18
#define RSTMGR_SOC64_MPUMODRST 0x20
#define RSTMGR_SOC64_PER0MODRST 0x24
#define RSTMGR_SOC64_PER1MODRST 0x28
@@ -20,8 +23,17 @@
#define RSTMGR_MPUMODRST_CORE0 0
#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00
-#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040
-#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004
+
+#define RSTMGR_BRGMODRST_SOC2FPGA_MASK BIT(0)
+#define RSTMGR_BRGMODRST_LWSOC2FPGA_MASK BIT(1)
+#define RSTMGR_BRGMODRST_FPGA2SOC_MASK BIT(2)
+#define RSTMGR_BRGMODRST_F2SDRAM0_MASK BIT(3)
+#define RSTMGR_BRGMODRST_F2SDRAM1_MASK BIT(4)
+#define RSTMGR_BRGMODRST_F2SDRAM2_MASK BIT(5)
+#define RSTMGR_BRGMODRST_DDRSCH_MASK BIT(6)
+
+#define RSTMGR_HDSKEN_FPGAHSEN BIT(2)
+#define RSTMGR_HDSKREQ_FPGAHSREQ BIT(2)
/* SDM, Watchdogs and MPU warm reset mask */
#define RSTMGR_STAT_SDMWARMRST 0x2
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c
index b69bd3e..f9c34e8 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -6,6 +6,7 @@
#include <asm/arch/clock_manager.h>
#include <asm/arch/mailbox_s10.h>
+#include <asm/arch/smc_api.h>
#include <asm/arch/system_manager.h>
#include <asm/global_data.h>
#include <asm/io.h>
@@ -474,6 +475,17 @@
urgent, resp_buf_len, resp_buf);
}
+int mbox_hps_stage_notify(u32 execution_stage)
+{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ return smc_send_mailbox(MBOX_HPS_STAGE_NOTIFY, 1, &execution_stage,
+ 0, 0, NULL);
+#else
+ return mbox_send_cmd(MBOX_ID_UBOOT, MBOX_HPS_STAGE_NOTIFY,
+ MBOX_CMD_DIRECT, 1, &execution_stage, 0, 0, NULL);
+#endif
+}
+
int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg)
{
return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg);
diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c
index e0b2b42..4f080f4 100644
--- a/arch/arm/mach-socfpga/misc_soc64.c
+++ b/arch/arm/mach-socfpga/misc_soc64.c
@@ -61,7 +61,7 @@
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
- printf("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-%s)\n",
+ printf("CPU: Altera FPGA SoCFPGA Platform (ARMv8 64bit Cortex-%s)\n",
IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) ? "A55/A76" : "A53");
return 0;
@@ -107,5 +107,5 @@
return;
}
- socfpga_bridges_reset(enable);
+ socfpga_bridges_reset(enable, mask);
}
diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c
index b8e40d9a..1dc44ab 100644
--- a/arch/arm/mach-socfpga/mmu-arm64_s10.c
+++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c
@@ -58,6 +58,20 @@
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE,
}, {
+ /* MEM 30GB */
+ .virt = 0x880000000UL,
+ .phys = 0x880000000UL,
+ .size = 0x780000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE,
+ }, {
+ /* MEM 480GB */
+ .virt = 0x8800000000UL,
+ .phys = 0x8800000000UL,
+ .size = 0x7800000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE,
+ }, {
/* List terminator */
},
};
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
index a634c11..abb62a9 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -1,21 +1,34 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*
*/
+#include <errno.h>
#include <hang.h>
#include <asm/global_data.h>
#include <asm/io.h>
+#include <asm/secure.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/smc_api.h>
#include <asm/arch/system_manager.h>
+#include <asm/arch/timer.h>
#include <dt-bindings/reset/altr,rst-mgr-s10.h>
+#include <exports.h>
#include <linux/iopoll.h>
#include <linux/intel-smc.h>
+#include <wait_bit.h>
DECLARE_GLOBAL_DATA_PTR;
+#define TIMEOUT_300MS 300
+
+/* F2S manager registers */
+#define F2SDRAM_SIDEBAND_FLAGINSTATUS0 0x14
+#define F2SDRAM_SIDEBAND_FLAGOUTSET0 0x50
+#define F2SDRAM_SIDEBAND_FLAGOUTCLR0 0x54
+
/* Assert or de-assert SoCFPGA reset manager reset. */
void socfpga_per_reset(u32 reset, int set)
{
@@ -56,66 +69,213 @@
writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER1MODRST);
}
-void socfpga_bridges_reset(int enable)
+static void socfpga_f2s_bridges_reset(int enable, unsigned int mask)
{
-#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF)
- u64 arg = enable;
+ int ret;
+ u32 brg_mask;
+ u32 flagout_idlereq = 0;
+ u32 flagoutset_fdrain = 0;
+ u32 flagoutset_en = 0;
+ u32 flaginstatus_idleack = 0;
+ u32 flaginstatus_respempty = 0;
+
+ if (CONFIG_IS_ENABLED(TARGET_SOCFPGA_STRATIX10)) {
+ /* Support fpga2soc and f2sdram */
+ brg_mask = mask & (RSTMGR_BRGMODRST_FPGA2SOC_MASK |
+ RSTMGR_BRGMODRST_F2SDRAM0_MASK |
+ RSTMGR_BRGMODRST_F2SDRAM1_MASK |
+ RSTMGR_BRGMODRST_F2SDRAM2_MASK);
- int ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0);
- if (ret) {
- printf("SMC call failed with error %d in %s.\n", ret, __func__);
+ if (brg_mask & RSTMGR_BRGMODRST_F2SDRAM0_MASK) {
+ flagout_idlereq |= BIT(0);
+ flaginstatus_idleack |= BIT(1);
+ flagoutset_fdrain |= BIT(2);
+ flagoutset_en |= BIT(1);
+ flaginstatus_respempty |= BIT(3);
+ }
+
+ if (brg_mask & RSTMGR_BRGMODRST_F2SDRAM1_MASK) {
+ flagout_idlereq |= BIT(3);
+ flaginstatus_idleack |= BIT(5);
+ flagoutset_fdrain |= BIT(5);
+ flagoutset_en |= BIT(4);
+ flaginstatus_respempty |= BIT(7);
+ }
+
+ if (brg_mask & RSTMGR_BRGMODRST_F2SDRAM2_MASK) {
+ flagout_idlereq |= BIT(6);
+ flaginstatus_idleack |= BIT(9);
+ flagoutset_fdrain |= BIT(8);
+ flagoutset_en |= BIT(7);
+ flaginstatus_respempty |= BIT(11);
+ }
+ } else {
+ /* Support fpga2soc only */
+ brg_mask = mask & RSTMGR_BRGMODRST_FPGA2SOC_MASK;
+ if (brg_mask & RSTMGR_BRGMODRST_FPGA2SOC_MASK) {
+ flagout_idlereq |= BIT(0);
+ flaginstatus_idleack |= BIT(1);
+ flagoutset_fdrain |= BIT(2);
+ flagoutset_en |= BIT(1);
+ flaginstatus_respempty |= BIT(3);
+ }
+ }
+
+ /* mask is not set, return here */
+ if (!brg_mask)
return;
+
+ if (enable) {
+ clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
+ brg_mask);
+ setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS +
+ F2SDRAM_SIDEBAND_FLAGOUTCLR0,
+ flagout_idlereq);
+
+ /* Wait for mpfe noc idleack to 0 */
+ wait_for_bit_le32((u32 *)(SOCFPGA_F2SDRAM_MGR_ADDRESS +
+ F2SDRAM_SIDEBAND_FLAGINSTATUS0),
+ flaginstatus_idleack, false, TIMEOUT_300MS, false);
+
+ setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS +
+ F2SDRAM_SIDEBAND_FLAGOUTCLR0,
+ flagoutset_fdrain);
+ setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS +
+ F2SDRAM_SIDEBAND_FLAGOUTSET0, flagoutset_en);
+
+ udelay(1); /* wait 1us */
+ } else {
+ if (readl((socfpga_get_rstmgr_addr() +
+ RSTMGR_SOC64_BRGMODRST) & brg_mask)) {
+ /* Bridge cannot be reset twice */
+ return;
+ }
+
+ setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_HDSKEN,
+ RSTMGR_HDSKEN_FPGAHSEN);
+ setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_HDSKREQ,
+ RSTMGR_HDSKREQ_FPGAHSREQ);
+
+ /* Wait for FPGA ack the handshake request to 1 */
+ wait_for_bit_le32((u32 *)(socfpga_get_rstmgr_addr() +
+ RSTMGR_SOC64_HDSKACK), RSTMGR_HDSKREQ_FPGAHSREQ,
+ true, TIMEOUT_300MS, false);
+
+ setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS +
+ F2SDRAM_SIDEBAND_FLAGOUTCLR0, flagoutset_en);
+
+ udelay(1);
+
+ /* Requests MPFE NoC to idle */
+ setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS +
+ F2SDRAM_SIDEBAND_FLAGOUTSET0, flagout_idlereq);
+
+ /* Force F2S bridge to drain */
+ setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS +
+ F2SDRAM_SIDEBAND_FLAGOUTSET0, flagoutset_fdrain);
+
+ /* Wait for respond queue empty status to 1 (resp idle) */
+ ret = wait_for_bit_le32((u32 *)(SOCFPGA_F2SDRAM_MGR_ADDRESS +
+ F2SDRAM_SIDEBAND_FLAGINSTATUS0),
+ flaginstatus_respempty, true,
+ TIMEOUT_300MS, false);
+
+ /* Confirm again */
+ if (!ret)
+ ret = wait_for_bit_le32((u32 *)
+ (SOCFPGA_F2SDRAM_MGR_ADDRESS +
+ F2SDRAM_SIDEBAND_FLAGINSTATUS0),
+ flaginstatus_respempty, true,
+ TIMEOUT_300MS, false);
+
+ setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
+ brg_mask & ~RSTMGR_BRGMODRST_FPGA2SOC_MASK);
+ clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_HDSKREQ,
+ RSTMGR_HDSKREQ_FPGAHSREQ);
+ setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS +
+ F2SDRAM_SIDEBAND_FLAGOUTCLR0,
+ flagout_idlereq);
+ }
+}
+
+static void socfpga_s2f_bridges_reset(int enable, unsigned int mask)
+{
+ unsigned int noc_mask = 0;
+ unsigned int brg_mask = 0;
+
+ if (mask & RSTMGR_BRGMODRST_SOC2FPGA_MASK) {
+ noc_mask = SYSMGR_NOC_H2F_MSK;
+ brg_mask = RSTMGR_BRGMODRST_SOC2FPGA_MASK;
+ }
+
+ if (mask & RSTMGR_BRGMODRST_LWSOC2FPGA_MASK) {
+ noc_mask |= SYSMGR_NOC_LWH2F_MSK;
+ brg_mask |= RSTMGR_BRGMODRST_LWSOC2FPGA_MASK;
}
-#else
- u32 reg;
+
+ /* s2f mask is not set, return here */
+ if (!brg_mask)
+ return;
if (enable) {
/* clear idle request to all bridges */
setbits_le32(socfpga_get_sysmgr_addr() +
- SYSMGR_SOC64_NOC_IDLEREQ_CLR, ~0);
+ SYSMGR_SOC64_NOC_IDLEREQ_CLR, noc_mask);
- /* Release all bridges from reset state */
+ /* Release SOC2FPGA bridges from reset state */
clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
- ~0);
+ brg_mask);
- /* Poll until all idleack to 0 */
- read_poll_timeout(readl, reg, !reg, 1000, 300000,
- socfpga_get_sysmgr_addr() +
- SYSMGR_SOC64_NOC_IDLEACK);
+ /* Wait for all NOC master ack to 0 */
+ wait_for_bit_le32((u32 *)(socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_NOC_IDLEACK), noc_mask, false,
+ TIMEOUT_300MS, false);
} else {
/* set idle request to all bridges */
- writel(~0,
- socfpga_get_sysmgr_addr() +
- SYSMGR_SOC64_NOC_IDLEREQ_SET);
+ setbits_le32(socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_NOC_IDLEREQ_SET, noc_mask);
/* Enable the NOC timeout */
writel(1, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
- /* Poll until all idleack to 1 */
- read_poll_timeout(readl, reg,
- reg == (SYSMGR_NOC_H2F_MSK |
- SYSMGR_NOC_LWH2F_MSK),
- 1000, 300000,
- socfpga_get_sysmgr_addr() +
- SYSMGR_SOC64_NOC_IDLEACK);
+ /* Wait for all NOC master ack to 1 */
+ wait_for_bit_le32((u32 *)(socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_NOC_IDLEACK), noc_mask, true,
+ TIMEOUT_300MS, false);
- /* Poll until all idlestatus to 1 */
- read_poll_timeout(readl, reg,
- reg == (SYSMGR_NOC_H2F_MSK |
- SYSMGR_NOC_LWH2F_MSK),
- 1000, 300000,
- socfpga_get_sysmgr_addr() +
- SYSMGR_SOC64_NOC_IDLESTATUS);
+ /* Wait for all NOC master idlestatus to 1 */
+ wait_for_bit_le32((u32 *)(socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_NOC_IDLESTATUS), noc_mask, true,
+ TIMEOUT_300MS, false);
- /* Reset all bridges (except NOR DDR scheduler & F2S) */
+ /* Reset all SOC2FPGA bridges */
setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
- ~(RSTMGR_BRGMODRST_DDRSCH_MASK |
- RSTMGR_BRGMODRST_FPGA2SOC_MASK));
+ brg_mask);
/* Disable NOC timeout */
writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
}
+}
+
+void socfpga_bridges_reset(int enable, unsigned int mask)
+{
+ if (!IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)) {
+ u64 arg[2];
+ int ret;
+
+ /* Set bit-1 to indicate has mask value in arg[1]. */
+ arg[0] = (enable & BIT(0)) | BIT(1);
+ arg[1] = mask;
+
+ ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, arg,
+ ARRAY_SIZE(arg), NULL, 0);
+ if (ret)
+ printf("Failed to %s the HPS bridges, check bridges availability. Status %d.\n",
+ enable ? "enable" : "disable", ret);
+ } else {
+ socfpga_s2f_bridges_reset(enable, mask);
+ socfpga_f2s_bridges_reset(enable, mask);
+ }
-#endif
}
/*
diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c
index 52617a3..91c27a5 100644
--- a/arch/arm/mach-socfpga/spl_agilex.c
+++ b/arch/arm/mach-socfpga/spl_agilex.c
@@ -50,6 +50,10 @@
timer_init();
+ mbox_init();
+
+ mbox_hps_stage_notify(HPS_EXECUTION_STATE_FSBL);
+
sysmgr_pinmux_init();
ret = uclass_get_device(UCLASS_CLK, 0, &dev);
@@ -77,8 +81,6 @@
}
#endif
- mbox_init();
-
#ifdef CONFIG_CADENCE_QSPI
mbox_qspi_open();
#endif
diff --git a/arch/arm/mach-socfpga/spl_agilex5.c b/arch/arm/mach-socfpga/spl_agilex5.c
index 3451611..a9aad53 100644
--- a/arch/arm/mach-socfpga/spl_agilex5.c
+++ b/arch/arm/mach-socfpga/spl_agilex5.c
@@ -62,6 +62,10 @@
timer_init();
+ mbox_init();
+
+ mbox_hps_stage_notify(HPS_EXECUTION_STATE_FSBL);
+
ret = uclass_get_device(UCLASS_CLK, 0, &dev);
if (ret) {
debug("Clock init failed: %d\n", ret);
@@ -100,8 +104,6 @@
}
}
- mbox_init();
-
if (IS_ENABLED(CONFIG_CADENCE_QSPI))
mbox_qspi_open();
diff --git a/arch/arm/mach-socfpga/spl_n5x.c b/arch/arm/mach-socfpga/spl_n5x.c
index 5ff137e..81283ef 100644
--- a/arch/arm/mach-socfpga/spl_n5x.c
+++ b/arch/arm/mach-socfpga/spl_n5x.c
@@ -49,6 +49,10 @@
timer_init();
+ mbox_init();
+
+ mbox_hps_stage_notify(HPS_EXECUTION_STATE_FSBL);
+
sysmgr_pinmux_init();
preloader_console_init();
@@ -84,8 +88,6 @@
}
#endif
- mbox_init();
-
#ifdef CONFIG_CADENCE_QSPI
mbox_qspi_open();
#endif
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index 53852cb..fa83ff9 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -52,6 +52,10 @@
socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
timer_init();
+ mbox_init();
+
+ mbox_hps_stage_notify(HPS_EXECUTION_STATE_FSBL);
+
sysmgr_pinmux_init();
/* configuring the HPS clocks */
@@ -84,8 +88,6 @@
}
#endif
- mbox_init();
-
#ifdef CONFIG_CADENCE_QSPI
mbox_qspi_open();
#endif
diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig
index a44ebf2..de9d854 100644
--- a/arch/arm/mach-stm32/Kconfig
+++ b/arch/arm/mach-stm32/Kconfig
@@ -15,6 +15,7 @@
select STM32_SERIAL
select STM32_TIMER
select TIMER
+ imply OF_UPSTREAM
config STM32F7
bool "stm32f7 family"
@@ -32,6 +33,7 @@
select STM32_TIMER
select SUPPORT_SPL
select TIMER
+ imply OF_UPSTREAM
imply SPL_OS_BOOT
config STM32H7
@@ -51,6 +53,7 @@
select STM32_TIMER
select SYSCON
select TIMER
+ imply OF_UPSTREAM
source "arch/arm/mach-stm32/stm32f4/Kconfig"
source "arch/arm/mach-stm32/stm32f7/Kconfig"
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index 002da2e..5825090 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -52,6 +52,7 @@
select STM32_SERIAL
select SYS_ARCH_TIMER
imply CMD_NVEDIT_INFO
+ imply OF_UPSTREAM
help
support of STMicroelectronics SOC STM32MP13x family
STMicroelectronics MPU with core ARMv7
@@ -73,6 +74,7 @@
select SUPPORT_SPL
select SYS_ARCH_TIMER
imply CMD_NVEDIT_INFO
+ imply OF_UPSTREAM
help
support of STMicroelectronics SOC STM32MP15x family
STM32MP157, STM32MP153 or STM32MP151
@@ -94,6 +96,7 @@
imply CMD_NVEDIT_INFO
imply DM_REGULATOR
imply DM_REGULATOR_SCMI
+ imply OF_UPSTREAM
imply OPTEE
imply RESET_SCMI
imply SYSRESET_PSCI
@@ -127,14 +130,6 @@
Partition on the second MMC to load U-Boot from when the MMC is being
used in raw mode
-config STM32_ETZPC
- bool "STM32 Extended TrustZone Protection"
- depends on STM32MP15X || STM32MP13X
- default y
- imply BOOTP_SERVERIP
- help
- Say y to enable STM32 Extended TrustZone Protection
-
config STM32_ECDSA_VERIFY
bool "STM32 ECDSA verification via the ROM API"
depends on SPL_ECDSA_VERIFY
diff --git a/arch/arm/mach-stm32mp/cmd_stm32key.c b/arch/arm/mach-stm32mp/cmd_stm32key.c
index 040a70f..6bfa678 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32key.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32key.c
@@ -14,12 +14,23 @@
/*
* Closed device: OTP0
- * STM32MP15x: bit 6 of OPT0
+ * STM32MP15x: bit 6 of OTP0
* STM32MP13x: 0b111111 = 0x3F for OTP_SECURED closed device
+ * STM32MP25x: bit 0 of OTP18
*/
-#define STM32_OTP_CLOSE_ID 0
-#define STM32_OTP_STM32MP13X_CLOSE_MASK 0x3F
-#define STM32_OTP_STM32MP15X_CLOSE_MASK BIT(6)
+#define STM32MP1_OTP_CLOSE_ID 0
+#define STM32_OTP_STM32MP13X_CLOSE_MASK GENMASK(5, 0)
+#define STM32_OTP_STM32MP15X_CLOSE_MASK BIT(6)
+#define STM32MP25_OTP_WORD8 8
+#define STM32_OTP_STM32MP25X_BOOTROM_CLOSE_MASK GENMASK(7, 0)
+#define STM32MP25_OTP_CLOSE_ID 18
+#define STM32_OTP_STM32MP25X_CLOSE_MASK GENMASK(3, 0)
+#define STM32_OTP_STM32MP25X_PROVISIONING_DONE_MASK GENMASK(7, 4)
+#define STM32MP25_OTP_HWCONFIG 124
+#define STM32_OTP_STM32MP25X_DISABLE_SCAN_MASK BIT(20)
+
+#define STM32MP25_OTP_BOOTROM_CONF8 17
+#define STM32_OTP_STM32MP25X_OEM_KEY2_EN BIT(8)
/* PKH is the first element of the key list */
#define STM32KEY_PKH 0
@@ -27,8 +38,9 @@
struct stm32key {
char *name;
char *desc;
- u8 start;
+ u16 start;
u8 size;
+ int (*post_process)(struct udevice *dev);
};
const struct stm32key stm32mp13_list[] = {
@@ -52,9 +64,102 @@
.desc = "Hash of the ECC Public Key (ECDSA is the authentication algorithm)",
.start = 24,
.size = 8,
+ }
+};
+
+static int post_process_oem_key2(struct udevice *dev);
+
+const struct stm32key stm32mp25_list[] = {
+ [STM32KEY_PKH] = {
+ .name = "OEM-KEY1",
+ .desc = "Hash of the 8 ECC Public Keys Hashes Table (ECDSA is the authentication algorithm) for FSBLA or M",
+ .start = 144,
+ .size = 8,
+ },
+ {
+ .name = "OEM-KEY2",
+ .desc = "Hash of the 8 ECC Public Keys Hashes Table (ECDSA is the authentication algorithm) for FSBLM",
+ .start = 152,
+ .size = 8,
+ .post_process = post_process_oem_key2,
+ },
+ {
+ .name = "FIP-EDMK",
+ .desc = "Encryption/Decryption Master Key for FIP",
+ .start = 260,
+ .size = 8,
+ },
+ {
+ .name = "EDMK1",
+ .desc = "Encryption/Decryption Master Key for FSBLA or M",
+ .start = 364,
+ .size = 4,
+ },
+ {
+ .name = "EDMK2",
+ .desc = "Encryption/Decryption Master Key for FSBLM",
+ .start = 360,
+ .size = 4,
+ }
+};
+
+struct otp_close {
+ u32 word;
+ u32 mask_wr;
+ u32 mask_rd;
+ bool (*close_status_ops)(u32 value, u32 mask);
+};
+
+static bool compare_mask_exact(u32 value, u32 mask)
+{
+ return ((value & mask) == mask);
+}
+
+static bool compare_any_bits(u32 value, u32 mask)
+{
+ return ((value & mask) != 0);
+}
+
+const struct otp_close stm32mp13_close_state_otp[] = {
+ {
+ .word = STM32MP1_OTP_CLOSE_ID,
+ .mask_wr = STM32_OTP_STM32MP13X_CLOSE_MASK,
+ .mask_rd = STM32_OTP_STM32MP13X_CLOSE_MASK,
+ .close_status_ops = compare_mask_exact,
+ }
+};
+
+const struct otp_close stm32mp15_close_state_otp[] = {
+ {
+ .word = STM32MP1_OTP_CLOSE_ID,
+ .mask_wr = STM32_OTP_STM32MP15X_CLOSE_MASK,
+ .mask_rd = STM32_OTP_STM32MP15X_CLOSE_MASK,
+ .close_status_ops = compare_mask_exact,
}
};
+const struct otp_close stm32mp25_close_state_otp[] = {
+ {
+ .word = STM32MP25_OTP_WORD8,
+ .mask_wr = STM32_OTP_STM32MP25X_BOOTROM_CLOSE_MASK,
+ .mask_rd = 0,
+ .close_status_ops = NULL
+ },
+ {
+ .word = STM32MP25_OTP_CLOSE_ID,
+ .mask_wr = STM32_OTP_STM32MP25X_CLOSE_MASK |
+ STM32_OTP_STM32MP25X_PROVISIONING_DONE_MASK,
+ .mask_rd = STM32_OTP_STM32MP25X_CLOSE_MASK,
+ .close_status_ops = compare_any_bits
+ },
+ {
+ .word = STM32MP25_OTP_HWCONFIG,
+ .mask_wr = STM32_OTP_STM32MP25X_DISABLE_SCAN_MASK,
+ .mask_rd = 0,
+ .close_status_ops = NULL
+ },
+};
+
/* index of current selected key in stm32key list, 0 = PKH by default */
static u8 stm32key_index;
@@ -65,6 +170,9 @@
if (IS_ENABLED(CONFIG_STM32MP15X))
return ARRAY_SIZE(stm32mp15_list);
+
+ if (IS_ENABLED(CONFIG_STM32MP25X))
+ return ARRAY_SIZE(stm32mp25_list);
}
static const struct stm32key *get_key(u8 index)
@@ -74,17 +182,35 @@
if (IS_ENABLED(CONFIG_STM32MP15X))
return &stm32mp15_list[index];
+
+ if (IS_ENABLED(CONFIG_STM32MP25X))
+ return &stm32mp25_list[index];
}
-static u32 get_otp_close_mask(void)
+static u8 get_otp_close_state_nb(void)
{
if (IS_ENABLED(CONFIG_STM32MP13X))
- return STM32_OTP_STM32MP13X_CLOSE_MASK;
+ return ARRAY_SIZE(stm32mp13_close_state_otp);
if (IS_ENABLED(CONFIG_STM32MP15X))
- return STM32_OTP_STM32MP15X_CLOSE_MASK;
+ return ARRAY_SIZE(stm32mp15_close_state_otp);
+
+ if (IS_ENABLED(CONFIG_STM32MP25X))
+ return ARRAY_SIZE(stm32mp25_close_state_otp);
}
+static const struct otp_close *get_otp_close_state(u8 index)
+{
+ if (IS_ENABLED(CONFIG_STM32MP13X))
+ return &stm32mp13_close_state_otp[index];
+
+ if (IS_ENABLED(CONFIG_STM32MP15X))
+ return &stm32mp15_close_state_otp[index];
+
+ if (IS_ENABLED(CONFIG_STM32MP25X))
+ return &stm32mp25_close_state_otp[index];
+}
+
static int get_misc_dev(struct udevice **dev)
{
int ret;
@@ -96,13 +222,13 @@
return ret;
}
-static void read_key_value(const struct stm32key *key, u32 addr)
+static void read_key_value(const struct stm32key *key, unsigned long addr)
{
int i;
for (i = 0; i < key->size; i++) {
printf("%s OTP %i: [%08x] %08x\n", key->name, key->start + i,
- addr, __be32_to_cpu(*(u32 *)addr));
+ (u32)addr, __be32_to_cpu(*(u32 *)addr));
addr += 4;
}
}
@@ -157,26 +283,42 @@
static int read_close_status(struct udevice *dev, bool print, bool *closed)
{
- int word, ret, result;
- u32 val, lock, mask;
- bool status;
+ int ret, result, i;
+ const struct otp_close *otp_close = NULL;
+ u32 otp_close_nb = get_otp_close_state_nb();
+ u32 val, lock, mask, word = 0;
+ bool status = true;
+ bool tested_once = false;
result = 0;
- word = STM32_OTP_CLOSE_ID;
- ret = misc_read(dev, STM32_BSEC_OTP(word), &val, 4);
- if (ret < 0)
- result = ret;
- if (ret != 4)
- val = 0x0;
+ for (i = 0; status && (i < otp_close_nb); i++) {
+ otp_close = get_otp_close_state(i);
- ret = misc_read(dev, STM32_BSEC_LOCK(word), &lock, 4);
- if (ret < 0)
- result = ret;
- if (ret != 4)
- lock = BSEC_LOCK_ERROR;
+ if (!otp_close->close_status_ops)
+ continue;
- mask = get_otp_close_mask();
- status = (val & mask) == mask;
+ mask = otp_close->mask_rd;
+ word = otp_close->word;
+
+ ret = misc_read(dev, STM32_BSEC_OTP(word), &val, 4);
+ if (ret < 0)
+ result = ret;
+ if (ret != 4)
+ val = 0x0;
+
+ ret = misc_read(dev, STM32_BSEC_LOCK(word), &lock, 4);
+ if (ret < 0)
+ result = ret;
+ if (ret != 4)
+ lock = BSEC_LOCK_ERROR;
+
+ status = otp_close->close_status_ops(val, mask);
+ tested_once = true;
+ }
+
+ if (!tested_once)
+ status = false;
+
if (closed)
*closed = status;
if (print)
@@ -185,7 +327,49 @@
return result;
}
+static int write_close_status(struct udevice *dev)
+{
+ int i;
+ u32 val, word, ret;
+ const struct otp_close *otp_close = NULL;
+ u32 otp_num = get_otp_close_state_nb();
+
+ for (i = 0; i < otp_num; i++) {
+ otp_close = get_otp_close_state(i);
+ val = otp_close->mask_wr;
+ word = otp_close->word;
+ ret = misc_write(dev, STM32_BSEC_OTP(word), &val, 4);
+ if (ret != 4) {
+ log_err("Error: can't update OTP %d\n", word);
+ return ret;
+ }
+ }
+ return 0;
+}
+
+static int post_process_oem_key2(struct udevice *dev)
+{
+ int ret;
+ u32 val;
+
+ ret = misc_read(dev, STM32_BSEC_OTP(STM32MP25_OTP_BOOTROM_CONF8), &val, 4);
+ if (ret != 4) {
+ log_err("Error %d failed to read STM32MP25_OTP_BOOTROM_CONF8\n", ret);
+ return -EIO;
+ }
+
+ val |= STM32_OTP_STM32MP25X_OEM_KEY2_EN;
+ ret = misc_write(dev, STM32_BSEC_OTP(STM32MP25_OTP_BOOTROM_CONF8), &val, 4);
+ if (ret != 4) {
+ log_err("Error %d failed to write OEM_KEY2_ENABLE\n", ret);
+ return -EIO;
+ }
+
+ return 0;
+}
+
-static int fuse_key_value(struct udevice *dev, const struct stm32key *key, u32 addr, bool print)
+static int fuse_key_value(struct udevice *dev, const struct stm32key *key, unsigned long addr,
+ bool print)
{
u32 word, val;
int i, ret;
@@ -229,7 +413,7 @@
static void display_key_info(const struct stm32key *key)
{
printf("%s : %s\n", key->name, key->desc);
- printf("\tOTP%d..%d\n", key->start, key->start + key->size);
+ printf("\tOTP%d..%d\n", key->start, key->start + key->size - 1);
}
static int do_stm32key_list(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
@@ -272,7 +456,7 @@
{
const struct stm32key *key;
struct udevice *dev;
- u32 addr;
+ unsigned long addr;
int ret, i;
int result;
@@ -310,7 +494,7 @@
return CMD_RET_USAGE;
key = get_key(stm32key_index);
- printf("Read %s at 0x%08x\n", key->name, addr);
+ printf("Read %s at 0x%08x\n", key->name, (u32)addr);
read_key_value(key, addr);
return CMD_RET_SUCCESS;
@@ -320,7 +504,7 @@
{
const struct stm32key *key = get_key(stm32key_index);
struct udevice *dev;
- u32 addr;
+ unsigned long addr;
int ret;
bool yes = false, lock;
@@ -361,6 +545,13 @@
if (fuse_key_value(dev, key, addr, !yes))
return CMD_RET_FAILURE;
+ if (key->post_process) {
+ if (key->post_process(dev)) {
+ printf("Error: %s for post process\n", key->name);
+ return CMD_RET_FAILURE;
+ }
+ }
+
printf("%s updated !\n", key->name);
return CMD_RET_SUCCESS;
@@ -371,7 +562,6 @@
const struct stm32key *key;
bool yes, lock, closed;
struct udevice *dev;
- u32 val;
int ret;
yes = false;
@@ -407,12 +597,8 @@
if (!yes && !confirm_prog())
return CMD_RET_FAILURE;
- val = get_otp_close_mask();
- ret = misc_write(dev, STM32_BSEC_OTP(STM32_OTP_CLOSE_ID), &val, 4);
- if (ret != 4) {
- printf("Error: can't update OTP %d\n", STM32_OTP_CLOSE_ID);
+ if (write_close_status(dev))
return CMD_RET_FAILURE;
- }
printf("Device is closed !\n");
@@ -432,3 +618,25 @@
U_BOOT_SUBCMD_MKENT(read, 2, 0, do_stm32key_read),
U_BOOT_SUBCMD_MKENT(fuse, 3, 0, do_stm32key_fuse),
U_BOOT_SUBCMD_MKENT(close, 2, 0, do_stm32key_close));
+
+/*
+ * Check the "closed" state in product life cycle, when product secrets have
+ * been provisioned into the device, by SSP tools for example.
+ * On closed devices, authentication is mandatory.
+ */
+bool stm32mp_is_closed(void)
+{
+ struct udevice *dev;
+ bool closed;
+ int ret;
+
+ ret = get_misc_dev(&dev);
+ if (ret)
+ return false;
+
+ ret = read_close_status(dev, false, &closed);
+ if (ret)
+ return false;
+
+ return closed;
+}
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig
index 5892762..490097e 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig
@@ -27,6 +27,8 @@
config CMD_STM32PROG_SERIAL
bool "support stm32prog over UART"
depends on CMD_STM32PROG
+ imply DISABLE_CONSOLE
+ imply SILENT_CONSOLE
default y
help
activate the command "stm32prog serial" for STM32MP soc family
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
index 353aecc..5b027fa 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
@@ -13,6 +13,7 @@
#include <part.h>
#include <tee.h>
#include <asm/arch/stm32mp1_smc.h>
+#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <dm/uclass.h>
@@ -1156,7 +1157,8 @@
/* partition UUID */
uuid_bin = NULL;
- if (!rootfs_found && !strcmp(part->name, "rootfs")) {
+ if (!rootfs_found && (!strcmp(part->name, "rootfs") ||
+ !strcmp(part->name, "rootfs-a"))) {
mmc_id = part->dev_id;
rootfs_found = true;
if (mmc_id < ARRAY_SIZE(uuid_mmc))
@@ -1357,7 +1359,7 @@
alt_nb = 1; /* number of virtual = CMD*/
- if (IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) {
+ if (IS_ENABLED(CONFIG_CMD_STM32PROG_OTP) && !stm32mp_is_closed()) {
/* OTP_SIZE_SMC = 0 if SMC is not supported */
otp_size = OTP_SIZE_SMC;
/* check if PTA BSEC is supported */
diff --git a/arch/arm/mach-stm32mp/include/mach/etzpc.h b/arch/arm/mach-stm32mp/include/mach/etzpc.h
new file mode 100644
index 0000000..fd697c3
--- /dev/null
+++ b/arch/arm/mach-stm32mp/include/mach/etzpc.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#ifndef MACH_ETZPC_H
+#define MACH_ETZPC_H
+
+#include <linux/types.h>
+
+/**
+ * stm32_etzpc_check_access - Check ETZPC accesses for given device node
+ *
+ * @device_node Node of the device for which the accesses are checked
+ *
+ * @returns 0 on success (if access is granted), -EINVAL if access is denied.
+ * Else, returns an appropriate negative ERRNO value
+ */
+int stm32_etzpc_check_access(ofnode device_node);
+
+/**
+ * stm32_etzpc_check_access_by_id - Check ETZPC accesses for given id
+ *
+ * @device_node Node of the device to get a reference on ETZPC
+ * @id ID of the resource to check
+ *
+ * @returns 0 on success (if access is granted), -EINVAL if access is denied.
+ * Else, returns an appropriate negative ERRNO value
+ */
+int stm32_etzpc_check_access_by_id(ofnode device_node, u32 id);
+
+#endif /* MACH_ETZPC_H*/
diff --git a/arch/arm/mach-stm32mp/include/mach/rif.h b/arch/arm/mach-stm32mp/include/mach/rif.h
new file mode 100644
index 0000000..10b2210
--- /dev/null
+++ b/arch/arm/mach-stm32mp/include/mach/rif.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#ifndef MACH_RIF_H
+#define MACH_RIF_H
+
+#include <linux/types.h>
+
+/**
+ * stm32_rifsc_check_access - Check RIF accesses for given device node
+ *
+ * @device_node Node of the device for which the accesses are checked
+ */
+int stm32_rifsc_check_access(ofnode device_node);
+
+/**
+ * stm32_rifsc_check_access - Check RIF accesses for given id
+ *
+ * @device_node Node of the device to get a reference on RIFSC
+ * @id ID of the resource to check
+ */
+int stm32_rifsc_check_access_by_id(ofnode device_node, u32 id);
+
+#endif /* MACH_RIF_H*/
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h
index 6eb85ba..a9ac49b 100644
--- a/arch/arm/mach-stm32mp/include/mach/stm32.h
+++ b/arch/arm/mach-stm32mp/include/mach/stm32.h
@@ -42,6 +42,9 @@
BOOT_FLASH_SPINAND = 0x70,
BOOT_FLASH_SPINAND_1 = 0x71,
+
+ BOOT_FLASH_HYPERFLASH = 0x80,
+ BOOT_FLASH_HYPERFLASH_1 = 0x81
};
#define TAMP_BOOT_MODE_MASK GENMASK(15, 8)
@@ -158,8 +161,20 @@
#endif /* CONFIG_STM32MP15X || CONFIG_STM32MP13X */
#ifdef CONFIG_STM32MP25X
+#define STM32_USART2_BASE 0x400E0000
+#define STM32_USART3_BASE 0x400F0000
+#define STM32_UART4_BASE 0x40100000
+#define STM32_UART5_BASE 0x40110000
+#define STM32_USART6_BASE 0x40220000
+#define STM32_UART9_BASE 0x402C0000
+#define STM32_USART1_BASE 0x40330000
+#define STM32_UART7_BASE 0x40370000
+#define STM32_UART8_BASE 0x40380000
#define STM32_RCC_BASE 0x44200000
#define STM32_TAMP_BASE 0x46010000
+#define STM32_SDMMC1_BASE 0x48220000
+#define STM32_SDMMC2_BASE 0x48230000
+#define STM32_SDMMC3_BASE 0x48240000
#define STM32_DDR_BASE 0x80000000
@@ -197,6 +212,7 @@
#ifdef CONFIG_STM32MP25X
#define BSEC_OTP_SERIAL 5
#define BSEC_OTP_RPN 9
+#define BSEC_OTP_REVID 102
#define BSEC_OTP_PKG 122
#define BSEC_OTP_BOARD 246
#define BSEC_OTP_MAC 247
diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h
index 2a65efc..1907366 100644
--- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h
+++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h
@@ -58,6 +58,7 @@
/* return CPU_DEV constants */
u32 get_cpu_dev(void);
+/* Silicon revision = REV_ID[15:0] of Device Version */
#define CPU_REV1 0x1000
#define CPU_REV1_1 0x1001
#define CPU_REV1_2 0x1003
@@ -65,7 +66,15 @@
#define CPU_REV2_1 0x2001
#define CPU_REV2_2 0x2003
-/* return Silicon revision = REV_ID[15:0] of Device Version */
+/* OTP revision ID = 6 bits : 3 for Major / 3 for Minor */
+#define OTP_REVID_1 0b001000
+#define OTP_REVID_1_1 0b001001
+#define OTP_REVID_1_2 0b001010
+#define OTP_REVID_2 0b010000
+#define OTP_REVID_2_1 0b010001
+#define OTP_REVID_2_2 0b010010
+
+/* return SoC revision = Silicon revision (STM32MP1) or OTP revision ID (STM32MP2)*/
u32 get_cpu_rev(void);
/* Get Package options from OTP */
@@ -80,9 +89,9 @@
/* package used for STM32MP25x */
#define STM32MP25_PKG_CUSTOM 0
-#define STM32MP25_PKG_AL_TBGA361 3
-#define STM32MP25_PKG_AK_TBGA424 4
-#define STM32MP25_PKG_AI_TBGA436 5
+#define STM32MP25_PKG_AL_VFBGA361 1
+#define STM32MP25_PKG_AK_VFBGA424 3
+#define STM32MP25_PKG_AI_TFBGA436 5
#define STM32MP25_PKG_UNKNOWN 7
/* Get SOC name */
@@ -111,3 +120,10 @@
uintptr_t get_stm32mp_rom_api_table(void);
uintptr_t get_stm32mp_bl2_dtb(void);
+
+/* helper function: check "closed" state in product "Life Cycle" */
+#ifdef CONFIG_CMD_STM32KEY
+bool stm32mp_is_closed(void);
+#else
+static inline bool stm32mp_is_closed(void) { return false; }
+#endif
diff --git a/arch/arm/mach-stm32mp/stm32mp1/Makefile b/arch/arm/mach-stm32mp/stm32mp1/Makefile
index db160c2..1f4ada3 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/Makefile
+++ b/arch/arm/mach-stm32mp/stm32mp1/Makefile
@@ -4,6 +4,7 @@
#
obj-y += cpu.o
+obj-y += etzpc.o
obj-$(CONFIG_STM32MP13X) += stm32mp13x.o
obj-$(CONFIG_STM32MP15X) += stm32mp15x.o
@@ -15,5 +16,5 @@
obj-$(CONFIG_ARMV7_PSCI) += psci.o
endif
-obj-$(CONFIG_$(XPL_)STM32MP15_PWR) += pwr_regulator.o
+obj-$(CONFIG_$(PHASE_)STM32MP15_PWR) += pwr_regulator.o
obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o
diff --git a/arch/arm/mach-stm32mp/stm32mp1/etzpc.c b/arch/arm/mach-stm32mp/stm32mp1/etzpc.c
new file mode 100644
index 0000000..7013bf9
--- /dev/null
+++ b/arch/arm/mach-stm32mp/stm32mp1/etzpc.c
@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#define LOG_CATEGORY UCLASS_NOP
+
+#include <dm.h>
+#include <asm/io.h>
+#include <dm/device.h>
+#include <dm/device_compat.h>
+#include <dm/lists.h>
+#include <linux/bitfield.h>
+#include <mach/etzpc.h>
+
+/* ETZPC peripheral as firewall bus */
+/* ETZPC registers */
+#define ETZPC_DECPROT 0x10
+#define ETZPC_HWCFGR 0x3F0
+
+/* ETZPC miscellaneous */
+#define ETZPC_PROT_MASK GENMASK(1, 0)
+#define ETZPC_PROT_A7NS 0x3
+#define ETZPC_DECPROT_SHIFT 1
+
+#define IDS_PER_DECPROT_REGS 16
+
+#define ETZPC_HWCFGR_NUM_PER_SEC GENMASK(15, 8)
+#define ETZPC_HWCFGR_NUM_AHB_SEC GENMASK(23, 16)
+
+/*
+ * struct stm32_etzpc_plat: Information about ETZPC device
+ *
+ * @base: Base address of ETZPC
+ * @max_entries: Number of securable peripherals in ETZPC
+ */
+struct stm32_etzpc_plat {
+ void *base;
+ unsigned int max_entries;
+};
+
+static int etzpc_parse_feature_domain(ofnode node, struct ofnode_phandle_args *args)
+{
+ int ret;
+
+ ret = ofnode_parse_phandle_with_args(node, "access-controllers",
+ "#access-controller-cells", 0,
+ 0, args);
+ if (ret) {
+ log_debug("failed to parse access-controller (%d)\n", ret);
+ return ret;
+ }
+
+ if (args->args_count != 1) {
+ log_debug("invalid domain args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int etzpc_check_access(void *base, u32 id)
+{
+ u32 reg_offset, offset, sec_val;
+
+ /* Check access configuration, 16 peripherals per register */
+ reg_offset = ETZPC_DECPROT + 0x4 * (id / IDS_PER_DECPROT_REGS);
+ offset = (id % IDS_PER_DECPROT_REGS) << ETZPC_DECPROT_SHIFT;
+
+ /* Verify peripheral is non-secure and attributed to cortex A7 */
+ sec_val = (readl(base + reg_offset) >> offset) & ETZPC_PROT_MASK;
+ if (sec_val != ETZPC_PROT_A7NS) {
+ log_debug("Invalid bus configuration: reg_offset %#x, value %d\n",
+ reg_offset, sec_val);
+ return -EACCES;
+ }
+
+ return 0;
+}
+
+int stm32_etzpc_check_access_by_id(ofnode device_node, u32 id)
+{
+ struct stm32_etzpc_plat *plat;
+ struct ofnode_phandle_args args;
+ struct udevice *dev;
+ int err;
+
+ err = etzpc_parse_feature_domain(device_node, &args);
+ if (err)
+ return err;
+
+ if (id == -1U)
+ id = args.args[0];
+
+ err = uclass_get_device_by_ofnode(UCLASS_NOP, args.node, &dev);
+ if (err || dev->driver != DM_DRIVER_GET(stm32_etzpc)) {
+ log_err("No device found\n");
+ return -EINVAL;
+ }
+
+ plat = dev_get_plat(dev);
+
+ if (id >= plat->max_entries) {
+ dev_err(dev, "Invalid sys bus ID for %s\n", ofnode_get_name(device_node));
+ return -EINVAL;
+ }
+
+ return etzpc_check_access(plat->base, id);
+}
+
+int stm32_etzpc_check_access(ofnode device_node)
+{
+ return stm32_etzpc_check_access_by_id(device_node, -1U);
+}
+
+static int stm32_etzpc_bind(struct udevice *dev)
+{
+ struct stm32_etzpc_plat *plat = dev_get_plat(dev);
+ struct ofnode_phandle_args args;
+ u32 nb_per, nb_master;
+ int ret = 0, err = 0;
+ ofnode node, parent;
+
+ plat->base = dev_read_addr_ptr(dev);
+ if (!plat->base) {
+ dev_err(dev, "can't get registers base address\n");
+ return -ENOENT;
+ }
+
+ /* Get number of etzpc entries*/
+ nb_per = FIELD_GET(ETZPC_HWCFGR_NUM_PER_SEC,
+ readl(plat->base + ETZPC_HWCFGR));
+ nb_master = FIELD_GET(ETZPC_HWCFGR_NUM_AHB_SEC,
+ readl(plat->base + ETZPC_HWCFGR));
+ plat->max_entries = nb_per + nb_master;
+
+ parent = dev_ofnode(dev);
+ for (node = ofnode_first_subnode(parent);
+ ofnode_valid(node);
+ node = ofnode_next_subnode(node)) {
+ const char *node_name = ofnode_get_name(node);
+
+ if (!ofnode_is_enabled(node))
+ continue;
+
+ err = etzpc_parse_feature_domain(node, &args);
+ if (err) {
+ dev_err(dev, "%s failed to parse child on bus (%d)\n", node_name, err);
+ continue;
+ }
+
+ if (!ofnode_equal(args.node, parent)) {
+ dev_err(dev, "%s phandle to %s\n",
+ node_name, ofnode_get_name(args.node));
+ continue;
+ }
+
+ if (args.args[0] >= plat->max_entries) {
+ dev_err(dev, "Invalid sys bus ID for %s\n", node_name);
+ return -EINVAL;
+ }
+
+ err = etzpc_check_access(plat->base, args.args[0]);
+ if (err) {
+ dev_info(dev, "%s not allowed on bus (%d)\n", node_name, err);
+ continue;
+ }
+
+ err = lists_bind_fdt(dev, node, NULL, NULL,
+ gd->flags & GD_FLG_RELOC ? false : true);
+ if (err) {
+ ret = err;
+ dev_err(dev, "%s failed to bind on bus (%d)\n", node_name, ret);
+ }
+ }
+
+ if (ret)
+ dev_err(dev, "Some child failed to bind (%d)\n", ret);
+
+ return ret;
+}
+
+static const struct udevice_id stm32_etzpc_ids[] = {
+ { .compatible = "st,stm32-etzpc" },
+ {},
+};
+
+U_BOOT_DRIVER(stm32_etzpc) = {
+ .name = "stm32_etzpc",
+ .id = UCLASS_NOP,
+ .of_match = stm32_etzpc_ids,
+ .bind = stm32_etzpc_bind,
+ .plat_auto = sizeof(struct stm32_etzpc_plat),
+};
diff --git a/arch/arm/mach-stm32mp/stm32mp1/fdt.c b/arch/arm/mach-stm32mp/stm32mp1/fdt.c
index e1e4dc0..72474fa 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/fdt.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/fdt.c
@@ -14,20 +14,6 @@
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
#include <linux/io.h>
-#define ETZPC_DECPROT(n) (STM32_ETZPC_BASE + 0x10 + 4 * (n))
-#define ETZPC_DECPROT_NB 6
-
-#define DECPROT_MASK 0x03
-#define NB_PROT_PER_REG 0x10
-#define DECPROT_NB_BITS 2
-
-#define DECPROT_SECURED 0x00
-#define DECPROT_WRITE_SECURE 0x01
-#define DECPROT_MCU_ISOLATION 0x02
-#define DECPROT_NON_SECURED 0x03
-
-#define ETZPC_RESERVED 0xffffffff
-
#define STM32MP13_FDCAN_BASE 0x4400F000
#define STM32MP13_ADC1_BASE 0x48003000
#define STM32MP13_TSC_BASE 0x5000B000
@@ -42,204 +28,6 @@
#define STM32MP15_GPU_BASE 0x59000000
#define STM32MP15_DSI_BASE 0x5a000000
-static const u32 stm32mp13_ip_addr[] = {
- 0x50025000, /* 0 VREFBUF APB3 */
- 0x50021000, /* 1 LPTIM2 APB3 */
- 0x50022000, /* 2 LPTIM3 APB3 */
- STM32MP13_LTDC_BASE, /* 3 LTDC APB4 */
- STM32MP13_DCMIPP_BASE, /* 4 DCMIPP APB4 */
- 0x5A006000, /* 5 USBPHYCTRL APB4 */
- 0x5A003000, /* 6 DDRCTRLPHY APB4 */
- ETZPC_RESERVED, /* 7 Reserved*/
- ETZPC_RESERVED, /* 8 Reserved*/
- ETZPC_RESERVED, /* 9 Reserved*/
- 0x5C006000, /* 10 TZC APB5 */
- 0x58001000, /* 11 MCE APB5 */
- 0x5C000000, /* 12 IWDG1 APB5 */
- 0x5C008000, /* 13 STGENC APB5 */
- ETZPC_RESERVED, /* 14 Reserved*/
- ETZPC_RESERVED, /* 15 Reserved*/
- 0x4C000000, /* 16 USART1 APB6 */
- 0x4C001000, /* 17 USART2 APB6 */
- 0x4C002000, /* 18 SPI4 APB6 */
- 0x4C003000, /* 19 SPI5 APB6 */
- 0x4C004000, /* 20 I2C3 APB6 */
- 0x4C005000, /* 21 I2C4 APB6 */
- 0x4C006000, /* 22 I2C5 APB6 */
- 0x4C007000, /* 23 TIM12 APB6 */
- 0x4C008000, /* 24 TIM13 APB6 */
- 0x4C009000, /* 25 TIM14 APB6 */
- 0x4C00A000, /* 26 TIM15 APB6 */
- 0x4C00B000, /* 27 TIM16 APB6 */
- 0x4C00C000, /* 28 TIM17 APB6 */
- ETZPC_RESERVED, /* 29 Reserved*/
- ETZPC_RESERVED, /* 30 Reserved*/
- ETZPC_RESERVED, /* 31 Reserved*/
- STM32MP13_ADC1_BASE, /* 32 ADC1 AHB2 */
- 0x48004000, /* 33 ADC2 AHB2 */
- 0x49000000, /* 34 OTG AHB2 */
- ETZPC_RESERVED, /* 35 Reserved*/
- ETZPC_RESERVED, /* 36 Reserved*/
- STM32MP13_TSC_BASE, /* 37 TSC AHB4 */
- ETZPC_RESERVED, /* 38 Reserved*/
- ETZPC_RESERVED, /* 39 Reserved*/
- 0x54004000, /* 40 RNG AHB5 */
- 0x54003000, /* 41 HASH AHB5 */
- STM32MP13_CRYP_BASE, /* 42 CRYPT AHB5 */
- 0x54005000, /* 43 SAES AHB5 */
- 0x54006000, /* 44 PKA AHB5 */
- 0x54000000, /* 45 BKPSRAM AHB5 */
- ETZPC_RESERVED, /* 46 Reserved*/
- ETZPC_RESERVED, /* 47 Reserved*/
- 0x5800A000, /* 48 ETH1 AHB6 */
- STM32MP13_ETH2_BASE, /* 49 ETH2 AHB6 */
- 0x58005000, /* 50 SDMMC1 AHB6 */
- 0x58007000, /* 51 SDMMC2 AHB6 */
- ETZPC_RESERVED, /* 52 Reserved*/
- ETZPC_RESERVED, /* 53 Reserved*/
- 0x58002000, /* 54 FMC AHB6 */
- 0x58003000, /* 55 QSPI AHB6 */
- ETZPC_RESERVED, /* 56 Reserved*/
- ETZPC_RESERVED, /* 57 Reserved*/
- ETZPC_RESERVED, /* 58 Reserved*/
- ETZPC_RESERVED, /* 59 Reserved*/
- 0x30000000, /* 60 SRAM1 MLAHB */
- 0x30004000, /* 61 SRAM2 MLAHB */
- 0x30006000, /* 62 SRAM3 MLAHB */
- ETZPC_RESERVED, /* 63 Reserved*/
- ETZPC_RESERVED, /* 64 Reserved*/
- ETZPC_RESERVED, /* 65 Reserved*/
- ETZPC_RESERVED, /* 66 Reserved*/
- ETZPC_RESERVED, /* 67 Reserved*/
- ETZPC_RESERVED, /* 68 Reserved*/
- ETZPC_RESERVED, /* 69 Reserved*/
- ETZPC_RESERVED, /* 70 Reserved*/
- ETZPC_RESERVED, /* 71 Reserved*/
- ETZPC_RESERVED, /* 72 Reserved*/
- ETZPC_RESERVED, /* 73 Reserved*/
- ETZPC_RESERVED, /* 74 Reserved*/
- ETZPC_RESERVED, /* 75 Reserved*/
- ETZPC_RESERVED, /* 76 Reserved*/
- ETZPC_RESERVED, /* 77 Reserved*/
- ETZPC_RESERVED, /* 78 Reserved*/
- ETZPC_RESERVED, /* 79 Reserved*/
- ETZPC_RESERVED, /* 80 Reserved*/
- ETZPC_RESERVED, /* 81 Reserved*/
- ETZPC_RESERVED, /* 82 Reserved*/
- ETZPC_RESERVED, /* 83 Reserved*/
- ETZPC_RESERVED, /* 84 Reserved*/
- ETZPC_RESERVED, /* 85 Reserved*/
- ETZPC_RESERVED, /* 86 Reserved*/
- ETZPC_RESERVED, /* 87 Reserved*/
- ETZPC_RESERVED, /* 88 Reserved*/
- ETZPC_RESERVED, /* 89 Reserved*/
- ETZPC_RESERVED, /* 90 Reserved*/
- ETZPC_RESERVED, /* 91 Reserved*/
- ETZPC_RESERVED, /* 92 Reserved*/
- ETZPC_RESERVED, /* 93 Reserved*/
- ETZPC_RESERVED, /* 94 Reserved*/
- ETZPC_RESERVED, /* 95 Reserved*/
-};
-
-static const u32 stm32mp15_ip_addr[] = {
- 0x5c008000, /* 00 stgenc */
- 0x54000000, /* 01 bkpsram */
- 0x5c003000, /* 02 iwdg1 */
- 0x5c000000, /* 03 usart1 */
- 0x5c001000, /* 04 spi6 */
- 0x5c002000, /* 05 i2c4 */
- ETZPC_RESERVED, /* 06 reserved */
- 0x54003000, /* 07 rng1 */
- 0x54002000, /* 08 hash1 */
- STM32MP15_CRYP1_BASE, /* 09 cryp1 */
- 0x5a003000, /* 0A ddrctrl */
- 0x5a004000, /* 0B ddrphyc */
- 0x5c009000, /* 0C i2c6 */
- ETZPC_RESERVED, /* 0D reserved */
- ETZPC_RESERVED, /* 0E reserved */
- ETZPC_RESERVED, /* 0F reserved */
- 0x40000000, /* 10 tim2 */
- 0x40001000, /* 11 tim3 */
- 0x40002000, /* 12 tim4 */
- 0x40003000, /* 13 tim5 */
- 0x40004000, /* 14 tim6 */
- 0x40005000, /* 15 tim7 */
- 0x40006000, /* 16 tim12 */
- 0x40007000, /* 17 tim13 */
- 0x40008000, /* 18 tim14 */
- 0x40009000, /* 19 lptim1 */
- 0x4000a000, /* 1A wwdg1 */
- 0x4000b000, /* 1B spi2 */
- 0x4000c000, /* 1C spi3 */
- 0x4000d000, /* 1D spdifrx */
- 0x4000e000, /* 1E usart2 */
- 0x4000f000, /* 1F usart3 */
- 0x40010000, /* 20 uart4 */
- 0x40011000, /* 21 uart5 */
- 0x40012000, /* 22 i2c1 */
- 0x40013000, /* 23 i2c2 */
- 0x40014000, /* 24 i2c3 */
- 0x40015000, /* 25 i2c5 */
- 0x40016000, /* 26 cec */
- 0x40017000, /* 27 dac */
- 0x40018000, /* 28 uart7 */
- 0x40019000, /* 29 uart8 */
- ETZPC_RESERVED, /* 2A reserved */
- ETZPC_RESERVED, /* 2B reserved */
- 0x4001c000, /* 2C mdios */
- ETZPC_RESERVED, /* 2D reserved */
- ETZPC_RESERVED, /* 2E reserved */
- ETZPC_RESERVED, /* 2F reserved */
- 0x44000000, /* 30 tim1 */
- 0x44001000, /* 31 tim8 */
- ETZPC_RESERVED, /* 32 reserved */
- 0x44003000, /* 33 usart6 */
- 0x44004000, /* 34 spi1 */
- 0x44005000, /* 35 spi4 */
- 0x44006000, /* 36 tim15 */
- 0x44007000, /* 37 tim16 */
- 0x44008000, /* 38 tim17 */
- 0x44009000, /* 39 spi5 */
- 0x4400a000, /* 3A sai1 */
- 0x4400b000, /* 3B sai2 */
- 0x4400c000, /* 3C sai3 */
- 0x4400d000, /* 3D dfsdm */
- STM32MP15_FDCAN_BASE, /* 3E tt_fdcan */
- ETZPC_RESERVED, /* 3F reserved */
- 0x50021000, /* 40 lptim2 */
- 0x50022000, /* 41 lptim3 */
- 0x50023000, /* 42 lptim4 */
- 0x50024000, /* 43 lptim5 */
- 0x50027000, /* 44 sai4 */
- 0x50025000, /* 45 vrefbuf */
- 0x4c006000, /* 46 dcmi */
- 0x4c004000, /* 47 crc2 */
- 0x48003000, /* 48 adc */
- 0x4c002000, /* 49 hash2 */
- 0x4c003000, /* 4A rng2 */
- STM32MP15_CRYP2_BASE, /* 4B cryp2 */
- ETZPC_RESERVED, /* 4C reserved */
- ETZPC_RESERVED, /* 4D reserved */
- ETZPC_RESERVED, /* 4E reserved */
- ETZPC_RESERVED, /* 4F reserved */
- ETZPC_RESERVED, /* 50 sram1 */
- ETZPC_RESERVED, /* 51 sram2 */
- ETZPC_RESERVED, /* 52 sram3 */
- ETZPC_RESERVED, /* 53 sram4 */
- ETZPC_RESERVED, /* 54 retram */
- 0x49000000, /* 55 otg */
- 0x48004000, /* 56 sdmmc3 */
- 0x48005000, /* 57 dlybsd3 */
- 0x48000000, /* 58 dma1 */
- 0x48001000, /* 59 dma2 */
- 0x48002000, /* 5A dmamux */
- 0x58002000, /* 5B fmc */
- 0x58003000, /* 5C qspi */
- 0x58004000, /* 5D dlybq */
- 0x5800a000, /* 5E eth */
- ETZPC_RESERVED, /* 5F reserved */
-};
-
/* fdt helper */
static bool fdt_disable_subnode_by_address(void *fdt, int offset, u32 addr)
{
@@ -263,46 +51,6 @@
return false;
}
-static int stm32_fdt_fixup_etzpc(void *fdt, int soc_node)
-{
- const u32 *array;
- int array_size, i;
- int offset, shift;
- u32 addr, status, decprot[ETZPC_DECPROT_NB];
-
- if (IS_ENABLED(CONFIG_STM32MP13X)) {
- array = stm32mp13_ip_addr;
- array_size = ARRAY_SIZE(stm32mp13_ip_addr);
- }
-
- if (IS_ENABLED(CONFIG_STM32MP15X)) {
- array = stm32mp15_ip_addr;
- array_size = ARRAY_SIZE(stm32mp15_ip_addr);
- }
-
- for (i = 0; i < ETZPC_DECPROT_NB; i++)
- decprot[i] = readl(ETZPC_DECPROT(i));
-
- for (i = 0; i < array_size; i++) {
- offset = i / NB_PROT_PER_REG;
- shift = (i % NB_PROT_PER_REG) * DECPROT_NB_BITS;
- status = (decprot[offset] >> shift) & DECPROT_MASK;
- addr = array[i];
-
- log_debug("ETZPC: 0x%08x decprot %d=%d\n", addr, i, status);
-
- if (addr == ETZPC_RESERVED ||
- status == DECPROT_NON_SECURED)
- continue;
-
- if (fdt_disable_subnode_by_address(fdt, soc_node, addr))
- log_notice("ETZPC: 0x%08x node disabled, decprot %d=%d\n",
- addr, i, status);
- }
-
- return 0;
-}
-
/* deactivate all the cpu except core 0 */
static void stm32_fdt_fixup_cpu(void *blob, char *name)
{
@@ -481,12 +229,6 @@
if (soc < 0)
return soc;
- if (CONFIG_IS_ENABLED(STM32_ETZPC)) {
- ret = stm32_fdt_fixup_etzpc(blob, soc);
- if (ret)
- return ret;
- }
-
/* MPUs Part Numbers and name*/
cpu = get_cpu_type();
get_soc_name(name);
diff --git a/arch/arm/mach-stm32mp/stm32mp2/Makefile b/arch/arm/mach-stm32mp/stm32mp2/Makefile
index b579ce5..5dbf75d 100644
--- a/arch/arm/mach-stm32mp/stm32mp2/Makefile
+++ b/arch/arm/mach-stm32mp/stm32mp2/Makefile
@@ -5,5 +5,6 @@
obj-y += cpu.o
obj-y += arm64-mmu.o
+obj-y += rifsc.o
obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o
obj-$(CONFIG_STM32MP25X) += stm32mp25x.o
diff --git a/arch/arm/mach-stm32mp/stm32mp2/cpu.c b/arch/arm/mach-stm32mp/stm32mp2/cpu.c
index 9530aa8..c3b87d7 100644
--- a/arch/arm/mach-stm32mp/stm32mp2/cpu.c
+++ b/arch/arm/mach-stm32mp/stm32mp2/cpu.c
@@ -24,7 +24,7 @@
* early TLB into the .data section so that it not get cleared
* with 16kB alignment
*/
-#define EARLY_TLB_SIZE 0xA000
+#define EARLY_TLB_SIZE 0x10000
u8 early_tlb[EARLY_TLB_SIZE] __section(".data") __aligned(0x4000);
/*
@@ -55,6 +55,19 @@
return 0;
}
+int mach_cpu_init(void)
+{
+ u32 boot_mode;
+
+ boot_mode = get_bootmode();
+
+ if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) &&
+ (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
+ gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+
+ return 0;
+}
+
void enable_caches(void)
{
/* deactivate the data cache, early enabled in arch_cpu_init() */
@@ -67,14 +80,6 @@
dcache_enable();
}
-int arch_misc_init(void)
-{
- setup_serial_number();
- setup_mac_address();
-
- return 0;
-}
-
/*
* Force data-section, as .bss will not be valid
* when save_boot_params is invoked.
@@ -97,3 +102,150 @@
save_boot_params_ret();
}
+
+u32 get_bootmode(void)
+{
+ /* read bootmode from TAMP backup register */
+ return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
+ TAMP_BOOT_MODE_SHIFT;
+}
+
+static void setup_boot_mode(void)
+{
+ const u32 serial_addr[] = {
+ STM32_USART1_BASE,
+ STM32_USART2_BASE,
+ STM32_USART3_BASE,
+ STM32_UART4_BASE,
+ STM32_UART5_BASE,
+ STM32_USART6_BASE,
+ STM32_UART7_BASE,
+ STM32_UART8_BASE,
+ STM32_UART9_BASE
+ };
+ const u32 sdmmc_addr[] = {
+ STM32_SDMMC1_BASE,
+ STM32_SDMMC2_BASE,
+ STM32_SDMMC3_BASE
+ };
+ char cmd[60];
+ u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
+ u32 boot_mode =
+ (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
+ unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
+ u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
+ struct udevice *dev;
+
+ log_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
+ __func__, boot_ctx, boot_mode, instance, forced_mode);
+ switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
+ case BOOT_SERIAL_UART:
+ if (instance > ARRAY_SIZE(serial_addr))
+ break;
+ /* serial : search associated node in devicetree */
+ sprintf(cmd, "serial@%x", serial_addr[instance]);
+ if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev)) {
+ /* restore console on error */
+ if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL))
+ gd->flags &= ~(GD_FLG_SILENT |
+ GD_FLG_DISABLE_CONSOLE);
+ log_err("uart%d = %s not found in device tree!\n",
+ instance + 1, cmd);
+ break;
+ }
+ sprintf(cmd, "%d", dev_seq(dev));
+ env_set("boot_device", "serial");
+ env_set("boot_instance", cmd);
+
+ /* restore console on uart when not used */
+ if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && gd->cur_serial_dev != dev) {
+ gd->flags &= ~(GD_FLG_SILENT |
+ GD_FLG_DISABLE_CONSOLE);
+ log_info("serial boot with console enabled!\n");
+ }
+ break;
+ case BOOT_SERIAL_USB:
+ env_set("boot_device", "usb");
+ env_set("boot_instance", "0");
+ break;
+ case BOOT_FLASH_SD:
+ case BOOT_FLASH_EMMC:
+ if (instance > ARRAY_SIZE(sdmmc_addr))
+ break;
+ /* search associated sdmmc node in devicetree */
+ sprintf(cmd, "mmc@%x", sdmmc_addr[instance]);
+ if (uclass_get_device_by_name(UCLASS_MMC, cmd, &dev)) {
+ printf("mmc%d = %s not found in device tree!\n",
+ instance, cmd);
+ break;
+ }
+ sprintf(cmd, "%d", dev_seq(dev));
+ env_set("boot_device", "mmc");
+ env_set("boot_instance", cmd);
+ break;
+ case BOOT_FLASH_NAND:
+ env_set("boot_device", "nand");
+ env_set("boot_instance", "0");
+ break;
+ case BOOT_FLASH_SPINAND:
+ env_set("boot_device", "spi-nand");
+ env_set("boot_instance", "0");
+ break;
+ case BOOT_FLASH_NOR:
+ env_set("boot_device", "nor");
+ if (IS_ENABLED(CONFIG_SYS_MAX_FLASH_BANKS))
+ sprintf(cmd, "%d", CONFIG_SYS_MAX_FLASH_BANKS);
+ else
+ sprintf(cmd, "%d", 0);
+ env_set("boot_instance", cmd);
+ break;
+ case BOOT_FLASH_HYPERFLASH:
+ env_set("boot_device", "nor");
+ env_set("boot_instance", "0");
+ break;
+ default:
+ env_set("boot_device", "invalid");
+ env_set("boot_instance", "");
+ log_err("unexpected boot mode = %x\n", boot_mode);
+ break;
+ }
+
+ switch (forced_mode) {
+ case BOOT_FASTBOOT:
+ log_info("Enter fastboot!\n");
+ env_set("preboot", "env set preboot; fastboot 0");
+ break;
+ case BOOT_STM32PROG:
+ env_set("boot_device", "usb");
+ env_set("boot_instance", "0");
+ break;
+ case BOOT_UMS_MMC0:
+ case BOOT_UMS_MMC1:
+ case BOOT_UMS_MMC2:
+ log_info("Enter UMS!\n");
+ instance = forced_mode - BOOT_UMS_MMC0;
+ sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
+ env_set("preboot", cmd);
+ break;
+ case BOOT_RECOVERY:
+ env_set("preboot", "env set preboot; run altbootcmd");
+ break;
+ case BOOT_NORMAL:
+ break;
+ default:
+ log_debug("unexpected forced boot mode = %x\n", forced_mode);
+ break;
+ }
+
+ /* clear TAMP for next reboot */
+ clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL);
+}
+
+int arch_misc_init(void)
+{
+ setup_boot_mode();
+ setup_serial_number();
+ setup_mac_address();
+
+ return 0;
+}
diff --git a/arch/arm/mach-stm32mp/stm32mp2/rifsc.c b/arch/arm/mach-stm32mp/stm32mp2/rifsc.c
new file mode 100644
index 0000000..50decec
--- /dev/null
+++ b/arch/arm/mach-stm32mp/stm32mp2/rifsc.c
@@ -0,0 +1,364 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#define LOG_CATEGORY UCLASS_NOP
+
+#include <dm.h>
+#include <asm/io.h>
+#include <dm/device.h>
+#include <dm/device_compat.h>
+#include <dm/lists.h>
+#include <linux/bitfield.h>
+#include <mach/rif.h>
+
+/* RIFSC offset register */
+#define RIFSC_RISC_SECCFGR0(id) (0x10 + 0x4 * (id))
+#define RIFSC_RISC_PER0_CIDCFGR(id) (0x100 + 0x8 * (id))
+#define RIFSC_RISC_PER0_SEMCR(id) (0x104 + 0x8 * (id))
+
+/*
+ * SEMCR register
+ */
+#define SEMCR_MUTEX BIT(0)
+
+/* RIFSC miscellaneous */
+#define RIFSC_RISC_SCID_MASK GENMASK(6, 4)
+#define RIFSC_RISC_SEMWL_MASK GENMASK(23, 16)
+
+#define IDS_PER_RISC_SEC_PRIV_REGS 32
+
+/*
+ * CIDCFGR register fields
+ */
+#define CIDCFGR_CFEN BIT(0)
+#define CIDCFGR_SEMEN BIT(1)
+
+#define SEMWL_SHIFT 16
+
+#define STM32MP25_RIFSC_ENTRIES 178
+
+/* Compartiment IDs */
+#define RIF_CID0 0x0
+#define RIF_CID1 0x1
+
+/*
+ * struct stm32_rifsc_plat: Information about RIFSC device
+ *
+ * @base: Base address of RIFSC
+ */
+struct stm32_rifsc_plat {
+ void *base;
+};
+
+/*
+ * struct stm32_rifsc_child_plat: Information about each child
+ *
+ * @domain_id: Domain id
+ */
+struct stm32_rifsc_child_plat {
+ u32 domain_id;
+};
+
+static bool stm32_rif_is_semaphore_available(void *base, u32 id)
+{
+ void *addr = base + RIFSC_RISC_PER0_SEMCR(id);
+
+ return !(readl(addr) & SEMCR_MUTEX);
+}
+
+static int stm32_rif_acquire_semaphore(void *base, u32 id)
+{
+ void *addr = base + RIFSC_RISC_PER0_SEMCR(id);
+
+ /* Check that the semaphore is available */
+ if (!stm32_rif_is_semaphore_available(base, id))
+ return -EACCES;
+
+ setbits_le32(addr, SEMCR_MUTEX);
+
+ /* Check that CID1 has the semaphore */
+ if (stm32_rif_is_semaphore_available(base, id) ||
+ FIELD_GET(RIFSC_RISC_SCID_MASK, (readl(addr)) != RIF_CID1))
+ return -EACCES;
+
+ return 0;
+}
+
+static int stm32_rif_release_semaphore(void *base, u32 id)
+{
+ void *addr = base + RIFSC_RISC_PER0_SEMCR(id);
+
+ if (stm32_rif_is_semaphore_available(base, id))
+ return 0;
+
+ clrbits_le32(addr, SEMCR_MUTEX);
+
+ /* Ok if another compartment takes the semaphore before the check */
+ if (!stm32_rif_is_semaphore_available(base, id) &&
+ FIELD_GET(RIFSC_RISC_SCID_MASK, (readl(addr)) == RIF_CID1))
+ return -EACCES;
+
+ return 0;
+}
+
+static int rifsc_parse_access_controller(ofnode node, struct ofnode_phandle_args *args)
+{
+ int ret;
+
+ ret = ofnode_parse_phandle_with_args(node, "access-controllers",
+ "#access-controller-cells", 0,
+ 0, args);
+ if (ret) {
+ log_debug("failed to parse access-controller (%d)\n", ret);
+ return ret;
+ }
+
+ if (args->args_count != 1) {
+ log_debug("invalid domain args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ if (args->args[0] >= STM32MP25_RIFSC_ENTRIES) {
+ log_err("Invalid sys bus ID for %s\n", ofnode_get_name(node));
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int rifsc_check_access(void *base, u32 id)
+{
+ u32 reg_offset, reg_id, sec_reg_value, cid_reg_value, sem_reg_value;
+
+ /*
+ * RIFSC_RISC_PRIVCFGRx and RIFSC_RISC_SECCFGRx both handle configuration access for
+ * 32 peripherals. On the other hand, there is one _RIFSC_RISC_PERx_CIDCFGR register
+ * per peripheral
+ */
+ reg_id = id / IDS_PER_RISC_SEC_PRIV_REGS;
+ reg_offset = id % IDS_PER_RISC_SEC_PRIV_REGS;
+ sec_reg_value = readl(base + RIFSC_RISC_SECCFGR0(reg_id));
+ cid_reg_value = readl(base + RIFSC_RISC_PER0_CIDCFGR(id));
+ sem_reg_value = readl(base + RIFSC_RISC_PER0_SEMCR(id));
+
+ /*
+ * First check conditions for semaphore mode, which doesn't take into
+ * account static CID.
+ */
+ if (cid_reg_value & CIDCFGR_SEMEN)
+ goto skip_cid_check;
+
+ /*
+ * Skip cid check if CID filtering isn't enabled or filtering is enabled on CID0, which
+ * corresponds to whatever CID.
+ */
+ if (!(cid_reg_value & CIDCFGR_CFEN) ||
+ FIELD_GET(RIFSC_RISC_SCID_MASK, cid_reg_value) == RIF_CID0)
+ goto skip_cid_check;
+
+ /* Coherency check with the CID configuration */
+ if (FIELD_GET(RIFSC_RISC_SCID_MASK, cid_reg_value) != RIF_CID1) {
+ log_debug("Invalid CID configuration for peripheral %d\n", id);
+ return -EACCES;
+ }
+
+ /* Check semaphore accesses */
+ if (cid_reg_value & CIDCFGR_SEMEN) {
+ if (!(FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) {
+ log_debug("Not in semaphore whitelist for peripheral %d\n", id);
+ return -EACCES;
+ }
+ if (!stm32_rif_is_semaphore_available(base, id) &&
+ !(FIELD_GET(RIFSC_RISC_SCID_MASK, sem_reg_value) & BIT(RIF_CID1))) {
+ log_debug("Semaphore unavailable for peripheral %d\n", id);
+ return -EACCES;
+ }
+ }
+
+skip_cid_check:
+ /* Check security configuration */
+ if (sec_reg_value & BIT(reg_offset)) {
+ log_debug("Invalid security configuration for peripheral %d\n", id);
+ return -EACCES;
+ }
+
+ return 0;
+}
+
+int stm32_rifsc_check_access_by_id(ofnode device_node, u32 id)
+{
+ struct ofnode_phandle_args args;
+ int err;
+
+ if (id >= STM32MP25_RIFSC_ENTRIES)
+ return -EINVAL;
+
+ err = rifsc_parse_access_controller(device_node, &args);
+ if (err)
+ return err;
+
+ return rifsc_check_access((void *)ofnode_get_addr(args.node), id);
+}
+
+int stm32_rifsc_check_access(ofnode device_node)
+{
+ struct ofnode_phandle_args args;
+ int err;
+
+ err = rifsc_parse_access_controller(device_node, &args);
+ if (err)
+ return err;
+
+ return rifsc_check_access((void *)ofnode_get_addr(args.node), args.args[0]);
+}
+
+static int stm32_rifsc_child_pre_probe(struct udevice *dev)
+{
+ struct stm32_rifsc_plat *plat = dev_get_plat(dev->parent);
+ struct stm32_rifsc_child_plat *child_plat = dev_get_parent_plat(dev);
+ u32 cid_reg_value;
+ int err;
+ u32 id = child_plat->domain_id;
+
+ cid_reg_value = readl(plat->base + RIFSC_RISC_PER0_CIDCFGR(id));
+
+ /*
+ * If the peripheral is in semaphore mode, take the semaphore so that
+ * the CID1 has the ownership.
+ */
+ if (cid_reg_value & CIDCFGR_SEMEN &&
+ (FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) {
+ err = stm32_rif_acquire_semaphore(plat->base, id);
+ if (err) {
+ dev_err(dev, "Couldn't acquire RIF semaphore for peripheral %d (%d)\n",
+ id, err);
+ return err;
+ }
+ dev_dbg(dev, "Acquiring semaphore for peripheral %d\n", id);
+ }
+
+ return 0;
+}
+
+static int stm32_rifsc_child_post_remove(struct udevice *dev)
+{
+ struct stm32_rifsc_plat *plat = dev_get_plat(dev->parent);
+ struct stm32_rifsc_child_plat *child_plat = dev_get_parent_plat(dev);
+ u32 cid_reg_value;
+ int err;
+ u32 id = child_plat->domain_id;
+
+ cid_reg_value = readl(plat->base + RIFSC_RISC_PER0_CIDCFGR(id));
+
+ /*
+ * If the peripheral is in semaphore mode, release the semaphore so that
+ * there's no ownership.
+ */
+ if (cid_reg_value & CIDCFGR_SEMEN &&
+ (FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) {
+ err = stm32_rif_release_semaphore(plat->base, id);
+ if (err)
+ dev_err(dev, "Couldn't release rif semaphore for peripheral %d (%d)\n",
+ id, err);
+ }
+
+ return 0;
+}
+
+static int stm32_rifsc_child_post_bind(struct udevice *dev)
+{
+ struct stm32_rifsc_child_plat *child_plat = dev_get_parent_plat(dev);
+ struct ofnode_phandle_args args;
+ int ret;
+
+ if (!dev_has_ofnode(dev))
+ return -EPERM;
+
+ ret = rifsc_parse_access_controller(dev_ofnode(dev), &args);
+ if (ret)
+ return ret;
+
+ child_plat->domain_id = args.args[0];
+
+ return 0;
+}
+
+static int stm32_rifsc_bind(struct udevice *dev)
+{
+ struct stm32_rifsc_plat *plat = dev_get_plat(dev);
+ struct ofnode_phandle_args args;
+ int ret = 0, err = 0;
+ ofnode node;
+
+ plat->base = dev_read_addr_ptr(dev);
+ if (!plat->base) {
+ dev_err(dev, "can't get registers base address\n");
+ return -ENOENT;
+ }
+
+ for (node = ofnode_first_subnode(dev_ofnode(dev));
+ ofnode_valid(node);
+ node = ofnode_next_subnode(node)) {
+ const char *node_name = ofnode_get_name(node);
+
+ if (!ofnode_is_enabled(node))
+ continue;
+
+ err = rifsc_parse_access_controller(node, &args);
+ if (err) {
+ dev_dbg(dev, "%s failed to parse child on bus (%d)\n", node_name, err);
+ continue;
+ }
+
+ err = rifsc_check_access(plat->base, args.args[0]);
+ if (err) {
+ dev_info(dev, "%s not allowed on bus (%d)\n", node_name, err);
+ continue;
+ }
+
+ err = lists_bind_fdt(dev, node, NULL, NULL,
+ gd->flags & GD_FLG_RELOC ? false : true);
+ if (err && !ret) {
+ ret = err;
+ dev_err(dev, "%s failed to bind on bus (%d)\n", node_name, ret);
+ }
+ }
+
+ if (ret)
+ dev_err(dev, "Some child failed to bind (%d)\n", ret);
+
+ return ret;
+}
+
+static int stm32_rifsc_remove(struct udevice *bus)
+{
+ struct udevice *dev;
+
+ /* Deactivate all child devices not yet removed */
+ for (device_find_first_child(bus, &dev); dev; device_find_next_child(&dev))
+ if (device_active(dev))
+ stm32_rifsc_child_post_remove(dev);
+
+ return 0;
+}
+
+static const struct udevice_id stm32_rifsc_ids[] = {
+ { .compatible = "st,stm32mp25-rifsc" },
+ {},
+};
+
+U_BOOT_DRIVER(stm32_rifsc) = {
+ .name = "stm32_rifsc",
+ .id = UCLASS_NOP,
+ .of_match = stm32_rifsc_ids,
+ .bind = stm32_rifsc_bind,
+ .remove = stm32_rifsc_remove,
+ .child_post_bind = stm32_rifsc_child_post_bind,
+ .child_pre_probe = stm32_rifsc_child_pre_probe,
+ .child_post_remove = stm32_rifsc_child_post_remove,
+ .plat_auto = sizeof(struct stm32_rifsc_plat),
+ .per_child_plat_auto = sizeof(struct stm32_rifsc_child_plat),
+ .flags = DM_FLAG_OS_PREPARE,
+};
diff --git a/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c b/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c
index 7f896a0..12b43ea 100644
--- a/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c
+++ b/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c
@@ -15,8 +15,10 @@
#define SYSCFG_DEVICEID_OFFSET 0x6400
#define SYSCFG_DEVICEID_DEV_ID_MASK GENMASK(11, 0)
#define SYSCFG_DEVICEID_DEV_ID_SHIFT 0
-#define SYSCFG_DEVICEID_REV_ID_MASK GENMASK(31, 16)
-#define SYSCFG_DEVICEID_REV_ID_SHIFT 16
+
+/* Revision ID = OTP102[5:0] 6 bits : 3 for Major / 3 for Minor*/
+#define REVID_SHIFT 0
+#define REVID_MASK GENMASK(5, 0)
/* Device Part Number (RPN) = OTP9 */
#define RPN_SHIFT 0
@@ -24,8 +26,8 @@
/* Package = bit 0:2 of OTP122 => STM32MP25_PKG defines
* - 000: Custom package
- * - 011: TFBGA361 => AL = 10x10, 361 balls pith 0.5mm
- * - 100: TFBGA424 => AK = 14x14, 424 balls pith 0.5mm
+ * - 001: VFBGA361 => AL = 10x10, 361 balls pith 0.5mm
+ * - 011: VFBGA424 => AK = 14x14, 424 balls pith 0.5mm
* - 101: TFBGA436 => AI = 18x18, 436 balls pith 0.5mm
* - others: Reserved
*/
@@ -46,7 +48,7 @@
u32 get_cpu_rev(void)
{
- return (read_deviceid() & SYSCFG_DEVICEID_REV_ID_MASK) >> SYSCFG_DEVICEID_REV_ID_SHIFT;
+ return get_otp(BSEC_OTP_REVID, REVID_SHIFT, REVID_MASK);
}
/* Get Device Part Number (RPN) from OTP */
@@ -164,12 +166,21 @@
}
/* REVISION */
switch (get_cpu_rev()) {
- case CPU_REV1:
+ case OTP_REVID_1:
cpu_r = "A";
break;
+ case OTP_REVID_1_1:
+ cpu_r = "Z";
+ break;
- case CPU_REV2:
+ case OTP_REVID_2:
cpu_r = "B";
break;
+ case OTP_REVID_2_1:
+ cpu_r = "Y";
+ break;
+ case OTP_REVID_2_2:
+ cpu_r = "X";
+ break;
default:
break;
}
@@ -178,13 +189,13 @@
case STM32MP25_PKG_CUSTOM:
package = "XX";
break;
- case STM32MP25_PKG_AL_TBGA361:
+ case STM32MP25_PKG_AL_VFBGA361:
package = "AL";
break;
- case STM32MP25_PKG_AK_TBGA424:
+ case STM32MP25_PKG_AK_VFBGA424:
package = "AK";
break;
- case STM32MP25_PKG_AI_TBGA436:
+ case STM32MP25_PKG_AI_TFBGA436:
package = "AI";
break;
default:
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index ab43239..1717959 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -782,49 +782,6 @@
slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
support for this.
-config USB0_VBUS_PIN
- string "Vbus enable pin for usb0 (otg)"
- default ""
- ---help---
- Set the Vbus enable pin for usb0 (otg). This takes a string in the
- format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
-config USB0_VBUS_DET
- string "Vbus detect pin for usb0 (otg)"
- default ""
- ---help---
- Set the Vbus detect pin for usb0 (otg). This takes a string in the
- format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
-config USB0_ID_DET
- string "ID detect pin for usb0 (otg)"
- default ""
- ---help---
- Set the ID detect pin for usb0 (otg). This takes a string in the
- format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
-config USB1_VBUS_PIN
- string "Vbus enable pin for usb1 (ehci0)"
- default "PH6" if MACH_SUN4I || MACH_SUN7I
- default "PH27" if MACH_SUN6I
- ---help---
- Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
- a string in the format understood by sunxi_name_to_gpio, e.g.
- PH1 for pin 1 of port H.
-
-config USB2_VBUS_PIN
- string "Vbus enable pin for usb2 (ehci1)"
- default "PH3" if MACH_SUN4I || MACH_SUN7I
- default "PH24" if MACH_SUN6I
- ---help---
- See USB1_VBUS_PIN help text.
-
-config USB3_VBUS_PIN
- string "Vbus enable pin for usb3 (ehci2)"
- default ""
- ---help---
- See USB1_VBUS_PIN help text.
-
config I2C0_ENABLE
bool "Enable I2C/TWI controller 0"
default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
@@ -879,6 +836,7 @@
depends on !SUNXI_GEN_NCAT2
select VIDEO
select DISPLAY
+ imply VIDEO_DAMAGE
imply VIDEO_DT_SIMPLEFB
default y
---help---
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index eb6a491..a33cd5b 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -41,8 +41,8 @@
obj-$(CONFIG_SPL_SPI_SUNXI) += spl_spi_sunxi.o
obj-$(CONFIG_SUNXI_DRAM_DW) += dram_sunxi_dw.o
obj-$(CONFIG_SUNXI_DRAM_DW) += dram_timings/
-obj-$(CONFIG_DRAM_SUN50I_H6) += dram_sun50i_h6.o
+obj-$(CONFIG_DRAM_SUN50I_H6) += dram_sun50i_h6.o dram_dw_helpers.o
obj-$(CONFIG_DRAM_SUN50I_H6) += dram_timings/
-obj-$(CONFIG_DRAM_SUN50I_H616) += dram_sun50i_h616.o
+obj-$(CONFIG_DRAM_SUN50I_H616) += dram_sun50i_h616.o dram_dw_helpers.o
obj-$(CONFIG_DRAM_SUN50I_H616) += dram_timings/
endif
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 701899e..b1bf51f 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -35,6 +35,9 @@
uint32_t cpsr;
uint32_t sctlr;
uint32_t vbar;
+ uint32_t sp_irq;
+ uint32_t icc_pmr;
+ uint32_t icc_igrpen1;
};
struct fel_stash fel_stash __section(".data");
diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index 359513d..4c522f6 100644
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -6,86 +6,83 @@
#ifdef CONFIG_XPL_BUILD
void clock_init_safe(void)
{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- struct sunxi_prcm_reg *const prcm =
- (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+ void *const ccm = (void *)SUNXI_CCM_BASE;
+ void *const prcm = (void *)SUNXI_PRCM_BASE;
if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) {
/* this seems to enable PLLs on H616 */
- setbits_le32(&prcm->sys_pwroff_gating, 0x10);
- setbits_le32(&prcm->res_cal_ctrl, 2);
+ setbits_le32(prcm + CCU_PRCM_SYS_PWROFF_GATING, 0x10);
+ setbits_le32(prcm + CCU_PRCM_RES_CAL_CTRL, 2);
}
if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) ||
IS_ENABLED(CONFIG_MACH_SUN50I_H6)) {
- clrbits_le32(&prcm->res_cal_ctrl, 1);
- setbits_le32(&prcm->res_cal_ctrl, 1);
+ clrbits_le32(prcm + CCU_PRCM_RES_CAL_CTRL, 1);
+ setbits_le32(prcm + CCU_PRCM_RES_CAL_CTRL, 1);
}
if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) {
/* set key field for ldo enable */
- setbits_le32(&prcm->pll_ldo_cfg, 0xA7000000);
+ setbits_le32(prcm + CCU_PRCM_PLL_LDO_CFG, 0xA7000000);
/* set PLL VDD LDO output to 1.14 V */
- setbits_le32(&prcm->pll_ldo_cfg, 0x60000);
+ setbits_le32(prcm + CCU_PRCM_PLL_LDO_CFG, 0x60000);
}
clock_set_pll1(408000000);
- writel(CCM_PLL6_DEFAULT, &ccm->pll6_cfg);
- while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_LOCK))
+ writel(CCM_PLL6_DEFAULT, ccm + CCU_H6_PLL6_CFG);
+ while (!(readl(ccm + CCU_H6_PLL6_CFG) & CCM_PLL6_LOCK))
;
- clrsetbits_le32(&ccm->cpu_axi_cfg, CCM_CPU_AXI_APB_MASK | CCM_CPU_AXI_AXI_MASK,
+ clrsetbits_le32(ccm + CCU_H6_CPU_AXI_CFG,
+ CCM_CPU_AXI_APB_MASK | CCM_CPU_AXI_AXI_MASK,
CCM_CPU_AXI_DEFAULT_FACTORS);
- writel(CCM_PSI_AHB1_AHB2_DEFAULT, &ccm->psi_ahb1_ahb2_cfg);
+ writel(CCM_PSI_AHB1_AHB2_DEFAULT, ccm + CCU_H6_PSI_AHB1_AHB2_CFG);
#ifdef CCM_AHB3_DEFAULT
- writel(CCM_AHB3_DEFAULT, &ccm->ahb3_cfg);
+ writel(CCM_AHB3_DEFAULT, ccm + CCU_H6_AHB3_CFG);
#endif
- writel(CCM_APB1_DEFAULT, &ccm->apb1_cfg);
+ writel(CCM_APB1_DEFAULT, ccm + CCU_H6_APB1_CFG);
/*
* The mux and factor are set, but the clock will be enabled in
* DRAM initialization code.
*/
- writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), &ccm->mbus_cfg);
+ writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), ccm + CCU_H6_MBUS_CFG);
}
void clock_init_uart(void)
{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ void *const ccm = (void *)SUNXI_CCM_BASE;
/* uart clock source is apb2 */
writel(APB2_CLK_SRC_OSC24M|
APB2_CLK_RATE_N_1|
APB2_CLK_RATE_M(1),
- &ccm->apb2_cfg);
+ ccm + CCU_H6_APB2_CFG);
/* open the clock for uart */
- setbits_le32(&ccm->uart_gate_reset,
+ setbits_le32(ccm + CCU_H6_UART_GATE_RESET,
1 << (CONFIG_CONS_INDEX - 1));
/* deassert uart reset */
- setbits_le32(&ccm->uart_gate_reset,
+ setbits_le32(ccm + CCU_H6_UART_GATE_RESET,
1 << (RESET_SHIFT + CONFIG_CONS_INDEX - 1));
}
void clock_set_pll1(unsigned int clk)
{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ void *const ccm = (void *)SUNXI_CCM_BASE;
u32 val;
/* Do not support clocks < 288MHz as they need factor P */
if (clk < 288000000) clk = 288000000;
/* Switch to 24MHz clock while changing PLL1 */
- val = readl(&ccm->cpu_axi_cfg);
+ val = readl(ccm + CCU_H6_CPU_AXI_CFG);
val &= ~CCM_CPU_AXI_MUX_MASK;
val |= CCM_CPU_AXI_MUX_OSC24M;
- writel(val, &ccm->cpu_axi_cfg);
+ writel(val, ccm + CCU_H6_CPU_AXI_CFG);
/* clk = 24*n/p, p is ignored if clock is >288MHz */
val = CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2;
@@ -94,22 +91,20 @@
val |= CCM_PLL1_OUT_EN;
if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2))
val |= CCM_PLL1_OUT_EN | CCM_PLL1_LDO_EN;
- writel(val, &ccm->pll1_cfg);
- while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_LOCK)) {}
+ writel(val, ccm + CCU_H6_PLL1_CFG);
+ while (!(readl(ccm + CCU_H6_PLL1_CFG) & CCM_PLL1_LOCK)) {}
/* Switch CPU to PLL1 */
- val = readl(&ccm->cpu_axi_cfg);
+ val = readl(ccm + CCU_H6_CPU_AXI_CFG);
val &= ~CCM_CPU_AXI_MUX_MASK;
val |= CCM_CPU_AXI_MUX_PLL_CPUX;
- writel(val, &ccm->cpu_axi_cfg);
+ writel(val, ccm + CCU_H6_CPU_AXI_CFG);
}
int clock_twi_onoff(int port, int state)
{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- struct sunxi_prcm_reg *const prcm =
- (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+ void *const ccm = (void *)SUNXI_CCM_BASE;
+ void *const prcm = (void *)SUNXI_PRCM_BASE;
u32 value, *ptr;
int shift;
@@ -117,10 +112,10 @@
if (port == 5) {
shift = 0;
- ptr = &prcm->twi_gate_reset;
+ ptr = prcm + CCU_PRCM_I2C_GATE_RESET;
} else {
shift = port;
- ptr = &ccm->twi_gate_reset;
+ ptr = ccm + CCU_H6_I2C_GATE_RESET;
}
/* set the apb clock gate and reset for twi */
@@ -136,9 +131,8 @@
/* PLL_PERIPH0 clock, used by the MMC driver */
unsigned int clock_get_pll6(void)
{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- uint32_t rval = readl(&ccm->pll6_cfg);
+ void *const ccm = (void *)SUNXI_CCM_BASE;
+ uint32_t rval = readl(ccm + CCU_H6_PLL6_CFG);
int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
diff --git a/arch/arm/mach-sunxi/dram_dw_helpers.c b/arch/arm/mach-sunxi/dram_dw_helpers.c
new file mode 100644
index 0000000..2476735
--- /dev/null
+++ b/arch/arm/mach-sunxi/dram_dw_helpers.c
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Helpers that are commonly used with DW memory controller.
+ *
+ * (C) Copyright 2025 Jernej Skrabec <jernej.skrabec@gmail.com>
+ *
+ */
+
+#include <init.h>
+#include <asm/arch/dram_dw_helpers.h>
+
+void mctl_auto_detect_rank_width(const struct dram_para *para,
+ struct dram_config *config)
+{
+ /* this is minimum size that it's supported */
+ config->cols = 8;
+ config->rows = 13;
+
+ /*
+ * Strategy here is to test most demanding combination first and least
+ * demanding last, otherwise HW might not be fully utilized. For
+ * example, half bus width and rank = 1 combination would also work
+ * on HW with full bus width and rank = 2, but only 1/4 RAM would be
+ * visible.
+ */
+
+ debug("testing 32-bit width, rank = 2\n");
+ config->bus_full_width = 1;
+ config->ranks = 2;
+ if (mctl_core_init(para, config))
+ return;
+
+ debug("testing 32-bit width, rank = 1\n");
+ config->bus_full_width = 1;
+ config->ranks = 1;
+ if (mctl_core_init(para, config))
+ return;
+
+ debug("testing 16-bit width, rank = 2\n");
+ config->bus_full_width = 0;
+ config->ranks = 2;
+ if (mctl_core_init(para, config))
+ return;
+
+ debug("testing 16-bit width, rank = 1\n");
+ config->bus_full_width = 0;
+ config->ranks = 1;
+ if (mctl_core_init(para, config))
+ return;
+
+ panic("This DRAM setup is currently not supported.\n");
+}
+
+static void mctl_write_pattern(void)
+{
+ unsigned int i;
+ u32 *ptr, val;
+
+ ptr = (u32 *)CFG_SYS_SDRAM_BASE;
+ for (i = 0; i < 16; ptr++, i++) {
+ if (i & 1)
+ val = ~(ulong)ptr;
+ else
+ val = (ulong)ptr;
+ writel(val, ptr);
+ }
+}
+
+static bool mctl_check_pattern(ulong offset)
+{
+ unsigned int i;
+ u32 *ptr, val;
+
+ ptr = (u32 *)CFG_SYS_SDRAM_BASE;
+ for (i = 0; i < 16; ptr++, i++) {
+ if (i & 1)
+ val = ~(ulong)ptr;
+ else
+ val = (ulong)ptr;
+ if (val != *(ptr + offset / 4))
+ return false;
+ }
+
+ return true;
+}
+
+void mctl_auto_detect_dram_size(const struct dram_para *para,
+ struct dram_config *config)
+{
+ unsigned int shift, cols, rows;
+ u32 buffer[16];
+
+ /* max. config for columns, but not rows */
+ config->cols = 11;
+ config->rows = 13;
+ mctl_core_init(para, config);
+
+ /*
+ * Store content so it can be restored later. This is important
+ * if controller was already initialized and holds any data
+ * which is important for restoring system.
+ */
+ memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer));
+
+ mctl_write_pattern();
+
+ shift = config->bus_full_width + 1;
+
+ /* detect column address bits */
+ for (cols = 8; cols < 11; cols++) {
+ if (mctl_check_pattern(1ULL << (cols + shift)))
+ break;
+ }
+ debug("detected %u columns\n", cols);
+
+ /* restore data */
+ memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer));
+
+ /* reconfigure to make sure that all active rows are accessible */
+ config->cols = 8;
+ config->rows = 17;
+ mctl_core_init(para, config);
+
+ /* store data again as it might be moved */
+ memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer));
+
+ mctl_write_pattern();
+
+ /* detect row address bits */
+ shift = config->bus_full_width + 4 + config->cols;
+ for (rows = 13; rows < 17; rows++) {
+ if (mctl_check_pattern(1ULL << (rows + shift)))
+ break;
+ }
+ debug("detected %u rows\n", rows);
+
+ /* restore data again */
+ memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer));
+
+ config->cols = cols;
+ config->rows = rows;
+}
+
+unsigned long mctl_calc_size(const struct dram_config *config)
+{
+ u8 width = config->bus_full_width ? 4 : 2;
+
+ /* 8 banks */
+ return (1ULL << (config->cols + config->rows + 3)) * width * config->ranks;
+}
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c
index e7862bd..84fd64a 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c
@@ -10,6 +10,7 @@
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/dram.h>
+#include <asm/arch/dram_dw_helpers.h>
#include <asm/arch/cpu.h>
#include <asm/arch/prcm.h>
#include <linux/bitops.h>
@@ -34,23 +35,26 @@
* similar PHY is ZynqMP.
*/
-static void mctl_sys_init(struct dram_para *para);
-static void mctl_com_init(struct dram_para *para);
-static bool mctl_channel_init(struct dram_para *para);
+static void mctl_sys_init(u32 clk_rate);
+static void mctl_com_init(const struct dram_para *para,
+ const struct dram_config *config);
+static bool mctl_channel_init(const struct dram_para *para,
+ const struct dram_config *config);
-static bool mctl_core_init(struct dram_para *para)
+bool mctl_core_init(const struct dram_para *para,
+ const struct dram_config *config)
{
- mctl_sys_init(para);
- mctl_com_init(para);
+ mctl_sys_init(para->clk);
+ mctl_com_init(para, config);
switch (para->type) {
case SUNXI_DRAM_TYPE_LPDDR3:
case SUNXI_DRAM_TYPE_DDR3:
- mctl_set_timing_params(para);
+ mctl_set_timing_params();
break;
default:
panic("Unsupported DRAM type!");
};
- return mctl_channel_init(para);
+ return mctl_channel_init(para, config);
}
/* PHY initialisation */
@@ -150,36 +154,36 @@
MBUS_CONF(HDCP2, true, HIGH, 2, 100, 64, 32);
}
-static void mctl_sys_init(struct dram_para *para)
+static void mctl_sys_init(u32 clk_rate)
{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ void * const ccm = (void *)SUNXI_CCM_BASE;
struct sunxi_mctl_com_reg * const mctl_com =
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
/* Put all DRAM-related blocks to reset state */
- clrbits_le32(&ccm->mbus_cfg, MBUS_ENABLE | MBUS_RESET);
- clrbits_le32(&ccm->dram_gate_reset, BIT(0));
+ clrbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_ENABLE | MBUS_RESET);
+ clrbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(0));
udelay(5);
- writel(0, &ccm->dram_gate_reset);
- clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
- clrbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);
+ writel(0, ccm + CCU_H6_DRAM_GATE_RESET);
+ clrbits_le32(ccm + CCU_H6_PLL5_CFG, CCM_PLL5_CTRL_EN);
+ clrbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_MOD_RESET);
udelay(5);
/* Set PLL5 rate to doubled DRAM clock rate */
writel(CCM_PLL5_CTRL_EN | CCM_PLL5_LOCK_EN |
- CCM_PLL5_CTRL_N(para->clk * 2 / 24), &ccm->pll5_cfg);
- mctl_await_completion(&ccm->pll5_cfg, CCM_PLL5_LOCK, CCM_PLL5_LOCK);
+ CCM_PLL5_CTRL_N(clk_rate * 2 / 24), ccm + CCU_H6_PLL5_CFG);
+ mctl_await_completion(ccm + CCU_H6_PLL5_CFG,
+ CCM_PLL5_LOCK, CCM_PLL5_LOCK);
/* Configure DRAM mod clock */
- writel(DRAM_CLK_SRC_PLL5, &ccm->dram_clk_cfg);
- setbits_le32(&ccm->dram_clk_cfg, DRAM_CLK_UPDATE);
- writel(BIT(RESET_SHIFT), &ccm->dram_gate_reset);
+ writel(DRAM_CLK_SRC_PLL5, ccm + CCU_H6_DRAM_CLK_CFG);
+ setbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_CLK_UPDATE);
+ writel(BIT(RESET_SHIFT), ccm + CCU_H6_DRAM_GATE_RESET);
udelay(5);
- setbits_le32(&ccm->dram_gate_reset, BIT(0));
+ setbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(0));
/* Disable all channels */
writel(0, &mctl_com->maer0);
@@ -187,24 +191,24 @@
writel(0, &mctl_com->maer2);
/* Configure MBUS and enable DRAM mod reset */
- setbits_le32(&ccm->mbus_cfg, MBUS_RESET);
- setbits_le32(&ccm->mbus_cfg, MBUS_ENABLE);
- setbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);
+ setbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_RESET);
+ setbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_ENABLE);
+ setbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_MOD_RESET);
udelay(5);
/* Unknown hack from the BSP, which enables access of mctl_ctl regs */
writel(0x8000, &mctl_ctl->unk_0x00c);
}
-static void mctl_set_addrmap(struct dram_para *para)
+static void mctl_set_addrmap(const struct dram_config *config)
{
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
- u8 cols = para->cols;
- u8 rows = para->rows;
- u8 ranks = para->ranks;
+ u8 cols = config->cols;
+ u8 rows = config->rows;
+ u8 ranks = config->ranks;
- if (!para->bus_full_width)
+ if (!config->bus_full_width)
cols -= 1;
/* Ranks */
@@ -282,7 +286,8 @@
mctl_ctl->addrmap[8] = 0x3F3F;
}
-static void mctl_com_init(struct dram_para *para)
+static void mctl_com_init(const struct dram_para *para,
+ const struct dram_config *config)
{
struct sunxi_mctl_com_reg * const mctl_com =
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
@@ -292,7 +297,7 @@
(struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
u32 reg_val, tmp;
- mctl_set_addrmap(para);
+ mctl_set_addrmap(config);
setbits_le32(&mctl_com->cr, BIT(31));
@@ -311,12 +316,12 @@
clrsetbits_le32(&mctl_com->unk_0x008, 0x3f00, reg_val);
/* TODO: DDR4 */
- reg_val = MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(para->ranks);
+ reg_val = MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(config->ranks);
if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
reg_val |= MSTR_DEVICETYPE_LPDDR3;
if (para->type == SUNXI_DRAM_TYPE_DDR3)
reg_val |= MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE;
- if (para->bus_full_width)
+ if (config->bus_full_width)
reg_val |= MSTR_BUSWIDTH_FULL;
else
reg_val |= MSTR_BUSWIDTH_HALF;
@@ -328,7 +333,7 @@
reg_val = DCR_DDR3 | DCR_DDR8BANK | DCR_DDR2T;
writel(reg_val | 0x400, &mctl_phy->dcr);
- if (para->ranks == 2)
+ if (config->ranks == 2)
writel(0x0303, &mctl_ctl->odtmap);
else
writel(0x0201, &mctl_ctl->odtmap);
@@ -346,13 +351,13 @@
}
writel(reg_val, &mctl_ctl->odtcfg);
- if (!para->bus_full_width) {
+ if (!config->bus_full_width) {
writel(0x0, &mctl_phy->dx[2].gcr[0]);
writel(0x0, &mctl_phy->dx[3].gcr[0]);
}
}
-static void mctl_bit_delay_set(struct dram_para *para)
+static void mctl_bit_delay_set(const struct dram_para *para)
{
struct sunxi_mctl_phy_reg * const mctl_phy =
(struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
@@ -411,7 +416,8 @@
}
}
-static bool mctl_channel_init(struct dram_para *para)
+static bool mctl_channel_init(const struct dram_para *para,
+ const struct dram_config *config)
{
struct sunxi_mctl_com_reg * const mctl_com =
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
@@ -446,14 +452,14 @@
udelay(100);
- if (para->ranks == 2)
+ if (config->ranks == 2)
setbits_le32(&mctl_phy->dtcr[1], 0x30000);
else
clrsetbits_le32(&mctl_phy->dtcr[1], 0x30000, 0x10000);
if (sunxi_dram_is_lpddr(para->type))
clrbits_le32(&mctl_phy->dtcr[1], BIT(1));
- if (para->ranks == 2) {
+ if (config->ranks == 2) {
writel(0x00010001, &mctl_phy->rankidr);
writel(0x20000, &mctl_phy->odtcr);
} else {
@@ -555,90 +561,6 @@
return true;
}
-static void mctl_auto_detect_rank_width(struct dram_para *para)
-{
- /* this is minimum size that it's supported */
- para->cols = 8;
- para->rows = 13;
-
- /*
- * Previous versions of this driver tried to auto detect the rank
- * and width by looking at controller registers. However this proved
- * to be not reliable, so this approach here is the more robust
- * solution. Check the git history for details.
- *
- * Strategy here is to test most demanding combination first and least
- * demanding last, otherwise HW might not be fully utilized. For
- * example, half bus width and rank = 1 combination would also work
- * on HW with full bus width and rank = 2, but only 1/4 RAM would be
- * visible.
- */
-
- debug("testing 32-bit width, rank = 2\n");
- para->bus_full_width = 1;
- para->ranks = 2;
- if (mctl_core_init(para))
- return;
-
- debug("testing 32-bit width, rank = 1\n");
- para->bus_full_width = 1;
- para->ranks = 1;
- if (mctl_core_init(para))
- return;
-
- debug("testing 16-bit width, rank = 2\n");
- para->bus_full_width = 0;
- para->ranks = 2;
- if (mctl_core_init(para))
- return;
-
- debug("testing 16-bit width, rank = 1\n");
- para->bus_full_width = 0;
- para->ranks = 1;
- if (mctl_core_init(para))
- return;
-
- panic("This DRAM setup is currently not supported.\n");
-}
-
-static void mctl_auto_detect_dram_size(struct dram_para *para)
-{
- /* TODO: non-(LP)DDR3 */
-
- /* detect row address bits */
- para->cols = 8;
- para->rows = 18;
- mctl_core_init(para);
-
- for (para->rows = 13; para->rows < 18; para->rows++) {
- /* 8 banks, 8 bit per byte and 16/32 bit width */
- if (mctl_mem_matches((1 << (para->rows + para->cols +
- 4 + para->bus_full_width))))
- break;
- }
-
- /* detect column address bits */
- para->cols = 11;
- mctl_core_init(para);
-
- for (para->cols = 8; para->cols < 11; para->cols++) {
- /* 8 bits per byte and 16/32 bit width */
- if (mctl_mem_matches(1 << (para->cols + 1 +
- para->bus_full_width)))
- break;
- }
-}
-
-unsigned long mctl_calc_size(struct dram_para *para)
-{
- u8 width = para->bus_full_width ? 4 : 2;
-
- /* TODO: non-(LP)DDR3 */
-
- /* 8 banks */
- return (1ULL << (para->cols + para->rows + 3)) * width * para->ranks;
-}
-
#define SUN50I_H6_LPDDR3_DX_WRITE_DELAYS \
{{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
@@ -661,36 +583,36 @@
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }}
-unsigned long sunxi_dram_init(void)
-{
- struct sunxi_mctl_com_reg * const mctl_com =
- (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
- struct sunxi_prcm_reg *const prcm =
- (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
- struct dram_para para = {
- .clk = CONFIG_DRAM_CLK,
+static const struct dram_para para = {
+ .clk = CONFIG_DRAM_CLK,
#ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3
- .type = SUNXI_DRAM_TYPE_LPDDR3,
- .dx_read_delays = SUN50I_H6_LPDDR3_DX_READ_DELAYS,
- .dx_write_delays = SUN50I_H6_LPDDR3_DX_WRITE_DELAYS,
+ .type = SUNXI_DRAM_TYPE_LPDDR3,
+ .dx_read_delays = SUN50I_H6_LPDDR3_DX_READ_DELAYS,
+ .dx_write_delays = SUN50I_H6_LPDDR3_DX_WRITE_DELAYS,
#elif defined(CONFIG_SUNXI_DRAM_H6_DDR3_1333)
- .type = SUNXI_DRAM_TYPE_DDR3,
- .dx_read_delays = SUN50I_H6_DDR3_DX_READ_DELAYS,
- .dx_write_delays = SUN50I_H6_DDR3_DX_WRITE_DELAYS,
+ .type = SUNXI_DRAM_TYPE_DDR3,
+ .dx_read_delays = SUN50I_H6_DDR3_DX_READ_DELAYS,
+ .dx_write_delays = SUN50I_H6_DDR3_DX_WRITE_DELAYS,
#endif
- };
+};
+unsigned long sunxi_dram_init(void)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ void *const prcm = (void *)SUNXI_PRCM_BASE;
+ struct dram_config config;
unsigned long size;
- setbits_le32(&prcm->res_cal_ctrl, BIT(8));
- clrbits_le32(&prcm->ohms240, 0x3f);
+ setbits_le32(prcm + CCU_PRCM_RES_CAL_CTRL, BIT(8));
+ clrbits_le32(prcm + CCU_PRCM_OHMS240, 0x3f);
- mctl_auto_detect_rank_width(¶);
- mctl_auto_detect_dram_size(¶);
+ mctl_auto_detect_rank_width(¶, &config);
+ mctl_auto_detect_dram_size(¶, &config);
- mctl_core_init(¶);
+ mctl_core_init(¶, &config);
- size = mctl_calc_size(¶);
+ size = mctl_calc_size(&config);
clrsetbits_le32(&mctl_com->cr, 0xf0, (size >> (10 + 10 + 4)) & 0xf0);
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index cd9d321..5a59f82 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -17,6 +17,7 @@
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/dram.h>
+#include <asm/arch/dram_dw_helpers.h>
#include <asm/arch/cpu.h>
#include <asm/arch/prcm.h>
#include <linux/bitops.h>
@@ -93,34 +94,34 @@
static void mctl_sys_init(u32 clk_rate)
{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ void * const ccm = (void *)SUNXI_CCM_BASE;
struct sunxi_mctl_com_reg * const mctl_com =
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
/* Put all DRAM-related blocks to reset state */
- clrbits_le32(&ccm->mbus_cfg, MBUS_ENABLE);
- clrbits_le32(&ccm->mbus_cfg, MBUS_RESET);
- clrbits_le32(&ccm->dram_gate_reset, BIT(GATE_SHIFT));
+ clrbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_ENABLE);
+ clrbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_RESET);
+ clrbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(GATE_SHIFT));
udelay(5);
- clrbits_le32(&ccm->dram_gate_reset, BIT(RESET_SHIFT));
- clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
- clrbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);
+ clrbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(RESET_SHIFT));
+ clrbits_le32(ccm + CCU_H6_PLL5_CFG, CCM_PLL5_CTRL_EN);
+ clrbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_MOD_RESET);
udelay(5);
/* Set PLL5 rate to doubled DRAM clock rate */
writel(CCM_PLL5_CTRL_EN | CCM_PLL5_LOCK_EN | CCM_PLL5_OUT_EN |
- CCM_PLL5_CTRL_N(clk_rate * 2 / 24), &ccm->pll5_cfg);
- mctl_await_completion(&ccm->pll5_cfg, CCM_PLL5_LOCK, CCM_PLL5_LOCK);
+ CCM_PLL5_CTRL_N(clk_rate * 2 / 24), ccm + CCU_H6_PLL5_CFG);
+ mctl_await_completion(ccm + CCU_H6_PLL5_CFG,
+ CCM_PLL5_LOCK, CCM_PLL5_LOCK);
/* Configure DRAM mod clock */
- writel(DRAM_CLK_SRC_PLL5, &ccm->dram_clk_cfg);
- writel(BIT(RESET_SHIFT), &ccm->dram_gate_reset);
+ writel(DRAM_CLK_SRC_PLL5, ccm + CCU_H6_DRAM_CLK_CFG);
+ writel(BIT(RESET_SHIFT), ccm + CCU_H6_DRAM_GATE_RESET);
udelay(5);
- setbits_le32(&ccm->dram_gate_reset, BIT(GATE_SHIFT));
+ setbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(GATE_SHIFT));
/* Disable all channels */
writel(0, &mctl_com->maer0);
@@ -128,12 +129,12 @@
writel(0, &mctl_com->maer2);
/* Configure MBUS and enable DRAM mod reset */
- setbits_le32(&ccm->mbus_cfg, MBUS_RESET);
- setbits_le32(&ccm->mbus_cfg, MBUS_ENABLE);
+ setbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_RESET);
+ setbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_ENABLE);
clrbits_le32(&mctl_com->unk_0x500, BIT(25));
- setbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);
+ setbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_MOD_RESET);
udelay(5);
/* Unknown hack, which enables access of mctl_ctl regs */
@@ -1310,154 +1311,14 @@
return true;
}
-static bool mctl_core_init(const struct dram_para *para,
- const struct dram_config *config)
+bool mctl_core_init(const struct dram_para *para,
+ const struct dram_config *config)
{
mctl_sys_init(para->clk);
return mctl_ctrl_init(para, config);
}
-static void mctl_auto_detect_rank_width(const struct dram_para *para,
- struct dram_config *config)
-{
- /* this is minimum size that it's supported */
- config->cols = 8;
- config->rows = 13;
-
- /*
- * Strategy here is to test most demanding combination first and least
- * demanding last, otherwise HW might not be fully utilized. For
- * example, half bus width and rank = 1 combination would also work
- * on HW with full bus width and rank = 2, but only 1/4 RAM would be
- * visible.
- */
-
- debug("testing 32-bit width, rank = 2\n");
- config->bus_full_width = 1;
- config->ranks = 2;
- if (mctl_core_init(para, config))
- return;
-
- debug("testing 32-bit width, rank = 1\n");
- config->bus_full_width = 1;
- config->ranks = 1;
- if (mctl_core_init(para, config))
- return;
-
- debug("testing 16-bit width, rank = 2\n");
- config->bus_full_width = 0;
- config->ranks = 2;
- if (mctl_core_init(para, config))
- return;
-
- debug("testing 16-bit width, rank = 1\n");
- config->bus_full_width = 0;
- config->ranks = 1;
- if (mctl_core_init(para, config))
- return;
-
- panic("This DRAM setup is currently not supported.\n");
-}
-
-static void mctl_write_pattern(void)
-{
- unsigned int i;
- u32 *ptr, val;
-
- ptr = (u32 *)CFG_SYS_SDRAM_BASE;
- for (i = 0; i < 16; ptr++, i++) {
- if (i & 1)
- val = ~(ulong)ptr;
- else
- val = (ulong)ptr;
- writel(val, ptr);
- }
-}
-
-static bool mctl_check_pattern(ulong offset)
-{
- unsigned int i;
- u32 *ptr, val;
-
- ptr = (u32 *)CFG_SYS_SDRAM_BASE;
- for (i = 0; i < 16; ptr++, i++) {
- if (i & 1)
- val = ~(ulong)ptr;
- else
- val = (ulong)ptr;
- if (val != *(ptr + offset / 4))
- return false;
- }
-
- return true;
-}
-
-static void mctl_auto_detect_dram_size(const struct dram_para *para,
- struct dram_config *config)
-{
- unsigned int shift, cols, rows;
- u32 buffer[16];
-
- /* max. config for columns, but not rows */
- config->cols = 11;
- config->rows = 13;
- mctl_core_init(para, config);
-
- /*
- * Store content so it can be restored later. This is important
- * if controller was already initialized and holds any data
- * which is important for restoring system.
- */
- memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer));
-
- mctl_write_pattern();
-
- shift = config->bus_full_width + 1;
-
- /* detect column address bits */
- for (cols = 8; cols < 11; cols++) {
- if (mctl_check_pattern(1ULL << (cols + shift)))
- break;
- }
- debug("detected %u columns\n", cols);
-
- /* restore data */
- memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer));
-
- /* reconfigure to make sure that all active rows are accessible */
- config->cols = 8;
- config->rows = 17;
- mctl_core_init(para, config);
-
- /* store data again as it might be moved */
- memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer));
-
- mctl_write_pattern();
-
- /* detect row address bits */
- shift = config->bus_full_width + 4 + config->cols;
- for (rows = 13; rows < 17; rows++) {
- if (mctl_check_pattern(1ULL << (rows + shift)))
- break;
- }
- debug("detected %u rows\n", rows);
-
- /* restore data again */
- memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer));
-
- config->cols = cols;
- config->rows = rows;
-}
-
-static unsigned long mctl_calc_size(const struct dram_config *config)
-{
- u8 width = config->bus_full_width ? 4 : 2;
-
- /* 8 banks */
- return (1ULL << (config->cols + config->rows + 3)) * width * config->ranks;
-}
-
static const struct dram_para para = {
.clk = CONFIG_DRAM_CLK,
#ifdef CONFIG_SUNXI_DRAM_H616_DDR3_1333
@@ -1481,13 +1342,12 @@
unsigned long sunxi_dram_init(void)
{
- struct sunxi_prcm_reg *const prcm =
- (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+ void *const prcm = (void *)SUNXI_PRCM_BASE;
struct dram_config config;
unsigned long size;
- setbits_le32(&prcm->res_cal_ctrl, BIT(8));
- clrbits_le32(&prcm->ohms240, 0x3f);
+ setbits_le32(prcm + CCU_PRCM_RES_CAL_CTRL, BIT(8));
+ clrbits_le32(prcm + CCU_PRCM_OHMS240, 0x3f);
mctl_auto_detect_rank_width(¶, &config);
mctl_auto_detect_dram_size(¶, &config);
diff --git a/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c
index afe8e25..1ed46fe 100644
--- a/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c
+++ b/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c
@@ -37,7 +37,7 @@
};
/* TODO: flexible timing */
-void mctl_set_timing_params(struct dram_para *para)
+void mctl_set_timing_params(void)
{
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
diff --git a/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c b/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c
index c243b57..c02f542 100644
--- a/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c
+++ b/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c
@@ -16,7 +16,7 @@
};
/* TODO: flexible timing */
-void mctl_set_timing_params(struct dram_para *para)
+void mctl_set_timing_params(void)
{
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
diff --git a/arch/arm/mach-sunxi/rmr_switch.S b/arch/arm/mach-sunxi/rmr_switch.S
index 422007c..a6d75c3 100644
--- a/arch/arm/mach-sunxi/rmr_switch.S
+++ b/arch/arm/mach-sunxi/rmr_switch.S
@@ -49,10 +49,22 @@
str lr, [r0, #4]
mrs lr, CPSR
str lr, [r0, #8]
+ mrs lr, SP_irq
+ str lr, [r0, #20]
mrc p15, 0, lr, cr1, cr0, 0 // SCTLR
str lr, [r0, #12]
mrc p15, 0, lr, cr12, cr0, 0 // VBAR
str lr, [r0, #16]
+//#ifdef CONFIG_MACH_SUN55I_A523
+ mrc p15, 0, lr, cr12, cr12, 5 // ICC_SRE
+ tst lr, #1
+ beq 1f
+ mrc p15, 0, lr, c4, c6, 0 // ICC_PMR
+ str lr, [r0, #24]
+ mrc p15, 0, lr, c12, c12, 7 // ICC_IGRPEN1
+ str lr, [r0, #28]
+1:
+//#endif
ldr r1, =CONFIG_SUNXI_RVBAR_ADDRESS
ldr r0, =SUNXI_SRAMC_BASE
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index ebac347..2f0341b 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -16,7 +16,7 @@
obj-y += board.o board2.o
obj-y += cache.o
obj-$(CONFIG_TEGRA_CLKRST) += clock.o
-obj-$(CONFIG_$(XPL_)TEGRA_CRYPTO) += crypto.o
+obj-$(CONFIG_$(PHASE_)TEGRA_CRYPTO) += crypto.o
obj-$(CONFIG_TEGRA_PMC) += powergate.o
obj-y += xusb-padctl-dummy.o
diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c
index 7ca56a3..4835824 100644
--- a/arch/arm/mach-tegra/board.c
+++ b/arch/arm/mach-tegra/board.c
@@ -169,6 +169,8 @@
FUNCMUX_UART1_GPU,
#elif defined(CONFIG_TEGRA_UARTA_SDIO1)
FUNCMUX_UART1_SDIO1,
+ #elif defined(CONFIG_TEGRA_UARTA_SDB_SDD)
+ FUNCMUX_UART1_SDB_SDD,
#else
FUNCMUX_UART1_IRRX_IRTX,
#endif
@@ -236,18 +238,23 @@
int uart_ids = 0; /* bit mask of which UART ids to enable */
#ifdef CONFIG_TEGRA_ENABLE_UARTA
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
uart_ids |= UARTA;
#endif
#ifdef CONFIG_TEGRA_ENABLE_UARTB
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTB_BASE
uart_ids |= UARTB;
#endif
#ifdef CONFIG_TEGRA_ENABLE_UARTC
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTC_BASE
uart_ids |= UARTC;
#endif
#ifdef CONFIG_TEGRA_ENABLE_UARTD
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
uart_ids |= UARTD;
#endif
#ifdef CONFIG_TEGRA_ENABLE_UARTE
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTE_BASE
uart_ids |= UARTE;
#endif
setup_uarts(uart_ids);
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 6e9ef68..68534dc 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -96,7 +96,7 @@
{
int board_id = tegra_board_id();
- printf("Board: %s", CFG_TEGRA_BOARD_STRING);
+ printf("Board: %s", CONFIG_TEGRA_BOARD_STRING);
if (board_id != -1)
printf(", ID: %d\n", board_id);
printf("\n");
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index a375693..4f0cc19 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -703,6 +703,12 @@
else
writel(base_reg, &simple_pll->pll_base);
+ /* PLLD and PLLD2 are only clocks which have ENABLE bit */
+ if (clkid == CLOCK_ID_DISPLAY)
+ setbits_le32(&pll->pll_misc, BIT(PLLD_CLKENABLE));
+ if (clkid == CLOCK_ID_DISPLAY2)
+ setbits_le32(&simple_pll->pll_misc, BIT(PLLD_CLKENABLE));
+
/*
* Changing clocks was never intended in the U-Boot for Tegra.
* If a clock is changed after clock_init() the parent rate is wrong.
diff --git a/arch/arm/mach-tegra/tegra114/Kconfig b/arch/arm/mach-tegra/tegra114/Kconfig
index 5f0f909..98f1d0e 100644
--- a/arch/arm/mach-tegra/tegra114/Kconfig
+++ b/arch/arm/mach-tegra/tegra114/Kconfig
@@ -8,11 +8,21 @@
bool "NVIDIA Tegra114 Dalmore evaluation board"
select BOARD_LATE_INIT
+config TARGET_TEGRATAB
+ bool "NVIDIA Tegra114 TegraTab evaluation board"
+ select BOARD_LATE_INIT
+
+config TARGET_TRANSFORMER_T114
+ bool "ASUS Tegra114 Transformer board"
+ select BOARD_LATE_INIT
+
endchoice
config SYS_SOC
default "tegra114"
source "board/nvidia/dalmore/Kconfig"
+source "board/nvidia/tegratab/Kconfig"
+source "board/asus/transformer-t114/Kconfig"
endif
diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c
index d5cc8ac..d67d808 100644
--- a/arch/arm/mach-tegra/tegra114/clock.c
+++ b/arch/arm/mach-tegra/tegra114/clock.c
@@ -796,7 +796,6 @@
{ PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
{ PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
- { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
{ PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c
index 0ea212f..8a6735d 100644
--- a/arch/arm/mach-tegra/tegra124/clock.c
+++ b/arch/arm/mach-tegra/tegra124/clock.c
@@ -598,8 +598,8 @@
.lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
{ .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
.lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */
- { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
- .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */
+ { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0xF,
+ .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLD2 */
{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0xF,
.lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */
};
diff --git a/arch/arm/mach-tegra/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig
index e2735d9..a79fdc2 100644
--- a/arch/arm/mach-tegra/tegra20/Kconfig
+++ b/arch/arm/mach-tegra/tegra20/Kconfig
@@ -17,6 +17,9 @@
config TEGRA_UARTA_SDIO1
bool
+config TEGRA_UARTA_SDB_SDD
+ bool
+
choice
prompt "Tegra20 board select"
optional
@@ -29,6 +32,10 @@
bool "Avionic Design Medcom-Wide board"
select BOARD_LATE_INIT
+config TARGET_MOT
+ bool "Motorola Tegra20 board"
+ select BOARD_LATE_INIT
+
config TARGET_PAZ00
bool "Paz00 board"
select BOARD_LATE_INIT
@@ -76,6 +83,7 @@
source "board/nvidia/harmony/Kconfig"
source "board/avionic-design/medcom-wide/Kconfig"
+source "board/motorola/mot/Kconfig"
source "board/compal/paz00/Kconfig"
source "board/acer/picasso/Kconfig"
source "board/avionic-design/plutux/Kconfig"
diff --git a/arch/arm/mach-tegra/tegra20/Makefile b/arch/arm/mach-tegra/tegra20/Makefile
index 32c1866..a3ea759 100644
--- a/arch/arm/mach-tegra/tegra20/Makefile
+++ b/arch/arm/mach-tegra/tegra20/Makefile
@@ -3,7 +3,7 @@
# (C) Copyright 2010,2011 Nvidia Corporation.
obj-$(CONFIG_XPL_BUILD) += cpu.o
-obj-$(CONFIG_$(XPL_)CMD_EBTUPDATE) += bct.o
+obj-$(CONFIG_$(PHASE_)CMD_EBTUPDATE) += bct.o
# The AVP is ARMv4T architecture so we must use special compiler
# flags for any startup files it might use.
diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c
index 04708f9..d1ede52 100644
--- a/arch/arm/mach-tegra/tegra210/clock.c
+++ b/arch/arm/mach-tegra/tegra210/clock.c
@@ -668,8 +668,8 @@
.lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
{ .m_shift = 0, .m_mask = 0, .n_shift = 0, .n_mask = 0, .p_shift = 0, .p_mask = 0,
.lock_ena = 0, .lock_det = 0, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLS (gone)*/
- { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
- .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */
+ { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 19, .p_mask = 0x1F,
+ .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLD2 */
{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 19, .p_mask = 0x1F,
.lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */
};
diff --git a/arch/arm/mach-tegra/tegra30/Makefile b/arch/arm/mach-tegra/tegra30/Makefile
index b36657a..d635173 100644
--- a/arch/arm/mach-tegra/tegra30/Makefile
+++ b/arch/arm/mach-tegra/tegra30/Makefile
@@ -3,6 +3,6 @@
# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
obj-$(CONFIG_XPL_BUILD) += cpu.o
-obj-$(CONFIG_$(XPL_)CMD_EBTUPDATE) += bct.o
+obj-$(CONFIG_$(PHASE_)CMD_EBTUPDATE) += bct.o
obj-y += clock.o
diff --git a/arch/arm/mach-versal-net/Kconfig b/arch/arm/mach-versal-net/Kconfig
index 54fb93a..7def7b9 100644
--- a/arch/arm/mach-versal-net/Kconfig
+++ b/arch/arm/mach-versal-net/Kconfig
@@ -45,6 +45,5 @@
default 200000000
source "board/xilinx/Kconfig"
-source "board/xilinx/versal-net/Kconfig"
endif
diff --git a/arch/arm/mach-versal/Kconfig b/arch/arm/mach-versal/Kconfig
index 629a141..5ab901c 100644
--- a/arch/arm/mach-versal/Kconfig
+++ b/arch/arm/mach-versal/Kconfig
@@ -46,6 +46,5 @@
access to DDR memory where DDR is not present.
source "board/xilinx/Kconfig"
-source "board/xilinx/versal/Kconfig"
endif
diff --git a/arch/arm/mach-versal/include/mach/hardware.h b/arch/arm/mach-versal/include/mach/hardware.h
index 9d1c2f0..b5f80a8 100644
--- a/arch/arm/mach-versal/include/mach/hardware.h
+++ b/arch/arm/mach-versal/include/mach/hardware.h
@@ -87,6 +87,8 @@
#define JTAG_MODE 0x00000000
#define BOOT_MODE_USE_ALT 0x100
#define BOOT_MODE_ALT_SHIFT 12
+#define PMC_MULTI_BOOT_REG 0xF1110004
+#define PMC_MULTI_BOOT_MASK 0x1FFF
#define FLASH_RESET_GPIO 0xc
#define WPROT_CRP 0xF126001C
diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h
index 757bd87..a6dfa55 100644
--- a/arch/arm/mach-versal/include/mach/sys_proto.h
+++ b/arch/arm/mach-versal/include/mach/sys_proto.h
@@ -5,11 +5,11 @@
#include <linux/build_bug.h>
-enum {
- TCM_LOCK,
- TCM_SPLIT,
+enum tcm_mode {
+ TCM_LOCK = 0,
+ TCM_SPLIT = 1,
};
-void initialize_tcm(bool mode);
-void tcm_init(u8 mode);
+void initialize_tcm(enum tcm_mode mode);
+void tcm_init(enum tcm_mode mode);
void mem_map_fill(void);
diff --git a/arch/arm/mach-versal/mp.c b/arch/arm/mach-versal/mp.c
index 921ca49..7423b8d 100644
--- a/arch/arm/mach-versal/mp.c
+++ b/arch/arm/mach-versal/mp.c
@@ -24,7 +24,7 @@
#define VERSAL_CRL_RST_CPU_R5_RESET_PGE_MASK 0x10
#define VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK 0x1000000
-static void set_r5_halt_mode(u8 halt, u8 mode)
+static void set_r5_halt_mode(u8 halt, enum tcm_mode mode)
{
u32 tmp;
@@ -45,7 +45,7 @@
}
}
-static void set_r5_tcm_mode(u8 mode)
+static void set_r5_tcm_mode(enum tcm_mode mode)
{
u32 tmp;
@@ -63,7 +63,7 @@
writel(tmp, &rpu_base->rpu_glbl_ctrl);
}
-static void release_r5_reset(u8 mode)
+static void release_r5_reset(enum tcm_mode mode)
{
u32 tmp;
@@ -87,9 +87,9 @@
writel(tmp, &crlapb_base->cpu_r5_ctrl);
}
-void initialize_tcm(bool mode)
+void initialize_tcm(enum tcm_mode mode)
{
- if (!mode) {
+ if (mode == TCM_LOCK) {
set_r5_tcm_mode(TCM_LOCK);
set_r5_halt_mode(HALT, TCM_LOCK);
enable_clock_r5();
@@ -102,7 +102,7 @@
}
}
-void tcm_init(u8 mode)
+void tcm_init(enum tcm_mode mode)
{
puts("WARNING: Initializing TCM overwrites TCM content\n");
initialize_tcm(mode);
diff --git a/arch/arm/mach-versal2/Kconfig b/arch/arm/mach-versal2/Kconfig
index 3f18e33..2a59515 100644
--- a/arch/arm/mach-versal2/Kconfig
+++ b/arch/arm/mach-versal2/Kconfig
@@ -50,6 +50,5 @@
default 200000000
source "board/xilinx/Kconfig"
-source "board/amd/versal2/Kconfig"
endif
diff --git a/arch/arm/mach-versal2/include/mach/hardware.h b/arch/arm/mach-versal2/include/mach/hardware.h
index 15085f9..7ca2bbb 100644
--- a/arch/arm/mach-versal2/include/mach/hardware.h
+++ b/arch/arm/mach-versal2/include/mach/hardware.h
@@ -68,6 +68,7 @@
#define USB_MODE 0x00000007
#define OSPI_MODE 0x00000008
#define SELECTMAP_MODE 0x0000000A
+#define UFS_MODE 0x0000000B
#define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */
#define JTAG_MODE 0x00000000
#define BOOT_MODE_USE_ALT 0x100
@@ -96,3 +97,9 @@
#define MIO_PIN_12 0xF1060030
#define BANK0_OUTPUT 0xF1020040
#define BANK0_TRI 0xF1060200
+
+#define PMXC_EFUSE_CACHE_BASE_ADDRESS 0xF1250000
+#define PMXC_SLCR_BASE_ADDRESS 0xF1061000
+#define PMXC_UFS_CAL_1_OFFSET 0xBE8
+#define PMXC_SRAM_CSR 0x4C
+#define PMXC_TX_RX_CFG_RDY 0x54
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index 376d1bc..c3f505f 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -58,5 +58,6 @@
source "board/xilinx/Kconfig"
source "board/xilinx/zynq/Kconfig"
+source "board/BuR/zynq/Kconfig"
endif
diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile
index ff42604..4bd4014 100644
--- a/arch/arm/mach-zynqmp/Makefile
+++ b/arch/arm/mach-zynqmp/Makefile
@@ -7,7 +7,7 @@
obj-$(CONFIG_MP) += mp.o
obj-$(CONFIG_XPL_BUILD) += spl.o handoff.o psu_spl_init.o
obj-$(CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT) += ecc_spl_init.o
-obj-$(CONFIG_$(XPL_)ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o
+obj-$(CONFIG_$(PHASE_)ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o
ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_CMD_ZYNQMP) += zynqmp.o
diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c
index 960ffac..b7a4142 100644
--- a/arch/arm/mach-zynqmp/cpu.c
+++ b/arch/arm/mach-zynqmp/cpu.c
@@ -113,7 +113,7 @@
}
#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
-void tcm_init(u8 mode)
+void tcm_init(enum tcm_mode mode)
{
int ret;
diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
index 9af3ab5..b6a41df 100644
--- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h
+++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
@@ -41,18 +41,18 @@
ZYNQMP_SILICON_V4,
};
-enum {
- TCM_LOCK,
- TCM_SPLIT,
+enum tcm_mode {
+ TCM_LOCK = 0,
+ TCM_SPLIT = 1,
};
unsigned int zynqmp_get_silicon_version(void);
-int check_tcm_mode(bool mode);
-void initialize_tcm(bool mode);
+int check_tcm_mode(enum tcm_mode mode);
+void initialize_tcm(enum tcm_mode mode);
void mem_map_fill(void);
#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
-void tcm_init(u8 mode);
+void tcm_init(enum tcm_mode mode);
#endif
#endif /* _ASM_ARCH_SYS_PROTO_H */
diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c
index 448bc53..d2a7f30 100644
--- a/arch/arm/mach-zynqmp/mp.c
+++ b/arch/arm/mach-zynqmp/mp.c
@@ -17,9 +17,6 @@
#include <linux/errno.h>
#include <linux/string.h>
-#define LOCK 0
-#define SPLIT 1
-
#define HALT 0
#define RELEASE 1
@@ -65,11 +62,11 @@
return 0;
}
-static void set_r5_halt_mode(u32 nr, u8 halt, u8 mode)
+static void set_r5_halt_mode(u32 nr, u8 halt, enum tcm_mode mode)
{
u32 tmp;
- if (mode == LOCK || nr == ZYNQMP_CORE_RPU0) {
+ if (mode == TCM_LOCK || nr == ZYNQMP_CORE_RPU0) {
tmp = readl(&rpu_base->rpu0_cfg);
if (halt == HALT)
tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;
@@ -78,7 +75,7 @@
writel(tmp, &rpu_base->rpu0_cfg);
}
- if (mode == LOCK || nr == ZYNQMP_CORE_RPU1) {
+ if (mode == TCM_LOCK || nr == ZYNQMP_CORE_RPU1) {
tmp = readl(&rpu_base->rpu1_cfg);
if (halt == HALT)
tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;
@@ -88,12 +85,12 @@
}
}
-static void set_r5_tcm_mode(u8 mode)
+static void set_r5_tcm_mode(enum tcm_mode mode)
{
u32 tmp;
tmp = readl(&rpu_base->rpu_glbl_ctrl);
- if (mode == LOCK) {
+ if (mode == TCM_LOCK) {
tmp &= ~ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
tmp |= ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK |
ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK;
@@ -106,12 +103,12 @@
writel(tmp, &rpu_base->rpu_glbl_ctrl);
}
-static void set_r5_reset(u32 nr, u8 mode)
+static void set_r5_reset(u32 nr, enum tcm_mode mode)
{
u32 tmp;
tmp = readl(&crlapb_base->rst_lpd_top);
- if (mode == LOCK) {
+ if (mode == TCM_LOCK) {
tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK |
ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK);
@@ -130,16 +127,16 @@
writel(tmp, &crlapb_base->rst_lpd_top);
}
-static void release_r5_reset(u32 nr, u8 mode)
+static void release_r5_reset(u32 nr, enum tcm_mode mode)
{
u32 tmp;
tmp = readl(&crlapb_base->rst_lpd_top);
- if (mode == LOCK || nr == ZYNQMP_CORE_RPU0)
+ if (mode == TCM_LOCK || nr == ZYNQMP_CORE_RPU0)
tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK);
- if (mode == LOCK || nr == ZYNQMP_CORE_RPU1)
+ if (mode == TCM_LOCK || nr == ZYNQMP_CORE_RPU1)
tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK);
@@ -165,9 +162,9 @@
tmp = readl(&rpu_base->rpu_glbl_ctrl);
if (tmp & ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK)
- return SPLIT;
+ return TCM_SPLIT;
- return LOCK;
+ return TCM_LOCK;
}
int cpu_disable(u32 nr)
@@ -249,27 +246,27 @@
}
}
-void initialize_tcm(bool mode)
+void initialize_tcm(enum tcm_mode mode)
{
- if (!mode) {
- set_r5_tcm_mode(LOCK);
- set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, LOCK);
+ if (mode == TCM_LOCK) {
+ set_r5_tcm_mode(TCM_LOCK);
+ set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, TCM_LOCK);
enable_clock_r5();
- release_r5_reset(ZYNQMP_CORE_RPU0, LOCK);
+ release_r5_reset(ZYNQMP_CORE_RPU0, TCM_LOCK);
} else {
- set_r5_tcm_mode(SPLIT);
- set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, SPLIT);
- set_r5_halt_mode(ZYNQMP_CORE_RPU1, HALT, SPLIT);
+ set_r5_tcm_mode(TCM_SPLIT);
+ set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, TCM_SPLIT);
+ set_r5_halt_mode(ZYNQMP_CORE_RPU1, HALT, TCM_SPLIT);
enable_clock_r5();
- release_r5_reset(ZYNQMP_CORE_RPU0, SPLIT);
- release_r5_reset(ZYNQMP_CORE_RPU1, SPLIT);
+ release_r5_reset(ZYNQMP_CORE_RPU0, TCM_SPLIT);
+ release_r5_reset(ZYNQMP_CORE_RPU1, TCM_SPLIT);
}
}
-int check_tcm_mode(bool mode)
+int check_tcm_mode(enum tcm_mode mode)
{
u32 tmp, cpu_state;
- bool mode_prev;
+ enum tcm_mode mode_prev;
tmp = readl(&rpu_base->rpu_glbl_ctrl);
mode_prev = FIELD_GET(ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK, tmp);
@@ -279,7 +276,7 @@
ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK, tmp);
cpu_state = cpu_state ? false : true;
- if ((mode_prev == SPLIT && mode == LOCK) && cpu_state)
+ if ((mode_prev == TCM_SPLIT && mode == TCM_LOCK) && cpu_state)
return -EACCES;
if (mode_prev == mode)
@@ -288,11 +285,11 @@
return 0;
}
-static void mark_r5_used(u32 nr, u8 mode)
+static void mark_r5_used(u32 nr, enum tcm_mode mode)
{
u32 mask = 0;
- if (mode == LOCK) {
+ if (mode == TCM_LOCK) {
mask = ZYNQMP_RPU0_USE_MASK | ZYNQMP_RPU1_USE_MASK;
} else {
switch (nr) {
@@ -358,30 +355,30 @@
return 1;
}
printf("R5 lockstep mode\n");
- set_r5_reset(nr, LOCK);
- set_r5_tcm_mode(LOCK);
- set_r5_halt_mode(nr, HALT, LOCK);
+ set_r5_reset(nr, TCM_LOCK);
+ set_r5_tcm_mode(TCM_LOCK);
+ set_r5_halt_mode(nr, HALT, TCM_LOCK);
set_r5_start(boot_addr);
enable_clock_r5();
- release_r5_reset(nr, LOCK);
+ release_r5_reset(nr, TCM_LOCK);
dcache_disable();
write_tcm_boot_trampoline(nr, boot_addr_uniq);
dcache_enable();
- set_r5_halt_mode(nr, RELEASE, LOCK);
- mark_r5_used(nr, LOCK);
+ set_r5_halt_mode(nr, RELEASE, TCM_LOCK);
+ mark_r5_used(nr, TCM_LOCK);
} else if (!strcmp(argv[1], "split") || !strcmp(argv[1], "1")) {
printf("R5 split mode\n");
- set_r5_reset(nr, SPLIT);
- set_r5_tcm_mode(SPLIT);
- set_r5_halt_mode(nr, HALT, SPLIT);
+ set_r5_reset(nr, TCM_SPLIT);
+ set_r5_tcm_mode(TCM_SPLIT);
+ set_r5_halt_mode(nr, HALT, TCM_SPLIT);
set_r5_start(boot_addr);
enable_clock_r5();
- release_r5_reset(nr, SPLIT);
+ release_r5_reset(nr, TCM_SPLIT);
dcache_disable();
write_tcm_boot_trampoline(nr, boot_addr_uniq);
dcache_enable();
- set_r5_halt_mode(nr, RELEASE, SPLIT);
- mark_r5_used(nr, SPLIT);
+ set_r5_halt_mode(nr, RELEASE, TCM_SPLIT);
+ mark_r5_used(nr, TCM_SPLIT);
} else {
printf("Unsupported mode\n");
return 1;
diff --git a/arch/arm/mach-zynqmp/zynqmp.c b/arch/arm/mach-zynqmp/zynqmp.c
index 3aa2185..279006b 100644
--- a/arch/arm/mach-zynqmp/zynqmp.c
+++ b/arch/arm/mach-zynqmp/zynqmp.c
@@ -146,7 +146,7 @@
static int do_zynqmp_tcm_init(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
- u8 mode;
+ enum tcm_mode mode;
if (argc != cmdtp->maxargs)
return CMD_RET_USAGE;
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 7ea439e..a031701 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -146,7 +146,35 @@
select SUPPORTS_CPU_MIPS64_R6
select SUPPORT_BIG_ENDIAN
select SUPPORT_LITTLE_ENDIAN
+ imply OF_UPSTREAM
+ imply BOOTSTD_FULL
+ imply CLK
+ imply CLK_BOSTON
imply CMD_DM
+ imply AHCI
+ imply AHCI_PCI
+ imply CFI_FLASH
+ imply MTD_NOR_FLASH
+ imply MMC
+ imply MMC_PCI
+ imply MMC_SDHCI
+ imply MMC_SDHCI_SDMA
+ imply PCH_GBE
+ imply PCI
+ imply PCI_XILINX
+ imply PCI_INIT_R
+ imply SCSI
+ imply SCSI_AHCI
+ imply SYS_NS16550
+ imply SYSRESET
+ imply SYSRESET_CMD_POWEROFF
+ imply SYSRESET_SYSCON
+ imply USB
+ imply USB_EHCI_HCD
+ imply USB_EHCI_PCI
+ imply USB_XHCI_HCD
+ imply USB_XHCI_PCI
+ imply CMD_USB
config TARGET_XILFPGA
bool "Support Imagination Xilfpga"
@@ -322,6 +350,7 @@
config MIPS_RELOCATION_TABLE_SIZE
hex "Relocation table size"
range 0x100 0x10000
+ default "0xc000" if TARGET_MALTA
default "0x8000"
---help---
A table of relocation data will be appended to the U-Boot binary
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 752e771..7c4ee8b 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -3,7 +3,6 @@
dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
dtb-$(CONFIG_TARGET_AP143) += ap143.dtb
dtb-$(CONFIG_TARGET_AP152) += ap152.dtb
-dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb
dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb
diff --git a/arch/mips/dts/boston-u-boot.dtsi b/arch/mips/dts/boston-u-boot.dtsi
new file mode 100644
index 0000000..1b0c0a28
--- /dev/null
+++ b/arch/mips/dts/boston-u-boot.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+&plat_regs {
+ compatible = "img,boston-platform-regs", "syscon", "simple-mfd";
+ bootph-all;
+};
+
+&clk_boston {
+ bootph-all;
+};
diff --git a/arch/mips/dts/img,boston.dts b/arch/mips/dts/img,boston.dts
deleted file mode 100644
index c1a7396..0000000
--- a/arch/mips/dts/img,boston.dts
+++ /dev/null
@@ -1,222 +0,0 @@
-/dts-v1/;
-
-#include <dt-bindings/clock/boston-clock.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/mips-gic.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "img,boston";
-
- chosen {
- stdout-path = &uart0;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- compatible = "img,mips";
- reg = <0>;
- clocks = <&clk_boston BOSTON_CLK_CPU>;
- };
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x00000000 0x10000000>;
- };
-
- gic: interrupt-controller {
- compatible = "mti,gic";
-
- interrupt-controller;
- #interrupt-cells = <3>;
-
- timer {
- compatible = "mti,gic-timer";
- interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
- clocks = <&clk_boston BOSTON_CLK_CPU>;
- };
- };
-
- pci0: pci@10000000 {
- status = "disabled";
- compatible = "xlnx,axi-pcie-host-1.00.a";
- device_type = "pci";
- reg = <0x10000000 0x2000000>;
-
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
-
- interrupt-parent = <&gic>;
- interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;
-
- ranges = <0x02000000 0 0x40000000
- 0x40000000 0 0x40000000>;
-
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pci0_intc 0>,
- <0 0 0 2 &pci0_intc 1>,
- <0 0 0 3 &pci0_intc 2>,
- <0 0 0 4 &pci0_intc 3>;
-
- pci0_intc: interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- };
- };
-
- pci1: pci@12000000 {
- status = "disabled";
- compatible = "xlnx,axi-pcie-host-1.00.a";
- device_type = "pci";
- reg = <0x12000000 0x2000000>;
-
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
-
- interrupt-parent = <&gic>;
- interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>;
-
- ranges = <0x02000000 0 0x20000000
- 0x20000000 0 0x20000000>;
-
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pci1_intc 0>,
- <0 0 0 2 &pci1_intc 1>,
- <0 0 0 3 &pci1_intc 2>,
- <0 0 0 4 &pci1_intc 3>;
-
- pci1_intc: interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- };
- };
-
- pci2: pci@14000000 {
- compatible = "xlnx,axi-pcie-host-1.00.a";
- device_type = "pci";
- reg = <0x14000000 0x2000000>;
-
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
-
- interrupt-parent = <&gic>;
- interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>;
-
- ranges = <0x02000000 0 0x16000000
- 0x16000000 0 0x100000>;
-
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pci2_intc 0>,
- <0 0 0 2 &pci2_intc 1>,
- <0 0 0 3 &pci2_intc 2>,
- <0 0 0 4 &pci2_intc 3>;
-
- pci2_intc: interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- };
-
- pci2_root@0,0,0 {
- compatible = "pci10ee,7021";
- reg = <0x00000000 0 0 0 0>;
-
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
-
- eg20t_bridge@1,0,0 {
- compatible = "pci8086,8800";
- reg = <0x00010000 0 0 0 0>;
-
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
-
- eg20t_mac@2,0,1 {
- compatible = "pci8086,8802";
- reg = <0x00020100 0 0 0 0>;
- phy-reset-gpios = <&eg20t_gpio 6 GPIO_ACTIVE_LOW>;
- };
-
- eg20t_gpio: eg20t_gpio@2,0,2 {
- compatible = "pci8086,8803";
- reg = <0x00020200 0 0 0 0>;
-
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- eg20t_i2c@2,12,2 {
- compatible = "pci8086,8817";
- reg = <0x00026200 0 0 0 0>;
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- rtc@0x68 {
- compatible = "st,m41t81s";
- reg = <0x68>;
- };
- };
- };
- };
- };
-
- plat_regs: system-controller@17ffd000 {
- compatible = "img,boston-platform-regs", "syscon";
- reg = <0x17ffd000 0x1000>;
- bootph-all;
- };
-
- clk_boston: clock {
- compatible = "img,boston-clock";
- #clock-cells = <1>;
- regmap = <&plat_regs>;
- bootph-all;
- };
-
- reboot: syscon-reboot {
- compatible = "syscon-reboot";
- regmap = <&plat_regs>;
- offset = <0x10>;
- mask = <0x10>;
- };
-
- uart0: uart@17ffe000 {
- compatible = "ns16550a";
- reg = <0x17ffe000 0x1000>;
- reg-shift = <2>;
- reg-io-width = <4>;
-
- interrupt-parent = <&gic>;
- interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
-
- clocks = <&clk_boston BOSTON_CLK_SYS>;
-
- bootph-all;
- };
-
- lcd: lcd@17fff000 {
- compatible = "img,boston-lcd";
- reg = <0x17fff000 0x8>;
- };
-
- flash@18000000 {
- compatible = "cfi-flash";
- reg = <0x18000000 0x8000000>;
- bank-width = <2>;
- };
-};
diff --git a/arch/mips/include/asm/acpi_table.h b/arch/mips/include/asm/acpi_table.h
new file mode 100644
index 0000000..b4139d0
--- /dev/null
+++ b/arch/mips/include/asm/acpi_table.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __ASM_ACPI_TABLE_H__
+#define __ASM_ACPI_TABLE_H__
+
+/*
+ * This file is needed by some drivers.
+ */
+
+#endif /* __ASM_ACPI_TABLE_H__ */
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 4e6f347..6f80f4a 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -48,7 +48,7 @@
ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
-mcmodel=$(CMODEL)
-ifeq ($(CONFIG_$(XPL_)FRAMEPOINTER),y)
+ifeq ($(CONFIG_$(PHASE_)FRAMEPOINTER),y)
ARCH_FLAGS += -fno-omit-frame-pointer
endif
diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds
index 9070946..0717833 100644
--- a/arch/riscv/cpu/u-boot-spl.lds
+++ b/arch/riscv/cpu/u-boot-spl.lds
@@ -16,6 +16,7 @@
SECTIONS
{
. = ALIGN(4);
+ __image_copy_start = ADDR(.text);
.text : {
arch/riscv/cpu/start.o (.text)
*(.text*)
@@ -46,6 +47,7 @@
_end = .;
_image_binary_end = .;
+ __image_copy_end = .;
.bss : {
__bss_start = .;
diff --git a/arch/riscv/cpu/u-boot.lds b/arch/riscv/cpu/u-boot.lds
index 2ffe6ba..b11ea8b 100644
--- a/arch/riscv/cpu/u-boot.lds
+++ b/arch/riscv/cpu/u-boot.lds
@@ -10,6 +10,7 @@
SECTIONS
{
. = ALIGN(4);
+ __image_copy_start = ADDR(.text);
.text : {
arch/riscv/cpu/start.o (.text)
}
@@ -57,6 +58,8 @@
__efi_runtime_rel_stop = .;
}
+ __image_copy_end = .;
+
/DISCARD/ : { *(.rela.plt*) }
.rela.dyn : {
__rel_dyn_start = .;
diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi
index ceb916b..5aeeedd 100644
--- a/arch/riscv/dts/binman.dtsi
+++ b/arch/riscv/dts/binman.dtsi
@@ -35,7 +35,7 @@
compression = "none";
load = /bits/ 64 <CONFIG_TEXT_BASE>;
- uboot_blob: blob-ext {
+ uboot_blob: u-boot-nodtb {
filename = "u-boot-nodtb.bin";
};
};
diff --git a/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi b/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi
new file mode 100644
index 0000000..ab882d0
--- /dev/null
+++ b/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ */
+
+#include "jh7110-common-u-boot.dtsi"
+#include "starfive-visionfive2-binman.dtsi"
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
index ce7d9e1..a9e318c 100644
--- a/arch/riscv/dts/jh7110-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -102,6 +102,10 @@
bootph-pre-ram;
};
+&pllclk {
+ bootph-pre-ram;
+};
+
&syscrg {
bootph-pre-ram;
};
diff --git a/arch/riscv/dts/k1-bananapi-f3.dts b/arch/riscv/dts/k1-bananapi-f3.dts
index d2486f7..6b5b83b 100644
--- a/arch/riscv/dts/k1-bananapi-f3.dts
+++ b/arch/riscv/dts/k1-bananapi-f3.dts
@@ -5,6 +5,7 @@
#include "k1.dtsi"
#include "binman.dtsi"
+#include "k1-pinctrl.dtsi"
/ {
model = "Banana Pi BPI-F3";
@@ -21,5 +22,7 @@
};
&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_2_cfg>;
status = "okay";
};
diff --git a/arch/riscv/dts/k1-pinctrl.dtsi b/arch/riscv/dts/k1-pinctrl.dtsi
new file mode 100644
index 0000000..14e7096
--- /dev/null
+++ b/arch/riscv/dts/k1-pinctrl.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 Spacemit Inc.
+ * Copyright (C) 2025 Yixun Lan <dlan@gentoo.org>
+ */
+
+#define K1_PADCONF(pin, func) (((pin) << 16) | (func))
+
+&pinctrl {
+ uart0_2_cfg: uart0-2-cfg {
+ uart0-2-pins {
+ pinmux = <K1_PADCONF(68, 2)>,
+ <K1_PADCONF(69, 2)>;
+
+ bias-pull-up = <0>;
+ drive-strength = <32>;
+ };
+ };
+};
diff --git a/arch/riscv/dts/k1.dtsi b/arch/riscv/dts/k1.dtsi
index 7c0f1b9..a633e43 100644
--- a/arch/riscv/dts/k1.dtsi
+++ b/arch/riscv/dts/k1.dtsi
@@ -470,5 +470,11 @@
#reset-cells = <1>;
status = "disabled";
};
+
+ pinctrl: pinctrl@d401e000 {
+ compatible = "spacemit,k1-pinctrl", "pinctrl-single";
+ reg = <0x0 0xd401e000 0x0 0x400>;
+ pinctrl-single,register-width = <32>;
+ };
};
-};
\ No newline at end of file
+};
diff --git a/arch/riscv/dts/starfive-visionfive2-binman.dtsi b/arch/riscv/dts/starfive-visionfive2-binman.dtsi
index 05787bd..6e083bf 100644
--- a/arch/riscv/dts/starfive-visionfive2-binman.dtsi
+++ b/arch/riscv/dts/starfive-visionfive2-binman.dtsi
@@ -20,6 +20,7 @@
args = "-T sfspl";
u-boot-spl {
+ no-write-symbols;
};
};
};
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 268116f..189b35c 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -11,22 +11,23 @@
obj-$(CONFIG_CMD_GO) += boot.o
obj-y += cache.o
obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
-ifeq ($(CONFIG_$(XPL_)RISCV_MMODE),y)
-obj-$(CONFIG_$(XPL_)RISCV_ACLINT) += aclint_ipi.o
+ifeq ($(CONFIG_$(PHASE_)RISCV_MMODE),y)
+obj-$(CONFIG_$(PHASE_)RISCV_ACLINT) += aclint_ipi.o
obj-$(CONFIG_ANDES_PLICSW) += andes_plicsw.o
else
obj-$(CONFIG_SBI) += sbi.o
obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
endif
obj-y += interrupts.o
-ifeq ($(CONFIG_$(XPL_)SYSRESET),)
+ifeq ($(CONFIG_$(PHASE_)SYSRESET),)
obj-y += reset.o
endif
obj-y += setjmp.o
-obj-$(CONFIG_$(XPL_)SMP) += smp.o
+obj-$(CONFIG_$(PHASE_)SMP) += smp.o
obj-$(CONFIG_XPL_BUILD) += spl.o
obj-y += fdt_fixup.o
obj-$(CONFIG_$(SPL)CMD_BDI) += bdinfo.o
+obj-$(CONFIG_OF_BOARD) += board.o
# For building EFI apps
CFLAGS_NON_EFI := -fstack-protector-strong
diff --git a/arch/riscv/lib/board.c b/arch/riscv/lib/board.c
new file mode 100644
index 0000000..624c4ea
--- /dev/null
+++ b/arch/riscv/lib/board.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * RISC-V-specific handling of firmware FDT
+ */
+
+#include <asm/global_data.h>
+#include <linux/errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak int board_fdt_blob_setup(void **fdtp)
+{
+ if (!gd->arch.firmware_fdt_addr)
+ return -EEXIST;
+
+ *fdtp = (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
+
+ return 0;
+}
diff --git a/arch/riscv/lib/setjmp.S b/arch/riscv/lib/setjmp.S
index 99d6195..9e1f3d5 100644
--- a/arch/riscv/lib/setjmp.S
+++ b/arch/riscv/lib/setjmp.S
@@ -59,3 +59,14 @@
ret
ENDPROC(longjmp)
.popsection
+
+.pushsection .text.initjmp, "ax"
+ENTRY(initjmp)
+ /* a1: entry point address, a2: stack base, a3: stack size */
+ add a2, a2, a3
+ STORE_IDX(a1, 12)
+ STORE_IDX(a2, 13)
+ li a0, 0
+ ret
+ENDPROC(initjmp)
+.popsection
diff --git a/arch/sandbox/cpu/Makefile b/arch/sandbox/cpu/Makefile
index bfcdc33..038ad78 100644
--- a/arch/sandbox/cpu/Makefile
+++ b/arch/sandbox/cpu/Makefile
@@ -5,7 +5,7 @@
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-obj-y := cache.o cpu.o state.o
+obj-y := cache.o cpu.o state.o initjmp.o
extra-y := start.o os.o
extra-$(CONFIG_SANDBOX_SDL) += sdl.o
obj-$(CONFIG_XPL_BUILD) += spl.o
@@ -29,6 +29,15 @@
$(obj)/eth-raw-os.o: $(src)/eth-raw-os.c FORCE
$(call if_changed_dep,cc_eth-raw-os.o)
+# initjmp.c is build in the system environment, so needs standard includes
+# CFLAGS_REMOVE_initjmp.o cannot be used to drop header include path
+quiet_cmd_cc_initjmp.o = CC $(quiet_modtag) $@
+cmd_cc_initjmp.o = $(CC) $(filter-out -nostdinc, \
+ $(patsubst -I%,-idirafter%,$(c_flags))) -c -o $@ $<
+
+$(obj)/initjmp.o: $(src)/initjmp.c FORCE
+ $(call if_changed_dep,cc_initjmp.o)
+
# sdl.c fails to build with -fshort-wchar using musl
cmd_cc_sdl.o = $(CC) $(filter-out -nostdinc -fshort-wchar, \
$(patsubst -I%,-idirafter%,$(c_flags))) -fno-lto -c -o $@ $<
diff --git a/arch/sandbox/cpu/initjmp.c b/arch/sandbox/cpu/initjmp.c
new file mode 100644
index 0000000..6e72d32
--- /dev/null
+++ b/arch/sandbox/cpu/initjmp.c
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: LGPL-2.1-or-later
+/*
+ * An implementation of initjmp() in C, that plays well with the system's
+ * setjmp() and longjmp() functions.
+ * Taken verbatim from arch/sandbox/os/setjmp.c in the barebox project.
+ * Modified so that initjmp() accepts a stack_size argument.
+ *
+ * Copyright (C) 2006 Anthony Liguori <anthony@codemonkey.ws>
+ * Copyright (C) 2011 Kevin Wolf <kwolf@redhat.com>
+ * Copyright (C) 2012 Alex Barcelo <abarcelo@ac.upc.edu>
+ * Copyright (C) 2021 Ahmad Fatoum, Pengutronix
+ * Copyright (C) 2025 Linaro Ltd.
+ * This file is partly based on pth_mctx.c, from the GNU Portable Threads
+ * Copyright (c) 1999-2006 Ralf S. Engelschall <rse@engelschall.com>
+ */
+
+/* XXX Is there a nicer way to disable glibc's stack check for longjmp? */
+#ifdef _FORTIFY_SOURCE
+#undef _FORTIFY_SOURCE
+#endif
+
+#include <pthread.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <setjmp.h>
+#include <signal.h>
+
+typedef sigjmp_buf _jmp_buf __attribute__((aligned((16))));
+_Static_assert(sizeof(_jmp_buf) <= 512, "sigjmp_buf size exceeds expectation");
+
+/*
+ * Information for the signal handler (trampoline)
+ */
+static struct {
+ _jmp_buf *reenter;
+ void (*entry)(void);
+ volatile sig_atomic_t called;
+} tr_state;
+
+/*
+ * "boot" function
+ * This is what starts the coroutine, is called from the trampoline
+ * (from the signal handler when it is not signal handling, read ahead
+ * for more information).
+ */
+static void __attribute__((noinline, noreturn))
+coroutine_bootstrap(void (*entry)(void))
+{
+ for (;;)
+ entry();
+}
+
+/*
+ * This is used as the signal handler. This is called with the brand new stack
+ * (thanks to sigaltstack). We have to return, given that this is a signal
+ * handler and the sigmask and some other things are changed.
+ */
+static void coroutine_trampoline(int signal)
+{
+ /* Get the thread specific information */
+ tr_state.called = 1;
+
+ /*
+ * Here we have to do a bit of a ping pong between the caller, given that
+ * this is a signal handler and we have to do a return "soon". Then the
+ * caller can reestablish everything and do a siglongjmp here again.
+ */
+ if (!sigsetjmp(*tr_state.reenter, 0)) {
+ return;
+ }
+
+ /*
+ * Ok, the caller has siglongjmp'ed back to us, so now prepare
+ * us for the real machine state switching. We have to jump
+ * into another function here to get a new stack context for
+ * the auto variables (which have to be auto-variables
+ * because the start of the thread happens later). Else with
+ * PIC (i.e. Position Independent Code which is used when PTH
+ * is built as a shared library) most platforms would
+ * horrible core dump as experience showed.
+ */
+ coroutine_bootstrap(tr_state.entry);
+}
+
+int __attribute__((weak)) initjmp(_jmp_buf jmp, void (*func)(void),
+ void *stack_base, size_t stack_size)
+{
+ struct sigaction sa;
+ struct sigaction osa;
+ stack_t ss;
+ stack_t oss;
+ sigset_t sigs;
+ sigset_t osigs;
+
+ /* The way to manipulate stack is with the sigaltstack function. We
+ * prepare a stack, with it delivering a signal to ourselves and then
+ * put sigsetjmp/siglongjmp where needed.
+ * This has been done keeping coroutine-ucontext (from the QEMU project)
+ * as a model and with the pth ideas (GNU Portable Threads).
+ * See coroutine-ucontext for the basics of the coroutines and see
+ * pth_mctx.c (from the pth project) for the
+ * sigaltstack way of manipulating stacks.
+ */
+
+ tr_state.entry = func;
+ tr_state.reenter = (void *)jmp;
+
+ /*
+ * Preserve the SIGUSR2 signal state, block SIGUSR2,
+ * and establish our signal handler. The signal will
+ * later transfer control onto the signal stack.
+ */
+ sigemptyset(&sigs);
+ sigaddset(&sigs, SIGUSR2);
+ pthread_sigmask(SIG_BLOCK, &sigs, &osigs);
+ sa.sa_handler = coroutine_trampoline;
+ sigfillset(&sa.sa_mask);
+ sa.sa_flags = SA_ONSTACK;
+ if (sigaction(SIGUSR2, &sa, &osa) != 0) {
+ return -1;
+ }
+
+ /*
+ * Set the new stack.
+ */
+ ss.ss_sp = stack_base;
+ ss.ss_size = stack_size;
+ ss.ss_flags = 0;
+ if (sigaltstack(&ss, &oss) < 0) {
+ return -1;
+ }
+
+ /*
+ * Now transfer control onto the signal stack and set it up.
+ * It will return immediately via "return" after the sigsetjmp()
+ * was performed. Be careful here with race conditions. The
+ * signal can be delivered the first time sigsuspend() is
+ * called.
+ */
+ tr_state.called = 0;
+ pthread_kill(pthread_self(), SIGUSR2);
+ sigfillset(&sigs);
+ sigdelset(&sigs, SIGUSR2);
+ while (!tr_state.called) {
+ sigsuspend(&sigs);
+ }
+
+ /*
+ * Inform the system that we are back off the signal stack by
+ * removing the alternative signal stack. Be careful here: It
+ * first has to be disabled, before it can be removed.
+ */
+ sigaltstack(NULL, &ss);
+ ss.ss_flags = SS_DISABLE;
+ if (sigaltstack(&ss, NULL) < 0) {
+ return -1;
+ }
+ sigaltstack(NULL, &ss);
+ if (!(oss.ss_flags & SS_DISABLE)) {
+ sigaltstack(&oss, NULL);
+ }
+
+ /*
+ * Restore the old SIGUSR2 signal handler and mask
+ */
+ sigaction(SIGUSR2, &osa, NULL);
+ pthread_sigmask(SIG_SETMASK, &osigs, NULL);
+
+ /*
+ * jmp can now be used to enter the trampoline again, but not as a
+ * signal handler. Instead it's longjmp'd to directly.
+ */
+ return 0;
+}
+
diff --git a/arch/sandbox/include/asm/power-domain.h b/arch/sandbox/include/asm/power-domain.h
index 4d5e861..3b0717f 100644
--- a/arch/sandbox/include/asm/power-domain.h
+++ b/arch/sandbox/include/asm/power-domain.h
@@ -13,6 +13,8 @@
int sandbox_power_domain_test_get(struct udevice *dev);
int sandbox_power_domain_test_on(struct udevice *dev);
int sandbox_power_domain_test_off(struct udevice *dev);
+int sandbox_power_domain_test_on_ll(struct udevice *dev);
+int sandbox_power_domain_test_off_ll(struct udevice *dev);
int sandbox_power_domain_test_free(struct udevice *dev);
#endif
diff --git a/arch/sandbox/lib/Makefile b/arch/sandbox/lib/Makefile
index 5d7beb2..cefe26d 100644
--- a/arch/sandbox/lib/Makefile
+++ b/arch/sandbox/lib/Makefile
@@ -9,4 +9,4 @@
obj-$(CONFIG_PCI) += pci_io.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-$(CONFIG_CMD_BOOTZ) += bootm.o
-obj-$(CONFIG_$(SPL_)ACPIGEN) += acpi_table.o
+obj-$(CONFIG_$(PHASE_)ACPIGEN) += acpi_table.o
diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c
index 53b1c14..2daf54e 100644
--- a/arch/sh/lib/board.c
+++ b/arch/sh/lib/board.c
@@ -19,18 +19,13 @@
void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaddr)
{
- void (*reloc_board_init_r)(gd_t *gd, ulong dest) = board_init_r;
-
- if (new_gd->reloc_off) {
+ if (new_gd->reloc_off)
memcpy((void *)new_gd->relocaddr,
(void *)(new_gd->relocaddr - new_gd->reloc_off),
new_gd->mon_len);
- reloc_board_init_r += new_gd->reloc_off;
- }
-
__asm__ __volatile__("mov.l %0, r15\n" : : "m" (new_gd->start_addr_sp));
while (1)
- reloc_board_init_r(new_gd, 0x0);
+ board_init_r(new_gd, 0x0);
}
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index fd409b9..7dc3171 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
ifeq ($(CONFIG_EFI_APP),)
-ifdef CONFIG_$(XPL_)X86_64
+ifdef CONFIG_$(PHASE_)X86_64
head-y := arch/x86/cpu/start64.o
else
ifeq ($(CONFIG_$(PHASE_)X86_16BIT_INIT),y)
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 39c8b08..cc55c8f 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -6,7 +6,7 @@
# (C) Copyright 2002
# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
-ifeq ($(CONFIG_$(XPL_)X86_64),y)
+ifeq ($(CONFIG_$(PHASE_)X86_64),y)
extra-y = start64.o
else
ifeq ($(CONFIG_$(PHASE_)X86_16BIT_INIT),y)
@@ -31,7 +31,7 @@
obj-y += cpu_x86.o
endif
-ifndef CONFIG_$(XPL_)X86_64
+ifndef CONFIG_$(PHASE_)X86_64
AFLAGS_REMOVE_call32.o := -mregparm=3 \
$(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32)
AFLAGS_call32.o := -fpic -fshort-wchar \
@@ -59,18 +59,18 @@
ifndef CONFIG_SYS_COREBOOT
obj-$(CONFIG_$(PHASE_)X86_32BIT_INIT) += irq.o
endif
-ifndef CONFIG_$(XPL_)X86_64
-obj-$(CONFIG_$(XPL_)SMP) += mp_init.o
+ifndef CONFIG_$(PHASE_)X86_64
+obj-$(CONFIG_$(PHASE_)SMP) += mp_init.o
endif
obj-y += mtrr.o
obj-$(CONFIG_PCI) += pci.o
-ifndef CONFIG_$(XPL_)X86_64
+ifndef CONFIG_$(PHASE_)X86_64
obj-$(CONFIG_SMP) += sipi_vector.o
endif
obj-y += turbo.o
obj-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.o
-ifeq ($(CONFIG_$(XPL_)X86_64),y)
+ifeq ($(CONFIG_$(PHASE_)X86_64),y)
obj-y += x86_64/
else
obj-y += i386/
diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile
index a28e6c7..3f77f2b 100644
--- a/arch/x86/cpu/intel_common/Makefile
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -26,10 +26,10 @@
obj-y += fast_spi.o
obj-y += lpc.o
obj-y += lpss.o
-obj-$(CONFIG_$(XPL_)INTEL_GENERIC_WIFI) += generic_wifi.o
+obj-$(CONFIG_$(PHASE_)INTEL_GENERIC_WIFI) += generic_wifi.o
ifndef CONFIG_EFI_APP
obj-$(CONFIG_$(PHASE_)X86_32BIT_INIT) += microcode.o
-ifndef CONFIG_$(XPL_)X86_64
+ifndef CONFIG_$(PHASE_)X86_64
obj-y += microcode.o
endif
endif
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
index 471ad8d..6f6d10a 100644
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -5,15 +5,15 @@
ifdef CONFIG_HAVE_FSP
obj-y += fsp_configs.o ivybridge.o
else
-obj-$(CONFIG_$(XPL_)X86_32BIT_INIT) += cpu.o
+obj-$(CONFIG_$(PHASE_)X86_32BIT_INIT) += cpu.o
obj-y += early_me.o
obj-y += lpc.o
obj-y += northbridge.o
ifndef CONFIG_XPL_BUILD
obj-y += sata.o
endif
-obj-$(CONFIG_$(XPL_)X86_32BIT_INIT) += sdram.o
-ifndef CONFIG_$(XPL_)X86_32BIT_INIT
+obj-$(CONFIG_$(PHASE_)X86_32BIT_INIT) += sdram.o
+ifndef CONFIG_$(PHASE_)X86_32BIT_INIT
obj-y += sdram_nop.o
endif
endif
diff --git a/arch/x86/cpu/qemu/Makefile b/arch/x86/cpu/qemu/Makefile
index 1439916..2134b0d 100644
--- a/arch/x86/cpu/qemu/Makefile
+++ b/arch/x86/cpu/qemu/Makefile
@@ -2,7 +2,7 @@
#
# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
-ifndef CONFIG_$(XPL_)X86_64
+ifndef CONFIG_$(PHASE_)X86_64
obj-y += car.o
endif
obj-y += dram.o
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index a908356..afb6abb 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -19,7 +19,7 @@
obj-$(CONFIG_CMD_BOOTM) += bootm.o
endif
obj-y += cmd_boot.o
-obj-$(CONFIG_$(XPL_)COREBOOT_SYSINFO) += coreboot/
+obj-$(CONFIG_$(PHASE_)COREBOOT_SYSINFO) += coreboot/
obj-$(CONFIG_SEABIOS) += coreboot_table.o
obj-y += early_cmos.o
obj-y += e820.o
@@ -92,7 +92,7 @@
ifdef CONFIG_EFI_STUB
-ifeq ($(CONFIG_$(XPL_)X86_64),)
+ifeq ($(CONFIG_$(PHASE_)X86_64),)
extra-y += $(EFI_CRT0) $(EFI_RELOC)
endif
diff --git a/board/BuR/common/Kconfig b/board/BuR/common/Kconfig
new file mode 100644
index 0000000..490201e
--- /dev/null
+++ b/board/BuR/common/Kconfig
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# B&R Industrial Automation GmbH - http://www.br-automation.com
+
+config BR_RESETC_I2CBUS
+ int "I2C Bus address of B&R reset controller"
+ depends on SYS_VENDOR = "BuR" && DM_I2C
+ default 0
diff --git a/board/BuR/common/br_resetc.c b/board/BuR/common/br_resetc.c
index f5d09fe..dfe2c2e 100644
--- a/board/BuR/common/br_resetc.c
+++ b/board/BuR/common/br_resetc.c
@@ -52,10 +52,16 @@
{
struct udevice *i2cbus;
int rc;
+#if !defined(BR_RESETC_I2CBUS)
+ int busno = 0;
+#else
+ int busno = CONFIG_BR_RESETC_I2CBUS;
+#endif
- rc = uclass_get_device_by_seq(UCLASS_I2C, 0, &i2cbus);
+ rc = uclass_get_device_by_seq(UCLASS_I2C, busno, &i2cbus);
+
if (rc) {
- printf("Cannot find I2C bus #0!\n");
+ printf("Cannot find I2C bus #%d!\n", busno);
return -1;
}
@@ -108,9 +114,73 @@
{
int rc = 0;
u16 regw;
+ unsigned int bmode = 0;
+
+ if (!resetc.i2cdev)
+ rc = resetc_init();
+
+ if (rc != 0)
+ return rc;
+
+ board_boot_led(1);
+
+ rc = br_resetc_bmode_get(&bmode);
+ if (rc != 0)
+ return rc;
+
+ LCD_SETCURSOR(1, 8);
+
+ switch (bmode) {
+ case BMODE_PME:
+ LCD_PUTS("entering PME-Mode (netscript). ");
+ regw = 0x0C0C;
+ break;
+ case BMODE_DEFAULTAR:
+ LCD_PUTS("entering BOOT-mode. ");
+ regw = 0x0000;
+ break;
+ case BMODE_DIAG:
+ LCD_PUTS("entering DIAGNOSE-mode. ");
+ regw = 0x0F0F;
+ break;
+ case BMODE_SERVICE:
+ LCD_PUTS("entering SERVICE mode. ");
+ regw = 0xB4B4;
+ break;
+ case BMODE_RUN:
+ LCD_PUTS("loading OS... ");
+ regw = 0x0404;
+ break;
+ }
+
+ board_boot_led(0);
+
+ if (resetc.is_psoc)
+ rc = dm_i2c_write(resetc.i2cdev, RSTCTRL_SCRATCHREG0,
+ (u8 *)®w, 2);
+ else
+ rc = dm_i2c_write(resetc.i2cdev, RSTCTRL_SCRATCHREG0,
+ (u8 *)®w, 1);
+
+ if (rc != 0)
+ printf("WARN: cannot write into resetcontroller!\n");
+
+ if (resetc.is_psoc)
+ printf("Reset: PSOC controller\n");
+ else
+ printf("Reset: STM32 controller\n");
+
+ printf("Mode: %s\n", bootmodeascii[regw & 0x0F]);
+ env_set_ulong("b_mode", regw & 0x0F);
+
+ return rc;
+}
+
+int br_resetc_bmode_get(unsigned int *bmode)
+{
+ int rc = 0;
u8 regb, scr;
int cnt;
- unsigned int bmode = 0;
if (!resetc.i2cdev)
rc = resetc_init();
@@ -130,13 +200,11 @@
return -1;
}
- board_boot_led(1);
-
/* special bootmode from resetcontroller */
if (regb & 0x4) {
- bmode = BMODE_DIAG;
+ *bmode = BMODE_DIAG;
} else if (regb & 0x8) {
- bmode = BMODE_DEFAULTAR;
+ *bmode = BMODE_DEFAULTAR;
} else if (board_boot_key() != 0) {
cnt = 4;
do {
@@ -163,68 +231,23 @@
switch (cnt) {
case 0:
- bmode = BMODE_PME;
+ *bmode = BMODE_PME;
break;
case 1:
- bmode = BMODE_DEFAULTAR;
+ *bmode = BMODE_DEFAULTAR;
break;
case 2:
- bmode = BMODE_DIAG;
+ *bmode = BMODE_DIAG;
break;
case 3:
- bmode = BMODE_SERVICE;
+ *bmode = BMODE_SERVICE;
break;
}
} else if ((regb & 0x1) || scr == 0xCC) {
- bmode = BMODE_PME;
+ *bmode = BMODE_PME;
} else {
- bmode = BMODE_RUN;
- }
-
- LCD_SETCURSOR(1, 8);
-
- switch (bmode) {
- case BMODE_PME:
- LCD_PUTS("entering PME-Mode (netscript). ");
- regw = 0x0C0C;
- break;
- case BMODE_DEFAULTAR:
- LCD_PUTS("entering BOOT-mode. ");
- regw = 0x0000;
- break;
- case BMODE_DIAG:
- LCD_PUTS("entering DIAGNOSE-mode. ");
- regw = 0x0F0F;
- break;
- case BMODE_SERVICE:
- LCD_PUTS("entering SERVICE mode. ");
- regw = 0xB4B4;
- break;
- case BMODE_RUN:
- LCD_PUTS("loading OS... ");
- regw = 0x0404;
- break;
+ *bmode = BMODE_RUN;
}
- board_boot_led(0);
-
- if (resetc.is_psoc)
- rc = dm_i2c_write(resetc.i2cdev, RSTCTRL_SCRATCHREG0,
- (u8 *)®w, 2);
- else
- rc = dm_i2c_write(resetc.i2cdev, RSTCTRL_SCRATCHREG0,
- (u8 *)®w, 1);
-
- if (rc != 0)
- printf("WARN: cannot write into resetcontroller!\n");
-
- if (resetc.is_psoc)
- printf("Reset: PSOC controller\n");
- else
- printf("Reset: STM32 controller\n");
-
- printf("Mode: %s\n", bootmodeascii[regw & 0x0F]);
- env_set_ulong("b_mode", regw & 0x0F);
-
return rc;
}
diff --git a/board/BuR/common/br_resetc.h b/board/BuR/common/br_resetc.h
index 999045b..3bd5ac2 100644
--- a/board/BuR/common/br_resetc.h
+++ b/board/BuR/common/br_resetc.h
@@ -11,6 +11,7 @@
int br_resetc_regget(u8 reg, u8 *dst);
int br_resetc_regset(u8 reg, u8 val);
int br_resetc_bmode(void);
+int br_resetc_bmode_get(unsigned int *bmode);
/* reset controller register defines */
#define RSTCTRL_CTRLREG 0x01
diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c
index 7fb6173..3513f43 100644
--- a/board/BuR/common/common.c
+++ b/board/BuR/common/common.c
@@ -68,7 +68,7 @@
"if test -r ${ipaddr}; then; else setenv ipaddr 192.168.60.%d; setenv serverip 192.168.60.254; setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;",
u8buf);
else
- strncpy(defip,
+ strlcpy(defip,
"if test -r ${ipaddr}; then; else setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254; setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;",
sizeof(defip));
diff --git a/board/BuR/zynq/Kconfig b/board/BuR/zynq/Kconfig
new file mode 100644
index 0000000..b450a21
--- /dev/null
+++ b/board/BuR/zynq/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# B&R Industrial Automation GmbH - http://www.br-automation.com
+if ARCH_ZYNQ
+
+config TARGET_ZYNQ_BR
+ bool "Support BR Zynq builds"
+ depends on SYS_VENDOR = "BuR"
+ select BINMAN
+ select SPL_BINMAN_FDT
+
+endif
+
+source "board/BuR/common/Kconfig"
diff --git a/board/BuR/zynq/MAINTAINERS b/board/BuR/zynq/MAINTAINERS
new file mode 100644
index 0000000..d655cae
--- /dev/null
+++ b/board/BuR/zynq/MAINTAINERS
@@ -0,0 +1,11 @@
+ZYNQ BOARD
+M: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
+S: Maintained
+F: board/BuR/zynq/
+F: board/BuR/common/
+F: include/configs/brzynq.h
+F: arch/arm/dts/zynq-br*
+F: configs/brcp1_*
+F: configs/brcp150_defconfig
+F: configs/brcp170_defconfig
+F: configs/brsmarc2_defconfig
diff --git a/board/BuR/zynq/Makefile b/board/BuR/zynq/Makefile
new file mode 100644
index 0000000..fed40b0a
--- /dev/null
+++ b/board/BuR/zynq/Makefile
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# B&R Industrial Automation GmbH - http://www.br-automation.com
+
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/zynq-//')
+
+obj-y := ../common/common.o
+obj-y += ../common/br_resetc.o
+obj-y += common/board.o
+obj-y += $(hw-platform-y)/board.o
+
+obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o
+
+# Suppress "warning: function declaration isn't a prototype"
+CFLAGS_REMOVE_ps7_init_gpl.o := -Wstrict-prototypes
diff --git a/board/BuR/zynq/brcp150/board.c b/board/BuR/zynq/brcp150/board.c
new file mode 100644
index 0000000..456d490
--- /dev/null
+++ b/board/BuR/zynq/brcp150/board.c
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ */
diff --git a/board/BuR/zynq/brcp150/ps7_init_gpl.c b/board/BuR/zynq/brcp150/ps7_init_gpl.c
new file mode 100644
index 0000000..822bce3
--- /dev/null
+++ b/board/BuR/zynq/brcp150/ps7_init_gpl.c
@@ -0,0 +1,278 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000011U),
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00500141U),
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000801U),
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001001U),
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001003U),
+ EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000802U),
+ EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00A01403U),
+ EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000801U),
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400800U),
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01FF844DU),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x0000103FU),
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00042E1AU),
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D154D4U),
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U),
+ EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U),
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U),
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
+ EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U),
+ EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U),
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU),
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U),
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C000U),
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U),
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U),
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU),
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU),
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU),
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU),
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C5U),
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U),
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U),
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU),
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU),
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU),
+ EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U),
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U),
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U),
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x000003E0U),
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x000003E1U),
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000321U),
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001220U),
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001220U),
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000321U),
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000013E1U),
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000003E0U),
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_post_config_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+ return ps7_config(ps7_post_config_3_0);
+}
+
+int ps7_init(void)
+{
+ int ret;
+
+ ret = ps7_config(ps7_mio_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_pll_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_clock_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_ddr_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_peripherals_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ return PS7_INIT_SUCCESS;
+}
diff --git a/board/BuR/zynq/brcp170/board.c b/board/BuR/zynq/brcp170/board.c
new file mode 100644
index 0000000..456d490
--- /dev/null
+++ b/board/BuR/zynq/brcp170/board.c
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ */
diff --git a/board/BuR/zynq/brcp170/ps7_init_gpl.c b/board/BuR/zynq/brcp170/ps7_init_gpl.c
new file mode 100644
index 0000000..223d13c
--- /dev/null
+++ b/board/BuR/zynq/brcp170/ps7_init_gpl.c
@@ -0,0 +1,274 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000502U),
+ EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00501903U),
+ EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400500U),
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DF844DU),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x0000103FU),
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00042E1AU),
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D154D4U),
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U),
+ EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U),
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U),
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
+ EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U),
+ EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U),
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU),
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U),
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C000U),
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U),
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U),
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU),
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU),
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU),
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU),
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C5U),
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U),
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U),
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU),
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU),
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU),
+ EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U),
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U),
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U),
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000321U),
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001220U),
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001220U),
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000321U),
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000013E1U),
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000003E0U),
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_post_config_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+ return ps7_config(ps7_post_config_3_0);
+}
+
+int ps7_init(void)
+{
+ int ret;
+
+ ret = ps7_config(ps7_mio_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_pll_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_clock_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_ddr_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_peripherals_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ return PS7_INIT_SUCCESS;
+}
diff --git a/board/BuR/zynq/brcp1_1r/board.c b/board/BuR/zynq/brcp1_1r/board.c
new file mode 100644
index 0000000..456d490
--- /dev/null
+++ b/board/BuR/zynq/brcp1_1r/board.c
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ */
diff --git a/board/BuR/zynq/brcp1_1r/ps7_init_gpl.c b/board/BuR/zynq/brcp1_1r/ps7_init_gpl.c
new file mode 100644
index 0000000..be39db9
--- /dev/null
+++ b/board/BuR/zynq/brcp1_1r/ps7_init_gpl.c
@@ -0,0 +1,274 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA240U),
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0003C000U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000300U),
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x000FA240U),
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0003C000U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U),
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00101001U),
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001401U),
+ EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000A02U),
+ EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00A01901U),
+ EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00500800U),
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DD844DU),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000084U),
+ EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001040U),
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00040EDAU),
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D258D4U),
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U),
+ EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U),
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U),
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000666U),
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFFF0000U),
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FFF5555U),
+ EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U),
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU),
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000000U),
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000000U),
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U),
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C400U),
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U),
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U),
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU),
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU),
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU),
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU),
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C6U),
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U),
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U),
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU),
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU),
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU),
+ EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U),
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000085U),
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000800U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000800U),
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000220U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U),
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U),
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000361U),
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00000360U),
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00000361U),
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000361U),
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000012E1U),
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000002E0U),
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_post_config_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+ return ps7_config(ps7_post_config_3_0);
+}
+
+int ps7_init(void)
+{
+ int ret;
+
+ ret = ps7_config(ps7_mio_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_pll_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_clock_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_ddr_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_peripherals_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ return PS7_INIT_SUCCESS;
+}
diff --git a/board/BuR/zynq/brcp1_1r_switch/board.c b/board/BuR/zynq/brcp1_1r_switch/board.c
new file mode 100644
index 0000000..456d490
--- /dev/null
+++ b/board/BuR/zynq/brcp1_1r_switch/board.c
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ */
diff --git a/board/BuR/zynq/brcp1_1r_switch/ps7_init_gpl.c b/board/BuR/zynq/brcp1_1r_switch/ps7_init_gpl.c
new file mode 100644
index 0000000..e4fc708
--- /dev/null
+++ b/board/BuR/zynq/brcp1_1r_switch/ps7_init_gpl.c
@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U),
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000011U),
+ EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U),
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00500141U),
+ EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00500141U),
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000502U),
+ EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00501901U),
+ EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400500U),
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DD84CDU),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000084U),
+ EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001040U),
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00040EDAU),
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D258D4U),
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U),
+ EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U),
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U),
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000666U),
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFFF0000U),
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FFF5555U),
+ EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U),
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU),
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000000U),
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000000U),
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U),
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C400U),
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U),
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U),
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU),
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU),
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU),
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU),
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C6U),
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U),
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U),
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU),
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU),
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU),
+ EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U),
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000085U),
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000800U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000800U),
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000220U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U),
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U),
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000361U),
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00000360U),
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00000361U),
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000361U),
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000012E1U),
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000002E0U),
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000300U),
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_post_config_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+ return ps7_config(ps7_post_config_3_0);
+}
+
+int ps7_init(void)
+{
+ int ret;
+
+ ret = ps7_config(ps7_mio_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_pll_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_clock_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_ddr_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_peripherals_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ return PS7_INIT_SUCCESS;
+}
diff --git a/board/BuR/zynq/brcp1_2r/board.c b/board/BuR/zynq/brcp1_2r/board.c
new file mode 100644
index 0000000..456d490
--- /dev/null
+++ b/board/BuR/zynq/brcp1_2r/board.c
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ */
diff --git a/board/BuR/zynq/brcp1_2r/ps7_init_gpl.c b/board/BuR/zynq/brcp1_2r/ps7_init_gpl.c
new file mode 100644
index 0000000..4ebed8b
--- /dev/null
+++ b/board/BuR/zynq/brcp1_2r/ps7_init_gpl.c
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA3C0U),
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0002E000U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U),
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000502U),
+ EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00501901U),
+ EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00101400U),
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00101400U),
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00101400U),
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DD844DU),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001040U),
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004281AU),
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D258D4U),
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U),
+ EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U),
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U),
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U),
+ EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U),
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU),
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U),
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C400U),
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U),
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U),
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU),
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU),
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU),
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU),
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C6U),
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U),
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U),
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU),
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU),
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU),
+ EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U),
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U),
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U),
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000361U),
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00000360U),
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00000361U),
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000361U),
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000012E1U),
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000002E0U),
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_post_config_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+ return ps7_config(ps7_post_config_3_0);
+}
+
+int ps7_init(void)
+{
+ int ret;
+
+ ret = ps7_config(ps7_mio_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_pll_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_clock_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_ddr_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_peripherals_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ return PS7_INIT_SUCCESS;
+}
diff --git a/board/BuR/zynq/brsmarc2/board.c b/board/BuR/zynq/brsmarc2/board.c
new file mode 100644
index 0000000..7d9e13a
--- /dev/null
+++ b/board/BuR/zynq/brsmarc2/board.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ */
+#include <linux/types.h>
+#include <i2c.h>
+#include <init.h>
+#include "../../common/br_resetc.h"
+#include "../../common/bur_common.h"
+
+int board_boot_key(void)
+{
+ unsigned char u8buf = 0;
+ int rc;
+
+ rc = br_resetc_regget(RSTCTRL_ENHSTATUS, &u8buf);
+ if (rc == 0)
+ return (u8buf & 0x1);
+
+ return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+int br_board_late_init(void)
+{
+ brdefaultip_setup(0, 0x57);
+
+ return 0;
+}
+#endif
diff --git a/board/BuR/zynq/brsmarc2/ps7_init_gpl.c b/board/BuR/zynq/brsmarc2/ps7_init_gpl.c
new file mode 100644
index 0000000..51ff8bf
--- /dev/null
+++ b/board/BuR/zynq/brsmarc2/ps7_init_gpl.c
@@ -0,0 +1,276 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U),
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+ EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U),
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00500801U),
+ EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00500141U),
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000503U),
+ EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00501903U),
+ EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400500U),
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DFC4CDU),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001040U),
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00040EDAU),
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D258D4U),
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U),
+ EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U),
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U),
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FFF6666U),
+ EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U),
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU),
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U),
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C400U),
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U),
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U),
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU),
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU),
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU),
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU),
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C6U),
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U),
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U),
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU),
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU),
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU),
+ EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U),
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U),
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x000016E1U),
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x000006E0U),
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000302U),
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000303U),
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U),
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U),
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000321U),
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00000320U),
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00000320U),
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000321U),
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000340U),
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000340U),
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_post_config_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+ return ps7_config(ps7_post_config_3_0);
+}
+
+int ps7_init(void)
+{
+ int ret;
+
+ ret = ps7_config(ps7_mio_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_pll_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_clock_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_ddr_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_peripherals_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ return PS7_INIT_SUCCESS;
+}
diff --git a/board/BuR/zynq/common/board.c b/board/BuR/zynq/common/board.c
new file mode 100644
index 0000000..35e8ed8
--- /dev/null
+++ b/board/BuR/zynq/common/board.c
@@ -0,0 +1,231 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board functions for B&R brcp150, brcp170, brcp1, brsmarc2 Board
+ *
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ *
+ */
+
+#include <fdtdec.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <init.h>
+#include <i2c.h>
+#include <dm/uclass.h>
+#include <command.h>
+#include <binman.h>
+#include "../../common/br_resetc.h"
+#include "../../common/bur_common.h"
+
+#include <fdt_support.h>
+#include <spi_flash.h>
+#include <fpga.h>
+#include <zynqpl.h>
+
+#define RSTCTRL_CTRLSPEC_nPCIRST 0x1
+
+__weak int br_board_late_init(void)
+{
+ return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(FPGA)
+const char *fpga_paths[2] = { "/binman/blob-ext@4",
+ "/binman/blob-ext@1"};
+
+static int start_fpga(unsigned int bank)
+{
+ struct spi_flash *flash_dev;
+ ofnode fpga_node;
+ void *buf;
+
+ u32 flash_offset, flash_size;
+ int rc;
+
+ fpga_node = ofnode_path(fpga_paths[bank]);
+
+ if (!ofnode_valid(fpga_node)) {
+ printf("WARN: binman node not found %s\n", fpga_paths[bank]);
+ return -ENOENT;
+ }
+
+ flash_offset = ofnode_read_u32_default(fpga_node, "offset", ~0UL);
+ flash_size = ofnode_read_u32_default(fpga_node, "size", ~0UL);
+
+ if (flash_offset == ~0UL || flash_size == ~0UL) {
+ printf("WARN: invalid fpga 'offset, size' in fdt (0x%x, 0x%x)",
+ flash_offset, flash_size);
+ return -EINVAL;
+ }
+
+ printf("loading bitstream from bank #%d (0x%08x / 0x%08x)\n", bank,
+ flash_offset, flash_size);
+
+ flash_dev = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+ CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE);
+
+ if (rc) {
+ printf("WARN: cannot probe SPI-flash for bitstream!\n");
+ return -ENODEV;
+ }
+
+ buf = kmalloc(flash_size, 0);
+ if (!buf) {
+ spi_flash_free(flash_dev);
+ return -ENOMEM;
+ }
+
+ debug("using buf @ %p, flashbase: 0x%08x, len: 0x%08x\n",
+ buf, flash_offset, flash_size);
+
+ rc = spi_flash_read(flash_dev, flash_offset, flash_size, buf);
+
+ spi_flash_free(flash_dev);
+
+ if (rc) {
+ printf("WARN: cannot read bitstream from spi-flash!\n");
+ kfree(buf);
+
+ return -EIO;
+ }
+
+ rc = fpga_loadbitstream(0, buf, flash_size, BIT_FULL);
+ if (rc) {
+ printf("WARN: FPGA configuration from bank #%d failed!\n", bank);
+ kfree(buf);
+
+ return -EIO;
+ }
+
+ kfree(buf);
+
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_SPL_BUILD)
+const char *boot_gpios[] = { "br,rs232-en",
+ "br,board-reset",
+ NULL};
+
+/* spl stage */
+int board_init(void)
+{
+ struct gpio_desc gpio;
+ int node;
+ int rc;
+
+ /* peripheral RESET on PSOC reset-controller */
+ rc = br_resetc_regset(RSTCTRL_SPECGPIO_O, RSTCTRL_CTRLSPEC_nPCIRST);
+ if (rc != 0)
+ printf("ERROR: cannot write to resetc (nPCIRST)!\n");
+
+ for (int i = 0; boot_gpios[i]; i++) {
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, boot_gpios[i]);
+
+ if (node < 0) {
+ printf("INFO: %s not found!\n", boot_gpios[i]);
+ } else {
+ rc = gpio_request_by_name_nodev(offset_to_ofnode(node), "pin",
+ 0, &gpio, GPIOD_IS_OUT);
+
+ if (!rc)
+ dm_gpio_set_value(&gpio, 1);
+ else
+ printf("ERROR: failed to setup %s!\n", boot_gpios[i]);
+ }
+ }
+
+#if CONFIG_IS_ENABLED(FPGA)
+ unsigned int bmode;
+ unsigned int bank;
+
+ rc = br_resetc_bmode_get(&bmode);
+ if (rc) {
+ printf("WARN: can't get Boot Mode!\n");
+ return -ENODEV;
+ }
+
+ /* use golden FPGA image in case of special boot flow (PME, BootAR, USB, Net ...) */
+ bank = ((bmode == 0) || (bmode == 12)) ? 1 : 0;
+
+ /* bring up FPGA */
+ if (start_fpga(bank) != 0) {
+ printf("WARN: cannot start fpga from bank %d, trying bank %d!\n", bank, bank ^ 1);
+ bank ^= 1;
+ start_fpga(bank);
+ }
+#endif
+ return 0;
+}
+#else
+int board_init(void)
+{
+ return 0;
+}
+
+/*
+ * PMIC buckboost regulator workaround:
+ * The DA9062 PMIC can switch its buckboost regulator output
+ * between PFM and PWM mode for eco-purpose.
+ * In very rare situations this transition leads into a non-
+ * functional buckboost regulator with zero output.
+ * With this workaround we prevent this with turning this
+ * feature off by forcing PWM-mode if auto-mode is selected.
+ */
+static void pmic_fixup(int addr)
+{
+ u8 regs[] = { 0x9E, 0x9D, 0xA0, 0x9F };
+ struct udevice *i2cdev = NULL;
+ unsigned int i;
+ u8 val;
+ int rc;
+
+ i2c_get_chip_for_busnum(0, addr, 1, &i2cdev);
+ if (!i2cdev)
+ return;
+
+ printf("PMIC: fixup buckboost at i2c device 0x%x\n", addr);
+
+ for (i = 0; i < sizeof(regs); i++) {
+ rc = dm_i2c_read(i2cdev, regs[i], &val, 1);
+ if (rc == 0 && val == 0xC0) {
+ val = 0x80;
+ dm_i2c_write(i2cdev, regs[i], &val, 1);
+ }
+ }
+}
+
+int board_late_init(void)
+{
+ ofnode node;
+ u32 addr;
+
+ br_resetc_bmode();
+ br_board_late_init();
+
+ node = ofnode_by_compatible(ofnode_null(), "dlg,da9062");
+
+ if (!ofnode_valid(node))
+ return 0;
+
+ if (!ofnode_read_u32(node, "reg", &addr))
+ pmic_fixup(addr);
+ else
+ printf("WARN: cannot read PMIC address!");
+
+ return 0;
+}
+#endif
+
+int dram_init(void)
+{
+ if (fdtdec_setup_mem_size_base() != 0)
+ return -EINVAL;
+
+ zynq_ddrc_init();
+
+ return 0;
+}
diff --git a/board/BuR/zynq/env/brcp1.env b/board/BuR/zynq/env/brcp1.env
new file mode 100644
index 0000000..269e519
--- /dev/null
+++ b/board/BuR/zynq/env/brcp1.env
@@ -0,0 +1,109 @@
+autoload=0
+b_break=0
+fpgastatus=disabled
+/* Memory variable */
+scradr=0xC0000
+fdtbackaddr=0x4000000
+loadaddr=CONFIG_SYS_LOAD_ADDR
+
+/* PREBOOT */
+preboot=run setupaddr_spi; run brdefaultip; run cfgscr; setenv bootstart 1
+
+/* SPI layout variables */
+cfg_addr=
+ fdt get value cfgaddr_spi /binman/blob-ext@0 offset &&
+ fdt get value cfgsize_spi /binman/blob-ext@0 size
+
+fpga_addr=
+ fdt get value fpgaaddr_spi /binman/blob-ext@1 offset &&
+ fdt get value fpgasize_spi /binman/blob-ext@1 size
+
+os_addr=
+ fdt get value osaddr_spi /binman/blob-ext@2 offset &&
+ fdt get value ossize_spi /binman/blob-ext@2 size
+
+dtb_addr=
+ fdt get value dtbaddr_spi /binman/blob-ext@3 offset &&
+ fdt get value dtbsize_spi /binman/blob-ext@3 size
+
+setupaddr_spi=
+ fdt addr ${fdtcontroladdr};
+ run dtb_addr; run os_addr;
+ run fpga_addr; run cfg_addr
+
+/* IP setup */
+brdefaultip=
+ if test -r ${ipaddr}; then;
+ else
+ setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254;
+ setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0;
+ fi
+
+/* Boot orders */
+b_tgts_std=mmc0 mmc1 spi usb0 usb1 net
+b_tgts_rcy=spi usb0 usb1 net
+b_tgts_pme=net usb0 usb1 mmc spi
+
+/* Boot targets */
+b_mmc0=
+ run fpga; mmc dev 0; load mmc 0 ${loadaddr} arimg.itb &&
+ run vxargs && bootm ${loadaddr}
+
+b_mmc1=
+ run fpga; mmc dev 0; load mmc 0 ${loadaddr} arimg &&
+ run vxargs &&
+ sf read ${fdtbackaddr} ${dtbaddr_spi} ${dtbsize_spi} &&
+ fdt addr ${fdtbackaddr} &&
+ bootm ${loadaddr} - ${fdtbackaddr}
+
+b_spi=
+ run fpga; sf read ${loadaddr} ${osaddr_spi} ${ossize_spi} &&
+ run vxargs && bootm ${loadaddr}
+
+b_net=run fpga; tftp ${scradr} netscript.img && source ${scradr}
+b_usb0=usb start && load usb 0 ${scradr} usbscript.img && source ${scradr}
+b_usb1=usb start && load usb 0 ${scradr} bootscr.img && source ${scradr}
+
+/* FPGA setup */
+fpga=
+ setenv fpgastatus disabled;
+ sf read ${loadaddr} ${fpgaaddr_spi} ${fpgasize_spi} &&
+ fpga loadb 0 ${loadaddr} ${fpgasize_spi} &&
+ setenv fpgastatus okay
+
+/* Configuration preboot*/
+cfgscr=
+ sf probe &&
+ sf read ${scradr} ${cfgaddr_spi} ${cfgsize_spi} &&
+ source ${scradr}
+
+/* OS Boot */
+fdt_fixup=
+ run cfgscr; run vxfdt
+
+vxargs=
+ setenv bootargs gem(0,0)host:vxWorks h=${serverip}
+ e=${ipaddr}:${netmask} g=${gatewayip} u=vxWorksFTP pw=vxWorks f=0x1
+
+vxfdt=
+ fdt set /fpga/pci status ${fpgastatus};
+ fdt set /fpga status ${fpgastatus}
+
+/* Boot code */
+b_default=
+ run b_deftgts;
+ for target in ${b_tgts}; do
+ run b_${target};
+ if test ${b_break} = 1; then;
+ exit;
+ fi;
+ done
+
+b_deftgts=
+ if test ${b_mode} = 12; then
+ setenv b_tgts ${b_tgts_pme};
+ elif test ${b_mode} = 0; then
+ setenv b_tgts ${b_tgts_rcy};
+ else
+ setenv b_tgts ${b_tgts_std};
+ fi
diff --git a/board/BuR/zynq/env/brcp150.env b/board/BuR/zynq/env/brcp150.env
new file mode 100644
index 0000000..9c27f0f
--- /dev/null
+++ b/board/BuR/zynq/env/brcp150.env
@@ -0,0 +1,119 @@
+autoload=0
+b_break=0
+fpgastatus=disabled
+/* Memory variable */
+scradr=0xC0000
+fdtbackaddr=0x4000000
+loadaddr=CONFIG_SYS_LOAD_ADDR
+
+/* PREBOOT */
+preboot=run setupaddr_spi; run brdefaultip; run cfgscr; setenv bootstart 1
+
+/* SPI layout variables */
+cfg_addr=
+ fdt get value cfgaddr_spi /binman/blob-ext@0 offset &&
+ fdt get value cfgsize_spi /binman/blob-ext@0 size
+
+fpga_addr=
+ fdt get value fpgaaddr_spi /binman/blob-ext@1 offset &&
+ fdt get value fpgasize_spi /binman/blob-ext@1 size
+
+os_addr=
+ fdt get value osaddr_spi /binman/blob-ext@2 offset &&
+ fdt get value ossize_spi /binman/blob-ext@2 size
+
+dtb_addr=
+ fdt get value dtbaddr_spi /binman/blob-ext@3 offset &&
+ fdt get value dtbsize_spi /binman/blob-ext@3 size
+
+opt_addr=
+ fdt get value optaddr_spi /binman/blob-ext@5 offset &&
+ fdt get value optsize_spi /binman/blob-ext@5 size
+
+setupaddr_spi=
+ fdt addr ${fdtcontroladdr};
+ run dtb_addr; run os_addr;
+ run fpga_addr; run cfg_addr;
+ run opt_addr
+
+/* IP setup */
+brdefaultip=
+ if test -r ${ipaddr}; then;
+ else
+ setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254;
+ setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0;
+ fi
+
+/* Boot orders */
+b_tgts_std=mmc0 mmc1 fpga spi usb0 usb1 net
+b_tgts_rcy=spi usb0 usb1 net
+b_tgts_pme=net usb0 usb1 mmc spi
+
+/* Boot targets */
+b_mmc0=
+ mmc dev 0; load mmc 0 ${loadaddr} arimg.itb &&
+ run vxargs && bootm ${loadaddr}
+
+b_mmc1=
+ mmc dev 0; load mmc 0 ${loadaddr} arimg &&
+ run vxargs &&
+ sf read ${fdtbackaddr} ${dtbaddr_spi} ${dtbsize_spi} &&
+ fdt addr ${fdtbackaddr} &&
+ bootm ${loadaddr} - ${fdtbackaddr}
+
+b_spi=
+ sf read ${loadaddr} ${osaddr_spi} ${ossize_spi} &&
+ run vxargs && bootm ${loadaddr}
+
+b_net=tftp ${scradr} netscript.img && source ${scradr}
+b_usb0=usb start && load usb 0 ${scradr} usbscript.img && source ${scradr}
+b_usb1=usb start && load usb 0 ${scradr} bootscr.img && source ${scradr}
+
+/* FPGA setup */
+b_fpga=
+ setenv fpgastatus disabled;
+ sf read ${loadaddr} ${fpgaaddr_spi} ${fpgasize_spi} &&
+ fpga loadb 0 ${loadaddr} ${fpgasize_spi} &&
+ setenv fpgastatus okay
+
+/* Configuration preboot*/
+cfgscr=
+ sf probe &&
+ sf read ${scradr} ${cfgaddr_spi} ${cfgsize_spi} &&
+ source ${scradr}
+
+cfgoptsct=
+ sf probe &&
+ sf read ${scradr} ${optaddr_spi} ${optsize_spi} &&
+ source ${scradr}
+
+/* OS Boot */
+fdt_fixup=
+ run cfgscr; run cfgoptsct; run vxfdt
+
+vxargs=
+ setenv bootargs gem(0,0)host:vxWorks h=${serverip}
+ e=${ipaddr}:${netmask} g=${gatewayip} u=vxWorksFTP pw=vxWorks f=0x1
+
+vxfdt=
+ fdt set /fpga/pci status ${fpgastatus};
+ fdt set /fpga status ${fpgastatus}
+
+/* Boot code */
+b_default=
+ run b_deftgts;
+ for target in ${b_tgts}; do
+ run b_${target};
+ if test ${b_break} = 1; then;
+ exit;
+ fi;
+ done
+
+b_deftgts=
+ if test ${b_mode} = 12; then
+ setenv b_tgts ${b_tgts_pme};
+ elif test ${b_mode} = 0; then
+ setenv b_tgts ${b_tgts_rcy};
+ else
+ setenv b_tgts ${b_tgts_std};
+ fi
diff --git a/board/acer/picasso/Kconfig b/board/acer/picasso/Kconfig
index 73c0aa0..879b778 100644
--- a/board/acer/picasso/Kconfig
+++ b/board/acer/picasso/Kconfig
@@ -7,6 +7,10 @@
default "acer"
config SYS_CONFIG_NAME
- default "picasso"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "Acer Iconia Tab A500"
endif
diff --git a/board/amd/versal2/Kconfig b/board/amd/versal2/Kconfig
deleted file mode 100644
index ab46af6..0000000
--- a/board/amd/versal2/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Copyright (C) 2020 - 2022, Xilinx, Inc.
-# Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
-#
-if ARCH_VERSAL2
-
-config CMD_VERSAL2
- bool "Enable Versal Gen 2 specific commands"
- default y
- depends on ZYNQMP_FIRMWARE
- help
- Select this to enable AMD Versal Gen 2 specific commands.
- Commands like versal2 loadpdi are enabled by this.
-
-endif
diff --git a/board/amd/versal2/Makefile b/board/amd/versal2/Makefile
index 3a04451..1673be4 100644
--- a/board/amd/versal2/Makefile
+++ b/board/amd/versal2/Makefile
@@ -8,4 +8,3 @@
obj-y := board.o
-obj-$(CONFIG_CMD_VERSAL2) += cmds.o
diff --git a/board/amd/versal2/board.c b/board/amd/versal2/board.c
index 5651d51..72967e6 100644
--- a/board/amd/versal2/board.c
+++ b/board/amd/versal2/board.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 - 2022, Xilinx, Inc.
- * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
+ * Copyright (C) 2022 - 2025, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -20,6 +20,7 @@
#include <asm/arch/sys_proto.h>
#include <dm/device.h>
#include <dm/uclass.h>
+#include <versalpl.h>
#include "../../xilinx/common/board.h"
#include <linux/bitfield.h>
@@ -28,10 +29,25 @@
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_FPGA_VERSALPL)
+static xilinx_desc versalpl = {
+ xilinx_versal2, csu_dma, 1, &versal_op, 0, &versal_op, NULL,
+ FPGA_LEGACY
+};
+#endif
+
int board_init(void)
{
printf("EL Level:\tEL%d\n", current_el());
+#if defined(CONFIG_FPGA_VERSALPL)
+ fpga_init();
+ fpga_add(fpga_xilinx, &versalpl);
+#endif
+
+ if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
+ xilinx_read_eeprom();
+
return 0;
}
@@ -149,7 +165,7 @@
return 0;
}
-static u8 versal_net_get_bootmode(void)
+static u8 versal2_get_bootmode(void)
{
u8 bootmode;
u32 reg = 0;
@@ -175,7 +191,7 @@
char *new_targets;
char *env_targets;
- bootmode = versal_net_get_bootmode();
+ bootmode = versal2_get_bootmode();
puts("Bootmode: ");
switch (bootmode) {
@@ -252,6 +268,16 @@
mode = "mmc";
bootseq = dev_seq(dev);
break;
+ case UFS_MODE:
+ puts("UFS_MODE\n");
+ if (uclass_get_device(UCLASS_UFS, 0, &dev)) {
+ debug("UFS driver for UFS device is not present\n");
+ break;
+ }
+ debug("ufs device found at %p\n", dev);
+
+ mode = "ufs";
+ break;
default:
printf("Invalid Boot Mode:0x%x\n", bootmode);
break;
@@ -284,6 +310,7 @@
env_targets ? env_targets : "");
env_set("boot_targets", new_targets);
+ free(new_targets);
}
return 0;
@@ -340,4 +367,36 @@
void reset_cpu(void)
{
+}
+
+#if defined(CONFIG_ENV_IS_NOWHERE)
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ u32 bootmode = versal2_get_bootmode();
+
+ if (prio)
+ return ENVL_UNKNOWN;
+
+ switch (bootmode) {
+ case EMMC_MODE:
+ case SD_MODE:
+ case SD1_LSHFT_MODE:
+ case SD_MODE1:
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
+ return ENVL_FAT;
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
+ return ENVL_EXT4;
+ return ENVL_NOWHERE;
+ case OSPI_MODE:
+ case QSPI_MODE_24BIT:
+ case QSPI_MODE_32BIT:
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
+ return ENVL_SPI_FLASH;
+ return ENVL_NOWHERE;
+ case JTAG_MODE:
+ case SELECTMAP_MODE:
+ default:
+ return ENVL_NOWHERE;
+ }
}
+#endif
diff --git a/board/amd/versal2/cmds.c b/board/amd/versal2/cmds.c
deleted file mode 100644
index 56ae39b..0000000
--- a/board/amd/versal2/cmds.c
+++ /dev/null
@@ -1,80 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2024, Advanced Micro Devices, Inc.
- *
- * Michal Simek <michal.simek@amd.com>
- */
-
-#include <cpu_func.h>
-#include <command.h>
-#include <log.h>
-#include <memalign.h>
-#include <versalpl.h>
-#include <vsprintf.h>
-#include <zynqmp_firmware.h>
-
-/**
- * do_versal2_load_pdi - Handle the "versal2 load pdi" command-line command
- * @cmdtp: Command data struct pointer
- * @flag: Command flag
- * @argc: Command-line argument count
- * @argv: Array of command-line arguments
- *
- * Processes the versal2 load pdi command
- *
- * Return: return 0 on success, Error value if command fails.
- * CMD_RET_USAGE incase of incorrect/missing parameters.
- */
-static int do_versal2_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc,
- char * const argv[])
-{
- u32 buf_lo, buf_hi;
- u32 ret_payload[PAYLOAD_ARG_CNT];
- ulong addr, *pdi_buf;
- size_t len;
- int ret;
-
- if (argc != cmdtp->maxargs) {
- debug("pdi_load: incorrect parameters passed\n");
- return CMD_RET_USAGE;
- }
-
- addr = simple_strtol(argv[1], NULL, 16);
- if (!addr) {
- debug("pdi_load: zero pdi_data address\n");
- return CMD_RET_USAGE;
- }
-
- len = hextoul(argv[2], NULL);
- if (!len) {
- debug("pdi_load: zero size\n");
- return CMD_RET_USAGE;
- }
-
- pdi_buf = (ulong *)ALIGN((ulong)addr, ARCH_DMA_MINALIGN);
- if ((ulong)addr != (ulong)pdi_buf) {
- memcpy((void *)pdi_buf, (void *)addr, len);
- debug("Pdi addr:0x%lx aligned to 0x%lx\n",
- addr, (ulong)pdi_buf);
- }
-
- flush_dcache_range((ulong)pdi_buf, (ulong)pdi_buf + len);
-
- buf_lo = lower_32_bits((ulong)pdi_buf);
- buf_hi = upper_32_bits((ulong)pdi_buf);
-
- ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
- buf_hi, 0, ret_payload);
- if (ret)
- printf("PDI load failed with err: 0x%08x\n", ret);
-
- return cmd_process_error(cmdtp, ret);
-}
-
-U_BOOT_LONGHELP(versal2,
- "loadpdi addr len - Load pdi image\n"
- "load pdi image at ddr address 'addr' with pdi image size 'len'\n");
-
-U_BOOT_CMD_WITH_SUBCMDS(versal2, "Versal Gen 2 sub-system", versal2_help_text,
- U_BOOT_SUBCMD_MKENT(loadpdi, 3, 1,
- do_versal2_load_pdi));
diff --git a/board/asus/grouper/Kconfig b/board/asus/grouper/Kconfig
index f935cce..3bd712b 100644
--- a/board/asus/grouper/Kconfig
+++ b/board/asus/grouper/Kconfig
@@ -7,6 +7,10 @@
default "asus"
config SYS_CONFIG_NAME
- default "grouper"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "ASUS Google Nexus 7 (2012)"
endif
diff --git a/board/asus/transformer-t114/Kconfig b/board/asus/transformer-t114/Kconfig
new file mode 100644
index 0000000..2560c35
--- /dev/null
+++ b/board/asus/transformer-t114/Kconfig
@@ -0,0 +1,16 @@
+if TARGET_TRANSFORMER_T114
+
+config SYS_BOARD
+ default "transformer-t114"
+
+config SYS_VENDOR
+ default "asus"
+
+config SYS_CONFIG_NAME
+ default "transformer-t114"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "ASUS Transformer T114"
+
+endif
diff --git a/board/asus/transformer-t114/MAINTAINERS b/board/asus/transformer-t114/MAINTAINERS
new file mode 100644
index 0000000..2e8f01b
--- /dev/null
+++ b/board/asus/transformer-t114/MAINTAINERS
@@ -0,0 +1,8 @@
+TRANSFORMER T114 BOARD
+M: Svyatoslav Ryhel <clamor95@gmail.com>
+S: Maintained
+F: arch/arm/dts/tegra114-asus-tf701t.dts
+F: board/asus/transformer-t114/
+F: configs/tf701t_defconfig
+F: doc/board/asus/transformer_t114.rst
+F: include/configs/transformer-t114.h
diff --git a/board/asus/transformer-t114/Makefile b/board/asus/transformer-t114/Makefile
new file mode 100644
index 0000000..37dda5f
--- /dev/null
+++ b/board/asus/transformer-t114/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+#
+# Copyright (c) 2023, Svyatoslav Ryhel <clamor95@gmail.com>
+#
+
+obj-$(CONFIG_XPL_BUILD) += transformer-t114-spl.o
+
+obj-y += transformer-t114.o
diff --git a/board/asus/transformer-t114/transformer-t114-spl.c b/board/asus/transformer-t114/transformer-t114-spl.c
new file mode 100644
index 0000000..ceddff3
--- /dev/null
+++ b/board/asus/transformer-t114/transformer-t114-spl.c
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * T114 Transformers SPL stage configuration
+ *
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2023
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include <linux/delay.h>
+
+#define TPS65913_I2C_ADDR (0x58 << 1)
+
+#define TPS65913_SMPS12_CTRL 0x20
+#define TPS65913_SMPS12_VOLTAGE 0x23
+#define TPS65913_SMPS45_CTRL 0x28
+#define TPS65913_SMPS45_VOLTAGE 0x2B
+
+#define TPS65913_SMPS12_CTRL_DATA (0x5100 | TPS65913_SMPS12_CTRL)
+#define TPS65913_SMPS12_VOLTAGE_DATA (0x3900 | TPS65913_SMPS12_VOLTAGE)
+#define TPS65913_SMPS45_CTRL_DATA (0x5100 | TPS65913_SMPS45_CTRL)
+#define TPS65913_SMPS45_VOLTAGE_DATA (0x4c00 | TPS65913_SMPS45_VOLTAGE)
+
+void pmic_enable_cpu_vdd(void)
+{
+ /* Set CORE VDD to 1.200V. */
+ tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_VOLTAGE_DATA);
+ udelay(1000);
+ tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_CTRL_DATA);
+
+ udelay(1000);
+
+ /* Set CPU VDD to 1.0125V. */
+ tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_VOLTAGE_DATA);
+ udelay(1000);
+ tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_CTRL_DATA);
+ udelay(10 * 1000);
+}
diff --git a/board/asus/transformer-t114/transformer-t114.c b/board/asus/transformer-t114/transformer-t114.c
new file mode 100644
index 0000000..cca64b5
--- /dev/null
+++ b/board/asus/transformer-t114/transformer-t114.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2023
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+/* T114 Transformers derive from Macallan board */
+
+#include <dm.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <log.h>
+
+#ifdef CONFIG_MMC_SDHCI_TEGRA
+
+#define TPS65913_I2C_ADDRESS 0x58
+#define TPS65913_PRIMARY_SECONDARY_PAD2 0xfb
+#define GPIO_4 BIT(0)
+#define TPS65913_PRIMARY_SECONDARY_PAD3 0xfe
+#define DVFS2 BIT(1)
+#define DVFS1 BIT(0)
+
+/* We are using this function only till palmas pinctrl driver is available */
+void pin_mux_mmc(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(0, TPS65913_I2C_ADDRESS, 1, &dev);
+ if (ret) {
+ log_debug("%s: cannot find PMIC I2C chip\n", __func__);
+ return;
+ }
+
+ /* GPIO4 function has to be GPIO */
+ dm_i2c_reg_clrset(dev, TPS65913_PRIMARY_SECONDARY_PAD2,
+ GPIO_4, 0);
+
+ /* DVFS1 is enabled, DVFS2 is disabled */
+ dm_i2c_reg_clrset(dev, TPS65913_PRIMARY_SECONDARY_PAD3,
+ DVFS2 | DVFS1, DVFS1);
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ /* Remove TrustZone nodes */
+ fdt_del_node_and_alias(blob, "/firmware");
+ fdt_del_node_and_alias(blob, "/reserved-memory/trustzone@bfe00000");
+
+ return 0;
+}
+#endif
diff --git a/board/asus/transformer-t114/transformer-t114.env b/board/asus/transformer-t114/transformer-t114.env
new file mode 100644
index 0000000..f7278b8
--- /dev/null
+++ b/board/asus/transformer-t114/transformer-t114.env
@@ -0,0 +1,15 @@
+button_cmd_0_name=Volume Down
+button_cmd_0=bootmenu
+button_cmd_1_name=Hall Sensor
+button_cmd_1=poweroff
+
+fastboot_partition_alias_boot=CAC
+fastboot_partition_alias_root=UDA
+
+bootmenu_0=mount internal storage=usb start && ums 0 mmc 0:e; bootmenu
+bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu
+bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu
+bootmenu_3=reboot RCM=enterrcm
+bootmenu_4=reboot=reset
+bootmenu_5=power off=poweroff
+bootmenu_delay=-1
diff --git a/board/asus/transformer-t20/Kconfig b/board/asus/transformer-t20/Kconfig
index d5fe412..3e80d38 100644
--- a/board/asus/transformer-t20/Kconfig
+++ b/board/asus/transformer-t20/Kconfig
@@ -7,6 +7,10 @@
default "asus"
config SYS_CONFIG_NAME
- default "transformer-t20"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "ASUS Transformer T20"
endif
diff --git a/board/asus/transformer-t30/Kconfig b/board/asus/transformer-t30/Kconfig
index 915436b..34fd6f2 100644
--- a/board/asus/transformer-t30/Kconfig
+++ b/board/asus/transformer-t30/Kconfig
@@ -7,6 +7,10 @@
default "asus"
config SYS_CONFIG_NAME
- default "transformer-t30"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "ASUS Transformer T30"
endif
diff --git a/board/avionic-design/medcom-wide/Kconfig b/board/avionic-design/medcom-wide/Kconfig
index 267647c..54474b5 100644
--- a/board/avionic-design/medcom-wide/Kconfig
+++ b/board/avionic-design/medcom-wide/Kconfig
@@ -7,6 +7,10 @@
default "avionic-design"
config SYS_CONFIG_NAME
- default "medcom-wide"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "Avionic Design Medcom-Wide"
endif
diff --git a/board/avionic-design/plutux/Kconfig b/board/avionic-design/plutux/Kconfig
index 09a3ac9..35b19dd 100644
--- a/board/avionic-design/plutux/Kconfig
+++ b/board/avionic-design/plutux/Kconfig
@@ -7,6 +7,10 @@
default "avionic-design"
config SYS_CONFIG_NAME
- default "plutux"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "Avionic Design Plutux"
endif
diff --git a/board/avionic-design/tec-ng/Kconfig b/board/avionic-design/tec-ng/Kconfig
index 36a0cec..8782e7a 100644
--- a/board/avionic-design/tec-ng/Kconfig
+++ b/board/avionic-design/tec-ng/Kconfig
@@ -7,6 +7,10 @@
default "avionic-design"
config SYS_CONFIG_NAME
- default "tec-ng"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "Avionic Design Tamonten™ NG Evaluation Carrier"
endif
diff --git a/board/avionic-design/tec/Kconfig b/board/avionic-design/tec/Kconfig
index bc9751b..12cc4e1 100644
--- a/board/avionic-design/tec/Kconfig
+++ b/board/avionic-design/tec/Kconfig
@@ -7,6 +7,10 @@
default "avionic-design"
config SYS_CONFIG_NAME
- default "tec"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "Avionic Design Tamonten Evaluation Carrier"
endif
diff --git a/board/beagle/beagleboneai64/beagleboneai64.c b/board/beagle/beagleboneai64/beagleboneai64.c
index e8d07f1..99eb897 100644
--- a/board/beagle/beagleboneai64/beagleboneai64.c
+++ b/board/beagle/beagleboneai64/beagleboneai64.c
@@ -45,14 +45,6 @@
.images = fw_images,
};
-#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO)
-void set_dfu_alt_info(char *interface, char *devstr)
-{
- if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
- env_set("dfu_alt_info", update_info.dfu_string);
-}
-#endif
-
int board_init(void)
{
return 0;
diff --git a/board/beagle/beagleplay/beagleplay.c b/board/beagle/beagleplay/beagleplay.c
index fae69b3..7863581 100644
--- a/board/beagle/beagleplay/beagleplay.c
+++ b/board/beagle/beagleplay/beagleplay.c
@@ -41,14 +41,6 @@
.images = fw_images,
};
-#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO)
-void set_dfu_alt_info(char *interface, char *devstr)
-{
- if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
- env_set("dfu_alt_info", update_info.dfu_string);
-}
-#endif
-
int board_init(void)
{
return 0;
diff --git a/board/bosch/guardian/Makefile b/board/bosch/guardian/Makefile
index 8e38881..87c34c7 100644
--- a/board/bosch/guardian/Makefile
+++ b/board/bosch/guardian/Makefile
@@ -5,7 +5,7 @@
# Copyright (C) 2018 Robert Bosch Power Tools GmbH
#
-ifeq ($(CONFIG_$(XPL_)SKIP_LOWLEVEL_INIT),)
+ifeq ($(CONFIG_$(PHASE_)SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif
diff --git a/board/cei/cei-tk1-som/Kconfig b/board/cei/cei-tk1-som/Kconfig
index 5fcb51f..9b94473 100644
--- a/board/cei/cei-tk1-som/Kconfig
+++ b/board/cei/cei-tk1-som/Kconfig
@@ -7,6 +7,10 @@
default "cei"
config SYS_CONFIG_NAME
- default "cei-tk1-som"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "CEI tk1-som"
endif
diff --git a/board/compal/paz00/Kconfig b/board/compal/paz00/Kconfig
index 30ba11d..7fa47fc 100644
--- a/board/compal/paz00/Kconfig
+++ b/board/compal/paz00/Kconfig
@@ -7,6 +7,10 @@
default "compal"
config SYS_CONFIG_NAME
- default "paz00"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "Compal Paz00"
endif
diff --git a/board/compulab/trimslice/Kconfig b/board/compulab/trimslice/Kconfig
index 3576914..226ebc2 100644
--- a/board/compulab/trimslice/Kconfig
+++ b/board/compulab/trimslice/Kconfig
@@ -7,6 +7,10 @@
default "compulab"
config SYS_CONFIG_NAME
- default "trimslice"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "Compulab Trimslice"
endif
diff --git a/board/emulation/qemu-arm/MAINTAINERS b/board/emulation/qemu-arm/MAINTAINERS
index 7bc0ee6..538769f 100644
--- a/board/emulation/qemu-arm/MAINTAINERS
+++ b/board/emulation/qemu-arm/MAINTAINERS
@@ -5,6 +5,5 @@
F: board/emulation/common/
F: include/configs/qemu-arm.h
F: include/configs/qemu-sbsa.h
-F: configs/qemu_arm_defconfig
-F: configs/qemu_arm64_defconfig
+F: configs/qemu_arm*
F: configs/qemu-arm-sbsa_defconfig
diff --git a/board/emulation/qemu-riscv/MAINTAINERS b/board/emulation/qemu-riscv/MAINTAINERS
index 3d7453f..d75d1b5 100644
--- a/board/emulation/qemu-riscv/MAINTAINERS
+++ b/board/emulation/qemu-riscv/MAINTAINERS
@@ -4,9 +4,4 @@
F: board/emulation/qemu-riscv/
F: board/emulation/common/
F: include/configs/qemu-riscv.h
-F: configs/qemu-riscv32_defconfig
-F: configs/qemu-riscv32_smode_defconfig
-F: configs/qemu-riscv32_spl_defconfig
-F: configs/qemu-riscv64_defconfig
-F: configs/qemu-riscv64_smode_defconfig
-F: configs/qemu-riscv64_spl_defconfig
+F: configs/qemu-riscv*
diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c
index a90222e..70190eb 100644
--- a/board/emulation/qemu-riscv/qemu-riscv.c
+++ b/board/emulation/qemu-riscv/qemu-riscv.c
@@ -63,11 +63,3 @@
return 0;
}
#endif
-
-int board_fdt_blob_setup(void **fdtp)
-{
- /* Stored the DTB address there during our init */
- *fdtp = (void *)(ulong)gd->arch.firmware_fdt_addr;
-
- return 0;
-}
diff --git a/board/firefly/roc-pc-rk3576/Kconfig b/board/firefly/roc-pc-rk3576/Kconfig
new file mode 100644
index 0000000..2fc0f91
--- /dev/null
+++ b/board/firefly/roc-pc-rk3576/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ROC_PC_RK3576
+
+config SYS_BOARD
+ default "roc-pc-rk3576"
+
+config SYS_VENDOR
+ default "firefly"
+
+config SYS_CONFIG_NAME
+ default "roc-pc-rk3576"
+
+endif
diff --git a/board/firefly/roc-pc-rk3576/MAINTAINERS b/board/firefly/roc-pc-rk3576/MAINTAINERS
new file mode 100644
index 0000000..aa8897c
--- /dev/null
+++ b/board/firefly/roc-pc-rk3576/MAINTAINERS
@@ -0,0 +1,7 @@
+ROC-RK3576-PC
+M: Heiko Stuebner <heiko@sntech.de>
+S: Maintained
+F: board/firefly/roc-pc-rk3576
+F: include/configs/roc-pc-rk3576.h
+F: configs/roc-pc-rk3576_defconfig
+F: arch/arm/dts/rk3576-roc-pc*
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 468a067..b04e19e 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -34,7 +34,7 @@
endif
obj-$(I2C_COMMON) += i2c_common.o
obj-$(CONFIG_FSL_USE_PCA9547_MUX) += i2c_mux.o
-obj-$(CONFIG_$(XPL_)VID) += vid.o
+obj-$(CONFIG_$(PHASE_)VID) += vid.o
obj-$(CONFIG_FSL_QIXIS) += qixis.o
ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o
@@ -54,7 +54,7 @@
obj-$(CONFIG_TARGET_P3041DS) += ics307_clk.o
obj-$(CONFIG_TARGET_P4080DS) += ics307_clk.o
obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o
-ifeq ($(CONFIG_$(XPL_)POWER_LEGACY),y)
+ifeq ($(CONFIG_$(PHASE_)POWER_LEGACY),y)
obj-$(CONFIG_POWER_PFUZE100) += pfuze.o
endif
obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze.o
diff --git a/board/freescale/mx51evk/MAINTAINERS b/board/freescale/mx51evk/MAINTAINERS
index 1ca55f7..025a5f8 100644
--- a/board/freescale/mx51evk/MAINTAINERS
+++ b/board/freescale/mx51evk/MAINTAINERS
@@ -1,6 +1,5 @@
MX51EVK BOARD
M: Fabio Estevam <festevam@gmail.com>
-M: Stefano Babic <sbabic@denx.de>
S: Maintained
F: board/freescale/mx51evk/
F: include/configs/mx51evk.h
diff --git a/board/htc/endeavoru/Kconfig b/board/htc/endeavoru/Kconfig
index 0b72c4a..ef50da9 100644
--- a/board/htc/endeavoru/Kconfig
+++ b/board/htc/endeavoru/Kconfig
@@ -7,6 +7,10 @@
default "htc"
config SYS_CONFIG_NAME
- default "endeavoru"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "HTC One X"
endif
diff --git a/board/imgtec/boston/Kconfig b/board/imgtec/boston/Kconfig
index 5537788..965847d 100644
--- a/board/imgtec/boston/Kconfig
+++ b/board/imgtec/boston/Kconfig
@@ -9,6 +9,10 @@
config SYS_CONFIG_NAME
default "boston"
+
+config ENV_SOURCE_FILE
+ default "boston"
+
config TEXT_BASE
default 0x9fc00000 if 32BIT
default 0xffffffff9fc00000 if 64BIT
diff --git a/board/imgtec/boston/MAINTAINERS b/board/imgtec/boston/MAINTAINERS
index 07f6156..b03a648 100644
--- a/board/imgtec/boston/MAINTAINERS
+++ b/board/imgtec/boston/MAINTAINERS
@@ -1,6 +1,7 @@
BOSTON BOARD
-M: Paul Burton <paul.burton@mips.com>
+M: Paul Burton <paulburton@kernel.org>
S: Maintained
+F: arch/mips/dts/boston-u-boot.dtsi
F: board/imgtec/boston/
F: include/configs/boston.h
F: configs/boston32r2_defconfig
diff --git a/board/imgtec/boston/boston.env b/board/imgtec/boston/boston.env
new file mode 100644
index 0000000..796e0fd
--- /dev/null
+++ b/board/imgtec/boston/boston.env
@@ -0,0 +1,9 @@
+#ifdef CONFIG_64BIT
+fdt_addr_r=0xffffffff80001000
+kernel_addr_r=0xffffffff88000000
+ramdisk_addr_r=0xffffffff8b000000
+#else
+fdt_addr_r=0x80001000
+kernel_addr_r=0x88000000
+ramdisk_addr_r=0x8b000000
+#endif
diff --git a/board/imgtec/malta/MAINTAINERS b/board/imgtec/malta/MAINTAINERS
index b1cf297..252c5e4 100644
--- a/board/imgtec/malta/MAINTAINERS
+++ b/board/imgtec/malta/MAINTAINERS
@@ -1,5 +1,5 @@
MALTA BOARD
-M: Paul Burton <paul.burton@mips.com>
+M: Paul Burton <paulburton@kernel.org>
S: Maintained
F: board/imgtec/malta/
F: include/configs/malta.h
diff --git a/board/kobol/helios4/helios4.c b/board/kobol/helios4/helios4.c
index 4c8407b..7714076 100644
--- a/board/kobol/helios4/helios4.c
+++ b/board/kobol/helios4/helios4.c
@@ -73,7 +73,11 @@
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
NOT_COMBINED, /* ddr twin-die combined */
{ {0} }, /* raw spd data */
- {0} /* timing parameters */
+ {0}, /* timing parameters */
+ { {0} }, /* electrical configuration */
+ {0,}, /* electrical parameters */
+ 0x30000, /* ODT configuration */
+ 0x3, /* clock enable mask */
};
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
diff --git a/board/lenovo/ideapad-yoga-11/Kconfig b/board/lenovo/ideapad-yoga-11/Kconfig
index 6764440..cd4aa32 100644
--- a/board/lenovo/ideapad-yoga-11/Kconfig
+++ b/board/lenovo/ideapad-yoga-11/Kconfig
@@ -7,6 +7,10 @@
default "lenovo"
config SYS_CONFIG_NAME
- default "ideapad-yoga-11"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "Lenovo Ideapad Yoga 11"
endif
diff --git a/board/lg/x3-t30/Kconfig b/board/lg/x3-t30/Kconfig
index 53b6ab3..d2cdf86 100644
--- a/board/lg/x3-t30/Kconfig
+++ b/board/lg/x3-t30/Kconfig
@@ -7,6 +7,10 @@
default "lg"
config SYS_CONFIG_NAME
- default "x3-t30"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "LG X3 Board"
endif
diff --git a/board/libre-computer/aml-a311d-cc/aml-a311d-cc.c b/board/libre-computer/aml-a311d-cc/aml-a311d-cc.c
index 294f788..b3b78bf 100644
--- a/board/libre-computer/aml-a311d-cc/aml-a311d-cc.c
+++ b/board/libre-computer/aml-a311d-cc/aml-a311d-cc.c
@@ -31,8 +31,6 @@
{
if (interface && strcmp(interface, "ram") == 0)
env_set("dfu_alt_info", "fitimage ram 0x08080000 0x4000000");
- else if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
- env_set("dfu_alt_info", update_info.dfu_string);
}
#endif
diff --git a/board/libre-computer/aml-s805x-ac/aml-s805x-ac.c b/board/libre-computer/aml-s805x-ac/aml-s805x-ac.c
index 1ec9a5b..daece29 100644
--- a/board/libre-computer/aml-s805x-ac/aml-s805x-ac.c
+++ b/board/libre-computer/aml-s805x-ac/aml-s805x-ac.c
@@ -38,8 +38,6 @@
{
if (interface && strcmp(interface, "ram") == 0)
env_set("dfu_alt_info", "fitimage ram 0x08080000 0x4000000");
- else if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
- env_set("dfu_alt_info", update_info.dfu_string);
}
#endif
diff --git a/board/libre-computer/aml-s905d3-cc/aml-s905d3-cc.c b/board/libre-computer/aml-s905d3-cc/aml-s905d3-cc.c
index b552035..09a69b0 100644
--- a/board/libre-computer/aml-s905d3-cc/aml-s905d3-cc.c
+++ b/board/libre-computer/aml-s905d3-cc/aml-s905d3-cc.c
@@ -31,8 +31,6 @@
{
if (interface && strcmp(interface, "ram") == 0)
env_set("dfu_alt_info", "fitimage ram 0x08080000 0x4000000");
- else if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
- env_set("dfu_alt_info", update_info.dfu_string);
}
#endif
diff --git a/board/microsoft/surface-rt/Kconfig b/board/microsoft/surface-rt/Kconfig
index 9e66897..6afddb9 100644
--- a/board/microsoft/surface-rt/Kconfig
+++ b/board/microsoft/surface-rt/Kconfig
@@ -7,6 +7,10 @@
default "microsoft"
config SYS_CONFIG_NAME
- default "surface-rt"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "Microsoft Surface RT"
endif
diff --git a/board/motorola/mot/Kconfig b/board/motorola/mot/Kconfig
new file mode 100644
index 0000000..3f6f03e
--- /dev/null
+++ b/board/motorola/mot/Kconfig
@@ -0,0 +1,16 @@
+if TARGET_MOT
+
+config SYS_BOARD
+ default "mot"
+
+config SYS_VENDOR
+ default "motorola"
+
+config SYS_CONFIG_NAME
+ default "mot"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "Motorola Mot"
+
+endif
diff --git a/board/motorola/mot/MAINTAINERS b/board/motorola/mot/MAINTAINERS
new file mode 100644
index 0000000..2aff81a
--- /dev/null
+++ b/board/motorola/mot/MAINTAINERS
@@ -0,0 +1,7 @@
+MOT BOARD
+M: Svyatoslav Ryhel <clamor95@gmail.com>
+S: Maintained
+F: board/motorola/mot/
+F: configs/mot_defconfig
+F: doc/board/motorola/mot.rst
+F: include/configs/mot.h
diff --git a/board/motorola/mot/Makefile b/board/motorola/mot/Makefile
new file mode 100644
index 0000000..f1073c2
--- /dev/null
+++ b/board/motorola/mot/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2010-2012
+# NVIDIA Corporation <www.nvidia.com>
+#
+# (C) Copyright 2025
+# Svyatoslav Ryhel <clamor95@gmail.com>
+
+obj-$(CONFIG_XPL_BUILD) += mot-spl.o
diff --git a/board/motorola/mot/configs/daytona.config b/board/motorola/mot/configs/daytona.config
new file mode 100644
index 0000000..0b6131b
--- /dev/null
+++ b/board/motorola/mot/configs/daytona.config
@@ -0,0 +1,2 @@
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-motorola-daytona"
+CONFIG_SYS_PROMPT="Tegra20 (Daytona) # "
diff --git a/board/motorola/mot/configs/olympus.config b/board/motorola/mot/configs/olympus.config
new file mode 100644
index 0000000..57aa601
--- /dev/null
+++ b/board/motorola/mot/configs/olympus.config
@@ -0,0 +1,2 @@
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-motorola-olympus"
+CONFIG_SYS_PROMPT="Tegra20 (Olympus) # "
diff --git a/board/motorola/mot/mot-spl.c b/board/motorola/mot/mot-spl.c
new file mode 100644
index 0000000..a86e523
--- /dev/null
+++ b/board/motorola/mot/mot-spl.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * T20 Motorola Atrix 4G and Droid X2 SPL stage configuration
+ *
+ * (C) Copyright 2025
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <asm/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/pmc.h>
+#include <spl_gpio.h>
+#include <linux/delay.h>
+
+/*
+ * Unlike all other supported Tegra devices and most known Tegra devices, the
+ * both Atrix 4G and Droid X2 have no hardware way to enter APX/RCM mode, which
+ * may lead to a dangerous situation when, if BCT is set correctly and the
+ * bootloader is faulty, the device will hang in a permanent brick state.
+ * Exiting from this state can be done only by disassembling the device and
+ * shortening testpad to the ground.
+ *
+ * To prevent this or to minimize the probability of such an accident, it was
+ * proposed to add the RCM rebooting hook as early into SPL as possible since
+ * SPL is much more robust and has minimal changes that can break bootflow.
+ *
+ * gpio_early_init_uart() function was chosen as it is the earliest function
+ * exposed for setup by the device. Hook performs a check for volume up
+ * button state and triggers RCM if it is pressed.
+ */
+void gpio_early_init_uart(void)
+{
+ int value;
+
+ /* Configure pinmux for PR0 */
+ pinmux_set_func(PMUX_PINGRP_KBCA, PMUX_FUNC_KBC);
+ pinmux_set_pullupdown(PMUX_PINGRP_KBCA, PMUX_PULL_UP);
+ pinmux_tristate_disable(PMUX_PINGRP_KBCA);
+
+ /* Configure pinmux for PQ0 */
+ pinmux_set_func(PMUX_PINGRP_KBCC, PMUX_FUNC_KBC);
+ pinmux_set_pullupdown(PMUX_PINGRP_KBCC, PMUX_PULL_UP);
+ pinmux_tristate_disable(PMUX_PINGRP_KBCC);
+
+ /* Hog column 0 (PQ0) low - active */
+ spl_gpio_output(NULL, TEGRA_GPIO(Q, 0), 0);
+ udelay(500);
+
+ spl_gpio_input(NULL, TEGRA_GPIO(R, 0));
+ value = spl_gpio_get_value(NULL, TEGRA_GPIO(R, 0));
+
+ /* Enter RCM if button is pressed */
+ if (!value) {
+ tegra_pmc_writel(2, PMC_SCRATCH0);
+ tegra_pmc_writel(PMC_CNTRL_MAIN_RST, PMC_CNTRL);
+ }
+}
diff --git a/board/motorola/mot/mot.env b/board/motorola/mot/mot.env
new file mode 100644
index 0000000..f2bf298
--- /dev/null
+++ b/board/motorola/mot/mot.env
@@ -0,0 +1,15 @@
+#include <env/nvidia/prod_upd.env>
+
+button_cmd_0_name=Volume Down
+button_cmd_0=bootmenu
+partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}
+boot_dev=1
+
+bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu
+bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu
+bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu
+bootmenu_3=update bootloader=run flash_uboot
+bootmenu_4=reboot RCM=enterrcm
+bootmenu_5=reboot=reset
+bootmenu_6=power off=poweroff
+bootmenu_delay=-1
diff --git a/board/nvidia/beaver/Kconfig b/board/nvidia/beaver/Kconfig
index 23f7c94..fe36d47 100644
--- a/board/nvidia/beaver/Kconfig
+++ b/board/nvidia/beaver/Kconfig
@@ -7,6 +7,10 @@
default "nvidia"
config SYS_CONFIG_NAME
- default "beaver"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "NVIDIA Beaver"
endif
diff --git a/board/nvidia/cardhu/Kconfig b/board/nvidia/cardhu/Kconfig
index 63ace66..92de3f2 100644
--- a/board/nvidia/cardhu/Kconfig
+++ b/board/nvidia/cardhu/Kconfig
@@ -7,6 +7,10 @@
default "nvidia"
config SYS_CONFIG_NAME
- default "cardhu"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "NVIDIA Cardhu"
endif
diff --git a/board/nvidia/dalmore/Kconfig b/board/nvidia/dalmore/Kconfig
index 96eaa01..8da3499 100644
--- a/board/nvidia/dalmore/Kconfig
+++ b/board/nvidia/dalmore/Kconfig
@@ -7,6 +7,10 @@
default "nvidia"
config SYS_CONFIG_NAME
- default "dalmore"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "NVIDIA Dalmore"
endif
diff --git a/board/nvidia/harmony/Kconfig b/board/nvidia/harmony/Kconfig
index 328c946..eedee71 100644
--- a/board/nvidia/harmony/Kconfig
+++ b/board/nvidia/harmony/Kconfig
@@ -7,6 +7,10 @@
default "nvidia"
config SYS_CONFIG_NAME
- default "harmony"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "NVIDIA Harmony"
endif
diff --git a/board/nvidia/jetson-tk1/Kconfig b/board/nvidia/jetson-tk1/Kconfig
index d90a74e..9eeb55f 100644
--- a/board/nvidia/jetson-tk1/Kconfig
+++ b/board/nvidia/jetson-tk1/Kconfig
@@ -7,6 +7,10 @@
default "nvidia"
config SYS_CONFIG_NAME
- default "jetson-tk1"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "NVIDIA Jetson TK1"
endif
diff --git a/board/nvidia/nyan-big/Kconfig b/board/nvidia/nyan-big/Kconfig
index 341c8d7..65fef3c 100644
--- a/board/nvidia/nyan-big/Kconfig
+++ b/board/nvidia/nyan-big/Kconfig
@@ -7,6 +7,10 @@
default "nvidia"
config SYS_CONFIG_NAME
- default "nyan-big"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "Google/NVIDIA Nyan-big"
endif
diff --git a/board/nvidia/p2371-0000/Kconfig b/board/nvidia/p2371-0000/Kconfig
index f94be12..e277078 100644
--- a/board/nvidia/p2371-0000/Kconfig
+++ b/board/nvidia/p2371-0000/Kconfig
@@ -7,6 +7,10 @@
default "nvidia"
config SYS_CONFIG_NAME
- default "p2371-0000"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "NVIDIA P2371-0000"
endif
diff --git a/board/nvidia/p2371-2180/Kconfig b/board/nvidia/p2371-2180/Kconfig
index 8622bda..8d97dc3 100644
--- a/board/nvidia/p2371-2180/Kconfig
+++ b/board/nvidia/p2371-2180/Kconfig
@@ -7,6 +7,10 @@
default "nvidia"
config SYS_CONFIG_NAME
- default "p2371-2180"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "NVIDIA P2371-2180"
endif
diff --git a/board/nvidia/p2571/Kconfig b/board/nvidia/p2571/Kconfig
index 7bc4874..1d41e9d 100644
--- a/board/nvidia/p2571/Kconfig
+++ b/board/nvidia/p2571/Kconfig
@@ -7,6 +7,10 @@
default "nvidia"
config SYS_CONFIG_NAME
- default "p2571"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "NVIDIA P2571"
endif
diff --git a/board/nvidia/p2771-0000/Kconfig b/board/nvidia/p2771-0000/Kconfig
index 1b1116f..199e04d 100644
--- a/board/nvidia/p2771-0000/Kconfig
+++ b/board/nvidia/p2771-0000/Kconfig
@@ -11,6 +11,10 @@
default "nvidia"
config SYS_CONFIG_NAME
- default "p2771-0000"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "NVIDIA P2771-0000"
endif
diff --git a/board/nvidia/p3450-0000/Kconfig b/board/nvidia/p3450-0000/Kconfig
index 7a08cd8..9235c2a 100644
--- a/board/nvidia/p3450-0000/Kconfig
+++ b/board/nvidia/p3450-0000/Kconfig
@@ -7,6 +7,10 @@
default "nvidia"
config SYS_CONFIG_NAME
- default "p3450-0000"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "NVIDIA P3450-0000"
endif
diff --git a/board/nvidia/seaboard/Kconfig b/board/nvidia/seaboard/Kconfig
index 0924bde..a6baeeb 100644
--- a/board/nvidia/seaboard/Kconfig
+++ b/board/nvidia/seaboard/Kconfig
@@ -7,6 +7,10 @@
default "nvidia"
config SYS_CONFIG_NAME
- default "seaboard"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "NVIDIA Seaboard"
endif
diff --git a/board/nvidia/tegratab/Kconfig b/board/nvidia/tegratab/Kconfig
new file mode 100644
index 0000000..8bd7cfd
--- /dev/null
+++ b/board/nvidia/tegratab/Kconfig
@@ -0,0 +1,16 @@
+if TARGET_TEGRATAB
+
+config SYS_BOARD
+ default "tegratab"
+
+config SYS_VENDOR
+ default "nvidia"
+
+config SYS_CONFIG_NAME
+ default "tegratab"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "NVIDIA TegraTab"
+
+endif
diff --git a/board/nvidia/tegratab/MAINTAINERS b/board/nvidia/tegratab/MAINTAINERS
new file mode 100644
index 0000000..bfd9eae
--- /dev/null
+++ b/board/nvidia/tegratab/MAINTAINERS
@@ -0,0 +1,8 @@
+TEGRATAB BOARD
+M: Svyatoslav Ryhel <clamor95@gmail.com>
+S: Maintained
+F: arch/arm/dts/tegra114-nvidia-tegratab.dts
+F: board/nvidia/tegratab/
+F: configs/tegratab_defconfig
+F: doc/board/nvidia/tegratab.rst
+F: include/configs/tegratab.h
diff --git a/board/nvidia/tegratab/Makefile b/board/nvidia/tegratab/Makefile
new file mode 100644
index 0000000..183a0ba
--- /dev/null
+++ b/board/nvidia/tegratab/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+#
+# Copyright (c) 2023, Svyatoslav Ryhel <clamor95@gmail.com>
+#
+
+obj-$(CONFIG_XPL_BUILD) += tegratab-spl.o
+
+obj-y += tegratab.o
diff --git a/board/nvidia/tegratab/tegratab-spl.c b/board/nvidia/tegratab/tegratab-spl.c
new file mode 100644
index 0000000..423b307
--- /dev/null
+++ b/board/nvidia/tegratab/tegratab-spl.c
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * TegraTab SPL stage configuration
+ *
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2023
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include <linux/delay.h>
+
+#define TPS65913_I2C_ADDR (0x58 << 1)
+
+#define TPS65913_SMPS12_CTRL 0x20
+#define TPS65913_SMPS12_VOLTAGE 0x23
+#define TPS65913_SMPS45_CTRL 0x28
+#define TPS65913_SMPS45_VOLTAGE 0x2B
+
+#define TPS65913_SMPS12_CTRL_DATA (0x5100 | TPS65913_SMPS12_CTRL)
+#define TPS65913_SMPS12_VOLTAGE_DATA (0x3900 | TPS65913_SMPS12_VOLTAGE)
+#define TPS65913_SMPS45_CTRL_DATA (0x5100 | TPS65913_SMPS45_CTRL)
+#define TPS65913_SMPS45_VOLTAGE_DATA (0x4c00 | TPS65913_SMPS45_VOLTAGE)
+
+void pmic_enable_cpu_vdd(void)
+{
+ /* Set CORE VDD to 1.200V. */
+ tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_VOLTAGE_DATA);
+ udelay(1000);
+ tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_CTRL_DATA);
+
+ udelay(1000);
+
+ /* Set CPU VDD to 1.0125V. */
+ tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_VOLTAGE_DATA);
+ udelay(1000);
+ tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_CTRL_DATA);
+ udelay(10 * 1000);
+}
diff --git a/board/nvidia/tegratab/tegratab.c b/board/nvidia/tegratab/tegratab.c
new file mode 100644
index 0000000..775e5be
--- /dev/null
+++ b/board/nvidia/tegratab/tegratab.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2023
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <log.h>
+
+#ifdef CONFIG_MMC_SDHCI_TEGRA
+
+#define TPS65913_I2C_ADDRESS 0x58
+#define TPS65913_PRIMARY_SECONDARY_PAD2 0xfb
+#define GPIO_4 BIT(0)
+#define TPS65913_PRIMARY_SECONDARY_PAD3 0xfe
+#define DVFS2 BIT(1)
+#define DVFS1 BIT(0)
+
+/* We are using this function only till palmas pinctrl driver is available */
+void pin_mux_mmc(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(0, TPS65913_I2C_ADDRESS, 1, &dev);
+ if (ret) {
+ log_debug("%s: cannot find PMIC I2C chip\n", __func__);
+ return;
+ }
+
+ /* GPIO4 function has to be GPIO */
+ dm_i2c_reg_clrset(dev, TPS65913_PRIMARY_SECONDARY_PAD2,
+ GPIO_4, 0);
+
+ /* DVFS1 is enabled, DVFS2 is disabled */
+ dm_i2c_reg_clrset(dev, TPS65913_PRIMARY_SECONDARY_PAD3,
+ DVFS2 | DVFS1, DVFS1);
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ /* Remove TrustZone nodes and memory reserves */
+ fdt_del_node_and_alias(blob, "/firmware");
+ fdt_del_node_and_alias(blob, "/reserved-memory/trustzone@bfe00000");
+ fdt_del_node_and_alias(blob, "/reserved-memory/bootloader-firmware@b7e00000");
+
+ return 0;
+}
+#endif
diff --git a/board/nvidia/tegratab/tegratab.env b/board/nvidia/tegratab/tegratab.env
new file mode 100644
index 0000000..b2ba4f4
--- /dev/null
+++ b/board/nvidia/tegratab/tegratab.env
@@ -0,0 +1,15 @@
+button_cmd_0_name=Volume Down
+button_cmd_0=bootmenu
+button_cmd_1_name=Hall Sensor
+button_cmd_1=poweroff
+
+fastboot_partition_alias_boot=CAC
+fastboot_partition_alias_root=UDA
+
+bootmenu_0=mount internal storage=usb start && ums 0 mmc 0:c; bootmenu
+bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu
+bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu
+bootmenu_3=reboot RCM=enterrcm
+bootmenu_4=reboot=reset
+bootmenu_5=power off=poweroff
+bootmenu_delay=-1
diff --git a/board/nvidia/venice2/Kconfig b/board/nvidia/venice2/Kconfig
index 6905f00..9ebaa2f 100644
--- a/board/nvidia/venice2/Kconfig
+++ b/board/nvidia/venice2/Kconfig
@@ -7,6 +7,10 @@
default "nvidia"
config SYS_CONFIG_NAME
- default "venice2"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "NVIDIA Venice2"
endif
diff --git a/board/nvidia/ventana/Kconfig b/board/nvidia/ventana/Kconfig
index c1ad7b7..b8654c2 100644
--- a/board/nvidia/ventana/Kconfig
+++ b/board/nvidia/ventana/Kconfig
@@ -7,6 +7,10 @@
default "nvidia"
config SYS_CONFIG_NAME
- default "ventana"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "NVIDIA Ventana"
endif
diff --git a/board/ouya/ouya/Kconfig b/board/ouya/ouya/Kconfig
index 6bab40c..c698f73 100644
--- a/board/ouya/ouya/Kconfig
+++ b/board/ouya/ouya/Kconfig
@@ -7,6 +7,10 @@
default "ouya"
config SYS_CONFIG_NAME
- default "ouya"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "Ouya Game Console"
endif
diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c
index 7d2146d..828973a 100644
--- a/board/phytec/common/k3/board.c
+++ b/board/phytec/common/k3/board.c
@@ -82,14 +82,6 @@
}
#endif
-#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO)
-void set_dfu_alt_info(char *interface, char *devstr)
-{
- if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
- env_set("dfu_alt_info", update_info.dfu_string);
-}
-#endif
-
#if IS_ENABLED(CONFIG_ENV_IS_IN_FAT) || IS_ENABLED(CONFIG_ENV_IS_IN_MMC)
int mmc_get_env_dev(void)
{
diff --git a/board/phytec/common/phytec_som_detection.c b/board/phytec/common/phytec_som_detection.c
index 1f22139..4d7c9b9 100644
--- a/board/phytec/common/phytec_som_detection.c
+++ b/board/phytec/common/phytec_som_detection.c
@@ -295,17 +295,16 @@
switch (api2->som_type) {
case 0:
+ case 1:
+ case 2:
+ case 3:
som_type = api2->som_type;
break;
case 4:
- som_type = 0;
- break;
case 5:
som_type = 0;
break;
case 6:
- som_type = 1;
- break;
case 7:
som_type = 1;
break;
diff --git a/board/phytec/phycore_am62ax/MAINTAINERS b/board/phytec/phycore_am62ax/MAINTAINERS
index 7c8a29b..feb1e0b 100644
--- a/board/phytec/phycore_am62ax/MAINTAINERS
+++ b/board/phytec/phycore_am62ax/MAINTAINERS
@@ -10,6 +10,7 @@
F: board/phytec/phycore_am62ax/
F: configs/phycore_am62ax_a53_defconfig
F: configs/phycore_am62ax_r5_defconfig
+F: configs/phycore_am62ax_r5_ethboot_defconfig
F: configs/phycore_am62ax_r5_usbdfu_defconfig
F: include/configs/phycore_am62ax.h
F: doc/board/phytec/phycore-am62ax.rst
diff --git a/board/phytec/phycore_am62ax/rm-cfg.yaml b/board/phytec/phycore_am62ax/rm-cfg.yaml
index cbd087d..0f34b8c 100644
--- a/board/phytec/phycore_am62ax/rm-cfg.yaml
+++ b/board/phytec/phycore_am62ax/rm-cfg.yaml
@@ -713,7 +713,7 @@
start_resource: 19
num_resource: 64
type: 1937
- host_id: 30
+ host_id: 36
reserved: 0
-
start_resource: 83
@@ -767,7 +767,7 @@
start_resource: 118
num_resource: 16
type: 1943
- host_id: 30
+ host_id: 36
reserved: 0
-
start_resource: 134
@@ -833,7 +833,7 @@
start_resource: 19
num_resource: 8
type: 1956
- host_id: 30
+ host_id: 36
reserved: 0
-
start_resource: 27
@@ -917,7 +917,7 @@
start_resource: 19
num_resource: 1
type: 1963
- host_id: 30
+ host_id: 36
reserved: 0
-
start_resource: 19
@@ -929,7 +929,7 @@
start_resource: 19
num_resource: 16
type: 1964
- host_id: 30
+ host_id: 36
reserved: 0
-
start_resource: 20
diff --git a/board/phytec/phycore_am62ax/tifs-rm-cfg.yaml b/board/phytec/phycore_am62ax/tifs-rm-cfg.yaml
index 151cd59..23dcd78 100644
--- a/board/phytec/phycore_am62ax/tifs-rm-cfg.yaml
+++ b/board/phytec/phycore_am62ax/tifs-rm-cfg.yaml
@@ -24,26 +24,26 @@
allowed_priority: 0xAAAA
allowed_sched_priority: 0xAA
- # 2
- host_id: 30
+ host_id: 20
allowed_atype: 0x2A
allowed_qos: 0xAAAA
allowed_orderid: 0xAAAAAAAA
allowed_priority: 0xAAAA
allowed_sched_priority: 0xAA
- # 3
- host_id: 36
+ host_id: 30
allowed_atype: 0x2A
allowed_qos: 0xAAAA
allowed_orderid: 0xAAAAAAAA
allowed_priority: 0xAAAA
allowed_sched_priority: 0xAA
- # 4
- host_id: 0
- allowed_atype: 0
- allowed_qos: 0
- allowed_orderid: 0
- allowed_priority: 0
- allowed_sched_priority: 0
+ host_id: 36
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
- # 5
host_id: 0
allowed_atype: 0
@@ -244,7 +244,7 @@
subhdr:
magic: 0x7B25
size: 8
- resasg_entries_size: 872
+ resasg_entries_size: 880
reserved: 0
resasg_entries:
-
@@ -257,7 +257,7 @@
start_resource: 18
num_resource: 6
type: 1677
- host_id: 35
+ host_id: 20
reserved: 0
-
start_resource: 18
@@ -287,7 +287,7 @@
start_resource: 72
num_resource: 6
type: 1678
- host_id: 35
+ host_id: 20
reserved: 0
-
start_resource: 72
@@ -317,7 +317,7 @@
start_resource: 44
num_resource: 6
type: 1679
- host_id: 35
+ host_id: 20
reserved: 0
-
start_resource: 44
@@ -347,7 +347,7 @@
start_resource: 18
num_resource: 6
type: 1696
- host_id: 35
+ host_id: 20
reserved: 0
-
start_resource: 18
@@ -377,7 +377,7 @@
start_resource: 18
num_resource: 6
type: 1697
- host_id: 35
+ host_id: 20
reserved: 0
-
start_resource: 18
@@ -407,7 +407,7 @@
start_resource: 12
num_resource: 6
type: 1698
- host_id: 35
+ host_id: 20
reserved: 0
-
start_resource: 12
@@ -429,11 +429,17 @@
reserved: 0
-
start_resource: 6
- num_resource: 34
+ num_resource: 26
type: 1802
host_id: 12
reserved: 0
-
+ start_resource: 32
+ num_resource: 8
+ type: 1802
+ host_id: 20
+ reserved: 0
+ -
start_resource: 44
num_resource: 36
type: 1802
@@ -587,7 +593,7 @@
start_resource: 19
num_resource: 64
type: 1937
- host_id: 30
+ host_id: 36
reserved: 0
-
start_resource: 83
@@ -641,7 +647,7 @@
start_resource: 118
num_resource: 16
type: 1943
- host_id: 30
+ host_id: 36
reserved: 0
-
start_resource: 134
@@ -707,7 +713,7 @@
start_resource: 19
num_resource: 8
type: 1956
- host_id: 30
+ host_id: 36
reserved: 0
-
start_resource: 27
@@ -791,7 +797,7 @@
start_resource: 19
num_resource: 1
type: 1963
- host_id: 30
+ host_id: 36
reserved: 0
-
start_resource: 19
@@ -803,7 +809,7 @@
start_resource: 19
num_resource: 16
type: 1964
- host_id: 30
+ host_id: 36
reserved: 0
-
start_resource: 20
diff --git a/board/phytec/phycore_am62x/MAINTAINERS b/board/phytec/phycore_am62x/MAINTAINERS
index 8f2b806..274dc0c 100644
--- a/board/phytec/phycore_am62x/MAINTAINERS
+++ b/board/phytec/phycore_am62x/MAINTAINERS
@@ -9,6 +9,7 @@
F: board/phytec/phycore_am62x/
F: configs/phycore_am62x_a53_defconfig
F: configs/phycore_am62x_r5_defconfig
+F: configs/phycore_am62x_r5_ethboot_defconfig
F: configs/phycore_am62x_r5_usbdfu_defconfig
F: include/configs/phycore_am62x.h
F: doc/board/phytec/phycore-am62x.rst
diff --git a/board/phytec/phycore_imx93/phycore_imx93.env b/board/phytec/phycore_imx93/phycore_imx93.env
index ab65cfc..3b2f301 100644
--- a/board/phytec/phycore_imx93/phycore_imx93.env
+++ b/board/phytec/phycore_imx93/phycore_imx93.env
@@ -1,26 +1,42 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+#include <env/phytec/rauc.env>
#include <env/phytec/overlays.env>
+bootcmd=
+ mmc dev ${mmcdev};
+ if mmc rescan; then
+ if test ${doraucboot} = 1; then
+ run raucinit;
+ fi;
+ if run loadimage; then
+ run mmcboot;
+ else
+ run netboot;
+ fi;
+ fi;
image=Image
console=ttyLP0
-fdt_addr_r=0x83000000
-fdtoverlay_addr_r=0x830c0000
-bootenv_addr_r=0x83500000
+fdt_addr_r=0x90000000
+fdtoverlay_addr_r=0x900c0000
+bootenv_addr_r=0x90500000
fdtfile=CONFIG_DEFAULT_FDT_FILE
ip_dyn=yes
+prepare_mcore=setenv optargs "${optargs} clk-imx93.mcore_booted"
mmcdev=CONFIG_SYS_MMC_ENV_DEV
mmcpart=1
mmcroot=2
mmcautodetect=yes
mmcargs=setenv bootargs console=${console},${baudrate} earlycon
- root=/dev/mmcblk${mmcdev}p${mmcroot} ${raucargs} rootwait rw
+ root=/dev/mmcblk${mmcdev}p${mmcroot} ${raucargs} rootwait rw ${optargs}
loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}
mmcboot=
echo Booting from mmc ...;
- if run mmc_load_bootenv; then
- env import -t ${bootenv_addr_r} ${filesize};
+ if test ${no_bootenv} = 0; then
+ if run mmc_load_bootenv; then
+ env import -t ${bootenv_addr_r} ${filesize};
+ fi;
fi;
run mmcargs;
if run loadfdt; then
@@ -31,7 +47,7 @@
fi;
nfsroot=/nfs
netargs=setenv bootargs console=${console},${baudrate} earlycon
- root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp
+ root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp ${optargs}
netboot=
echo Booting from net ...;
run netargs;
@@ -40,8 +56,10 @@
else
setenv get_cmd tftp;
fi;
- if run net_load_bootenv; then
- env import -t ${bootenv_addr_r} ${filesize};
+ if test ${no_bootenv} = 0; then
+ if run net_load_bootenv; then
+ env import -t ${bootenv_addr_r} ${filesize};
+ fi;
fi;
${get_cmd} ${loadaddr} ${image};
if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then
diff --git a/board/qualcomm/dragonboard410c/MAINTAINERS b/board/qualcomm/dragonboard410c/MAINTAINERS
index e78f5b2..9c10fa3 100644
--- a/board/qualcomm/dragonboard410c/MAINTAINERS
+++ b/board/qualcomm/dragonboard410c/MAINTAINERS
@@ -1,5 +1,6 @@
DRAGONBOARD410C BOARD
-M: Ramon Fried <rfried.dev@gmail.com>
+M: Stephan Gerhold <stephan@gerhold.net>
+R: Sam Day <me@samcday.com>
S: Maintained
F: board/qualcomm/dragonboard410c/
F: include/configs/dragonboard410c.h
diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c
index fcbf2c3..4698b9d 100644
--- a/board/qualcomm/dragonboard410c/dragonboard410c.c
+++ b/board/qualcomm/dragonboard410c/dragonboard410c.c
@@ -22,21 +22,6 @@
DECLARE_GLOBAL_DATA_PTR;
-/* UNSTUFF_BITS macro taken from Linux Kernel: drivers/mmc/core/sd.c */
-#define UNSTUFF_BITS(resp, start, size) \
- ({ \
- const int __size = size; \
- const u32 __mask = (__size < 32 ? 1 << __size : 0) - 1; \
- const int __off = 3 - ((start) / 32); \
- const int __shft = (start) & 31; \
- u32 __res; \
- \
- __res = resp[__off] >> __shft; \
- if (__size + __shft > 32) \
- __res |= resp[__off - 1] << ((32 - __shft) % 32); \
- __res & __mask; \
- })
-
static u32 msm_board_serial(void)
{
struct mmc *mmc_dev;
@@ -48,7 +33,8 @@
if (mmc_init(mmc_dev))
return 0;
- return UNSTUFF_BITS(mmc_dev->cid, 16, 32);
+ /* MMC serial number */
+ return mmc_dev->cid[2] << 16 | mmc_dev->cid[3] >> 16;
}
static void msm_generate_mac_addr(u8 *mac)
@@ -65,28 +51,6 @@
put_unaligned_be32(msm_board_serial(), &mac[2]);
}
-/* Check for vol- button - if pressed - stop autoboot */
-int misc_init_r(void)
-{
- struct udevice *btn;
- int ret;
- enum button_state_t state;
-
- ret = button_get_by_label("vol_down", &btn);
- if (ret < 0) {
- printf("Couldn't find power button!\n");
- return ret;
- }
-
- state = button_get_state(btn);
- if (state == BUTTON_ON) {
- env_set("preboot", "setenv preboot; fastboot 0");
- printf("vol_down pressed - Starting fastboot.\n");
- }
-
- return 0;
-}
-
int qcom_late_init(void)
{
char serial[16];
@@ -97,9 +61,9 @@
return 0;
}
-/* Fixup of DTB for Linux Kernel
- * 1. Fixup installed DRAM.
- * 2. Fixup WLAN/BT Mac address:
+/*
+ * Fixup of DTB for Linux Kernel
+ * 1. Fixup WLAN/BT Mac address:
* First, check if MAC addresses for WLAN/BT exists as environemnt
* variables wlanaddr,btaddr. if not, generate a unique address.
*/
@@ -107,6 +71,7 @@
int ft_board_setup(void *blob, struct bd_info *bd)
{
u8 mac[ARP_HLEN];
+ int i;
if (!eth_env_get_enetaddr("wlanaddr", mac)) {
msm_generate_mac_addr(mac);
@@ -118,12 +83,24 @@
if (!eth_env_get_enetaddr("btaddr", mac)) {
msm_generate_mac_addr(mac);
-/* The BD address is same as WLAN MAC address but with
- * least significant bit flipped.
- */
- mac[0] ^= 0x01;
+ /*
+ * The BD address is same as WLAN MAC address but with
+ * least significant bit flipped.
+ */
+ mac[ARP_HLEN - 1] ^= 0x01;
};
+ /*
+ * Reverse array since local-bd-address is formatted with least
+ * significant byte first (little endian).
+ */
+ for (i = 0; i < ARP_HLEN / 2; ++i) {
+ u8 tmp = mac[i];
+
+ mac[i] = mac[ARP_HLEN - 1 - i];
+ mac[ARP_HLEN - 1 - i] = tmp;
+ }
+
do_fixup_by_compat(blob, "qcom,wcnss-bt",
"local-bd-address", mac, ARP_HLEN, 1);
return 0;
diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.env b/board/qualcomm/dragonboard410c/dragonboard410c.env
index 9d9a575..38399d6 100644
--- a/board/qualcomm/dragonboard410c/dragonboard410c.env
+++ b/board/qualcomm/dragonboard410c/dragonboard410c.env
@@ -1,36 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
-
-/* Does what recovery does */
-#define REFLASH(file, partnum) \
-part start mmc 0 partnum start && \
-part size mmc 0 partnum size && \
-tftp $loadaddr file && \
-mmc write $loadaddr $start $size &&
-
-reflash=
-mmc dev 0 &&
-usb start &&
-dhcp &&
-tftp $loadaddr dragonboard/rescue/gpt_both0.bin &&
-mmc write $loadaddr 0 43 &&
-mmc rescan &&
-REFLASH(dragonboard/rescue/NON-HLOS.bin, 1)
-REFLASH(dragonboard/rescue/sbl1.mbn, 2)
-REFLASH(dragonboard/rescue/rpm.mbn, 3)
-REFLASH(dragonboard/rescue/tz.mbn, 4)
-REFLASH(dragonboard/rescue/hyp.mbn, 5)
-REFLASH(dragonboard/rescue/sec.dat, 6)
-REFLASH(dragonboard/rescue/emmc_appsboot.mbn, 7)
-REFLASH(dragonboard/u-boot.img, 8)
-usb stop &&
-echo Reflash completed
-
-loadaddr=0x81000000
initrd_high=0xffffffffffffffff
-linux_image=Image
-kernel_addr_r=0x81000000
-fdtfile=qcom/apq8016-sbc.dtb
-fdt_addr_r=0x83000000
-ramdisk_addr_r=0x84000000
-scriptaddr=0x90000000
-pxefile_addr_r=0x90100000
+fastboot=fastboot -l $fastboot_addr_r usb 0
+boot_targets=usb mmc1 mmc0 pxe
+button_cmd_0_name=vol_down
+button_cmd_0=run fastboot
diff --git a/board/qualcomm/dragonboard820c/dragonboard820c.c b/board/qualcomm/dragonboard820c/dragonboard820c.c
index d3333a5..12a9273 100644
--- a/board/qualcomm/dragonboard820c/dragonboard820c.c
+++ b/board/qualcomm/dragonboard820c/dragonboard820c.c
@@ -106,7 +106,7 @@
int ret;
enum button_state_t state;
- ret = button_get_by_label("pwrkey", &btn);
+ ret = button_get_by_label("Power Button", &btn);
if (ret < 0) {
printf("Couldn't find power button!\n");
return ret;
diff --git a/board/qualcomm/qcom-phone.config b/board/qualcomm/qcom-phone.config
new file mode 100644
index 0000000..913c917
--- /dev/null
+++ b/board/qualcomm/qcom-phone.config
@@ -0,0 +1,29 @@
+# Settings for phones
+CONFIG_DEFAULT_ENV_FILE="board/qualcomm/qcom-phone.env"
+# Hang on panic so the error message can be read
+CONFIG_PANIC_HANG=y
+# We use pause in various places to allow text to be read
+# before it scrolls off the screen
+CONFIG_CMD_PAUSE=y
+CONFIG_BOOT_RETRY=y
+CONFIG_BOOT_RETRY_TIME=1
+CONFIG_BUTTON_REMAP_PHONE_KEYS=y
+CONFIG_RETRY_BOOTCMD=y
+CONFIG_FASTBOOT_BUF_ADDR=0x1A000000
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_USB_FUNCTION_ACM=y
+CONFIG_CMD_UMS_ABORT_KEYED=y
+
+# Record all console output and let it be dumped via fastboot
+CONFIG_CONSOLE_RECORD=y
+CONFIG_CONSOLE_RECORD_INIT_F=y
+CONFIG_CONSOLE_RECORD_OUT_SIZE=0x6000
+CONFIG_FASTBOOT_CMD_OEM_CONSOLE=y
+
+# Only MMC is supported by fastboot currently, but this is still useful.
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_OEM_RUN=y
+
+# Many phones don't actually define a serial port in their DTS
+# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
diff --git a/board/qualcomm/qcom-phone.env b/board/qualcomm/qcom-phone.env
new file mode 100644
index 0000000..e91ae3e
--- /dev/null
+++ b/board/qualcomm/qcom-phone.env
@@ -0,0 +1,47 @@
+bootdelay=0
+bootretry=1
+stdin=serial,button-kbd
+stdout=serial,vidconsole
+stderr=serial,vidconsole
+
+# Fastboot is keen to use the address from kconfig, but we
+# allocate its buffer at runtime.
+fastboot=fastboot -l $fastboot_addr_r usb 0
+
+# Always probe for UFS storage, though it should be done by board code.
+preboot=scsi scan
+
+# Shortcut to enable USB serial gadget and disable bootretry
+serial_gadget=setenv stdin serial,button-kbd,usbacm; \
+ setenv stdout serial,vidconsole,usbacm; \
+ setenv stderr serial,vidconsole,usbacm; \
+ setenv bootretry -1; \
+ echo Enabled U-Boot console serial gadget
+
+# bootretry will run this command over and over, if we fail once
+# then bail out to the boot menu instead (with a pause to read
+# the error message)
+bootcmd=bootefi bootmgr; pause; run menucmd
+
+# When entering the menu (either from button press or failed boot)
+# remap bootcmd so it will re-open the menu and we won't get stuck
+# at the console with no way to type
+menucmd=setenv bootcmd run menucmd; bootmenu -1
+
+# Pause is used so the output can be read on the display
+bootmenu_0=Boot=bootefi bootmgr; pause
+bootmenu_1=Enable serial console gadget=run serial_gadget
+bootmenu_2=Enable USB mass storage=echo "Press any key to exit UMS mode"; ums 0 scsi 0
+bootmenu_3=Enable fastboot mode=run fastboot
+# Disabling bootretry means we'll just drop the shell
+bootmenu_4=Drop to shell=setenv bootretry -1
+bootmenu_5=Reset device=reset
+bootmenu_6=Dump clocks=clk dump; pause
+bootmenu_7=Dump environment=printenv; pause
+bootmenu_8=Board info=bdinfo; pause
+bootmenu_9=Dump bootargs=fdt print /chosen bootargs; pause
+
+# Allow holding the volume down button while U-Boot loads to enter
+# the boot menu
+button_cmd_0_name=Volume Down
+button_cmd_0=run menucmd
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index 6ecd3eb..1b0b664 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -359,9 +359,6 @@
*/
static void set_fdt_addr(void)
{
- if (env_get("fdt_addr"))
- return;
-
if (fdt_magic(fw_dtb_pointer) != FDT_MAGIC)
return;
@@ -602,6 +599,9 @@
/* Bluetooth device address as provided by the firmware */
copy_property(fdt, fw_fdt, "/soc/serial@7e201000/bluetooth", "local-bd-address");
+
+ /* copy uart clk as provided by the firmware */
+ copy_property(fdt, fw_fdt, "/clocks/clk-uart", "clock-frequency");
}
int ft_board_setup(void *blob, struct bd_info *bd)
diff --git a/board/raspberrypi/rpi/rpi.env b/board/raspberrypi/rpi/rpi.env
index 3022828..9ac9d67 100644
--- a/board/raspberrypi/rpi/rpi.env
+++ b/board/raspberrypi/rpi/rpi.env
@@ -48,30 +48,33 @@
*
* scriptaddr and pxefile_addr_r can be pretty much anywhere that doesn't
* conflict with something else. Reserving 1M for each of them at
- * 0x02400000-0x02500000 and 0x02500000-0x02600000 should be plenty.
+ * 0x05400000-0x05500000 and 0x05500000-0x05600000 should be plenty.
*
* On ARM, both the DTB and any possible initrd must be loaded such that they
* fit inside the lowmem mapping in Linux. In practice, this usually means not
* more than ~700M away from the start of the kernel image but this number can
* be larger OR smaller depending on e.g. the 'vmalloc=xxxM' command line
* parameter given to the kernel. So reserving memory from low to high
- * satisfies this constraint again. Reserving 1M at 0x02600000-0x02700000 for
- * the DTB leaves rest of the free RAM to the initrd starting at 0x02700000.
- * Even with the smallest possible CPU-GPU memory split of the CPU getting
- * only 64M, the remaining 25M starting at 0x02700000 should allow quite
- * large initrds before they start colliding with U-Boot.
+ * satisfies this constraint again. Reserving 1M at 0x05600000-0x05700000 for
+ * the DTB leaves rest of the free RAM to the initrd starting at 0x05700000.
+ * This means that the board must have at least 128MB of RAM available to
+ * U-Boot, more if the initrd is large.
+ *
+ * For compressed kernels, the maximum size is just under 32MB, with an area for
+ * decompression at 0x02000000 with space for 52MB, which is plenty for current
+ * kernels.
+ *
+ * limit bootm_size to 512MB so that all boot images stay within the bottom
+ * 512MB of memory
*/
-#ifdef CONFIG_ARM64
-fdt_high=ffffffffffffffff
-initrd_high=ffffffffffffffff
-#else
-fdt_high=ffffffff
-initrd_high=ffffffff
-#endif
+bootm_size=0x20000000
+
kernel_addr_r=0x00080000
-scriptaddr=0x02400000
-pxefile_addr_r=0x02500000
-fdt_addr_r=0x02600000
-ramdisk_addr_r=0x02700000
+kernel_comp_addr_r=0x02000000
+kernel_comp_size=0x03400000
+scriptaddr=0x05400000
+pxefile_addr_r=0x05500000
+fdt_addr_r=0x05600000
+ramdisk_addr_r=0x05700000
boot_targets=mmc usb pxe dhcp
diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS
index 5f81be5..8c9b42f 100644
--- a/board/rockchip/evb_rk3328/MAINTAINERS
+++ b/board/rockchip/evb_rk3328/MAINTAINERS
@@ -7,6 +7,12 @@
F: arch/arm/dts/rk3328-evb.dts
F: arch/arm/dts/rk3328-evb-u-boot.dtsi
+GENERIC-RK3328
+M: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: configs/generic-rk3328_defconfig
+F: arch/arm/dts/rk3328-generic*
+
NANOPI-R2C-RK3328
M: Tianling Shen <cnsztl@gmail.com>
S: Maintained
diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS
index 8dab3fa..8319db2 100644
--- a/board/rockchip/evb_rk3399/MAINTAINERS
+++ b/board/rockchip/evb_rk3399/MAINTAINERS
@@ -14,6 +14,12 @@
F: configs/eaidk-610-rk3399_defconfig
F: arch/arm/dts/rk3399-eaidk-610*
+GENERIC-RK3399
+M: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: configs/generic-rk3399_defconfig
+F: arch/arm/dts/rk3399-generic*
+
KHADAS-EDGE
M: Nick Xie <nick@khadas.com>
S: Maintained
diff --git a/board/sandbox/sandbox.env b/board/sandbox/sandbox.env
index a2c1970..29197f5 100644
--- a/board/sandbox/sandbox.env
+++ b/board/sandbox/sandbox.env
@@ -8,6 +8,11 @@
ethaddr=02:00:11:22:33:44
eth6addr=02:00:11:22:33:47
ipaddr=192.0.2.1
+ipaddr2=192.0.2.3
+ipaddr3=192.0.2.4
+ipaddr5=192.0.2.6
+ipaddr6=192.0.2.7
+ipaddr7=192.0.2.8
/*
* These are used for distro boot which is not supported. But once bootmethod
diff --git a/board/siemens/capricorn/MAINTAINERS b/board/siemens/capricorn/MAINTAINERS
index 5f467aa..3b4bd64 100644
--- a/board/siemens/capricorn/MAINTAINERS
+++ b/board/siemens/capricorn/MAINTAINERS
@@ -9,4 +9,5 @@
F: arch/arm/dts/imx8-capricorn.dtsi
F: board/siemens/capricorn/
F: configs/capricorn_cxg3_defconfig
+F: configs/imx8qxp_capricorn.config
F: include/configs/capricorn-common.h
diff --git a/board/siemens/capricorn/capricorn_default.env b/board/siemens/capricorn/capricorn_default.env
new file mode 100644
index 0000000..4c26e9d
--- /dev/null
+++ b/board/siemens/capricorn/capricorn_default.env
@@ -0,0 +1,49 @@
+altbootcmd=run bootcmd
+baudrate=115200
+bootcmd=run flash_self;reset;
+bootdelay=3
+bootdir=targetdir/rootfs/boot
+bootlimit=3
+check_upgrade=if test ${upgrade_available} -eq 1; then echo upgrade_available is set; if test ${bootcount} -gt ${bootlimit}; then setenv upgrade_available 0;echo toggle partition;run toggle_partition;fi;fi;
+cntr_addr=0x88000000
+cntr_file=os_cntr_signed.bin
+console=ttyLP2
+dtb_name_default=default
+ethprime=eth1
+fdt_addr=0x83000000
+fdt_high=0xffffffffffffffff
+flash_self=run mmc_boot
+flash_self_test=setenv testargs test loglevel=3 systemd.unit=test.target; run mmc_boot
+hostname=capricorn
+initrd_addr=0x83100000
+initrd_high=0xffffffffffffffff
+ip_method=none
+kernel_name=Image
+loadaddr=0x80400000
+mmc_boot=run set_bootargs;run check_upgrade; run set_partition;run set_bootargs_mmc;run mmc_load_bootfiles
+mmc_boot_fit=ext4load mmc 0:${mmc_part_nr} 0x88000000 boot/fitImage;if test -n ${A};then setenv bootargs ${bootargs} rootfs_sig=${sig_a};fi;if test -n ${B};then setenv bootargs ${bootargs} rootfs_sig=${sig_b};fi;bootm 0x88000000#conf-${dtb_name}.dtb;bootm
+mmc_boot_image=ext4load mmc 0:${mmc_part_nr} ${fdt_addr} boot/${dtb_name}.dtb;if test $? -eq 1;then ext4load mmc 0:${mmc_part_nr} ${fdt_addr} boot/${dtb_name_default}.dtb;fi; ext4load mmc 0:${mmc_part_nr} ${loadaddr} boot/${kernel_name}; booti ${loadaddr} - ${fdt_addr}
+mmc_load_bootfiles=echo -n Loading from eMMC ...; if test -e mmc 0:${mmc_part_nr} boot/fitImage; then echo fit; setenv fdt_high; setenv initrd_high; run mmc_boot_fit; else echo image; run mmc_boot_image; fi
+net_nfs=wdt dev scu-wdt; wdt stop; echo Booting from network ...; run set_bootargs_net; tftpboot ${loadaddr} ${bootdir}/${kernel_name}; printenv bootargs; if test ${kernel_name} = fitImage; then setenv fdt_high; setenv initrd_high; bootm ${loadaddr}#conf-${dtb_name}.dtb; else tftpboot ${fdt_addr} ${serverip}:${bootdir}/${dtb_name}.dtb; if test $? -eq 1; then echo Loading default.dtb!; tftpboot ${fdt_addr} ${serverip}:${bootdir}/${dtb_name_default}.dtb; fi; booti ${loadaddr} - ${fdt_addr}; fi
+net_unfs=setenv nfsopts vers=3,udp,rsize=4096,wsize=4096,nolock,port=3049,mountport=3048 rw; run net_nfs
+netdev=lan0
+nfsopts=vers=3,udp,rsize=4096,wsize=4096,nolock rw
+partitionset_active=A
+rootfs_name=/dev/mmcblk0
+rootpath=/home/projects/targetdir/rootfs
+script_file=u-boot-commands.img
+set_bootargs_mmc=setenv bootargs ${bootargs} root=${mmc_active_vol} ro rootdelay=1 rootwait rootfstype=ext4 ip=${ip_method}
+set_bootargs_net=run set_bootargs; if test ${kernel_name} = fitImage; then setenv loadaddr 0x88000000; fi; setenv bootargs ${bootargs} root=/dev/nfs nfsroot=${serverip}:${rootpath},${nfsopts} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off
+set_bootargs=setenv bootargs console=${console},${baudrate} target_env=${target_env} ${testargs} ${optargs}
+set_partition=setenv ${partitionset_active} true;if test -n ${A}; then setenv mmc_part_nr 1;fi;if test -n ${B}; then setenv mmc_part_nr 2;fi;setenv mmc_active_vol ${rootfs_name}p${mmc_part_nr}
+tftp_run_script=tftpboot ${kernel_loadaddr} ${serverip}:${script_file};if test $? -eq 0;then source ${kernel_loadaddr};fi
+toggle_partition=setenv ${partitionset_active} true; if test -n ${A}; then setenv partitionset_active B; mmc partconf 0 1 2 0; env delete A; fi; if test -n ${B}; then setenv partitionset_active A; mmc partconf 0 1 1 0; env delete B; fi;saveenv; reset
+upgrade_available=0
+emmc_dev=0
+sd_dev=1
+mfgtool_args=setenv bootargs console=${console},${baudrate} rdinit=/linuxrc clk_ignore_unused
+kboot=booti
+bootcmd_mfg=run mfgtool_args; if iminfo ${initrd_addr}; then if test ${tee} = yes; then bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; else booti ${loadaddr} ${initrd_addr} ${fdt_addr}; fi; else echo "Run fastboot ..."; fastboot usb auto; fi;
+fastboot_bytes=124c00
+fastboot_dev=mmc
+mmcautodetect=yes
diff --git a/board/sifive/unleashed/Kconfig b/board/sifive/unleashed/Kconfig
index 5d842c3..bf4a00d 100644
--- a/board/sifive/unleashed/Kconfig
+++ b/board/sifive/unleashed/Kconfig
@@ -49,6 +49,7 @@
imply SPI_FLASH_ISSI
imply SYSRESET
imply SYSRESET_GPIO
+ imply SPL_SYSRESET_GPIO if SPL
imply CMD_I2C
endif
diff --git a/board/sifive/unleashed/unleashed.c b/board/sifive/unleashed/unleashed.c
index c1c3746..f5da289 100644
--- a/board/sifive/unleashed/unleashed.c
+++ b/board/sifive/unleashed/unleashed.c
@@ -114,17 +114,6 @@
#endif
-int board_fdt_blob_setup(void **fdtp)
-{
- if (gd->arch.firmware_fdt_addr) {
- *fdtp = (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
-
- return 0;
- }
-
- return -EEXIST;
-}
-
int board_init(void)
{
/* enable all cache ways */
diff --git a/board/sifive/unmatched/Kconfig b/board/sifive/unmatched/Kconfig
index bc1f33b..991dd23 100644
--- a/board/sifive/unmatched/Kconfig
+++ b/board/sifive/unmatched/Kconfig
@@ -48,6 +48,7 @@
imply PHY_MSCC
imply SYSRESET
imply SYSRESET_GPIO
+ imply SPL_SYSRESET_GPIO if SPL
imply CMD_I2C
endif
diff --git a/board/sifive/unmatched/unmatched.c b/board/sifive/unmatched/unmatched.c
index 23e03e1..a57ce1f 100644
--- a/board/sifive/unmatched/unmatched.c
+++ b/board/sifive/unmatched/unmatched.c
@@ -10,16 +10,6 @@
#include <dm.h>
#include <asm/sections.h>
-int board_fdt_blob_setup(void **fdtp)
-{
- if (gd->arch.firmware_fdt_addr) {
- *fdtp = (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
- return 0;
- }
-
- return -EEXIST;
-}
-
int board_init(void)
{
/* enable all cache ways */
diff --git a/board/socionext/developerbox/fwu_plat.c b/board/socionext/developerbox/fwu_plat.c
index 2603179..a8b1114 100644
--- a/board/socionext/developerbox/fwu_plat.c
+++ b/board/socionext/developerbox/fwu_plat.c
@@ -18,7 +18,7 @@
struct mtd_info *mtd;
int ret;
- memset(buf, 0, sizeof(buf));
+ memset(buf, 0, DFU_ALT_BUF_LEN);
mtd_probe_devices();
diff --git a/board/st/common/Makefile b/board/st/common/Makefile
index fda48d2..122b13c 100644
--- a/board/st/common/Makefile
+++ b/board/st/common/Makefile
@@ -8,7 +8,7 @@
ifeq ($(CONFIG_ARCH_STM32MP),y)
obj-$(CONFIG_SET_DFU_ALT_INFO) += stm32mp_dfu.o
-obj-$(CONFIG_$(XPL_)DFU_VIRT) += stm32mp_dfu_virt.o
+obj-$(CONFIG_$(PHASE_)DFU_VIRT) += stm32mp_dfu_virt.o
endif
obj-$(CONFIG_TYPEC_STUSB160X) += stusb160x.o
diff --git a/board/st/stm32mp1/MAINTAINERS b/board/st/stm32mp1/MAINTAINERS
index d5a09cd..f924e61 100644
--- a/board/st/stm32mp1/MAINTAINERS
+++ b/board/st/stm32mp1/MAINTAINERS
@@ -1,5 +1,6 @@
STM32MP1 BOARD
M: Patrick Delaunay <patrick.delaunay@foss.st.com>
+M: Patrice Chotard <patrice.chotard@foss.st.com>
L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
T: git https://source.denx.de/u-boot/custodians/u-boot-stm.git
S: Maintained
@@ -10,6 +11,7 @@
F: configs/stm32mp15_defconfig
F: configs/stm32mp15_basic_defconfig
F: configs/stm32mp15_trusted_defconfig
+F: configs/stm32mp15-odyssey_defconfig
F: include/configs/stm32mp13_common.h
F: include/configs/stm32mp13_st_common.h
F: include/configs/stm32mp15_common.h
diff --git a/board/st/stm32mp2/Kconfig b/board/st/stm32mp2/Kconfig
index 89039f0..f91e25f 100644
--- a/board/st/stm32mp2/Kconfig
+++ b/board/st/stm32mp2/Kconfig
@@ -7,7 +7,7 @@
default "st"
config SYS_CONFIG_NAME
- default "stm32mp25_common"
+ default "stm32mp25_st_common"
source "board/st/common/Kconfig"
endif
diff --git a/board/st/stm32mp2/MAINTAINERS b/board/st/stm32mp2/MAINTAINERS
index e6bea91..8f62481 100644
--- a/board/st/stm32mp2/MAINTAINERS
+++ b/board/st/stm32mp2/MAINTAINERS
@@ -7,3 +7,4 @@
F: board/st/stm32mp2/
F: configs/stm32mp25_defconfig
F: include/configs/stm32mp25_common.h
+F: include/configs/stm32mp25_st_common.h
diff --git a/board/st/stm32mp2/stm32mp2.c b/board/st/stm32mp2/stm32mp2.c
index aa7dd31..2547f2e 100644
--- a/board/st/stm32mp2/stm32mp2.c
+++ b/board/st/stm32mp2/stm32mp2.c
@@ -5,16 +5,21 @@
#define LOG_CATEGORY LOGC_BOARD
+#include <button.h>
#include <config.h>
-#include <env.h>
+#include <env_internal.h>
#include <fdt_support.h>
+#include <led.h>
#include <log.h>
#include <misc.h>
+#include <mmc.h>
#include <asm/global_data.h>
+#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <dm/device.h>
#include <dm/ofnode.h>
#include <dm/uclass.h>
+#include <linux/delay.h>
/*
* Get a global data pointer
@@ -53,12 +58,140 @@
return 0;
}
+static int get_led(struct udevice **dev, char *led_string)
+{
+ const char *led_name;
+ int ret;
+
+ led_name = ofnode_conf_read_str(led_string);
+ if (!led_name) {
+ log_debug("could not find %s config string\n", led_string);
+ return -ENOENT;
+ }
+ ret = led_get_by_label(led_name, dev);
+ if (ret) {
+ log_debug("get=%d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int setup_led(enum led_state_t cmd)
+{
+ struct udevice *dev;
+ int ret;
+
+ if (!CONFIG_IS_ENABLED(LED))
+ return 0;
+
+ ret = get_led(&dev, "u-boot,boot-led");
+ if (ret)
+ return ret;
+
+ ret = led_set_state(dev, cmd);
+ return ret;
+}
+
+static void check_user_button(void)
+{
+ struct udevice *button;
+ int i;
+
+ if (!IS_ENABLED(CONFIG_CMD_STM32PROG) || !IS_ENABLED(CONFIG_BUTTON))
+ return;
+
+ if (button_get_by_label("User-2", &button))
+ return;
+
+ for (i = 0; i < 21; ++i) {
+ if (button_get_state(button) != BUTTON_ON)
+ return;
+ if (i < 20)
+ mdelay(50);
+ }
+
+ log_notice("entering download mode...\n");
+ clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_STM32PROG);
+}
+
/* board dependent setup after realloc */
int board_init(void)
{
+ setup_led(LEDST_ON);
+ check_user_button();
+
return 0;
}
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ u32 bootmode = get_bootmode();
+
+ if (prio)
+ return ENVL_UNKNOWN;
+
+ switch (bootmode & TAMP_BOOT_DEVICE_MASK) {
+ case BOOT_FLASH_SD:
+ case BOOT_FLASH_EMMC:
+ if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC))
+ return ENVL_MMC;
+ else
+ return ENVL_NOWHERE;
+
+ case BOOT_FLASH_NAND:
+ case BOOT_FLASH_SPINAND:
+ if (CONFIG_IS_ENABLED(ENV_IS_IN_UBI))
+ return ENVL_UBI;
+ else
+ return ENVL_NOWHERE;
+
+ case BOOT_FLASH_NOR:
+ if (CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH))
+ return ENVL_SPI_FLASH;
+ else
+ return ENVL_NOWHERE;
+ default:
+ return ENVL_NOWHERE;
+ }
+}
+
+int mmc_get_boot(void)
+{
+ struct udevice *dev;
+ u32 boot_mode = get_bootmode();
+ unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
+ char cmd[20];
+ const u32 sdmmc_addr[] = {
+ STM32_SDMMC1_BASE,
+ STM32_SDMMC2_BASE,
+ STM32_SDMMC3_BASE
+ };
+
+ if (instance > ARRAY_SIZE(sdmmc_addr))
+ return 0;
+
+ /* search associated sdmmc node in devicetree */
+ snprintf(cmd, sizeof(cmd), "mmc@%x", sdmmc_addr[instance]);
+ if (uclass_get_device_by_name(UCLASS_MMC, cmd, &dev)) {
+ log_err("mmc%d = %s not found in device tree!\n", instance, cmd);
+ return 0;
+ }
+
+ return dev_seq(dev);
+};
+
+int mmc_get_env_dev(void)
+{
+ const int mmc_env_dev = CONFIG_IS_ENABLED(ENV_IS_IN_MMC, (CONFIG_SYS_MMC_ENV_DEV), (-1));
+
+ if (mmc_env_dev >= 0)
+ return mmc_env_dev;
+
+ /* use boot instance to select the correct mmc device identifier */
+ return mmc_get_boot();
+}
+
int board_late_init(void)
{
const void *fdt_compat;
@@ -86,3 +219,8 @@
return 0;
}
+
+void board_quiesce_devices(void)
+{
+ setup_led(LEDST_OFF);
+}
diff --git a/board/starfive/visionfive2/MAINTAINERS b/board/starfive/visionfive2/MAINTAINERS
index 898e284..9d348c4 100644
--- a/board/starfive/visionfive2/MAINTAINERS
+++ b/board/starfive/visionfive2/MAINTAINERS
@@ -2,6 +2,6 @@
M: Minda Chen <minda.chen@starfivetech.com>
M: Hal Feng <hal.feng@starfivetech.com>
S: Maintained
-F: drivers/ram/starfive/
+N: starfive
N: jh7110
N: visionfive2
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index 3e4d3e2..3dfa931 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -116,30 +116,29 @@
#if CONFIG_IS_ENABLED(LOAD_FIT)
int board_fit_config_name_match(const char *name)
{
- const char *product_id;
- u8 version;
-
- product_id = get_product_id_from_eeprom();
-
- /* Strip off prefix */
- if (strncmp(name, "starfive/", 9))
- return -EINVAL;
- name += 9;
- if (!strncmp(product_id, "VF7110", 6)) {
- version = get_pcb_revision_from_eeprom();
- if ((version == 'b' || version == 'B') &&
- !strcmp(name, "jh7110-starfive-visionfive-2-v1.3b"))
- return 0;
-
- if ((version == 'a' || version == 'A') &&
- !strcmp(name, "jh7110-starfive-visionfive-2-v1.2a"))
- return 0;
- } else if (!strncmp(product_id, "MARS", 4) &&
- !strcmp(name, "jh7110-milkv-mars")) {
+ if (!strcmp(name, "starfive/jh7110-deepcomputing-fml13v01") &&
+ !strncmp(get_product_id_from_eeprom(), "FML13V01", 8)) {
return 0;
- } else if (!strncmp(product_id, "STAR64", 6) &&
- !strcmp(name, "jh7110-pine64-star64")) {
+ } else if (!strcmp(name, "starfive/jh7110-milkv-mars") &&
+ !strncmp(get_product_id_from_eeprom(), "MARS", 4)) {
return 0;
+ } else if (!strcmp(name, "starfive/jh7110-pine64-star64") &&
+ !strncmp(get_product_id_from_eeprom(), "STAR64", 6)) {
+ return 0;
+ } else if (!strcmp(name, "starfive/jh7110-starfive-visionfive-2-v1.2a") &&
+ !strncmp(get_product_id_from_eeprom(), "VF7110", 6)) {
+ switch (get_pcb_revision_from_eeprom()) {
+ case 'a':
+ case 'A':
+ return 0;
+ }
+ } else if (!strcmp(name, "starfive/jh7110-starfive-visionfive-2-v1.3b") &&
+ !strncmp(get_product_id_from_eeprom(), "VF7110", 6)) {
+ switch (get_pcb_revision_from_eeprom()) {
+ case 'b':
+ case 'B':
+ return 0;
+ }
}
return -EINVAL;
diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c
index b8cd509..bfbb11a 100644
--- a/board/starfive/visionfive2/starfive_visionfive2.c
+++ b/board/starfive/visionfive2/starfive_visionfive2.c
@@ -17,14 +17,6 @@
DECLARE_GLOBAL_DATA_PTR;
#define JH7110_L2_PREFETCHER_BASE_ADDR 0x2030000
#define JH7110_L2_PREFETCHER_HART_OFFSET 0x2000
-#define FDTFILE_MILK_V_MARS \
- "starfive/jh7110-milkv-mars.dtb"
-#define FDTFILE_VISIONFIVE2_1_2A \
- "starfive/jh7110-starfive-visionfive-2-v1.2a.dtb"
-#define FDTFILE_VISIONFIVE2_1_3B \
- "starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"
-#define FDTFILE_PINE64_STAR64 \
- "starfive/jh7110-pine64-star64.dtb"
/* enable U74-mc hart1~hart4 prefetcher */
static void enable_prefetcher(void)
@@ -46,42 +38,41 @@
}
/**
- * set_fdtfile() - set the $fdtfile variable based on the board revision
+ * set_fdtfile() - set the $fdtfile variable based on product data in EEPROM
*/
static void set_fdtfile(void)
{
- u8 version;
const char *fdtfile;
- const char *product_id;
fdtfile = env_get("fdtfile");
if (fdtfile)
return;
- product_id = get_product_id_from_eeprom();
- if (!product_id) {
+ if (!get_product_id_from_eeprom()) {
log_err("Can't read EEPROM\n");
return;
}
- if (!strncmp(product_id, "MARS", 4)) {
- fdtfile = FDTFILE_MILK_V_MARS;
- } else if (!strncmp(product_id, "VF7110", 6)) {
- version = get_pcb_revision_from_eeprom();
- switch (version) {
+ if (!strncmp(get_product_id_from_eeprom(), "FML13V01", 8)) {
+ fdtfile = "starfive/jh7110-deepcomputing-fml13v01.dtb";
+ } else if (!strncmp(get_product_id_from_eeprom(), "MARS", 4)) {
+ fdtfile = "starfive/jh7110-milkv-mars.dtb";
+ } else if (!strncmp(get_product_id_from_eeprom(), "STAR64", 6)) {
+ fdtfile = "starfive/jh7110-pine64-star64.dtb";
+ } else if (!strncmp(get_product_id_from_eeprom(), "VF7110", 6)) {
+ switch (get_pcb_revision_from_eeprom()) {
case 'a':
case 'A':
- fdtfile = FDTFILE_VISIONFIVE2_1_2A;
+ fdtfile = "starfive/jh7110-starfive-visionfive-2-v1.2a.dtb";
break;
-
case 'b':
case 'B':
- default:
- fdtfile = FDTFILE_VISIONFIVE2_1_3B;
+ fdtfile = "starfive/jh7110-starfive-visionfive-2-v1.3b.dtb";
break;
+ default:
+ log_err("Unknown revision\n");
+ return;
}
- } else if (!strncmp(product_id, "STAR64", 6)) {
- fdtfile = FDTFILE_PINE64_STAR64;
} else {
log_err("Unknown product\n");
return;
@@ -106,16 +97,6 @@
return 0;
}
-int board_fdt_blob_setup(void **fdtp)
-{
- if (gd->arch.firmware_fdt_addr) {
- *fdtp = (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
- return 0;
- }
-
- return -EEXIST;
-}
-
int ft_board_setup(void *blob, struct bd_info *bd)
{
return fdt_fixup_memory(blob, 0x40000000, gd->ram_size);
diff --git a/board/tcl/sl50/Makefile b/board/tcl/sl50/Makefile
index 1502990..399e8cb 100644
--- a/board/tcl/sl50/Makefile
+++ b/board/tcl/sl50/Makefile
@@ -4,7 +4,7 @@
#
# Copyright (C) 2015 Toby Churchill Ltd - http://www.toby-churchill.com/
-ifeq ($(CONFIG_$(XPL_)SKIP_LOWLEVEL_INIT),)
+ifeq ($(CONFIG_$(PHASE_)SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif
diff --git a/board/theobroma-systems/common/Makefile b/board/theobroma-systems/common/Makefile
new file mode 100644
index 0000000..c1cadb4
--- /dev/null
+++ b/board/theobroma-systems/common/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (c) 2025 Cherry Embedded Solutions GmbH
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifneq ($(CONFIG_XPL_BUILD),y)
+obj-y += common.o
+endif
diff --git a/board/theobroma-systems/jaguar_rk3588/Makefile b/board/theobroma-systems/jaguar_rk3588/Makefile
index d43bf19..38b73d2 100644
--- a/board/theobroma-systems/jaguar_rk3588/Makefile
+++ b/board/theobroma-systems/jaguar_rk3588/Makefile
@@ -5,6 +5,3 @@
#
obj-y += jaguar_rk3588.o
-ifneq ($(CONFIG_XPL_BUILD),y)
-obj-y += ../common/common.o
-endif
diff --git a/board/theobroma-systems/puma_rk3399/Makefile b/board/theobroma-systems/puma_rk3399/Makefile
index 2256e72..d962b56 100644
--- a/board/theobroma-systems/puma_rk3399/Makefile
+++ b/board/theobroma-systems/puma_rk3399/Makefile
@@ -5,6 +5,3 @@
#
obj-y += puma-rk3399.o
-ifneq ($(CONFIG_XPL_BUILD),y)
-obj-y += ../common/common.o
-endif
diff --git a/board/theobroma-systems/ringneck_px30/Makefile b/board/theobroma-systems/ringneck_px30/Makefile
index 4d108f2..31ada1a 100644
--- a/board/theobroma-systems/ringneck_px30/Makefile
+++ b/board/theobroma-systems/ringneck_px30/Makefile
@@ -5,6 +5,3 @@
#
obj-y += ringneck-px30.o
-ifneq ($(CONFIG_XPL_BUILD),y)
-obj-y += ../common/common.o
-endif
diff --git a/board/theobroma-systems/tiger_rk3588/Makefile b/board/theobroma-systems/tiger_rk3588/Makefile
index 94b0859..9006477 100644
--- a/board/theobroma-systems/tiger_rk3588/Makefile
+++ b/board/theobroma-systems/tiger_rk3588/Makefile
@@ -5,6 +5,3 @@
#
obj-y += tiger_rk3588.o
-ifneq ($(CONFIG_XPL_BUILD),y)
-obj-y += ../common/common.o
-endif
diff --git a/board/ti/am335x/Makefile b/board/ti/am335x/Makefile
index 6ef87c2..7df62fa 100644
--- a/board/ti/am335x/Makefile
+++ b/board/ti/am335x/Makefile
@@ -4,7 +4,7 @@
#
# Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
-ifeq ($(CONFIG_$(XPL_)SKIP_LOWLEVEL_INIT),)
+ifeq ($(CONFIG_$(PHASE_)SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif
diff --git a/board/ti/am43xx/Makefile b/board/ti/am43xx/Makefile
index 5b7b5b3..800157d 100644
--- a/board/ti/am43xx/Makefile
+++ b/board/ti/am43xx/Makefile
@@ -4,7 +4,7 @@
#
# Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
-ifeq ($(CONFIG_$(XPL_)SKIP_LOWLEVEL_INIT),)
+ifeq ($(CONFIG_$(PHASE_)SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif
diff --git a/board/ti/am62px/evm.c b/board/ti/am62px/evm.c
index 75359fa..379d1a5 100644
--- a/board/ti/am62px/evm.c
+++ b/board/ti/am62px/evm.c
@@ -41,14 +41,6 @@
.images = fw_images,
};
-#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO)
-void set_dfu_alt_info(char *interface, char *devstr)
-{
- if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
- env_set("dfu_alt_info", update_info.dfu_string);
-}
-#endif
-
int board_init(void)
{
return 0;
diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c
index 279ceba..3051a0a 100644
--- a/board/ti/am62x/evm.c
+++ b/board/ti/am62x/evm.c
@@ -74,14 +74,6 @@
.images = fw_images,
};
-#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO)
-void set_dfu_alt_info(char *interface, char *devstr)
-{
- if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
- env_set("dfu_alt_info", update_info.dfu_string);
-}
-#endif
-
int board_init(void)
{
return 0;
diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c
index 6a17737..35fd30d 100644
--- a/board/ti/am64x/evm.c
+++ b/board/ti/am64x/evm.c
@@ -54,14 +54,6 @@
.images = fw_images,
};
-#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO)
-void set_dfu_alt_info(char *interface, char *devstr)
-{
- if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
- env_set("dfu_alt_info", update_info.dfu_string);
-}
-#endif
-
int board_init(void)
{
return 0;
diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig
index c03aa3a..b5978ac 100644
--- a/board/ti/common/Kconfig
+++ b/board/ti/common/Kconfig
@@ -41,6 +41,8 @@
imply CMD_I2C
imply CMD_MII
imply CMD_MMC
+ imply CMD_MMC_REG
+ imply MMC_SPEED_MODE_SET
imply CMD_NFS
imply CMD_PART
imply CMD_PING
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index 1fa78ff..0525f6e 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -65,14 +65,6 @@
.images = fw_images,
};
-#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO)
-void set_dfu_alt_info(char *interface, char *devstr)
-{
- if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
- env_set("dfu_alt_info", update_info.dfu_string);
-}
-#endif
-
int board_init(void)
{
return 0;
diff --git a/board/ti/j784s4/evm.c b/board/ti/j784s4/evm.c
index d317f3e..c6e46b7 100644
--- a/board/ti/j784s4/evm.c
+++ b/board/ti/j784s4/evm.c
@@ -40,14 +40,6 @@
.images = fw_images,
};
-#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO)
-void set_dfu_alt_info(char *interface, char *devstr)
-{
- if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
- env_set("dfu_alt_info", update_info.dfu_string);
-}
-#endif
-
int board_init(void)
{
return 0;
diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
index e0a7c66..542c7ba 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -466,10 +466,12 @@
MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 | MUX_PAD_CTRL(OUTPUT_RGB),
};
+#ifdef CONFIG_IMX_HDMI
static void do_enable_hdmi(struct display_info_t const *dev)
{
imx_enable_hdmi_phy();
}
+#endif
static void enable_lvds(struct display_info_t const *dev)
{
@@ -499,7 +501,9 @@
return 1;
}
-struct display_info_t const displays[] = {{
+struct display_info_t const displays[] = {
+#ifdef CONFIG_IMX_HDMI
+{
.bus = -1,
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB24,
@@ -519,7 +523,9 @@
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
-} }, {
+} },
+#endif
+{
.bus = -1,
.addr = 0,
.di = 1,
@@ -589,7 +595,11 @@
int reg;
enable_ipu_clock();
+
+#ifdef CONFIG_IMX_HDMI
imx_setup_hdmi();
+#endif
+
/* Turn on LDB0,IPU,IPU DI0 clocks */
reg = __raw_readl(&mxc_ccm->CCGR3);
reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
diff --git a/board/toradex/apalis_t30/Kconfig b/board/toradex/apalis_t30/Kconfig
index 9cd4970..6260f8e 100644
--- a/board/toradex/apalis_t30/Kconfig
+++ b/board/toradex/apalis_t30/Kconfig
@@ -7,7 +7,7 @@
default "toradex"
config SYS_CONFIG_NAME
- default "apalis_t30"
+ default "tegra"
config TDX_CFG_BLOCK
default y
diff --git a/board/toradex/apalis_t30/apalis_t30.env b/board/toradex/apalis_t30/apalis_t30.env
index a8f2904..85d0a05 100644
--- a/board/toradex/apalis_t30/apalis_t30.env
+++ b/board/toradex/apalis_t30/apalis_t30.env
@@ -1,6 +1,15 @@
uboot_hwpart=1
uboot_blk=0
+/*
+ * Board-specific serial config
+ *
+ * Apalis UART1: NVIDIA UARTA
+ * Apalis UART2: NVIDIA UARTD
+ * Apalis UART3: NVIDIA UARTB
+ * Apalis UART4: NVIDIA UARTC
+ */
+
set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff &&
setexpr blkcnt ${blkcnt} / 0x200
update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} &&
diff --git a/board/toradex/colibri_t20/Kconfig b/board/toradex/colibri_t20/Kconfig
index a43acdd..8a7295a 100644
--- a/board/toradex/colibri_t20/Kconfig
+++ b/board/toradex/colibri_t20/Kconfig
@@ -7,7 +7,7 @@
default "toradex"
config SYS_CONFIG_NAME
- default "colibri_t20"
+ default "tegra"
config TDX_CFG_BLOCK
default y
diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c
index 6425fa8..d432fd2 100644
--- a/board/toradex/colibri_t20/colibri_t20.c
+++ b/board/toradex/colibri_t20/colibri_t20.c
@@ -147,7 +147,7 @@
}
#endif
-#ifdef CONFIG_VIDEO_TEGRA20
+#ifdef CONFIG_VIDEO_TEGRA
/*
* Routine: pin_mux_display
* Description: setup the pin muxes/tristate values for the LCD interface)
diff --git a/board/toradex/colibri_t30/Kconfig b/board/toradex/colibri_t30/Kconfig
index 68ef82b..643309f 100644
--- a/board/toradex/colibri_t30/Kconfig
+++ b/board/toradex/colibri_t30/Kconfig
@@ -7,7 +7,7 @@
default "toradex"
config SYS_CONFIG_NAME
- default "colibri_t30"
+ default "tegra"
config TDX_CFG_BLOCK
default y
diff --git a/board/toradex/colibri_t30/colibri_t30.env b/board/toradex/colibri_t30/colibri_t30.env
index a8f2904..87919fb 100644
--- a/board/toradex/colibri_t30/colibri_t30.env
+++ b/board/toradex/colibri_t30/colibri_t30.env
@@ -1,6 +1,14 @@
uboot_hwpart=1
uboot_blk=0
+/*
+ * Board-specific serial config
+ *
+ * Colibri UART-A: NVIDIA UARTA
+ * Colibri UART-B: NVIDIA UARTD
+ * Colibri UART-C: NVIDIA UARTB
+ */
+
set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff &&
setexpr blkcnt ${blkcnt} / 0x200
update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} &&
diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c
index b214943..6c1cea7 100644
--- a/board/toradex/common/tdx-cfg-block.c
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -157,13 +157,15 @@
{ VERDIN_IMX8MMDL_2G_IT, "Verdin iMX8M Mini DualLite 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
{ VERDIN_IMX8MMQ_2G_IT_NO_CAN, "Verdin iMX8M Mini Quad 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
{ AQUILA_AM69O_32G_WIFI_BT_IT, "Aquila AM69 Octa 32GB WB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) },
- { VERDIN_IMX95H_16G_WIFI_BT_IT, "Verdin iMX95 Hexa 16GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX95) },
+ { VERDIN_IMX95H_8G_WIFI_BT_IT, "Verdin iMX95 Hexa 8GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX95) },
{ VERDIN_IMX8MMQ_4G_WIFI_BT_ET, "Verdin iMX8M Mini Quad 4GB WB ET", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
{ APALIS_IMX8QM_WIFI_BT_IT_1300MHZ, "Apalis iMX8QM 4GB WB IT", TARGET_IS_ENABLED(APALIS_IMX8) },
{ APALIS_IMX8QM_IT_1300MHZ, "Apalis iMX8QM 4GB IT", TARGET_IS_ENABLED(APALIS_IMX8) },
{ APALIS_IMX8QP_WIFI_BT_1300MHZ, "Apalis iMX8QP 2GB WB", TARGET_IS_ENABLED(APALIS_IMX8) },
{ APALIS_IMX8QP_1300MHZ, "Apalis iMX8QP 2GB", TARGET_IS_ENABLED(APALIS_IMX8) },
{ APALIS_IMX8QM_8GB_WIFI_BT_IT_1300MHZ, "Apalis iMX8QM 8GB WB IT", TARGET_IS_ENABLED(APALIS_IMX8) },
+ { SMARC_IMX95_HEXA_8GB_WB_IT, "SMARC iMX95 Hexa 8GB WB IT", TARGET_IS_ENABLED(TORADEX_SMARC_IMX95) },
+ { SMARC_IMX8MPQ_4GB_WB_IT, "SMARC iMX8M Plus Quad 4GB WB IT", TARGET_IS_ENABLED(TORADEX_SMARC_IMX8MP) },
};
struct pid4list {
diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h
index eaa52ed..f4dd853 100644
--- a/board/toradex/common/tdx-cfg-block.h
+++ b/board/toradex/common/tdx-cfg-block.h
@@ -115,13 +115,15 @@
VERDIN_IMX8MMDL_2G_IT,
VERDIN_IMX8MMQ_2G_IT_NO_CAN,
AQUILA_AM69O_32G_WIFI_BT_IT,
- VERDIN_IMX95H_16G_WIFI_BT_IT,
+ VERDIN_IMX95H_8G_WIFI_BT_IT,
VERDIN_IMX8MMQ_4G_WIFI_BT_ET, /* 90 */
APALIS_IMX8QM_WIFI_BT_IT_1300MHZ,
APALIS_IMX8QM_IT_1300MHZ,
APALIS_IMX8QP_WIFI_BT_1300MHZ,
APALIS_IMX8QP_1300MHZ,
APALIS_IMX8QM_8GB_WIFI_BT_IT_1300MHZ, /* 95 */
+ SMARC_IMX95_HEXA_8GB_WB_IT,
+ SMARC_IMX8MPQ_4GB_WB_IT,
};
enum {
diff --git a/board/toradex/smarc-imx8mp/Kconfig b/board/toradex/smarc-imx8mp/Kconfig
new file mode 100644
index 0000000..405a306
--- /dev/null
+++ b/board/toradex/smarc-imx8mp/Kconfig
@@ -0,0 +1,39 @@
+if TARGET_TORADEX_SMARC_IMX8MP
+
+config IMX_CONFIG
+ default "board/toradex/smarc-imx8mp/imximage.cfg"
+
+config SYS_BOARD
+ default "smarc-imx8mp"
+
+config SYS_CONFIG_NAME
+ default "toradex-smarc-imx8mp"
+
+config SYS_VENDOR
+ default "toradex"
+
+config TDX_CFG_BLOCK
+ default y
+
+config TDX_CFG_BLOCK_2ND_ETHADDR
+ default y
+
+config TDX_CFG_BLOCK_DEV
+ default "0"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+ default "-512"
+
+config TDX_CFG_BLOCK_PART
+ default "1"
+
+config TDX_HAVE_EEPROM_EXTRA
+ default y
+
+config TDX_HAVE_MMC
+ default y
+
+source "board/toradex/common/Kconfig"
+
+endif
diff --git a/board/toradex/smarc-imx8mp/MAINTAINERS b/board/toradex/smarc-imx8mp/MAINTAINERS
new file mode 100644
index 0000000..f7fcef1
--- /dev/null
+++ b/board/toradex/smarc-imx8mp/MAINTAINERS
@@ -0,0 +1,10 @@
+Toradex Smarc iMX8M Plus
+F: arch/arm/dts/imx8mp-toradex-smarc-dev-u-boot.dtsi
+F: board/toradex/smarc-imx8mp/
+F: board/toradex/common/
+F: configs/toradex-smarc-imx8mp_defconfig
+F: doc/board/toradex/toradex-smarc-imx8mp.rst
+F: include/configs/toradex-smarc-imx8mp.h
+M: Francesco Dolcini <francesco.dolcini@toradex.com>
+S: Maintained
+W: https://www.toradex.com/computer-on-modules/smarc-arm-family/nxp-imx-8m-plus
diff --git a/board/toradex/smarc-imx8mp/Makefile b/board/toradex/smarc-imx8mp/Makefile
new file mode 100644
index 0000000..9c22bcc
--- /dev/null
+++ b/board/toradex/smarc-imx8mp/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2024 Toradex
+
+obj-y += smarc-imx8mp.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
diff --git a/board/toradex/smarc-imx8mp/imximage.cfg b/board/toradex/smarc-imx8mp/imximage.cfg
new file mode 100644
index 0000000..7f6b940
--- /dev/null
+++ b/board/toradex/smarc-imx8mp/imximage.cfg
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* Copyright (C) 2024 Toradex */
+
+ROM_VERSION v2
+BOOT_FROM emmc_fastboot
+LOADER u-boot-spl-ddr.bin 0x920000
diff --git a/board/toradex/smarc-imx8mp/lpddr4_timing.c b/board/toradex/smarc-imx8mp/lpddr4_timing.c
new file mode 100644
index 0000000..15d26d4
--- /dev/null
+++ b/board/toradex/smarc-imx8mp/lpddr4_timing.c
@@ -0,0 +1,1903 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/* Copyright (C) 2024 Toradex */
+
+#include <asm/arch/ddr.h>
+#include <linux/kernel.h>
+
+#include "lpddr4_timing.h"
+
+struct dram_cfg_param ddr_ddrc_cfg_single_rank_patch[] = {
+ { 0x3d400000, 0xa1080020},
+ { 0x3d400200, 0x1f},
+ { 0x3d40021c, 0xf07}
+};
+
+struct dram_cfg_param ddr_fsp0_cfg_single_rank_patch[] = {
+ { 0x54012, 0x110},
+ { 0x5402c, 0x1}
+};
+
+struct dram_cfg_param ddr_fsp1_cfg_single_rank_patch[] = {
+ { 0x54012, 0x110},
+ { 0x5402c, 0x1}
+};
+
+struct dram_cfg_param ddr_fsp2_cfg_single_rank_patch[] = {
+ { 0x54012, 0x110},
+ { 0x5402c, 0x1}
+};
+
+struct dram_cfg_param ddr_fsp0_2d_cfg_single_rank_patch[] = {
+ { 0x54012, 0x110},
+ { 0x5402c, 0x1}
+};
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa3080020 },
+ { 0x3d400020, 0x1303 },
+ { 0x3d400024, 0x1e84800 },
+ { 0x3d400064, 0x7a017c },
+ { 0x3d400070, 0x7027f90 },
+ { 0x3d400074, 0x790 },
+ { 0x3d4000d0, 0xc00307a3 },
+ { 0x3d4000d4, 0xc50000 },
+ { 0x3d4000dc, 0xf4003f },
+ { 0x3d4000e0, 0x330000 },
+ { 0x3d4000e8, 0x660048 },
+ { 0x3d4000ec, 0x160048 },
+ { 0x3d400100, 0x2028222a },
+ { 0x3d400104, 0x8083f },
+ { 0x3d40010c, 0xe0e000 },
+ { 0x3d400110, 0x12040a12 },
+ { 0x3d400114, 0x2050f0f },
+ { 0x3d400118, 0x1010009 },
+ { 0x3d40011c, 0x502 },
+ { 0x3d400130, 0x20800 },
+ { 0x3d400134, 0xe100002 },
+ { 0x3d400138, 0x184 },
+ { 0x3d400144, 0xc80064 },
+ { 0x3d400180, 0x3e8001e },
+ { 0x3d400184, 0x3207a12 },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x49f820e },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x1f0e },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0x799 },
+ { 0x3d400108, 0x9121b1c },
+ { 0x3d400200, 0x17 },
+ { 0x3d400208, 0x0 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d40021c, 0xf08 },
+ { 0x3d400250, 0x1705 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400404, 0x72ff },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x1001 },
+ { 0x3d402024, 0x30d400 },
+ { 0x3d402050, 0x20d000 },
+ { 0x3d402064, 0xc0026 },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x330000 },
+ { 0x3d4020e8, 0x660048 },
+ { 0x3d4020ec, 0x160048 },
+ { 0x3d402100, 0xa040305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x302 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x27 },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0x599 },
+ { 0x3d403020, 0x1001 },
+ { 0x3d403024, 0xc3500 },
+ { 0x3d403050, 0x20d000 },
+ { 0x3d403064, 0x3000a },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x330000 },
+ { 0x3d4030e8, 0x660048 },
+ { 0x3d4030ec, 0x160048 },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x302 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0xa },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d4030f4, 0x599 },
+ { 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x100a0, 0x1 },
+ { 0x100a1, 0x6 },
+ { 0x100a2, 0x4 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x2 },
+ { 0x100a5, 0x7 },
+ { 0x100a6, 0x5 },
+ { 0x100a7, 0x0 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x4 },
+ { 0x110a4, 0x5 },
+ { 0x110a5, 0x2 },
+ { 0x110a6, 0x6 },
+ { 0x110a7, 0x7 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x1 },
+ { 0x120a2, 0x3 },
+ { 0x120a3, 0x2 },
+ { 0x120a4, 0x5 },
+ { 0x120a5, 0x4 },
+ { 0x120a6, 0x6 },
+ { 0x120a7, 0x7 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x1 },
+ { 0x130a2, 0x4 },
+ { 0x130a3, 0x3 },
+ { 0x130a4, 0x2 },
+ { 0x130a5, 0x6 },
+ { 0x130a6, 0x5 },
+ { 0x130a7, 0x7 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x1205f, 0x1ff },
+ { 0x1215f, 0x1ff },
+ { 0x1305f, 0x1ff },
+ { 0x1315f, 0x1ff },
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x11205f, 0x1ff },
+ { 0x11215f, 0x1ff },
+ { 0x11305f, 0x1ff },
+ { 0x11315f, 0x1ff },
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x21205f, 0x1ff },
+ { 0x21215f, 0x1ff },
+ { 0x21305f, 0x1ff },
+ { 0x21315f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0x18 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x20024, 0x1e3 },
+ { 0x2003a, 0x2 },
+ { 0x120024, 0x1e3 },
+ { 0x2003a, 0x2 },
+ { 0x220024, 0x1e3 },
+ { 0x2003a, 0x2 },
+ { 0x20056, 0x3 },
+ { 0x120056, 0x3 },
+ { 0x220056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x1204d, 0xe00 },
+ { 0x1214d, 0xe00 },
+ { 0x1304d, 0xe00 },
+ { 0x1314d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x11204d, 0xe00 },
+ { 0x11214d, 0xe00 },
+ { 0x11304d, 0xe00 },
+ { 0x11314d, 0xe00 },
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x21204d, 0xe00 },
+ { 0x21214d, 0xe00 },
+ { 0x21304d, 0xe00 },
+ { 0x21314d, 0xe00 },
+ { 0x10049, 0xeba },
+ { 0x10149, 0xeba },
+ { 0x11049, 0xeba },
+ { 0x11149, 0xeba },
+ { 0x12049, 0xeba },
+ { 0x12149, 0xeba },
+ { 0x13049, 0xeba },
+ { 0x13149, 0xeba },
+ { 0x110049, 0xeba },
+ { 0x110149, 0xeba },
+ { 0x111049, 0xeba },
+ { 0x111149, 0xeba },
+ { 0x112049, 0xeba },
+ { 0x112149, 0xeba },
+ { 0x113049, 0xeba },
+ { 0x113149, 0xeba },
+ { 0x210049, 0xeba },
+ { 0x210149, 0xeba },
+ { 0x211049, 0xeba },
+ { 0x211149, 0xeba },
+ { 0x212049, 0xeba },
+ { 0x212149, 0xeba },
+ { 0x213049, 0xeba },
+ { 0x213149, 0xeba },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x3 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x3e8 },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0x104 },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x12043, 0x5a1 },
+ { 0x12143, 0x5a1 },
+ { 0x13043, 0x5a1 },
+ { 0x13143, 0x5a1 },
+ { 0x1200b2, 0x104 },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x112043, 0x5a1 },
+ { 0x112143, 0x5a1 },
+ { 0x113043, 0x5a1 },
+ { 0x113143, 0x5a1 },
+ { 0x2200b2, 0x104 },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x212043, 0x5a1 },
+ { 0x212143, 0x5a1 },
+ { 0x213043, 0x5a1 },
+ { 0x213143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
+ { 0x2007d, 0x212 },
+ { 0x12007d, 0x212 },
+ { 0x22007d, 0x212 },
+ { 0x2007c, 0x61 },
+ { 0x12007c, 0x61 },
+ { 0x22007c, 0x61 },
+ { 0x1004a, 0x500 },
+ { 0x1104a, 0x500 },
+ { 0x1204a, 0x500 },
+ { 0x1304a, 0x500 },
+ { 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
+ { 0x8080, 0x0 },
+ { 0x108080, 0x0 },
+ { 0x208080, 0x0 },
+ { 0x9080, 0x0 },
+ { 0x109080, 0x0 },
+ { 0x209080, 0x0 },
+ { 0x10080, 0x0 },
+ { 0x110080, 0x0 },
+ { 0x210080, 0x0 },
+ { 0x10180, 0x0 },
+ { 0x110180, 0x0 },
+ { 0x210180, 0x0 },
+ { 0x11080, 0x0 },
+ { 0x111080, 0x0 },
+ { 0x211080, 0x0 },
+ { 0x11180, 0x0 },
+ { 0x111180, 0x0 },
+ { 0x211180, 0x0 },
+ { 0x12080, 0x0 },
+ { 0x112080, 0x0 },
+ { 0x212080, 0x0 },
+ { 0x12180, 0x0 },
+ { 0x112180, 0x0 },
+ { 0x212180, 0x0 },
+ { 0x13080, 0x0 },
+ { 0x113080, 0x0 },
+ { 0x213080, 0x0 },
+ { 0x13180, 0x0 },
+ { 0x113180, 0x0 },
+ { 0x213180, 0x0 },
+ { 0x10081, 0x0 },
+ { 0x110081, 0x0 },
+ { 0x210081, 0x0 },
+ { 0x10181, 0x0 },
+ { 0x110181, 0x0 },
+ { 0x210181, 0x0 },
+ { 0x11081, 0x0 },
+ { 0x111081, 0x0 },
+ { 0x211081, 0x0 },
+ { 0x11181, 0x0 },
+ { 0x111181, 0x0 },
+ { 0x211181, 0x0 },
+ { 0x12081, 0x0 },
+ { 0x112081, 0x0 },
+ { 0x212081, 0x0 },
+ { 0x12181, 0x0 },
+ { 0x112181, 0x0 },
+ { 0x212181, 0x0 },
+ { 0x13081, 0x0 },
+ { 0x113081, 0x0 },
+ { 0x213081, 0x0 },
+ { 0x13181, 0x0 },
+ { 0x113181, 0x0 },
+ { 0x213181, 0x0 },
+ { 0x100d0, 0x0 },
+ { 0x1100d0, 0x0 },
+ { 0x2100d0, 0x0 },
+ { 0x101d0, 0x0 },
+ { 0x1101d0, 0x0 },
+ { 0x2101d0, 0x0 },
+ { 0x110d0, 0x0 },
+ { 0x1110d0, 0x0 },
+ { 0x2110d0, 0x0 },
+ { 0x111d0, 0x0 },
+ { 0x1111d0, 0x0 },
+ { 0x2111d0, 0x0 },
+ { 0x120d0, 0x0 },
+ { 0x1120d0, 0x0 },
+ { 0x2120d0, 0x0 },
+ { 0x121d0, 0x0 },
+ { 0x1121d0, 0x0 },
+ { 0x2121d0, 0x0 },
+ { 0x130d0, 0x0 },
+ { 0x1130d0, 0x0 },
+ { 0x2130d0, 0x0 },
+ { 0x131d0, 0x0 },
+ { 0x1131d0, 0x0 },
+ { 0x2131d0, 0x0 },
+ { 0x100d1, 0x0 },
+ { 0x1100d1, 0x0 },
+ { 0x2100d1, 0x0 },
+ { 0x101d1, 0x0 },
+ { 0x1101d1, 0x0 },
+ { 0x2101d1, 0x0 },
+ { 0x110d1, 0x0 },
+ { 0x1110d1, 0x0 },
+ { 0x2110d1, 0x0 },
+ { 0x111d1, 0x0 },
+ { 0x1111d1, 0x0 },
+ { 0x2111d1, 0x0 },
+ { 0x120d1, 0x0 },
+ { 0x1120d1, 0x0 },
+ { 0x2120d1, 0x0 },
+ { 0x121d1, 0x0 },
+ { 0x1121d1, 0x0 },
+ { 0x2121d1, 0x0 },
+ { 0x130d1, 0x0 },
+ { 0x1130d1, 0x0 },
+ { 0x2130d1, 0x0 },
+ { 0x131d1, 0x0 },
+ { 0x1131d1, 0x0 },
+ { 0x2131d1, 0x0 },
+ { 0x10068, 0x0 },
+ { 0x10168, 0x0 },
+ { 0x10268, 0x0 },
+ { 0x10368, 0x0 },
+ { 0x10468, 0x0 },
+ { 0x10568, 0x0 },
+ { 0x10668, 0x0 },
+ { 0x10768, 0x0 },
+ { 0x10868, 0x0 },
+ { 0x11068, 0x0 },
+ { 0x11168, 0x0 },
+ { 0x11268, 0x0 },
+ { 0x11368, 0x0 },
+ { 0x11468, 0x0 },
+ { 0x11568, 0x0 },
+ { 0x11668, 0x0 },
+ { 0x11768, 0x0 },
+ { 0x11868, 0x0 },
+ { 0x12068, 0x0 },
+ { 0x12168, 0x0 },
+ { 0x12268, 0x0 },
+ { 0x12368, 0x0 },
+ { 0x12468, 0x0 },
+ { 0x12568, 0x0 },
+ { 0x12668, 0x0 },
+ { 0x12768, 0x0 },
+ { 0x12868, 0x0 },
+ { 0x13068, 0x0 },
+ { 0x13168, 0x0 },
+ { 0x13268, 0x0 },
+ { 0x13368, 0x0 },
+ { 0x13468, 0x0 },
+ { 0x13568, 0x0 },
+ { 0x13668, 0x0 },
+ { 0x13768, 0x0 },
+ { 0x13868, 0x0 },
+ { 0x10069, 0x0 },
+ { 0x10169, 0x0 },
+ { 0x10269, 0x0 },
+ { 0x10369, 0x0 },
+ { 0x10469, 0x0 },
+ { 0x10569, 0x0 },
+ { 0x10669, 0x0 },
+ { 0x10769, 0x0 },
+ { 0x10869, 0x0 },
+ { 0x11069, 0x0 },
+ { 0x11169, 0x0 },
+ { 0x11269, 0x0 },
+ { 0x11369, 0x0 },
+ { 0x11469, 0x0 },
+ { 0x11569, 0x0 },
+ { 0x11669, 0x0 },
+ { 0x11769, 0x0 },
+ { 0x11869, 0x0 },
+ { 0x12069, 0x0 },
+ { 0x12169, 0x0 },
+ { 0x12269, 0x0 },
+ { 0x12369, 0x0 },
+ { 0x12469, 0x0 },
+ { 0x12569, 0x0 },
+ { 0x12669, 0x0 },
+ { 0x12769, 0x0 },
+ { 0x12869, 0x0 },
+ { 0x13069, 0x0 },
+ { 0x13169, 0x0 },
+ { 0x13269, 0x0 },
+ { 0x13369, 0x0 },
+ { 0x13469, 0x0 },
+ { 0x13569, 0x0 },
+ { 0x13669, 0x0 },
+ { 0x13769, 0x0 },
+ { 0x13869, 0x0 },
+ { 0x1008c, 0x0 },
+ { 0x11008c, 0x0 },
+ { 0x21008c, 0x0 },
+ { 0x1018c, 0x0 },
+ { 0x11018c, 0x0 },
+ { 0x21018c, 0x0 },
+ { 0x1108c, 0x0 },
+ { 0x11108c, 0x0 },
+ { 0x21108c, 0x0 },
+ { 0x1118c, 0x0 },
+ { 0x11118c, 0x0 },
+ { 0x21118c, 0x0 },
+ { 0x1208c, 0x0 },
+ { 0x11208c, 0x0 },
+ { 0x21208c, 0x0 },
+ { 0x1218c, 0x0 },
+ { 0x11218c, 0x0 },
+ { 0x21218c, 0x0 },
+ { 0x1308c, 0x0 },
+ { 0x11308c, 0x0 },
+ { 0x21308c, 0x0 },
+ { 0x1318c, 0x0 },
+ { 0x11318c, 0x0 },
+ { 0x21318c, 0x0 },
+ { 0x1008d, 0x0 },
+ { 0x11008d, 0x0 },
+ { 0x21008d, 0x0 },
+ { 0x1018d, 0x0 },
+ { 0x11018d, 0x0 },
+ { 0x21018d, 0x0 },
+ { 0x1108d, 0x0 },
+ { 0x11108d, 0x0 },
+ { 0x21108d, 0x0 },
+ { 0x1118d, 0x0 },
+ { 0x11118d, 0x0 },
+ { 0x21118d, 0x0 },
+ { 0x1208d, 0x0 },
+ { 0x11208d, 0x0 },
+ { 0x21208d, 0x0 },
+ { 0x1218d, 0x0 },
+ { 0x11218d, 0x0 },
+ { 0x21218d, 0x0 },
+ { 0x1308d, 0x0 },
+ { 0x11308d, 0x0 },
+ { 0x21308d, 0x0 },
+ { 0x1318d, 0x0 },
+ { 0x11318d, 0x0 },
+ { 0x21318d, 0x0 },
+ { 0x100c0, 0x0 },
+ { 0x1100c0, 0x0 },
+ { 0x2100c0, 0x0 },
+ { 0x101c0, 0x0 },
+ { 0x1101c0, 0x0 },
+ { 0x2101c0, 0x0 },
+ { 0x102c0, 0x0 },
+ { 0x1102c0, 0x0 },
+ { 0x2102c0, 0x0 },
+ { 0x103c0, 0x0 },
+ { 0x1103c0, 0x0 },
+ { 0x2103c0, 0x0 },
+ { 0x104c0, 0x0 },
+ { 0x1104c0, 0x0 },
+ { 0x2104c0, 0x0 },
+ { 0x105c0, 0x0 },
+ { 0x1105c0, 0x0 },
+ { 0x2105c0, 0x0 },
+ { 0x106c0, 0x0 },
+ { 0x1106c0, 0x0 },
+ { 0x2106c0, 0x0 },
+ { 0x107c0, 0x0 },
+ { 0x1107c0, 0x0 },
+ { 0x2107c0, 0x0 },
+ { 0x108c0, 0x0 },
+ { 0x1108c0, 0x0 },
+ { 0x2108c0, 0x0 },
+ { 0x110c0, 0x0 },
+ { 0x1110c0, 0x0 },
+ { 0x2110c0, 0x0 },
+ { 0x111c0, 0x0 },
+ { 0x1111c0, 0x0 },
+ { 0x2111c0, 0x0 },
+ { 0x112c0, 0x0 },
+ { 0x1112c0, 0x0 },
+ { 0x2112c0, 0x0 },
+ { 0x113c0, 0x0 },
+ { 0x1113c0, 0x0 },
+ { 0x2113c0, 0x0 },
+ { 0x114c0, 0x0 },
+ { 0x1114c0, 0x0 },
+ { 0x2114c0, 0x0 },
+ { 0x115c0, 0x0 },
+ { 0x1115c0, 0x0 },
+ { 0x2115c0, 0x0 },
+ { 0x116c0, 0x0 },
+ { 0x1116c0, 0x0 },
+ { 0x2116c0, 0x0 },
+ { 0x117c0, 0x0 },
+ { 0x1117c0, 0x0 },
+ { 0x2117c0, 0x0 },
+ { 0x118c0, 0x0 },
+ { 0x1118c0, 0x0 },
+ { 0x2118c0, 0x0 },
+ { 0x120c0, 0x0 },
+ { 0x1120c0, 0x0 },
+ { 0x2120c0, 0x0 },
+ { 0x121c0, 0x0 },
+ { 0x1121c0, 0x0 },
+ { 0x2121c0, 0x0 },
+ { 0x122c0, 0x0 },
+ { 0x1122c0, 0x0 },
+ { 0x2122c0, 0x0 },
+ { 0x123c0, 0x0 },
+ { 0x1123c0, 0x0 },
+ { 0x2123c0, 0x0 },
+ { 0x124c0, 0x0 },
+ { 0x1124c0, 0x0 },
+ { 0x2124c0, 0x0 },
+ { 0x125c0, 0x0 },
+ { 0x1125c0, 0x0 },
+ { 0x2125c0, 0x0 },
+ { 0x126c0, 0x0 },
+ { 0x1126c0, 0x0 },
+ { 0x2126c0, 0x0 },
+ { 0x127c0, 0x0 },
+ { 0x1127c0, 0x0 },
+ { 0x2127c0, 0x0 },
+ { 0x128c0, 0x0 },
+ { 0x1128c0, 0x0 },
+ { 0x2128c0, 0x0 },
+ { 0x130c0, 0x0 },
+ { 0x1130c0, 0x0 },
+ { 0x2130c0, 0x0 },
+ { 0x131c0, 0x0 },
+ { 0x1131c0, 0x0 },
+ { 0x2131c0, 0x0 },
+ { 0x132c0, 0x0 },
+ { 0x1132c0, 0x0 },
+ { 0x2132c0, 0x0 },
+ { 0x133c0, 0x0 },
+ { 0x1133c0, 0x0 },
+ { 0x2133c0, 0x0 },
+ { 0x134c0, 0x0 },
+ { 0x1134c0, 0x0 },
+ { 0x2134c0, 0x0 },
+ { 0x135c0, 0x0 },
+ { 0x1135c0, 0x0 },
+ { 0x2135c0, 0x0 },
+ { 0x136c0, 0x0 },
+ { 0x1136c0, 0x0 },
+ { 0x2136c0, 0x0 },
+ { 0x137c0, 0x0 },
+ { 0x1137c0, 0x0 },
+ { 0x2137c0, 0x0 },
+ { 0x138c0, 0x0 },
+ { 0x1138c0, 0x0 },
+ { 0x2138c0, 0x0 },
+ { 0x100c1, 0x0 },
+ { 0x1100c1, 0x0 },
+ { 0x2100c1, 0x0 },
+ { 0x101c1, 0x0 },
+ { 0x1101c1, 0x0 },
+ { 0x2101c1, 0x0 },
+ { 0x102c1, 0x0 },
+ { 0x1102c1, 0x0 },
+ { 0x2102c1, 0x0 },
+ { 0x103c1, 0x0 },
+ { 0x1103c1, 0x0 },
+ { 0x2103c1, 0x0 },
+ { 0x104c1, 0x0 },
+ { 0x1104c1, 0x0 },
+ { 0x2104c1, 0x0 },
+ { 0x105c1, 0x0 },
+ { 0x1105c1, 0x0 },
+ { 0x2105c1, 0x0 },
+ { 0x106c1, 0x0 },
+ { 0x1106c1, 0x0 },
+ { 0x2106c1, 0x0 },
+ { 0x107c1, 0x0 },
+ { 0x1107c1, 0x0 },
+ { 0x2107c1, 0x0 },
+ { 0x108c1, 0x0 },
+ { 0x1108c1, 0x0 },
+ { 0x2108c1, 0x0 },
+ { 0x110c1, 0x0 },
+ { 0x1110c1, 0x0 },
+ { 0x2110c1, 0x0 },
+ { 0x111c1, 0x0 },
+ { 0x1111c1, 0x0 },
+ { 0x2111c1, 0x0 },
+ { 0x112c1, 0x0 },
+ { 0x1112c1, 0x0 },
+ { 0x2112c1, 0x0 },
+ { 0x113c1, 0x0 },
+ { 0x1113c1, 0x0 },
+ { 0x2113c1, 0x0 },
+ { 0x114c1, 0x0 },
+ { 0x1114c1, 0x0 },
+ { 0x2114c1, 0x0 },
+ { 0x115c1, 0x0 },
+ { 0x1115c1, 0x0 },
+ { 0x2115c1, 0x0 },
+ { 0x116c1, 0x0 },
+ { 0x1116c1, 0x0 },
+ { 0x2116c1, 0x0 },
+ { 0x117c1, 0x0 },
+ { 0x1117c1, 0x0 },
+ { 0x2117c1, 0x0 },
+ { 0x118c1, 0x0 },
+ { 0x1118c1, 0x0 },
+ { 0x2118c1, 0x0 },
+ { 0x120c1, 0x0 },
+ { 0x1120c1, 0x0 },
+ { 0x2120c1, 0x0 },
+ { 0x121c1, 0x0 },
+ { 0x1121c1, 0x0 },
+ { 0x2121c1, 0x0 },
+ { 0x122c1, 0x0 },
+ { 0x1122c1, 0x0 },
+ { 0x2122c1, 0x0 },
+ { 0x123c1, 0x0 },
+ { 0x1123c1, 0x0 },
+ { 0x2123c1, 0x0 },
+ { 0x124c1, 0x0 },
+ { 0x1124c1, 0x0 },
+ { 0x2124c1, 0x0 },
+ { 0x125c1, 0x0 },
+ { 0x1125c1, 0x0 },
+ { 0x2125c1, 0x0 },
+ { 0x126c1, 0x0 },
+ { 0x1126c1, 0x0 },
+ { 0x2126c1, 0x0 },
+ { 0x127c1, 0x0 },
+ { 0x1127c1, 0x0 },
+ { 0x2127c1, 0x0 },
+ { 0x128c1, 0x0 },
+ { 0x1128c1, 0x0 },
+ { 0x2128c1, 0x0 },
+ { 0x130c1, 0x0 },
+ { 0x1130c1, 0x0 },
+ { 0x2130c1, 0x0 },
+ { 0x131c1, 0x0 },
+ { 0x1131c1, 0x0 },
+ { 0x2131c1, 0x0 },
+ { 0x132c1, 0x0 },
+ { 0x1132c1, 0x0 },
+ { 0x2132c1, 0x0 },
+ { 0x133c1, 0x0 },
+ { 0x1133c1, 0x0 },
+ { 0x2133c1, 0x0 },
+ { 0x134c1, 0x0 },
+ { 0x1134c1, 0x0 },
+ { 0x2134c1, 0x0 },
+ { 0x135c1, 0x0 },
+ { 0x1135c1, 0x0 },
+ { 0x2135c1, 0x0 },
+ { 0x136c1, 0x0 },
+ { 0x1136c1, 0x0 },
+ { 0x2136c1, 0x0 },
+ { 0x137c1, 0x0 },
+ { 0x1137c1, 0x0 },
+ { 0x2137c1, 0x0 },
+ { 0x138c1, 0x0 },
+ { 0x1138c1, 0x0 },
+ { 0x2138c1, 0x0 },
+ { 0x10020, 0x0 },
+ { 0x110020, 0x0 },
+ { 0x210020, 0x0 },
+ { 0x11020, 0x0 },
+ { 0x111020, 0x0 },
+ { 0x211020, 0x0 },
+ { 0x12020, 0x0 },
+ { 0x112020, 0x0 },
+ { 0x212020, 0x0 },
+ { 0x13020, 0x0 },
+ { 0x113020, 0x0 },
+ { 0x213020, 0x0 },
+ { 0x20072, 0x0 },
+ { 0x20073, 0x0 },
+ { 0x20074, 0x0 },
+ { 0x100aa, 0x0 },
+ { 0x110aa, 0x0 },
+ { 0x120aa, 0x0 },
+ { 0x130aa, 0x0 },
+ { 0x20010, 0x0 },
+ { 0x120010, 0x0 },
+ { 0x220010, 0x0 },
+ { 0x20011, 0x0 },
+ { 0x120011, 0x0 },
+ { 0x220011, 0x0 },
+ { 0x100ae, 0x0 },
+ { 0x1100ae, 0x0 },
+ { 0x2100ae, 0x0 },
+ { 0x100af, 0x0 },
+ { 0x1100af, 0x0 },
+ { 0x2100af, 0x0 },
+ { 0x110ae, 0x0 },
+ { 0x1110ae, 0x0 },
+ { 0x2110ae, 0x0 },
+ { 0x110af, 0x0 },
+ { 0x1110af, 0x0 },
+ { 0x2110af, 0x0 },
+ { 0x120ae, 0x0 },
+ { 0x1120ae, 0x0 },
+ { 0x2120ae, 0x0 },
+ { 0x120af, 0x0 },
+ { 0x1120af, 0x0 },
+ { 0x2120af, 0x0 },
+ { 0x130ae, 0x0 },
+ { 0x1130ae, 0x0 },
+ { 0x2130ae, 0x0 },
+ { 0x130af, 0x0 },
+ { 0x1130af, 0x0 },
+ { 0x2130af, 0x0 },
+ { 0x20020, 0x0 },
+ { 0x120020, 0x0 },
+ { 0x220020, 0x0 },
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x0 },
+ { 0x100a2, 0x0 },
+ { 0x100a3, 0x0 },
+ { 0x100a4, 0x0 },
+ { 0x100a5, 0x0 },
+ { 0x100a6, 0x0 },
+ { 0x100a7, 0x0 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x0 },
+ { 0x110a2, 0x0 },
+ { 0x110a3, 0x0 },
+ { 0x110a4, 0x0 },
+ { 0x110a5, 0x0 },
+ { 0x110a6, 0x0 },
+ { 0x110a7, 0x0 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x0 },
+ { 0x120a2, 0x0 },
+ { 0x120a3, 0x0 },
+ { 0x120a4, 0x0 },
+ { 0x120a5, 0x0 },
+ { 0x120a6, 0x0 },
+ { 0x120a7, 0x0 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x0 },
+ { 0x130a2, 0x0 },
+ { 0x130a3, 0x0 },
+ { 0x130a4, 0x0 },
+ { 0x130a5, 0x0 },
+ { 0x130a6, 0x0 },
+ { 0x130a7, 0x0 },
+ { 0x2007c, 0x0 },
+ { 0x12007c, 0x0 },
+ { 0x22007c, 0x0 },
+ { 0x2007d, 0x0 },
+ { 0x12007d, 0x0 },
+ { 0x22007d, 0x0 },
+ { 0x400fd, 0x0 },
+ { 0x400c0, 0x0 },
+ { 0x90201, 0x0 },
+ { 0x190201, 0x0 },
+ { 0x290201, 0x0 },
+ { 0x90202, 0x0 },
+ { 0x190202, 0x0 },
+ { 0x290202, 0x0 },
+ { 0x90203, 0x0 },
+ { 0x190203, 0x0 },
+ { 0x290203, 0x0 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x90205, 0x0 },
+ { 0x190205, 0x0 },
+ { 0x290205, 0x0 },
+ { 0x90206, 0x0 },
+ { 0x190206, 0x0 },
+ { 0x290206, 0x0 },
+ { 0x90207, 0x0 },
+ { 0x190207, 0x0 },
+ { 0x290207, 0x0 },
+ { 0x90208, 0x0 },
+ { 0x190208, 0x0 },
+ { 0x290208, 0x0 },
+ { 0x10062, 0x0 },
+ { 0x10162, 0x0 },
+ { 0x10262, 0x0 },
+ { 0x10362, 0x0 },
+ { 0x10462, 0x0 },
+ { 0x10562, 0x0 },
+ { 0x10662, 0x0 },
+ { 0x10762, 0x0 },
+ { 0x10862, 0x0 },
+ { 0x11062, 0x0 },
+ { 0x11162, 0x0 },
+ { 0x11262, 0x0 },
+ { 0x11362, 0x0 },
+ { 0x11462, 0x0 },
+ { 0x11562, 0x0 },
+ { 0x11662, 0x0 },
+ { 0x11762, 0x0 },
+ { 0x11862, 0x0 },
+ { 0x12062, 0x0 },
+ { 0x12162, 0x0 },
+ { 0x12262, 0x0 },
+ { 0x12362, 0x0 },
+ { 0x12462, 0x0 },
+ { 0x12562, 0x0 },
+ { 0x12662, 0x0 },
+ { 0x12762, 0x0 },
+ { 0x12862, 0x0 },
+ { 0x13062, 0x0 },
+ { 0x13162, 0x0 },
+ { 0x13262, 0x0 },
+ { 0x13362, 0x0 },
+ { 0x13462, 0x0 },
+ { 0x13562, 0x0 },
+ { 0x13662, 0x0 },
+ { 0x13762, 0x0 },
+ { 0x13862, 0x0 },
+ { 0x20077, 0x0 },
+ { 0x10001, 0x0 },
+ { 0x11001, 0x0 },
+ { 0x12001, 0x0 },
+ { 0x13001, 0x0 },
+ { 0x10040, 0x0 },
+ { 0x10140, 0x0 },
+ { 0x10240, 0x0 },
+ { 0x10340, 0x0 },
+ { 0x10440, 0x0 },
+ { 0x10540, 0x0 },
+ { 0x10640, 0x0 },
+ { 0x10740, 0x0 },
+ { 0x10840, 0x0 },
+ { 0x10030, 0x0 },
+ { 0x10130, 0x0 },
+ { 0x10230, 0x0 },
+ { 0x10330, 0x0 },
+ { 0x10430, 0x0 },
+ { 0x10530, 0x0 },
+ { 0x10630, 0x0 },
+ { 0x10730, 0x0 },
+ { 0x10830, 0x0 },
+ { 0x11040, 0x0 },
+ { 0x11140, 0x0 },
+ { 0x11240, 0x0 },
+ { 0x11340, 0x0 },
+ { 0x11440, 0x0 },
+ { 0x11540, 0x0 },
+ { 0x11640, 0x0 },
+ { 0x11740, 0x0 },
+ { 0x11840, 0x0 },
+ { 0x11030, 0x0 },
+ { 0x11130, 0x0 },
+ { 0x11230, 0x0 },
+ { 0x11330, 0x0 },
+ { 0x11430, 0x0 },
+ { 0x11530, 0x0 },
+ { 0x11630, 0x0 },
+ { 0x11730, 0x0 },
+ { 0x11830, 0x0 },
+ { 0x12040, 0x0 },
+ { 0x12140, 0x0 },
+ { 0x12240, 0x0 },
+ { 0x12340, 0x0 },
+ { 0x12440, 0x0 },
+ { 0x12540, 0x0 },
+ { 0x12640, 0x0 },
+ { 0x12740, 0x0 },
+ { 0x12840, 0x0 },
+ { 0x12030, 0x0 },
+ { 0x12130, 0x0 },
+ { 0x12230, 0x0 },
+ { 0x12330, 0x0 },
+ { 0x12430, 0x0 },
+ { 0x12530, 0x0 },
+ { 0x12630, 0x0 },
+ { 0x12730, 0x0 },
+ { 0x12830, 0x0 },
+ { 0x13040, 0x0 },
+ { 0x13140, 0x0 },
+ { 0x13240, 0x0 },
+ { 0x13340, 0x0 },
+ { 0x13440, 0x0 },
+ { 0x13540, 0x0 },
+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+};
+
+/* P0 message block parameter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xfa0 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x3ff4 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x3ff4 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xf400 },
+ { 0x54033, 0x333f },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xf400 },
+ { 0x54039, 0x333f },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block parameter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3300 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3300 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P2 message block parameter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3300 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3300 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block parameter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xfa0 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x3ff4 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x3ff4 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xf400 },
+ { 0x54033, 0x333f },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xf400 },
+ { 0x54039, 0x333f },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x0 },
+ { 0x90033, 0xe8 },
+ { 0x90034, 0x109 },
+ { 0x90035, 0x2 },
+ { 0x90036, 0x10 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0xb },
+ { 0x90039, 0x7c0 },
+ { 0x9003a, 0x139 },
+ { 0x9003b, 0x44 },
+ { 0x9003c, 0x633 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x14f },
+ { 0x9003f, 0x630 },
+ { 0x90040, 0x159 },
+ { 0x90041, 0x47 },
+ { 0x90042, 0x633 },
+ { 0x90043, 0x149 },
+ { 0x90044, 0x4f },
+ { 0x90045, 0x633 },
+ { 0x90046, 0x179 },
+ { 0x90047, 0x8 },
+ { 0x90048, 0xe0 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x7c8 },
+ { 0x9004c, 0x109 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x1 },
+ { 0x9004f, 0x8 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x45a },
+ { 0x90052, 0x9 },
+ { 0x90053, 0x0 },
+ { 0x90054, 0x448 },
+ { 0x90055, 0x109 },
+ { 0x90056, 0x40 },
+ { 0x90057, 0x633 },
+ { 0x90058, 0x179 },
+ { 0x90059, 0x1 },
+ { 0x9005a, 0x618 },
+ { 0x9005b, 0x109 },
+ { 0x9005c, 0x40c0 },
+ { 0x9005d, 0x633 },
+ { 0x9005e, 0x149 },
+ { 0x9005f, 0x8 },
+ { 0x90060, 0x4 },
+ { 0x90061, 0x48 },
+ { 0x90062, 0x4040 },
+ { 0x90063, 0x633 },
+ { 0x90064, 0x149 },
+ { 0x90065, 0x0 },
+ { 0x90066, 0x4 },
+ { 0x90067, 0x48 },
+ { 0x90068, 0x40 },
+ { 0x90069, 0x633 },
+ { 0x9006a, 0x149 },
+ { 0x9006b, 0x10 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x18 },
+ { 0x9006e, 0x0 },
+ { 0x9006f, 0x4 },
+ { 0x90070, 0x78 },
+ { 0x90071, 0x549 },
+ { 0x90072, 0x633 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0xd49 },
+ { 0x90075, 0x633 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x94a },
+ { 0x90078, 0x633 },
+ { 0x90079, 0x159 },
+ { 0x9007a, 0x441 },
+ { 0x9007b, 0x633 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x42 },
+ { 0x9007e, 0x633 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x1 },
+ { 0x90081, 0x633 },
+ { 0x90082, 0x149 },
+ { 0x90083, 0x0 },
+ { 0x90084, 0xe0 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0xa },
+ { 0x90087, 0x10 },
+ { 0x90088, 0x109 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x149 },
+ { 0x9008c, 0x9 },
+ { 0x9008d, 0x3c0 },
+ { 0x9008e, 0x159 },
+ { 0x9008f, 0x18 },
+ { 0x90090, 0x10 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x0 },
+ { 0x90093, 0x3c0 },
+ { 0x90094, 0x109 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x48 },
+ { 0x90098, 0x18 },
+ { 0x90099, 0x4 },
+ { 0x9009a, 0x58 },
+ { 0x9009b, 0xb },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x1 },
+ { 0x9009f, 0x10 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x5 },
+ { 0x900a2, 0x7c0 },
+ { 0x900a3, 0x109 },
+ { 0x40000, 0x811 },
+ { 0x40020, 0x880 },
+ { 0x40040, 0x0 },
+ { 0x40060, 0x0 },
+ { 0x40001, 0x4008 },
+ { 0x40021, 0x83 },
+ { 0x40041, 0x4f },
+ { 0x40061, 0x0 },
+ { 0x40002, 0x4040 },
+ { 0x40022, 0x83 },
+ { 0x40042, 0x51 },
+ { 0x40062, 0x0 },
+ { 0x40003, 0x811 },
+ { 0x40023, 0x880 },
+ { 0x40043, 0x0 },
+ { 0x40063, 0x0 },
+ { 0x40004, 0x720 },
+ { 0x40024, 0xf },
+ { 0x40044, 0x1740 },
+ { 0x40064, 0x0 },
+ { 0x40005, 0x16 },
+ { 0x40025, 0x83 },
+ { 0x40045, 0x4b },
+ { 0x40065, 0x0 },
+ { 0x40006, 0x716 },
+ { 0x40026, 0xf },
+ { 0x40046, 0x2001 },
+ { 0x40066, 0x0 },
+ { 0x40007, 0x716 },
+ { 0x40027, 0xf },
+ { 0x40047, 0x2800 },
+ { 0x40067, 0x0 },
+ { 0x40008, 0x716 },
+ { 0x40028, 0xf },
+ { 0x40048, 0xf00 },
+ { 0x40068, 0x0 },
+ { 0x40009, 0x720 },
+ { 0x40029, 0xf },
+ { 0x40049, 0x1400 },
+ { 0x40069, 0x0 },
+ { 0x4000a, 0xe08 },
+ { 0x4002a, 0xc15 },
+ { 0x4004a, 0x0 },
+ { 0x4006a, 0x0 },
+ { 0x4000b, 0x625 },
+ { 0x4002b, 0x15 },
+ { 0x4004b, 0x0 },
+ { 0x4006b, 0x0 },
+ { 0x4000c, 0x4028 },
+ { 0x4002c, 0x80 },
+ { 0x4004c, 0x0 },
+ { 0x4006c, 0x0 },
+ { 0x4000d, 0xe08 },
+ { 0x4002d, 0xc1a },
+ { 0x4004d, 0x0 },
+ { 0x4006d, 0x0 },
+ { 0x4000e, 0x625 },
+ { 0x4002e, 0x1a },
+ { 0x4004e, 0x0 },
+ { 0x4006e, 0x0 },
+ { 0x4000f, 0x4040 },
+ { 0x4002f, 0x80 },
+ { 0x4004f, 0x0 },
+ { 0x4006f, 0x0 },
+ { 0x40010, 0x2604 },
+ { 0x40030, 0x15 },
+ { 0x40050, 0x0 },
+ { 0x40070, 0x0 },
+ { 0x40011, 0x708 },
+ { 0x40031, 0x5 },
+ { 0x40051, 0x0 },
+ { 0x40071, 0x2002 },
+ { 0x40012, 0x8 },
+ { 0x40032, 0x80 },
+ { 0x40052, 0x0 },
+ { 0x40072, 0x0 },
+ { 0x40013, 0x2604 },
+ { 0x40033, 0x1a },
+ { 0x40053, 0x0 },
+ { 0x40073, 0x0 },
+ { 0x40014, 0x708 },
+ { 0x40034, 0xa },
+ { 0x40054, 0x0 },
+ { 0x40074, 0x2002 },
+ { 0x40015, 0x4040 },
+ { 0x40035, 0x80 },
+ { 0x40055, 0x0 },
+ { 0x40075, 0x0 },
+ { 0x40016, 0x60a },
+ { 0x40036, 0x15 },
+ { 0x40056, 0x1200 },
+ { 0x40076, 0x0 },
+ { 0x40017, 0x61a },
+ { 0x40037, 0x15 },
+ { 0x40057, 0x1300 },
+ { 0x40077, 0x0 },
+ { 0x40018, 0x60a },
+ { 0x40038, 0x1a },
+ { 0x40058, 0x1200 },
+ { 0x40078, 0x0 },
+ { 0x40019, 0x642 },
+ { 0x40039, 0x1a },
+ { 0x40059, 0x1300 },
+ { 0x40079, 0x0 },
+ { 0x4001a, 0x4808 },
+ { 0x4003a, 0x880 },
+ { 0x4005a, 0x0 },
+ { 0x4007a, 0x0 },
+ { 0x900a4, 0x0 },
+ { 0x900a5, 0x790 },
+ { 0x900a6, 0x11a },
+ { 0x900a7, 0x8 },
+ { 0x900a8, 0x7aa },
+ { 0x900a9, 0x2a },
+ { 0x900aa, 0x10 },
+ { 0x900ab, 0x7b2 },
+ { 0x900ac, 0x2a },
+ { 0x900ad, 0x0 },
+ { 0x900ae, 0x7c8 },
+ { 0x900af, 0x109 },
+ { 0x900b0, 0x10 },
+ { 0x900b1, 0x10 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x10 },
+ { 0x900b4, 0x2a8 },
+ { 0x900b5, 0x129 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0x370 },
+ { 0x900b8, 0x129 },
+ { 0x900b9, 0xa },
+ { 0x900ba, 0x3c8 },
+ { 0x900bb, 0x1a9 },
+ { 0x900bc, 0xc },
+ { 0x900bd, 0x408 },
+ { 0x900be, 0x199 },
+ { 0x900bf, 0x14 },
+ { 0x900c0, 0x790 },
+ { 0x900c1, 0x11a },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x18 },
+ { 0x900c5, 0xe },
+ { 0x900c6, 0x408 },
+ { 0x900c7, 0x199 },
+ { 0x900c8, 0x8 },
+ { 0x900c9, 0x8568 },
+ { 0x900ca, 0x108 },
+ { 0x900cb, 0x18 },
+ { 0x900cc, 0x790 },
+ { 0x900cd, 0x16a },
+ { 0x900ce, 0x8 },
+ { 0x900cf, 0x1d8 },
+ { 0x900d0, 0x169 },
+ { 0x900d1, 0x10 },
+ { 0x900d2, 0x8558 },
+ { 0x900d3, 0x168 },
+ { 0x900d4, 0x70 },
+ { 0x900d5, 0x788 },
+ { 0x900d6, 0x16a },
+ { 0x900d7, 0x1ff8 },
+ { 0x900d8, 0x85a8 },
+ { 0x900d9, 0x1e8 },
+ { 0x900da, 0x50 },
+ { 0x900db, 0x798 },
+ { 0x900dc, 0x16a },
+ { 0x900dd, 0x60 },
+ { 0x900de, 0x7a0 },
+ { 0x900df, 0x16a },
+ { 0x900e0, 0x8 },
+ { 0x900e1, 0x8310 },
+ { 0x900e2, 0x168 },
+ { 0x900e3, 0x8 },
+ { 0x900e4, 0xa310 },
+ { 0x900e5, 0x168 },
+ { 0x900e6, 0xa },
+ { 0x900e7, 0x408 },
+ { 0x900e8, 0x169 },
+ { 0x900e9, 0x6e },
+ { 0x900ea, 0x0 },
+ { 0x900eb, 0x68 },
+ { 0x900ec, 0x0 },
+ { 0x900ed, 0x408 },
+ { 0x900ee, 0x169 },
+ { 0x900ef, 0x0 },
+ { 0x900f0, 0x8310 },
+ { 0x900f1, 0x168 },
+ { 0x900f2, 0x0 },
+ { 0x900f3, 0xa310 },
+ { 0x900f4, 0x168 },
+ { 0x900f5, 0x1ff8 },
+ { 0x900f6, 0x85a8 },
+ { 0x900f7, 0x1e8 },
+ { 0x900f8, 0x68 },
+ { 0x900f9, 0x798 },
+ { 0x900fa, 0x16a },
+ { 0x900fb, 0x78 },
+ { 0x900fc, 0x7a0 },
+ { 0x900fd, 0x16a },
+ { 0x900fe, 0x68 },
+ { 0x900ff, 0x790 },
+ { 0x90100, 0x16a },
+ { 0x90101, 0x8 },
+ { 0x90102, 0x8b10 },
+ { 0x90103, 0x168 },
+ { 0x90104, 0x8 },
+ { 0x90105, 0xab10 },
+ { 0x90106, 0x168 },
+ { 0x90107, 0xa },
+ { 0x90108, 0x408 },
+ { 0x90109, 0x169 },
+ { 0x9010a, 0x58 },
+ { 0x9010b, 0x0 },
+ { 0x9010c, 0x68 },
+ { 0x9010d, 0x0 },
+ { 0x9010e, 0x408 },
+ { 0x9010f, 0x169 },
+ { 0x90110, 0x0 },
+ { 0x90111, 0x8b10 },
+ { 0x90112, 0x168 },
+ { 0x90113, 0x1 },
+ { 0x90114, 0xab10 },
+ { 0x90115, 0x168 },
+ { 0x90116, 0x0 },
+ { 0x90117, 0x1d8 },
+ { 0x90118, 0x169 },
+ { 0x90119, 0x80 },
+ { 0x9011a, 0x790 },
+ { 0x9011b, 0x16a },
+ { 0x9011c, 0x18 },
+ { 0x9011d, 0x7aa },
+ { 0x9011e, 0x6a },
+ { 0x9011f, 0xa },
+ { 0x90120, 0x0 },
+ { 0x90121, 0x1e9 },
+ { 0x90122, 0x8 },
+ { 0x90123, 0x8080 },
+ { 0x90124, 0x108 },
+ { 0x90125, 0xf },
+ { 0x90126, 0x408 },
+ { 0x90127, 0x169 },
+ { 0x90128, 0xc },
+ { 0x90129, 0x0 },
+ { 0x9012a, 0x68 },
+ { 0x9012b, 0x9 },
+ { 0x9012c, 0x0 },
+ { 0x9012d, 0x1a9 },
+ { 0x9012e, 0x0 },
+ { 0x9012f, 0x408 },
+ { 0x90130, 0x169 },
+ { 0x90131, 0x0 },
+ { 0x90132, 0x8080 },
+ { 0x90133, 0x108 },
+ { 0x90134, 0x8 },
+ { 0x90135, 0x7aa },
+ { 0x90136, 0x6a },
+ { 0x90137, 0x0 },
+ { 0x90138, 0x8568 },
+ { 0x90139, 0x108 },
+ { 0x9013a, 0xb7 },
+ { 0x9013b, 0x790 },
+ { 0x9013c, 0x16a },
+ { 0x9013d, 0x1f },
+ { 0x9013e, 0x0 },
+ { 0x9013f, 0x68 },
+ { 0x90140, 0x8 },
+ { 0x90141, 0x8558 },
+ { 0x90142, 0x168 },
+ { 0x90143, 0xf },
+ { 0x90144, 0x408 },
+ { 0x90145, 0x169 },
+ { 0x90146, 0xd },
+ { 0x90147, 0x0 },
+ { 0x90148, 0x68 },
+ { 0x90149, 0x0 },
+ { 0x9014a, 0x408 },
+ { 0x9014b, 0x169 },
+ { 0x9014c, 0x0 },
+ { 0x9014d, 0x8558 },
+ { 0x9014e, 0x168 },
+ { 0x9014f, 0x8 },
+ { 0x90150, 0x3c8 },
+ { 0x90151, 0x1a9 },
+ { 0x90152, 0x3 },
+ { 0x90153, 0x370 },
+ { 0x90154, 0x129 },
+ { 0x90155, 0x20 },
+ { 0x90156, 0x2aa },
+ { 0x90157, 0x9 },
+ { 0x90158, 0x8 },
+ { 0x90159, 0xe8 },
+ { 0x9015a, 0x109 },
+ { 0x9015b, 0x0 },
+ { 0x9015c, 0x8140 },
+ { 0x9015d, 0x10c },
+ { 0x9015e, 0x10 },
+ { 0x9015f, 0x8138 },
+ { 0x90160, 0x104 },
+ { 0x90161, 0x8 },
+ { 0x90162, 0x448 },
+ { 0x90163, 0x109 },
+ { 0x90164, 0xf },
+ { 0x90165, 0x7c0 },
+ { 0x90166, 0x109 },
+ { 0x90167, 0x0 },
+ { 0x90168, 0xe8 },
+ { 0x90169, 0x109 },
+ { 0x9016a, 0x47 },
+ { 0x9016b, 0x630 },
+ { 0x9016c, 0x109 },
+ { 0x9016d, 0x8 },
+ { 0x9016e, 0x618 },
+ { 0x9016f, 0x109 },
+ { 0x90170, 0x8 },
+ { 0x90171, 0xe0 },
+ { 0x90172, 0x109 },
+ { 0x90173, 0x0 },
+ { 0x90174, 0x7c8 },
+ { 0x90175, 0x109 },
+ { 0x90176, 0x8 },
+ { 0x90177, 0x8140 },
+ { 0x90178, 0x10c },
+ { 0x90179, 0x0 },
+ { 0x9017a, 0x478 },
+ { 0x9017b, 0x109 },
+ { 0x9017c, 0x0 },
+ { 0x9017d, 0x1 },
+ { 0x9017e, 0x8 },
+ { 0x9017f, 0x8 },
+ { 0x90180, 0x4 },
+ { 0x90181, 0x0 },
+ { 0x90006, 0x8 },
+ { 0x90007, 0x7c8 },
+ { 0x90008, 0x109 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x400 },
+ { 0x9000b, 0x106 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x9001f, 0x29 },
+ { 0x90026, 0x68 },
+ { 0x400d0, 0x0 },
+ { 0x400d1, 0x101 },
+ { 0x400d2, 0x105 },
+ { 0x400d3, 0x107 },
+ { 0x400d4, 0x10f },
+ { 0x400d5, 0x202 },
+ { 0x400d6, 0x20a },
+ { 0x400d7, 0x20b },
+ { 0x2003a, 0x2 },
+ { 0x200be, 0x3 },
+ { 0x2000b, 0x465 },
+ { 0x2000c, 0xfa },
+ { 0x2000d, 0x9c4 },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0x70 },
+ { 0x12000c, 0x19 },
+ { 0x12000d, 0xfa },
+ { 0x12000e, 0x10 },
+ { 0x22000b, 0x1c },
+ { 0x22000c, 0x6 },
+ { 0x22000d, 0x3e },
+ { 0x22000e, 0x10 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0x2060 },
+ { 0x90013, 0x6152 },
+ { 0x20010, 0x5a },
+ { 0x20011, 0x3 },
+ { 0x40080, 0xe0 },
+ { 0x40081, 0x12 },
+ { 0x40082, 0xe0 },
+ { 0x40083, 0x12 },
+ { 0x40084, 0xe0 },
+ { 0x40085, 0x12 },
+ { 0x140080, 0xe0 },
+ { 0x140081, 0x12 },
+ { 0x140082, 0xe0 },
+ { 0x140083, 0x12 },
+ { 0x140084, 0xe0 },
+ { 0x140085, 0x12 },
+ { 0x240080, 0xe0 },
+ { 0x240081, 0x12 },
+ { 0x240082, 0xe0 },
+ { 0x240083, 0x12 },
+ { 0x240084, 0xe0 },
+ { 0x240085, 0x12 },
+ { 0x400fd, 0xf },
+ { 0x10011, 0x1 },
+ { 0x10012, 0x1 },
+ { 0x10013, 0x180 },
+ { 0x10018, 0x1 },
+ { 0x10002, 0x6209 },
+ { 0x100b2, 0x1 },
+ { 0x101b4, 0x1 },
+ { 0x102b4, 0x1 },
+ { 0x103b4, 0x1 },
+ { 0x104b4, 0x1 },
+ { 0x105b4, 0x1 },
+ { 0x106b4, 0x1 },
+ { 0x107b4, 0x1 },
+ { 0x108b4, 0x1 },
+ { 0x11011, 0x1 },
+ { 0x11012, 0x1 },
+ { 0x11013, 0x180 },
+ { 0x11018, 0x1 },
+ { 0x11002, 0x6209 },
+ { 0x110b2, 0x1 },
+ { 0x111b4, 0x1 },
+ { 0x112b4, 0x1 },
+ { 0x113b4, 0x1 },
+ { 0x114b4, 0x1 },
+ { 0x115b4, 0x1 },
+ { 0x116b4, 0x1 },
+ { 0x117b4, 0x1 },
+ { 0x118b4, 0x1 },
+ { 0x12011, 0x1 },
+ { 0x12012, 0x1 },
+ { 0x12013, 0x180 },
+ { 0x12018, 0x1 },
+ { 0x12002, 0x6209 },
+ { 0x120b2, 0x1 },
+ { 0x121b4, 0x1 },
+ { 0x122b4, 0x1 },
+ { 0x123b4, 0x1 },
+ { 0x124b4, 0x1 },
+ { 0x125b4, 0x1 },
+ { 0x126b4, 0x1 },
+ { 0x127b4, 0x1 },
+ { 0x128b4, 0x1 },
+ { 0x13011, 0x1 },
+ { 0x13012, 0x1 },
+ { 0x13013, 0x180 },
+ { 0x13018, 0x1 },
+ { 0x13002, 0x6209 },
+ { 0x130b2, 0x1 },
+ { 0x131b4, 0x1 },
+ { 0x132b4, 0x1 },
+ { 0x133b4, 0x1 },
+ { 0x134b4, 0x1 },
+ { 0x135b4, 0x1 },
+ { 0x136b4, 0x1 },
+ { 0x137b4, 0x1 },
+ { 0x138b4, 0x1 },
+ { 0x20089, 0x1 },
+ { 0x20088, 0x19 },
+ { 0xc0080, 0x2 },
+ { 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 4000mts 1D */
+ .drate = 4000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 4000mts 2D */
+ .drate = 4000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 4000, 400, 100, },
+};
+
+static void apply_cfg_patch(struct dram_cfg_param *cfg, int cfg_sz,
+ struct dram_cfg_param *patch, int patch_sz)
+{
+ int i, j;
+
+ for (i = 0; i < cfg_sz; i++)
+ for (j = 0; j < patch_sz; j++)
+ if (cfg[i].reg == patch[j].reg)
+ cfg[i].val = patch[j].val;
+}
+
+void lpddr4_single_rank_training_patch(void)
+{
+ apply_cfg_patch(ddr_ddrc_cfg, ARRAY_SIZE(ddr_ddrc_cfg),
+ ddr_ddrc_cfg_single_rank_patch,
+ ARRAY_SIZE(ddr_ddrc_cfg_single_rank_patch));
+
+ apply_cfg_patch(ddr_fsp0_cfg, ARRAY_SIZE(ddr_fsp0_cfg),
+ ddr_fsp0_cfg_single_rank_patch,
+ ARRAY_SIZE(ddr_fsp0_cfg_single_rank_patch));
+
+ apply_cfg_patch(ddr_fsp1_cfg, ARRAY_SIZE(ddr_fsp1_cfg),
+ ddr_fsp1_cfg_single_rank_patch,
+ ARRAY_SIZE(ddr_fsp1_cfg_single_rank_patch));
+
+ apply_cfg_patch(ddr_fsp2_cfg, ARRAY_SIZE(ddr_fsp2_cfg),
+ ddr_fsp2_cfg_single_rank_patch,
+ ARRAY_SIZE(ddr_fsp2_cfg_single_rank_patch));
+
+ apply_cfg_patch(ddr_fsp0_2d_cfg, ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ ddr_fsp0_2d_cfg_single_rank_patch,
+ ARRAY_SIZE(ddr_fsp0_2d_cfg_single_rank_patch));
+}
diff --git a/board/toradex/smarc-imx8mp/lpddr4_timing.h b/board/toradex/smarc-imx8mp/lpddr4_timing.h
new file mode 100644
index 0000000..f61789c
--- /dev/null
+++ b/board/toradex/smarc-imx8mp/lpddr4_timing.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* Copyright (C) 2024 Toradex */
+
+#ifndef __LPDDR4_TIMING_H__
+#define __LPDDR4_TIMING_H__
+
+void lpddr4_single_rank_training_patch(void);
+
+#endif /* __LPDDR4_TIMING_H__ */
diff --git a/board/toradex/smarc-imx8mp/smarc-imx8mp.c b/board/toradex/smarc-imx8mp/smarc-imx8mp.c
new file mode 100644
index 0000000..bbe3715
--- /dev/null
+++ b/board/toradex/smarc-imx8mp/smarc-imx8mp.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/* Copyright (C) 2024 Toradex */
+
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm-generic/gpio.h>
+#include <linux/errno.h>
+
+#include "../common/tdx-cfg-block.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int board_phys_sdram_size(phys_size_t *size)
+{
+ if (!size)
+ return -EINVAL;
+
+ *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE);
+
+ return 0;
+}
+
+#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP)
+static bool board_has_wifi(void)
+{
+ struct gpio_desc *desc;
+
+ if (!gpio_hog_lookup_name("BT_UART_RXD_GPIO", &desc))
+ return !!dm_gpio_get_value(desc);
+
+ return true;
+}
+
+/*
+ * Module variants with a Wi-Fi/Bluetooth module use UART3 for Bluetooth,
+ * those without use UART3 as the SMARC SER3 UART.
+ * Test for a Wi-Fi module and if none found reassign UART3 interface to
+ * the SMARC SER3 pins.
+ */
+static void ft_board_assign_uart(void *blob)
+{
+ const char *uart_path = "/soc@0/bus@30800000/spba-bus@30800000/serial@30880000";
+ const char *pinctrl_path = "/soc@0/bus@30000000/pinctrl@30330000/uart3grp";
+ int pinctrl_offset;
+ int uart_offset;
+ int bt_offset;
+ u32 phandle;
+
+ if (board_has_wifi())
+ return;
+
+ uart_offset = fdt_path_offset(blob, uart_path);
+ if (uart_offset < 0)
+ return;
+
+ fdt_delprop(blob, uart_offset, "uart-has-rtscts");
+ bt_offset = fdt_subnode_offset(blob, uart_offset, "bluetooth");
+ if (bt_offset < 0)
+ return;
+
+ fdt_del_node(blob, bt_offset);
+
+ pinctrl_offset = fdt_path_offset(blob, pinctrl_path);
+ if (pinctrl_offset < 0)
+ return;
+
+ phandle = fdt_get_phandle(blob, pinctrl_offset);
+ if (phandle < 0)
+ return;
+
+ fdt_setprop_u32(blob, uart_offset, "pinctrl-0", phandle);
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ ft_board_assign_uart(blob);
+
+ return ft_common_board_setup(blob, bd);
+}
+#endif
diff --git a/board/toradex/smarc-imx8mp/smarc-imx8mp.env b/board/toradex/smarc-imx8mp/smarc-imx8mp.env
new file mode 100644
index 0000000..58f152e
--- /dev/null
+++ b/board/toradex/smarc-imx8mp/smarc-imx8mp.env
@@ -0,0 +1,20 @@
+boot_script_dhcp=boot.scr
+boot_targets=mmc1 mmc0 dhcp
+console=ttymxc1
+fdt_addr_r=0x50200000
+fdt_board=dev
+initrd_addr=0x43800000
+initrd_high=0xffffffffffffffff
+kernel_addr_r=CONFIG_SYS_LOAD_ADDR
+kernel_comp_addr_r=0x40200000
+kernel_comp_size=0x08000000
+ramdisk_addr_r=0x50300000
+scriptaddr=0x50280000
+
+update_uboot=
+ askenv confirm Did you load flash.bin (y/N)?;
+ if test $confirm = y; then
+ setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt
+ ${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0
+ ${blkcnt};
+ fi
diff --git a/board/toradex/smarc-imx8mp/spl.c b/board/toradex/smarc-imx8mp/spl.c
new file mode 100644
index 0000000..32233c0
--- /dev/null
+++ b/board/toradex/smarc-imx8mp/spl.c
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/* Copyright (C) 2024 Toradex */
+
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <dm/device.h>
+#include <power/pmic.h>
+#include <power/pca9450.h>
+
+#include "lpddr4_timing.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+ return BOOT_DEVICE_BOOTROM;
+}
+
+void spl_dram_init(void)
+{
+ /*
+ * Try configuring for dual rank memory falling back to single rank
+ */
+ if (!ddr_init(&dram_timing)) {
+ puts("DDR configured as dual rank\n");
+ return;
+ }
+
+ lpddr4_single_rank_training_patch();
+ if (!ddr_init(&dram_timing)) {
+ puts("DDR configured as single rank\n");
+ return;
+ }
+ puts("DDR configuration failed\n");
+}
+
+void spl_board_init(void)
+{
+ arch_misc_init();
+
+ /*
+ * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
+ * not allow to change it. Should set the clock after PMIC
+ * setting done. Default is 400Mhz (system_pll1_800m with div = 2)
+ * set by ROM for ND VDD_SOC
+ */
+ clock_enable(CCGR_GIC, 0);
+ clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
+ clock_enable(CCGR_GIC, 1);
+
+ puts("Normal Boot\n");
+}
+
+int power_init_board(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = pmic_get("pmic@25", &dev);
+ if (ret == -ENODEV) {
+ puts("No pmic@25\n");
+ return 0;
+ }
+ if (ret < 0)
+ return ret;
+
+ /* BUCKxOUT_DVS0/1 control BUCK123 output */
+ pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
+
+ /*
+ * Increase VDD_SOC to typical value 0.95V before first
+ * DRAM access, set DVS1 to 0.85V for suspend.
+ * Enable DVS control through PMIC_STBY_REQ and
+ * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
+ */
+ if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV))
+ /* set DVS0 to 0.85v for special case */
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
+ else
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1c);
+
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
+ pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
+
+ /*
+ * Kernel uses OD/OD freq for SOC.
+ * To avoid timing risk from SOC to ARM,increase VDD_ARM to OD
+ * voltage 0.95V.
+ */
+ pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c);
+
+ /* set LDO4 and CONFIG2 to enable the I2C level translator */
+ pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59);
+ pmic_reg_write(dev, PCA9450_CONFIG2, 0x1);
+
+ return 0;
+}
+
+/* Do not use BSS area in this phase */
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ arch_cpu_init();
+
+ init_uart_clk(3);
+
+ ret = spl_early_init();
+ if (ret) {
+ debug("spl_init() failed: %d\n", ret);
+ hang();
+ }
+
+ preloader_console_init();
+
+ enable_tzc380();
+
+ /* PMIC initialization */
+ power_init_board();
+
+ /* DDR initialization */
+ spl_dram_init();
+}
diff --git a/board/vscom/baltos/Makefile b/board/vscom/baltos/Makefile
index 6ef87c2..7df62fa 100644
--- a/board/vscom/baltos/Makefile
+++ b/board/vscom/baltos/Makefile
@@ -4,7 +4,7 @@
#
# Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
-ifeq ($(CONFIG_$(XPL_)SKIP_LOWLEVEL_INIT),)
+ifeq ($(CONFIG_$(PHASE_)SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif
diff --git a/board/wexler/qc750/Kconfig b/board/wexler/qc750/Kconfig
index 45a1e5e..b449720 100644
--- a/board/wexler/qc750/Kconfig
+++ b/board/wexler/qc750/Kconfig
@@ -7,6 +7,10 @@
default "wexler"
config SYS_CONFIG_NAME
- default "qc750"
+ default "tegra"
+
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "Wexler QC750"
endif
diff --git a/board/xiaomi/mocha/Kconfig b/board/xiaomi/mocha/Kconfig
index 25c61d4..bb53cc5 100644
--- a/board/xiaomi/mocha/Kconfig
+++ b/board/xiaomi/mocha/Kconfig
@@ -9,4 +9,8 @@
config SYS_CONFIG_NAME
default "mocha"
+config TEGRA_BOARD_STRING
+ string "Default Tegra board name"
+ default "Xiaomi Mocha"
+
endif
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index deea6c7..8ffe742 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -80,7 +80,7 @@
};
static int highest_id = -1;
-static struct xilinx_board_description *board_info;
+static struct xilinx_board_description *board_info __section(".data");
#define XILINX_I2C_DETECTION_BITS sizeof(struct fru_common_hdr)
@@ -468,6 +468,9 @@
ret |= env_set_addr("bootm_size", (void *)bootm_size);
for (id = 0; id <= highest_id; id++) {
+ if (!board_info)
+ break;
+
desc = &board_info[id];
if (desc && desc->header == EEPROM_HEADER_MAGIC) {
if (desc->manufacturer[0])
diff --git a/board/xilinx/common/board.h b/board/xilinx/common/board.h
index 64d6576..cb86c4c 100644
--- a/board/xilinx/common/board.h
+++ b/board/xilinx/common/board.h
@@ -18,4 +18,7 @@
char *soc_name_decode(void);
bool soc_detection(void);
+
+void configure_capsule_updates(void);
+
#endif /* BOARD_XILINX_COMMON_BOARD_H */
diff --git a/board/xilinx/versal-net/Kconfig b/board/xilinx/versal-net/Kconfig
deleted file mode 100644
index 2484429..0000000
--- a/board/xilinx/versal-net/Kconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Copyright (C) 2020 - 2022, Xilinx, Inc.
-# Copyright (C) 2022, Advanced Micro Devices, Inc.
-#
-
-if ARCH_VERSAL_NET
-
-config CMD_VERSAL_NET
- bool "Enable Versal NET specific commands"
- default y
- depends on ZYNQMP_FIRMWARE
- help
- Select this to enable Versal NET specific commands.
- Commands like versalnet loadpdi are enabled by this.
-
-endif
diff --git a/board/xilinx/versal-net/Makefile b/board/xilinx/versal-net/Makefile
index f9ff07c..2008d4e 100644
--- a/board/xilinx/versal-net/Makefile
+++ b/board/xilinx/versal-net/Makefile
@@ -7,4 +7,3 @@
#
obj-y := board.o
-obj-$(CONFIG_CMD_VERSAL_NET) += cmds.o
diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c
index 4d5913c..65b2a45 100644
--- a/board/xilinx/versal-net/board.c
+++ b/board/xilinx/versal-net/board.c
@@ -21,6 +21,8 @@
#include <asm/arch/sys_proto.h>
#include <dm/device.h>
#include <dm/uclass.h>
+#include <zynqmp_firmware.h>
+#include <versalpl.h>
#include "../common/board.h"
#include <linux/bitfield.h>
@@ -29,10 +31,21 @@
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_FPGA_VERSALPL)
+static xilinx_desc versalpl = {
+ xilinx_versal_net, csu_dma, 1, &versal_op, 0, &versal_op, NULL,
+ FPGA_LEGACY
+};
+#endif
+
int board_init(void)
{
printf("EL Level:\tEL%d\n", current_el());
+#if defined(CONFIG_FPGA_VERSALPL)
+ fpga_init();
+ fpga_add(fpga_xilinx, &versalpl);
+#endif
return 0;
}
@@ -184,7 +197,11 @@
u8 bootmode;
u32 reg = 0;
- reg = readl(&crp_base->boot_mode_usr);
+ if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3) {
+ reg = zynqmp_pm_get_bootmode_reg();
+ } else {
+ reg = readl(&crp_base->boot_mode_usr);
+ }
if (reg >> BOOT_MODE_ALT_SHIFT)
reg >>= BOOT_MODE_ALT_SHIFT;
diff --git a/board/xilinx/versal-net/cmds.c b/board/xilinx/versal-net/cmds.c
deleted file mode 100644
index e8b669f..0000000
--- a/board/xilinx/versal-net/cmds.c
+++ /dev/null
@@ -1,80 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2023, Advanced Micro Devices, Inc.
- *
- * Michal Simek <michal.simek@amd.com>
- */
-
-#include <cpu_func.h>
-#include <command.h>
-#include <log.h>
-#include <memalign.h>
-#include <versalpl.h>
-#include <vsprintf.h>
-#include <zynqmp_firmware.h>
-
-/**
- * do_versalnet_load_pdi - Handle the "versalnet load pdi" command-line command
- * @cmdtp: Command data struct pointer
- * @flag: Command flag
- * @argc: Command-line argument count
- * @argv: Array of command-line arguments
- *
- * Processes the Versal NET load pdi command
- *
- * Return: return 0 on success, Error value if command fails.
- * CMD_RET_USAGE incase of incorrect/missing parameters.
- */
-static int do_versalnet_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc,
- char * const argv[])
-{
- u32 buf_lo, buf_hi;
- u32 ret_payload[PAYLOAD_ARG_CNT];
- ulong addr, *pdi_buf;
- size_t len;
- int ret;
-
- if (argc != cmdtp->maxargs) {
- debug("pdi_load: incorrect parameters passed\n");
- return CMD_RET_USAGE;
- }
-
- addr = simple_strtol(argv[1], NULL, 16);
- if (!addr) {
- debug("pdi_load: zero pdi_data address\n");
- return CMD_RET_USAGE;
- }
-
- len = hextoul(argv[2], NULL);
- if (!len) {
- debug("pdi_load: zero size\n");
- return CMD_RET_USAGE;
- }
-
- pdi_buf = (ulong *)ALIGN((ulong)addr, ARCH_DMA_MINALIGN);
- if ((ulong)addr != (ulong)pdi_buf) {
- memcpy((void *)pdi_buf, (void *)addr, len);
- debug("Pdi addr:0x%lx aligned to 0x%lx\n",
- addr, (ulong)pdi_buf);
- }
-
- flush_dcache_range((ulong)pdi_buf, (ulong)pdi_buf + len);
-
- buf_lo = lower_32_bits((ulong)pdi_buf);
- buf_hi = upper_32_bits((ulong)pdi_buf);
-
- ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
- buf_hi, 0, ret_payload);
- if (ret)
- printf("PDI load failed with err: 0x%08x\n", ret);
-
- return cmd_process_error(cmdtp, ret);
-}
-
-U_BOOT_LONGHELP(versalnet,
- "loadpdi addr len - Load pdi image\n"
- "load pdi image at ddr address 'addr' with pdi image size 'len'\n");
-
-U_BOOT_CMD_WITH_SUBCMDS(versalnet, "Versal NET sub-system", versalnet_help_text,
- U_BOOT_SUBCMD_MKENT(loadpdi, 3, 1,
- do_versalnet_load_pdi));
diff --git a/board/xilinx/versal/Kconfig b/board/xilinx/versal/Kconfig
deleted file mode 100644
index c0cccc2..0000000
--- a/board/xilinx/versal/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-# Copyright (c) 2020, Xilinx, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0
-
-if ARCH_VERSAL
-
-config CMD_VERSAL
- bool "Enable Versal specific commands"
- default y
- depends on ZYNQMP_FIRMWARE
- help
- Enable Versal specific commands.
-
-endif
diff --git a/board/xilinx/versal/Makefile b/board/xilinx/versal/Makefile
index d912f2e..761e084 100644
--- a/board/xilinx/versal/Makefile
+++ b/board/xilinx/versal/Makefile
@@ -5,4 +5,3 @@
#
obj-y := board.o
-obj-$(CONFIG_CMD_VERSAL) += cmds.o
diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
index b4483d0..9371c30 100644
--- a/board/xilinx/versal/board.c
+++ b/board/xilinx/versal/board.c
@@ -8,6 +8,7 @@
#include <cpu_func.h>
#include <dfu.h>
#include <env.h>
+#include <efi_loader.h>
#include <fdtdec.h>
#include <init.h>
#include <env_internal.h>
@@ -26,6 +27,7 @@
#include <dm/device.h>
#include <dm/uclass.h>
#include <versalpl.h>
+#include <zynqmp_firmware.h>
#include "../common/board.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -42,7 +44,11 @@
u8 bootmode;
u32 reg = 0;
- reg = readl(&crp_base->boot_mode_usr);
+ if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3) {
+ reg = zynqmp_pm_get_bootmode_reg();
+ } else {
+ reg = readl(&crp_base->boot_mode_usr);
+ }
if (reg >> BOOT_MODE_ALT_SHIFT)
reg >>= BOOT_MODE_ALT_SHIFT;
@@ -55,12 +61,18 @@
static u32 versal_multi_boot(void)
{
u8 bootmode = versal_get_bootmode();
+ u32 reg = 0;
/* Mostly workaround for QEMU CI pipeline */
if (bootmode == JTAG_MODE)
return 0;
- return readl(0xF1110004);
+ if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3)
+ reg = zynqmp_pm_get_pmc_multi_boot_reg();
+ else
+ reg = readl(PMC_MULTI_BOOT_REG);
+
+ return reg & PMC_MULTI_BOOT_MASK;
}
int board_init(void)
@@ -271,6 +283,7 @@
env_targets ? env_targets : "");
env_set("boot_targets", new_targets);
+ free(new_targets);
}
return 0;
@@ -280,6 +293,9 @@
{
int ret;
+ if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
+ configure_capsule_updates();
+
if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
debug("Saved variables - Skipping\n");
return 0;
@@ -356,8 +372,6 @@
}
#endif
-#if defined(CONFIG_SET_DFU_ALT_INFO)
-
#define DFU_ALT_BUF_LEN SZ_1K
static void mtd_found_part(u32 *base, u32 *size)
@@ -385,7 +399,7 @@
}
}
-void set_dfu_alt_info(char *interface, char *devstr)
+void configure_capsule_updates(void)
{
int bootseq = 0, len = 0;
u32 multiboot = versal_multi_boot();
@@ -393,10 +407,7 @@
ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
- if (env_get("dfu_alt_info"))
- return;
-
- memset(buf, 0, sizeof(buf));
+ memset(buf, 0, DFU_ALT_BUF_LEN);
multiboot = env_get_hex("multiboot", multiboot);
@@ -436,7 +447,6 @@
return;
}
- env_set("dfu_alt_info", buf);
- puts("DFU alt info setting: done\n");
+ update_info.dfu_string = strdup(buf);
+ debug("Capsule DFU: %s\n", update_info.dfu_string);
}
-#endif
diff --git a/board/xilinx/versal/cmds.c b/board/xilinx/versal/cmds.c
deleted file mode 100644
index c787935..0000000
--- a/board/xilinx/versal/cmds.c
+++ /dev/null
@@ -1,101 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * (C) Copyright 2020 Xilinx, Inc.
- * Michal Simek <michal.simek@amd.com>
- */
-
-#include <cpu_func.h>
-#include <command.h>
-#include <log.h>
-#include <memalign.h>
-#include <versalpl.h>
-#include <vsprintf.h>
-#include <zynqmp_firmware.h>
-
-static int do_versal_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc,
- char * const argv[])
-{
- u32 buf_lo, buf_hi;
- u32 ret_payload[PAYLOAD_ARG_CNT];
- ulong addr, *pdi_buf;
- size_t len;
- int ret;
-
- if (argc != cmdtp->maxargs) {
- debug("pdi_load: incorrect parameters passed\n");
- return CMD_RET_USAGE;
- }
-
- addr = simple_strtol(argv[2], NULL, 16);
- if (!addr) {
- debug("pdi_load: zero pdi_data address\n");
- return CMD_RET_USAGE;
- }
-
- len = hextoul(argv[3], NULL);
- if (!len) {
- debug("pdi_load: zero size\n");
- return CMD_RET_USAGE;
- }
-
- pdi_buf = (ulong *)ALIGN((ulong)addr, ARCH_DMA_MINALIGN);
- if ((ulong)addr != (ulong)pdi_buf) {
- memcpy((void *)pdi_buf, (void *)addr, len);
- debug("Pdi addr:0x%lx aligned to 0x%lx\n",
- addr, (ulong)pdi_buf);
- }
-
- flush_dcache_range((ulong)pdi_buf, (ulong)pdi_buf + len);
-
- buf_lo = lower_32_bits((ulong)pdi_buf);
- buf_hi = upper_32_bits((ulong)pdi_buf);
-
- ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
- buf_hi, 0, ret_payload);
- if (ret)
- printf("PDI load failed with err: 0x%08x\n", ret);
-
- return ret;
-}
-
-static struct cmd_tbl cmd_versal_sub[] = {
- U_BOOT_CMD_MKENT(loadpdi, 4, 1, do_versal_load_pdi, "", ""),
-};
-
-/**
- * do_versal - Handle the "versal" command-line command
- * @cmdtp: Command data struct pointer
- * @flag: Command flag
- * @argc: Command-line argument count
- * @argv: Array of command-line arguments
- *
- * Processes the versal specific commands
- *
- * Return: return 0 on success, Error value if command fails.
- * CMD_RET_USAGE incase of incorrect/missing parameters.
- */
-static int do_versal(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
-{
- struct cmd_tbl *c;
- int ret = CMD_RET_USAGE;
-
- if (argc < 2)
- return CMD_RET_USAGE;
-
- c = find_cmd_tbl(argv[1], &cmd_versal_sub[0],
- ARRAY_SIZE(cmd_versal_sub));
- if (c)
- ret = c->cmd(c, flag, argc, argv);
-
- return cmd_process_error(c, ret);
-}
-
-U_BOOT_LONGHELP(versal,
- "loadpdi addr len - Load pdi image\n"
- "load pdi image at ddr address 'addr' with pdi image size 'len'\n");
-
-U_BOOT_CMD(versal, 4, 1, do_versal,
- "versal sub-system",
- versal_help_text
-);
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 8dbfa56..04dee1b 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -7,6 +7,7 @@
#include <config.h>
#include <debug_uart.h>
#include <dfu.h>
+#include <efi_loader.h>
#include <init.h>
#include <log.h>
#include <dm/uclass.h>
@@ -52,6 +53,9 @@
char *new_targets;
char *env_targets;
+ if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
+ configure_capsule_updates();
+
if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
debug("Saved variables - Skipping\n");
return 0;
@@ -165,18 +169,13 @@
}
}
-#if defined(CONFIG_SET_DFU_ALT_INFO)
-
#define DFU_ALT_BUF_LEN SZ_1K
-void set_dfu_alt_info(char *interface, char *devstr)
+void configure_capsule_updates(void)
{
ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
- if (env_get("dfu_alt_info"))
- return;
-
- memset(buf, 0, sizeof(buf));
+ memset(buf, 0, DFU_ALT_BUF_LEN);
switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
#if defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME)
@@ -199,7 +198,6 @@
return;
}
- env_set("dfu_alt_info", buf);
- puts("DFU alt info setting: done\n");
+ update_info.dfu_string = strdup(buf);
+ debug("Capsule DFU: %s\n", update_info.dfu_string);
}
-#endif
diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile
index 6476f20..5b2b6e1 100644
--- a/board/xilinx/zynqmp/Makefile
+++ b/board/xilinx/zynqmp/Makefile
@@ -31,7 +31,7 @@
endif
endif
-obj-$(CONFIG_$(XPL_)ZYNQMP_PSU_INIT_ENABLED) += $(init-objs)
+obj-$(CONFIG_$(PHASE_)ZYNQMP_PSU_INIT_ENABLED) += $(init-objs)
ifdef CONFIG_XPL_BUILD
ifneq ($(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE),"")
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 820fb25..735ef3c 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -11,6 +11,7 @@
#include <dfu.h>
#include <env.h>
#include <env_internal.h>
+#include <efi_loader.h>
#include <init.h>
#include <log.h>
#include <net.h>
@@ -526,6 +527,9 @@
usb_ether_init();
#endif
+ if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
+ configure_capsule_updates();
+
multiboot = multi_boot();
if (multiboot >= 0)
env_set_hex("multiboot", multiboot);
@@ -631,8 +635,6 @@
}
#endif
-#if defined(CONFIG_SET_DFU_ALT_INFO)
-
#define DFU_ALT_BUF_LEN SZ_1K
static void mtd_found_part(u32 *base, u32 *size)
@@ -660,16 +662,13 @@
}
}
-void set_dfu_alt_info(char *interface, char *devstr)
+void configure_capsule_updates(void)
{
int multiboot, bootseq = 0, len = 0;
ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
- if (env_get("dfu_alt_info"))
- return;
-
- memset(buf, 0, sizeof(buf));
+ memset(buf, 0, DFU_ALT_BUF_LEN);
multiboot = multi_boot();
if (multiboot < 0)
@@ -732,10 +731,9 @@
return;
}
- env_set("dfu_alt_info", buf);
- puts("DFU alt info setting: done\n");
+ update_info.dfu_string = strdup(buf);
+ debug("Capsule DFU: %s\n", update_info.dfu_string);
}
-#endif
#if defined(CONFIG_SPL_SPI_LOAD)
unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash)
diff --git a/board/xilinx/zynqmp/zynqmp_kria.env b/board/xilinx/zynqmp/zynqmp_kria.env
index 75b604a..89f48c0 100644
--- a/board/xilinx/zynqmp/zynqmp_kria.env
+++ b/board/xilinx/zynqmp/zynqmp_kria.env
@@ -42,7 +42,7 @@
script_size_f=0x80000
scriptaddr=0x20000000
usb_boot=usb start; if usb dev ${devnum}; then devtype=usb; run scan_dev_for_boot_part; fi
-preboot=setenv boot_targets; setenv modeboot; run board_setup
+preboot=setenv boot_targets; setenv modeboot; run board_setup; usb start
usb_pgood_delay=1000
# SOM specific boot methods
diff --git a/boot/Kconfig b/boot/Kconfig
index f101200..2456856 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig
@@ -1170,7 +1170,7 @@
config BOOTSTAGE_RECORD_COUNT
int "Number of boot stage records to store"
depends on BOOTSTAGE
- default 30
+ default 50
help
This is the size of the bootstage record list and is the maximum
number of bootstage records that can be recorded.
@@ -1704,6 +1704,13 @@
After the countdown timed out, the board will be reset to restart
again.
+config RETRY_BOOTCMD
+ bool "Run bootcmd on retry"
+ depends on BOOT_RETRY && HUSH_PARSER && !RESET_TO_RETRY
+ help
+ If this option is enabled, the "bootcmd" will be run after the
+ countdown times out.
+
endmenu
menu "Image support"
diff --git a/boot/Makefile b/boot/Makefile
index 34bac26..71dafae 100644
--- a/boot/Makefile
+++ b/boot/Makefile
@@ -47,7 +47,7 @@
obj-$(CONFIG_$(PHASE_)OF_LIBFDT) += image-fdt.o
obj-$(CONFIG_$(PHASE_)FIT_SIGNATURE) += fdt_region.o
obj-$(CONFIG_$(PHASE_)FIT) += image-fit.o
-obj-$(CONFIG_$(XPL_)MULTI_DTB_FIT) += boot_fit.o common_fit.o
+obj-$(CONFIG_$(PHASE_)MULTI_DTB_FIT) += boot_fit.o common_fit.o
obj-$(CONFIG_$(PHASE_)IMAGE_PRE_LOAD) += image-pre-load.o
obj-$(CONFIG_$(PHASE_)IMAGE_SIGN_INFO) += image-sig.o
obj-$(CONFIG_$(PHASE_)FIT_SIGNATURE) += image-fit-sig.o
diff --git a/boot/bootm.c b/boot/bootm.c
index 854ac7e..f5cbb10 100644
--- a/boot/bootm.c
+++ b/boot/bootm.c
@@ -545,7 +545,8 @@
images.os.type == IH_TYPE_KERNEL_NOLOAD ||
images.os.type == IH_TYPE_MULTI) &&
(images.os.os == IH_OS_LINUX || images.os.os == IH_OS_VXWORKS ||
- images.os.os == IH_OS_EFI || images.os.os == IH_OS_TEE)) {
+ images.os.os == IH_OS_EFI || images.os.os == IH_OS_TEE ||
+ images.os.os == IH_OS_ELF)) {
return bootm_find_images(img_addr, conf_ramdisk, conf_fdt, 0,
0);
}
diff --git a/boot/bootm_os.c b/boot/bootm_os.c
index e9522cd..a3c7cb5 100644
--- a/boot/bootm_os.c
+++ b/boot/bootm_os.c
@@ -402,7 +402,7 @@
if (flag != BOOTM_STATE_OS_GO)
return 0;
- bootelf(bmi->images->ep, flags, 0, NULL);
+ bootelf(bmi->images->ep, flags, bmi->argc, bmi->argv);
return 1;
}
@@ -498,16 +498,18 @@
/* We expect to return */
images->os.type = IH_TYPE_STANDALONE;
- image_buf = map_sysmem(images->ep, images->os.image_len);
+ image_buf = map_sysmem(images->os.image_start, images->os.image_len);
/* Run EFI image */
printf("## Transferring control to EFI (at address %08lx) ...\n",
- images->ep);
+ images->os.image_start);
bootstage_mark(BOOTSTAGE_ID_RUN_OS);
ret = efi_binary_run(image_buf, images->os.image_len,
images->ft_len
- ? images->ft_addr : EFI_FDT_USE_INTERNAL);
+ ? images->ft_addr : EFI_FDT_USE_INTERNAL,
+ (void *)images->initrd_start,
+ (size_t)(images->initrd_end - images->initrd_start));
return ret;
}
diff --git a/boot/bootmeth_android.c b/boot/bootmeth_android.c
index a5a86b2..654ebfd 100644
--- a/boot/bootmeth_android.c
+++ b/boot/bootmeth_android.c
@@ -455,7 +455,8 @@
if (result != AVB_SLOT_VERIFY_RESULT_OK) {
printf("Verification failed, reason: %s\n",
str_avb_slot_error(result));
- avb_slot_verify_data_free(out_data);
+ if (out_data)
+ avb_slot_verify_data_free(out_data);
return log_msg_ret("avb verify", -EIO);
}
boot_state = AVB_GREEN;
@@ -465,7 +466,8 @@
result != AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION) {
printf("Unlocked verification failed, reason: %s\n",
str_avb_slot_error(result));
- avb_slot_verify_data_free(out_data);
+ if (out_data)
+ avb_slot_verify_data_free(out_data);
return log_msg_ret("avb verify unlocked", -EIO);
}
boot_state = AVB_ORANGE;
diff --git a/boot/bootretry.c b/boot/bootretry.c
index 587b2de..a60767e 100644
--- a/boot/bootretry.c
+++ b/boot/bootretry.c
@@ -37,6 +37,8 @@
*/
void bootretry_reset_cmd_timeout(void)
{
+ /* Parse changes to bootretry */
+ bootretry_init_cmd_timeout();
endtime = endtick(retry_time);
}
diff --git a/boot/image-fit-sig.c b/boot/image-fit-sig.c
index a121de6..f23e9d5 100644
--- a/boot/image-fit-sig.c
+++ b/boot/image-fit-sig.c
@@ -191,6 +191,11 @@
int noffset;
int key_node;
+#ifdef USE_HOSTCC
+ if (!key_blob)
+ return 0;
+#endif
+
/* Work out what we need to verify */
*no_sigsp = 1;
key_node = fdt_subnode_offset(key_blob, 0, FIT_SIG_NODENAME);
@@ -477,6 +482,11 @@
bool reqd_policy_all = true;
const char *reqd_mode;
+#ifdef USE_HOSTCC
+ if (!key_blob)
+ return 0;
+#endif
+
/*
* We don't support this since libfdt considers names with the
* name root but different @ suffix to be equal
diff --git a/cmd/Kconfig b/cmd/Kconfig
index ecef664..f21d27c 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -5,7 +5,7 @@
Enable U-Boot's command-line functions. This provides a means
to enter commands into U-Boot for a wide variety of purposes. It
also allows scripts (containing commands) to be executed.
- Various commands and command categorys can be indivdually enabled.
+ Various commands and command categories can be individually enabled.
Depending on the number of commands enabled, this can add
substantially to the size of U-Boot.
@@ -185,6 +185,7 @@
config CMD_FWU_METADATA
bool "fwu metadata read"
depends on FWU_MULTI_BANK_UPDATE
+ imply HEXDUMP if FWU_MDATA_V2
help
Command to read the metadata and dump it's contents
@@ -3080,4 +3081,21 @@
help
Enable useful commands for the Meson Soc family developed by Amlogic Inc.
+config CMD_SPAWN
+ bool "spawn and wait commands"
+ depends on UTHREAD
+ help
+ spawn runs a command in the background and sets the job_id environment
+ variable. wait is used to suspend the shell execution until one or more
+ jobs are complete.
+
+config CMD_SPAWN_NUM_JOBS
+ int "Maximum number of simultaneous jobs for spawn"
+ default 16
+ help
+ Job identifiers are in the range 1..CMD_SPAWN_NUM_JOBS. In other words
+ there can be no more that CMD_SPAWN_NUM_JOBS running simultaneously.
+ When a jobs exits, its identifier is available to be re-used by the next
+ spawn command.
+
endif
diff --git a/cmd/Makefile b/cmd/Makefile
index c1275d4..80cf70b 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -239,6 +239,8 @@
obj-$(CONFIG_HUSH_SELECTABLE) += cli.o
+obj-$(CONFIG_CMD_SPAWN) += spawn.o
+
obj-$(CONFIG_ARM) += arm/
obj-$(CONFIG_RISCV) += riscv/
obj-$(CONFIG_SANDBOX) += sandbox/
@@ -255,7 +257,7 @@
obj-$(CONFIG_ARCH_OMAP2PLUS) += ti/
endif # !CONFIG_XPL_BUILD
-obj-$(CONFIG_$(XPL_)CMD_TLV_EEPROM) += tlv_eeprom.o
+obj-$(CONFIG_$(PHASE_)CMD_TLV_EEPROM) += tlv_eeprom.o
obj-$(CONFIG_CMD_BCM_EXT_UTILS) += broadcom/
diff --git a/cmd/blk_common.c b/cmd/blk_common.c
index 4c05a4e..5652970 100644
--- a/cmd/blk_common.c
+++ b/cmd/blk_common.c
@@ -107,6 +107,23 @@
printf("%ld blocks written: %s\n", n,
n == cnt ? "OK" : "ERROR");
return n == cnt ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
+ } else if (strcmp(argv[1], "erase") == 0) {
+ lbaint_t blk = hextoul(argv[2], NULL);
+ ulong cnt = hextoul(argv[3], NULL);
+ struct blk_desc *desc;
+ ulong n;
+
+ printf("\n%s erase: device %d block # "LBAFU", count %lu ... ",
+ if_name, *cur_devnump, blk, cnt);
+
+ if (blk_get_desc(uclass_id, *cur_devnump, &desc))
+ return CMD_RET_FAILURE;
+
+ n = blk_derase(desc, blk, cnt);
+
+ printf("%ld blocks erased: %s\n", n,
+ n == cnt ? "OK" : "ERROR");
+ return n == cnt ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
} else {
return CMD_RET_USAGE;
}
diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index c1454ff..cea6d35 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -38,6 +38,9 @@
if (ret != EFI_SUCCESS)
return ret;
+ (*image_objp)->auth_status = EFI_IMAGE_AUTH_PASSED;
+ (*image_objp)->entry = efi_selftest;
+
/* Transfer environment variable as load options */
return efi_env_set_load_options((efi_handle_t)*image_objp,
load_options_path,
@@ -106,8 +109,8 @@
return CMD_RET_FAILURE;
/* Execute the test */
- ret = EFI_CALL(efi_selftest(&image_obj->header, &systab));
- free(loaded_image_info->load_options);
+ ret = do_bootefi_exec(&image_obj->header,
+ loaded_image_info->load_options);
efi_free_pool(test_device_path);
efi_free_pool(test_image_path);
if (ret != EFI_SUCCESS)
@@ -211,7 +214,7 @@
}
}
- ret = efi_binary_run(image_buf, size, fdt);
+ ret = efi_binary_run(image_buf, size, fdt, NULL, 0);
if (ret != EFI_SUCCESS)
return CMD_RET_FAILURE;
diff --git a/cmd/cls.c b/cmd/cls.c
index 4bee8a1..b1e0619 100644
--- a/cmd/cls.c
+++ b/cmd/cls.c
@@ -18,4 +18,4 @@
return CMD_RET_SUCCESS;
}
-U_BOOT_CMD(cls, 1, 1, do_video_clear, "clear screen", "");
+U_BOOT_CMD(cls, 1, 0, do_video_clear, "clear screen", "");
diff --git a/cmd/eficonfig.c b/cmd/eficonfig.c
index e08b6ba..629bf1b 100644
--- a/cmd/eficonfig.c
+++ b/cmd/eficonfig.c
@@ -2283,26 +2283,11 @@
{
efi_status_t ret = EFI_SUCCESS;
static bool init;
- struct efi_handler *handler;
unsigned long columns, rows;
if (!init) {
- ret = efi_search_protocol(efi_root, &efi_guid_text_input_protocol, &handler);
- if (ret != EFI_SUCCESS)
- return ret;
-
- ret = efi_protocol_open(handler, (void **)&cin, efi_root, NULL,
- EFI_OPEN_PROTOCOL_GET_PROTOCOL);
- if (ret != EFI_SUCCESS)
- return ret;
- ret = efi_search_protocol(efi_root, &efi_guid_text_output_protocol, &handler);
- if (ret != EFI_SUCCESS)
- return ret;
-
- ret = efi_protocol_open(handler, (void **)&cout, efi_root, NULL,
- EFI_OPEN_PROTOCOL_GET_PROTOCOL);
- if (ret != EFI_SUCCESS)
- return ret;
+ cout = systab.con_out;
+ cin = systab.con_in;
cout->query_mode(cout, cout->mode->mode, &columns, &rows);
avail_row = rows - (EFICONFIG_MENU_HEADER_ROW_NUM +
diff --git a/cmd/fastboot.c b/cmd/fastboot.c
index d4cfc0c..be84a48 100644
--- a/cmd/fastboot.c
+++ b/cmd/fastboot.c
@@ -16,6 +16,7 @@
#include <linux/printk.h>
#include <linux/stringify.h>
+#if CONFIG_IS_ENABLED(NET)
static int do_fastboot_udp(int argc, char *const argv[],
uintptr_t buf_addr, size_t buf_size)
{
@@ -55,6 +56,7 @@
return CMD_RET_SUCCESS;
}
+#endif
static int do_fastboot_usb(int argc, char *const argv[],
uintptr_t buf_addr, size_t buf_size)
@@ -160,10 +162,12 @@
fastboot_init((void *)buf_addr, buf_size);
+#if CONFIG_IS_ENABLED(NET)
if (!strcmp(argv[1], "udp"))
return do_fastboot_udp(argc, argv, buf_addr, buf_size);
if (!strcmp(argv[1], "tcp"))
return do_fastboot_tcp(argc, argv, buf_addr, buf_size);
+#endif
if (!strcmp(argv[1], "usb")) {
argv++;
argc--;
diff --git a/cmd/fwu_mdata.c b/cmd/fwu_mdata.c
index 9c048d6..5b5a2e4 100644
--- a/cmd/fwu_mdata.c
+++ b/cmd/fwu_mdata.c
@@ -7,6 +7,7 @@
#include <dm.h>
#include <fwu.h>
#include <fwu_mdata.h>
+#include <hexdump.h>
#include <log.h>
#include <stdio.h>
#include <stdlib.h>
@@ -45,6 +46,30 @@
img_info->accepted == 0x1 ? "yes" : "no");
}
}
+
+ if (data->version == 2) {
+ struct fwu_mdata *mdata = data->fwu_mdata;
+ struct fwu_fw_store_desc *desc;
+ void *end;
+ u32 diff;
+
+ /*
+ * fwu_mdata defines only header that's why taking it as array
+ * which exactly point to image description location
+ */
+ desc = (struct fwu_fw_store_desc *)&mdata[1];
+
+ /* Number of entries is taken from for loop - variable i */
+ end = &desc->img_entry[i];
+ debug("mdata %p, desc %p, end %p\n", mdata, desc, end);
+
+ diff = data->metadata_size - ((void *)end - (void *)mdata);
+ if (diff) {
+ printf("Custom fields covered by CRC len: 0x%x\n", diff);
+ print_hex_dump_bytes("CUSTOM ", DUMP_PREFIX_OFFSET,
+ end, diff);
+ }
+ }
}
int do_fwu_mdata_read(struct cmd_tbl *cmdtp, int flag,
diff --git a/cmd/mvebu/bubt.c b/cmd/mvebu/bubt.c
index 5e4ffc4..6b7d9ee 100644
--- a/cmd/mvebu/bubt.c
+++ b/cmd/mvebu/bubt.c
@@ -931,7 +931,7 @@
size = le32_to_cpu(hdr->blocksize);
if (hdr->blockid == 0x78) { /* SATA id */
- struct blk_desc *blk_dev = IS_ENABLED(BLK) ? blk_get_devnum_by_uclass_id(UCLASS_SCSI, 0) : NULL;
+ struct blk_desc *blk_dev = IS_ENABLED(CONFIG_BLK) ? blk_get_devnum_by_uclass_id(UCLASS_SCSI, 0) : NULL;
unsigned long blksz = blk_dev ? blk_dev->blksz : 512;
offset *= blksz;
}
diff --git a/cmd/net.c b/cmd/net.c
index 79525f7..eaa1de5 100644
--- a/cmd/net.c
+++ b/cmd/net.c
@@ -456,8 +456,7 @@
}
#if defined(CONFIG_CMD_PING)
-static int do_ping(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
+int do_ping(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
if (argc < 2)
return CMD_RET_USAGE;
diff --git a/cmd/optee.c b/cmd/optee.c
index d0d3729..e3aae5e 100644
--- a/cmd/optee.c
+++ b/cmd/optee.c
@@ -53,7 +53,7 @@
{
int ret, value = 0;
- if (strcmp(argv[1], NULL))
+ if (argc > 1)
value = hextoul(argv[1], NULL);
ret = hello_world_ta(value);
diff --git a/cmd/pxe.c b/cmd/pxe.c
index 37b8dea..0f26b3b 100644
--- a/cmd/pxe.c
+++ b/cmd/pxe.c
@@ -13,7 +13,6 @@
#include "pxe_utils.h"
-#ifdef CONFIG_CMD_NET
const char *pxe_default_paths[] = {
#ifdef CONFIG_SYS_SOC
#ifdef CONFIG_SYS_BOARD
@@ -331,5 +330,3 @@
"get [" USE_IP6_CMD_PARAM "] - try to retrieve a pxe file using tftp\n"
"pxe boot [pxefile_addr_r] [-ipv6] - boot from the pxe file at pxefile_addr_r\n"
);
-
-#endif /* CONFIG_CMD_NET */
diff --git a/cmd/scsi.c b/cmd/scsi.c
index c286bdc..9f76134 100644
--- a/cmd/scsi.c
+++ b/cmd/scsi.c
@@ -60,7 +60,8 @@
"scsi read addr blk# cnt - read `cnt' blocks starting at block `blk#'\n"
" to memory address `addr'\n"
"scsi write addr blk# cnt - write `cnt' blocks starting at block\n"
- " `blk#' from memory address `addr'"
+ " `blk#' from memory address `addr'\n"
+ "scsi erase blk# cnt - erase `cnt' blocks starting at block `blk#'"
);
U_BOOT_CMD(
diff --git a/cmd/spawn.c b/cmd/spawn.c
new file mode 100644
index 0000000..eddbcb7
--- /dev/null
+++ b/cmd/spawn.c
@@ -0,0 +1,187 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+#include <command.h>
+#include <console.h>
+#include <malloc.h>
+#include <vsprintf.h>
+#include <uthread.h>
+
+/* Spawn arguments and job index */
+struct spa {
+ int argc;
+ char **argv;
+ unsigned int job_idx;
+};
+
+/*
+ * uthread group identifiers for each running job
+ * 0: job slot available, != 0: uthread group id
+ * Note that job[0] is job_id 1, job[1] is job_id 2 etc.
+ */
+static unsigned int job[CONFIG_CMD_SPAWN_NUM_JOBS];
+/* Return values of the commands run as jobs */
+static enum command_ret_t job_ret[CONFIG_CMD_SPAWN_NUM_JOBS];
+
+static void spa_free(struct spa *spa)
+{
+ int i;
+
+ if (!spa)
+ return;
+
+ for (i = 0; i < spa->argc; i++)
+ free(spa->argv[i]);
+ free(spa->argv);
+ free(spa);
+}
+
+static struct spa *spa_create(int argc, char *const argv[])
+{
+ struct spa *spa;
+ int i;
+
+ spa = calloc(1, sizeof(*spa));
+ if (!spa)
+ return NULL;
+ spa->argc = argc;
+ spa->argv = malloc(argc * sizeof(char *));
+ if (!spa->argv)
+ goto err;
+ for (i = 0; i < argc; i++) {
+ spa->argv[i] = strdup(argv[i]);
+ if (!spa->argv[i])
+ goto err;
+ }
+ return spa;
+err:
+ spa_free(spa);
+ return NULL;
+}
+
+static void spawn_thread(void *arg)
+{
+ struct spa *spa = (struct spa *)arg;
+ ulong cycles = 0;
+ int repeatable = 0;
+
+ job_ret[spa->job_idx] = cmd_process(0, spa->argc, spa->argv,
+ &repeatable, &cycles);
+ spa_free(spa);
+}
+
+static unsigned int next_job_id(void)
+{
+ int i;
+
+ for (i = 0; i < CONFIG_CMD_SPAWN_NUM_JOBS; i++)
+ if (!job[i])
+ return i + 1;
+
+ /* No job available */
+ return 0;
+}
+
+static void refresh_jobs(void)
+{
+ int i;
+
+ for (i = 0; i < CONFIG_CMD_SPAWN_NUM_JOBS; i++)
+ if (job[i] && uthread_grp_done(job[i]))
+ job[i] = 0;
+
+}
+
+static int do_spawn(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ unsigned int id;
+ unsigned int idx;
+ struct spa *spa;
+ int ret;
+
+ if (argc == 1)
+ return CMD_RET_USAGE;
+
+ spa = spa_create(argc - 1, argv + 1);
+ if (!spa)
+ return CMD_RET_FAILURE;
+
+ refresh_jobs();
+
+ id = next_job_id();
+ if (!id)
+ return CMD_RET_FAILURE;
+ idx = id - 1;
+
+ job[idx] = uthread_grp_new_id();
+
+ ret = uthread_create(NULL, spawn_thread, spa, 0, job[idx]);
+ if (ret) {
+ job[idx] = 0;
+ return CMD_RET_FAILURE;
+ }
+
+ ret = env_set_ulong("job_id", id);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(spawn, CONFIG_SYS_MAXARGS, 0, do_spawn,
+ "run commands and summarize execution time",
+ "command [args...]\n");
+
+static enum command_ret_t wait_job(unsigned int idx)
+{
+ int prev = disable_ctrlc(false);
+
+ while (!uthread_grp_done(job[idx])) {
+ if (ctrlc()) {
+ puts("<INTERRUPT>\n");
+ disable_ctrlc(prev);
+ return CMD_RET_FAILURE;
+ }
+ uthread_schedule();
+ }
+
+ job[idx] = 0;
+ disable_ctrlc(prev);
+
+ return job_ret[idx];
+}
+
+static int do_wait(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ enum command_ret_t ret = CMD_RET_SUCCESS;
+ unsigned long id;
+ unsigned int idx;
+ int i;
+
+ if (argc == 1) {
+ for (i = 0; i < CONFIG_CMD_SPAWN_NUM_JOBS; i++)
+ if (job[i])
+ ret = wait_job(i);
+ } else {
+ for (i = 1; i < argc; i++) {
+ id = dectoul(argv[i], NULL);
+ if (id < 0 || id > CONFIG_CMD_SPAWN_NUM_JOBS)
+ return CMD_RET_USAGE;
+ idx = (int)id - 1;
+ ret = wait_job(idx);
+ }
+ }
+
+ return ret;
+}
+
+U_BOOT_CMD(wait, CONFIG_SYS_MAXARGS, 0, do_wait,
+ "wait for one or more jobs to complete",
+ "[job_id ...]\n"
+ " - Wait until all specified jobs have exited and return the\n"
+ " exit status of the last job waited for. When no job_id is\n"
+ " given, wait for all the background jobs.\n");
diff --git a/common/board_f.c b/common/board_f.c
index c456187..bff465d 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -38,6 +38,7 @@
#include <spl.h>
#include <status_led.h>
#include <sysreset.h>
+#include <time.h>
#include <timer.h>
#include <trace.h>
#include <upl.h>
@@ -476,6 +477,13 @@
static int reserve_uboot(void)
{
+ /*
+ * This should be the first place GD_FLG_SKIP_RELOC is read from.
+ * Set GD_FLG_SKIP_RELOC flag if CONFIG_SKIP_RELOCATE is enabled.
+ */
+ if (CONFIG_IS_ENABLED(SKIP_RELOCATE))
+ gd->flags |= GD_FLG_SKIP_RELOC;
+
if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
/*
* reserve memory for U-Boot code, data & bss
@@ -753,7 +761,7 @@
return 0;
}
-#ifdef CONFIG_OF_BOARD_FIXUP
+#if CONFIG_IS_ENABLED(OF_BOARD_FIXUP)
static int fix_fdt(void)
{
return board_fix_fdt((void *)gd->fdt_blob);
@@ -881,81 +889,86 @@
return 0;
}
-static const init_fnc_t init_sequence_f[] = {
- setup_mon_len,
-#ifdef CONFIG_OF_CONTROL
- fdtdec_setup,
+static void initcall_run_f(void)
+{
+ /*
+ * Please do not add logic to this function (variables, if (), etc.).
+ * For simplicity it should remain an ordered list of function calls.
+ */
+ INITCALL(setup_mon_len);
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ INITCALL(fdtdec_setup);
#endif
-#ifdef CONFIG_TRACE_EARLY
- trace_early_init,
+#if CONFIG_IS_ENABLED(TRACE_EARLY)
+ INITCALL(trace_early_init);
#endif
- initf_malloc,
- initf_upl,
- log_init,
- initf_bootstage, /* uses its own timer, so does not need DM */
- event_init,
- bloblist_maybe_init,
- setup_spl_handoff,
-#if defined(CONFIG_CONSOLE_RECORD_INIT_F)
- console_record_init,
+ INITCALL(initf_malloc);
+ INITCALL(initf_upl);
+ INITCALL(log_init);
+ INITCALL(initf_bootstage); /* uses its own timer, so does not need DM */
+ INITCALL(event_init);
+ INITCALL(bloblist_maybe_init);
+ INITCALL(setup_spl_handoff);
+#if CONFIG_IS_ENABLED(CONSOLE_RECORD_INIT_F)
+ INITCALL(console_record_init);
#endif
- INITCALL_EVENT(EVT_FSP_INIT_F),
- arch_cpu_init, /* basic arch cpu dependent setup */
- mach_cpu_init, /* SoC/machine dependent CPU setup */
- initf_dm,
-#if defined(CONFIG_BOARD_EARLY_INIT_F)
- board_early_init_f,
+ INITCALL_EVT(EVT_FSP_INIT_F);
+ INITCALL(arch_cpu_init); /* basic arch cpu dependent setup */
+ INITCALL(mach_cpu_init); /* SoC/machine dependent CPU setup */
+ INITCALL(initf_dm);
+#if CONFIG_IS_ENABLED(BOARD_EARLY_INIT_F)
+ INITCALL(board_early_init_f);
#endif
#if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K)
/* get CPU and bus clocks according to the environment variable */
- get_clocks, /* get CPU and bus clocks (etc.) */
+ INITCALL(get_clocks); /* get CPU and bus clocks (etc.) */
#endif
#if !defined(CONFIG_M68K) || (defined(CONFIG_M68K) && !defined(CONFIG_MCFTMR))
- timer_init, /* initialize timer */
+ INITCALL(timer_init); /* initialize timer */
#endif
-#if defined(CONFIG_BOARD_POSTCLK_INIT)
- board_postclk_init,
+#if CONFIG_IS_ENABLED(BOARD_POSTCLK_INIT)
+ INITCALL(board_postclk_init);
#endif
- env_init, /* initialize environment */
- init_baud_rate, /* initialze baudrate settings */
- serial_init, /* serial communications setup */
- console_init_f, /* stage 1 init of console */
- display_options, /* say that we are here */
- display_text_info, /* show debugging info if required */
- checkcpu,
-#if defined(CONFIG_SYSRESET)
- print_resetinfo,
+ INITCALL(env_init); /* initialize environment */
+ INITCALL(init_baud_rate); /* initialze baudrate settings */
+ INITCALL(serial_init); /* serial communications setup */
+ INITCALL(console_init_f); /* stage 1 init of console */
+ INITCALL(display_options); /* say that we are here */
+ INITCALL(display_text_info); /* show debugging info if required */
+ INITCALL(checkcpu);
+#if CONFIG_IS_ENABLED(SYSRESET)
+ INITCALL(print_resetinfo);
#endif
-#if defined(CONFIG_DISPLAY_CPUINFO)
- print_cpuinfo, /* display cpu info (and speed) */
+ /* display cpu info (and speed) */
+#if CONFIG_IS_ENABLED(DISPLAY_CPUINFO)
+ INITCALL(print_cpuinfo);
#endif
-#if defined(CONFIG_DTB_RESELECT)
- embedded_dtb_select,
+#if CONFIG_IS_ENABLED(DTB_RESELECT)
+ INITCALL(embedded_dtb_select);
#endif
-#if defined(CONFIG_DISPLAY_BOARDINFO)
- show_board_info,
+#if CONFIG_IS_ENABLED(DISPLAY_BOARDINFO)
+ INITCALL(show_board_info);
#endif
- INIT_FUNC_WATCHDOG_INIT
- INITCALL_EVENT(EVT_MISC_INIT_F),
- INIT_FUNC_WATCHDOG_RESET
+ WATCHDOG_INIT();
+ INITCALL_EVT(EVT_MISC_INIT_F);
+ WATCHDOG_RESET();
#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
- init_func_i2c,
+ INITCALL(init_func_i2c);
#endif
- announce_dram_init,
- dram_init, /* configure available RAM banks */
-#ifdef CONFIG_POST
- post_init_f,
+ INITCALL(announce_dram_init);
+ INITCALL(dram_init); /* configure available RAM banks */
+#if CONFIG_IS_ENABLED(POST)
+ INITCALL(post_init_f);
#endif
- INIT_FUNC_WATCHDOG_RESET
+ WATCHDOG_RESET();
#if defined(CFG_SYS_DRAM_TEST)
- testdram,
+ INITCALL(testdram);
#endif /* CFG_SYS_DRAM_TEST */
- INIT_FUNC_WATCHDOG_RESET
-
-#ifdef CONFIG_POST
- init_post,
+ WATCHDOG_RESET();
+#if CONFIG_IS_ENABLED(POST)
+ INITCALL(init_post);
#endif
- INIT_FUNC_WATCHDOG_RESET
+ WATCHDOG_RESET();
/*
* Now that we have DRAM mapped and working, we can
* relocate the code and continue running from DRAM.
@@ -968,48 +981,51 @@
* - monitor code
* - board info struct
*/
- setup_dest_addr,
-#if defined(CONFIG_OF_BOARD_FIXUP) && !defined(CONFIG_OF_INITIAL_DTB_READONLY)
- fix_fdt,
+ INITCALL(setup_dest_addr);
+#if CONFIG_IS_ENABLED(OF_BOARD_FIXUP) && \
+ !CONFIG_IS_ENABLED(OF_INITIAL_DTB_READONLY)
+ INITCALL(fix_fdt);
#endif
#ifdef CFG_PRAM
- reserve_pram,
+ INITCALL(reserve_pram);
#endif
- reserve_round_4k,
- setup_relocaddr_from_bloblist,
- arch_reserve_mmu,
- reserve_video,
- reserve_trace,
- reserve_uboot,
- reserve_malloc,
- reserve_board,
- reserve_global_data,
- reserve_fdt,
-#if defined(CONFIG_OF_BOARD_FIXUP) && defined(CONFIG_OF_INITIAL_DTB_READONLY)
- reloc_fdt,
- fix_fdt,
+ INITCALL(reserve_round_4k);
+ INITCALL(setup_relocaddr_from_bloblist);
+ INITCALL(arch_reserve_mmu);
+ INITCALL(reserve_video);
+ INITCALL(reserve_trace);
+ INITCALL(reserve_uboot);
+ INITCALL(reserve_malloc);
+ INITCALL(reserve_board);
+ INITCALL(reserve_global_data);
+ INITCALL(reserve_fdt);
+#if CONFIG_IS_ENABLED(OF_BOARD_FIXUP) && \
+ CONFIG_IS_ENABLED(OF_INITIAL_DTB_READONLY)
+ INITCALL(reloc_fdt);
+ INITCALL(fix_fdt);
#endif
- reserve_bootstage,
- reserve_bloblist,
- reserve_arch,
- reserve_stacks,
- dram_init_banksize,
- show_dram_config,
- INIT_FUNC_WATCHDOG_RESET
- setup_bdinfo,
- display_new_sp,
- INIT_FUNC_WATCHDOG_RESET
-#if !defined(CONFIG_OF_BOARD_FIXUP) || !defined(CONFIG_OF_INITIAL_DTB_READONLY)
- reloc_fdt,
+ INITCALL(reserve_bootstage);
+ INITCALL(reserve_bloblist);
+ INITCALL(reserve_arch);
+ INITCALL(reserve_stacks);
+ INITCALL(dram_init_banksize);
+ INITCALL(show_dram_config);
+ WATCHDOG_RESET();
+ INITCALL(setup_bdinfo);
+ INITCALL(display_new_sp);
+ WATCHDOG_RESET();
+#if !CONFIG_IS_ENABLED(OF_BOARD_FIXUP) || \
+ !CONFIG_IS_ENABLED(INITIAL_DTB_READONLY)
+ INITCALL(reloc_fdt);
#endif
- reloc_bootstage,
- reloc_bloblist,
- setup_reloc,
-#if defined(CONFIG_X86) || defined(CONFIG_ARC)
- copy_uboot_to_ram,
- do_elf_reloc_fixups,
+ INITCALL(reloc_bootstage);
+ INITCALL(reloc_bloblist);
+ INITCALL(setup_reloc);
+#if CONFIG_IS_ENABLED(X86) || CONFIG_IS_ENABLED(ARC)
+ INITCALL(copy_uboot_to_ram);
+ INITCALL(do_elf_reloc_fixups);
#endif
- clear_bss,
+ INITCALL(clear_bss);
/*
* Deregister all cyclic functions before relocation, so that
* gd->cyclic_list does not contain any references to pre-relocation
@@ -1019,12 +1035,11 @@
* This should happen as late as possible so that the window where a
* watchdog device is not serviced is as small as possible.
*/
- cyclic_unregister_all,
-#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX)
- jump_to_copy,
+ INITCALL(cyclic_unregister_all);
+#if !CONFIG_IS_ENABLED(ARM) && !CONFIG_IS_ENABLED(SANDBOX)
+ INITCALL(jump_to_copy);
#endif
- NULL,
-};
+}
void board_init_f(ulong boot_flags)
{
@@ -1034,8 +1049,7 @@
gd->flags &= ~GD_FLG_HAVE_CONSOLE;
gd->boardf = &boardf;
- if (initcall_run_list(init_sequence_f))
- hang();
+ initcall_run_f();
#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
!defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \
@@ -1049,8 +1063,8 @@
/*
* For now this code is only used on x86.
*
- * init_sequence_f_r is the list of init functions which are run when
- * U-Boot is executing from Flash with a semi-limited 'C' environment.
+ * Run init functions which are run when U-Boot is executing from Flash with a
+ * semi-limited 'C' environment.
* The following limitations must be considered when implementing an
* '_f_r' function:
* - 'static' variables are read-only
@@ -1063,18 +1077,16 @@
* NOTE: At present only x86 uses this route, but it is intended that
* all archs will move to this when generic relocation is implemented.
*/
-static const init_fnc_t init_sequence_f_r[] = {
-#if !CONFIG_IS_ENABLED(X86_64)
- init_cache_f_r,
+static void initcall_run_f_r(void)
+{
+#if CONFIG_IS_ENABLED(X86_64)
+ INITCALL(init_cache_f_r);
#endif
-
- NULL,
-};
+}
void board_init_f_r(void)
{
- if (initcall_run_list(init_sequence_f_r))
- hang();
+ initcall_run_f_r();
/*
* The pre-relocation drivers may be using memory that has now gone
diff --git a/common/board_r.c b/common/board_r.c
index 8d69db1..b90a4d9 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -169,7 +169,8 @@
*/
efi_save_gd();
- efi_runtime_relocate(gd->relocaddr, NULL);
+ if (!(gd->flags & GD_FLG_SKIP_RELOC))
+ efi_runtime_relocate(gd->relocaddr, NULL);
#endif
/*
@@ -508,7 +509,7 @@
return 0;
}
-#if defined(CONFIG_CMD_NET)
+#if CONFIG_IS_ENABLED(NET) || CONFIG_IS_ENABLED(NET_LWIP)
static int initr_net(void)
{
puts("Net: ");
@@ -602,21 +603,24 @@
}
/*
- * Over time we hope to remove these functions with code fragments and
- * stub functions, and instead call the relevant function directly.
- *
- * We also hope to remove most of the driver-related init and do it if/when
- * the driver is later used.
+ * Over time we hope to remove most of the driver-related init and do it
+ * if/when the driver is later used.
*
* TODO: perhaps reset the watchdog in the initcall function after each call?
*/
-static init_fnc_t init_sequence_r[] = {
- initr_trace,
- initr_reloc,
- event_init,
+
+static void initcall_run_r(void)
+{
+ /*
+ * Please do not add logic to this function (variables, if (), etc.).
+ * For simplicity it should remain an ordered list of function calls.
+ */
+ INITCALL(initr_trace);
+ INITCALL(initr_reloc);
+ INITCALL(event_init);
/* TODO: could x86/PPC have this also perhaps? */
-#if defined(CONFIG_ARM) || defined(CONFIG_RISCV)
- initr_caches,
+#if CONFIG_IS_ENABLED(ARM) || CONFIG_IS_ENABLED(RISCV)
+ INITCALL(initr_caches);
/* Note: For Freescale LS2 SoCs, new MMU table is created in DDR.
* A temporary mapping of IFC high region is since removed,
* so environmental variables in NOR flash is not available
@@ -624,29 +628,30 @@
* region.
*/
#endif
- initr_reloc_global_data,
-#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
- initr_unlock_ram_in_cache,
+ INITCALL(initr_reloc_global_data);
+#if CONFIG_IS_ENABLED(SYS_INIT_RAM_LOCK) && CONFIG_IS_ENABLED(E500)
+ INITCALL(initr_unlock_ram_in_cache);
#endif
- initr_barrier,
- initr_malloc,
- log_init,
- initr_bootstage, /* Needs malloc() but has its own timer */
-#if defined(CONFIG_CONSOLE_RECORD)
- console_record_init,
+ INITCALL(initr_barrier);
+ INITCALL(initr_malloc);
+ INITCALL(log_init);
+ INITCALL(initr_bootstage); /* Needs malloc() but has its own timer */
+#if CONFIG_IS_ENABLED(CONSOLE_RECORD)
+ INITCALL(console_record_init);
#endif
-#ifdef CONFIG_SYS_NONCACHED_MEMORY
- noncached_init,
+#if CONFIG_IS_ENABLED(SYS_HAS_NONCACHED_MEMORY)
+ INITCALL(noncached_init);
#endif
- initr_of_live,
-#ifdef CONFIG_DM
- initr_dm,
+ INITCALL(initr_of_live);
+#if CONFIG_IS_ENABLED(DM)
+ INITCALL(initr_dm);
#endif
-#ifdef CONFIG_ADDR_MAP
- init_addr_map,
+#if CONFIG_IS_ENABLED(ADDR_MAP)
+ INITCALL(init_addr_map);
#endif
-#if defined(CONFIG_ARM) || defined(CONFIG_RISCV) || defined(CONFIG_SANDBOX)
- board_init, /* Setup chipselects */
+#if CONFIG_IS_ENABLED(ARM) || CONFIG_IS_ENABLED(RISCV) || \
+ CONFIG_IS_ENABLED(SANDBOX)
+ INITCALL(board_init); /* Setup chipselects */
#endif
/*
* TODO: printing of the clock inforamtion of the board is now
@@ -654,139 +659,141 @@
* davinci SOC's is added. Remove this check once all the board
* implement this.
*/
-#ifdef CONFIG_CLOCKS
- set_cpu_clk_info, /* Setup clock information */
+#if CONFIG_IS_ENABLED(CLOCKS)
+ INITCALL(set_cpu_clk_info);
#endif
- initr_lmb,
-#ifdef CONFIG_EFI_LOADER
- efi_memory_init,
+ INITCALL(initr_lmb);
+#if CONFIG_IS_ENABLED(EFI_LOADER)
+ INITCALL(efi_memory_init);
#endif
-#ifdef CONFIG_BINMAN_FDT
- initr_binman,
+#if CONFIG_IS_ENABLED(BINMAN_FDT)
+ INITCALL(initr_binman);
#endif
-#ifdef CONFIG_FSP_VERSION2
- arch_fsp_init_r,
+#if CONFIG_IS_ENABLED(FSP_VERSION2)
+ INITCALL(arch_fsp_init_r);
#endif
- initr_dm_devices,
- stdio_init_tables,
- serial_initialize,
- initr_announce,
- dm_announce,
+ INITCALL(initr_dm_devices);
+ INITCALL(stdio_init_tables);
+ INITCALL(serial_initialize);
+ INITCALL(initr_announce);
+ INITCALL(dm_announce);
#if CONFIG_IS_ENABLED(WDT)
- initr_watchdog,
+ INITCALL(initr_watchdog);
#endif
- INIT_FUNC_WATCHDOG_RESET
- arch_initr_trap,
-#if defined(CONFIG_BOARD_EARLY_INIT_R)
- board_early_init_r,
+ WATCHDOG_RESET();
+ INITCALL(arch_initr_trap);
+#if CONFIG_IS_ENABLED(BOARD_EARLY_INIT_R)
+ INITCALL(board_early_init_r);
#endif
- INIT_FUNC_WATCHDOG_RESET
-#ifdef CONFIG_POST
- post_output_backlog,
+ WATCHDOG_RESET();
+#if CONFIG_IS_ENABLED(POST)
+ INITCALL(post_output_backlog);
#endif
- INIT_FUNC_WATCHDOG_RESET
-#if defined(CONFIG_PCI_INIT_R) && defined(CONFIG_SYS_EARLY_PCI_INIT)
+ WATCHDOG_RESET();
+#if CONFIG_IS_ENABLED(PCI_INIT_R) && CONFIG_IS_ENABLED(SYS_EARLY_PCI_INIT)
/*
* Do early PCI configuration _before_ the flash gets initialised,
* because PCU resources are crucial for flash access on some boards.
*/
- pci_init,
+ INITCALL(pci_init);
#endif
-#ifdef CONFIG_ARCH_EARLY_INIT_R
- arch_early_init_r,
+#if CONFIG_IS_ENABLED(ARCH_EARLY_INIT_R)
+ INITCALL(arch_early_init_r);
#endif
- power_init_board,
-#ifdef CONFIG_MTD_NOR_FLASH
- initr_flash,
+ INITCALL(power_init_board);
+#if CONFIG_IS_ENABLED(MTD_NOR_FLASH)
+ INITCALL(initr_flash);
#endif
- INIT_FUNC_WATCHDOG_RESET
-#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_X86)
+ WATCHDOG_RESET();
+#if CONFIG_IS_ENABLED(PPC) || CONFIG_IS_ENABLED(M68K) || CONFIG_IS_ENABLED(X86)
/* initialize higher level parts of CPU like time base and timers */
- cpu_init_r,
+ INITCALL(cpu_init_r);
#endif
-#ifdef CONFIG_EFI_LOADER
- efi_init_early,
+#if CONFIG_IS_ENABLED(EFI_LOADER)
+ INITCALL(efi_init_early);
#endif
-#ifdef CONFIG_CMD_NAND
- initr_nand,
+#if CONFIG_IS_ENABLED(CMD_NAND)
+ INITCALL(initr_nand);
#endif
-#ifdef CONFIG_CMD_ONENAND
- initr_onenand,
+#if CONFIG_IS_ENABLED(CMD_ONENAND)
+ INITCALL(initr_onenand);
#endif
-#ifdef CONFIG_MMC
- initr_mmc,
+#if CONFIG_IS_ENABLED(MMC)
+ INITCALL(initr_mmc);
#endif
-#ifdef CONFIG_XEN
- xen_init,
+#if CONFIG_IS_ENABLED(XEN)
+ INITCALL(xen_init);
#endif
-#ifdef CONFIG_PVBLOCK
- initr_pvblock,
+#if CONFIG_IS_ENABLED(PVBLOCK)
+ INITCALL(initr_pvblock);
#endif
- initr_env,
-#ifdef CONFIG_SYS_MALLOC_BOOTPARAMS
- initr_malloc_bootparams,
+ INITCALL(initr_env);
+#if CONFIG_IS_ENABLED(SYS_MALLOC_BOOTPARAMS)
+ INITCALL(initr_malloc_bootparams);
#endif
- INIT_FUNC_WATCHDOG_RESET
- cpu_secondary_init_r,
-#if defined(CONFIG_ID_EEPROM)
- mac_read_from_eeprom,
+ WATCHDOG_RESET();
+ INITCALL(cpu_secondary_init_r);
+#if CONFIG_IS_ENABLED(ID_EEPROM)
+ INITCALL(mac_read_from_eeprom);
#endif
- INITCALL_EVENT(EVT_SETTINGS_R),
- INIT_FUNC_WATCHDOG_RESET
-#if defined(CONFIG_PCI_INIT_R) && !defined(CONFIG_SYS_EARLY_PCI_INIT)
+ INITCALL_EVT(EVT_SETTINGS_R);
+ WATCHDOG_RESET();
+#if CONFIG_IS_ENABLED(PCI_INIT_R) && !CONFIG_IS_ENABLED(SYS_EARLY_PCI_INIT)
/*
* Do pci configuration
*/
- pci_init,
+ INITCALL(pci_init);
#endif
- stdio_add_devices,
- jumptable_init,
-#ifdef CONFIG_API
- api_init,
+ INITCALL(stdio_add_devices);
+ INITCALL(jumptable_init);
+#if CONFIG_IS_ENABLED(API)
+ INITCALL(api_init);
#endif
- console_init_r, /* fully init console as a device */
-#ifdef CONFIG_DISPLAY_BOARDINFO_LATE
- console_announce_r,
- show_board_info,
+ INITCALL(console_init_r); /* fully init console as a device */
+#if CONFIG_IS_ENABLED(DISPLAY_BOARDINFO_LATE)
+ INITCALL(console_announce_r);
+ INITCALL(show_board_info);
#endif
-#ifdef CONFIG_ARCH_MISC_INIT
- arch_misc_init, /* miscellaneous arch-dependent init */
+ /* miscellaneous arch-dependent init */
+#if CONFIG_IS_ENABLED(ARCH_MISC_INIT)
+ INITCALL(arch_misc_init);
#endif
-#ifdef CONFIG_MISC_INIT_R
- misc_init_r, /* miscellaneous platform-dependent init */
+ /* miscellaneous platform-dependent init */
+#if CONFIG_IS_ENABLED(MISC_INIT_R)
+ INITCALL(misc_init_r);
#endif
- INIT_FUNC_WATCHDOG_RESET
-#ifdef CONFIG_CMD_KGDB
- kgdb_init,
+ WATCHDOG_RESET();
+#if CONFIG_IS_ENABLED(CMD_KGDB)
+ INITCALL(kgdb_init);
#endif
- interrupt_init,
+ INITCALL(interrupt_init);
#if defined(CONFIG_MICROBLAZE) || defined(CONFIG_M68K)
- timer_init, /* initialize timer */
+ INITCALL(timer_init); /* initialize timer */
#endif
- initr_status_led,
- initr_boot_led_blink,
+ INITCALL(initr_status_led);
+ INITCALL(initr_boot_led_blink);
/* PPC has a udelay(20) here dating from 2002. Why? */
-#ifdef CONFIG_BOARD_LATE_INIT
- board_late_init,
+#if CONFIG_IS_ENABLED(BOARD_LATE_INIT)
+ INITCALL(board_late_init);
#endif
-#ifdef CONFIG_PCI_ENDPOINT
- pci_ep_init,
+#if CONFIG_IS_ENABLED(PCI_ENDPOINT)
+ INITCALL(pci_ep_init);
#endif
-#if defined(CONFIG_CMD_NET)
- INIT_FUNC_WATCHDOG_RESET
- initr_net,
+#if CONFIG_IS_ENABLED(NET) || CONFIG_IS_ENABLED(NET_LWIP)
+ WATCHDOG_RESET();
+ INITCALL(initr_net);
#endif
-#ifdef CONFIG_POST
- initr_post,
+#if CONFIG_IS_ENABLED(POST)
+ INITCALL(initr_post);
#endif
- INIT_FUNC_WATCHDOG_RESET
- INITCALL_EVENT(EVT_LAST_STAGE_INIT),
+ WATCHDOG_RESET();
+ INITCALL_EVT(EVT_LAST_STAGE_INIT);
#if defined(CFG_PRAM)
- initr_mem,
+ INITCALL(initr_mem);
#endif
- initr_boot_led_on,
- run_main_loop,
-};
+ INITCALL(initr_boot_led_on);
+ INITCALL(run_main_loop);
+}
void board_init_r(gd_t *new_gd, ulong dest_addr)
{
@@ -813,8 +820,7 @@
#endif
gd->flags &= ~GD_FLG_LOG_READY;
- if (initcall_run_list(init_sequence_r))
- hang();
+ initcall_run_r();
/* NOTREACHED - run_main_loop() does not return */
hang();
diff --git a/common/cli_hush.c b/common/cli_hush.c
index 9f437ae..7bd6943 100644
--- a/common/cli_hush.c
+++ b/common/cli_hush.c
@@ -1028,8 +1028,10 @@
puts("\nTimeout waiting for command\n");
# ifdef CONFIG_RESET_TO_RETRY
do_reset(NULL, 0, 0, NULL);
-# else
-# error "This currently only works with CONFIG_RESET_TO_RETRY enabled"
+# elif IS_ENABLED(CONFIG_RETRY_BOOTCMD)
+ strcpy(console_buffer, "run bootcmd\n");
+# else
+# error "This only works with CONFIG_RESET_TO_RETRY or CONFIG_BOOT_RETRY_COMMAND enabled"
# endif
}
#endif
diff --git a/common/cli_hush_upstream.c b/common/cli_hush_upstream.c
index ab5aa5f..748ef60 100644
--- a/common/cli_hush_upstream.c
+++ b/common/cli_hush_upstream.c
@@ -2907,8 +2907,10 @@
puts("\nTimeout waiting for command\n");
# ifdef CONFIG_RESET_TO_RETRY
do_reset(NULL, 0, 0, NULL);
-# else
-# error "This currently only works with CONFIG_RESET_TO_RETRY enabled"
+# elif IS_ENABLED(CONFIG_RETRY_BOOTCMD)
+ strcpy(console_buffer, "run bootcmd\n");
+# else
+# error "This only works with CONFIG_RESET_TO_RETRY or CONFIG_BOOT_RETRY_COMMAND enabled"
# endif
}
# endif
diff --git a/common/console.c b/common/console.c
index b69bb18..275da2f 100644
--- a/common/console.c
+++ b/common/console.c
@@ -208,8 +208,8 @@
gd->jt->printf = printf;
break;
}
- break;
#endif
+ break;
default: /* Invalid file ID */
error = -1;
}
diff --git a/common/cyclic.c b/common/cyclic.c
index fad071a..b695f09 100644
--- a/common/cyclic.c
+++ b/common/cyclic.c
@@ -16,6 +16,7 @@
#include <linux/list.h>
#include <asm/global_data.h>
#include <u-boot/schedule.h>
+#include <uthread.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -100,6 +101,8 @@
*/
if (gd)
cyclic_run();
+
+ uthread_schedule();
}
int cyclic_unregister_all(void)
diff --git a/common/iomux.c b/common/iomux.c
index 1224c15..4844df5 100644
--- a/common/iomux.c
+++ b/common/iomux.c
@@ -131,7 +131,7 @@
/* Stop dropped consoles */
for (i = 0; i < repeat; i++) {
j = iomux_match_device(cons_set, cs_idx, old_set[i]);
- if (j == cs_idx)
+ if (j == -ENOENT)
console_stop(console, old_set[i]);
}
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index c08045f..b076f49 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -270,6 +270,8 @@
default 0x40200000 if OMAP34XX
default 0x402F4000 if AM43XX
default 0x402F0400 if AM33XX
+ default 0x80080000 if ARCH_K3 && ARM64
+ default 0x43c00000 if ARCH_K3 && !ARM64
default 0x00908000 if ARCH_MX6
default 0x00912000 if ARCH_MX7
default 0x40301350 if OMAP54XX
@@ -537,6 +539,7 @@
choice
prompt "Method for locating next phase of boot (e.g. U-Boot)"
+ default SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR if MVEBU_SPL_BOOT_DEVICE_MMC
config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
bool "MMC raw mode: by sector"
diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig
index 5a10fce..20fa977 100644
--- a/configs/A10s-OLinuXino-M_defconfig
+++ b/configs/A10s-OLinuXino-M_defconfig
@@ -5,7 +5,6 @@
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC_SUNXI_SLOT_EXTRA=1
-CONFIG_USB1_VBUS_PIN="PB10"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig
index 5001ce9..4bb34d0 100644
--- a/configs/A13-OLinuXinoM_defconfig
+++ b/configs/A13-OLinuXinoM_defconfig
@@ -5,7 +5,6 @@
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=0
-CONFIG_USB1_VBUS_PIN="PG11"
# CONFIG_VIDEO_HDMI is not set
CONFIG_VIDEO_VGA_VIA_LCD=y
CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y
diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig
index bc0fc0e..5183ece 100644
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=0
-CONFIG_USB0_VBUS_DET="PG1"
-CONFIG_USB1_VBUS_PIN="PG11"
CONFIG_AXP_GPIO=y
# CONFIG_VIDEO_HDMI is not set
CONFIG_VIDEO_VGA_VIA_LCD=y
diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
index 22d80ca..73b2845 100644
--- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
+++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="PC17"
-CONFIG_USB0_VBUS_DET="PH5"
CONFIG_I2C1_ENABLE=y
CONFIG_SPL_SPI_SUNXI=y
CONFIG_AHCI=y
diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig
index e10660c..f885fc0 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
-CONFIG_USB0_VBUS_PIN="PC17"
-CONFIG_USB0_VBUS_DET="PH5"
CONFIG_I2C1_ENABLE=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
index ac90047..34c1f5f 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
-CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB0_VBUS_DET="PH5"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
index 00a9814..5f44d3d 100644
--- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
+++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="PC17"
-CONFIG_USB0_VBUS_DET="PH5"
CONFIG_I2C1_ENABLE=y
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
diff --git a/configs/A20-Olimex-SOM204-EVB_defconfig b/configs/A20-Olimex-SOM204-EVB_defconfig
index f4ae3ae..271d911 100644
--- a/configs/A20-Olimex-SOM204-EVB_defconfig
+++ b/configs/A20-Olimex-SOM204-EVB_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
-CONFIG_USB0_VBUS_PIN="PC17"
-CONFIG_USB0_VBUS_DET="PH5"
CONFIG_I2C1_ENABLE=y
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
diff --git a/configs/A33-OLinuXino_defconfig b/configs/A33-OLinuXino_defconfig
index df4acaf..e90cdda 100644
--- a/configs/A33-OLinuXino_defconfig
+++ b/configs/A33-OLinuXino_defconfig
@@ -6,14 +6,13 @@
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=15291
CONFIG_DRAM_ODT_EN=y
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PB3"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
CONFIG_VIDEO_LCD_BL_EN="PB2"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DCDC1_VOLT=3300
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig
index 51f26f4..eda0c95 100644
--- a/configs/Ainol_AW1_defconfig
+++ b/configs/Ainol_AW1_defconfig
@@ -5,7 +5,6 @@
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=123
-CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:40000,le:87,ri:112,up:38,lo:141,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PH8"
diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig
index 0f8e571..32775a3 100644
--- a/configs/Ampe_A76_defconfig
+++ b/configs/Ampe_A76_defconfig
@@ -4,9 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
-CONFIG_USB0_VBUS_PIN="PG12"
-CONFIG_USB0_VBUS_DET="PG1"
-CONFIG_USB0_ID_DET="PG2"
CONFIG_AXP_GPIO=y
# CONFIG_VIDEO_HDMI is not set
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:82,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
diff --git a/configs/Auxtek-T003_defconfig b/configs/Auxtek-T003_defconfig
index 5209395..92e3016 100644
--- a/configs/Auxtek-T003_defconfig
+++ b/configs/Auxtek-T003_defconfig
@@ -5,7 +5,6 @@
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=0
-CONFIG_USB1_VBUS_PIN="PB10"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig
index 8b3a9ea..2290a44 100644
--- a/configs/Auxtek-T004_defconfig
+++ b/configs/Auxtek-T004_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
-CONFIG_USB1_VBUS_PIN="PG13"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig
index 2cc7bbb..b1195af 100644
--- a/configs/Bananapi_M2_Ultra_defconfig
+++ b/configs/Bananapi_M2_Ultra_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN8I_R40=y
CONFIG_DRAM_CLK=576
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB1_VBUS_PIN="PH23"
-CONFIG_USB2_VBUS_PIN="PH23"
# CONFIG_HAS_ARMV7_SECURE_BASE is not set
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/Bananapi_m2m_defconfig b/configs/Bananapi_m2m_defconfig
index d26aa0b..1e793f1 100644
--- a/configs/Bananapi_m2m_defconfig
+++ b/configs/Bananapi_m2m_defconfig
@@ -7,7 +7,6 @@
CONFIG_DRAM_ZQ=15291
CONFIG_DRAM_ODT_EN=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_ID_DET="PH8"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig
index 02be897..46025e9 100644
--- a/configs/Bananapro_defconfig
+++ b/configs/Bananapro_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
-CONFIG_USB1_VBUS_PIN="PH0"
-CONFIG_USB2_VBUS_PIN="PH1"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig
index c220d26..70d2cfa 100644
--- a/configs/CHIP_defconfig
+++ b/configs/CHIP_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
-CONFIG_USB0_VBUS_PIN="PB10"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_CHIP_DIP_SCAN=y
CONFIG_SPL_I2C=y
diff --git a/configs/CHIP_pro_defconfig b/configs/CHIP_pro_defconfig
index 0587412..17737d8 100644
--- a/configs/CHIP_pro_defconfig
+++ b/configs/CHIP_pro_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
-CONFIG_USB0_VBUS_PIN="PB10"
CONFIG_SPL_I2C=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=sunxi-nand.0"
diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig
index 1cd39d4..61fcb61 100644
--- a/configs/CSQ_CS908_defconfig
+++ b/configs/CSQ_CS908_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=432
-CONFIG_USB1_VBUS_PIN=""
-CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig
index 40f52d1..4713fbe 100644
--- a/configs/Chuwi_V7_CW0825_defconfig
+++ b/configs/Chuwi_V7_CW0825_defconfig
@@ -5,9 +5,6 @@
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=4
-CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB0_VBUS_DET="PH5"
-CONFIG_USB0_ID_DET="PH4"
CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:24,pclk_khz:51000,le:19,ri:300,up:6,lo:31,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_VIDEO_LCD_BL_EN="PH7"
diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
index 270bd7d..368919d 100644
--- a/configs/Colombus_defconfig
+++ b/configs/Colombus_defconfig
@@ -5,7 +5,6 @@
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=240
CONFIG_DRAM_ZQ=251
-CONFIG_USB1_VBUS_PIN=""
CONFIG_I2C0_ENABLE=y
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:2048,y:1536,depth:24,pclk_khz:208000,le:5,ri:150,up:9,lo:24,hs:5,vs:1,sync:3,vmode:0"
diff --git a/configs/Cubieboard4_defconfig b/configs/Cubieboard4_defconfig
index d3678ad..5b8428f 100644
--- a/configs/Cubieboard4_defconfig
+++ b/configs/Cubieboard4_defconfig
@@ -5,11 +5,8 @@
CONFIG_MACH_SUN9I=y
CONFIG_DRAM_CLK=672
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PH16"
-CONFIG_USB1_VBUS_PIN="PH14"
-CONFIG_USB3_VBUS_PIN="PH15"
CONFIG_AXP_GPIO=y
CONFIG_SYS_I2C_SUN8I_RSB=y
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP809_POWER=y
diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig
index 184143d..5f117f3 100644
--- a/configs/Cubietruck_defconfig
+++ b/configs/Cubietruck_defconfig
@@ -4,9 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
-CONFIG_USB0_VBUS_PIN="PH17"
-CONFIG_USB0_VBUS_DET="PH22"
-CONFIG_USB0_ID_DET="PH19"
CONFIG_VIDEO_VGA=y
CONFIG_GMAC_TX_DELAY=1
CONFIG_AHCI=y
diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig
index 29f4df2..e02e70f 100644
--- a/configs/Cubietruck_plus_defconfig
+++ b/configs/Cubietruck_plus_defconfig
@@ -7,10 +7,6 @@
CONFIG_DRAM_ZQ=15355
CONFIG_DRAM_ODT_EN=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PH11"
-CONFIG_USB1_VBUS_PIN="PD29"
-CONFIG_USB2_VBUS_PIN="PL6"
CONFIG_I2C0_ENABLE=y
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@@ -21,6 +17,7 @@
CONFIG_SYS_I2C_SPEED=400000
CONFIG_PHY_REALTEK=y
CONFIG_SUN8I_EMAC=y
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DLDO3_VOLT=2500
CONFIG_AXP_DLDO4_VOLT=3300
diff --git a/configs/Empire_electronix_d709_defconfig b/configs/Empire_electronix_d709_defconfig
index 18b1cfa..5130f27 100644
--- a/configs/Empire_electronix_d709_defconfig
+++ b/configs/Empire_electronix_d709_defconfig
@@ -5,9 +5,6 @@
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=0
-CONFIG_USB0_VBUS_PIN="PG12"
-CONFIG_USB0_VBUS_DET="PG1"
-CONFIG_USB0_ID_DET="PG2"
CONFIG_AXP_GPIO=y
# CONFIG_VIDEO_HDMI is not set
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:210,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
diff --git a/configs/Empire_electronix_m712_defconfig b/configs/Empire_electronix_m712_defconfig
index abaf386..7d33a53 100644
--- a/configs/Empire_electronix_m712_defconfig
+++ b/configs/Empire_electronix_m712_defconfig
@@ -4,9 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
-CONFIG_USB0_VBUS_PIN="PG12"
-CONFIG_USB0_VBUS_DET="PG1"
-CONFIG_USB0_ID_DET="PG2"
CONFIG_AXP_GPIO=y
# CONFIG_VIDEO_HDMI is not set
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:82,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig
index 24e8b5b..2bc9a09 100644
--- a/configs/Hummingbird_A31_defconfig
+++ b/configs/Hummingbird_A31_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_ZQ=251
-CONFIG_USB1_VBUS_PIN="PH24"
-CONFIG_USB2_VBUS_PIN=""
CONFIG_VIDEO_VGA_VIA_LCD=y
CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig
index 541f98d..6789e6b 100644
--- a/configs/Hyundai_A7HD_defconfig
+++ b/configs/Hyundai_A7HD_defconfig
@@ -4,10 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_EMR1=4
-CONFIG_USB0_VBUS_PIN="PB09"
-CONFIG_USB0_VBUS_DET="PH5"
-CONFIG_USB1_VBUS_PIN=""
-CONFIG_USB2_VBUS_PIN="PH6"
CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:45,ri:274,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PH2"
CONFIG_VIDEO_LCD_BL_EN="PH9"
diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig
index 9eb9a918..3e6c280 100644
--- a/configs/Linksprite_pcDuino3_Nano_defconfig
+++ b/configs/Linksprite_pcDuino3_Nano_defconfig
@@ -5,7 +5,6 @@
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=122
-CONFIG_USB1_VBUS_PIN="PH11"
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig
index 0e1a778..4b0b0e3 100644
--- a/configs/Linksprite_pcDuino_defconfig
+++ b/configs/Linksprite_pcDuino_defconfig
@@ -3,8 +3,6 @@
CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-pcduino"
CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
-CONFIG_USB1_VBUS_PIN=""
-CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig
index d60eedb..9a7d80f 100644
--- a/configs/MSI_Primo81_defconfig
+++ b/configs/MSI_Primo81_defconfig
@@ -5,13 +5,13 @@
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=360
CONFIG_DRAM_ZQ=122
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:768,y:1024,depth:18,pclk_khz:66000,le:56,ri:60,up:30,lo:36,hs:64,vs:50,sync:3,vmode:0"
CONFIG_VIDEO_LCD_BL_EN="PA25"
CONFIG_VIDEO_LCD_BL_PWM="PH13"
CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DLDO1_VOLT=3300
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig
index c697d28..1f4739e 100644
--- a/configs/Mele_A1000G_quad_defconfig
+++ b/configs/Mele_A1000G_quad_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_ZQ=120
-CONFIG_USB1_VBUS_PIN="PC27"
-CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/Mele_I7_defconfig b/configs/Mele_I7_defconfig
index 2b9bca1..be2e4d1 100644
--- a/configs/Mele_I7_defconfig
+++ b/configs/Mele_I7_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_ZQ=120
-CONFIG_USB1_VBUS_PIN="PC27"
-CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig
index be6dd41..9b1bb97 100644
--- a/configs/Mele_M9_defconfig
+++ b/configs/Mele_M9_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_ZQ=120
-CONFIG_USB1_VBUS_PIN="PC27"
-CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig
index a26677e..c47dc59 100644
--- a/configs/Merrii_A80_Optimus_defconfig
+++ b/configs/Merrii_A80_Optimus_defconfig
@@ -5,11 +5,8 @@
CONFIG_MACH_SUN9I=y
CONFIG_DRAM_CLK=672
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PH3"
-CONFIG_USB1_VBUS_PIN="PH4"
-CONFIG_USB3_VBUS_PIN="PH5"
CONFIG_AXP_GPIO=y
CONFIG_SYS_I2C_SUN8I_RSB=y
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP809_POWER=y
diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig
index e64352b..b1d8cdb 100644
--- a/configs/Mini-X_defconfig
+++ b/configs/Mini-X_defconfig
@@ -3,7 +3,6 @@
CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-mini-xplus"
CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
-CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig
index 53edf52..2ca40fd 100644
--- a/configs/Orangepi_defconfig
+++ b/configs/Orangepi_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
-CONFIG_USB1_VBUS_PIN="PH26"
-CONFIG_USB2_VBUS_PIN="PH22"
CONFIG_VIDEO_VGA=y
CONFIG_VIDEO_COMPOSITE=y
CONFIG_GMAC_TX_DELAY=3
diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig
index ccf3267..6b6e402 100644
--- a/configs/Orangepi_mini_defconfig
+++ b/configs/Orangepi_mini_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
-CONFIG_USB1_VBUS_PIN="PH26"
-CONFIG_USB2_VBUS_PIN="PH22"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
diff --git a/configs/Sinlinx_SinA31s_defconfig b/configs/Sinlinx_SinA31s_defconfig
index 59869b7..1c4c851 100644
--- a/configs/Sinlinx_SinA31s_defconfig
+++ b/configs/Sinlinx_SinA31s_defconfig
@@ -6,8 +6,6 @@
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=251
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
-CONFIG_USB1_VBUS_PIN=""
-CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
index cfb4329..a230599 100644
--- a/configs/Sinlinx_SinA33_defconfig
+++ b/configs/Sinlinx_SinA33_defconfig
@@ -6,7 +6,6 @@
CONFIG_DRAM_CLK=552
CONFIG_DRAM_ZQ=15291
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_ID_DET="PH8"
CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:66000,le:90,ri:160,up:3,lo:127,hs:70,vs:20,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
CONFIG_VIDEO_LCD_BL_EN="PH6"
diff --git a/configs/Sinovoip_BPI_M2_defconfig b/configs/Sinovoip_BPI_M2_defconfig
index aba9527..d7ef265 100644
--- a/configs/Sinovoip_BPI_M2_defconfig
+++ b/configs/Sinovoip_BPI_M2_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=432
-CONFIG_USB1_VBUS_PIN=""
-CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig
index ad41dbd..98c533b 100644
--- a/configs/Sinovoip_BPI_M3_defconfig
+++ b/configs/Sinovoip_BPI_M3_defconfig
@@ -8,15 +8,13 @@
CONFIG_DRAM_ZQ=15355
CONFIG_DRAM_ODT_EN=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PH11"
-CONFIG_USB1_VBUS_PIN="PD24"
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
CONFIG_PHY_REALTEK=y
CONFIG_SUN8I_EMAC=y
CONFIG_INITIAL_USB_SCAN_DELAY=500
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DCDC5_VOLT=1200
CONFIG_AXP_DLDO3_VOLT=3300
diff --git a/configs/Sunchip_CX-A99_defconfig b/configs/Sunchip_CX-A99_defconfig
index 348140d..0d78a13 100644
--- a/configs/Sunchip_CX-A99_defconfig
+++ b/configs/Sunchip_CX-A99_defconfig
@@ -7,7 +7,4 @@
CONFIG_DRAM_ZQ=3881915
CONFIG_DRAM_ODT_EN=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="PH15"
-CONFIG_USB1_VBUS_PIN="PL7"
-CONFIG_USB3_VBUS_PIN="PL8"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig
index d74ef21..fb2b20b 100644
--- a/configs/UTOO_P66_defconfig
+++ b/configs/UTOO_P66_defconfig
@@ -6,9 +6,6 @@
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=0
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="PB04"
-CONFIG_USB0_VBUS_DET="PG01"
-CONFIG_USB0_ID_DET="PG2"
CONFIG_AXP_GPIO=y
# CONFIG_VIDEO_HDMI is not set
CONFIG_VIDEO_LCD_MODE="x:480,y:800,depth:18,pclk_khz:25000,le:2,ri:93,up:2,lo:93,hs:1,vs:1,sync:3,vmode:0"
diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig
index 40aeb66..649e95b 100644
--- a/configs/Wexler_TAB7200_defconfig
+++ b/configs/Wexler_TAB7200_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
-CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB0_ID_DET="PH4"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:210,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PH8"
diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig
index 9f6d2a7..49c87c3 100644
--- a/configs/Wobo_i5_defconfig
+++ b/configs/Wobo_i5_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
-CONFIG_USB1_VBUS_PIN="PG12"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig
index 9b13659..d798861 100644
--- a/configs/Yones_Toptech_BD1078_defconfig
+++ b/configs/Yones_Toptech_BD1078_defconfig
@@ -6,7 +6,6 @@
CONFIG_DRAM_CLK=408
CONFIG_MMC1_PINS_PH=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=1
-CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:63000,le:32,ri:287,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
diff --git a/configs/Yones_Toptech_BS1078_V2_defconfig b/configs/Yones_Toptech_BS1078_V2_defconfig
index de69ebe..ae31b7f 100644
--- a/configs/Yones_Toptech_BS1078_V2_defconfig
+++ b/configs/Yones_Toptech_BS1078_V2_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=420
CONFIG_DRAM_ZQ=251
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PA15"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:70000,le:120,ri:180,up:17,lo:15,hs:20,vs:3,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
@@ -14,6 +12,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PH13"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig
index d77ff2d..3667a06 100644
--- a/configs/am62ax_evm_a53_defconfig
+++ b/configs/am62ax_evm_a53_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
@@ -15,7 +16,6 @@
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x80a00000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
@@ -39,8 +39,6 @@
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_CMD_MMC=y
-CONFIG_MMC_SPEED_MODE_SET=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_UPSTREAM=y
diff --git a/configs/am62ax_evm_r5_defconfig b/configs/am62ax_evm_r5_defconfig
index cbdc219..4ea551b 100644
--- a/configs/am62ax_evm_r5_defconfig
+++ b/configs/am62ax_evm_r5_defconfig
@@ -16,7 +16,6 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x7145
-CONFIG_SPL_TEXT_BASE=0x43c00000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x43c3b000
CONFIG_SPL_BSS_MAX_SIZE=0x3000
diff --git a/configs/am62px_evm_a53_defconfig b/configs/am62px_evm_a53_defconfig
index 4b5d1ec..fa857e5 100644
--- a/configs/am62px_evm_a53_defconfig
+++ b/configs/am62px_evm_a53_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
@@ -13,10 +14,10 @@
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am62p5-sk"
-CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
@@ -54,20 +55,12 @@
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_CLK=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_REMOTEPROC=y
-CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_EFIDEBUG=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
-CONFIG_MMC_SPEED_MODE_SET=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_UPSTREAM=y
@@ -115,6 +108,7 @@
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_MTD=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
CONFIG_DM_SPI_FLASH=y
@@ -147,6 +141,7 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
+CONFIG_ZSTD=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
diff --git a/configs/am62px_evm_r5_defconfig b/configs/am62px_evm_r5_defconfig
index 39b6a83..f2e1f31 100644
--- a/configs/am62px_evm_r5_defconfig
+++ b/configs/am62px_evm_r5_defconfig
@@ -19,7 +19,6 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL_TEXT_BASE=0x43c00000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x43c4b000
CONFIG_SPL_BSS_MAX_SIZE=0x3000
diff --git a/configs/am62x_beagleplay_a53_defconfig b/configs/am62x_beagleplay_a53_defconfig
index cedd0f7..f61e701 100644
--- a/configs/am62x_beagleplay_a53_defconfig
+++ b/configs/am62x_beagleplay_a53_defconfig
@@ -11,7 +11,6 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am625-beagleplay"
-CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
diff --git a/configs/am62x_beagleplay_r5_defconfig b/configs/am62x_beagleplay_r5_defconfig
index 5a465bf..7ca5f58 100644
--- a/configs/am62x_beagleplay_r5_defconfig
+++ b/configs/am62x_beagleplay_r5_defconfig
@@ -18,7 +18,6 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x7000
-CONFIG_SPL_TEXT_BASE=0x43c00000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x43c3b000
CONFIG_SPL_BSS_MAX_SIZE=0x3000
diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig
index d9596cb..2c04d32 100644
--- a/configs/am62x_evm_a53_defconfig
+++ b/configs/am62x_evm_a53_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
@@ -12,10 +13,10 @@
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am625-sk"
-CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
@@ -54,9 +55,10 @@
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
-CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
CONFIG_CMD_EFIDEBUG=y
-CONFIG_MMC_SPEED_MODE_SET=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_UPSTREAM=y
@@ -97,6 +99,8 @@
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_MTD=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_SOFT_RESET=y
@@ -129,6 +133,7 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
+CONFIG_ZSTD=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig
index 8eb5940..4e3ed78 100644
--- a/configs/am62x_evm_r5_defconfig
+++ b/configs/am62x_evm_r5_defconfig
@@ -20,7 +20,6 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x7000
-CONFIG_SPL_TEXT_BASE=0x43c00000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x43c3b000
CONFIG_SPL_BSS_MAX_SIZE=0x3000
diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig
index c2ad124..59e8c51 100644
--- a/configs/am64x_evm_a53_defconfig
+++ b/configs/am64x_evm_a53_defconfig
@@ -3,6 +3,7 @@
CONFIG_ARCH_K3=y
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
@@ -16,10 +17,10 @@
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am642-evm"
-CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
@@ -31,6 +32,7 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
+CONFIG_PCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
@@ -64,19 +66,18 @@
CONFIG_SPL_THERMAL=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_BOOTEFI_SELFTEST=y
-CONFIG_CMD_ASKENV=y
CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_EFIDEBUG=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_PMIC=y
-CONFIG_CMD_REGULATOR=y
-CONFIG_MMC_SPEED_MODE_SET=y
+CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_UPSTREAM=y
@@ -128,6 +129,7 @@
CONFIG_SPI_FLASH_S28HX_T=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
+CONFIG_DM_MTD=y
CONFIG_MULTIPLEXER=y
CONFIG_MUX_MMIO=y
CONFIG_PHY_TI_DP83867=y
@@ -135,6 +137,9 @@
CONFIG_PHY_FIXED=y
CONFIG_TI_AM65_CPSW_NUSS=y
CONFIG_TI_ICSSG_PRUETH=y
+CONFIG_NVME_PCI=y
+CONFIG_PCI_CONFIG_HOST_BRIDGE=y
+CONFIG_PCIE_CDNS_TI=y
CONFIG_PHY=y
CONFIG_SPL_PHY=y
CONFIG_PHY_CADENCE_TORRENT=y
@@ -160,6 +165,7 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
+CONFIG_ZSTD=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index 12c4cb9..a41f67a 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -3,6 +3,7 @@
CONFIG_ARCH_K3=y
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SOC_K3_AM654=y
@@ -19,7 +20,6 @@
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x80a00000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
@@ -35,9 +35,10 @@
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_BOOTCOMMAND=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run boot_rprocs; if test ${boot_fit} -eq 1; then run get_fit_${boot}; run get_overlaystring; run run_fit; else; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern; fi;"
CONFIG_LOGLEVEL=7
CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
@@ -59,15 +60,7 @@
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_MMC_SPEED_MODE_SET=y
CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_TIME=y
CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),128k(ospi.env),128k(ospi.env.backup),1m(ospi.sysfw),-@8m(ospi.rootfs)"
CONFIG_CMD_UBI=y
diff --git a/configs/amd_versal2_mini_defconfig b/configs/amd_versal2_mini_defconfig
index b657118..d224583 100644
--- a/configs/amd_versal2_mini_defconfig
+++ b/configs/amd_versal2_mini_defconfig
@@ -13,12 +13,9 @@
CONFIG_ENV_SIZE=0x80
CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-mini"
CONFIG_SYS_LOAD_ADDR=0xBBF80000
-CONFIG_DEBUG_UART_BASE=0xf1920000
-CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_XILINX_MINI=y
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
# CONFIG_PSCI_RESET is not set
-CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00001000
# CONFIG_EXPERT is not set
@@ -71,9 +68,6 @@
# CONFIG_INPUT is not set
# CONFIG_MMC is not set
# CONFIG_POWER is not set
-CONFIG_DEBUG_UART_PL011=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_ARM_DCC=y
CONFIG_PL01X_SERIAL=y
# CONFIG_GZIP is not set
diff --git a/configs/amd_versal2_mini_emmc_defconfig b/configs/amd_versal2_mini_emmc_defconfig
index da3eebe..3afc6cb 100644
--- a/configs/amd_versal2_mini_emmc_defconfig
+++ b/configs/amd_versal2_mini_emmc_defconfig
@@ -10,11 +10,8 @@
CONFIG_ENV_SIZE=0x80
CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-mini"
CONFIG_SYS_LOAD_ADDR=0x8000000
-CONFIG_DEBUG_UART_BASE=0xf1920000
-CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_XILINX_MINI=y
# CONFIG_PSCI_RESET is not set
-CONFIG_DEBUG_UART=y
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
# CONFIG_EFI_LOADER is not set
@@ -60,9 +57,6 @@
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_DEBUG_UART_PL011=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_ARM_DCC=y
CONFIG_PL01X_SERIAL=y
CONFIG_FAT_WRITE=y
diff --git a/configs/amd_versal2_mini_ospi_defconfig b/configs/amd_versal2_mini_ospi_defconfig
index 8b9c440..54328e8 100644
--- a/configs/amd_versal2_mini_ospi_defconfig
+++ b/configs/amd_versal2_mini_ospi_defconfig
@@ -13,12 +13,9 @@
CONFIG_ENV_SIZE=0x80
CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-mini"
CONFIG_SYS_LOAD_ADDR=0xBBF80000
-CONFIG_DEBUG_UART_BASE=0xf1920000
-CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_XILINX_MINI=y
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
# CONFIG_PSCI_RESET is not set
-CONFIG_DEBUG_UART=y
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
# CONFIG_LEGACY_IMAGE_FORMAT is not set
@@ -72,9 +69,6 @@
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MT35XU=y
# CONFIG_POWER is not set
-CONFIG_DEBUG_UART_PL011=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_ARM_DCC=y
CONFIG_PL01X_SERIAL=y
CONFIG_SPI=y
diff --git a/configs/amd_versal2_mini_qspi_defconfig b/configs/amd_versal2_mini_qspi_defconfig
index e17ca86..48fb7ae 100644
--- a/configs/amd_versal2_mini_qspi_defconfig
+++ b/configs/amd_versal2_mini_qspi_defconfig
@@ -13,12 +13,9 @@
CONFIG_ENV_SIZE=0x80
CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-mini"
CONFIG_SYS_LOAD_ADDR=0xBBF80000
-CONFIG_DEBUG_UART_BASE=0xf1920000
-CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_XILINX_MINI=y
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
# CONFIG_PSCI_RESET is not set
-CONFIG_DEBUG_UART=y
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
# CONFIG_LEGACY_IMAGE_FORMAT is not set
@@ -65,9 +62,6 @@
# CONFIG_INPUT is not set
# CONFIG_MMC is not set
# CONFIG_POWER is not set
-CONFIG_DEBUG_UART_PL011=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_ARM_DCC=y
CONFIG_PL01X_SERIAL=y
CONFIG_SPI=y
diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig
index 9911caa..6ec7dd3 100644
--- a/configs/amd_versal2_virt_defconfig
+++ b/configs/amd_versal2_virt_defconfig
@@ -3,17 +3,15 @@
CONFIG_POSITION_INDEPENDENT=y
CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864
CONFIG_ARCH_VERSAL2=y
-CONFIG_TEXT_BASE=0x8000000
+CONFIG_TEXT_BASE=0x40000000
CONFIG_SYS_MALLOC_F_LEN=0x100000
+CONFIG_NR_DRAM_BANKS=36
CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-virt"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_SYS_BOOTM_LEN=0x6400000
CONFIG_SYS_LOAD_ADDR=0x8000000
-CONFIG_DEBUG_UART_BASE=0xf1920000
-CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_CMD_FRU=y
-CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00001000
CONFIG_REMAKE_ELF=y
@@ -28,6 +26,7 @@
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_CLOCKS=y
CONFIG_SYS_PROMPT="versal2> "
+CONFIG_CMD_SMBIOS=y
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_NVEDIT_EFI=y
@@ -64,8 +63,9 @@
CONFIG_CMD_UBI=y
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_BOARD=y
-CONFIG_DTB_RESELECT=y
-CONFIG_MULTI_DTB_FIT=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_LWIP=y
@@ -75,6 +75,8 @@
CONFIG_CLK_SCMI=y
CONFIG_DFU_RAM=y
CONFIG_ARM_FFA_TRANSPORT=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_VERSALPL=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_I2C_MUX=y
@@ -82,6 +84,7 @@
CONFIG_DM_MAILBOX=y
CONFIG_ZYNQMP_IPI=y
CONFIG_MISC=y
+CONFIG_NVMEM=y
CONFIG_I2C_EEPROM=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
@@ -113,11 +116,10 @@
CONFIG_XILINX_AXIEMAC=y
CONFIG_ZYNQ_GEM=y
CONFIG_POWER_DOMAIN=y
+CONFIG_ZYNQMP_POWER_DOMAIN=y
CONFIG_RESET_SCMI=y
+CONFIG_RESET_ZYNQMP=y
CONFIG_SCSI=y
-CONFIG_DEBUG_UART_PL011=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_ARM_DCC=y
CONFIG_PL01X_SERIAL=y
CONFIG_SOC_DEVICE=y
diff --git a/configs/an7581_evb_defconfig b/configs/an7581_evb_defconfig
index f09b5b6..c74247e 100644
--- a/configs/an7581_evb_defconfig
+++ b/configs/an7581_evb_defconfig
@@ -76,3 +76,6 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SHA512=y
+CONFIG_AIROHA_ETH=y
+CONFIG_MMC_MTK=y
+CONFIG_AIROHA_SNFI_SPI=y
diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig
index c76f36e..60b678a 100644
--- a/configs/ba10_tv_box_defconfig
+++ b/configs/ba10_tv_box_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=384
CONFIG_DRAM_EMR1=4
-CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB2_VBUS_PIN="PH12"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
diff --git a/configs/bananapi-f3_defconfig b/configs/bananapi-f3_defconfig
index 7483f12..30c4f8a 100644
--- a/configs/bananapi-f3_defconfig
+++ b/configs/bananapi-f3_defconfig
@@ -19,3 +19,5 @@
CONFIG_SYS_NS16550=y
CONFIG_SYS_NS16550_MEM32=y
CONFIG_RESET_SPACEMIT_K1=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
diff --git a/configs/bananapi_m2_berry_defconfig b/configs/bananapi_m2_berry_defconfig
index f4edcf4..94d29a4 100644
--- a/configs/bananapi_m2_berry_defconfig
+++ b/configs/bananapi_m2_berry_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN8I_R40=y
CONFIG_DRAM_CLK=576
-CONFIG_USB1_VBUS_PIN="PH23"
# CONFIG_HAS_ARMV7_SECURE_BASE is not set
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/boston32r2_defconfig b/configs/boston32r2_defconfig
index 6f4dfad..5556148 100644
--- a/configs/boston32r2_defconfig
+++ b/configs/boston32r2_defconfig
@@ -4,7 +4,7 @@
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="img,boston"
+CONFIG_DEFAULT_DEVICE_TREE="img/boston"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x88000000
CONFIG_ENV_ADDR=0xBFFE0000
diff --git a/configs/boston32r2el_defconfig b/configs/boston32r2el_defconfig
index cdf13c8..d23eb99 100644
--- a/configs/boston32r2el_defconfig
+++ b/configs/boston32r2el_defconfig
@@ -4,7 +4,7 @@
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="img,boston"
+CONFIG_DEFAULT_DEVICE_TREE="img/boston"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x88000000
CONFIG_ENV_ADDR=0xBFFE0000
diff --git a/configs/boston32r6_defconfig b/configs/boston32r6_defconfig
index d8fb956..56738e9 100644
--- a/configs/boston32r6_defconfig
+++ b/configs/boston32r6_defconfig
@@ -4,7 +4,7 @@
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="img,boston"
+CONFIG_DEFAULT_DEVICE_TREE="img/boston"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x88000000
CONFIG_ENV_ADDR=0xBFFE0000
diff --git a/configs/boston32r6el_defconfig b/configs/boston32r6el_defconfig
index b6d3102..ddc6655 100644
--- a/configs/boston32r6el_defconfig
+++ b/configs/boston32r6el_defconfig
@@ -4,7 +4,7 @@
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="img,boston"
+CONFIG_DEFAULT_DEVICE_TREE="img/boston"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x88000000
CONFIG_ENV_ADDR=0xBFFE0000
diff --git a/configs/boston64r2_defconfig b/configs/boston64r2_defconfig
index 6b23d18..fa234b6 100644
--- a/configs/boston64r2_defconfig
+++ b/configs/boston64r2_defconfig
@@ -4,7 +4,7 @@
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="img,boston"
+CONFIG_DEFAULT_DEVICE_TREE="img/boston"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0xffffffff88000000
CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000
diff --git a/configs/boston64r2el_defconfig b/configs/boston64r2el_defconfig
index ff4b526..58bf881 100644
--- a/configs/boston64r2el_defconfig
+++ b/configs/boston64r2el_defconfig
@@ -4,7 +4,7 @@
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="img,boston"
+CONFIG_DEFAULT_DEVICE_TREE="img/boston"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0xffffffff88000000
CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000
diff --git a/configs/boston64r6_defconfig b/configs/boston64r6_defconfig
index a7446ec..eb3ec00 100644
--- a/configs/boston64r6_defconfig
+++ b/configs/boston64r6_defconfig
@@ -4,7 +4,7 @@
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="img,boston"
+CONFIG_DEFAULT_DEVICE_TREE="img/boston"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0xffffffff88000000
CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000
diff --git a/configs/boston64r6el_defconfig b/configs/boston64r6el_defconfig
index 0dab8ef..332c2ba 100644
--- a/configs/boston64r6el_defconfig
+++ b/configs/boston64r6el_defconfig
@@ -4,7 +4,7 @@
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="img,boston"
+CONFIG_DEFAULT_DEVICE_TREE="img/boston"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0xffffffff88000000
CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000
diff --git a/configs/brcp150_defconfig b/configs/brcp150_defconfig
new file mode 100644
index 0000000..d619f71
--- /dev/null
+++ b/configs/brcp150_defconfig
@@ -0,0 +1,121 @@
+CONFIG_ARM=y
+CONFIG_SYS_VENDOR="BuR"
+CONFIG_SYS_CONFIG_NAME="brzynq"
+CONFIG_SYS_L2CACHE_OFF=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SOURCE_FILE="env/brcp150"
+CONFIG_SF_DEFAULT_SPEED=100000000
+CONFIG_SF_DEFAULT_MODE=0x3
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x20000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp150"
+CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000
+# CONFIG_SPL_MMC is not set
+CONFIG_SPL_STACK_R_ADDR=0x800000
+CONFIG_SPL_STACK=0xFFFFFE00
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x20000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_LOAD_ADDR=0x2000000
+CONFIG_SPL_SIZE_LIMIT=0x20000
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x30000
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000
+CONFIG_TARGET_ZYNQ_BR=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000
+CONFIG_SPL_LOAD_FIT_FULL=y
+CONFIG_BOOTDELAY=0
+CONFIG_OF_ENV_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run b_default"
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_CLOCKS=y
+CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
+CONFIG_SPL_CPU=y
+CONFIG_SPL_FPGA=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_HUSH_PARSER=y
+CONFIG_HUSH_MODERN_PARSER=y
+CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_BOOTP_MAY_FAIL=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_NET_RETRY_COUNT=10
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
+CONFIG_MAX7320_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_ZYNQ_HISPD_BROKEN=y
+CONFIG_DM_MTD=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HX_T=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_ZBIT=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_PHY_TI_GENERIC=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y
+# CONFIG_SHA256 is not set
+CONFIG_SPL_CRC32=y
+# CONFIG_SPL_SHA1 is not set
diff --git a/configs/brcp170_defconfig b/configs/brcp170_defconfig
new file mode 100644
index 0000000..06cd64a
--- /dev/null
+++ b/configs/brcp170_defconfig
@@ -0,0 +1,120 @@
+CONFIG_ARM=y
+CONFIG_SYS_VENDOR="BuR"
+CONFIG_SYS_CONFIG_NAME="brzynq"
+CONFIG_SYS_L2CACHE_OFF=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SOURCE_FILE="env/brcp1"
+CONFIG_SF_DEFAULT_SPEED=100000000
+CONFIG_SF_DEFAULT_MODE=0x3
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x20000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp170"
+CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000
+# CONFIG_SPL_MMC is not set
+CONFIG_SPL_STACK_R_ADDR=0x800000
+CONFIG_SPL_STACK=0xFFFFFE00
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x20000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_LOAD_ADDR=0x2000000
+CONFIG_SPL_SIZE_LIMIT=0x20000
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x30000
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000
+CONFIG_TARGET_ZYNQ_BR=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000
+CONFIG_SPL_LOAD_FIT_FULL=y
+CONFIG_BOOTDELAY=0
+CONFIG_OF_ENV_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run b_default"
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_CLOCKS=y
+CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
+CONFIG_SPL_CPU=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_HUSH_PARSER=y
+CONFIG_HUSH_MODERN_PARSER=y
+CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_BOOTP_MAY_FAIL=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_NET_RETRY_COUNT=10
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
+CONFIG_MAX7320_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_ZYNQ_HISPD_BROKEN=y
+CONFIG_DM_MTD=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HX_T=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_ZBIT=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_PHY_TI_GENERIC=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y
+# CONFIG_SHA256 is not set
+CONFIG_SPL_CRC32=y
+# CONFIG_SPL_SHA1 is not set
diff --git a/configs/brcp1_1r_defconfig b/configs/brcp1_1r_defconfig
new file mode 100644
index 0000000..ed2eb86
--- /dev/null
+++ b/configs/brcp1_1r_defconfig
@@ -0,0 +1,120 @@
+CONFIG_ARM=y
+CONFIG_SYS_VENDOR="BuR"
+CONFIG_SYS_CONFIG_NAME="brzynq"
+CONFIG_SYS_L2CACHE_OFF=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SOURCE_FILE="env/brcp1"
+CONFIG_SF_DEFAULT_SPEED=100000000
+CONFIG_SF_DEFAULT_MODE=0x3
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x20000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp1_1r"
+CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000
+# CONFIG_SPL_MMC is not set
+CONFIG_SPL_STACK_R_ADDR=0x800000
+CONFIG_SPL_STACK=0xFFFFFE00
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x20000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_LOAD_ADDR=0x2000000
+CONFIG_SPL_SIZE_LIMIT=0x20000
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x30000
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000
+CONFIG_TARGET_ZYNQ_BR=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000
+CONFIG_SPL_LOAD_FIT_FULL=y
+CONFIG_BOOTDELAY=0
+CONFIG_OF_ENV_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run b_default"
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_CLOCKS=y
+CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
+CONFIG_SPL_CPU=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_HUSH_PARSER=y
+CONFIG_HUSH_MODERN_PARSER=y
+CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_BOOTP_MAY_FAIL=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_NET_RETRY_COUNT=10
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
+CONFIG_MAX7320_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_ZYNQ_HISPD_BROKEN=y
+CONFIG_DM_MTD=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HX_T=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_ZBIT=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y
+# CONFIG_SHA256 is not set
+CONFIG_SPL_CRC32=y
+# CONFIG_SPL_SHA1 is not set
diff --git a/configs/brcp1_1r_switch_defconfig b/configs/brcp1_1r_switch_defconfig
new file mode 100644
index 0000000..38427da
--- /dev/null
+++ b/configs/brcp1_1r_switch_defconfig
@@ -0,0 +1,121 @@
+CONFIG_ARM=y
+CONFIG_SYS_VENDOR="BuR"
+CONFIG_SYS_CONFIG_NAME="brzynq"
+CONFIG_SYS_L2CACHE_OFF=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SOURCE_FILE="env/brcp1"
+CONFIG_SF_DEFAULT_SPEED=100000000
+CONFIG_SF_DEFAULT_MODE=0x3
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x20000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp1_1r_switch"
+CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000
+# CONFIG_SPL_MMC is not set
+CONFIG_SPL_STACK_R_ADDR=0x800000
+CONFIG_SPL_STACK=0xFFFFFE00
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x20000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_LOAD_ADDR=0x2000000
+CONFIG_SPL_SIZE_LIMIT=0x20000
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x30000
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000
+CONFIG_TARGET_ZYNQ_BR=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000
+CONFIG_SPL_LOAD_FIT_FULL=y
+CONFIG_BOOTDELAY=0
+CONFIG_OF_ENV_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run b_default"
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_CLOCKS=y
+CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
+CONFIG_SPL_CPU=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_HUSH_PARSER=y
+CONFIG_HUSH_MODERN_PARSER=y
+CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_BOOTP_MAY_FAIL=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_NET_RETRY_COUNT=10
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
+CONFIG_MAX7320_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_ZYNQ_HISPD_BROKEN=y
+CONFIG_DM_MTD=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HX_T=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_ZBIT=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_FIXED=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y
+# CONFIG_SHA256 is not set
+CONFIG_SPL_CRC32=y
+# CONFIG_SPL_SHA1 is not set
diff --git a/configs/brcp1_2r_defconfig b/configs/brcp1_2r_defconfig
new file mode 100644
index 0000000..2bc8eab
--- /dev/null
+++ b/configs/brcp1_2r_defconfig
@@ -0,0 +1,120 @@
+CONFIG_ARM=y
+CONFIG_SYS_VENDOR="BuR"
+CONFIG_SYS_CONFIG_NAME="brzynq"
+CONFIG_SYS_L2CACHE_OFF=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SOURCE_FILE="env/brcp1"
+CONFIG_SF_DEFAULT_SPEED=100000000
+CONFIG_SF_DEFAULT_MODE=0x3
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x20000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp1_2r"
+CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000
+# CONFIG_SPL_MMC is not set
+CONFIG_SPL_STACK_R_ADDR=0x800000
+CONFIG_SPL_STACK=0xFFFFFE00
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x20000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_LOAD_ADDR=0x2000000
+CONFIG_SPL_SIZE_LIMIT=0x20000
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x30000
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000
+CONFIG_TARGET_ZYNQ_BR=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000
+CONFIG_SPL_LOAD_FIT_FULL=y
+CONFIG_BOOTDELAY=0
+CONFIG_OF_ENV_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run b_default"
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_CLOCKS=y
+CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
+CONFIG_SPL_CPU=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_HUSH_PARSER=y
+CONFIG_HUSH_MODERN_PARSER=y
+CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_BOOTP_MAY_FAIL=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_NET_RETRY_COUNT=10
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
+CONFIG_MAX7320_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_ZYNQ_HISPD_BROKEN=y
+CONFIG_DM_MTD=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HX_T=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_ZBIT=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y
+# CONFIG_SHA256 is not set
+CONFIG_SPL_CRC32=y
+# CONFIG_SPL_SHA1 is not set
diff --git a/configs/brsmarc2_defconfig b/configs/brsmarc2_defconfig
new file mode 100644
index 0000000..0b57042
--- /dev/null
+++ b/configs/brsmarc2_defconfig
@@ -0,0 +1,120 @@
+CONFIG_ARM=y
+CONFIG_SYS_VENDOR="BuR"
+CONFIG_SYS_CONFIG_NAME="brzynq"
+CONFIG_SYS_L2CACHE_OFF=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SOURCE_FILE="env/brcp1"
+CONFIG_SF_DEFAULT_SPEED=100000000
+CONFIG_SF_DEFAULT_MODE=0x3
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x20000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-brsmarc2"
+CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000
+# CONFIG_SPL_MMC is not set
+CONFIG_SPL_STACK_R_ADDR=0x800000
+CONFIG_SPL_STACK=0xFFFFFE00
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x20000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_LOAD_ADDR=0x2000000
+CONFIG_SPL_SIZE_LIMIT=0x20000
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x30000
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000
+CONFIG_TARGET_ZYNQ_BR=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000
+CONFIG_SPL_LOAD_FIT_FULL=y
+CONFIG_BOOTDELAY=0
+CONFIG_OF_ENV_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run b_default"
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_CLOCKS=y
+CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
+CONFIG_SPL_CPU=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_HUSH_PARSER=y
+CONFIG_HUSH_MODERN_PARSER=y
+CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_BOOTP_MAY_FAIL=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_NET_RETRY_COUNT=10
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
+CONFIG_MAX7320_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_ZYNQ_HISPD_BROKEN=y
+CONFIG_DM_MTD=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HX_T=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_ZBIT=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y
+# CONFIG_SHA256 is not set
+CONFIG_SPL_CRC32=y
+# CONFIG_SPL_SHA1 is not set
diff --git a/configs/capricorn_cxg3_defconfig b/configs/capricorn_cxg3_defconfig
index 3cc4606..5689544 100644
--- a/configs/capricorn_cxg3_defconfig
+++ b/configs/capricorn_cxg3_defconfig
@@ -1,117 +1,16 @@
-CONFIG_ARM=y
-CONFIG_ARCH_IMX8=y
-CONFIG_TEXT_BASE=0x80020000
-CONFIG_SYS_MALLOC_LEN=0x2800000
-CONFIG_SYS_MALLOC_F_LEN=0x4000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=3
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x200000
-CONFIG_DM_GPIO=y
+#include <configs/imx8qxp_capricorn.config>
+
CONFIG_DEFAULT_DEVICE_TREE="imx8-capricorn-cxg3"
-CONFIG_TARGET_CAPRICORN=y
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK=0x13e000
-CONFIG_SPL_TEXT_BASE=0x100000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x128000
-CONFIG_SPL_BSS_MAX_SIZE=0x1000
-CONFIG_SYS_BOOTM_LEN=0x800000
-CONFIG_SYS_LOAD_ADDR=0x80280000
-CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0x202000
CONFIG_IDENT_STRING=" ##v01.06"
-CONFIG_REMAKE_ELF=y
-# CONFIG_EFI_LOADER is not set
-CONFIG_FIT=y
-CONFIG_FIT_EXTERNAL_OFFSET=0x3000
-CONFIG_BOOTDELAY=3
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
-CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
-CONFIG_AUTOBOOT_KEYED_CTRLC=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="if usrbutton; then run flash_self_test; reset; fi;run flash_self;reset;"
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2073
-CONFIG_LOG=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_MAX_SIZE=0x1f000
-CONFIG_SPL_BOARD_INIT=y
-# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set
-CONFIG_SPL_LOAD_IMX_CONTAINER=y
-CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg"
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_HAVE_INIT_STACK=y
-CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
-CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000
-CONFIG_SPL_SYS_MALLOC_SIZE=0x4000
-CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
-CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_WATCHDOG=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="U-Boot# "
-CONFIG_CMD_CPU=y
-# CONFIG_BOOTM_NETBSD is not set
-# CONFIG_CMD_EXPORTENV is not set
-# CONFIG_CMD_IMPORTENV is not set
-# CONFIG_CMD_CRC32 is not set
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DM=y
-CONFIG_CMD_FUSE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_READ=y
-CONFIG_CMD_WDT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_MMC_ENV_PART=2
+
+CONFIG_ENV_SOURCE_FILE="capricorn_default"
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_ENV_OFFSET=0x200000
+CONFIG_ENV_OFFSET_REDUND=0x202000
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eth1"
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_BOOTCOUNT_ENV=y
-CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd"
-CONFIG_SPL_CLK=y
-CONFIG_CLK_IMX8=y
-CONFIG_CPU=y
-CONFIG_MXC_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_IMX_LPI2C=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_MISC=y
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_FSL_USDHC=y
-CONFIG_PHYLIB=y
+
CONFIG_MV88E61XX_SWITCH=y
CONFIG_MV88E61XX_CPU_PORT=5
CONFIG_MV88E61XX_PHY_PORTS=0x7
@@ -119,23 +18,3 @@
CONFIG_FEC_MXC_SHARE_MDIO=y
CONFIG_FEC_MXC_MDIO_BASE=0x5B050000
CONFIG_FEC_MXC=y
-CONFIG_MII=y
-CONFIG_PHY=y
-CONFIG_NOP_PHY=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
-CONFIG_PINCTRL_IMX8=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_IMX8_POWER_DOMAIN=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SPL_DM_REGULATOR_GPIO=y
-CONFIG_DM_SERIAL=y
-CONFIG_FSL_LPUART=y
-CONFIG_DM_THERMAL=y
-CONFIG_IMX_SCU_THERMAL=y
-# CONFIG_WATCHDOG is not set
-CONFIG_WDT=y
-CONFIG_WDT_SIEMENS_PMIC=y
-CONFIG_SPL_TINY_MEMSET=y
diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig
index d9314ed..4adf8cc 100644
--- a/configs/clearfog_defconfig
+++ b/configs/clearfog_defconfig
@@ -61,7 +61,6 @@
CONFIG_I2C_EEPROM=y
CONFIG_SPL_I2C_EEPROM=y
CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
diff --git a/configs/clearfog_sata_defconfig b/configs/clearfog_sata_defconfig
index d5f90d0..8154125 100644
--- a/configs/clearfog_sata_defconfig
+++ b/configs/clearfog_sata_defconfig
@@ -62,7 +62,6 @@
CONFIG_SPL_I2C_EEPROM=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
diff --git a/configs/clearfog_spi_defconfig b/configs/clearfog_spi_defconfig
index 8868c7f..e9e3e8c 100644
--- a/configs/clearfog_spi_defconfig
+++ b/configs/clearfog_spi_defconfig
@@ -62,7 +62,6 @@
CONFIG_SPL_I2C_EEPROM=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
diff --git a/configs/colorfly_e708_q1_defconfig b/configs/colorfly_e708_q1_defconfig
index 07bda04..bdabca2 100644
--- a/configs/colorfly_e708_q1_defconfig
+++ b/configs/colorfly_e708_q1_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=251
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PA15"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:800,y:1280,depth:24,pclk_khz:64000,le:20,ri:34,up:1,lo:16,hs:10,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
@@ -14,6 +12,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PH13"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_AXP_DLDO2_VOLT=1800
diff --git a/configs/difrnce_dit4350_defconfig b/configs/difrnce_dit4350_defconfig
index b060430..3b59091 100644
--- a/configs/difrnce_dit4350_defconfig
+++ b/configs/difrnce_dit4350_defconfig
@@ -4,9 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
-CONFIG_USB0_VBUS_PIN="PG12"
-CONFIG_USB0_VBUS_DET="PG1"
-CONFIG_USB0_ID_DET="PG2"
CONFIG_AXP_GPIO=y
# CONFIG_VIDEO_HDMI is not set
CONFIG_VIDEO_LCD_MODE="x:480,y:272,depth:18,pclk_khz:12000,le:1,ri:43,up:1,lo:12,hs:1,vs:1,sync:3,vmode:0"
diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig
index 5870aae..449d48a 100644
--- a/configs/dragonboard410c_defconfig
+++ b/configs/dragonboard410c_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_BOARD="dragonboard410c"
-CONFIG_COUNTER_FREQUENCY=19000000
+CONFIG_COUNTER_FREQUENCY=19200000
CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
CONFIG_ARCH_SNAPDRAGON=y
CONFIG_TEXT_BASE=0x8f600000
@@ -14,18 +14,16 @@
CONFIG_SYS_LOAD_ADDR=0x80080000
CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 410C"
CONFIG_REMAKE_ELF=y
-# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_BUTTON_CMD=y
CONFIG_FIT=y
-CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTSTD_FULL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CBSIZE=512
CONFIG_SYS_PBSIZE=548
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="dragonboard410c => "
-# CONFIG_CMD_IMI is not set
CONFIG_CMD_MD5SUM=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPIO=y
@@ -35,6 +33,7 @@
CONFIG_BOOTP_BOOTFILESIZE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIMER=y
+CONFIG_CMD_SYSBOOT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
@@ -69,6 +68,7 @@
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_VENDOR_NUM=0x18d1
diff --git a/configs/dserve_dsrv9703c_defconfig b/configs/dserve_dsrv9703c_defconfig
index 06a79c9..9060db4 100644
--- a/configs/dserve_dsrv9703c_defconfig
+++ b/configs/dserve_dsrv9703c_defconfig
@@ -3,9 +3,6 @@
CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-dserve-dsrv9703c"
CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
-CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB0_VBUS_DET="PH5"
-CONFIG_USB0_ID_DET="PH4"
CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:80000,le:479,ri:544,up:5,lo:26,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
CONFIG_VIDEO_LCD_POWER="PH8"
diff --git a/configs/endeavoru_defconfig b/configs/endeavoru_defconfig
index fb3d7fc..c85994b 100644
--- a/configs/endeavoru_defconfig
+++ b/configs/endeavoru_defconfig
@@ -83,5 +83,5 @@
CONFIG_VIDEO_BRIDGE=y
# CONFIG_VIDEO_LOGO is not set
CONFIG_VIDEO_LCD_ENDEAVORU=y
-CONFIG_VIDEO_DSI_TEGRA30=y
+CONFIG_VIDEO_DSI_TEGRA=y
CONFIG_TEGRA_BACKLIGHT_PWM=y
diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig
index 935071d..a3fc34f 100644
--- a/configs/ga10h_v1_1_defconfig
+++ b/configs/ga10h_v1_1_defconfig
@@ -6,8 +6,6 @@
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=15291
CONFIG_DRAM_ODT_EN=y
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PH8"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:52000,le:138,ri:162,up:22,lo:10,hs:20,vs:3,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
@@ -16,6 +14,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_CONS_INDEX=5
diff --git a/configs/gardena-smart-gateway-mt7688_defconfig b/configs/gardena-smart-gateway-mt7688_defconfig
index b7f4a76..2c69e91 100644
--- a/configs/gardena-smart-gateway-mt7688_defconfig
+++ b/configs/gardena-smart-gateway-mt7688_defconfig
@@ -47,6 +47,7 @@
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_LICENSE=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_MEMINFO=y
diff --git a/configs/ge_b1x5v2_defconfig b/configs/ge_b1x5v2_defconfig
index fec4b67..b8cca3c 100644
--- a/configs/ge_b1x5v2_defconfig
+++ b/configs/ge_b1x5v2_defconfig
@@ -116,6 +116,7 @@
CONFIG_SYSRESET=y
CONFIG_SYSRESET_CMD_POWEROFF=y
CONFIG_POWEROFF_GPIO=y
+CONFIG_SPL_POWEROFF_GPIO=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
diff --git a/configs/generic-rk3328_defconfig b/configs/generic-rk3328_defconfig
new file mode 100644
index 0000000..8d34a29
--- /dev/null
+++ b/configs/generic-rk3328_defconfig
@@ -0,0 +1,90 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=25000000
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-generic"
+CONFIG_DM_RESET=y
+CONFIG_ROCKCHIP_RK3328=y
+CONFIG_ROCKCHIP_EXTERNAL_TPL=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART_BASE=0xFF130000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_BOOTMETH_VBE is not set
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-generic.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MISC=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RNG=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+# CONFIG_OF_UPSTREAM is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NO_NET=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+# CONFIG_ADC is not set
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
+CONFIG_ROCKCHIP_GPIO=y
+# CONFIG_ROCKCHIP_IODOMAIN is not set
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_ZBIT=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/generic-rk3399_defconfig b/configs/generic-rk3399_defconfig
new file mode 100644
index 0000000..3abe65b
--- /dev/null
+++ b/configs/generic-rk3399_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=25000000
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-generic"
+CONFIG_DM_RESET=y
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_EXTERNAL_TPL=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
+CONFIG_TARGET_EVB_RK3399=y
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_DEBUG_UART=y
+CONFIG_FIT_VERBOSE=y
+# CONFIG_BOOTMETH_VBE is not set
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-generic.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MISC=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RNG=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+# CONFIG_OF_UPSTREAM is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NO_NET=y
+# CONFIG_ADC is not set
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
+CONFIG_ROCKCHIP_GPIO=y
+# CONFIG_ROCKCHIP_IODOMAIN is not set
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_ZBIT=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/generic-rk3528_defconfig b/configs/generic-rk3528_defconfig
new file mode 100644
index 0000000..e19c7bc
--- /dev/null
+++ b/configs/generic-rk3528_defconfig
@@ -0,0 +1,40 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3528-generic"
+CONFIG_ROCKCHIP_RK3528=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART_BASE=0xFF9F0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+# CONFIG_BOOTMETH_VBE is not set
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3528-generic.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MISC=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RNG=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_OF_UPSTREAM is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_NO_NET=y
+# CONFIG_ADC is not set
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig
index f79f0e8..76418ba 100644
--- a/configs/generic-rk3568_defconfig
+++ b/configs/generic-rk3568_defconfig
@@ -28,6 +28,8 @@
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
CONFIG_SPL_ATF=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MISC=y
@@ -35,6 +37,7 @@
CONFIG_CMD_ROCKUSB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RNG=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
diff --git a/configs/generic-rk3588_defconfig b/configs/generic-rk3588_defconfig
index 51e31dc..2075584 100644
--- a/configs/generic-rk3588_defconfig
+++ b/configs/generic-rk3588_defconfig
@@ -22,6 +22,8 @@
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MISC=y
@@ -29,6 +31,7 @@
CONFIG_CMD_ROCKUSB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RNG=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
diff --git a/configs/grouper_defconfig b/configs/grouper_defconfig
index b98f23a..016fc60 100644
--- a/configs/grouper_defconfig
+++ b/configs/grouper_defconfig
@@ -88,4 +88,4 @@
CONFIG_CI_UDC=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_LOGO is not set
-CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_TEGRA=y
diff --git a/configs/gt90h_v4_defconfig b/configs/gt90h_v4_defconfig
index 205eab2..ba22a3e 100644
--- a/configs/gt90h_v4_defconfig
+++ b/configs/gt90h_v4_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN8I_A23=y
CONFIG_DRAM_CLK=480
CONFIG_DRAM_ZQ=32767
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PH8"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:55000,le:159,ri:160,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
@@ -14,6 +12,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_CONS_INDEX=5
diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig
index 29f9652..2fcae46 100644
--- a/configs/h8_homlet_v2_defconfig
+++ b/configs/h8_homlet_v2_defconfig
@@ -6,8 +6,6 @@
CONFIG_DRAM_CLK=480
CONFIG_DRAM_ZQ=15355
CONFIG_DRAM_ODT_EN=y
-CONFIG_USB0_VBUS_PIN="PL5"
-CONFIG_USB1_VBUS_PIN="PL6"
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig
index fa8fe24..9fa9c12 100644
--- a/configs/harmony_defconfig
+++ b/configs/harmony_defconfig
@@ -64,5 +64,5 @@
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
-CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_TEGRA=y
CONFIG_CONSOLE_SCROLL_LINES=10
diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig
index 6927e20..3fb5f67 100644
--- a/configs/helios4_defconfig
+++ b/configs/helios4_defconfig
@@ -61,7 +61,6 @@
CONFIG_I2C_EEPROM=y
CONFIG_SPL_I2C_EEPROM=y
CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig
index c96336f..6893b4a 100644
--- a/configs/iNet_3F_defconfig
+++ b/configs/iNet_3F_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=4
-CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB0_VBUS_DET="PH5"
CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:100000,le:799,ri:260,up:15,lo:16,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_VIDEO_LCD_BL_EN="PH7"
diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig
index 76228f0..6cb55b6 100644
--- a/configs/iNet_3W_defconfig
+++ b/configs/iNet_3W_defconfig
@@ -6,8 +6,6 @@
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=127
CONFIG_DRAM_EMR1=4
-CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB0_VBUS_DET="PH5"
CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:24,pclk_khz:65000,le:159,ri:160,up:22,lo:15,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_VIDEO_LCD_BL_EN="PH7"
diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig
index afa530d..2acf11d 100644
--- a/configs/iNet_86VS_defconfig
+++ b/configs/iNet_86VS_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
-CONFIG_USB0_VBUS_PIN="PG12"
-CONFIG_USB0_VBUS_DET="PG1"
CONFIG_AXP_GPIO=y
# CONFIG_VIDEO_HDMI is not set
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
diff --git a/configs/iNet_D978_rev2_defconfig b/configs/iNet_D978_rev2_defconfig
index ed6a603..00ed5d4 100644
--- a/configs/iNet_D978_rev2_defconfig
+++ b/configs/iNet_D978_rev2_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=456
CONFIG_DRAM_ZQ=15291
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PH8"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:65000,le:120,ri:180,up:22,lo:13,hs:20,vs:3,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
@@ -15,6 +13,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DLDO1_VOLT=3300
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
diff --git a/configs/icnova-a20-swac_defconfig b/configs/icnova-a20-swac_defconfig
index 30c28f7..3812eed 100644
--- a/configs/icnova-a20-swac_defconfig
+++ b/configs/icnova-a20-swac_defconfig
@@ -9,9 +9,6 @@
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_OLD_SUNXI_KERNEL_COMPAT=y
-CONFIG_USB0_VBUS_PIN="PG11"
-CONFIG_USB0_VBUS_DET="PH7"
-CONFIG_USB1_VBUS_PIN="PG10"
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PH22"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
diff --git a/configs/ideapad-yoga-11_defconfig b/configs/ideapad-yoga-11_defconfig
index bc7f615..b77110e 100644
--- a/configs/ideapad-yoga-11_defconfig
+++ b/configs/ideapad-yoga-11_defconfig
@@ -83,4 +83,4 @@
CONFIG_VIDEO=y
# CONFIG_VIDEO_LOGO is not set
CONFIG_VIDEO_BRIDGE_PARADE_DP501=y
-CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_TEGRA=y
diff --git a/configs/imx8qxp_capricorn.config b/configs/imx8qxp_capricorn.config
new file mode 100644
index 0000000..463e584
--- /dev/null
+++ b/configs/imx8qxp_capricorn.config
@@ -0,0 +1,134 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2800000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_MMC_ENV_PART=2
+
+CONFIG_DM_GPIO=y
+CONFIG_AHAB_BOOT=y
+
+CONFIG_TARGET_CAPRICORN=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK=0x13e000
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x128000
+CONFIG_SPL_BSS_MAX_SIZE=0x1000
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_SYS_LOAD_ADDR=0x80280000
+CONFIG_SPL=y
+
+CONFIG_REMAKE_ELF=y
+# CONFIG_EFI_LOADER is not set
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_BOOTDELAY=3
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
+CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
+CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="if usrbutton; then run flash_self_test; reset; fi;run flash_self;reset;"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2073
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_MAX_SIZE=0x1f000
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg"
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x4000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="U-Boot# "
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_BIND is not set
+CONFIG_CMD_WDT=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+
+CONFIG_SPL_DM=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ENV=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd"
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+
+CONFIG_MII=y
+CONFIG_PHY=y
+CONFIG_NOP_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+CONFIG_WATCHDOG=y
+CONFIG_WDT=y
+CONFIG_WDT_SIEMENS_PMIC=y
+CONFIG_SPL_TINY_MEMSET=y
diff --git a/configs/imx93-phycore_defconfig b/configs/imx93-phycore_defconfig
index af1fbc7..ddd642a 100644
--- a/configs/imx93-phycore_defconfig
+++ b/configs/imx93-phycore_defconfig
@@ -35,7 +35,6 @@
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;"
CONFIG_DEFAULT_FDT_FILE="oftree"
CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_PBSIZE=2074
diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig
index 59c4da7..d03895e 100644
--- a/configs/imx93_11x11_evk_defconfig
+++ b/configs/imx93_11x11_evk_defconfig
@@ -129,3 +129,5 @@
CONFIG_WDT=y
CONFIG_LZO=y
CONFIG_BZIP2=y
+CONFIG_UTHREAD=y
+CONFIG_CMD_SPAWN=y
diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig
index 68a6df5..0a50992 100644
--- a/configs/inet1_defconfig
+++ b/configs/inet1_defconfig
@@ -5,9 +5,6 @@
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=4
-CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB0_VBUS_DET="PH5"
-CONFIG_USB0_ID_DET="PH4"
CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:52000,le:32,ri:287,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_VIDEO_LCD_BL_EN="PH7"
diff --git a/configs/inet86dz_defconfig b/configs/inet86dz_defconfig
index d215a83..da0fb74 100644
--- a/configs/inet86dz_defconfig
+++ b/configs/inet86dz_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN8I_A23=y
CONFIG_DRAM_CLK=552
CONFIG_DRAM_ZQ=63351
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PH8"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:138,ri:162,up:22,lo:10,hs:20,vs:3,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
@@ -14,6 +12,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_CONS_INDEX=5
diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig
index a5414e2..826141a 100644
--- a/configs/inet97fv2_defconfig
+++ b/configs/inet97fv2_defconfig
@@ -5,9 +5,6 @@
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=4
-CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB0_VBUS_DET="PH5"
-CONFIG_USB0_ID_DET="PH4"
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_VIDEO_LCD_BL_EN="PH7"
diff --git a/configs/inet98v_rev2_defconfig b/configs/inet98v_rev2_defconfig
index 48b20c0..7da2963 100644
--- a/configs/inet98v_rev2_defconfig
+++ b/configs/inet98v_rev2_defconfig
@@ -4,9 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
-CONFIG_USB0_VBUS_PIN="PG12"
-CONFIG_USB0_VBUS_DET="PG1"
-CONFIG_USB0_ID_DET="PG2"
CONFIG_AXP_GPIO=y
# CONFIG_VIDEO_HDMI is not set
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig
index 5b0cda1..ffc3548 100644
--- a/configs/inet9f_rev03_defconfig
+++ b/configs/inet9f_rev03_defconfig
@@ -5,9 +5,6 @@
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=4
-CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB0_VBUS_DET="PH5"
-CONFIG_USB0_ID_DET="PH4"
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_VIDEO_LCD_BL_EN="PH7"
diff --git a/configs/inet_q972_defconfig b/configs/inet_q972_defconfig
index 24ff6c0..5a48bd0 100644
--- a/configs/inet_q972_defconfig
+++ b/configs/inet_q972_defconfig
@@ -5,14 +5,13 @@
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=384
CONFIG_DRAM_ZQ=251
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PA15"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:65000,le:280,ri:20,up:22,lo:8,hs:20,vs:8,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
CONFIG_VIDEO_LCD_BL_EN="PA25"
CONFIG_VIDEO_LCD_BL_PWM="PH13"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/iot2050_defconfig b/configs/iot2050_defconfig
index 72d4b8e..5bb692e 100644
--- a/configs/iot2050_defconfig
+++ b/configs/iot2050_defconfig
@@ -21,7 +21,6 @@
CONFIG_DM_RESET=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x80a00000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index 3126ba3..fbdec74 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -22,7 +22,6 @@
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x80a00000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
diff --git a/configs/j721e_beagleboneai64_a72_defconfig b/configs/j721e_beagleboneai64_a72_defconfig
index fad01c2..e3cd593 100644
--- a/configs/j721e_beagleboneai64_a72_defconfig
+++ b/configs/j721e_beagleboneai64_a72_defconfig
@@ -14,7 +14,6 @@
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j721e-beagleboneai64"
-CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 6bc7166..99461cf 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -14,7 +14,6 @@
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j721e-common-proc-board"
-CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig
index 5e84abf..084deea 100644
--- a/configs/j721s2_evm_a72_defconfig
+++ b/configs/j721s2_evm_a72_defconfig
@@ -21,7 +21,6 @@
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x80a00000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
diff --git a/configs/j722s_evm_a53_defconfig b/configs/j722s_evm_a53_defconfig
index 5d2bb52..19f4a3b 100644
--- a/configs/j722s_evm_a53_defconfig
+++ b/configs/j722s_evm_a53_defconfig
@@ -19,7 +19,6 @@
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x80a00000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
diff --git a/configs/j722s_evm_r5_defconfig b/configs/j722s_evm_r5_defconfig
index d96392d..40db0da 100644
--- a/configs/j722s_evm_r5_defconfig
+++ b/configs/j722s_evm_r5_defconfig
@@ -19,7 +19,6 @@
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL_TEXT_BASE=0x43c00000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x43c7b000
CONFIG_SPL_BSS_MAX_SIZE=0x3000
diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig
index 1280194..56af023 100644
--- a/configs/j784s4_evm_a72_defconfig
+++ b/configs/j784s4_evm_a72_defconfig
@@ -21,7 +21,6 @@
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x80a00000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig
index b41c2cf..f8c38aa 100644
--- a/configs/jesurun_q5_defconfig
+++ b/configs/jesurun_q5_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=312
-CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
diff --git a/configs/malta64_defconfig b/configs/malta64_defconfig
index ec5df0b..d1211b0 100644
--- a/configs/malta64_defconfig
+++ b/configs/malta64_defconfig
@@ -46,3 +46,4 @@
CONFIG_RTC_MC146818=y
CONFIG_SYS_NS16550=y
CONFIG_SYS_NS16550_PORT_MAPPED=y
+CONFIG_UNIT_TEST=y
diff --git a/configs/malta_defconfig b/configs/malta_defconfig
index ca017c4..dfa37d1 100644
--- a/configs/malta_defconfig
+++ b/configs/malta_defconfig
@@ -45,3 +45,4 @@
CONFIG_RTC_MC146818=y
CONFIG_SYS_NS16550=y
CONFIG_SYS_NS16550_PORT_MAPPED=y
+CONFIG_UNIT_TEST=y
diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig
index 737a061..d99adda 100644
--- a/configs/medcom-wide_defconfig
+++ b/configs/medcom-wide_defconfig
@@ -53,4 +53,4 @@
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
-CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_TEGRA=y
diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
index 08f8bdb..7497d20 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -97,6 +97,7 @@
CONFIG_XILINX_UARTLITE=y
CONFIG_XILINX_SPI=y
CONFIG_SYSRESET_GPIO=y
+CONFIG_SPL_SYSRESET_GPIO=y
CONFIG_SYSRESET_MICROBLAZE=y
CONFIG_WDT=y
CONFIG_XILINX_TB_WATCHDOG=y
diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig
index 2f92228..11e7a3d 100644
--- a/configs/mixtile_loftq_defconfig
+++ b/configs/mixtile_loftq_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_ZQ=251
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB1_VBUS_PIN="PH24"
-CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig
index d3d7402..f1812d6 100644
--- a/configs/mk802_a10s_defconfig
+++ b/configs/mk802_a10s_defconfig
@@ -5,7 +5,6 @@
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=0
-CONFIG_USB1_VBUS_PIN="PB10"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig
index 8ebd5e9..edf64f8 100644
--- a/configs/mk802_defconfig
+++ b/configs/mk802_defconfig
@@ -3,7 +3,6 @@
CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-mk802"
CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
-CONFIG_USB2_VBUS_PIN="PH12"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/mocha_defconfig b/configs/mocha_defconfig
index dfeb16a..66cf81d 100644
--- a/configs/mocha_defconfig
+++ b/configs/mocha_defconfig
@@ -89,4 +89,4 @@
# CONFIG_VIDEO_LOGO is not set
CONFIG_VIDEO_LCD_SHARP_LQ079L1SX01=y
CONFIG_BACKLIGHT_LP855x=y
-CONFIG_VIDEO_DSI_TEGRA30=y
+CONFIG_VIDEO_DSI_TEGRA=y
diff --git a/configs/mot_defconfig b/configs/mot_defconfig
new file mode 100644
index 0000000..40b4fee
--- /dev/null
+++ b/configs/mot_defconfig
@@ -0,0 +1,93 @@
+CONFIG_ARM=y
+CONFIG_ARCH_TEGRA=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x00110000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SOURCE_FILE="mot"
+CONFIG_ENV_SIZE=0x3000
+CONFIG_ENV_OFFSET=0xFFFFD000
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-motorola-olympus"
+CONFIG_SPL_STACK=0xffffc
+CONFIG_SPL_TEXT_BASE=0x00108000
+CONFIG_SYS_LOAD_ADDR=0x2000000
+CONFIG_TEGRA20=y
+CONFIG_TARGET_MOT=y
+CONFIG_TEGRA_ENABLE_UARTB=y
+CONFIG_CMD_EBTUPDATE=y
+CONFIG_BUTTON_CMD=y
+CONFIG_BOOTDELAY=0
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="bootflow scan; echo 'Boot configuration not found... Power off in 3 sec'; sleep 3; poweroff"
+CONFIG_SYS_PBSIZE=2085
+CONFIG_SPL_FOOTPRINT_LIMIT=y
+CONFIG_SPL_MAX_FOOTPRINT=0x8000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
+CONFIG_SYS_PROMPT="Tegra20 (Mot) # "
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
+CONFIG_CMD_BOOTMENU=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_UMS_ABORT_KEYED=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PAUSE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_BUTTON=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x11000000
+CONFIG_FASTBOOT_BUF_SIZE=0x5000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_GPIO_HOG=y
+CONFIG_SYS_I2C_TEGRA=y
+CONFIG_BUTTON_KEYBOARD=y
+CONFIG_CPCAP_POWER_BUTTON=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_CPCAP=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_CPCAP=y
+CONFIG_SYS_NS16550=y
+CONFIG_TEGRA20_SLINK=y
+CONFIG_SYSRESET_CMD_POWEROFF=y
+CONFIG_POWEROFF_GPIO=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Motorola"
+CONFIG_USB_GADGET_VENDOR_NUM=0x22b8
+CONFIG_USB_GADGET_PRODUCT_NUM=0x708c
+CONFIG_CI_UDC=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_LOGO is not set
+CONFIG_VIDEO_LCD_MOT=y
+CONFIG_BACKLIGHT_LM3532=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_VIDEO_DSI_TEGRA=y
diff --git a/configs/mvebu_espressobin_ultra-88f3720_defconfig b/configs/mvebu_espressobin_ultra-88f3720_defconfig
index 6f1a66f..1cbeee8 100644
--- a/configs/mvebu_espressobin_ultra-88f3720_defconfig
+++ b/configs/mvebu_espressobin_ultra-88f3720_defconfig
@@ -34,7 +34,6 @@
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PCI=y
-CONFIG_CMD_SATA=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_WDT=y
diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig
index 7aaa519..50047d9 100644
--- a/configs/orangepi_2_defconfig
+++ b/configs/orangepi_2_defconfig
@@ -5,7 +5,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
-CONFIG_USB1_VBUS_PIN="PG13"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
index adffe38..008c09d 100644
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB1_VBUS_PIN="PG13"
-CONFIG_USB3_VBUS_PIN="PG11"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/orangepi_zero2_defconfig b/configs/orangepi_zero2_defconfig
index f2265ea..831bfe6 100644
--- a/configs/orangepi_zero2_defconfig
+++ b/configs/orangepi_zero2_defconfig
@@ -8,7 +8,6 @@
CONFIG_DRAM_SUNXI_TPR10=0xf83438
CONFIG_MACH_SUN50I_H616=y
CONFIG_SUNXI_DRAM_H616_DDR3_1333=y
-CONFIG_USB1_VBUS_PIN="PC16"
CONFIG_R_I2C_ENABLE=y
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/orangepi_zero3_defconfig b/configs/orangepi_zero3_defconfig
index 63f9a73..8594924 100644
--- a/configs/orangepi_zero3_defconfig
+++ b/configs/orangepi_zero3_defconfig
@@ -13,7 +13,6 @@
CONFIG_MACH_SUN50I_H616=y
CONFIG_SUNXI_DRAM_H616_LPDDR4=y
CONFIG_DRAM_CLK=792
-CONFIG_USB1_VBUS_PIN="PC16"
CONFIG_R_I2C_ENABLE=y
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/parrot_r16_defconfig b/configs/parrot_r16_defconfig
index 72235cc..631cfd8 100644
--- a/configs/parrot_r16_defconfig
+++ b/configs/parrot_r16_defconfig
@@ -6,8 +6,6 @@
CONFIG_DRAM_CLK=600
CONFIG_DRAM_ZQ=15291
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_ID_DET="PD10"
-CONFIG_USB1_VBUS_PIN="PD12"
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig
index b8645d6..af2cb71 100644
--- a/configs/paz00_defconfig
+++ b/configs/paz00_defconfig
@@ -53,5 +53,5 @@
CONFIG_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
CONFIG_I2C_EDID=y
-CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_TEGRA=y
CONFIG_CONSOLE_SCROLL_LINES=10
diff --git a/configs/phycore_am62ax_a53_defconfig b/configs/phycore_am62ax_a53_defconfig
index d86e19d..9417692 100644
--- a/configs/phycore_am62ax_a53_defconfig
+++ b/configs/phycore_am62ax_a53_defconfig
@@ -24,7 +24,6 @@
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x80a00000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
diff --git a/configs/phycore_am62ax_r5_defconfig b/configs/phycore_am62ax_r5_defconfig
index 25d2d9b..7bcfbe9 100644
--- a/configs/phycore_am62ax_r5_defconfig
+++ b/configs/phycore_am62ax_r5_defconfig
@@ -17,7 +17,6 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x7145
-CONFIG_SPL_TEXT_BASE=0x43c00000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x43c3b000
CONFIG_SPL_BSS_MAX_SIZE=0x3000
diff --git a/configs/phycore_am62ax_r5_ethboot_defconfig b/configs/phycore_am62ax_r5_ethboot_defconfig
new file mode 100644
index 0000000..81a7f5b
--- /dev/null
+++ b/configs/phycore_am62ax_r5_ethboot_defconfig
@@ -0,0 +1,43 @@
+#include <configs/phycore_am62ax_r5_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_AM62A7=y
+CONFIG_TARGET_PHYCORE_AM62AX_R5=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am62a7-r5-phycore-som-2gb"
+
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000
+CONFIG_SPL_BSS_MAX_SIZE=0x3100
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_ETH=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_NET=y
+CONFIG_SPL_NET_VCI_STRING="AM62AX U-Boot R5 SPL"
+CONFIG_SPL_SYSCON=y
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_SPL_MMC=n
+CONFIG_SPL_DM_SPI=n
+CONFIG_SPL_MMC=n
+CONFIG_SPL_SPI_FLASH_SUPPORT=n
+CONFIG_SPL_SPI=n
+CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=n
+CONFIG_SPL_SPI_LOAD=n
+CONFIG_SPL_YMODEM_SUPPORT=n
+CONFIG_DM_SPI_FLASH=n
+CONFIG_SPI_FLASH_SFDP_SUPPORT=n
+CONFIG_SPI_FLASH_SOFT_RESET=n
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=n
+CONFIG_SPI_FLASH_STMICRO=n
+CONFIG_SPI_FLASH_MT35XU=n
+CONFIG_SPI=n
+CONFIG_DM_SPI=n
+CONFIG_CADENCE_QSPI=n
diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig
index d7aa59b..4ad3998 100644
--- a/configs/phycore_am62x_a53_defconfig
+++ b/configs/phycore_am62x_a53_defconfig
@@ -3,6 +3,7 @@
CONFIG_ARCH_K3=y
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SOC_K3_AM625=y
@@ -14,20 +15,21 @@
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am625-phyboard-lyra-rdk"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x83000000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x80c80000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SPL_STACK_R=y
CONFIG_SYS_BOOTM_LEN=0x800000
-CONFIG_SPL_SIZE_LIMIT=0x40000
+CONFIG_SPL_SIZE_LIMIT=0x80000
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x800
CONFIG_ENV_OFFSET_REDUND=0x6c0000
CONFIG_SPL_FS_FAT=y
@@ -52,11 +54,15 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SPL_DMA=y
CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_ETH=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_NET=y
+CONFIG_SPL_NET_VCI_STRING="AM62X U-Boot A53 SPL"
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_DEVICE=y
# CONFIG_SPL_SPI_FLASH_TINY is not set
@@ -68,9 +74,11 @@
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
+CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
@@ -106,6 +114,7 @@
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DA8XX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
diff --git a/configs/phycore_am62x_r5_defconfig b/configs/phycore_am62x_r5_defconfig
index f157103..a5d494c 100644
--- a/configs/phycore_am62x_r5_defconfig
+++ b/configs/phycore_am62x_r5_defconfig
@@ -21,7 +21,6 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL_TEXT_BASE=0x43c00000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x43c3b000
CONFIG_SPL_BSS_MAX_SIZE=0x3000
diff --git a/configs/phycore_am62x_r5_ethboot_defconfig b/configs/phycore_am62x_r5_ethboot_defconfig
new file mode 100644
index 0000000..3bc4268
--- /dev/null
+++ b/configs/phycore_am62x_r5_ethboot_defconfig
@@ -0,0 +1,43 @@
+#include <configs/phycore_am62x_r5_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_AM625=y
+CONFIG_TARGET_PHYCORE_AM62X_R5=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am625-r5-phycore-som-2gb"
+
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_ETH=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_NET=y
+CONFIG_SPL_NET_VCI_STRING="AM62X U-Boot R5 SPL"
+CONFIG_SPL_SYSCON=y
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_SPL_MMC=n
+CONFIG_SPL_DM_SPI=n
+CONFIG_SPL_MMC=n
+CONFIG_SPL_SPI_FLASH_SUPPORT=n
+CONFIG_SPL_SPI=n
+CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=n
+CONFIG_SPL_SPI_LOAD=n
+CONFIG_SPL_YMODEM_SUPPORT=n
+CONFIG_DM_SPI_FLASH=n
+CONFIG_SPI_FLASH_SFDP_SUPPORT=n
+CONFIG_SPI_FLASH_SOFT_RESET=n
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=n
+CONFIG_SPI_FLASH_STMICRO=n
+CONFIG_SPI_FLASH_MT35XU=n
+CONFIG_SPI=n
+CONFIG_DM_SPI=n
+CONFIG_CADENCE_QSPI=n
+CONFIG_SPL_DM_SPI=n
diff --git a/configs/phycore_am64x_a53_defconfig b/configs/phycore_am64x_a53_defconfig
index 4ee1bd8..d484293 100644
--- a/configs/phycore_am64x_a53_defconfig
+++ b/configs/phycore_am64x_a53_defconfig
@@ -24,7 +24,6 @@
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x80a00000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
@@ -77,6 +76,7 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
+CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
diff --git a/configs/picasso_defconfig b/configs/picasso_defconfig
index fe1eeb6..6a83df9 100644
--- a/configs/picasso_defconfig
+++ b/configs/picasso_defconfig
@@ -81,4 +81,4 @@
CONFIG_VIDEO=y
# CONFIG_VIDEO_LOGO is not set
# CONFIG_VIDEO_BPP8 is not set
-CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_TEGRA=y
diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig
index 20a4a0a..3eaa9c8 100644
--- a/configs/pine_h64_defconfig
+++ b/configs/pine_h64_defconfig
@@ -5,7 +5,6 @@
CONFIG_MACH_SUN50I_H6=y
CONFIG_SUNXI_DRAM_H6_LPDDR3=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB3_VBUS_PIN="PL5"
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_PSCI_RESET is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/polaroid_mid2407pxe03_defconfig b/configs/polaroid_mid2407pxe03_defconfig
index 6ec7c83..6c0d4f1 100644
--- a/configs/polaroid_mid2407pxe03_defconfig
+++ b/configs/polaroid_mid2407pxe03_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN8I_A23=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=63351
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PH8"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:40,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
@@ -14,6 +12,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_CONS_INDEX=5
diff --git a/configs/polaroid_mid2809pxe04_defconfig b/configs/polaroid_mid2809pxe04_defconfig
index 1aefc50..7b64c8b 100644
--- a/configs/polaroid_mid2809pxe04_defconfig
+++ b/configs/polaroid_mid2809pxe04_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN8I_A23=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=63351
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PH8"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:36,ri:210,up:18,lo:22,hs:10,vs:5,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
@@ -14,6 +12,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_CONS_INDEX=5
diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig
index 330c97f..21da05f 100644
--- a/configs/pov_protab2_ips9_defconfig
+++ b/configs/pov_protab2_ips9_defconfig
@@ -4,9 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=432
-CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB0_VBUS_DET="PH5"
-CONFIG_USB0_ID_DET="PH4"
CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:100000,le:480,ri:260,up:6,lo:16,hs:320,vs:10,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
CONFIG_VIDEO_LCD_POWER="PH8"
diff --git a/configs/q8_a13_tablet_defconfig b/configs/q8_a13_tablet_defconfig
index 93a2578..2c7bc20 100644
--- a/configs/q8_a13_tablet_defconfig
+++ b/configs/q8_a13_tablet_defconfig
@@ -4,9 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=384
-CONFIG_USB0_VBUS_PIN="PG12"
-CONFIG_USB0_VBUS_DET="PG1"
-CONFIG_USB0_ID_DET="PG2"
CONFIG_AXP_GPIO=y
# CONFIG_VIDEO_HDMI is not set
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:40,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0"
diff --git a/configs/q8_a23_tablet_800x480_defconfig b/configs/q8_a23_tablet_800x480_defconfig
index 0f8c30e..fcf13f6 100644
--- a/configs/q8_a23_tablet_800x480_defconfig
+++ b/configs/q8_a23_tablet_800x480_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN8I_A23=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=63306
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PH8"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:36,ri:210,up:18,lo:22,hs:10,vs:5,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
@@ -14,6 +12,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_CONS_INDEX=5
diff --git a/configs/q8_a33_tablet_1024x600_defconfig b/configs/q8_a33_tablet_1024x600_defconfig
index b3b5cc7..22e27ab 100644
--- a/configs/q8_a33_tablet_1024x600_defconfig
+++ b/configs/q8_a33_tablet_1024x600_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=456
CONFIG_DRAM_ZQ=15291
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PH8"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:159,ri:160,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
@@ -14,6 +12,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_CONS_INDEX=5
diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig
index 37ee08f..1d9d6fc 100644
--- a/configs/q8_a33_tablet_800x480_defconfig
+++ b/configs/q8_a33_tablet_800x480_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=456
CONFIG_DRAM_ZQ=15291
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PH8"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:167,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
@@ -14,6 +12,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_CONS_INDEX=5
diff --git a/configs/qc750_defconfig b/configs/qc750_defconfig
index a42860d..9104cc0 100644
--- a/configs/qc750_defconfig
+++ b/configs/qc750_defconfig
@@ -80,4 +80,4 @@
CONFIG_CI_UDC=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_LOGO is not set
-CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_TEGRA=y
diff --git a/configs/qemu-arm-sbsa_defconfig b/configs/qemu-arm-sbsa_defconfig
index 8c5d3eb..3819670 100644
--- a/configs/qemu-arm-sbsa_defconfig
+++ b/configs/qemu-arm-sbsa_defconfig
@@ -9,3 +9,4 @@
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_EFI_MEDIA=y
CONFIG_FS_FAT=y
+CONFIG_UNIT_TEST=y
diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig
index 9f20b3f..a444899 100644
--- a/configs/qemu-ppce500_defconfig
+++ b/configs/qemu-ppce500_defconfig
@@ -66,3 +66,4 @@
CONFIG_VIRTIO_BLK=y
CONFIG_ADDR_MAP=y
CONFIG_PANIC_HANG=y
+CONFIG_UNIT_TEST=y
diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig
index 1cd80f5..b9cb780 100644
--- a/configs/qemu-riscv32_defconfig
+++ b/configs/qemu-riscv32_defconfig
@@ -1,6 +1,5 @@
CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0x800000
-CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_ENV_SIZE=0x20000
@@ -16,7 +15,10 @@
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
# CONFIG_CMD_MII is not set
+CONFIG_CMD_SPAWN=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_SYS_MAX_FLASH_BANKS=2
+CONFIG_UTHREAD=y
+CONFIG_UNIT_TEST=y
diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig
index 6f871c8..8a09d80 100644
--- a/configs/qemu-riscv32_smode_defconfig
+++ b/configs/qemu-riscv32_smode_defconfig
@@ -1,6 +1,5 @@
CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0x800000
-CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_ENV_SIZE=0x20000
@@ -17,7 +16,10 @@
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
# CONFIG_CMD_MII is not set
+CONFIG_CMD_SPAWN=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_SYS_MAX_FLASH_BANKS=2
+CONFIG_UTHREAD=y
+CONFIG_UNIT_TEST=y
diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig
index 9906f8b..c4b6d57 100644
--- a/configs/qemu-riscv32_spl_defconfig
+++ b/configs/qemu-riscv32_spl_defconfig
@@ -1,6 +1,5 @@
CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0x800000
-CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_ENV_SIZE=0x20000
@@ -26,3 +25,4 @@
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_SYS_MAX_FLASH_BANKS=2
# CONFIG_BINMAN_FDT is not set
+CONFIG_UNIT_TEST=y
diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig
index cdd511b..6b2fed4 100644
--- a/configs/qemu-riscv64_defconfig
+++ b/configs/qemu-riscv64_defconfig
@@ -1,6 +1,5 @@
CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0x800000
-CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_ENV_SIZE=0x20000
@@ -16,7 +15,10 @@
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
# CONFIG_CMD_MII is not set
+CONFIG_CMD_SPAWN=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_SYS_MAX_FLASH_BANKS=2
+CONFIG_UTHREAD=y
+CONFIG_UNIT_TEST=y
diff --git a/configs/qemu-riscv64_smode_acpi_defconfig b/configs/qemu-riscv64_smode_acpi_defconfig
new file mode 100644
index 0000000..e78e5ff
--- /dev/null
+++ b/configs/qemu-riscv64_smode_acpi_defconfig
@@ -0,0 +1,2 @@
+#include <configs/qemu-riscv64_smode_defconfig>
+#include <board/emulation/configs/acpi.config>
diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig
index 2f62f17..95f24ac 100644
--- a/configs/qemu-riscv64_smode_defconfig
+++ b/configs/qemu-riscv64_smode_defconfig
@@ -1,6 +1,5 @@
CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0x800000
-CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_ENV_SIZE=0x20000
@@ -19,7 +18,10 @@
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
# CONFIG_CMD_MII is not set
+CONFIG_CMD_SPAWN=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_SYS_MAX_FLASH_BANKS=2
+CONFIG_UTHREAD=y
+CONFIG_UNIT_TEST=y
diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig
index 27e092b..d2b0aec 100644
--- a/configs/qemu-riscv64_spl_defconfig
+++ b/configs/qemu-riscv64_spl_defconfig
@@ -1,6 +1,5 @@
CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0x800000
-CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_ENV_SIZE=0x20000
@@ -25,3 +24,4 @@
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_SYS_MAX_FLASH_BANKS=2
# CONFIG_BINMAN_FDT is not set
+CONFIG_UNIT_TEST=y
diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig
index 58b1fbf..47075dc 100644
--- a/configs/qemu-x86_64_defconfig
+++ b/configs/qemu-x86_64_defconfig
@@ -93,3 +93,4 @@
CONFIG_GENERATE_ACPI_TABLE=y
CONFIG_CMD_DHRYSTONE=y
# CONFIG_GZIP is not set
+CONFIG_UNIT_TEST=y
diff --git a/configs/qemu_arm64_acpi_defconfig b/configs/qemu_arm64_acpi_defconfig
new file mode 100644
index 0000000..f85f291
--- /dev/null
+++ b/configs/qemu_arm64_acpi_defconfig
@@ -0,0 +1,2 @@
+#include <configs/qemu_arm64_defconfig>
+#include <board/emulation/configs/acpi.config>
diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig
index 03028c7..b1371d4 100644
--- a/configs/qemu_arm64_defconfig
+++ b/configs/qemu_arm64_defconfig
@@ -3,7 +3,6 @@
CONFIG_ARCH_QEMU=y
CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_BLOBLIST_SIZE_RELOC=0x2000
-CONFIG_NR_DRAM_BANKS=1
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40200000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SECT_SIZE=0x40000
@@ -38,6 +37,7 @@
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TPM=y
CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_SPAWN=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
@@ -76,3 +76,5 @@
CONFIG_TPM=y
CONFIG_TPM_PCR_ALLOCATE=y
CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE=y
+CONFIG_UTHREAD=y
+CONFIG_UNIT_TEST=y
diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig
index e09f54e..97d2f2f 100644
--- a/configs/qemu_arm_defconfig
+++ b/configs/qemu_arm_defconfig
@@ -3,7 +3,6 @@
CONFIG_ARCH_QEMU=y
CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_BLOBLIST_SIZE_RELOC=0x2000
-CONFIG_NR_DRAM_BANKS=1
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40200000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SECT_SIZE=0x40000
@@ -36,6 +35,7 @@
CONFIG_CMD_PCI=y
CONFIG_CMD_TPM=y
CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_SPAWN=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
@@ -68,4 +68,5 @@
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_PCI=y
CONFIG_TPM=y
+CONFIG_UTHREAD=y
CONFIG_UNIT_TEST=y
diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig
index 0c9f619..e90773f 100644
--- a/configs/r7-tv-dongle_defconfig
+++ b/configs/r7-tv-dongle_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=384
-CONFIG_USB1_VBUS_PIN="PG13"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/radxa-e20c-rk3528_defconfig b/configs/radxa-e20c-rk3528_defconfig
new file mode 100644
index 0000000..08f3a13
--- /dev/null
+++ b/configs/radxa-e20c-rk3528_defconfig
@@ -0,0 +1,56 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3528-radxa-e20c"
+CONFIG_ROCKCHIP_RK3528=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART_BASE=0xFF9F0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3528-radxa-e20c.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MISC=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RNG=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig
index 324581b..b6b3d3e 100644
--- a/configs/ringneck-px30_defconfig
+++ b/configs/ringneck-px30_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rockchip/px30-ringneck-haikou"
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_PX30=y
# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
diff --git a/configs/roc-pc-rk3576_defconfig b/configs/roc-pc-rk3576_defconfig
new file mode 100644
index 0000000..af2c102
--- /dev/null
+++ b/configs/roc-pc-rk3576_defconfig
@@ -0,0 +1,45 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-roc-pc"
+CONFIG_ROCKCHIP_RK3576=y
+CONFIG_TARGET_ROC_PC_RK3576=y
+CONFIG_SYS_LOAD_ADDR=0x40c00800
+CONFIG_DEBUG_UART_BASE=0x2AD40000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-roc-pc.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index 1236ce4..23df4c3 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -99,6 +99,7 @@
CONFIG_CMD_CRAMFS=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_SPAWN=y
CONFIG_MAC_PARTITION=y
CONFIG_AMIGA_PARTITION=y
CONFIG_OF_CONTROL=y
@@ -256,6 +257,8 @@
CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y
CONFIG_I2C_EDID=y
CONFIG_VIDEO_SANDBOX_SDL=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_VIDEO_BRIDGE_LVDS_CODEC=y
CONFIG_OSD=y
CONFIG_SANDBOX_OSD=y
CONFIG_BMP_16BPP=y
@@ -273,6 +276,7 @@
CONFIG_ERRNO_STR=y
CONFIG_GETOPT=y
CONFIG_TEST_FDTDEC=y
+CONFIG_UTHREAD=y
CONFIG_UNIT_TEST=y
CONFIG_UT_TIME=y
CONFIG_UT_DM=y
diff --git a/configs/sandbox64_lwip_defconfig b/configs/sandbox64_lwip_defconfig
new file mode 100644
index 0000000..0e92728
--- /dev/null
+++ b/configs/sandbox64_lwip_defconfig
@@ -0,0 +1,5 @@
+#include <configs/sandbox64_defconfig>
+
+CONFIG_SANDBOX=y
+
+CONFIG_NET_LWIP=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 87f21fd..c4b1b81 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -143,6 +143,7 @@
CONFIG_CMD_SQUASHFS=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_STACKPROTECTOR_TEST=y
+CONFIG_CMD_SPAWN=y
CONFIG_MAC_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIVE=y
@@ -364,6 +365,7 @@
CONFIG_ERRNO_STR=y
CONFIG_GETOPT=y
CONFIG_TEST_FDTDEC=y
+CONFIG_UTHREAD=y
CONFIG_UNIT_TEST=y
CONFIG_UT_TIME=y
CONFIG_UT_DM=y
diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig
index 563093d..67c0ed7 100644
--- a/configs/sandbox_flattree_defconfig
+++ b/configs/sandbox_flattree_defconfig
@@ -220,6 +220,8 @@
CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y
CONFIG_I2C_EDID=y
CONFIG_VIDEO_SANDBOX_SDL=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_VIDEO_BRIDGE_LVDS_CODEC=y
CONFIG_OSD=y
CONFIG_SANDBOX_OSD=y
CONFIG_BMP_16BPP=y
diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig
index eeb911a..21375f2 100644
--- a/configs/seaboard_defconfig
+++ b/configs/seaboard_defconfig
@@ -60,5 +60,5 @@
CONFIG_USB_ETHER_ASIX=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
-CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_TEGRA=y
CONFIG_CONSOLE_SCROLL_LINES=10
diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig
index 8f327e5f..4ac0a5d 100644
--- a/configs/socfpga_agilex5_defconfig
+++ b/configs/socfpga_agilex5_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_TEXT_BASE=0x80200000
+CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80300000
@@ -31,6 +32,8 @@
CONFIG_BOOTARGS="console=ttyS0,115200 initrd=0x90000000 root=/dev/ram0 rw init=/sbin/init ramdisk_size=10000000 earlycon panic=-1 nosmp kvm-arm.mode=nvhe"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BLOBLIST=y
+CONFIG_BLOBLIST_FIXED=y
+CONFIG_BLOBLIST_ADDR=0x7e000
CONFIG_BLOBLIST_SIZE=0x1000
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_HANDOFF=y
@@ -73,6 +76,8 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_ALTERA_SDRAM=y
+CONFIG_GPIO_HOG=y
+CONFIG_SPL_GPIO_HOG=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
@@ -82,6 +87,7 @@
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_MARVELL=y
CONFIG_DWC_ETH_XGMAC=y
CONFIG_RGMII=y
CONFIG_SYS_NS16550_MEM32=y
diff --git a/configs/socfpga_agilex5_vab_defconfig b/configs/socfpga_agilex5_vab_defconfig
new file mode 100644
index 0000000..a5f4b33
--- /dev/null
+++ b/configs/socfpga_agilex5_vab_defconfig
@@ -0,0 +1,3 @@
+#include <configs/socfpga_agilex5_defconfig>
+
+CONFIG_SOCFPGA_SECURE_VAB_AUTH=y
diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index 6a5b247..e145ced 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -80,7 +80,7 @@
CONFIG_CMD_WGET=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_OF_BOARD=y
-CONFIG_OF_LIST="starfive/jh7110-milkv-mars starfive/jh7110-pine64-star64 starfive/jh7110-starfive-visionfive-2-v1.2a starfive/jh7110-starfive-visionfive-2-v1.3b"
+CONFIG_OF_LIST="starfive/jh7110-deepcomputing-fml13v01 starfive/jh7110-milkv-mars starfive/jh7110-pine64-star64 starfive/jh7110-starfive-visionfive-2-v1.2a starfive/jh7110-starfive-visionfive-2-v1.3b"
CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig
index 1e5190d..582b5f3 100644
--- a/configs/stih410-b2260_defconfig
+++ b/configs/stih410-b2260_defconfig
@@ -8,7 +8,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7bdfff10
CONFIG_ENV_SIZE=0x4000
-CONFIG_DEFAULT_DEVICE_TREE="stih410-b2260"
+CONFIG_DEFAULT_DEVICE_TREE="st/stih410-b2260"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_SYS_LOAD_ADDR=0x40000000
@@ -31,6 +31,7 @@
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_ISO_PARTITION is not set
CONFIG_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
diff --git a/configs/stm32746g-eval_defconfig b/configs/stm32746g-eval_defconfig
index bd3a48b..c95cb60 100644
--- a/configs/stm32746g-eval_defconfig
+++ b/configs/stm32746g-eval_defconfig
@@ -6,7 +6,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000
CONFIG_ENV_SIZE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="stm32746g-eval"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32746g-eval"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SYS_LOAD_ADDR=0x8008000
@@ -20,6 +20,7 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
CONFIG_SYS_PBSIZE=1050
+CONFIG_DEFAULT_FDT_FILE="stm32746g-eval"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CMD_GPT=y
diff --git a/configs/stm32746g-eval_spl_defconfig b/configs/stm32746g-eval_spl_defconfig
index d47d059..8a0b1e2 100644
--- a/configs/stm32746g-eval_spl_defconfig
+++ b/configs/stm32746g-eval_spl_defconfig
@@ -9,7 +9,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000
CONFIG_ENV_SIZE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="stm32746g-eval"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32746g-eval"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_SERIAL=y
@@ -28,6 +28,7 @@
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
+CONFIG_DEFAULT_FDT_FILE="stm32746g-eval"
CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_PAD_TO=0x9000
diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig
index 7788933..59416cb 100644
--- a/configs/stm32f429-discovery_defconfig
+++ b/configs/stm32f429-discovery_defconfig
@@ -7,7 +7,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10010000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="stm32f429-disco"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32f429-disco"
CONFIG_SYS_LOAD_ADDR=0x90400000
CONFIG_STM32F4=y
CONFIG_TARGET_STM32F429_DISCOVERY=y
diff --git a/configs/stm32f429-evaluation_defconfig b/configs/stm32f429-evaluation_defconfig
index 2fa8dc9..5747187 100644
--- a/configs/stm32f429-evaluation_defconfig
+++ b/configs/stm32f429-evaluation_defconfig
@@ -6,7 +6,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10010000
CONFIG_ENV_SIZE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="stm32429i-eval"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32429i-eval"
CONFIG_SYS_LOAD_ADDR=0x400000
CONFIG_STM32F4=y
CONFIG_TARGET_STM32F429_EVALUATION=y
diff --git a/configs/stm32f469-discovery_defconfig b/configs/stm32f469-discovery_defconfig
index b014476..80e15c4 100644
--- a/configs/stm32f469-discovery_defconfig
+++ b/configs/stm32f469-discovery_defconfig
@@ -6,7 +6,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10010000
CONFIG_ENV_SIZE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="stm32f469-disco"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32f469-disco"
CONFIG_SYS_LOAD_ADDR=0x400000
CONFIG_STM32F4=y
CONFIG_TARGET_STM32F469_DISCOVERY=y
diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
index f6fbf83..2d18d77 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -6,7 +6,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000
CONFIG_ENV_SIZE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32f746-disco"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SYS_LOAD_ADDR=0x8008000
@@ -19,6 +19,7 @@
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
+CONFIG_DEFAULT_FDT_FILE="stm32f746-disco"
CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="U-Boot > "
diff --git a/configs/stm32f746-disco_spl_defconfig b/configs/stm32f746-disco_spl_defconfig
index dcf077d..8a8f506 100644
--- a/configs/stm32f746-disco_spl_defconfig
+++ b/configs/stm32f746-disco_spl_defconfig
@@ -9,7 +9,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000
CONFIG_ENV_SIZE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32f746-disco"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_SERIAL=y
@@ -28,6 +28,7 @@
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
+CONFIG_DEFAULT_FDT_FILE="stm32f746-disco"
CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_PAD_TO=0x9000
diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig
index 9edda0e..0f145f2 100644
--- a/configs/stm32f769-disco_defconfig
+++ b/configs/stm32f769-disco_defconfig
@@ -6,7 +6,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000
CONFIG_ENV_SIZE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="stm32f769-disco"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32f769-disco"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SYS_LOAD_ADDR=0x8008000
@@ -19,6 +19,7 @@
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySTM0,115200n8 earlyprintk consoleblank=0 ignore_loglevel"
+CONFIG_DEFAULT_FDT_FILE="stm32f769-disco"
CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_CYCLIC_MAX_CPU_TIME_US=8000
@@ -52,6 +53,7 @@
CONFIG_MII=y
# CONFIG_PINCTRL_FULL is not set
CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
diff --git a/configs/stm32f769-disco_spl_defconfig b/configs/stm32f769-disco_spl_defconfig
index 7d4bda4..6a3cdd4 100644
--- a/configs/stm32f769-disco_spl_defconfig
+++ b/configs/stm32f769-disco_spl_defconfig
@@ -9,7 +9,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000
CONFIG_ENV_SIZE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="stm32f769-disco"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32f769-disco"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_SERIAL=y
@@ -28,6 +28,7 @@
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
+CONFIG_DEFAULT_FDT_FILE="stm32f769-disco"
CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_CYCLIC_MAX_CPU_TIME_US=8000
@@ -75,6 +76,7 @@
# CONFIG_PINCTRL_FULL is not set
CONFIG_SPL_PINCTRL=y
CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPL_RAM=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_SPI=y
diff --git a/configs/stm32h743-disco_defconfig b/configs/stm32h743-disco_defconfig
index 40fc938..a674a20 100644
--- a/configs/stm32h743-disco_defconfig
+++ b/configs/stm32h743-disco_defconfig
@@ -6,7 +6,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x24040000
CONFIG_ENV_SIZE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="stm32h743i-disco"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32h743i-disco"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_LOAD_ADDR=0xd0400000
CONFIG_STM32H7=y
diff --git a/configs/stm32h743-eval_defconfig b/configs/stm32h743-eval_defconfig
index 953e67e..d63e721 100644
--- a/configs/stm32h743-eval_defconfig
+++ b/configs/stm32h743-eval_defconfig
@@ -6,7 +6,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x24040000
CONFIG_ENV_SIZE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="stm32h743i-eval"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32h743i-eval"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_LOAD_ADDR=0xd0400000
CONFIG_STM32H7=y
diff --git a/configs/stm32h750-art-pi_defconfig b/configs/stm32h750-art-pi_defconfig
index 4ca2d30..a92a57d 100644
--- a/configs/stm32h750-art-pi_defconfig
+++ b/configs/stm32h750-art-pi_defconfig
@@ -6,7 +6,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x24040000
CONFIG_ENV_SIZE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="stm32h750i-art-pi"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32h750i-art-pi"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_LOAD_ADDR=0xc1800000
CONFIG_STM32H7=y
diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig
index 4c6a7f8..530f6aa 100644
--- a/configs/stm32mp13_defconfig
+++ b/configs/stm32mp13_defconfig
@@ -4,7 +4,7 @@
CONFIG_SYS_MALLOC_F_LEN=0x180000
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0400000
CONFIG_ENV_OFFSET=0x900000
-CONFIG_DEFAULT_DEVICE_TREE="stm32mp135f-dk"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp135f-dk"
CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_STM32MP13X=y
diff --git a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig
index 28a5d93..fc095ac 100644
--- a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig
+++ b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig
@@ -4,7 +4,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
CONFIG_ENV_OFFSET=0x280000
-CONFIG_DEFAULT_DEVICE_TREE="stm32mp157a-icore-stm32mp1-ctouch2"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157a-icore-stm32mp1-ctouch2"
CONFIG_SPL_MMC=y
CONFIG_SPL_STACK=0x30000000
CONFIG_SPL_TEXT_BASE=0x2FFC2500
diff --git a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig
index efac476..b243c45 100644
--- a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig
+++ b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig
@@ -4,7 +4,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
CONFIG_ENV_OFFSET=0x280000
-CONFIG_DEFAULT_DEVICE_TREE="stm32mp157a-icore-stm32mp1-edimm2.2"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157a-icore-stm32mp1-edimm2.2"
CONFIG_SPL_MMC=y
CONFIG_SPL_STACK=0x30000000
CONFIG_SPL_TEXT_BASE=0x2FFC2500
diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig
index f9f55d1..e635c726 100644
--- a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig
+++ b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig
@@ -4,7 +4,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
CONFIG_ENV_OFFSET=0x280000
-CONFIG_DEFAULT_DEVICE_TREE="stm32mp157a-microgea-stm32mp1-microdev2.0-of7"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157a-microgea-stm32mp1-microdev2.0-of7"
CONFIG_SPL_MMC=y
CONFIG_SPL_STACK=0x30000000
CONFIG_SPL_TEXT_BASE=0x2FFC2500
diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig
index d573235..9e7849f 100644
--- a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig
+++ b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig
@@ -4,7 +4,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
CONFIG_ENV_OFFSET=0x280000
-CONFIG_DEFAULT_DEVICE_TREE="stm32mp157a-microgea-stm32mp1-microdev2.0"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157a-microgea-stm32mp1-microdev2.0"
CONFIG_SPL_MMC=y
CONFIG_SPL_STACK=0x30000000
CONFIG_SPL_TEXT_BASE=0x2FFC2500
diff --git a/configs/stm32mp15-odyssey_defconfig b/configs/stm32mp15-odyssey_defconfig
new file mode 100644
index 0000000..be8d9ae
--- /dev/null
+++ b/configs/stm32mp15-odyssey_defconfig
@@ -0,0 +1,172 @@
+CONFIG_ARM=y
+CONFIG_ARCH_STM32MP=y
+CONFIG_TFABOOT=y
+CONFIG_SYS_MALLOC_F_LEN=0x80000
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
+CONFIG_ENV_OFFSET=0x900000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-odyssey"
+CONFIG_DDR_CACHEABLE_SIZE=0x8000000
+CONFIG_CMD_STM32KEY=y
+CONFIG_TYPEC_STUSB160X=y
+CONFIG_TARGET_ST_STM32MP15X=y
+CONFIG_ENV_OFFSET_REDUND=0x940000
+CONFIG_CMD_STM32PROG=y
+# CONFIG_ARMV7_NONSEC is not set
+CONFIG_SYS_LOAD_ADDR=0xc2000000
+CONFIG_SYS_MEMTEST_START=0xc0000000
+CONFIG_SYS_MEMTEST_END=0xc4000000
+CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=1
+CONFIG_FDT_SIMPLEFB=y
+CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
+CONFIG_SYS_PBSIZE=1050
+CONFIG_SYS_PROMPT="STM32MP> "
+CONFIG_CMD_ADTIMG=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_UNZIP=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SYS_DISABLE_AUTOLOAD=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_RNG=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_LOG=y
+CONFIG_CMD_UBI=y
+CONFIG_OF_LIVE=y
+# CONFIG_OF_UPSTREAM is not set
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_IS_IN_UBI=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_ENV_UBI_PART="UBI"
+CONFIG_ENV_UBI_VOLUME="uboot_config"
+CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=-1
+CONFIG_ENV_MMC_USE_DT=y
+CONFIG_TFTP_TSIZE=y
+CONFIG_USE_SERVERIP=y
+CONFIG_SERVERIP="192.168.1.1"
+CONFIG_STM32_ADC=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_CLK_SCMI=y
+CONFIG_SET_DFU_ALT_INFO=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0xC0000000
+CONFIG_FASTBOOT_BUF_SIZE=0x02000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
+CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc1boot0"
+CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc1boot1"
+CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
+CONFIG_FASTBOOT_MMC_USER_NAME="mmc1"
+CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y
+CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y
+CONFIG_GPIO_HOG=y
+CONFIG_DM_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_STM32=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_STM32F7=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_STM32_FMC2_EBI=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_STM32_SDMMC2=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_STM32_FMC2=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_PHY=y
+CONFIG_PHY_STM32_USBPHYC=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_STMFX=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_STPMIC1=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_REGULATOR_STM32_VREFBUF=y
+CONFIG_DM_REGULATOR_STPMIC1=y
+CONFIG_DM_REGULATOR_SCMI=y
+CONFIG_REMOTEPROC_STM32_COPRO=y
+CONFIG_RESET_SCMI=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_STM32=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_STM32=y
+CONFIG_SERIAL_RX_BUFFER=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_STM32_QSPI=y
+CONFIG_STM32_SPI=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+# CONFIG_OPTEE_TA_AVB is not set
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_ONBOARD_HUB=y
+CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2000
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0483
+CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y
+CONFIG_VIDEO_STM32=y
+CONFIG_VIDEO_STM32_DSI=y
+CONFIG_VIDEO_STM32_MAX_XRES=1280
+CONFIG_VIDEO_STM32_MAX_YRES=800
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_WDT=y
+CONFIG_WDT_STM32MP=y
+# CONFIG_BINMAN_FDT is not set
+CONFIG_ERRNO_STR=y
+# CONFIG_LMB_USE_MAX_REGIONS is not set
+CONFIG_LMB_MEMORY_REGIONS=2
+CONFIG_LMB_RESERVED_REGIONS=16
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
index cda17e5..e3090ec 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -6,7 +6,7 @@
CONFIG_ENV_OFFSET=0x280000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157c-ev1"
CONFIG_SPL_MMC=y
CONFIG_SPL_STACK=0x30000000
CONFIG_SPL_TEXT_BASE=0x2FFC2500
@@ -81,6 +81,8 @@
CONFIG_CMD_UBI=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_OF_LIVE=y
+CONFIG_OF_UPSTREAM_BUILD_VENDOR=y
+CONFIG_OF_UPSTREAM_VENDOR="st"
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig
index d31349e..5ddec18 100644
--- a/configs/stm32mp15_defconfig
+++ b/configs/stm32mp15_defconfig
@@ -5,7 +5,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
CONFIG_ENV_OFFSET=0x900000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157c-ev1"
CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_DDR_CACHEABLE_SIZE=0x8000000
@@ -54,6 +54,8 @@
CONFIG_CMD_LOG=y
CONFIG_CMD_UBI=y
CONFIG_OF_LIVE=y
+CONFIG_OF_UPSTREAM_BUILD_VENDOR=y
+CONFIG_OF_UPSTREAM_VENDOR="st"
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig
index 1f807f3..f0e6b64 100644
--- a/configs/stm32mp15_trusted_defconfig
+++ b/configs/stm32mp15_trusted_defconfig
@@ -5,7 +5,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
CONFIG_ENV_OFFSET=0x280000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157c-ev1"
CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_DDR_CACHEABLE_SIZE=0x10000000
@@ -55,6 +55,8 @@
CONFIG_CMD_LOG=y
CONFIG_CMD_UBI=y
CONFIG_OF_LIVE=y
+CONFIG_OF_UPSTREAM_BUILD_VENDOR=y
+CONFIG_OF_UPSTREAM_VENDOR="st"
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
diff --git a/configs/stm32mp25_defconfig b/configs/stm32mp25_defconfig
index 4538ff0..317a6d5 100644
--- a/configs/stm32mp25_defconfig
+++ b/configs/stm32mp25_defconfig
@@ -2,17 +2,23 @@
CONFIG_ARCH_STM32MP=y
CONFIG_SYS_MALLOC_F_LEN=0x400000
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x90000000
-CONFIG_DEFAULT_DEVICE_TREE="stm32mp257f-ev1"
+CONFIG_ENV_OFFSET=0x900000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp257f-ev1"
CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_SYS_LOAD_ADDR=0x84000000
CONFIG_STM32MP25X=y
CONFIG_DDR_CACHEABLE_SIZE=0x10000000
+CONFIG_ENV_OFFSET_REDUND=0x940000
CONFIG_TARGET_ST_STM32MP25X=y
CONFIG_SYS_MEMTEST_START=0x84000000
CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_API=y
+CONFIG_SYS_MMC_MAX_DEVICE=3
CONFIG_FIT=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
-CONFIG_LAST_STAGE_INIT=y
+CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_SYS_PROMPT="STM32MP> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
@@ -24,19 +30,38 @@
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADB is not set
+CONFIG_CMD_MMC=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_RNG=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_LOG=y
+CONFIG_CMD_UBI=y
CONFIG_OF_LIVE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_IS_IN_UBI=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_ENV_UBI_PART="UBI"
+CONFIG_ENV_UBI_VOLUME="uboot_config"
+CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r"
+CONFIG_SYS_MMC_ENV_DEV=-1
CONFIG_NO_NET=y
CONFIG_SYS_64BIT_LBA=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
CONFIG_GPIO_HOG=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_STM32F7=y
-# CONFIG_MMC is not set
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_STM32_SDMMC2=y
+CONFIG_MTD=y
+CONFIG_USE_SYS_MAX_FLASH_BANKS=y
+CONFIG_SPI_FLASH=y
CONFIG_PINCONF=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
@@ -44,8 +69,11 @@
# CONFIG_STM32MP1_DDR is not set
CONFIG_DM_RNG=y
CONFIG_SERIAL_RX_BUFFER=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
# CONFIG_OPTEE_TA_AVB is not set
CONFIG_WDT=y
CONFIG_WDT_STM32MP=y
CONFIG_WDT_ARM_SMC=y
+# CONFIG_UBIFS_SILENCE_DEBUG_DUMP is not set
CONFIG_ERRNO_STR=y
diff --git a/configs/sun8i_a23_evb_defconfig b/configs/sun8i_a23_evb_defconfig
index a3b1d76..3bafc4d 100644
--- a/configs/sun8i_a23_evb_defconfig
+++ b/configs/sun8i_a23_evb_defconfig
@@ -5,9 +5,6 @@
CONFIG_MACH_SUN8I_A23=y
CONFIG_DRAM_CLK=552
CONFIG_DRAM_ZQ=63351
-CONFIG_USB0_VBUS_PIN="axp_drivebus"
-CONFIG_USB0_VBUS_DET="axp_vbus_detect"
-CONFIG_USB1_VBUS_PIN="PH7"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONS_INDEX=5
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/surface-rt_defconfig b/configs/surface-rt_defconfig
index 24fca75..da19b34 100644
--- a/configs/surface-rt_defconfig
+++ b/configs/surface-rt_defconfig
@@ -79,4 +79,4 @@
CONFIG_CI_UDC=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_LOGO is not set
-CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_TEGRA=y
diff --git a/configs/tanix_tx1_defconfig b/configs/tanix_tx1_defconfig
index 28cf951..00e34dc 100644
--- a/configs/tanix_tx1_defconfig
+++ b/configs/tanix_tx1_defconfig
@@ -14,11 +14,13 @@
CONFIG_SUNXI_DRAM_H616_LPDDR3=y
CONFIG_R_I2C_ENABLE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_SPL_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_AXP313_POWER=y
CONFIG_AXP_DCDC3_VOLT=1200
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/tbs_a711_defconfig b/configs/tbs_a711_defconfig
index 9a70b6b..e56bbab 100644
--- a/configs/tbs_a711_defconfig
+++ b/configs/tbs_a711_defconfig
@@ -8,11 +8,10 @@
CONFIG_DRAM_ZQ=15355
CONFIG_DRAM_ODT_EN=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PH11"
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DCDC5_VOLT=1200
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/tec_defconfig b/configs/tec_defconfig
index 2f68610..7cb13f9 100644
--- a/configs/tec_defconfig
+++ b/configs/tec_defconfig
@@ -53,4 +53,4 @@
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
-CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_TEGRA=y
diff --git a/configs/tegratab_defconfig b/configs/tegratab_defconfig
new file mode 100644
index 0000000..f0f8321
--- /dev/null
+++ b/configs/tegratab_defconfig
@@ -0,0 +1,84 @@
+CONFIG_ARM=y
+CONFIG_ARCH_TEGRA=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x80110000
+CONFIG_SYS_MALLOC_LEN=0x2500000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SOURCE_FILE="tegratab"
+CONFIG_ENV_SIZE=0x3000
+CONFIG_ENV_OFFSET=0xFFFFD000
+CONFIG_DEFAULT_DEVICE_TREE="tegra114-nvidia-tegratab"
+CONFIG_SPL_STACK=0x800ffffc
+CONFIG_SPL_TEXT_BASE=0x80108000
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_TEGRA114=y
+CONFIG_TARGET_TEGRATAB=y
+CONFIG_TEGRA_ENABLE_UARTD=y
+CONFIG_BUTTON_CMD=y
+CONFIG_BOOTDELAY=0
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="bootflow scan; echo 'Boot configuration not found... Power off in 3 sec'; sleep 3; poweroff"
+CONFIG_SYS_PBSIZE=2086
+CONFIG_SPL_FOOTPRINT_LIMIT=y
+CONFIG_SPL_MAX_FOOTPRINT=0x8000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
+CONFIG_SYS_PROMPT="Tegra114 (TegraTab) # "
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
+CONFIG_CMD_BOOTMENU=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_UMS_ABORT_KEYED=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PAUSE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_TEGRA_PARTITION=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_BUTTON=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x91000000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_PALMAS_GPIO=y
+CONFIG_SYS_I2C_TEGRA=y
+CONFIG_BUTTON_KEYBOARD=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_PALMAS=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_PALMAS=y
+CONFIG_PWM_TEGRA=y
+CONFIG_SYS_NS16550=y
+CONFIG_SYSRESET_PALMAS=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_LOGO is not set
+CONFIG_VIDEO_LCD_LG_LD070WX3=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_VIDEO_DSI_TEGRA=y
diff --git a/configs/teres_i_defconfig b/configs/teres_i_defconfig
index b9b22e7..6a9261e 100644
--- a/configs/teres_i_defconfig
+++ b/configs/teres_i_defconfig
@@ -6,7 +6,6 @@
CONFIG_DRAM_CLK=552
CONFIG_DRAM_ZQ=3881949
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB1_VBUS_PIN="PL7"
CONFIG_I2C0_ENABLE=y
CONFIG_PREBOOT="setenv usb_pgood_delay 2000; usb start"
CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/tf701t_defconfig b/configs/tf701t_defconfig
new file mode 100644
index 0000000..69bc945
--- /dev/null
+++ b/configs/tf701t_defconfig
@@ -0,0 +1,89 @@
+CONFIG_ARM=y
+CONFIG_ARCH_TEGRA=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x80110000
+CONFIG_SYS_MALLOC_LEN=0x2500000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SOURCE_FILE="transformer-t114"
+CONFIG_ENV_SIZE=0x3000
+CONFIG_ENV_OFFSET=0xFFFFD000
+CONFIG_DEFAULT_DEVICE_TREE="tegra114-asus-tf701t"
+CONFIG_SPL_STACK=0x800ffffc
+CONFIG_SPL_TEXT_BASE=0x80108000
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_TEGRA114=y
+CONFIG_TARGET_TRANSFORMER_T114=y
+CONFIG_TEGRA_ENABLE_UARTD=y
+CONFIG_BUTTON_CMD=y
+CONFIG_BOOTDELAY=0
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="bootflow scan; echo 'Boot configuration not found... Power off in 3 sec'; sleep 3; poweroff"
+CONFIG_SYS_PBSIZE=2086
+CONFIG_SPL_FOOTPRINT_LIMIT=y
+CONFIG_SPL_MAX_FOOTPRINT=0x8000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
+CONFIG_SYS_PROMPT="Tegra114 (Transformer) # "
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
+CONFIG_CMD_BOOTMENU=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_UMS_ABORT_KEYED=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PAUSE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_TEGRA_PARTITION=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_BUTTON=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x91000000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_PALMAS_GPIO=y
+CONFIG_SYS_I2C_TEGRA=y
+CONFIG_BUTTON_KEYBOARD=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_PALMAS=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_PALMAS=y
+CONFIG_PWM_TEGRA=y
+CONFIG_SYS_NS16550=y
+CONFIG_SYSRESET_PALMAS=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="ASUS"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0b05
+CONFIG_USB_GADGET_PRODUCT_NUM=0x4daf
+CONFIG_CI_UDC=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_FONT_8X16 is not set
+CONFIG_VIDEO_FONT_16X32=y
+# CONFIG_VIDEO_LOGO is not set
+CONFIG_VIDEO_LCD_SHARP_LQ101R1SX01=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_VIDEO_DSI_TEGRA=y
diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig
index 6bfcaab..1be8d89 100644
--- a/configs/topic_miami_defconfig
+++ b/configs/topic_miami_defconfig
@@ -28,9 +28,9 @@
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=0
-CONFIG_BOOTCOMMAND="if mmcinfo; then if fatload mmc 0 0x1900000 ${bootscript}; then source 0x1900000; fi; fi; run $modeboot"
CONFIG_USE_PREBOOT=y
CONFIG_SYS_PBSIZE=2077
+# CONFIG_BOARD_LATE_INIT is not set
CONFIG_CLOCKS=y
CONFIG_SPL_MAX_SIZE=0x30000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
@@ -41,15 +41,25 @@
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SYS_PROMPT="zynq-uboot> "
CONFIG_SYS_MAXARGS=32
+# CONFIG_CMD_BOOTEFI is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_SPL is not set
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_THOR_RESET_OFF=y
+# CONFIG_CMD_SAVEENV is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DFU=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
+# CONFIG_CMD_EFICONFIG is not set
+CONFIG_CMD_SQUASHFS=y
+CONFIG_MTDIDS_DEFAULT="nor0=spi0.0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:0x100000(qspi-boot-bin),-(qspi-rootfs)"
+CONFIG_CMD_UBI=y
CONFIG_OF_EMBED=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
@@ -57,14 +67,18 @@
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_RAM=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x600000
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQPL=y
+CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_BLOCK=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_MTD_UBI_BEB_LIMIT=0
+CONFIG_UBI_BLOCK=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_ARM_DCC=y
CONFIG_ZYNQ_SERIAL=y
@@ -80,3 +94,4 @@
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_SYS_TIMER_COUNTS_DOWN=y
+CONFIG_LZ4=y
diff --git a/configs/toradex-smarc-imx8mp_defconfig b/configs/toradex-smarc-imx8mp_defconfig
new file mode 100644
index 0000000..7d44eda
--- /dev/null
+++ b/configs/toradex-smarc-imx8mp_defconfig
@@ -0,0 +1,184 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xFFFFDE00
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mp-toradex-smarc-dev"
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_TARGET_TORADEX_SMARC_IMX8MP=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
+CONFIG_SYS_MONITOR_LEN=524288
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK=0x960000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x98fc00
+CONFIG_SPL_BSS_MAX_SIZE=0x400
+CONFIG_SPL=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_SYS_LOAD_ADDR=0x48200000
+CONFIG_PCI=y
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTSTD_FULL=y
+# CONFIG_BOOTSTD_BOOTCOMMAND is not set
+CONFIG_BOOTDELAY=1
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="bootflow scan -b"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile imx8mp-toradex-smarc-dev.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2081
+CONFIG_LOG=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MAX_SIZE=0x26000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="SMARC iMX8MP # "
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_MD5SUM_VERIFY=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_BOOTCOUNT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_SYSBOOT=y
+CONFIG_CMD_UUID=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_SYS_MMC_ENV_PART=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="eth0"
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_IP_DEFRAG=y
+CONFIG_TFTP_BLOCKSIZE=4096
+CONFIG_SPL_DM=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ENV=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_FSL_CAAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x44200000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_GPIO_HOG=y
+CONFIG_SPL_GPIO_HOG=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_SPL_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_IMX=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PHY_IMX8M_PCIE=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR_PCA9450=y
+CONFIG_SPL_DM_REGULATOR_PCA9450=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_MX7 is not set
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Toradex"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
+CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
+CONFIG_IMX_WATCHDOG=y
+CONFIG_HEXDUMP=y
diff --git a/configs/transformer_t20_defconfig b/configs/transformer_t20_defconfig
index 50b5885..c934e1a 100644
--- a/configs/transformer_t20_defconfig
+++ b/configs/transformer_t20_defconfig
@@ -81,4 +81,4 @@
CONFIG_VIDEO=y
# CONFIG_VIDEO_LOGO is not set
# CONFIG_VIDEO_BPP8 is not set
-CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_TEGRA=y
diff --git a/configs/transformer_t30_defconfig b/configs/transformer_t30_defconfig
index 3e2db0c..828634d 100644
--- a/configs/transformer_t30_defconfig
+++ b/configs/transformer_t30_defconfig
@@ -93,5 +93,5 @@
CONFIG_VIDEO_BRIDGE=y
# CONFIG_VIDEO_LOGO is not set
CONFIG_VIDEO_BRIDGE_TOSHIBA_TC358768=y
-CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_TEGRA=y
CONFIG_VIDEO_HDMI_TEGRA=y
diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig
index c24fdca..3afa04d 100644
--- a/configs/ventana_defconfig
+++ b/configs/ventana_defconfig
@@ -53,5 +53,5 @@
CONFIG_USB_ETHER_ASIX=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
-CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_TEGRA=y
CONFIG_CONSOLE_SCROLL_LINES=10
diff --git a/configs/verdin-am62_a53_defconfig b/configs/verdin-am62_a53_defconfig
index ecd3284..4bdcb4b 100644
--- a/configs/verdin-am62_a53_defconfig
+++ b/configs/verdin-am62_a53_defconfig
@@ -20,7 +20,6 @@
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x80c80000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
diff --git a/configs/verdin-am62_r5_defconfig b/configs/verdin-am62_r5_defconfig
index 9ac4b53..f9580e6 100644
--- a/configs/verdin-am62_r5_defconfig
+++ b/configs/verdin-am62_r5_defconfig
@@ -17,7 +17,6 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x7000
-CONFIG_SPL_TEXT_BASE=0x43c00000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x43c3b000
CONFIG_SPL_BSS_MAX_SIZE=0x3000
diff --git a/configs/x3_t30_defconfig b/configs/x3_t30_defconfig
index e738bd2..4252526 100644
--- a/configs/x3_t30_defconfig
+++ b/configs/x3_t30_defconfig
@@ -87,4 +87,4 @@
# CONFIG_VIDEO_LOGO is not set
CONFIG_BACKLIGHT_LM3533=y
CONFIG_VIDEO_BRIDGE_SOLOMON_SSD2825=y
-CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_TEGRA=y
diff --git a/configs/x96_mate_defconfig b/configs/x96_mate_defconfig
index bd9b611..c062837 100644
--- a/configs/x96_mate_defconfig
+++ b/configs/x96_mate_defconfig
@@ -11,6 +11,7 @@
CONFIG_DRAM_SUNXI_TPR12=0xfedf7557
CONFIG_MACH_SUN50I_H616=y
CONFIG_SUNXI_DRAM_H616_DDR3_1333=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_R_I2C_ENABLE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig
index e1cdc18..af9ce49 100644
--- a/configs/xilinx_versal_mini_ospi_defconfig
+++ b/configs/xilinx_versal_mini_ospi_defconfig
@@ -7,7 +7,7 @@
CONFIG_SYS_MALLOC_F_LEN=0x500
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xFFFFFE00
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xFFFE1000
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_ENV_SIZE=0x80
# CONFIG_DM_GPIO is not set
diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig
index 1604b59..a82ccdc 100644
--- a/configs/xilinx_versal_net_virt_defconfig
+++ b/configs/xilinx_versal_net_virt_defconfig
@@ -74,6 +74,8 @@
CONFIG_CLK_VERSAL=y
CONFIG_DFU_RAM=y
CONFIG_ARM_FFA_TRANSPORT=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_VERSALPL=y
CONFIG_ZYNQ_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
@@ -121,7 +123,6 @@
CONFIG_RESET_ZYNQMP=y
CONFIG_ARM_DCC=y
CONFIG_PL01X_SERIAL=y
-CONFIG_XILINX_UARTLITE=y
CONFIG_SOC_DEVICE=y
CONFIG_SOC_XILINX_VERSAL_NET=y
CONFIG_SPI=y
diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig
index baa4b8e..ba4519c 100644
--- a/configs/xilinx_versal_virt_defconfig
+++ b/configs/xilinx_versal_virt_defconfig
@@ -133,7 +133,6 @@
CONFIG_RESET_ZYNQMP=y
CONFIG_ARM_DCC=y
CONFIG_PL01X_SERIAL=y
-CONFIG_XILINX_UARTLITE=y
CONFIG_SOC_XILINX_VERSAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig
index 1f8e8c3..ae79f10 100644
--- a/configs/xilinx_zynqmp_kria_defconfig
+++ b/configs/xilinx_zynqmp_kria_defconfig
@@ -187,7 +187,6 @@
CONFIG_RTC_ZYNQMP=y
CONFIG_SCSI=y
CONFIG_ARM_DCC=y
-CONFIG_XILINX_UARTLITE=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_SOC_XILINX_ZYNQMP=y
CONFIG_SPI=y
@@ -228,3 +227,4 @@
CONFIG_MBEDTLS_LIB=y
CONFIG_TPM=y
CONFIG_SPL_GZIP=y
+CONFIG_TOOLS_MKFWUMDATA=y
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index abd1e1b..29aa589 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -199,7 +199,6 @@
CONFIG_RTC_ZYNQMP=y
CONFIG_SCSI=y
CONFIG_ARM_DCC=y
-CONFIG_XILINX_UARTLITE=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_SOC_XILINX_ZYNQMP=y
CONFIG_SPI=y
diff --git a/doc/api/index.rst b/doc/api/index.rst
index a108718..506843ed 100644
--- a/doc/api/index.rst
+++ b/doc/api/index.rst
@@ -25,6 +25,8 @@
rng
sandbox
serial
+ setjmp
sysreset
timer
unicode
+ uthread
diff --git a/doc/api/setjmp.rst b/doc/api/setjmp.rst
new file mode 100644
index 0000000..c30e51c
--- /dev/null
+++ b/doc/api/setjmp.rst
@@ -0,0 +1,20 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+Long jump API
+=============
+
+.. kernel-doc:: include/setjmp.h
+ :doc: Overview
+
+.. kernel-doc:: include/setjmp.h
+ :internal:
+
+Example
+-------
+
+Here is an example showing how to use the a long jump functions and
+initjmp() in particular:
+
+.. literalinclude:: ../../test/lib/initjmp.c
+ :language: c
+ :linenos:
diff --git a/doc/api/uthread.rst b/doc/api/uthread.rst
new file mode 100644
index 0000000..8b25cc1
--- /dev/null
+++ b/doc/api/uthread.rst
@@ -0,0 +1,19 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+Uthread API
+===========
+
+.. kernel-doc:: include/uthread.h
+ :doc: Overview
+
+.. kernel-doc:: include/uthread.h
+ :internal:
+
+Example
+-------
+
+Here is an example of how to use this API:
+
+.. literalinclude:: ../../test/lib/uthread.c
+ :language: c
+ :linenos:
diff --git a/doc/arch/arm64.rst b/doc/arch/arm64.rst
index 19662be..d72200f 100644
--- a/doc/arch/arm64.rst
+++ b/doc/arch/arm64.rst
@@ -14,11 +14,11 @@
-----
1. U-Boot can run at any exception level it is entered in, it is
- recommened to enter it in EL3 if U-Boot takes some responsibilities of a
+ recommended to enter it in EL3 if U-Boot takes some responsibilities of a
classical firmware (like initial hardware setup, CPU errata workarounds
or SMP bringup). U-Boot can be entered in EL2 when its main purpose is
that of a boot loader. It can drop to lower exception levels before
- entering the OS. For ARMv8-R it is recommened to enter at S-EL1, as for this
+ entering the OS. For ARMv8-R it is recommended to enter at S-EL1, as for this
architecture there is no S-EL3.
2. U-Boot for arm64 is compiled with AArch64-gcc. AArch64-gcc
diff --git a/doc/board/asus/index.rst b/doc/board/asus/index.rst
index 2cac04c..a9ba7a5 100644
--- a/doc/board/asus/index.rst
+++ b/doc/board/asus/index.rst
@@ -9,3 +9,4 @@
grouper
transformer_t20
transformer_t30
+ transformer_t114
diff --git a/doc/board/asus/transformer_t114.rst b/doc/board/asus/transformer_t114.rst
new file mode 100644
index 0000000..3e42b5d
--- /dev/null
+++ b/doc/board/asus/transformer_t114.rst
@@ -0,0 +1,74 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for the ASUS Transformer device family
+=============================================
+
+Quick Start
+-----------
+
+- Build U-Boot
+- Boot U-Boot by loading it into RAM (coldboot)
+- Chainloading U-Boot from the vendor bootloader
+- Boot
+
+Build U-Boot
+------------
+
+U-Boot can be built in two forms: U-Boot with SPL, which is used for booting
+by loading directly into RAM and U-Boot without SPL, which can be flashed
+and chainloaded from the vendor bootloader.
+
+To build U-Boot with SPL proseed:
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=arm-none-eabi-
+ $ make tf701t_defconfig
+ $ make
+
+After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin``
+file, ready for cold booting by loading into RAM.
+
+To build U-Boot without SPL adjust tf701t_defconfig:
+
+.. code-block::
+
+ CONFIG_TEXT_BASE=0x80A00000
+ CONFIG_SKIP_LOWLEVEL_INIT=y
+ # CONFIG_OF_BOARD_SETUP is not set
+ CONFIG_TEGRA_SUPPORT_NON_SECURE=y
+
+After the build succeeds, you will obtain the final ``u-boot-dtb.bin`` file,
+ready for booting with fastboot boot or which can be further processed into
+a flashable boot.img.
+
+Boot U-Boot by loading it into RAM (coldboot)
+---------------------------------------------
+
+Done fairly simply by using fusee-tools (using run_bootloader.sh) and placing
+``u-boot-dtb-tegra.bin`` generated on the previous step into fusee-tools dir.
+This method requires constant access to the host PC or payloader and can fully
+eliminate influence of the vendor bootloader onto the boot process.
+
+.. code-block:: bash
+
+ $ ./run_bootloader.sh -s T114 -t ./bct/tf701t.bct
+
+Chainloading U-Boot from the vendor bootloader
+----------------------------------------------
+
+``u-boot-dtb.bin`` has to be further packed into Android boot image form,
+where ``u-boot-dtb.bin`` acts as kernel, while dtb and ramdisk parts should
+not be included. Then the generated boot image can be flashed into the /boot
+partition of the tablet using vendor bootloader's fastboot and will act as
+the bootloader of the last stage.
+
+Boot
+----
+In both cases after U-Boot obtains control it performs search of extlinux.conf
+first on the dock USB device is available, then on MicroSD card if available
+and lastly on eMMC. If none of the devices above are present, then the device
+is turned off.
+
+If during boot of U-Boot Volume Down button is pressed, the device will enter
+U-Boot bootmenu.
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 7ad1137..3c5a2c7 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -41,6 +41,8 @@
mediatek/index
microchip/index
microsoft/index
+ motorola/index
+ nvidia/index
nxp/index
openpiton/index
ouya/index
diff --git a/doc/board/motorola/index.rst b/doc/board/motorola/index.rst
new file mode 100644
index 0000000..9666ff2
--- /dev/null
+++ b/doc/board/motorola/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Motorola
+========
+
+.. toctree::
+ :maxdepth: 2
+
+ mot
diff --git a/doc/board/motorola/mot.rst b/doc/board/motorola/mot.rst
new file mode 100644
index 0000000..d0f89bc
--- /dev/null
+++ b/doc/board/motorola/mot.rst
@@ -0,0 +1,104 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for the Motorola Atrix 4G (MB860) and Droid X2 (MB870)
+=============================================================
+
+``DISCLAMER!`` Moving your device to use U-Boot assumes replacement of the
+vendor bootloader. Vendor Android firmwares will no longer be able to run on
+the device. This replacement IS reversible if you have backups.
+
+Quick Start
+-----------
+
+- Prerequisites
+- Build U-Boot
+- Process U-Boot
+- Flashing U-Boot into the eMMC
+- Boot
+- Self Upgrading
+
+Prerequisites
+-------------
+
+In order to work with RCM/APX mode, both devices require a factory cable which
+is made by routing 5V to the ID pin of a micro-USB cable (5v is applied to both
+ID and dedicated 5v). This way, the host PC can detect the device in RCM mode,
+and the device can operate without a battery.
+
+Build U-Boot
+------------
+
+Device support is implemented by applying config fragment to a generic
+board defconfig. Valid fragments are ``daytona.config`` and ``olympus.config``.
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=arm-none-eabi-
+ $ make mot_defconfig olympus.config # For Atrix 4G
+ $ make
+
+After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin``
+image, ready for further processing.
+
+Process U-Boot
+--------------
+
+``DISCLAMER!`` All questions related to the re-crypt work should be asked
+in re-crypt repo issues. NOT HERE!
+
+re-crypt is a tool that processes the ``u-boot-dtb-tegra.bin`` binary into form
+usable by device. This process is required only on the first installation or to
+recover the device in case of a failed update. You need to know your device
+individual SBK to continue.
+
+.. code-block:: bash
+
+ $ git clone https://gitlab.com/grate-driver/re-crypt.git
+ $ cd re-crypt # place your u-boot-dtb-tegra.bin here
+ $ ./re-crypt.py --dev olympus --sbk <your sbk> --split
+
+where SBK has next form ``0xXXXXXXXX`` ``0xXXXXXXXX`` ``0xXXXXXXXX`` ``0xXXXXXXXX``
+
+The script will produce ``bct.img`` and ``ebt.img`` ready to flash.
+
+Flashing U-Boot into the eMMC
+-----------------------------
+
+``DISCLAMER!`` All questions related to fusee-tools should be asked in the proper
+place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before!
+
+U-Boot pre-loaded into RAM acts the same as when it was booted "cold". Currently
+U-Boot supports bootmenu entry fastboot, which allows to write a processed copy
+of U-Boot permanently into eMMC.
+
+While pre-loading U-Boot, hold the ``volume down`` button which will trigger
+the bootmenu. There, select ``fastboot`` using the volume and power buttons.
+After, on host PC, do:
+
+.. code-block:: bash
+
+ $ fastboot flash 0.1 bct.img
+ $ fastboot flash 0.2 ebt.img
+ $ fastboot reboot
+
+Device will reboot.
+
+Boot
+----
+
+To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD and then on
+eMMC. Additionally, if the Volume Down button is pressed while booting, the
+device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC
+as mass storage, fastboot, reboot, reboot RCM, poweroff, enter U-Boot console
+and update bootloader (check the next chapter).
+
+Flashing ``repart-block.bin`` eliminates vendor restrictions on eMMC and allows
+the user to use/partition it in any way the user desires.
+
+Self Upgrading
+--------------
+
+Place your ``u-boot-dtb-tegra.bin`` on the first partition of the MicroSD card
+and insert it into the device. Enter bootmenu, choose update the bootloader
+option with the Power button and U-Boot should update itself. Once the process
+is completed, U-Boot will ask to press any button to reboot.
diff --git a/doc/board/nvidia/index.rst b/doc/board/nvidia/index.rst
new file mode 100644
index 0000000..7c10544
--- /dev/null
+++ b/doc/board/nvidia/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+NVIDIA
+======
+
+.. toctree::
+ :maxdepth: 2
+
+ tegratab
diff --git a/doc/board/nvidia/tegratab.rst b/doc/board/nvidia/tegratab.rst
new file mode 100644
index 0000000..c6d97ce
--- /dev/null
+++ b/doc/board/nvidia/tegratab.rst
@@ -0,0 +1,74 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for the Nvidia Tegra Note 7
+==================================
+
+Quick Start
+-----------
+
+- Build U-Boot
+- Boot U-Boot by loading it into RAM (coldboot)
+- Chainloading U-Boot from the vendor bootloader
+- Boot
+
+Build U-Boot
+------------
+
+U-Boot can be built in two forms: U-Boot with SPL, which is used for booting
+by loading directly into RAM and U-Boot without SPL, which can be flashed
+and chainloaded from the vendor bootloader.
+
+To build U-Boot with SPL proseed:
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=arm-none-eabi-
+ $ make tegratab_defconfig
+ $ make
+
+After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin``
+file, ready for cold booting by loading into RAM.
+
+To build U-Boot without SPL adjust tegratab_defconfig:
+
+.. code-block::
+
+ CONFIG_TEXT_BASE=0x80A00000
+ CONFIG_SKIP_LOWLEVEL_INIT=y
+ # CONFIG_OF_BOARD_SETUP is not set
+ CONFIG_TEGRA_SUPPORT_NON_SECURE=y
+
+After the build succeeds, you will obtain the final ``u-boot-dtb.bin`` file,
+ready for booting with fastboot boot or which can be further processed into
+a flashable boot.img.
+
+Boot U-Boot by loading it into RAM (coldboot)
+---------------------------------------------
+
+Done fairly simply by using fusee-tools (using run_bootloader.sh) and placing
+``u-boot-dtb-tegra.bin`` generated on the previous step into fusee-tools dir.
+This method requires constant access to the host PC or payloader and can fully
+eliminate influence of the vendor bootloader onto the boot process.
+
+.. code-block:: bash
+
+ $ ./run_bootloader.sh -s T114 -t ./bct/tegratab.bct
+
+Chainloading U-Boot from the vendor bootloader
+----------------------------------------------
+
+``u-boot-dtb.bin`` has to be further packed into Android boot image form,
+where ``u-boot-dtb.bin`` acts as kernel, while dtb and ramdisk parts should
+not be included. Then the generated boot image can be flashed into the /boot
+partition of the tablet using vendor bootloader's fastboot and will act as
+the bootloader of the last stage.
+
+Boot
+----
+In both cases after U-Boot obtains control it performs search of extlinux.conf
+first on the dock USB device is available, then on MicroSD card if available
+and lastly on eMMC. If none of the devices above are present, then the device
+is turned off.
+
+If during boot of U-Boot Volume Down button is pressed, the device will enter
+U-Boot bootmenu.
diff --git a/doc/board/qualcomm/board.rst b/doc/board/qualcomm/board.rst
index 4d79320..003d59a 100644
--- a/doc/board/qualcomm/board.rst
+++ b/doc/board/qualcomm/board.rst
@@ -90,6 +90,11 @@
make CROSS_COMPILE=aarch64-linux-gnu- O=.output dragonboard410c_defconfig
make O=.output -j$(nproc)
+Or for smartphones::
+
+ make CROSS_COMPILE=aarch64-linux-gnu- O=.output qcom_defconfig qcom-phone.config
+ make O=.output -j$(nproc)
+
- gzip u-boot::
gzip u-boot-nodtb.bin
diff --git a/doc/board/qualcomm/index.rst b/doc/board/qualcomm/index.rst
index 66bc922..e2fcbfa 100644
--- a/doc/board/qualcomm/index.rst
+++ b/doc/board/qualcomm/index.rst
@@ -9,5 +9,6 @@
dragonboard410c
rb3gen2
board
+ phones
debugging
rdp
diff --git a/doc/board/qualcomm/phones.rst b/doc/board/qualcomm/phones.rst
new file mode 100644
index 0000000..1d27196
--- /dev/null
+++ b/doc/board/qualcomm/phones.rst
@@ -0,0 +1,144 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Caleb Connolly <caleb.connolly@linaro.org>
+
+======================================
+Booting U-Boot on Qualcomm smartphones
+======================================
+
+About this
+----------
+
+This page attempts to the describe U-Boot support for Qualcomm phones, as a user guide but also a
+technical introduction to How Stuff Works to help new porters.
+
+In broad strokes, U-Boot should boot if the SoC is supported, and the device is already capable of
+booting an upstream Linux kernel.
+
+The list of supported Qualcomm SoCs changes often, for now it is best to look in
+``drivers/clk/qcom/`` to get a rough idea.
+
+For building instructions, see :doc:`board`.
+
+Phone bringup
+-------------
+
+It is usually easier to get Linux booting first, there are many good resources for this such as the
+`postmarketOS wiki`_. Once the device can boot Linux with logs on the display and ideally USB gadget
+support, it is highly likely that U-Boot will boot as well.
+
+For logs on display, you should have a simple framebuffer node defined in your DT, newer devices
+require that this follow the downstream naming scheme (that the DTB is compiled with labels enabled
+and the framebuffer reserved-memory region is labelled ``cont_splash``). Once this is working in
+Linux it should also work in U-Boot.
+
+In practise, U-Boot still has many more papercuts than Linux, which can be sticking points when
+porting a new device. In particular, drivers failing to bind/probe (especially pre-relocation) can
+be tricky to debug without UART since U-Boot will simply panic with no way to inform you of
+the error. As a result, bringing up a new device can be quite frustrating, but there are quite a few
+things you can try.
+
+The phone config
+^^^^^^^^^^^^^^^^
+
+Since most phones lack a physical keyboard or serial port, a special config fragment and environment
+file can be used to provide a more seamless experience. This can be enabled by generating the config
+with::
+
+ make CROSS_COMPILE=aarch64-linux-gnu- O=.output qcom_defconfig qcom-phone.config
+
+The config and associated environment file can be found in board/qualcomm/. The main changes are:
+
+- Panic on hang (so the panic message can be read on the display)
+- Boot retry (to automatically open and re-open the bootmenu)
+- A boot menu with helpful shortcuts (including USB console gadget)
+- Launch the boot menu if power is held during boot or on boot failure
+
+Fastboot mode
+-------------
+
+U-Boot's fastboot implementation is much more limited than Qualcomm's, and currently does not have a
+backend for UFS storage. If your device uses eMMC or has an sdcard slot, fastboot will use that by
+default.
+
+You may need to run the fastboot command on your PC as root since the USB product/vendor ID may not
+match the android udev rules.
+
+You can also use fastboot to run arbitrary U-Boot commands with ``fastboot oem run``
+
+Retrieving early logs
+^^^^^^^^^^^^^^^^^^^^^
+
+U-Boot is configured to save it's internal log to a buffer, this can help with debugging some driver
+bind/probe issues. If your device can boot and has working USB, you can enable fastboot mode (either
+via the U-Boot menu or by adding ``run fastboot`` to the end of the ``preboot=`` config in
+``board/qualcomm/qcom-phone.env``).
+
+You can then retrieve U-Boot's log buffer with the ``fastboot oem log`` command on your PC.
+
+Hang/crash bisection
+--------------------
+
+Without a way to get logs, we can still get quite far with only a few bits of information: what
+happens when you ``fastboot boot u-boot.img``?
+
+Does the device disconnect?
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+This can be verified by watching ``dmesg -w``. If it stays connected, it likely means the boot image
+doesn't match what the bootloader expected, use ``unpack_bootimg`` to compare it with a known-good
+boot image (ideally one with an upstream kernel).
+
+Does the device hang?
+^^^^^^^^^^^^^^^^^^^^^
+
+If it stays on a black screen and does nothing, then that's a hang! Since ``qcom-phone.config``
+enables CONFIG_PANIC_HANG, this likely means that you're successfully executing U-Boot code (yay!),
+but something is causing a panic.
+
+It could also be due to a bad memory or register access triggering a secure interrupt, it's worth
+waiting for around a minute to see if the device eventually reboots or goes to crashdump mode. You
+can also disable CONFIG_PANIC_HANG and see if that causes the device to reboot instead, if so then
+it is definitely a U-Boot panic.
+
+With enough time and patience, it should be possible to narrow down the cause of the panic by
+inserting calls to ``reset_cpu()`` (with CONFIG_PANIC_HANG enabled). Then if the device resets you
+know it executed the ``reset_cpu()`` call.
+
+A good place to start is ``board_fdt_blob_setup()`` in ``arch/arm/mach-snapdragon/board.c``, this
+function is called extremely early so adding a reset call is a good way to validate that U-Boot is
+definitely running.
+
+You can then do a binary search starting from the end of ``board_init_f()`` / start of
+``board_init_r()`` and work from there using the init sequences for reference.
+
+The Qualcomm RAM parsing code is a likely culprit, as ABL is known to sometimes give bogus entries
+in the memory node which can trip U-Boot up.
+
+To rule out crashes that might be caused by specific drivers, it's a good idea to disable them and
+re-enable them one by one. Here is a non-exhaustive list of drivers to disable:
+
+- pinctrl
+- mmc
+- scsi/ufs
+- usb (dwc3)
+- phy (usb, ufs)
+- clk (remove clock references from your framebuffer node in DT)
+
+Ideally, it would be possible to use the framebuffer as an early console / debug output, at the time
+of writing there are out of tree patches for this but they haven't been submitted upstream yet.
+
+Does the device reboot or go to crashdump mode?
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+On many devices crashdump mode is disabled, so they will reboot instead (maybe after some delay).
+The same approach as suggested above can be used to figure out where the crash occurs.
+
+If the device is rebooting, you can insert calls to ``hang()`` instead of ``reset_cpu()`` when
+following the instructions above.
+
+The most likely cause of a crashdump is the pinctrl/gpio driver or the SMMU driver, ensure that the
+``apps_smmu`` node in your SoCs devicetree file has one of its compatible strings referenced in
+``drivers/iommu/qcom-hyp-smmu.c``, you can also try disabling the pinctrl driver for your SoC (or
+``CONFIG_PINCTRL`` altogether).
+
+.. _`postmarketOS wiki`: https://wiki.postmarketos.org/wiki/Mainlining
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 1407080..b06f87b 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -66,6 +66,7 @@
- FriendlyElec NanoPi R2C Plus (nanopi-r2c-plus-rk3328)
- FriendlyElec NanoPi R2S (nanopi-r2s-rk3328)
- FriendlyElec NanoPi R2S Plus (nanopi-r2s-plus-rk3328)
+ - Generic RK3328 (generic-rk3328)
- Pine64 Rock64 (rock64-rk3328)
- Radxa ROCK Pi E (rock-pi-e-rk3328)
- Xunlong Orange Pi R1 Plus (orangepi-r1-plus-rk3328)
@@ -83,6 +84,7 @@
- FriendlyElec NanoPi M4 (nanopi-m4-rk3399)
- FriendlyElec NanoPi M4B (nanopi-m4b-rk3399)
- FriendlyARM NanoPi NEO4 (nanopi-neo4-rk3399)
+ - Generic RK3399 (generic-rk3399)
- Google Bob (chromebook_bob)
- Google Kevin (chromebook_kevin)
- Khadas Edge (khadas-edge-rk3399)
@@ -97,6 +99,10 @@
- Rockchip Evb-RK3399 (evb_rk3399)
- Theobroma Systems RK3399-Q7 SoM - Puma (puma_rk3399)
+* rk3528
+ - Generic RK3528 (generic-rk3528)
+ - Radxa E20C (radxa-e20c-rk3528)
+
* rk3566
- Anbernic RGxx3 (anbernic-rgxx3-rk3566)
- FriendlyElec NanoPi R3S (nanopi-r3s-rk3566)
@@ -126,6 +132,9 @@
- Radxa ROCK 3A (rock-3a-rk3568)
- Radxa ROCK 3B (rock-3b-rk3568)
+* rk3576
+ - Firefly ROC-RK3576-PC (roc-pc-rk3576)
+
* rk3588
- ArmSoM Sige7 (sige7-rk3588)
- Rockchip EVB (evb-rk3588)
@@ -258,6 +267,15 @@
make evb-rk3399_defconfig
make CROSS_COMPILE=aarch64-linux-gnu-
+To build rk3528 boards:
+
+.. code-block:: bash
+
+ export BL31=../rkbin/bin/rk35/rk3528_bl31_v1.18.elf
+ export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3528_ddr_1056MHz_v1.10.bin
+ make generic-rk3528_defconfig
+ make CROSS_COMPILE=aarch64-linux-gnu-
+
To build rk3568 boards:
.. code-block:: bash
@@ -268,6 +286,15 @@
make evb-rk3568_defconfig
make CROSS_COMPILE=aarch64-linux-gnu-
+To build rk3576 boards:
+
+.. code-block:: bash
+
+ export BL31=../rkbin/bin/rk35/rk3576_bl31_v1.04.elf
+ export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3576_ddr_lp4_2112MHz_lp5_2736MHz_v1.03.bin
+ make roc-pc-rk3576_defconfig
+ make CROSS_COMPILE=aarch64-linux-gnu-
+
To build rk3588 boards:
.. code-block:: bash
diff --git a/doc/board/starfive/deepcomputing_fml13v01.rst b/doc/board/starfive/deepcomputing_fml13v01.rst
new file mode 100644
index 0000000..5d96124
--- /dev/null
+++ b/doc/board/starfive/deepcomputing_fml13v01.rst
@@ -0,0 +1,80 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+DeepComputing Framework Motherboard (FLM13V01)
+==============================================
+
+The DeepComputing Framework motherboard (FLM13V01) can be combined with a
+13 inch Framework laptop chassis to provide a complete laptop.
+
+U-Boot for the board uses the same binaries as the VisionFive 2 board.
+Currently only serial console output is supported by mainline U-Boot.
+
+Building
+--------
+
+Setup the cross compilation environment variable:
+
+.. code-block:: bash
+
+ export CROSS_COMPILE=riscv64-linux-gnu-
+
+The M-mode software OpenSBI provides the supervisor binary interface (SBI) and
+is responsible for the switch to S-Mode. It is a prerequisite for building
+U-Boot. Support for the JH7110 was introduced in OpenSBI 1.2. It is recommended
+to use a current release.
+
+.. code-block:: bash
+
+ git clone https://github.com/riscv/opensbi.git
+ cd opensbi
+ make PLATFORM=generic FW_TEXT_START=0x40000000 FW_OPTIONS=0
+ export OPENSBI="$(pwd)/build/platform/generic/firmware/fw_dynamic.bin"
+
+Now build U-Boot SPL and main U-Boot.
+
+.. code-block:: bash
+
+ cd <U-Boot-dir>
+ make starfive_visionfive2_defconfig
+ make
+
+This will generate the U-Boot SPL image (spl/u-boot-spl.bin.normal.out) as well
+as the FIT image (u-boot.itb) with OpenSBI, U-Boot, and device-trees.
+
+Device-tree selection
+---------------------
+
+The product ID stored in the board EEPROM is used by U-Boot SPL to select the
+right configuration and device-tree from the u-boot.itb FIT image.
+
+Furthermore if variable $fdtfile has not been saved in the environment it is
+set based on the product ID to *starfive/jh7110-deepcomputing-fml13v01.dtb*.
+
+To overrule this default the variable can be set manually and saved in the
+environment
+
+.. code-block:: console
+
+ setenv fdtfile my_device-tree.dtb
+ env save
+
+Power switch
+------------
+
+A tiny power switch is located in right upper corner of the board.
+
+Open case detection
+-------------------
+
+The board has an open case detection switch. Red lights will flash and the
+board will not boot if the switch is not held down.
+
+UART
+----
+
+UART 0 is exposed via the side channel contacts SBU1 and SBU2 of the lower,
+right USB C connector. A USB C cable and a breakout board are needed for
+physical access. It depends on the cable orientation on which of SBU1 and SBU2
+you will find RX and TX. The signal voltage is 3.3 V. The baud rate is 115200.
+
+.. include:: jh7110_common.rst
diff --git a/doc/board/starfive/index.rst b/doc/board/starfive/index.rst
index 2cba1b6..66abc6f 100644
--- a/doc/board/starfive/index.rst
+++ b/doc/board/starfive/index.rst
@@ -6,6 +6,7 @@
.. toctree::
:maxdepth: 1
+ deepcomputing_fml13v01
milk-v_mars
pine64_star64
visionfive2
diff --git a/doc/board/starfive/jh7110_common.rst b/doc/board/starfive/jh7110_common.rst
new file mode 100644
index 0000000..4a8058e
--- /dev/null
+++ b/doc/board/starfive/jh7110_common.rst
@@ -0,0 +1,103 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+Boot source selection
+---------------------
+
+The board provides DIP switches to select the device for loading the boot
+firmware.
+
+=========== === ===
+Boot source SW1 SW2
+=========== === ===
+UART OFF OFF
+SD-card ON OFF
+eMMC OFF ON
+SPI flash ON ON
+=========== === ===
+
+Flashing a new U-Boot version
+-----------------------------
+
+U-Boot SPL is provided as file spl/u-boot-spl.bin.normal.out. Main U-Boot is
+in file u-boot.itb.
+
+Assuming your new U-Boot version is on partition 1 of an SD-card you could
+install it to the SPI flash with:
+
+.. code-block:: console
+
+ sf probe
+ load mmc 1:1 $kernel_addr_r u-boot-spl.bin.normal.out
+ sf update $kernel_addr_r 0 $filesize
+ load mmc 1:1 $kernel_addr_r u-boot.itb
+ sf update $kernel_addr_r 0x100000 $filesize
+
+For loading the files from a TFTP server refer to the dhcp and tftpboot
+commands.
+
+After updating U-Boot you may want to erase a saved environment and reboot.
+
+.. code-block:: console
+
+ env erase
+ reset
+
+Booting from SD-Card
+--------------------
+
+The device boot ROM loads U-Boot SPL (u-boot-spl.bin.normal.out) from the
+partition with type GUID 2E54B353-1271-4842-806F-E436D6AF6985. You are free
+to choose any partition number.
+
+With the default configuration U-Boot SPL loads the U-Boot FIT image
+(u-boot.itb) from partition 2 (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2).
+When formatting it is recommended to use GUID
+BC13C2FF-59E6-4262-A352-B275FD6F7172 for this partition.
+
+Booting from eMMC
+-----------------
+
+The device boot ROM tries to load U-Boot SPL (u-boot-spl.bin.normal.out) from
+sector 0 of the eMMC's main hardware partition. But this conflicts with GPT
+partitioning. Fortunately eMMC can alternatively load U-Boot SPL from a backup
+position.
+
+For U-Boot SPL (u-boot-spl.bin.normal.out) starting at sector 2048 (position
+0x100000) write the following bytes to the eMMC device after GPT partitioning:
+
+======= ========================
+Address Bytes
+======= ========================
+0x0000 40 02 00 00 00 00 10 00
+0x0290 40 02 00 00 00 00 10 00
+======= ========================
+
+With the default configuration U-Boot SPL loads the U-Boot FIT image
+(u-boot.itb) from partition 2 (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2).
+When formatting it is recommended to use GUID
+BC13C2FF-59E6-4262-A352-B275FD6F7172 for this partition.
+
+Booting from UART
+-----------------
+
+The boot ROM supports the X-modem protocol to upload
+spl/u-boot-spl.bin.normal.out. U-Boot SPL support loading the FIT image
+u-boot.itb via the Y-modem protocol.
+
+Due to restrictions of the boot ROM not all X-modem implementations are
+compatible. The package tio (https://github.com/tio/tio) has been found to be
+usable.
+
+Debug UART
+----------
+
+By default the SBI interface is used for the debug UART. But this only works
+in main U-Boot. To enable the debug UART in SPL, too, use the following
+settings::
+
+ CONFIG_DEBUG_UART=y
+ CONFIG_DEBUG_UART_NS16550=y
+ CONFIG_DEBUG_UART_BASE=0x10000000
+ CONFIG_SPL_DEBUG_UART_BASE=0x10000000
+ CONFIG_DEBUG_UART_CLOCK=24000000
+ CONFIG_DEBUG_UART_SHIFT=2
diff --git a/doc/board/starfive/milk-v_mars.rst b/doc/board/starfive/milk-v_mars.rst
index 554932e..ce4539a 100644
--- a/doc/board/starfive/milk-v_mars.rst
+++ b/doc/board/starfive/milk-v_mars.rst
@@ -8,7 +8,7 @@
accordingly.
Building
-~~~~~~~~
+--------
1. Add the RISC-V toolchain to your PATH.
2. Setup ARCH & cross compilation environment variable:
@@ -40,7 +40,7 @@
as the FIT image (u-boot.itb) with OpenSBI and U-Boot.
Device-tree selection
-~~~~~~~~~~~~~~~~~~~~~
+---------------------
Depending on the board version U-Boot set variable $fdtfile to either
starfive/jh7110-starfive-visionfive-2-v1.2a.dtb or
@@ -57,15 +57,8 @@
or the configuration variable CONFIG_DEFAULT_FDT_FILE can be used to set to
provide a default value.
-Boot source selection
-~~~~~~~~~~~~~~~~~~~~~
-
-The board provides the DIP switches MSEL[1:0] to select the boot device out of
-SPI flash, eMMC, SD-card, UART. To select booting from SD-card set the DIP
-switches MSEL[1:0] to 10.
-
Preparing the SD-Card
-~~~~~~~~~~~~~~~~~~~~~
+---------------------
The device firmware loads U-Boot SPL (u-boot-spl.bin.normal.out) from the
partition with type GUID 2E54B353-1271-4842-806F-E436D6AF6985. You are free
@@ -105,7 +98,4 @@
sudo cp jh7110-starfive-visionfive-2.dtb /mnt/
sudo umount /mnt
-Booting
-~~~~~~~
-
-Once you plugin the sdcard and power up, you should see the U-Boot prompt.
+.. include:: jh7110_common.rst
diff --git a/doc/board/starfive/pine64_star64.rst b/doc/board/starfive/pine64_star64.rst
index 52e9a90..d1752c4 100644
--- a/doc/board/starfive/pine64_star64.rst
+++ b/doc/board/starfive/pine64_star64.rst
@@ -8,7 +8,7 @@
accordingly.
Building
-~~~~~~~~
+--------
1. Add the RISC-V toolchain to your PATH.
2. Setup ARCH & cross compilation environment variable:
@@ -40,7 +40,7 @@
as the FIT image (u-boot.itb) with OpenSBI and U-Boot.
Device-tree selection
-~~~~~~~~~~~~~~~~~~~~~
+---------------------
U-Boot will set variable $fdtfile to starfive/jh7110-pine64-star64.dtb.
@@ -55,21 +55,8 @@
or the configuration variable CONFIG_DEFAULT_FDT_FILE can be used to set to
provide a default value.
-Boot source selection
-~~~~~~~~~~~~~~~~~~~~~
-
-Boot mode is selected by an MSEL-DIP marked S1804 and GPIO_0 position adjacent
-to the 40pin GPIO header. ON/ONKE and number markings of the MSEL-DIP are
-misleading; Instead refer to the ``L`` (0) and ``H`` (1) silkscreen for
-accurate selection.
-
-+ (QSPI) Flash: 00
-+ SD: 01
-+ EMMC: 10
-+ UART: 11
-
Preparing the SD-Card
-~~~~~~~~~~~~~~~~~~~~~
+---------------------
The device firmware loads U-Boot SPL (u-boot-spl.bin.normal.out) from the
partition with type GUID 2E54B353-1271-4842-806F-E436D6AF6985. You are free
@@ -109,13 +96,10 @@
sudo cp jh7110-starfive-visionfive-2.dtb /mnt/
sudo umount /mnt
-Booting
-~~~~~~~
-
-Once you plugin the sdcard and power up, you should see the U-Boot prompt.
+.. include:: jh7110_common.rst
Serial Number and MAC address issues
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------------------------------------
U-Boot requires valid EEPROM data to determine which board-specific fix-up to
apply at runtime. This affects the size of memory initialized, network mac
diff --git a/doc/board/starfive/visionfive2.rst b/doc/board/starfive/visionfive2.rst
index 2c68df3..11121a1 100644
--- a/doc/board/starfive/visionfive2.rst
+++ b/doc/board/starfive/visionfive2.rst
@@ -36,7 +36,7 @@
firmware with the latest.
Building
-~~~~~~~~
+--------
1. Add the RISC-V toolchain to your PATH.
2. Setup ARCH & cross compilation environment variable:
@@ -72,7 +72,7 @@
as the FIT image (u-boot.itb) with OpenSBI and U-Boot.
Device-tree selection
-~~~~~~~~~~~~~~~~~~~~~
+---------------------
Depending on the board version U-Boot set variable $fdtfile to either
starfive/jh7110-starfive-visionfive-2-v1.2a.dtb or
@@ -90,7 +90,7 @@
a default value.
Flashing
-~~~~~~~~
+--------
The device firmware loads U-Boot SPL (u-boot-spl.bin.normal.out) from the
partition with type GUID 2E54B353-1271-4842-806F-E436D6AF6985. You are free
@@ -116,6 +116,7 @@
--new=2:8192:16383 --change-name=2:uboot --typecode=2:BC13C2FF-59E6-4262-A352-B275FD6F7172 \
--new=3:16384:1654784 --change-name=3:system --typecode=3:EBD0A0A2-B9E5-4433-87C0-68B6B72699C7 \
/dev/sdb
+ sudo mkfs.vfat -F32 /dev/sdb3
Program the SD card
@@ -132,16 +133,10 @@
sudo cp jh7110-starfive-visionfive-2.dtb /mnt/
sudo umount /mnt
-Booting
-~~~~~~~
-
-The board provides the DIP switches MSEL[1:0] to select the boot device.
-To select booting from SD-card set the DIP switches MSEL[1:0] to 10.
-
-Once you plugin the sdcard and power up, you should see the U-Boot prompt.
+.. include:: jh7110_common.rst
Sample boot log from StarFive VisionFive2 board
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-----------------------------------------------
.. code-block:: none
@@ -479,34 +474,3 @@
Welcome to Buildroot
buildroot login:
-
-Booting from SPI
-----------------
-
-Use Building steps from "Booting from MMC using U-Boot SPL" section.
-
-Partition the SPI in Linux via mtdblock. (Require to boot the board in
-SD boot mode by enabling MTD block in Linux)
-
-Use prebuilt image from here [1], which support to partition the SPI flash.
-
-
-Program the SPI (Require to boot the board in SD boot mode)
-
-Execute below steps on U-Boot proper,
-
-.. code-block:: none
-
- sf probe
- fatload mmc 1:3 $kernel_addr_r u-boot.itb
- sf update $kernel_addr_r 0x100000 $filesize
-
- fatload mmc 1:3 $kernel_addr_r u-boot-spl.bin.normal.out
- sf update $kernel_addr_r 0x0 $filesize
-
-
-Power off the board
-
-Change DIP switches MSEL[1:0] are set to 00, select the boot mode to flash
-
-Power up the board.
diff --git a/doc/board/ti/am62ax_sk.rst b/doc/board/ti/am62ax_sk.rst
index 262340e..43a1db6 100644
--- a/doc/board/ti/am62ax_sk.rst
+++ b/doc/board/ti/am62ax_sk.rst
@@ -81,16 +81,16 @@
.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_defn
:end-before: .. k3_rst_include_end_common_env_vars_defn
-.. code-block:: bash
+.. prompt:: bash
- $ export UBOOT_CFG_CORTEXR=am62ax_evm_r5_defconfig
- $ export UBOOT_CFG_CORTEXA=am62ax_evm_a53_defconfig
- $ export TFA_BOARD=lite
- $ # we dont use any extra TFA parameters
- $ unset TFA_EXTRA_ARGS
- $ export OPTEE_PLATFORM=k3-am62ax
- $ # we dont use any extra OPTEE parameters
- $ unset OPTEE_EXTRA_ARGS
+ export UBOOT_CFG_CORTEXR=am62ax_evm_r5_defconfig
+ export UBOOT_CFG_CORTEXA=am62ax_evm_a53_defconfig
+ export TFA_BOARD=lite
+ # we dont use any extra TFA parameters
+ unset TFA_EXTRA_ARGS
+ export OPTEE_PLATFORM=k3-am62ax
+ # we dont use any extra OPTEE parameters
+ unset OPTEE_EXTRA_ARGS
1. Trusted Firmware-A:
@@ -212,6 +212,6 @@
To start OpenOCD and connect to the board
-.. code-block:: bash
+.. prompt:: bash
openocd -f board/ti_am62a7evm.cfg
diff --git a/doc/board/ti/am62px_sk.rst b/doc/board/ti/am62px_sk.rst
index 99bdc03..a07d6a4 100644
--- a/doc/board/ti/am62px_sk.rst
+++ b/doc/board/ti/am62px_sk.rst
@@ -91,15 +91,15 @@
:start-after: .. k3_rst_include_start_common_env_vars_defn
:end-before: .. k3_rst_include_end_common_env_vars_defn
-.. code-block:: bash
+.. prompt:: bash
- $ export UBOOT_CFG_CORTEXR=am62px_evm_r5_defconfig
- $ export UBOOT_CFG_CORTEXA=am62px_evm_a53_defconfig
- $ export TFA_BOARD=lite
- $ # we dont use any extra TFA parameters
- $ unset TFA_EXTRA_ARGS
- $ export OPTEE_PLATFORM=k3-am62x
- $ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y"
+ export UBOOT_CFG_CORTEXR=am62px_evm_r5_defconfig
+ export UBOOT_CFG_CORTEXA=am62px_evm_a53_defconfig
+ export TFA_BOARD=lite
+ # we dont use any extra TFA parameters
+ unset TFA_EXTRA_ARGS
+ export OPTEE_PLATFORM=k3-am62x
+ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y"
.. am62px_evm_rst_include_start_build_steps
@@ -312,6 +312,6 @@
To start OpenOCD and connect to the board
-.. code-block:: bash
+.. prompt:: bash
openocd -f board/ti_am62pevm.cfg
diff --git a/doc/board/ti/j722s_evm.rst b/doc/board/ti/j722s_evm.rst
index e5a1be5..9c53fa5 100644
--- a/doc/board/ti/j722s_evm.rst
+++ b/doc/board/ti/j722s_evm.rst
@@ -68,13 +68,12 @@
:start-after: .. k3_rst_include_start_common_env_vars_defn
:end-before: .. k3_rst_include_end_common_env_vars_defn
-.. code-block:: bash
+.. prompt:: bash
- $ export UBOOT_CFG_CORTEXR=j722s_evm_r5_defconfig
- $ export UBOOT_CFG_CORTEXA=j722s_evm_a53_defconfig
- $ export TFA_BOARD=lite
- $ export OPTEE_PLATFORM=k3-am62x
- $ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y"
+ export UBOOT_CFG_CORTEXR=j722s_evm_r5_defconfig
+ export UBOOT_CFG_CORTEXA=j722s_evm_a53_defconfig
+ export TFA_BOARD=lite
+ export OPTEE_PLATFORM=k3-am62x
.. j722s_evm_rst_include_start_build_steps
@@ -259,6 +258,6 @@
To start OpenOCD and connect to the board
-.. code-block:: bash
+.. prompt:: bash
openocd -f board/ti_j722sevm.cfg
diff --git a/doc/board/ti/j784s4_evm.rst b/doc/board/ti/j784s4_evm.rst
index a1e927c..349fb39 100644
--- a/doc/board/ti/j784s4_evm.rst
+++ b/doc/board/ti/j784s4_evm.rst
@@ -81,14 +81,14 @@
.. include:: k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_defn
:end-before: .. k3_rst_include_end_common_env_vars_defn
-.. code-block:: bash
+.. prompt:: bash
- $ export UBOOT_CFG_CORTEXR=j784s4_evm_r5_defconfig
- $ export UBOOT_CFG_CORTEXA=j784s4_evm_a72_defconfig
- $ export TFA_BOARD=j784s4
- $ export TFA_EXTRA_ARGS="K3_USART=0x8"
- $ export OPTEE_PLATFORM=k3-j784s4
- $ export OPTEE_EXTRA_ARGS="CFG_CONSOLE_UART=0x8"
+ export UBOOT_CFG_CORTEXR=j784s4_evm_r5_defconfig
+ export UBOOT_CFG_CORTEXA=j784s4_evm_a72_defconfig
+ export TFA_BOARD=j784s4
+ export TFA_EXTRA_ARGS="K3_USART=0x8"
+ export OPTEE_PLATFORM=k3-j784s4
+ export OPTEE_EXTRA_ARGS="CFG_CONSOLE_UART=0x8"
.. j784s4_evm_rst_include_start_build_steps
@@ -326,6 +326,6 @@
To start OpenOCD and connect to J784S4-EVM or AM69-SK board, use the
following.
-.. code-block:: bash
+.. prompt:: bash
openocd -f board/ti_j784s4evm.cfg
diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst
index 0deb4d7..b79f152 100644
--- a/doc/board/ti/k3.rst
+++ b/doc/board/ti/k3.rst
@@ -460,7 +460,7 @@
supports packing multiple images and configurations that allow you to
choose any configuration at runtime to boot from.
-.. code-block::
+.. code-block:: dts
/dts-v1/;
@@ -484,7 +484,7 @@
* Sample Images
-.. code-block::
+.. code-block:: dts
kernel-1 {
description = "Linux kernel";
@@ -533,7 +533,7 @@
* Sample Configurations
-.. code-block::
+.. code-block:: dts
conf-ti_k3-j721e-common-proc-board.dtb {
description = "Linux kernel, FDT blob";
@@ -585,7 +585,7 @@
For e.g
- .. code-block::
+ .. code-block:: diff
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index a5c1df7e0054..6d0126d955ef 100644
@@ -605,7 +605,7 @@
For e.g
- .. code-block::
+ .. code-block:: diff
diff --git a/arch/arm/dts/k3-j721e-binman.dtsi b/arch/arm/dts/k3-j721e-binman.dtsi
index 673be646b1e3..752fa805fe8d 100644
diff --git a/doc/board/toradex/index.rst b/doc/board/toradex/index.rst
index 89fbdcb..7d510a8 100644
--- a/doc/board/toradex/index.rst
+++ b/doc/board/toradex/index.rst
@@ -9,6 +9,7 @@
apalis-imx8
colibri_imx7
colibri-imx8x
+ smarc-imx8mp
verdin-am62
verdin-imx8mm
verdin-imx8mp
diff --git a/doc/board/toradex/smarc-imx8mp.rst b/doc/board/toradex/smarc-imx8mp.rst
new file mode 100644
index 0000000..6083ce6
--- /dev/null
+++ b/doc/board/toradex/smarc-imx8mp.rst
@@ -0,0 +1,116 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+Toradex SMARC iMX8M Plus Module
+===============================
+
+- SoM: https://www.toradex.com/computer-on-modules/smarc-arm-family/nxp-imx-8m-plus
+- Carrier board: https://www.toradex.com/products/carrier-board/smarc-development-board-kit
+
+Quick Start
+-----------
+
+- Build the ARM trusted firmware binary
+- Get the DDR firmware
+- Build U-Boot
+- Flash to eMMC
+- Boot
+
+Get and Build the ARM Trusted Firmware (Trusted Firmware A)
+-----------------------------------------------------------
+
+.. code-block:: bash
+
+ $ echo "Downloading and building TF-A..."
+ $ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
+ $ cd trusted-firmware-a
+
+Then build ATF (TF-A):
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-linux-gnu-
+ $ make PLAT=imx8mp IMX_BOOT_UART_BASE=0x30a60000 bl31
+ $ cp build/imx8mp/release/bl31.bin ../
+
+Get the DDR Firmware
+--------------------
+
+.. code-block:: bash
+
+ $ cd ..
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.10.1.bin
+ $ chmod +x firmware-imx-8.10.1.bin
+ $ ./firmware-imx-8.10.1.bin
+ $ cp firmware-imx-8.10.1/firmware/ddr/synopsys/lpddr4*_202006.bin ./
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-linux-gnu-
+ $ make toradex-smarc-imx8mp_defconfig
+ $ make
+
+Flash to eMMC
+-------------
+
+.. code-block:: bash
+
+ > tftpboot ${loadaddr} flash.bin
+ > setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
+ > mmc dev 0 1 && mmc write ${loadaddr} 0x0 ${blkcnt}
+
+As a convenience, instead of the last two commands, one may also use the update
+U-Boot wrapper:
+
+.. code-block:: bash
+
+ > run update_uboot
+
+Boot
+----
+
+ATF, U-Boot proper and u-boot.dtb images are packed into a FIT image,
+which is loaded and parsed by SPL.
+
+Boot sequence is:
+
+* SPL ---> ATF (TF-A) ---> U-Boot proper
+
+Output::
+
+ U-Boot SPL 2025.04-rc5-00023-g34c31be81211 (Apr 04 2025 - 15:36:23 +0100)
+ Training FAILED
+ DDR configured as single rank
+ SEC0: RNG instantiated
+ Normal Boot
+ Trying to boot from BOOTROM
+ Boot Stage: Primary boot
+ Find img info 0x4802f200, size 1100
+ Need continue download 1024
+ NOTICE: Do not release JR0 to NS as it can be used by HAB
+ NOTICE: BL31: v2.11.0(release):v2.11.0-723-gbd298f5c30ac
+ NOTICE: BL31: Built : 14:18:43, Apr 4 2025
+
+
+ U-Boot 2025.04-rc5-00023-g34c31be81211 (Apr 04 2025 - 15:36:23 +0100)
+
+ CPU: Freescale i.MX8MP[8] rev1.1 1600 MHz (running at 1200 MHz)
+ CPU: Industrial temperature grade (-40C to 105C) at 72C
+ Reset cause: POR
+ DRAM: 4 GiB
+ Core: 312 devices, 32 uclasses, devicetree: separate
+ WDT: Started watchdog@30280000 with servicing every 1000ms (60s timeout)
+ MMC: FSL_SDHC: 1, FSL_SDHC: 0
+ Loading Environment from MMC... Reading from MMC(0)... OK
+ In: serial@30a60000
+ Out: serial@30a60000
+ Err: serial@30a60000
+ Model: Toradex 0097 SMARC iMX8M Plus Quad 4GB WB IT V1.0A
+ Serial#: 15603364
+ SEC0: RNG instantiated
+ Net: Get shared mii bus on ethernet@30be0000
+ eth1: ethernet@30be0000, eth0: ethernet@30bf0000 [PRIME]
+ Hit any key to stop autoboot: 0
+ SMARC iMX8MP #
diff --git a/doc/build/gcc.rst b/doc/build/gcc.rst
index d8fcfdc..480e0e3 100644
--- a/doc/build/gcc.rst
+++ b/doc/build/gcc.rst
@@ -31,7 +31,7 @@
python3-pkg-resources python3-pycryptodome python3-pyelftools \
python3-pytest python3-pytest-xdist python3-sphinxcontrib.apidoc \
python3-sphinx-rtd-theme python3-subunit python3-testtools \
- python3-virtualenv swig uuid-dev
+ python3-venv swig uuid-dev
SUSE based
~~~~~~~~~~
diff --git a/doc/develop/codingstyle.rst b/doc/develop/codingstyle.rst
index fa3cd6a..bc18b2e 100644
--- a/doc/develop/codingstyle.rst
+++ b/doc/develop/codingstyle.rst
@@ -154,6 +154,73 @@
<https://www.kernel.org/doc/html/latest/doc-guide/kernel-doc.html#function-documentation>`_
for style.
+Conditional Compilation
+-----------------------
+
+Wherever possible, don't use preprocessor conditionals (#if, #ifdef) in .c
+files; doing so makes code harder to read and logic harder to follow. Instead,
+use such conditionals in a header file defining functions for use in those .c
+files, providing no-op stub versions in the #else case, and then call those
+functions unconditionally from .c files. The compiler will avoid generating
+any code for the stub calls, producing identical results, but the logic will
+remain easy to follow.
+
+Prefer to compile out entire functions, rather than portions of functions or
+portions of expressions. Rather than putting an ifdef in an expression, factor
+out part or all of the expression into a separate helper function and apply the
+conditional to that function.
+
+If you have a function or variable which may potentially go unused in a
+particular configuration, and the compiler would warn about its definition
+going unused, mark the definition as __maybe_unused rather than wrapping it in
+a preprocessor conditional. (However, if a function or variable *always* goes
+unused, delete it.)
+
+Within code, where possible, use the IS_ENABLED macro to convert a Kconfig
+symbol into a C boolean expression, and use it in a normal C conditional:
+
+.. code-block:: c
+
+ if (IS_ENABLED(CONFIG_SOMETHING)) {
+ ...
+ }
+
+The compiler will constant-fold the conditional away, and include or exclude
+the block of code just as with an #ifdef, so this will not add any runtime
+overhead. However, this approach still allows the C compiler to see the code
+inside the block, and check it for correctness (syntax, types, symbol
+references, etc). Thus, you still have to use an #ifdef if the code inside the
+block references symbols that will not exist if the condition is not met.
+
+When working with xPL (see :doc:`spl` for more information) we need to take
+further care to use the right macro. In the case where a symbol may be
+referenced with an xPL-specific Kconfig symbol, use the CONFIG_IS_ENABLED macro
+instead, in a similar manner:
+
+.. code-block:: c
+
+ if (CONIG_IS_ENABLED(SOMETHING)) {
+ ...
+ }
+
+When dealing with a Kconfig symbol that has both a normal name and one or more
+xPL-prefixed names, the Makefile needs special consideration as well. The
+PHASE\_ macro helps us in this situation thusly:
+
+.. code-block:: make
+
+ obj-$(CONFIG_$(PHASE_)SOMETHING) += something.o
+
+At the end of any non-trivial #if or #ifdef block (more than a few lines),
+place a comment after the #endif on the same line, noting the conditional
+expression used. For instance:
+
+.. code-block:: c
+
+ #ifdef CONFIG_SOMETHING
+ ...
+ #endif /* CONFIG_SOMETHING */
+
Driver model
------------
diff --git a/doc/develop/devicetree/dt_qemu.rst b/doc/develop/devicetree/dt_qemu.rst
index 8ba2b22..b452e2a 100644
--- a/doc/develop/devicetree/dt_qemu.rst
+++ b/doc/develop/devicetree/dt_qemu.rst
@@ -16,15 +16,22 @@
Where QEMU generates its own devicetree to pass to U-Boot you can use
`-dtb u-boot.dtb` to force QEMU to use U-Boot's in-tree version.
-To obtain the devicetree that qemu generates, add `-machine dumpdtb=qemu.dtb`,
-e.g.::
+To obtain the devicetree that QEMU generates, add `dumpdtb=qemu.dtb` to the
+`-machine` argument, e.g.
- qemu-system-arm -machine virt -machine dumpdtb=qemu.dtb
+.. code-block:: bash
- qemu-system-aarch64 -machine virt -machine dumpdtb=qemu.dtb
-
- qemu-system-riscv64 -machine virt -machine dumpdtb=qemu.dtb
+ qemu-system-aarch64 \
+ -machine virt,gic-version=3,dumpdtb=qemu.dtb \
+ -cpu cortex-a57 \
+ -smp 4 \
+ -memory 8G \
+ -chardev socket,id=chrtpm,path=/tmp/mytpm1/swtpm-sock \
+ -tpmdev emulator,id=tpm0,chardev=chrtpm \
+ -device tpm-tis-device,tpmdev=tpm0
+Except for the dumpdtb=qemu.dtb sub-parameter use the same qemu-system-<arch>
+invocation that you would use to start U-Boot to to get a complete device-tree.
Merging in U-Boot nodes/properties
----------------------------------
diff --git a/doc/develop/driver-model/design.rst b/doc/develop/driver-model/design.rst
index 3009373..6335459 100644
--- a/doc/develop/driver-model/design.rst
+++ b/doc/develop/driver-model/design.rst
@@ -312,7 +312,7 @@
.name = "demo_shape_drv",
.id = UCLASS_DEMO,
.ops = &shape_ops,
- .priv_data_size = sizeof(struct shape_data),
+ .priv_auto = sizeof(struct shape_data),
};
diff --git a/doc/develop/py_testing.rst b/doc/develop/py_testing.rst
index 502053f..217ae44 100644
--- a/doc/develop/py_testing.rst
+++ b/doc/develop/py_testing.rst
@@ -69,19 +69,19 @@
`test/py/tests/fs_helper.py` which shall be used in any tests that require
creating disk images.
-Using `virtualenv` to provide requirements
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Using a Python sandbox to provide requirements
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The recommended way to run the test suite, in order to ensure reproducibility
-is to use `virtualenv` to set up the necessary environment. This can be done
-via the following commands:
+is to use a Python sandbox such as `python -m venv` to set up the necessary
+environment. This can be done via the following commands:
.. code-block:: console
$ cd /path/to/u-boot
- $ sudo apt-get install python3 python3-virtualenv
- $ virtualenv -p /usr/bin/python3 venv
+ $ sudo apt-get install python3 python3-venv
+ $ python3 -m venv venv
$ . ./venv/bin/activate
$ pip install -r test/py/requirements.txt
diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst
index cbbc2ba..73b354d 100644
--- a/doc/develop/release_cycle.rst
+++ b/doc/develop/release_cycle.rst
@@ -1,3 +1,5 @@
+.. |next_ver| replace:: v2025.07
+
Release Cycle
=============
@@ -53,13 +55,13 @@
* U-Boot v2025.04 was released on Monday, 07 April 2025.
-* The Merge Window for the next release (v2025.07) is **open** until the -rc1
+* The Merge Window for the next release (|next_ver|) was **closed** with the -rc1
release on Monday, 28 April 2025.
* The next branch is now **closed** until the -rc2 release on Monday, 12 May
2025.
-* Release "v2025.07" is scheduled for Monday, 07 July 2025.
+* Release "|next_ver|" is scheduled for Monday, 07 July 2025.
Future Releases
---------------
@@ -67,17 +69,17 @@
.. The following commented out dates are for when release candidates are
planned to be tagged.
-.. For the next scheduled release, release candidates were made on::
+For the next scheduled release, release candidates were made on::
-.. * U-Boot v2025.07-rc1 was released on Mon 21 April 2025.
+* U-Boot |next_ver|-rc1 was released on Mon 28 April 2025.
-.. * U-Boot v2025.07-rc2 was released on Mon 12 May 2025.
+.. * U-Boot |next_ver|-rc2 was released on Mon 12 May 2025.
-.. * U-Boot v2025.07-rc3 was released on Mon 26 May 2025.
+.. * U-Boot |next_ver|-rc3 was released on Mon 26 May 2025.
-.. * U-Boot v2025.07-rc4 was released on Mon 09 June 2025.
+.. * U-Boot |next_ver|-rc4 was released on Mon 09 June 2025.
-.. * U-Boot v2025.07-rc5 was released on Mon 23 June 2025.
+.. * U-Boot |next_ver|-rc5 was released on Mon 23 June 2025.
Please note that the following dates are planned only and may be deviated from
as needed.
diff --git a/doc/develop/tests_writing.rst b/doc/develop/tests_writing.rst
index 7ea1708..f6f852c 100644
--- a/doc/develop/tests_writing.rst
+++ b/doc/develop/tests_writing.rst
@@ -309,15 +309,15 @@
Finally, add the test to the build by adding to the Makefile in the same
directory::
- obj-$(CONFIG_$(XPL_)CMDLINE) += wibble.o
+ obj-$(CONFIG_$(PHASE_)CMDLINE) += wibble.o
Note that CMDLINE is never enabled in SPL, so this test will only be present in
U-Boot proper. See below for how to do SPL tests.
You can add an extra Kconfig check if needed::
- ifneq ($(CONFIG_$(XPL_)WIBBLE),)
- obj-$(CONFIG_$(XPL_)CMDLINE) += wibble.o
+ ifneq ($(CONFIG_$(PHASE_)WIBBLE),)
+ obj-$(CONFIG_$(PHASE_)CMDLINE) += wibble.o
endif
Each suite can have an optional init and uninit function. These are run before
diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst
index 48d6110..3ca22b5 100644
--- a/doc/develop/uefi/uefi.rst
+++ b/doc/develop/uefi/uefi.rst
@@ -597,21 +597,6 @@
[--fit | --raw | --guid <guid-string] \
<image_blob> <capsule_file_name>
-4. Insert the signature list into a device tree in the following format::
-
- {
- signature {
- capsule-key = [ <binary of signature list> ];
- }
- ...
- }
-
-You can perform step-4 through the Kconfig symbol
-CONFIG_EFI_CAPSULE_CRT_FILE. This symbol points to the signing key
-generated in step-2. As part of U-Boot build, the ESL certificate file will
-be generated from the signing key and automatically get embedded into the
-platform's dtb.
-
Anti-rollback Protection
************************
diff --git a/doc/git-mailrc b/doc/git-mailrc
index 1177e42..6214dae 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -42,7 +42,7 @@
alias monstr Michal Simek <monstr@monstr.eu>
alias prom Minkyu Kang <mk7.kang@samsung.com>
alias ptomsich Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
-alias sbabic Stefano Babic <sbabic@denx.de>
+alias sbabic Stefano Babic <sbabic@nabladev.com>
alias simongoldschmidt Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
alias sjg Simon Glass <sjg@chromium.org>
alias smcnutt Scott McNutt <smcnutt@psyent.com>
diff --git a/doc/usage/blkmap.rst b/doc/usage/blkmap.rst
index 75f736c..4e9091e 100644
--- a/doc/usage/blkmap.rst
+++ b/doc/usage/blkmap.rst
@@ -39,7 +39,7 @@
dhcp ${ramdisk_addr_r} rootfs.ext4
-But now we are faced with a predicament: how to we extract the kernel
+But now we are faced with a predicament: how do we extract the kernel
image? Block maps to the rescue!
We start by creating a new device:
diff --git a/doc/usage/cmd/md.rst b/doc/usage/cmd/md.rst
index 9a9919f..1eeaa82 100644
--- a/doc/usage/cmd/md.rst
+++ b/doc/usage/cmd/md.rst
@@ -21,7 +21,7 @@
various data sizes and uses the endianness of the target.
The specified data_size and length become the defaults for future memory
-commands commands.
+commands.
address
start address to display
diff --git a/doc/usage/cmd/part.rst b/doc/usage/cmd/part.rst
index e7faecc..e7f6e54 100644
--- a/doc/usage/cmd/part.rst
+++ b/doc/usage/cmd/part.rst
@@ -50,7 +50,7 @@
varname
an optional environment variable to store the list of partitions value into.
-The 'part start' commnad sets an environment variable to the start of the partition (in blocks),
+The 'part start' command sets an environment variable to the start of the partition (in blocks),
part can be either partition number or partition name.
interface
diff --git a/drivers/Makefile b/drivers/Makefile
index 0e1f58c..3c0ad17 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -34,15 +34,15 @@
obj-$(CONFIG_$(PHASE_)SPI) += spi/
obj-$(CONFIG_$(PHASE_)TIMER) += timer/
obj-$(CONFIG_$(PHASE_)VIRTIO) += virtio/
-obj-$(CONFIG_$(XPL_)DM_MAILBOX) += mailbox/
-obj-$(CONFIG_$(XPL_)REMOTEPROC) += remoteproc/
-obj-$(CONFIG_$(XPL_)SYSINFO) += sysinfo/
+obj-$(CONFIG_$(PHASE_)DM_MAILBOX) += mailbox/
+obj-$(CONFIG_$(PHASE_)REMOTEPROC) += remoteproc/
+obj-$(CONFIG_$(PHASE_)SYSINFO) += sysinfo/
obj-$(CONFIG_$(PHASE_)SM) += sm/
obj-$(CONFIG_$(PHASE_)TPM) += tpm/
-obj-$(CONFIG_$(XPL_)NVME) += nvme/
+obj-$(CONFIG_$(PHASE_)NVME) += nvme/
obj-$(CONFIG_XEN) += xen/
-obj-$(CONFIG_$(XPL_)FPGA) += fpga/
-obj-$(CONFIG_$(XPL_)VIDEO) += video/
+obj-$(CONFIG_$(PHASE_)FPGA) += fpga/
+obj-$(CONFIG_$(PHASE_)VIDEO) += video/
obj-y += bus/
@@ -55,7 +55,7 @@
obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR) += ddr/fsl/
obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/
obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/
-obj-$(CONFIG_$(XPL_)ALTERA_SDRAM) += ddr/altera/
+obj-$(CONFIG_$(PHASE_)ALTERA_SDRAM) += ddr/altera/
obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/
obj-$(CONFIG_IMX8ULP_DRAM) += ddr/imx/imx8ulp/
obj-$(CONFIG_ARCH_IMX9) += ddr/imx/imx9/
diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c
index 7cf9735..1515951 100644
--- a/drivers/adc/rockchip-saradc.c
+++ b/drivers/adc/rockchip-saradc.c
@@ -339,6 +339,14 @@
.stop = rockchip_saradc_stop_v1,
};
+static const struct rockchip_saradc_data rk3528_saradc_data = {
+ .num_bits = 10,
+ .num_channels = 4,
+ .clk_rate = 1000000,
+ .channel_data = rockchip_saradc_channel_data_v2,
+ .start_channel = rockchip_saradc_start_channel_v2,
+};
+
static const struct rockchip_saradc_data rk3588_saradc_data = {
.num_bits = 12,
.num_channels = 8,
@@ -354,6 +362,8 @@
.data = (ulong)&rk3066_tsadc_data },
{ .compatible = "rockchip,rk3399-saradc",
.data = (ulong)&rk3399_saradc_data },
+ { .compatible = "rockchip,rk3528-saradc",
+ .data = (ulong)&rk3528_saradc_data },
{ .compatible = "rockchip,rk3588-saradc",
.data = (ulong)&rk3588_saradc_data },
{ }
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 69fa9b7..20e33f2 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -5,7 +5,7 @@
obj-$(CONFIG_DWC_AHCI) += dwc_ahci.o
obj-$(CONFIG_AHCI) += ahci-uclass.o
-obj-$(CONFIG_$(XPL_)AHCI_PCI) += ahci-pci.o
+obj-$(CONFIG_$(PHASE_)AHCI_PCI) += ahci-pci.o
obj-$(CONFIG_SCSI_AHCI) += ahci.o
obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o
obj-$(CONFIG_FSL_SATA) += fsl_sata.o
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index e593e22..38e953e 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -420,7 +420,7 @@
static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
{
- phys_addr_t pa = virt_to_phys((void *)pp->cmd_tbl);
+ phys_addr_t pa = virt_to_phys(pp->cmd_tbl);
pp->cmd_slot->opts = cpu_to_le32(opts);
pp->cmd_slot->status = 0;
@@ -449,7 +449,7 @@
{
struct ahci_ioports *pp = &(uc_priv->port[port]);
void __iomem *port_mmio = pp->port_mmio;
- u64 dma_addr;
+ phys_addr_t dma_addr;
u32 port_status;
void __iomem *mem;
@@ -472,34 +472,32 @@
* First item in chunk of DMA memory: 32-slot command table,
* 32 bytes each in size
*/
- pp->cmd_slot =
- (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
- debug("cmd_slot = %p\n", pp->cmd_slot);
- mem += (AHCI_CMD_SLOT_SZ + 224);
+ pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
+ mem += AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT;
/*
* Second item: Received-FIS area
*/
- pp->rx_fis = virt_to_phys((void *)mem);
+ pp->rx_fis = mem;
mem += AHCI_RX_FIS_SZ;
/*
* Third item: data area for storing a single command
* and its scatter-gather table
*/
- pp->cmd_tbl = virt_to_phys((void *)mem);
- debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl);
+ pp->cmd_tbl = mem;
mem += AHCI_CMD_TBL_HDR;
- pp->cmd_tbl_sg =
- (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
+ pp->cmd_tbl_sg = (struct ahci_sg *)(mem);
- dma_addr = (ulong)pp->cmd_slot;
- writel_with_flush(dma_addr, port_mmio + PORT_LST_ADDR);
- writel_with_flush(dma_addr >> 32, port_mmio + PORT_LST_ADDR_HI);
- dma_addr = (ulong)pp->rx_fis;
- writel_with_flush(dma_addr, port_mmio + PORT_FIS_ADDR);
- writel_with_flush(dma_addr >> 32, port_mmio + PORT_FIS_ADDR_HI);
+ dma_addr = virt_to_phys(pp->cmd_slot);
+ debug("cmd_slot_dma = 0x%08llx\n", (u64)dma_addr);
+ writel_with_flush(lower_32_bits(dma_addr), port_mmio + PORT_LST_ADDR);
+ writel_with_flush(upper_32_bits(dma_addr), port_mmio + PORT_LST_ADDR_HI);
+ dma_addr = virt_to_phys(pp->rx_fis);
+ debug("rx_fis_dma = 0x%08llx\n", (u64)dma_addr);
+ writel_with_flush(lower_32_bits(dma_addr), port_mmio + PORT_FIS_ADDR);
+ writel_with_flush(upper_32_bits(dma_addr), port_mmio + PORT_FIS_ADDR_HI);
#ifdef CONFIG_SUNXI_AHCI
sunxi_dma_init(port_mmio);
@@ -735,17 +733,6 @@
is_write ? "WRITE" : "READ");
return -EIO;
}
-
- /* If this transaction is a write, do a following flush.
- * Writes in u-boot are so rare, and the logic to know when is
- * the last write and do a flush only there is sufficiently
- * difficult. Just do a flush after every write. This incurs,
- * usually, one extra flush when the rare writes do happen.
- */
- if (is_write) {
- if (-EIO == ata_io_flush(uc_priv, pccb->target))
- return -EIO;
- }
user_buffer += transfer_size;
user_buffer_size -= transfer_size;
blocks -= now_blocks;
@@ -845,6 +832,9 @@
case SCSI_INQUIRY:
ret = ata_scsiop_inquiry(uc_priv, pccb);
break;
+ case SCSI_SYNC_CACHE:
+ ret = ata_io_flush(uc_priv, pccb->target);
+ break;
default:
printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
return -ENOTSUPP;
diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c
index 203f98e..d225289 100644
--- a/drivers/ata/dwc_ahsata.c
+++ b/drivers/ata/dwc_ahsata.c
@@ -7,6 +7,7 @@
#include <ahci.h>
#include <blk.h>
#include <bootdev.h>
+#include <clk.h>
#include <cpu_func.h>
#include <dm.h>
#include <dwc_ahsata.h>
@@ -19,9 +20,11 @@
#include <sata.h>
#include <asm/cache.h>
#include <asm/io.h>
+#if IS_ENABLED(CONFIG_ARCH_MX5) || IS_ENABLED(CONFIG_ARCH_MX6)
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/sata.h>
+#endif
#include <linux/bitops.h>
#include <linux/ctype.h>
#include <linux/delay.h>
@@ -116,13 +119,12 @@
return 0;
}
-static int ahci_host_init(struct ahci_uc_priv *uc_priv)
+static int ahci_host_init(struct ahci_uc_priv *uc_priv, int clk)
{
u32 tmp, cap_save, num_ports;
int i, j, timeout = 1000;
struct sata_port_regs *port_mmio = NULL;
struct sata_host_regs *host_mmio = uc_priv->mmio_base;
- int clk = mxc_get_clock(MXC_SATA_CLK);
cap_save = readl(&host_mmio->cap);
cap_save |= SATA_HOST_CAP_SSS;
@@ -330,6 +332,7 @@
{
struct ahci_ioports *pp = &uc_priv->port[port];
struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
+ phys_addr_t pa = virt_to_phys(buf);
u32 sg_count, max_bytes;
int i;
@@ -341,9 +344,8 @@
}
for (i = 0; i < sg_count; i++) {
- ahci_sg->addr =
- cpu_to_le32((u32)buf + i * max_bytes);
- ahci_sg->addr_hi = 0;
+ ahci_sg->addr = cpu_to_le32(lower_32_bits(pa));
+ ahci_sg->addr_hi = cpu_to_le32(upper_32_bits(pa));
ahci_sg->flags_size = cpu_to_le32(0x3fffff &
(buf_len < max_bytes
? (buf_len - 1)
@@ -359,14 +361,14 @@
{
struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot +
AHCI_CMD_SLOT_SZ * cmd_slot);
+ phys_addr_t pa = virt_to_phys(pp->cmd_tbl);
memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ);
cmd_hdr->opts = cpu_to_le32(opts);
cmd_hdr->status = 0;
- pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
+ pp->cmd_slot->tbl_addr = cpu_to_le32(lower_32_bits(pa));
#ifdef CONFIG_PHYS_64BIT
- pp->cmd_slot->tbl_addr_hi =
- cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
+ pp->cmd_slot->tbl_addr_hi = cpu_to_le32(upper_32_bits(pa));
#endif
}
@@ -404,7 +406,7 @@
}
ahci_fill_cmd_slot(pp, cmd_slot, opts);
- flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ);
+ flush_cache((ulong)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ);
writel_with_flush(1 << cmd_slot, &port_mmio->ci);
if (waiting_for_cmd_completed((u8 *)&port_mmio->ci, 10000,
@@ -412,8 +414,8 @@
printf("timeout exit!\n");
return -1;
}
- invalidate_dcache_range((int)(pp->cmd_slot),
- (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ);
+ invalidate_dcache_range((ulong)(pp->cmd_slot),
+ (ulong)(pp->cmd_slot) + AHCI_PORT_PRIV_DMA_SZ);
debug("ahci_exec_ata_cmd: %d byte transferred.\n",
pp->cmd_slot->status);
if (!is_write)
@@ -441,8 +443,9 @@
{
struct ahci_ioports *pp = &uc_priv->port[port];
struct sata_port_regs *port_mmio = pp->port_mmio;
+ phys_addr_t dma_addr;
u32 port_status;
- u32 mem;
+ void *mem;
int timeout = 10000000;
debug("Enter start port: %d\n", port);
@@ -453,22 +456,20 @@
return -1;
}
- mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024);
+ mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ);
if (!mem) {
printf("No mem for table!\n");
return -ENOMEM;
}
- mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */
- memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ);
+ memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
/*
* First item in chunk of DMA memory: 32-slot command table,
* 32 bytes each in size
*/
pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
- debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot);
- mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS);
+ mem += AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT;
/*
* Second item: Received-FIS area, 256-Byte aligned
@@ -481,14 +482,19 @@
* and its scatter-gather table
*/
pp->cmd_tbl = mem;
- debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl);
-
mem += AHCI_CMD_TBL_HDR;
+ pp->cmd_tbl_sg = (struct ahci_sg *)mem;
writel_with_flush(0x00004444, &port_mmio->dmacr);
- pp->cmd_tbl_sg = (struct ahci_sg *)mem;
- writel_with_flush((u32)pp->cmd_slot, &port_mmio->clb);
- writel_with_flush(pp->rx_fis, &port_mmio->fb);
+ dma_addr = virt_to_phys(pp->cmd_slot);
+ debug("cmd_slot_dma = 0x%08llx\n", (u64)dma_addr);
+ writel_with_flush(lower_32_bits(dma_addr), &port_mmio->clb);
+ writel_with_flush(upper_32_bits(dma_addr), &port_mmio->clbu);
+ dma_addr = virt_to_phys(pp->cmd_slot);
+ debug("rx_fis_slot_dma = 0x%08llx\n", (u64)dma_addr);
+ writel_with_flush(lower_32_bits(dma_addr), &port_mmio->fb);
+ writel_with_flush(upper_32_bits(dma_addr), &port_mmio->fbu);
+
/* Enable FRE */
writel_with_flush((SATA_PORT_CMD_FRE | readl(&port_mmio->cmd)),
@@ -910,17 +916,41 @@
int dwc_ahsata_probe(struct udevice *dev)
{
struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct clk_bulk clk_bulk __maybe_unused;
+ struct clk clk __maybe_unused;
+ int sataclk;
int ret;
-#if defined(CONFIG_MX6)
+#if IS_ENABLED(CONFIG_MX6)
setup_sata();
#endif
+#if IS_ENABLED(CONFIG_MX5) || IS_ENABLED(CONFIG_MX6)
+ sataclk = mxc_get_clock(MXC_SATA_CLK);
+#else
+ ret = clk_get_bulk(dev, &clk_bulk);
+ if (ret)
+ return ret;
+
+ ret = clk_enable_bulk(&clk_bulk);
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_name(dev, "sata", &clk);
+ if (ret)
+ return ret;
+
+ sataclk = clk_get_rate(&clk);
+#endif
+ if (IS_ERR_VALUE(sataclk)) {
+ log_err("Unable to get SATA clock rate\n");
+ return -EINVAL;
+ }
uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI;
uc_priv->mmio_base = dev_read_addr_ptr(dev);
/* initialize adapter */
- ret = ahci_host_init(uc_priv);
+ ret = ahci_host_init(uc_priv, sataclk);
if (ret)
return ret;
@@ -962,7 +992,6 @@
.ops = &dwc_ahsata_blk_ops,
};
-#if CONFIG_IS_ENABLED(DWC_AHSATA_AHCI)
struct ahci_ops dwc_ahsata_ahci_ops = {
.port_status = dwc_ahsata_port_status,
.reset = dwc_ahsata_bus_reset,
@@ -970,7 +999,9 @@
};
static const struct udevice_id dwc_ahsata_ahci_ids[] = {
+ { .compatible = "fsl,imx53-ahci" },
{ .compatible = "fsl,imx6q-ahci" },
+ { .compatible = "fsl,imx6qp-ahci" },
{ }
};
@@ -981,4 +1012,3 @@
.ops = &dwc_ahsata_ahci_ops,
.probe = dwc_ahsata_probe,
};
-#endif
diff --git a/drivers/ata/dwc_ahsata_priv.h b/drivers/ata/dwc_ahsata_priv.h
index 5b0579a..0c2cd54 100644
--- a/drivers/ata/dwc_ahsata_priv.h
+++ b/drivers/ata/dwc_ahsata_priv.h
@@ -7,8 +7,6 @@
#ifndef __DWC_AHSATA_PRIV_H__
#define __DWC_AHSATA_PRIV_H__
-#define DWC_AHSATA_MAX_CMD_SLOTS 32
-
/* Max host controller numbers */
#define SATA_HC_MAX_NUM 4
/* Max command queue depth per host controller */
diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index ee29062..f5a9d86 100644
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -5,7 +5,7 @@
obj-$(CONFIG_$(PHASE_)BLK) += blk-uclass.o
-ifndef CONFIG_$(XPL_)BLK
+ifndef CONFIG_$(PHASE_)BLK
obj-$(CONFIG_SPL_LEGACY_BLOCK) += blk_legacy.o
endif
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index 7daf824..2d242bc 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -8,4 +8,4 @@
obj-$(CONFIG_UNIPHIER_SYSTEM_BUS) += uniphier-system-bus.o
endif
-obj-$(CONFIG_$(XPL_)TI_SYSC) += ti-sysc.o
+obj-$(CONFIG_$(PHASE_)TI_SYSC) += ti-sysc.o
diff --git a/drivers/button/button-qcom-pmic.c b/drivers/button/button-qcom-pmic.c
index f9f0948..e3bb9bd 100644
--- a/drivers/button/button-qcom-pmic.c
+++ b/drivers/button/button-qcom-pmic.c
@@ -73,25 +73,25 @@
.compatible = "qcom,pm8941-pwrkey",
.status_bit = PON_KPDPWR_N_SET,
.code = KEY_ENTER,
- .label = "pwrkey",
+ .label = "Power Button",
},
{
.compatible = "qcom,pm8941-resin",
.status_bit = PON_RESIN_N_SET,
.code = KEY_DOWN,
- .label = "vol_down",
+ .label = "Volume Down",
},
{
.compatible = "qcom,pmk8350-pwrkey",
.status_bit = PON_GEN3_KPDPWR_N_SET,
.code = KEY_ENTER,
- .label = "pwrkey",
+ .label = "Power Button",
},
{
.compatible = "qcom,pmk8350-resin",
.status_bit = PON_GEN3_RESIN_N_SET,
.code = KEY_DOWN,
- .label = "vol_down",
+ .label = "Volume Down",
},
};
diff --git a/drivers/button/button-uclass.c b/drivers/button/button-uclass.c
index 729983d..0259178 100644
--- a/drivers/button/button-uclass.c
+++ b/drivers/button/button-uclass.c
@@ -21,7 +21,7 @@
struct button_uc_plat *uc_plat = dev_get_uclass_plat(dev);
/* Ignore the top-level button node */
- if (uc_plat->label && !strcmp(label, uc_plat->label))
+ if (uc_plat->label && !strcasecmp(label, uc_plat->label))
return uclass_get_device_tail(dev, 0, devp);
}
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index 9e3b519..207224b 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -155,6 +155,8 @@
goto err;
}
+ composite->dev = dev;
+
if (composite->mux)
composite->mux->dev = clk->dev;
if (composite->rate)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 90b7052..bc4d762 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -572,6 +572,9 @@
clk->rate = 0;
list_for_each_entry(child_dev, &clk->dev->child_head, sibling_node) {
+ if (device_get_uclass_id(child_dev) != UCLASS_CLK)
+ continue;
+
clkp = dev_get_clk_ptr(child_dev);
clk_clean_rate_cache(clkp);
}
@@ -623,14 +626,27 @@
if (!ops->set_parent)
return -ENOSYS;
+ ret = clk_enable(parent);
+ if (ret) {
+ printf("Cannot enable parent %s\n", parent->dev->name);
+ return ret;
+ }
+
ret = ops->set_parent(clk, parent);
- if (ret)
+ if (ret) {
+ clk_disable(parent);
return ret;
+ }
- if (CONFIG_IS_ENABLED(CLK_CCF))
+ if (CONFIG_IS_ENABLED(CLK_CCF)) {
ret = device_reparent(clk->dev, parent->dev);
+ if (ret) {
+ clk_disable(parent);
+ return ret;
+ }
+ }
- return ret;
+ return 0;
}
int clk_enable(struct clk *clk)
diff --git a/drivers/clk/clk_boston.c b/drivers/clk/clk_boston.c
index 030ff7c..71e030f 100644
--- a/drivers/clk/clk_boston.c
+++ b/drivers/clk/clk_boston.c
@@ -58,17 +58,21 @@
.get_rate = clk_boston_get_rate,
};
-static int clk_boston_of_to_plat(struct udevice *dev)
+static int clk_boston_probe(struct udevice *dev)
{
struct clk_boston *state = dev_get_plat(dev);
struct udevice *syscon;
int err;
- err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
- "regmap", &syscon);
- if (err) {
- pr_err("unable to find syscon device\n");
- return err;
+ if (dev->parent && device_get_uclass_id(dev->parent) == UCLASS_SYSCON) {
+ syscon = dev->parent;
+ } else {
+ err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
+ "regmap", &syscon);
+ if (err) {
+ pr_err("unable to find syscon device\n");
+ return err;
+ }
}
state->regmap = syscon_get_regmap(syscon);
@@ -91,7 +95,8 @@
.name = "boston_clock",
.id = UCLASS_CLK,
.of_match = clk_boston_match,
- .of_to_plat = clk_boston_of_to_plat,
+ .probe = clk_boston_probe,
.plat_auto = sizeof(struct clk_boston),
.ops = &clk_boston_ops,
+ .flags = DM_FLAG_PRE_RELOC,
};
diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
index 14c5b92..e1a3c0a 100644
--- a/drivers/clk/imx/clk-composite-8m.c
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -116,14 +116,42 @@
.set_rate = imx8m_clk_composite_divider_set_rate,
};
+static int imx8m_clk_mux_fetch_parent_index(struct udevice *cdev, struct clk *clk, struct clk *parent)
+{
+ struct clk_mux *mux = to_clk_mux(clk);
+ struct clk cclk;
+ int ret;
+ int i;
+
+ if (!parent)
+ return -EINVAL;
+
+ for (i = 0; i < mux->num_parents; i++) {
+ ret = clk_get_by_name(cdev, mux->parent_names[i], &cclk);
+ if (!ret && ofnode_equal(dev_ofnode(parent->dev), dev_ofnode(cclk.dev)))
+ return i;
+
+ if (!strcmp(parent->dev->name, mux->parent_names[i]))
+ return i;
+ if (!strcmp(parent->dev->name,
+ clk_resolve_parent_clk(clk->dev,
+ mux->parent_names[i])))
+ return i;
+ }
+
+ return -EINVAL;
+}
+
+
static int imx8m_clk_mux_set_parent(struct clk *clk, struct clk *parent)
{
struct clk_mux *mux = to_clk_mux(clk);
+ struct clk_composite *composite = (struct clk_composite *)clk->data;
int index;
u32 val;
u32 reg;
- index = clk_mux_fetch_parent_index(clk, parent);
+ index = imx8m_clk_mux_fetch_parent_index(composite->dev, clk, parent);
if (index < 0) {
log_err("Could not fetch index\n");
return index;
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index b81db51..7eb0518 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -81,19 +81,19 @@
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
"audio_pll2_out", "sys_pll1_133m", };
-static const char * const imx8mm_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+static const char * const imx8mm_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
"sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext4",
"audio_pll2_out", };
-static const char * const imx8mm_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+static const char * const imx8mm_uart2_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
"sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext3",
"audio_pll2_out", };
-static const char * const imx8mm_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+static const char * const imx8mm_uart3_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
"sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext4",
"audio_pll2_out", };
-static const char * const imx8mm_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+static const char * const imx8mm_uart4_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
"sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext3",
"audio_pll2_out", };
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index be5b793..2dfa860 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -97,19 +97,19 @@
"sys_pll3_out", "audio_pll1_out", "video_pll_out",
"audio_pll2_out", "sys_pll1_133m", };
-static const char * const imx8mn_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+static const char * const imx8mn_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
"sys_pll2_100m", "sys_pll3_out", "clk_ext2",
"clk_ext4", "audio_pll2_out", };
-static const char * const imx8mn_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+static const char * const imx8mn_uart2_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
"sys_pll2_100m", "sys_pll3_out", "clk_ext2",
"clk_ext3", "audio_pll2_out", };
-static const char * const imx8mn_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+static const char * const imx8mn_uart3_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
"sys_pll2_100m", "sys_pll3_out", "clk_ext2",
"clk_ext4", "audio_pll2_out", };
-static const char * const imx8mn_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+static const char * const imx8mn_uart4_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
"sys_pll2_100m", "sys_pll3_out", "clk_ext2",
"clk_ext3", "audio_pll2_out", };
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index bad579f..3d8ed21 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -14,7 +14,14 @@
#include "clk.h"
+#if CONFIG_IS_ENABLED(VIDEO)
+static u32 share_count_media;
+#endif
+
static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
+#if CONFIG_IS_ENABLED(VIDEO)
+static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
+#endif
static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
@@ -31,6 +38,12 @@
"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
"clk_ext4", "audio_pll2_out", };
+#if CONFIG_IS_ENABLED(VIDEO)
+static const char * const imx8mp_media_isp_sels[] = {"osc_24m", "sys_pll2_1000m", "sys_pll1_800m",
+ "sys_pll3_out", "sys_pll1_400m", "audio_pll2_out",
+ "clk_ext1", "sys_pll2_500m", };
+#endif
+
static const char * const imx8mp_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m",
"sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out",
"video_pll1_out", "sys_pll1_100m",};
@@ -43,6 +56,16 @@
"sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
"sys_pll2_250m", "audio_pll1_out", };
+#if CONFIG_IS_ENABLED(VIDEO)
+static const char * const imx8mp_media_axi_sels[] = {"osc_24m", "sys_pll2_1000m", "sys_pll1_800m",
+ "sys_pll3_out", "sys_pll1_40m", "audio_pll2_out",
+ "clk_ext1", "sys_pll2_500m", };
+
+static const char * const imx8mp_media_apb_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll1_800m",
+ "sys_pll3_out", "sys_pll1_40m", "audio_pll2_out",
+ "clk_ext1", "sys_pll1_133m", };
+#endif
+
static const char * const imx8mp_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out",
"sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
"video_pll1_out", "audio_pll2_out", };
@@ -175,6 +198,17 @@
"sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
"audio_pll2_out", "sys_pll1_100m", };
+#if CONFIG_IS_ENABLED(VIDEO)
+static const char * const imx8mp_media_disp_pix_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out",
+ "audio_pll1_out", "sys_pll1_800m",
+ "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", };
+
+static const char * const imx8mp_media_ldb_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
+ "sys_pll1_800m", "sys_pll2_1000m",
+ "clk_ext2", "audio_pll2_out",
+ "video_pll1_out", };
+#endif
+
static const char * const imx8mp_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m",
"sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
"video_pll1_out", "clk_ext4", };
@@ -199,12 +233,19 @@
clk_dm(IMX8MP_CLK_DUMMY, clk_register_fixed_rate(NULL, "dummy", 0));
+#if CONFIG_IS_ENABLED(VIDEO)
+ clk_dm(IMX8MP_VIDEO_PLL1_REF_SEL, imx_clk_mux(dev, "video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+#endif
clk_dm(IMX8MP_DRAM_PLL_REF_SEL, imx_clk_mux(dev, "dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MP_ARM_PLL_REF_SEL, imx_clk_mux(dev, "arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MP_SYS_PLL1_REF_SEL, imx_clk_mux(dev, "sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MP_SYS_PLL2_REF_SEL, imx_clk_mux(dev, "sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MP_SYS_PLL3_REF_SEL, imx_clk_mux(dev, "sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+#if CONFIG_IS_ENABLED(VIDEO)
+ clk_dm(IMX8MP_VIDEO_PLL1, imx_clk_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28,
+ &imx_1443x_pll));
+#endif
clk_dm(IMX8MP_DRAM_PLL, imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50,
&imx_1443x_dram_pll));
clk_dm(IMX8MP_ARM_PLL, imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84,
@@ -216,12 +257,18 @@
clk_dm(IMX8MP_SYS_PLL3, imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114,
&imx_1416x_pll));
+#if CONFIG_IS_ENABLED(VIDEO)
+ clk_dm(IMX8MP_VIDEO_PLL1_BYPASS, imx_clk_mux_flags(dev, "video_pll1_bypass", base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT));
+#endif
clk_dm(IMX8MP_DRAM_PLL_BYPASS, imx_clk_mux_flags(dev, "dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT));
clk_dm(IMX8MP_ARM_PLL_BYPASS, imx_clk_mux_flags(dev, "arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT));
clk_dm(IMX8MP_SYS_PLL1_BYPASS, imx_clk_mux_flags(dev, "sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT));
clk_dm(IMX8MP_SYS_PLL2_BYPASS, imx_clk_mux_flags(dev, "sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT));
clk_dm(IMX8MP_SYS_PLL3_BYPASS, imx_clk_mux_flags(dev, "sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT));
+#if CONFIG_IS_ENABLED(VIDEO)
+ clk_dm(IMX8MP_VIDEO_PLL1_OUT, imx_clk_gate(dev, "video_pll1_out", "video_pll1_bypass", base + 0x28, 13));
+#endif
clk_dm(IMX8MP_DRAM_PLL_OUT, imx_clk_gate(dev, "dram_pll_out", "dram_pll_bypass", base + 0x50, 13));
clk_dm(IMX8MP_ARM_PLL_OUT, imx_clk_gate(dev, "arm_pll_out", "arm_pll_bypass", base + 0x84, 11));
clk_dm(IMX8MP_SYS_PLL1_OUT, imx_clk_gate(dev, "sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11));
@@ -267,13 +314,23 @@
clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2(dev, "arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3));
clk_dm(IMX8MP_CLK_HSIO_AXI, imx8m_clk_composite(dev, "hsio_axi", imx8mp_hsio_axi_sels, base + 0x8380));
+#if CONFIG_IS_ENABLED(VIDEO)
+ clk_dm(IMX8MP_CLK_MEDIA_ISP, imx8m_clk_composite(dev, "media_isp", imx8mp_media_isp_sels, base + 0x8400));
+#endif
clk_dm(IMX8MP_CLK_MAIN_AXI, imx8m_clk_composite_critical(dev, "main_axi", imx8mp_main_axi_sels, base + 0x8800));
clk_dm(IMX8MP_CLK_ENET_AXI, imx8m_clk_composite_critical(dev, "enet_axi", imx8mp_enet_axi_sels, base + 0x8880));
clk_dm(IMX8MP_CLK_NAND_USDHC_BUS, imx8m_clk_composite_critical(dev, "nand_usdhc_bus", imx8mp_nand_usdhc_sels, base + 0x8900));
+#if CONFIG_IS_ENABLED(VIDEO)
+ clk_dm(IMX8MP_CLK_MEDIA_AXI, imx8m_clk_composite(dev, "media_axi", imx8mp_media_axi_sels, base + 0x8a00));
+ clk_dm(IMX8MP_CLK_MEDIA_APB, imx8m_clk_composite(dev, "media_apb", imx8mp_media_apb_sels, base + 0x8a80));
+#endif
clk_dm(IMX8MP_CLK_NOC, imx8m_clk_composite_critical(dev, "noc", imx8mp_noc_sels, base + 0x8d00));
clk_dm(IMX8MP_CLK_NOC_IO, imx8m_clk_composite_critical(dev, "noc_io", imx8mp_noc_io_sels, base + 0x8d80));
clk_dm(IMX8MP_CLK_AHB, imx8m_clk_composite_critical(dev, "ahb_root", imx8mp_ahb_sels, base + 0x9000));
+#if CONFIG_IS_ENABLED(VIDEO)
+ clk_dm(IMX8MP_CLK_MEDIA_DISP2_PIX, imx8m_clk_composite(dev, "media_disp2_pix", imx8mp_media_disp_pix_sels, base + 0x9300));
+#endif
clk_dm(IMX8MP_CLK_IPG_ROOT, imx_clk_divider2(dev, "ipg_root", "ahb_root", base + 0x9080, 0, 1));
@@ -312,6 +369,10 @@
clk_dm(IMX8MP_CLK_WDOG, imx8m_clk_composite(dev, "wdog", imx8mp_wdog_sels, base + 0xb900));
clk_dm(IMX8MP_CLK_USDHC3, imx8m_clk_composite(dev, "usdhc3", imx8mp_usdhc3_sels, base + 0xbc80));
+#if CONFIG_IS_ENABLED(VIDEO)
+ clk_dm(IMX8MP_CLK_MEDIA_DISP1_PIX, imx8m_clk_composite(dev, "media_disp1_pix", imx8mp_media_disp_pix_sels, base + 0xbe00));
+ clk_dm(IMX8MP_CLK_MEDIA_LDB, imx8m_clk_composite(dev, "media_ldb", imx8mp_media_ldb_sels, base + 0xbf00));
+#endif
clk_dm(IMX8MP_CLK_DRAM_ALT_ROOT, imx_clk_fixed_factor(dev, "dram_alt_root", "dram_alt", 1, 4));
clk_dm(IMX8MP_CLK_DRAM_CORE, imx_clk_mux2_flags(dev, "dram_core_clk", base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL));
@@ -355,6 +416,14 @@
clk_dm(IMX8MP_CLK_WDOG2_ROOT, imx_clk_gate4(dev, "wdog2_root_clk", "wdog", base + 0x4540, 0));
clk_dm(IMX8MP_CLK_WDOG3_ROOT, imx_clk_gate4(dev, "wdog3_root_clk", "wdog", base + 0x4550, 0));
clk_dm(IMX8MP_CLK_HSIO_ROOT, imx_clk_gate4(dev, "hsio_root_clk", "ipg_root", base + 0x45c0, 0));
+#if CONFIG_IS_ENABLED(VIDEO)
+ clk_dm(IMX8MP_CLK_MEDIA_APB_ROOT, imx_clk_gate2_shared2(dev, "media_apb_root_clk", "media_apb", base + 0x45d0, 0, &share_count_media));
+ clk_dm(IMX8MP_CLK_MEDIA_AXI_ROOT, imx_clk_gate2_shared2(dev, "media_axi_root_clk", "media_axi", base + 0x45d0, 0, &share_count_media));
+ clk_dm(IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT, imx_clk_gate2_shared2(dev, "media_disp1_pix_root_clk", "media_disp1_pix", base + 0x45d0, 0, &share_count_media));
+ clk_dm(IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT, imx_clk_gate2_shared2(dev, "media_disp2_pix_root_clk", "media_disp2_pix", base + 0x45d0, 0, &share_count_media));
+ clk_dm(IMX8MP_CLK_MEDIA_LDB_ROOT, imx_clk_gate2_shared2(dev, "media_ldb_root_clk", "media_ldb", base + 0x45d0, 0, &share_count_media));
+ clk_dm(IMX8MP_CLK_MEDIA_ISP_ROOT, imx_clk_gate2_shared2(dev, "media_isp_root_clk", "media_isp", base + 0x45d0, 0, &share_count_media));
+#endif
clk_dm(IMX8MP_CLK_USDHC3_ROOT, imx_clk_gate4(dev, "usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 9e379cc..34b63d4 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -15,7 +15,9 @@
obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
+obj-$(CONFIG_ROCKCHIP_RK3528) += clk_rk3528.o
obj-$(CONFIG_ROCKCHIP_RK3568) += clk_rk3568.o
+obj-$(CONFIG_ROCKCHIP_RK3576) += clk_rk3576.o
obj-$(CONFIG_ROCKCHIP_RK3588) += clk_rk3588.o
obj-$(CONFIG_ROCKCHIP_RV1108) += clk_rv1108.o
obj-$(CONFIG_ROCKCHIP_RV1126) += clk_rv1126.o
diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c
index 44c6f14..9dec40b 100644
--- a/drivers/clk/rockchip/clk_pll.c
+++ b/drivers/clk/rockchip/clk_pll.c
@@ -309,9 +309,11 @@
* When power on or changing PLL setting,
* we must force PLL into slow mode to ensure output stable clock.
*/
- rk_clrsetreg(base + pll->mode_offset,
- pll->mode_mask << pll->mode_shift,
- RKCLK_PLL_MODE_SLOW << pll->mode_shift);
+ if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) {
+ rk_clrsetreg(base + pll->mode_offset,
+ pll->mode_mask << pll->mode_shift,
+ RKCLK_PLL_MODE_SLOW << pll->mode_shift);
+ }
/* Power down */
rk_setreg(base + pll->con_offset + 0x4,
@@ -345,8 +347,11 @@
while (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift)))
udelay(1);
- rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift,
- RKCLK_PLL_MODE_NORMAL << pll->mode_shift);
+ if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) {
+ rk_clrsetreg(base + pll->mode_offset,
+ pll->mode_mask << pll->mode_shift,
+ RKCLK_PLL_MODE_NORMAL << pll->mode_shift);
+ }
debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n",
pll, readl(base + pll->con_offset),
readl(base + pll->con_offset + 0x4),
@@ -362,12 +367,18 @@
u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac;
u32 con = 0, shift, mask;
ulong rate;
+ int mode;
con = readl(base + pll->mode_offset);
shift = pll->mode_shift;
mask = pll->mode_mask << shift;
- switch ((con & mask) >> shift) {
+ if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE))
+ mode = (con & mask) >> shift;
+ else
+ mode = RKCLK_PLL_MODE_NORMAL;
+
+ switch (mode) {
case RKCLK_PLL_MODE_SLOW:
return OSC_HZ;
case RKCLK_PLL_MODE_NORMAL:
diff --git a/drivers/clk/rockchip/clk_rk3528.c b/drivers/clk/rockchip/clk_rk3528.c
new file mode 100644
index 0000000..06f2089
--- /dev/null
+++ b/drivers/clk/rockchip/clk_rk3528.c
@@ -0,0 +1,1754 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ * Author: Joseph Chen <chenjh@rock-chips.com>
+ */
+
+#include <bitfield.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3528.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dt-bindings/clock/rockchip,rk3528-cru.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
+
+/*
+ * PLL attention.
+ *
+ * [FRAC PLL]: GPLL, PPLL, DPLL
+ * - frac mode: refdiv can be 1 or 2 only
+ * - int mode: refdiv has no special limit
+ * - VCO range: [950, 3800] MHZ
+ *
+ * [INT PLL]: CPLL, APLL
+ * - int mode: refdiv can be 1 or 2 only
+ * - VCO range: [475, 1900] MHZ
+ *
+ * [PPLL]: normal mode only.
+ *
+ */
+static struct rockchip_pll_rate_table rk3528_pll_rates[] = {
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+ RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), /* GPLL */
+ RK3036_PLL_RATE(1092000000, 2, 91, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1008000000, 1, 42, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), /* PPLL */
+ RK3036_PLL_RATE(996000000, 2, 83, 1, 1, 1, 0), /* CPLL */
+ RK3036_PLL_RATE(960000000, 1, 40, 1, 1, 1, 0),
+ RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
+ RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
+ RK3036_PLL_RATE(600000000, 1, 50, 2, 1, 1, 0),
+ RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
+ RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
+ RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
+ RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
+ RK3036_PLL_RATE(96000000, 1, 24, 3, 2, 1, 0),
+ { /* sentinel */ },
+};
+
+static struct rockchip_pll_clock rk3528_pll_clks[] = {
+ [APLL] = PLL(pll_rk3328, PLL_APLL, RK3528_PLL_CON(0),
+ RK3528_MODE_CON, 0, 10, 0, rk3528_pll_rates),
+
+ [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3528_PLL_CON(8),
+ RK3528_MODE_CON, 2, 10, 0, rk3528_pll_rates),
+
+ [GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3528_PLL_CON(24),
+ RK3528_MODE_CON, 4, 10, 0, rk3528_pll_rates),
+
+ [PPLL] = PLL(pll_rk3328, PLL_PPLL, RK3528_PCIE_PLL_CON(32),
+ RK3528_MODE_CON, 6, 10, ROCKCHIP_PLL_FIXED_MODE, rk3528_pll_rates),
+
+ [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3528_DDRPHY_PLL_CON(16),
+ RK3528_DDRPHY_MODE_CON, 0, 10, 0, rk3528_pll_rates),
+};
+
+#define RK3528_CPUCLK_RATE(_rate, _aclk_m_core, _pclk_dbg) \
+{ \
+ .rate = _rate##U, \
+ .aclk_div = (_aclk_m_core), \
+ .pclk_div = (_pclk_dbg), \
+}
+
+/* sign-off: _aclk_m_core: 550M, _pclk_dbg: 137.5M, */
+static struct rockchip_cpu_rate_table rk3528_cpu_rates[] = {
+ RK3528_CPUCLK_RATE(1896000000, 1, 13),
+ RK3528_CPUCLK_RATE(1800000000, 1, 12),
+ RK3528_CPUCLK_RATE(1704000000, 1, 11),
+ RK3528_CPUCLK_RATE(1608000000, 1, 11),
+ RK3528_CPUCLK_RATE(1512000000, 1, 11),
+ RK3528_CPUCLK_RATE(1416000000, 1, 9),
+ RK3528_CPUCLK_RATE(1296000000, 1, 8),
+ RK3528_CPUCLK_RATE(1200000000, 1, 8),
+ RK3528_CPUCLK_RATE(1188000000, 1, 8),
+ RK3528_CPUCLK_RATE(1092000000, 1, 7),
+ RK3528_CPUCLK_RATE(1008000000, 1, 6),
+ RK3528_CPUCLK_RATE(1000000000, 1, 6),
+ RK3528_CPUCLK_RATE(996000000, 1, 6),
+ RK3528_CPUCLK_RATE(960000000, 1, 6),
+ RK3528_CPUCLK_RATE(912000000, 1, 6),
+ RK3528_CPUCLK_RATE(816000000, 1, 5),
+ RK3528_CPUCLK_RATE(600000000, 1, 3),
+ RK3528_CPUCLK_RATE(594000000, 1, 3),
+ RK3528_CPUCLK_RATE(408000000, 1, 2),
+ RK3528_CPUCLK_RATE(312000000, 1, 2),
+ RK3528_CPUCLK_RATE(216000000, 1, 1),
+ RK3528_CPUCLK_RATE(96000000, 1, 0),
+};
+
+/*
+ *
+ * rational_best_approximation(31415, 10000,
+ * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
+ *
+ * you may look at given_numerator as a fixed point number,
+ * with the fractional part size described in given_denominator.
+ *
+ * for theoretical background, see:
+ * http://en.wikipedia.org/wiki/Continued_fraction
+ */
+static void rational_best_approximation(unsigned long given_numerator,
+ unsigned long given_denominator,
+ unsigned long max_numerator,
+ unsigned long max_denominator,
+ unsigned long *best_numerator,
+ unsigned long *best_denominator)
+{
+ unsigned long n, d, n0, d0, n1, d1;
+
+ n = given_numerator;
+ d = given_denominator;
+ n0 = 0;
+ d1 = 0;
+ n1 = 1;
+ d0 = 1;
+ for (;;) {
+ unsigned long t, a;
+
+ if (n1 > max_numerator || d1 > max_denominator) {
+ n1 = n0;
+ d1 = d0;
+ break;
+ }
+ if (d == 0)
+ break;
+ t = d;
+ a = n / d;
+ d = n % d;
+ n = t;
+ t = n0 + a * n1;
+ n0 = n1;
+ n1 = t;
+ t = d0 + a * d1;
+ d0 = d1;
+ d1 = t;
+ }
+ *best_numerator = n1;
+ *best_denominator = d1;
+}
+
+static int rk3528_armclk_set_clk(struct rk3528_clk_priv *priv, ulong new_rate)
+{
+ const struct rockchip_cpu_rate_table *rate;
+ struct rk3528_cru *cru = priv->cru;
+ ulong old_rate;
+
+ rate = rockchip_get_cpu_settings(rk3528_cpu_rates, new_rate);
+ if (!rate) {
+ printf("%s unsupported rate\n", __func__);
+ return -EINVAL;
+ }
+
+ /*
+ * set up dependent divisors for DBG and ACLK clocks.
+ */
+ old_rate = rockchip_pll_get_rate(&rk3528_pll_clks[APLL], priv->cru, APLL);
+ if (old_rate > new_rate) {
+ if (rockchip_pll_set_rate(&rk3528_pll_clks[APLL],
+ priv->cru, APLL, new_rate))
+ return -EINVAL;
+
+ rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK,
+ rate->pclk_div << RK3528_DIV_PCLK_DBG_SHIFT);
+
+ rk_clrsetreg(&cru->clksel_con[39], RK3528_DIV_ACLK_M_CORE_MASK,
+ rate->aclk_div << RK3528_DIV_ACLK_M_CORE_SHIFT);
+ } else if (old_rate < new_rate) {
+ rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK,
+ rate->pclk_div << RK3528_DIV_PCLK_DBG_SHIFT);
+
+ rk_clrsetreg(&cru->clksel_con[39], RK3528_DIV_ACLK_M_CORE_MASK,
+ rate->aclk_div << RK3528_DIV_ACLK_M_CORE_SHIFT);
+
+ if (rockchip_pll_set_rate(&rk3528_pll_clks[APLL],
+ priv->cru, APLL, new_rate))
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static ulong rk3528_ppll_matrix_get_rate(struct rk3528_clk_priv *priv,
+ ulong clk_id)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div, mask, shift;
+ void *reg;
+
+ switch (clk_id) {
+ case CLK_PPLL_50M_MATRIX:
+ case CLK_GMAC1_RMII_VPU:
+ mask = PCIE_CLK_MATRIX_50M_SRC_DIV_MASK;
+ shift = PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT;
+ reg = &cru->pcieclksel_con[1];
+ break;
+
+ case CLK_PPLL_100M_MATRIX:
+ mask = PCIE_CLK_MATRIX_100M_SRC_DIV_MASK;
+ shift = PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT;
+ reg = &cru->pcieclksel_con[1];
+ break;
+
+ case CLK_PPLL_125M_MATRIX:
+ case CLK_GMAC1_SRC_VPU:
+ mask = CLK_MATRIX_125M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_125M_SRC_DIV_SHIFT;
+ reg = &cru->clksel_con[60];
+ break;
+
+ case CLK_GMAC1_VPU_25M:
+ mask = CLK_MATRIX_25M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_25M_SRC_DIV_SHIFT;
+ reg = &cru->clksel_con[60];
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ div = (readl(reg) & mask) >> shift;
+
+ return DIV_TO_RATE(priv->ppll_hz, div);
+}
+
+static ulong rk3528_ppll_matrix_set_rate(struct rk3528_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 id, div, mask, shift;
+ u8 is_pciecru = 0;
+
+ switch (clk_id) {
+ case CLK_PPLL_50M_MATRIX:
+ id = 1;
+ mask = PCIE_CLK_MATRIX_50M_SRC_DIV_MASK;
+ shift = PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT;
+ is_pciecru = 1;
+ break;
+
+ case CLK_PPLL_100M_MATRIX:
+ id = 1;
+ mask = PCIE_CLK_MATRIX_100M_SRC_DIV_MASK;
+ shift = PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT;
+ is_pciecru = 1;
+ break;
+
+ case CLK_PPLL_125M_MATRIX:
+ id = 60;
+ mask = CLK_MATRIX_125M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_125M_SRC_DIV_SHIFT;
+ break;
+ case CLK_GMAC1_VPU_25M:
+ id = 60;
+ mask = CLK_MATRIX_25M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_25M_SRC_DIV_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ div = DIV_ROUND_UP(priv->ppll_hz, rate);
+ if (is_pciecru)
+ rk_clrsetreg(&cru->pcieclksel_con[id], mask, (div - 1) << shift);
+ else
+ rk_clrsetreg(&cru->clksel_con[id], mask, (div - 1) << shift);
+
+ return rk3528_ppll_matrix_get_rate(priv, clk_id);
+}
+
+static ulong rk3528_cgpll_matrix_get_rate(struct rk3528_clk_priv *priv,
+ ulong clk_id)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 sel, div, mask, shift, con;
+ u32 sel_mask = 0, sel_shift;
+ u8 is_gpll_parent = 1;
+ u8 is_halfdiv = 0;
+ ulong prate;
+
+ switch (clk_id) {
+ case CLK_MATRIX_50M_SRC:
+ con = 0;
+ mask = CLK_MATRIX_50M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_50M_SRC_DIV_SHIFT;
+ is_gpll_parent = 0;
+ break;
+
+ case CLK_MATRIX_100M_SRC:
+ con = 0;
+ mask = CLK_MATRIX_100M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_100M_SRC_DIV_SHIFT;
+ is_gpll_parent = 0;
+ break;
+
+ case CLK_MATRIX_150M_SRC:
+ con = 1;
+ mask = CLK_MATRIX_150M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_150M_SRC_DIV_SHIFT;
+ break;
+
+ case CLK_MATRIX_200M_SRC:
+ con = 1;
+ mask = CLK_MATRIX_200M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_200M_SRC_DIV_SHIFT;
+ break;
+
+ case CLK_MATRIX_250M_SRC:
+ con = 1;
+ mask = CLK_MATRIX_250M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_250M_SRC_DIV_SHIFT;
+ sel_mask = CLK_MATRIX_250M_SRC_SEL_MASK;
+ sel_shift = CLK_MATRIX_250M_SRC_SEL_SHIFT;
+ break;
+
+ case CLK_MATRIX_300M_SRC:
+ con = 2;
+ mask = CLK_MATRIX_300M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_300M_SRC_DIV_SHIFT;
+ break;
+
+ case CLK_MATRIX_339M_SRC:
+ con = 2;
+ mask = CLK_MATRIX_339M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_339M_SRC_DIV_SHIFT;
+ is_halfdiv = 1;
+ break;
+
+ case CLK_MATRIX_400M_SRC:
+ con = 2;
+ mask = CLK_MATRIX_400M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_400M_SRC_DIV_SHIFT;
+ break;
+
+ case CLK_MATRIX_500M_SRC:
+ con = 3;
+ mask = CLK_MATRIX_500M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_500M_SRC_DIV_SHIFT;
+ sel_mask = CLK_MATRIX_500M_SRC_SEL_MASK;
+ sel_shift = CLK_MATRIX_500M_SRC_SEL_SHIFT;
+ break;
+
+ case CLK_MATRIX_600M_SRC:
+ con = 4;
+ mask = CLK_MATRIX_600M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_600M_SRC_DIV_SHIFT;
+ break;
+
+ case ACLK_BUS_VOPGL_ROOT:
+ case ACLK_BUS_VOPGL_BIU:
+ con = 43;
+ mask = ACLK_BUS_VOPGL_ROOT_DIV_MASK;
+ shift = ACLK_BUS_VOPGL_ROOT_DIV_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ if (sel_mask) {
+ sel = (readl(&cru->clksel_con[con]) & sel_mask) >> sel_shift;
+ if (sel == CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX) // TODO
+ prate = priv->gpll_hz;
+ else
+ prate = priv->cpll_hz;
+ } else {
+ if (is_gpll_parent)
+ prate = priv->gpll_hz;
+ else
+ prate = priv->cpll_hz;
+ }
+
+ div = (readl(&cru->clksel_con[con]) & mask) >> shift;
+
+ /* NOTE: '-1' to balance the DIV_TO_RATE() 'div+1' */
+ return is_halfdiv ? DIV_TO_RATE(prate * 2, (3 + 2 * div) - 1) : DIV_TO_RATE(prate, div);
+}
+
+static ulong rk3528_cgpll_matrix_set_rate(struct rk3528_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 sel, div, mask, shift, con;
+ u32 sel_mask = 0, sel_shift;
+ u8 is_gpll_parent = 1;
+ u8 is_halfdiv = 0;
+ ulong prate = 0;
+
+ switch (clk_id) {
+ case CLK_MATRIX_50M_SRC:
+ con = 0;
+ mask = CLK_MATRIX_50M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_50M_SRC_DIV_SHIFT;
+ is_gpll_parent = 0;
+ break;
+
+ case CLK_MATRIX_100M_SRC:
+ con = 0;
+ mask = CLK_MATRIX_100M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_100M_SRC_DIV_SHIFT;
+ is_gpll_parent = 0;
+ break;
+
+ case CLK_MATRIX_150M_SRC:
+ con = 1;
+ mask = CLK_MATRIX_150M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_150M_SRC_DIV_SHIFT;
+ break;
+
+ case CLK_MATRIX_200M_SRC:
+ con = 1;
+ mask = CLK_MATRIX_200M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_200M_SRC_DIV_SHIFT;
+ break;
+
+ case CLK_MATRIX_250M_SRC:
+ con = 1;
+ mask = CLK_MATRIX_250M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_250M_SRC_DIV_SHIFT;
+ sel_mask = CLK_MATRIX_250M_SRC_SEL_MASK;
+ sel_shift = CLK_MATRIX_250M_SRC_SEL_SHIFT;
+ break;
+
+ case CLK_MATRIX_300M_SRC:
+ con = 2;
+ mask = CLK_MATRIX_300M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_300M_SRC_DIV_SHIFT;
+ break;
+
+ case CLK_MATRIX_339M_SRC:
+ con = 2;
+ mask = CLK_MATRIX_339M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_339M_SRC_DIV_SHIFT;
+ is_halfdiv = 1;
+ break;
+
+ case CLK_MATRIX_400M_SRC:
+ con = 2;
+ mask = CLK_MATRIX_400M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_400M_SRC_DIV_SHIFT;
+ break;
+
+ case CLK_MATRIX_500M_SRC:
+ con = 3;
+ mask = CLK_MATRIX_500M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_500M_SRC_DIV_SHIFT;
+ sel_mask = CLK_MATRIX_500M_SRC_SEL_MASK;
+ sel_shift = CLK_MATRIX_500M_SRC_SEL_SHIFT;
+ break;
+
+ case CLK_MATRIX_600M_SRC:
+ con = 4;
+ mask = CLK_MATRIX_600M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_600M_SRC_DIV_SHIFT;
+ break;
+
+ case ACLK_BUS_VOPGL_ROOT:
+ case ACLK_BUS_VOPGL_BIU:
+ con = 43;
+ mask = ACLK_BUS_VOPGL_ROOT_DIV_MASK;
+ shift = ACLK_BUS_VOPGL_ROOT_DIV_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ if (sel_mask) {
+ if (priv->gpll_hz % rate == 0) {
+ sel = CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX; // TODO
+ prate = priv->gpll_hz;
+ } else {
+ sel = CLK_MATRIX_250M_SRC_SEL_CLK_CPLL_MUX;
+ prate = priv->cpll_hz;
+ }
+ } else {
+ if (is_gpll_parent)
+ prate = priv->gpll_hz;
+ else
+ prate = priv->cpll_hz;
+ }
+
+ if (is_halfdiv)
+ /* NOTE: '+1' to balance the following rk_clrsetreg() 'div-1' */
+ div = DIV_ROUND_UP((prate * 2) - (3 * rate), 2 * rate) + 1;
+ else
+ div = DIV_ROUND_UP(prate, rate);
+
+ rk_clrsetreg(&cru->clksel_con[con], mask, (div - 1) << shift);
+ if (sel_mask)
+ rk_clrsetreg(&cru->clksel_con[con], sel_mask, sel << sel_shift);
+
+ return rk3528_cgpll_matrix_get_rate(priv, clk_id);
+}
+
+static ulong rk3528_i2c_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 id, sel, con, mask, shift;
+ u8 is_pmucru = 0;
+ ulong rate;
+
+ switch (clk_id) {
+ case CLK_I2C0:
+ id = 79;
+ mask = CLK_I2C0_SEL_MASK;
+ shift = CLK_I2C0_SEL_SHIFT;
+ break;
+
+ case CLK_I2C1:
+ id = 79;
+ mask = CLK_I2C1_SEL_MASK;
+ shift = CLK_I2C1_SEL_SHIFT;
+ break;
+
+ case CLK_I2C2:
+ id = 0;
+ mask = CLK_I2C2_SEL_MASK;
+ shift = CLK_I2C2_SEL_SHIFT;
+ is_pmucru = 1;
+ break;
+
+ case CLK_I2C3:
+ id = 63;
+ mask = CLK_I2C3_SEL_MASK;
+ shift = CLK_I2C3_SEL_SHIFT;
+ break;
+
+ case CLK_I2C4:
+ id = 85;
+ mask = CLK_I2C4_SEL_MASK;
+ shift = CLK_I2C4_SEL_SHIFT;
+ break;
+
+ case CLK_I2C5:
+ id = 63;
+ mask = CLK_I2C5_SEL_MASK;
+ shift = CLK_I2C5_SEL_SHIFT;
+ break;
+
+ case CLK_I2C6:
+ id = 64;
+ mask = CLK_I2C6_SEL_MASK;
+ shift = CLK_I2C6_SEL_SHIFT;
+ break;
+
+ case CLK_I2C7:
+ id = 86;
+ mask = CLK_I2C7_SEL_MASK;
+ shift = CLK_I2C7_SEL_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ if (is_pmucru)
+ con = readl(&cru->pmuclksel_con[id]);
+ else
+ con = readl(&cru->clksel_con[id]);
+ sel = (con & mask) >> shift;
+ if (sel == CLK_I2C3_SEL_CLK_MATRIX_200M_SRC)
+ rate = 200 * MHz;
+ else if (sel == CLK_I2C3_SEL_CLK_MATRIX_100M_SRC)
+ rate = 100 * MHz;
+ else if (sel == CLK_I2C3_SEL_CLK_MATRIX_50M_SRC)
+ rate = 50 * MHz;
+ else
+ rate = OSC_HZ;
+
+ return rate;
+}
+
+static ulong rk3528_i2c_set_clk(struct rk3528_clk_priv *priv, ulong clk_id,
+ ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 id, sel, mask, shift;
+ u8 is_pmucru = 0;
+
+ if (rate >= 198 * MHz)
+ sel = CLK_I2C3_SEL_CLK_MATRIX_200M_SRC;
+ else if (rate >= 99 * MHz)
+ sel = CLK_I2C3_SEL_CLK_MATRIX_100M_SRC;
+ else if (rate >= 50 * MHz)
+ sel = CLK_I2C3_SEL_CLK_MATRIX_50M_SRC;
+ else
+ sel = CLK_I2C3_SEL_XIN_OSC0_FUNC;
+
+ switch (clk_id) {
+ case CLK_I2C0:
+ id = 79;
+ mask = CLK_I2C0_SEL_MASK;
+ shift = CLK_I2C0_SEL_SHIFT;
+ break;
+
+ case CLK_I2C1:
+ id = 79;
+ mask = CLK_I2C1_SEL_MASK;
+ shift = CLK_I2C1_SEL_SHIFT;
+ break;
+
+ case CLK_I2C2:
+ id = 0;
+ mask = CLK_I2C2_SEL_MASK;
+ shift = CLK_I2C2_SEL_SHIFT;
+ is_pmucru = 1;
+ break;
+
+ case CLK_I2C3:
+ id = 63;
+ mask = CLK_I2C3_SEL_MASK;
+ shift = CLK_I2C3_SEL_SHIFT;
+ break;
+
+ case CLK_I2C4:
+ id = 85;
+ mask = CLK_I2C4_SEL_MASK;
+ shift = CLK_I2C4_SEL_SHIFT;
+ break;
+
+ case CLK_I2C5:
+ id = 63;
+ mask = CLK_I2C5_SEL_MASK;
+ shift = CLK_I2C5_SEL_SHIFT;
+ break;
+
+ case CLK_I2C6:
+ id = 64;
+ mask = CLK_I2C6_SEL_MASK;
+ shift = CLK_I2C6_SEL_SHIFT;
+ break;
+
+ case CLK_I2C7:
+ id = 86;
+ mask = CLK_I2C7_SEL_MASK;
+ shift = CLK_I2C7_SEL_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ if (is_pmucru)
+ rk_clrsetreg(&cru->pmuclksel_con[id], mask, sel << shift);
+ else
+ rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift);
+
+ return rk3528_i2c_get_clk(priv, clk_id);
+}
+
+static ulong rk3528_spi_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 id, sel, con, mask, shift;
+ ulong rate;
+
+ switch (clk_id) {
+ case CLK_SPI0:
+ id = 79;
+ mask = CLK_SPI0_SEL_MASK;
+ shift = CLK_SPI0_SEL_SHIFT;
+ break;
+
+ case CLK_SPI1:
+ id = 63;
+ mask = CLK_SPI1_SEL_MASK;
+ shift = CLK_SPI1_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ con = readl(&cru->clksel_con[id]);
+ sel = (con & mask) >> shift;
+ if (sel == CLK_SPI1_SEL_CLK_MATRIX_200M_SRC)
+ rate = 200 * MHz;
+ else if (sel == CLK_SPI1_SEL_CLK_MATRIX_100M_SRC)
+ rate = 100 * MHz;
+ else if (sel == CLK_SPI1_SEL_CLK_MATRIX_50M_SRC)
+ rate = 50 * MHz;
+ else
+ rate = OSC_HZ;
+
+ return rate;
+}
+
+static ulong rk3528_spi_set_clk(struct rk3528_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 id, sel, mask, shift;
+
+ if (rate >= 198 * MHz)
+ sel = CLK_SPI1_SEL_CLK_MATRIX_200M_SRC;
+ else if (rate >= 99 * MHz)
+ sel = CLK_SPI1_SEL_CLK_MATRIX_100M_SRC;
+ else if (rate >= 50 * MHz)
+ sel = CLK_SPI1_SEL_CLK_MATRIX_50M_SRC;
+ else
+ sel = CLK_SPI1_SEL_XIN_OSC0_FUNC;
+
+ switch (clk_id) {
+ case CLK_SPI0:
+ id = 79;
+ mask = CLK_SPI0_SEL_MASK;
+ shift = CLK_SPI0_SEL_SHIFT;
+ break;
+
+ case CLK_SPI1:
+ id = 63;
+ mask = CLK_SPI1_SEL_MASK;
+ shift = CLK_SPI1_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift);
+
+ return rk3528_spi_get_clk(priv, clk_id);
+}
+
+static ulong rk3528_pwm_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 id, sel, con, mask, shift;
+ ulong rate;
+
+ switch (clk_id) {
+ case CLK_PWM0:
+ id = 44;
+ mask = CLK_PWM0_SEL_MASK;
+ shift = CLK_PWM0_SEL_SHIFT;
+ break;
+
+ case CLK_PWM1:
+ id = 44;
+ mask = CLK_PWM1_SEL_MASK;
+ shift = CLK_PWM1_SEL_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ con = readl(&cru->clksel_con[id]);
+ sel = (con & mask) >> shift;
+ if (sel == CLK_PWM0_SEL_CLK_MATRIX_100M_SRC)
+ rate = 100 * MHz;
+ if (sel == CLK_PWM0_SEL_CLK_MATRIX_50M_SRC)
+ rate = 50 * MHz;
+ else
+ rate = OSC_HZ;
+
+ return rate;
+}
+
+static ulong rk3528_pwm_set_clk(struct rk3528_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 id, sel, mask, shift;
+
+ if (rate >= 99 * MHz)
+ sel = CLK_PWM0_SEL_CLK_MATRIX_100M_SRC;
+ else if (rate >= 50 * MHz)
+ sel = CLK_PWM0_SEL_CLK_MATRIX_50M_SRC;
+ else
+ sel = CLK_PWM0_SEL_XIN_OSC0_FUNC;
+
+ switch (clk_id) {
+ case CLK_PWM0:
+ id = 44;
+ mask = CLK_PWM0_SEL_MASK;
+ shift = CLK_PWM0_SEL_SHIFT;
+ break;
+
+ case CLK_PWM1:
+ id = 44;
+ mask = CLK_PWM1_SEL_MASK;
+ shift = CLK_PWM1_SEL_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift);
+
+ return rk3528_pwm_get_clk(priv, clk_id);
+}
+
+static ulong rk3528_adc_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div, con;
+
+ con = readl(&cru->clksel_con[74]);
+ switch (clk_id) {
+ case CLK_SARADC:
+ div = (con & CLK_SARADC_DIV_MASK) >>
+ CLK_SARADC_DIV_SHIFT;
+ break;
+
+ case CLK_TSADC_TSEN:
+ div = (con & CLK_TSADC_TSEN_DIV_MASK) >>
+ CLK_TSADC_TSEN_DIV_SHIFT;
+ break;
+
+ case CLK_TSADC:
+ div = (con & CLK_TSADC_DIV_MASK) >>
+ CLK_TSADC_DIV_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ return DIV_TO_RATE(OSC_HZ, div);
+}
+
+static ulong rk3528_adc_set_clk(struct rk3528_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div, mask, shift;
+
+ switch (clk_id) {
+ case CLK_SARADC:
+ mask = CLK_SARADC_DIV_MASK;
+ shift = CLK_SARADC_DIV_SHIFT;
+ break;
+
+ case CLK_TSADC_TSEN:
+ mask = CLK_TSADC_TSEN_DIV_MASK;
+ shift = CLK_TSADC_TSEN_DIV_SHIFT;
+ break;
+
+ case CLK_TSADC:
+ mask = CLK_TSADC_DIV_MASK;
+ shift = CLK_TSADC_DIV_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ div = DIV_ROUND_UP(OSC_HZ, rate);
+ rk_clrsetreg(&cru->clksel_con[74], mask, (div - 1) << shift);
+
+ return rk3528_adc_get_clk(priv, clk_id);
+}
+
+static ulong rk3528_sdmmc_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div, sel, con;
+ ulong prate;
+
+ con = readl(&cru->clksel_con[85]);
+ div = (con & CCLK_SRC_SDMMC0_DIV_MASK) >>
+ CCLK_SRC_SDMMC0_DIV_SHIFT;
+ sel = (con & CCLK_SRC_SDMMC0_SEL_MASK) >>
+ CCLK_SRC_SDMMC0_SEL_SHIFT;
+
+ if (sel == CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX)
+ prate = priv->gpll_hz;
+ else if (sel == CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX)
+ prate = priv->cpll_hz;
+ else
+ prate = OSC_HZ;
+
+ return DIV_TO_RATE(prate, div);
+}
+
+static ulong rk3528_sdmmc_set_clk(struct rk3528_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div, sel;
+
+ if (OSC_HZ % rate == 0) {
+ div = DIV_ROUND_UP(OSC_HZ, rate);
+ sel = CCLK_SRC_SDMMC0_SEL_XIN_OSC0_FUNC;
+ } else if ((priv->cpll_hz % rate) == 0) {
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ sel = CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX;
+ } else {
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ sel = CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX;
+ }
+
+ assert(div - 1 <= 63);
+ rk_clrsetreg(&cru->clksel_con[85],
+ CCLK_SRC_SDMMC0_SEL_MASK |
+ CCLK_SRC_SDMMC0_DIV_MASK,
+ sel << CCLK_SRC_SDMMC0_SEL_SHIFT |
+ (div - 1) << CCLK_SRC_SDMMC0_DIV_SHIFT);
+
+ return rk3528_sdmmc_get_clk(priv, clk_id);
+}
+
+static ulong rk3528_sfc_get_clk(struct rk3528_clk_priv *priv)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div, sel, con, parent;
+
+ con = readl(&cru->clksel_con[61]);
+ div = (con & SCLK_SFC_DIV_MASK) >>
+ SCLK_SFC_DIV_SHIFT;
+ sel = (con & SCLK_SFC_SEL_MASK) >>
+ SCLK_SFC_SEL_SHIFT;
+ if (sel == SCLK_SFC_SEL_CLK_GPLL_MUX)
+ parent = priv->gpll_hz;
+ else if (sel == SCLK_SFC_SEL_CLK_CPLL_MUX)
+ parent = priv->cpll_hz;
+ else
+ parent = OSC_HZ;
+
+ return DIV_TO_RATE(parent, div);
+}
+
+static ulong rk3528_sfc_set_clk(struct rk3528_clk_priv *priv, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ int div, sel;
+
+ if (OSC_HZ % rate == 0) {
+ div = DIV_ROUND_UP(OSC_HZ, rate);
+ sel = SCLK_SFC_SEL_XIN_OSC0_FUNC;
+ } else if ((priv->cpll_hz % rate) == 0) {
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ sel = SCLK_SFC_SEL_CLK_CPLL_MUX;
+ } else {
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ sel = SCLK_SFC_SEL_CLK_GPLL_MUX;
+ }
+
+ assert(div - 1 <= 63);
+ rk_clrsetreg(&cru->clksel_con[61],
+ SCLK_SFC_SEL_MASK |
+ SCLK_SFC_DIV_MASK,
+ sel << SCLK_SFC_SEL_SHIFT |
+ (div - 1) << SCLK_SFC_DIV_SHIFT);
+
+ return rk3528_sfc_get_clk(priv);
+}
+
+static ulong rk3528_emmc_get_clk(struct rk3528_clk_priv *priv)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div, sel, con, parent;
+
+ con = readl(&cru->clksel_con[62]);
+ div = (con & CCLK_SRC_EMMC_DIV_MASK) >>
+ CCLK_SRC_EMMC_DIV_SHIFT;
+ sel = (con & CCLK_SRC_EMMC_SEL_MASK) >>
+ CCLK_SRC_EMMC_SEL_SHIFT;
+
+ if (sel == CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX)
+ parent = priv->gpll_hz;
+ else if (sel == CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX)
+ parent = priv->cpll_hz;
+ else
+ parent = OSC_HZ;
+
+ return DIV_TO_RATE(parent, div);
+}
+
+static ulong rk3528_emmc_set_clk(struct rk3528_clk_priv *priv, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div, sel;
+
+ if (OSC_HZ % rate == 0) {
+ div = DIV_ROUND_UP(OSC_HZ, rate);
+ sel = CCLK_SRC_EMMC_SEL_XIN_OSC0_FUNC;
+ } else if ((priv->cpll_hz % rate) == 0) {
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ sel = CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX;
+ } else {
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ sel = CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX;
+ }
+
+ assert(div - 1 <= 63);
+ rk_clrsetreg(&cru->clksel_con[62],
+ CCLK_SRC_EMMC_SEL_MASK |
+ CCLK_SRC_EMMC_DIV_MASK,
+ sel << CCLK_SRC_EMMC_SEL_SHIFT |
+ (div - 1) << CCLK_SRC_EMMC_DIV_SHIFT);
+
+ return rk3528_emmc_get_clk(priv);
+}
+
+static ulong rk3528_dclk_vop_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div_mask, div_shift;
+ u32 sel_mask, sel_shift;
+ u32 id, con, sel, div;
+ ulong prate;
+
+ switch (clk_id) {
+ case DCLK_VOP0:
+ id = 32;
+ sel_mask = DCLK_VOP_SRC0_SEL_MASK;
+ sel_shift = DCLK_VOP_SRC0_SEL_SHIFT;
+ /* FIXME if need src: clk_hdmiphy_pixel_io */
+ div_mask = DCLK_VOP_SRC0_DIV_MASK;
+ div_shift = DCLK_VOP_SRC0_DIV_SHIFT;
+ break;
+
+ case DCLK_VOP1:
+ id = 33;
+ sel_mask = DCLK_VOP_SRC1_SEL_MASK;
+ sel_shift = DCLK_VOP_SRC1_SEL_SHIFT;
+ div_mask = DCLK_VOP_SRC1_DIV_MASK;
+ div_shift = DCLK_VOP_SRC1_DIV_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ con = readl(&cru->clksel_con[id]);
+ div = (con & div_mask) >> div_shift;
+ sel = (con & sel_mask) >> sel_shift;
+ if (sel == DCLK_VOP_SRC_SEL_CLK_GPLL_MUX)
+ prate = priv->gpll_hz;
+ else
+ prate = priv->cpll_hz;
+
+ return DIV_TO_RATE(prate, div);
+}
+
+static ulong rk3528_dclk_vop_set_clk(struct rk3528_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div_mask, div_shift;
+ u32 sel_mask, sel_shift;
+ u32 id, sel, div;
+ ulong prate;
+
+ switch (clk_id) {
+ case DCLK_VOP0:
+ id = 32;
+ sel_mask = DCLK_VOP_SRC0_SEL_MASK;
+ sel_shift = DCLK_VOP_SRC0_SEL_SHIFT;
+ /* FIXME if need src: clk_hdmiphy_pixel_io */
+ div_mask = DCLK_VOP_SRC0_DIV_MASK;
+ div_shift = DCLK_VOP_SRC0_DIV_SHIFT;
+ break;
+
+ case DCLK_VOP1:
+ id = 33;
+ sel_mask = DCLK_VOP_SRC1_SEL_MASK;
+ sel_shift = DCLK_VOP_SRC1_SEL_SHIFT;
+ div_mask = DCLK_VOP_SRC1_DIV_MASK;
+ div_shift = DCLK_VOP_SRC1_DIV_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ if ((priv->gpll_hz % rate) == 0) {
+ prate = priv->gpll_hz;
+ sel = (DCLK_VOP_SRC_SEL_CLK_GPLL_MUX << sel_shift) & sel_mask;
+ } else {
+ prate = priv->cpll_hz;
+ sel = (DCLK_VOP_SRC_SEL_CLK_CPLL_MUX << sel_shift) & sel_mask;
+ }
+
+ div = ((DIV_ROUND_UP(prate, rate) - 1) << div_shift) & div_mask;
+ rk_clrsetreg(&cru->clksel_con[id], sel, div);
+
+ return rk3528_dclk_vop_get_clk(priv, clk_id);
+}
+
+static ulong rk3528_uart_get_rate(struct rk3528_clk_priv *priv, ulong clk_id)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 sel_shift, sel_mask, div_shift, div_mask;
+ u32 sel, id, con, frac_div, div;
+ ulong m, n, rate;
+
+ switch (clk_id) {
+ case SCLK_UART0:
+ id = 6;
+ sel_shift = SCLK_UART0_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART0_SRC_SEL_MASK;
+ div_shift = CLK_UART0_SRC_DIV_SHIFT;
+ div_mask = CLK_UART0_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART1:
+ id = 8;
+ sel_shift = SCLK_UART1_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART1_SRC_SEL_MASK;
+ div_shift = CLK_UART1_SRC_DIV_SHIFT;
+ div_mask = CLK_UART1_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART2:
+ id = 10;
+ sel_shift = SCLK_UART2_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART2_SRC_SEL_MASK;
+ div_shift = CLK_UART2_SRC_DIV_SHIFT;
+ div_mask = CLK_UART2_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART3:
+ id = 12;
+ sel_shift = SCLK_UART3_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART3_SRC_SEL_MASK;
+ div_shift = CLK_UART3_SRC_DIV_SHIFT;
+ div_mask = CLK_UART3_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART4:
+ id = 14;
+ sel_shift = SCLK_UART4_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART4_SRC_SEL_MASK;
+ div_shift = CLK_UART4_SRC_DIV_SHIFT;
+ div_mask = CLK_UART4_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART5:
+ id = 16;
+ sel_shift = SCLK_UART5_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART5_SRC_SEL_MASK;
+ div_shift = CLK_UART5_SRC_DIV_SHIFT;
+ div_mask = CLK_UART5_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART6:
+ id = 18;
+ sel_shift = SCLK_UART6_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART6_SRC_SEL_MASK;
+ div_shift = CLK_UART6_SRC_DIV_SHIFT;
+ div_mask = CLK_UART6_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART7:
+ id = 20;
+ sel_shift = SCLK_UART7_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART7_SRC_SEL_MASK;
+ div_shift = CLK_UART7_SRC_DIV_SHIFT;
+ div_mask = CLK_UART7_SRC_DIV_MASK;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ con = readl(&cru->clksel_con[id - 2]);
+ div = (con & div_mask) >> div_shift;
+
+ con = readl(&cru->clksel_con[id]);
+ sel = (con & sel_mask) >> sel_shift;
+
+ if (sel == SCLK_UART0_SRC_SEL_CLK_UART0_SRC) {
+ rate = DIV_TO_RATE(priv->gpll_hz, div);
+ } else if (sel == SCLK_UART0_SRC_SEL_CLK_UART0_FRAC) {
+ frac_div = readl(&cru->clksel_con[id - 1]);
+ n = (frac_div & 0xffff0000) >> 16;
+ m = frac_div & 0x0000ffff;
+ rate = DIV_TO_RATE(priv->gpll_hz, div) * n / m;
+ } else {
+ rate = OSC_HZ;
+ }
+
+ return rate;
+}
+
+static ulong rk3528_uart_set_rate(struct rk3528_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 sel_shift, sel_mask, div_shift, div_mask;
+ u32 sel, id, div;
+ ulong m = 0, n = 0, val;
+
+ if (rate == OSC_HZ) {
+ sel = SCLK_UART0_SRC_SEL_XIN_OSC0_FUNC;
+ div = DIV_ROUND_UP(OSC_HZ, rate);
+ } else if (priv->gpll_hz % rate == 0) {
+ sel = SCLK_UART0_SRC_SEL_CLK_UART0_SRC;
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ } else {
+ sel = SCLK_UART0_SRC_SEL_CLK_UART0_FRAC;
+ div = 2;
+ rational_best_approximation(rate, priv->gpll_hz / div,
+ GENMASK(16 - 1, 0),
+ GENMASK(16 - 1, 0),
+ &n, &m);
+ }
+
+ switch (clk_id) {
+ case SCLK_UART0:
+ id = 6;
+ sel_shift = SCLK_UART0_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART0_SRC_SEL_MASK;
+ div_shift = CLK_UART0_SRC_DIV_SHIFT;
+ div_mask = CLK_UART0_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART1:
+ id = 8;
+ sel_shift = SCLK_UART1_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART1_SRC_SEL_MASK;
+ div_shift = CLK_UART1_SRC_DIV_SHIFT;
+ div_mask = CLK_UART1_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART2:
+ id = 10;
+ sel_shift = SCLK_UART2_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART2_SRC_SEL_MASK;
+ div_shift = CLK_UART2_SRC_DIV_SHIFT;
+ div_mask = CLK_UART2_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART3:
+ id = 12;
+ sel_shift = SCLK_UART3_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART3_SRC_SEL_MASK;
+ div_shift = CLK_UART3_SRC_DIV_SHIFT;
+ div_mask = CLK_UART3_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART4:
+ id = 14;
+ sel_shift = SCLK_UART4_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART4_SRC_SEL_MASK;
+ div_shift = CLK_UART4_SRC_DIV_SHIFT;
+ div_mask = CLK_UART4_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART5:
+ id = 16;
+ sel_shift = SCLK_UART5_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART5_SRC_SEL_MASK;
+ div_shift = CLK_UART5_SRC_DIV_SHIFT;
+ div_mask = CLK_UART5_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART6:
+ id = 18;
+ sel_shift = SCLK_UART6_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART6_SRC_SEL_MASK;
+ div_shift = CLK_UART6_SRC_DIV_SHIFT;
+ div_mask = CLK_UART6_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART7:
+ id = 20;
+ sel_shift = SCLK_UART7_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART7_SRC_SEL_MASK;
+ div_shift = CLK_UART7_SRC_DIV_SHIFT;
+ div_mask = CLK_UART7_SRC_DIV_MASK;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ rk_clrsetreg(&cru->clksel_con[id - 2], div_mask, (div - 1) << div_shift);
+ rk_clrsetreg(&cru->clksel_con[id], sel_mask, sel << sel_shift);
+ if (m && n) {
+ val = n << 16 | m;
+ writel(val, &cru->clksel_con[id - 1]);
+ }
+
+ return rk3528_uart_get_rate(priv, clk_id);
+}
+
+static ulong rk3528_clk_get_rate(struct clk *clk)
+{
+ struct rk3528_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong rate = 0;
+
+ if (!priv->gpll_hz || !priv->cpll_hz) {
+ printf("%s: gpll=%lu, cpll=%ld\n",
+ __func__, priv->gpll_hz, priv->cpll_hz);
+ return -ENOENT;
+ }
+
+ switch (clk->id) {
+ case PLL_APLL:
+ case ARMCLK:
+ rate = rockchip_pll_get_rate(&rk3528_pll_clks[APLL], priv->cru,
+ APLL);
+ break;
+ case PLL_CPLL:
+ rate = rockchip_pll_get_rate(&rk3528_pll_clks[CPLL], priv->cru,
+ CPLL);
+ break;
+ case PLL_GPLL:
+ rate = rockchip_pll_get_rate(&rk3528_pll_clks[GPLL], priv->cru,
+ GPLL);
+ break;
+
+ case PLL_PPLL:
+ rate = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL], priv->cru,
+ PPLL);
+ break;
+ case PLL_DPLL:
+ rate = rockchip_pll_get_rate(&rk3528_pll_clks[DPLL], priv->cru,
+ DPLL);
+ break;
+
+ case TCLK_EMMC:
+ case TCLK_WDT_NS:
+ rate = OSC_HZ;
+ break;
+ case CLK_I2C0:
+ case CLK_I2C1:
+ case CLK_I2C2:
+ case CLK_I2C3:
+ case CLK_I2C4:
+ case CLK_I2C5:
+ case CLK_I2C6:
+ case CLK_I2C7:
+ rate = rk3528_i2c_get_clk(priv, clk->id);
+ break;
+ case CLK_SPI0:
+ case CLK_SPI1:
+ rate = rk3528_spi_get_clk(priv, clk->id);
+ break;
+ case CLK_PWM0:
+ case CLK_PWM1:
+ rate = rk3528_pwm_get_clk(priv, clk->id);
+ break;
+ case CLK_SARADC:
+ case CLK_TSADC:
+ case CLK_TSADC_TSEN:
+ rate = rk3528_adc_get_clk(priv, clk->id);
+ break;
+ case CCLK_SRC_EMMC:
+ rate = rk3528_emmc_get_clk(priv);
+ break;
+ case HCLK_SDMMC0:
+ case CCLK_SRC_SDMMC0:
+ rate = rk3528_sdmmc_get_clk(priv, clk->id);
+ break;
+ case SCLK_SFC:
+ rate = rk3528_sfc_get_clk(priv);
+ break;
+ case DCLK_VOP0:
+ case DCLK_VOP1:
+ rate = rk3528_dclk_vop_get_clk(priv, clk->id);
+ break;
+ case DCLK_CVBS:
+ rate = rk3528_dclk_vop_get_clk(priv, DCLK_VOP1) / 4;
+ break;
+ case DCLK_4X_CVBS:
+ rate = rk3528_dclk_vop_get_clk(priv, DCLK_VOP1);
+ break;
+ case SCLK_UART0:
+ case SCLK_UART1:
+ case SCLK_UART2:
+ case SCLK_UART3:
+ case SCLK_UART4:
+ case SCLK_UART5:
+ case SCLK_UART6:
+ case SCLK_UART7:
+ rate = rk3528_uart_get_rate(priv, clk->id);
+ break;
+ case CLK_MATRIX_50M_SRC:
+ case CLK_MATRIX_100M_SRC:
+ case CLK_MATRIX_150M_SRC:
+ case CLK_MATRIX_200M_SRC:
+ case CLK_MATRIX_250M_SRC:
+ case CLK_MATRIX_300M_SRC:
+ case CLK_MATRIX_339M_SRC:
+ case CLK_MATRIX_400M_SRC:
+ case CLK_MATRIX_500M_SRC:
+ case CLK_MATRIX_600M_SRC:
+ case ACLK_BUS_VOPGL_BIU:
+ rate = rk3528_cgpll_matrix_get_rate(priv, clk->id);
+ break;
+ case CLK_PPLL_50M_MATRIX:
+ case CLK_PPLL_100M_MATRIX:
+ case CLK_PPLL_125M_MATRIX:
+ case CLK_GMAC1_VPU_25M:
+ case CLK_GMAC1_RMII_VPU:
+ case CLK_GMAC1_SRC_VPU:
+ rate = rk3528_ppll_matrix_get_rate(priv, clk->id);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rate;
+};
+
+static ulong rk3528_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct rk3528_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong ret = 0;
+
+ if (!priv->gpll_hz) {
+ printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
+ return -ENOENT;
+ }
+
+ switch (clk->id) {
+ case PLL_APLL:
+ case ARMCLK:
+ if (priv->armclk_hz)
+ rk3528_armclk_set_clk(priv, rate);
+ priv->armclk_hz = rate;
+ break;
+ case PLL_CPLL:
+ ret = rockchip_pll_set_rate(&rk3528_pll_clks[CPLL], priv->cru,
+ CPLL, rate);
+ priv->cpll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[CPLL],
+ priv->cru, CPLL);
+ break;
+ case PLL_GPLL:
+ ret = rockchip_pll_set_rate(&rk3528_pll_clks[GPLL], priv->cru,
+ GPLL, rate);
+ priv->gpll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[GPLL],
+ priv->cru, GPLL);
+ break;
+ case PLL_PPLL:
+ ret = rockchip_pll_set_rate(&rk3528_pll_clks[PPLL], priv->cru,
+ PPLL, rate);
+ priv->ppll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL],
+ priv->cru, PPLL);
+ break;
+ case TCLK_EMMC:
+ case TCLK_WDT_NS:
+ return (rate == OSC_HZ) ? 0 : -EINVAL;
+ case CLK_I2C0:
+ case CLK_I2C1:
+ case CLK_I2C2:
+ case CLK_I2C3:
+ case CLK_I2C4:
+ case CLK_I2C5:
+ case CLK_I2C6:
+ case CLK_I2C7:
+ ret = rk3528_i2c_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_SPI0:
+ case CLK_SPI1:
+ ret = rk3528_spi_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_PWM0:
+ case CLK_PWM1:
+ ret = rk3528_pwm_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_SARADC:
+ case CLK_TSADC:
+ case CLK_TSADC_TSEN:
+ ret = rk3528_adc_set_clk(priv, clk->id, rate);
+ break;
+ case HCLK_SDMMC0:
+ case CCLK_SRC_SDMMC0:
+ ret = rk3528_sdmmc_set_clk(priv, clk->id, rate);
+ break;
+ case SCLK_SFC:
+ ret = rk3528_sfc_set_clk(priv, rate);
+ break;
+ case CCLK_SRC_EMMC:
+ ret = rk3528_emmc_set_clk(priv, rate);
+ break;
+ case DCLK_VOP0:
+ case DCLK_VOP1:
+ ret = rk3528_dclk_vop_set_clk(priv, clk->id, rate);
+ break;
+ case SCLK_UART0:
+ case SCLK_UART1:
+ case SCLK_UART2:
+ case SCLK_UART3:
+ case SCLK_UART4:
+ case SCLK_UART5:
+ case SCLK_UART6:
+ case SCLK_UART7:
+ ret = rk3528_uart_set_rate(priv, clk->id, rate);
+ break;
+ case CLK_MATRIX_50M_SRC:
+ case CLK_MATRIX_100M_SRC:
+ case CLK_MATRIX_150M_SRC:
+ case CLK_MATRIX_200M_SRC:
+ case CLK_MATRIX_250M_SRC:
+ case CLK_MATRIX_300M_SRC:
+ case CLK_MATRIX_339M_SRC:
+ case CLK_MATRIX_400M_SRC:
+ case CLK_MATRIX_500M_SRC:
+ case CLK_MATRIX_600M_SRC:
+ case ACLK_BUS_VOPGL_BIU:
+ ret = rk3528_cgpll_matrix_set_rate(priv, clk->id, rate);
+ break;
+ case CLK_PPLL_50M_MATRIX:
+ case CLK_PPLL_100M_MATRIX:
+ case CLK_PPLL_125M_MATRIX:
+ case CLK_GMAC1_VPU_25M:
+ ret = rk3528_ppll_matrix_set_rate(priv, clk->id, rate);
+ break;
+ case CLK_GMAC1_RMII_VPU:
+ case CLK_GMAC1_SRC_VPU:
+ /* dummy set */
+ ret = rk3528_ppll_matrix_get_rate(priv, clk->id);
+ break;
+
+ /* Might occur in cru assigned-clocks, can be ignored here */
+ case ACLK_BUS_VOPGL_ROOT:
+ case BCLK_EMMC:
+ case XIN_OSC0_DIV:
+ ret = 0;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return ret;
+};
+
+static struct clk_ops rk3528_clk_ops = {
+ .get_rate = rk3528_clk_get_rate,
+ .set_rate = rk3528_clk_set_rate,
+};
+
+#ifdef CONFIG_XPL_BUILD
+
+#define COREGRF_BASE 0xff300000
+#define PVTPLL_CON0_L 0x0
+#define PVTPLL_CON0_H 0x4
+
+static int rk3528_cpu_pvtpll_set_rate(struct rk3528_clk_priv *priv, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 length;
+
+ if (rate >= 1200000000)
+ length = 8;
+ else if (rate >= 1008000000)
+ length = 11;
+ else
+ length = 17;
+
+ /* set pclk dbg div to 9 */
+ rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK,
+ 9 << RK3528_DIV_PCLK_DBG_SHIFT);
+ /* set aclk_m_core div to 1 */
+ rk_clrsetreg(&cru->clksel_con[39], RK3528_DIV_ACLK_M_CORE_MASK,
+ 1 << RK3528_DIV_ACLK_M_CORE_SHIFT);
+
+ /* set ring sel = 1 */
+ writel(0x07000000 | (1 << 8), COREGRF_BASE + PVTPLL_CON0_L);
+ /* set length */
+ writel(0x007f0000 | length, COREGRF_BASE + PVTPLL_CON0_H);
+ /* enable pvtpll */
+ writel(0x00020002, COREGRF_BASE + PVTPLL_CON0_L);
+ /* start monitor */
+ writel(0x00010001, COREGRF_BASE + PVTPLL_CON0_L);
+
+ /* set core mux pvtpll */
+ writel(0x00010001, &cru->clksel_con[40]);
+ writel(0x00100010, &cru->clksel_con[39]);
+
+ /* set pclk dbg div to 8 */
+ rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK,
+ 8 << RK3528_DIV_PCLK_DBG_SHIFT);
+
+ return 0;
+}
+#endif
+
+static int rk3528_clk_init(struct rk3528_clk_priv *priv)
+{
+ int ret;
+
+ priv->sync_kernel = false;
+
+#ifdef CONFIG_XPL_BUILD
+ /*
+ * BOOTROM:
+ * CPU 1902/2(postdiv1)=546M
+ * CPLL 996/2(postdiv1)=498M
+ * GPLL 1188/2(postdiv1)=594M
+ * |-- clk_matrix_200m_src_div=1 => rate: 300M
+ * |-- clk_matrix_300m_src_div=2 => rate: 200M
+ *
+ * Avoid overclocking when change GPLL rate:
+ * Change clk_matrix_200m_src_div to 5.
+ * Change clk_matrix_300m_src_div to 3.
+ */
+ writel(0x01200120, &priv->cru->clksel_con[1]);
+ writel(0x00030003, &priv->cru->clksel_con[2]);
+
+ if (!priv->armclk_enter_hz) {
+ priv->armclk_enter_hz =
+ rockchip_pll_get_rate(&rk3528_pll_clks[APLL],
+ priv->cru, APLL);
+ priv->armclk_init_hz = priv->armclk_enter_hz;
+ }
+
+ if (priv->armclk_init_hz != APLL_HZ) {
+ ret = rk3528_armclk_set_clk(priv, APLL_HZ);
+ if (!ret)
+ priv->armclk_init_hz = APLL_HZ;
+ }
+
+ if (!rk3528_cpu_pvtpll_set_rate(priv, CPU_PVTPLL_HZ)) {
+ debug("cpu pvtpll %d KHz\n", CPU_PVTPLL_HZ / 1000);
+ priv->armclk_init_hz = CPU_PVTPLL_HZ;
+ }
+#endif
+
+ if (priv->cpll_hz != CPLL_HZ) {
+ ret = rockchip_pll_set_rate(&rk3528_pll_clks[CPLL], priv->cru,
+ CPLL, CPLL_HZ);
+ if (!ret)
+ priv->cpll_hz = CPLL_HZ;
+ }
+
+ if (priv->gpll_hz != GPLL_HZ) {
+ ret = rockchip_pll_set_rate(&rk3528_pll_clks[GPLL], priv->cru,
+ GPLL, GPLL_HZ);
+ if (!ret)
+ priv->gpll_hz = GPLL_HZ;
+ }
+
+ if (priv->ppll_hz != PPLL_HZ) {
+ ret = rockchip_pll_set_rate(&rk3528_pll_clks[PPLL], priv->cru,
+ PPLL, PPLL_HZ);
+ if (!ret)
+ priv->ppll_hz = PPLL_HZ;
+ }
+
+#ifdef CONFIG_XPL_BUILD
+ /* Init to override bootrom config */
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_50M_SRC, 50000000);
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_100M_SRC, 100000000);
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_150M_SRC, 150000000);
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_200M_SRC, 200000000);
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_250M_SRC, 250000000);
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_300M_SRC, 300000000);
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_339M_SRC, 340000000);
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_400M_SRC, 400000000);
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_500M_SRC, 500000000);
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_600M_SRC, 600000000);
+ rk3528_cgpll_matrix_set_rate(priv, ACLK_BUS_VOPGL_BIU, 500000000);
+
+ /* The default rate is 100Mhz, it's not friendly for remote IR module */
+ rk3528_pwm_set_clk(priv, CLK_PWM0, 24000000);
+ rk3528_pwm_set_clk(priv, CLK_PWM1, 24000000);
+#endif
+ return 0;
+}
+
+static int rk3528_clk_probe(struct udevice *dev)
+{
+ struct rk3528_clk_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = rk3528_clk_init(priv);
+ if (ret)
+ return ret;
+
+ /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
+ ret = clk_set_defaults(dev, 1);
+ if (ret)
+ debug("%s clk_set_defaults failed %d\n", __func__, ret);
+ else
+ priv->sync_kernel = true;
+
+ return 0;
+}
+
+static int rk3528_clk_ofdata_to_platdata(struct udevice *dev)
+{
+ struct rk3528_clk_priv *priv = dev_get_priv(dev);
+
+ priv->cru = dev_read_addr_ptr(dev);
+
+ return 0;
+}
+
+static int rk3528_clk_bind(struct udevice *dev)
+{
+ struct udevice *sys_child;
+ struct sysreset_reg *priv;
+ int ret;
+
+ /* The reset driver does not have a device node, so bind it here */
+ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
+ &sys_child);
+ if (ret) {
+ debug("Warning: No sysreset driver: ret=%d\n", ret);
+ } else {
+ priv = malloc(sizeof(struct sysreset_reg));
+ priv->glb_srst_fst_value = offsetof(struct rk3528_cru,
+ glb_srst_fst);
+ priv->glb_srst_snd_value = offsetof(struct rk3528_cru,
+ glb_srst_snd);
+ dev_set_priv(sys_child, priv);
+ }
+
+#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
+ ret = offsetof(struct rk3528_cru, softrst_con[0]);
+ ret = rk3528_reset_bind_lut(dev, ret, 47);
+ if (ret)
+ debug("Warning: software reset driver bind failed\n");
+#endif
+
+ return 0;
+}
+
+static const struct udevice_id rk3528_clk_ids[] = {
+ { .compatible = "rockchip,rk3528-cru" },
+ { }
+};
+
+U_BOOT_DRIVER(rockchip_rk3528_cru) = {
+ .name = "rockchip_rk3528_cru",
+ .id = UCLASS_CLK,
+ .of_match = rk3528_clk_ids,
+ .priv_auto = sizeof(struct rk3528_clk_priv),
+ .of_to_plat = rk3528_clk_ofdata_to_platdata,
+ .ops = &rk3528_clk_ops,
+ .bind = rk3528_clk_bind,
+ .probe = rk3528_clk_probe,
+};
diff --git a/drivers/clk/rockchip/clk_rk3576.c b/drivers/clk/rockchip/clk_rk3576.c
new file mode 100644
index 0000000..e84a094
--- /dev/null
+++ b/drivers/clk/rockchip/clk_rk3576.c
@@ -0,0 +1,2513 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#include <bitfield.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/cru_rk3576.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dt-bindings/clock/rockchip,rk3576-cru.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
+
+static struct rockchip_pll_rate_table rk3576_24m_pll_rates[] = {
+ /* _mhz, _p, _m, _s, _k */
+ RK3588_PLL_RATE(1500000000, 2, 250, 1, 0),
+ RK3588_PLL_RATE(1200000000, 1, 100, 1, 0),
+ RK3588_PLL_RATE(1188000000, 2, 198, 1, 0),
+ RK3588_PLL_RATE(1150000000, 3, 575, 2, 0),
+ RK3588_PLL_RATE(1100000000, 3, 550, 2, 0),
+ RK3588_PLL_RATE(1008000000, 2, 336, 2, 0),
+ RK3588_PLL_RATE(1000000000, 3, 500, 2, 0),
+ RK3588_PLL_RATE(900000000, 2, 300, 2, 0),
+ RK3588_PLL_RATE(850000000, 3, 425, 2, 0),
+ RK3588_PLL_RATE(816000000, 2, 272, 2, 0),
+ RK3588_PLL_RATE(786432000, 2, 262, 2, 9437),
+ RK3588_PLL_RATE(786000000, 1, 131, 2, 0),
+ RK3588_PLL_RATE(742500000, 4, 495, 2, 0),
+ RK3588_PLL_RATE(722534400, 8, 963, 2, 24850),
+ RK3588_PLL_RATE(600000000, 2, 200, 2, 0),
+ RK3588_PLL_RATE(594000000, 2, 198, 2, 0),
+ RK3588_PLL_RATE(200000000, 3, 400, 4, 0),
+ RK3588_PLL_RATE(100000000, 3, 400, 5, 0),
+ { /* sentinel */ },
+};
+
+static struct rockchip_pll_clock rk3576_pll_clks[] = {
+ [BPLL] = PLL(pll_rk3588, PLL_BPLL, RK3576_PLL_CON(0),
+ RK3576_BPLL_MODE_CON0, 0, 15, 0,
+ rk3576_24m_pll_rates),
+ [LPLL] = PLL(pll_rk3588, PLL_LPLL, RK3576_LPLL_CON(16),
+ RK3576_LPLL_MODE_CON0, 0, 15, 0, rk3576_24m_pll_rates),
+ [VPLL] = PLL(pll_rk3588, PLL_VPLL, RK3576_PLL_CON(88),
+ RK3576_LPLL_MODE_CON0, 4, 15, 0, rk3576_24m_pll_rates),
+ [AUPLL] = PLL(pll_rk3588, PLL_AUPLL, RK3576_PLL_CON(96),
+ RK3576_MODE_CON0, 6, 15, 0, rk3576_24m_pll_rates),
+ [CPLL] = PLL(pll_rk3588, PLL_CPLL, RK3576_PLL_CON(104),
+ RK3576_MODE_CON0, 8, 15, 0, rk3576_24m_pll_rates),
+ [GPLL] = PLL(pll_rk3588, PLL_GPLL, RK3576_PLL_CON(112),
+ RK3576_MODE_CON0, 2, 15, 0, rk3576_24m_pll_rates),
+ [PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3576_PMU_PLL_CON(128),
+ RK3576_MODE_CON0, 10, 15, 0, rk3576_24m_pll_rates),
+};
+
+#ifdef CONFIG_SPL_BUILD
+#ifndef BITS_WITH_WMASK
+#define BITS_WITH_WMASK(bits, msk, shift) \
+ ((bits) << (shift)) | ((msk) << ((shift) + 16))
+#endif
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ *
+ * rational_best_approximation(31415, 10000,
+ * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
+ *
+ * you may look at given_numerator as a fixed point number,
+ * with the fractional part size described in given_denominator.
+ *
+ * for theoretical background, see:
+ * http://en.wikipedia.org/wiki/Continued_fraction
+ */
+static void rational_best_approximation(unsigned long given_numerator,
+ unsigned long given_denominator,
+ unsigned long max_numerator,
+ unsigned long max_denominator,
+ unsigned long *best_numerator,
+ unsigned long *best_denominator)
+{
+ unsigned long n, d, n0, d0, n1, d1;
+
+ n = given_numerator;
+ d = given_denominator;
+ n0 = 0;
+ d1 = 0;
+ n1 = 1;
+ d0 = 1;
+ for (;;) {
+ unsigned long t, a;
+
+ if (n1 > max_numerator || d1 > max_denominator) {
+ n1 = n0;
+ d1 = d0;
+ break;
+ }
+ if (d == 0)
+ break;
+ t = d;
+ a = n / d;
+ d = n % d;
+ n = t;
+ t = n0 + a * n1;
+ n0 = n1;
+ n1 = t;
+ t = d0 + a * d1;
+ d0 = d1;
+ d1 = t;
+ }
+ *best_numerator = n1;
+ *best_denominator = d1;
+}
+#endif
+
+static ulong rk3576_bus_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 con, sel, div, rate;
+
+ switch (clk_id) {
+ case ACLK_BUS_ROOT:
+ con = readl(&cru->clksel_con[55]);
+ sel = (con & ACLK_BUS_ROOT_SEL_MASK) >>
+ ACLK_BUS_ROOT_SEL_SHIFT;
+ div = (con & ACLK_BUS_ROOT_DIV_MASK) >>
+ ACLK_BUS_ROOT_DIV_SHIFT;
+ if (sel == ACLK_BUS_ROOT_SEL_CPLL)
+ rate = DIV_TO_RATE(priv->cpll_hz, div);
+ else
+ rate = DIV_TO_RATE(priv->gpll_hz, div);
+ break;
+ case HCLK_BUS_ROOT:
+ con = readl(&cru->clksel_con[55]);
+ sel = (con & HCLK_BUS_ROOT_SEL_MASK) >>
+ HCLK_BUS_ROOT_SEL_SHIFT;
+ if (sel == HCLK_BUS_ROOT_SEL_200M)
+ rate = 198 * MHz;
+ else if (sel == HCLK_BUS_ROOT_SEL_100M)
+ rate = 100 * MHz;
+ else if (sel == HCLK_BUS_ROOT_SEL_50M)
+ rate = 50 * MHz;
+ else
+ rate = OSC_HZ;
+ break;
+ case PCLK_BUS_ROOT:
+ con = readl(&cru->clksel_con[55]);
+ sel = (con & PCLK_BUS_ROOT_SEL_MASK) >>
+ PCLK_BUS_ROOT_SEL_SHIFT;
+ if (sel == PCLK_BUS_ROOT_SEL_100M)
+ rate = 100 * MHz;
+ else if (sel == PCLK_BUS_ROOT_SEL_50M)
+ rate = 50 * MHz;
+ else
+ rate = OSC_HZ;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rate;
+}
+
+static ulong rk3576_bus_set_clk(struct rk3576_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3576_cru *cru = priv->cru;
+ int src_clk, src_clk_div;
+
+ switch (clk_id) {
+ case ACLK_BUS_ROOT:
+ if (!(priv->cpll_hz % rate)) {
+ src_clk = ACLK_BUS_ROOT_SEL_CPLL;
+ src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ } else {
+ src_clk = ACLK_BUS_ROOT_SEL_GPLL;
+ src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ }
+ rk_clrsetreg(&cru->clksel_con[55],
+ ACLK_BUS_ROOT_SEL_MASK,
+ src_clk << ACLK_BUS_ROOT_SEL_SHIFT);
+ assert(src_clk_div - 1 <= 31);
+ rk_clrsetreg(&cru->clksel_con[55],
+ ACLK_BUS_ROOT_DIV_MASK |
+ ACLK_BUS_ROOT_SEL_MASK,
+ (src_clk <<
+ ACLK_BUS_ROOT_SEL_SHIFT) |
+ (src_clk_div - 1) << ACLK_BUS_ROOT_DIV_SHIFT);
+ break;
+ case HCLK_BUS_ROOT:
+ if (rate >= 198 * MHz)
+ src_clk = HCLK_BUS_ROOT_SEL_200M;
+ else if (rate >= 99 * MHz)
+ src_clk = HCLK_BUS_ROOT_SEL_100M;
+ else if (rate >= 50 * MHz)
+ src_clk = HCLK_BUS_ROOT_SEL_50M;
+ else
+ src_clk = HCLK_BUS_ROOT_SEL_OSC;
+ rk_clrsetreg(&cru->clksel_con[55],
+ HCLK_BUS_ROOT_SEL_MASK,
+ src_clk << HCLK_BUS_ROOT_SEL_SHIFT);
+ break;
+ case PCLK_BUS_ROOT:
+ if (rate >= 99 * MHz)
+ src_clk = PCLK_BUS_ROOT_SEL_100M;
+ else if (rate >= 50 * MHz)
+ src_clk = PCLK_BUS_ROOT_SEL_50M;
+ else
+ src_clk = PCLK_BUS_ROOT_SEL_OSC;
+ rk_clrsetreg(&cru->clksel_con[55],
+ PCLK_BUS_ROOT_SEL_MASK,
+ src_clk << PCLK_BUS_ROOT_SEL_SHIFT);
+ break;
+ default:
+ printf("do not support this center freq\n");
+ return -EINVAL;
+ }
+
+ return rk3576_bus_get_clk(priv, clk_id);
+}
+
+static ulong rk3576_top_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 con, sel, div, rate, prate;
+
+ switch (clk_id) {
+ case ACLK_TOP:
+ con = readl(&cru->clksel_con[9]);
+ div = (con & ACLK_TOP_DIV_MASK) >>
+ ACLK_TOP_DIV_SHIFT;
+ sel = (con & ACLK_TOP_SEL_MASK) >>
+ ACLK_TOP_SEL_SHIFT;
+ if (sel == ACLK_TOP_SEL_CPLL)
+ prate = priv->cpll_hz;
+ else if (sel == ACLK_TOP_SEL_AUPLL)
+ prate = priv->aupll_hz;
+ else
+ prate = priv->gpll_hz;
+ return DIV_TO_RATE(prate, div);
+ case ACLK_TOP_MID:
+ con = readl(&cru->clksel_con[10]);
+ div = (con & ACLK_TOP_MID_DIV_MASK) >>
+ ACLK_TOP_MID_DIV_SHIFT;
+ sel = (con & ACLK_TOP_MID_SEL_MASK) >>
+ ACLK_TOP_MID_SEL_SHIFT;
+ if (sel == ACLK_TOP_MID_SEL_CPLL)
+ prate = priv->cpll_hz;
+ else
+ prate = priv->gpll_hz;
+ return DIV_TO_RATE(prate, div);
+ case PCLK_TOP_ROOT:
+ con = readl(&cru->clksel_con[8]);
+ sel = (con & PCLK_TOP_SEL_MASK) >> PCLK_TOP_SEL_SHIFT;
+ if (sel == PCLK_TOP_SEL_100M)
+ rate = 100 * MHz;
+ else if (sel == PCLK_TOP_SEL_50M)
+ rate = 50 * MHz;
+ else
+ rate = OSC_HZ;
+ break;
+ case HCLK_TOP:
+ con = readl(&cru->clksel_con[19]);
+ sel = (con & HCLK_TOP_SEL_MASK) >> HCLK_TOP_SEL_SHIFT;
+ if (sel == HCLK_TOP_SEL_200M)
+ rate = 200 * MHz;
+ else if (sel == HCLK_TOP_SEL_100M)
+ rate = 100 * MHz;
+ else if (sel == HCLK_TOP_SEL_50M)
+ rate = 50 * MHz;
+ else
+ rate = OSC_HZ;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rate;
+}
+
+static ulong rk3576_top_set_clk(struct rk3576_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3576_cru *cru = priv->cru;
+ int src_clk, src_clk_div;
+
+ switch (clk_id) {
+ case ACLK_TOP:
+ if (!(priv->cpll_hz % rate)) {
+ src_clk = ACLK_TOP_SEL_CPLL;
+ src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ } else {
+ src_clk = ACLK_TOP_SEL_GPLL;
+ src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ }
+ assert(src_clk_div - 1 <= 31);
+ rk_clrsetreg(&cru->clksel_con[9],
+ ACLK_TOP_DIV_MASK |
+ ACLK_TOP_SEL_MASK,
+ (src_clk <<
+ ACLK_TOP_SEL_SHIFT) |
+ (src_clk_div - 1) << ACLK_TOP_SEL_SHIFT);
+ break;
+ case ACLK_TOP_MID:
+ if (!(priv->cpll_hz % rate)) {
+ src_clk = ACLK_TOP_MID_SEL_CPLL;
+ src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ } else {
+ src_clk = ACLK_TOP_MID_SEL_GPLL;
+ src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ }
+ rk_clrsetreg(&cru->clksel_con[10],
+ ACLK_TOP_MID_DIV_MASK |
+ ACLK_TOP_MID_SEL_MASK,
+ (ACLK_TOP_MID_SEL_GPLL <<
+ ACLK_TOP_MID_SEL_SHIFT) |
+ (src_clk_div - 1) << ACLK_TOP_MID_DIV_SHIFT);
+ break;
+ case PCLK_TOP_ROOT:
+ if (rate >= 99 * MHz)
+ src_clk = PCLK_TOP_SEL_100M;
+ else if (rate >= 50 * MHz)
+ src_clk = PCLK_TOP_SEL_50M;
+ else
+ src_clk = PCLK_TOP_SEL_OSC;
+ rk_clrsetreg(&cru->clksel_con[8],
+ PCLK_TOP_SEL_MASK,
+ src_clk << PCLK_TOP_SEL_SHIFT);
+ break;
+ case HCLK_TOP:
+ if (rate >= 198 * MHz)
+ src_clk = HCLK_TOP_SEL_200M;
+ else if (rate >= 99 * MHz)
+ src_clk = HCLK_TOP_SEL_100M;
+ else if (rate >= 50 * MHz)
+ src_clk = HCLK_TOP_SEL_50M;
+ else
+ src_clk = HCLK_TOP_SEL_OSC;
+ rk_clrsetreg(&cru->clksel_con[19],
+ HCLK_TOP_SEL_MASK,
+ src_clk << HCLK_TOP_SEL_SHIFT);
+ break;
+ default:
+ printf("do not support this top freq\n");
+ return -EINVAL;
+ }
+
+ return rk3576_top_get_clk(priv, clk_id);
+}
+
+static ulong rk3576_i2c_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 sel, con;
+ ulong rate;
+
+ switch (clk_id) {
+ case CLK_I2C0:
+ con = readl(&cru->pmuclksel_con[6]);
+ sel = (con & CLK_I2C0_SEL_MASK) >> CLK_I2C0_SEL_SHIFT;
+ break;
+ case CLK_I2C1:
+ con = readl(&cru->clksel_con[57]);
+ sel = (con & CLK_I2C1_SEL_MASK) >> CLK_I2C1_SEL_SHIFT;
+ break;
+ case CLK_I2C2:
+ con = readl(&cru->clksel_con[57]);
+ sel = (con & CLK_I2C2_SEL_MASK) >> CLK_I2C2_SEL_SHIFT;
+ break;
+ case CLK_I2C3:
+ con = readl(&cru->clksel_con[57]);
+ sel = (con & CLK_I2C3_SEL_MASK) >> CLK_I2C3_SEL_SHIFT;
+ break;
+ case CLK_I2C4:
+ con = readl(&cru->clksel_con[57]);
+ sel = (con & CLK_I2C4_SEL_MASK) >> CLK_I2C4_SEL_SHIFT;
+ break;
+ case CLK_I2C5:
+ con = readl(&cru->clksel_con[57]);
+ sel = (con & CLK_I2C5_SEL_MASK) >> CLK_I2C5_SEL_SHIFT;
+ break;
+ case CLK_I2C6:
+ con = readl(&cru->clksel_con[57]);
+ sel = (con & CLK_I2C6_SEL_MASK) >> CLK_I2C6_SEL_SHIFT;
+ break;
+ case CLK_I2C7:
+ con = readl(&cru->clksel_con[57]);
+ sel = (con & CLK_I2C7_SEL_MASK) >> CLK_I2C7_SEL_SHIFT;
+ break;
+ case CLK_I2C8:
+ con = readl(&cru->clksel_con[57]);
+ sel = (con & CLK_I2C8_SEL_MASK) >> CLK_I2C8_SEL_SHIFT;
+ break;
+ case CLK_I2C9:
+ con = readl(&cru->clksel_con[58]);
+ sel = (con & CLK_I2C9_SEL_MASK) >> CLK_I2C9_SEL_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+ if (sel == CLK_I2C_SEL_200M)
+ rate = 200 * MHz;
+ else if (sel == CLK_I2C_SEL_100M)
+ rate = 100 * MHz;
+ else if (sel == CLK_I2C_SEL_50M)
+ rate = 50 * MHz;
+ else
+ rate = OSC_HZ;
+
+ return rate;
+}
+
+static ulong rk3576_i2c_set_clk(struct rk3576_clk_priv *priv, ulong clk_id,
+ ulong rate)
+{
+ struct rk3576_cru *cru = priv->cru;
+ int src_clk;
+
+ if (rate >= 198 * MHz)
+ src_clk = CLK_I2C_SEL_200M;
+ else if (rate >= 99 * MHz)
+ src_clk = CLK_I2C_SEL_100M;
+ if (rate >= 50 * MHz)
+ src_clk = CLK_I2C_SEL_50M;
+ else
+ src_clk = CLK_I2C_SEL_OSC;
+
+ switch (clk_id) {
+ case CLK_I2C0:
+ rk_clrsetreg(&cru->pmuclksel_con[6], CLK_I2C0_SEL_MASK,
+ src_clk << CLK_I2C0_SEL_SHIFT);
+ break;
+ case CLK_I2C1:
+ rk_clrsetreg(&cru->clksel_con[57], CLK_I2C1_SEL_MASK,
+ src_clk << CLK_I2C1_SEL_SHIFT);
+ break;
+ case CLK_I2C2:
+ rk_clrsetreg(&cru->clksel_con[57], CLK_I2C2_SEL_MASK,
+ src_clk << CLK_I2C2_SEL_SHIFT);
+ break;
+ case CLK_I2C3:
+ rk_clrsetreg(&cru->clksel_con[57], CLK_I2C3_SEL_MASK,
+ src_clk << CLK_I2C3_SEL_SHIFT);
+ break;
+ case CLK_I2C4:
+ rk_clrsetreg(&cru->clksel_con[57], CLK_I2C4_SEL_MASK,
+ src_clk << CLK_I2C4_SEL_SHIFT);
+ break;
+ case CLK_I2C5:
+ rk_clrsetreg(&cru->clksel_con[57], CLK_I2C5_SEL_MASK,
+ src_clk << CLK_I2C5_SEL_SHIFT);
+ break;
+ case CLK_I2C6:
+ rk_clrsetreg(&cru->clksel_con[57], CLK_I2C6_SEL_MASK,
+ src_clk << CLK_I2C6_SEL_SHIFT);
+ break;
+ case CLK_I2C7:
+ rk_clrsetreg(&cru->clksel_con[57], CLK_I2C7_SEL_MASK,
+ src_clk << CLK_I2C7_SEL_SHIFT);
+ break;
+ case CLK_I2C8:
+ rk_clrsetreg(&cru->clksel_con[57], CLK_I2C8_SEL_MASK,
+ src_clk << CLK_I2C8_SEL_SHIFT);
+ case CLK_I2C9:
+ rk_clrsetreg(&cru->clksel_con[58], CLK_I2C9_SEL_MASK,
+ src_clk << CLK_I2C9_SEL_SHIFT);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rk3576_i2c_get_clk(priv, clk_id);
+}
+
+static ulong rk3576_spi_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 sel, con;
+
+ switch (clk_id) {
+ case CLK_SPI0:
+ con = readl(&cru->clksel_con[70]);
+ sel = (con & CLK_SPI0_SEL_MASK) >> CLK_SPI0_SEL_SHIFT;
+ break;
+ case CLK_SPI1:
+ con = readl(&cru->clksel_con[71]);
+ sel = (con & CLK_SPI1_SEL_MASK) >> CLK_SPI1_SEL_SHIFT;
+ break;
+ case CLK_SPI2:
+ con = readl(&cru->clksel_con[71]);
+ sel = (con & CLK_SPI2_SEL_MASK) >> CLK_SPI2_SEL_SHIFT;
+ break;
+ case CLK_SPI3:
+ con = readl(&cru->clksel_con[71]);
+ sel = (con & CLK_SPI3_SEL_MASK) >> CLK_SPI3_SEL_SHIFT;
+ break;
+ case CLK_SPI4:
+ con = readl(&cru->clksel_con[71]);
+ sel = (con & CLK_SPI4_SEL_MASK) >> CLK_SPI4_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ switch (sel) {
+ case CLK_SPI_SEL_200M:
+ return 200 * MHz;
+ case CLK_SPI_SEL_100M:
+ return 100 * MHz;
+ case CLK_SPI_SEL_50M:
+ return 50 * MHz;
+ case CLK_SPI_SEL_OSC:
+ return OSC_HZ;
+ default:
+ return -ENOENT;
+ }
+}
+
+static ulong rk3576_spi_set_clk(struct rk3576_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3576_cru *cru = priv->cru;
+ int src_clk;
+
+ if (rate >= 198 * MHz)
+ src_clk = CLK_SPI_SEL_200M;
+ else if (rate >= 99 * MHz)
+ src_clk = CLK_SPI_SEL_100M;
+ else if (rate >= 50 * MHz)
+ src_clk = CLK_SPI_SEL_50M;
+ else
+ src_clk = CLK_SPI_SEL_OSC;
+
+ switch (clk_id) {
+ case CLK_SPI0:
+ rk_clrsetreg(&cru->clksel_con[70],
+ CLK_SPI0_SEL_MASK,
+ src_clk << CLK_SPI0_SEL_SHIFT);
+ break;
+ case CLK_SPI1:
+ rk_clrsetreg(&cru->clksel_con[71],
+ CLK_SPI1_SEL_MASK,
+ src_clk << CLK_SPI1_SEL_SHIFT);
+ break;
+ case CLK_SPI2:
+ rk_clrsetreg(&cru->clksel_con[71],
+ CLK_SPI2_SEL_MASK,
+ src_clk << CLK_SPI2_SEL_SHIFT);
+ break;
+ case CLK_SPI3:
+ rk_clrsetreg(&cru->clksel_con[71],
+ CLK_SPI3_SEL_MASK,
+ src_clk << CLK_SPI3_SEL_SHIFT);
+ break;
+ case CLK_SPI4:
+ rk_clrsetreg(&cru->clksel_con[71],
+ CLK_SPI4_SEL_MASK,
+ src_clk << CLK_SPI4_SEL_SHIFT);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rk3576_spi_get_clk(priv, clk_id);
+}
+
+static ulong rk3576_pwm_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 sel, con;
+
+ switch (clk_id) {
+ case CLK_PWM1:
+ con = readl(&cru->clksel_con[71]);
+ sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT;
+ break;
+ case CLK_PWM2:
+ con = readl(&cru->clksel_con[74]);
+ sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT;
+ break;
+ case CLK_PMU1PWM:
+ con = readl(&cru->pmuclksel_con[5]);
+ sel = (con & CLK_PMU1PWM_SEL_MASK) >> CLK_PMU1PWM_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ switch (sel) {
+ case CLK_PWM_SEL_100M:
+ return 100 * MHz;
+ case CLK_PWM_SEL_50M:
+ return 50 * MHz;
+ case CLK_PWM_SEL_OSC:
+ return OSC_HZ;
+ default:
+ return -ENOENT;
+ }
+}
+
+static ulong rk3576_pwm_set_clk(struct rk3576_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3576_cru *cru = priv->cru;
+ int src_clk;
+
+ if (rate >= 99 * MHz)
+ src_clk = CLK_PWM_SEL_100M;
+ else if (rate >= 50 * MHz)
+ src_clk = CLK_PWM_SEL_50M;
+ else
+ src_clk = CLK_PWM_SEL_OSC;
+
+ switch (clk_id) {
+ case CLK_PWM1:
+ rk_clrsetreg(&cru->clksel_con[71],
+ CLK_PWM1_SEL_MASK,
+ src_clk << CLK_PWM1_SEL_SHIFT);
+ break;
+ case CLK_PWM2:
+ rk_clrsetreg(&cru->clksel_con[74],
+ CLK_PWM2_SEL_MASK,
+ src_clk << CLK_PWM2_SEL_SHIFT);
+ break;
+ case CLK_PMU1PWM:
+ rk_clrsetreg(&cru->pmuclksel_con[5],
+ CLK_PMU1PWM_SEL_MASK,
+ src_clk << CLK_PMU1PWM_SEL_SHIFT);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rk3576_pwm_get_clk(priv, clk_id);
+}
+
+static ulong rk3576_adc_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 div, sel, con, prate;
+
+ switch (clk_id) {
+ case CLK_SARADC:
+ con = readl(&cru->clksel_con[58]);
+ div = (con & CLK_SARADC_DIV_MASK) >> CLK_SARADC_DIV_SHIFT;
+ sel = (con & CLK_SARADC_SEL_MASK) >>
+ CLK_SARADC_SEL_SHIFT;
+ if (sel == CLK_SARADC_SEL_OSC)
+ prate = OSC_HZ;
+ else
+ prate = priv->gpll_hz;
+ return DIV_TO_RATE(prate, div);
+ case CLK_TSADC:
+ con = readl(&cru->clksel_con[59]);
+ div = (con & CLK_TSADC_DIV_MASK) >>
+ CLK_TSADC_DIV_SHIFT;
+ prate = OSC_HZ;
+ return DIV_TO_RATE(prate, div);
+ default:
+ return -ENOENT;
+ }
+}
+
+static ulong rk3576_adc_set_clk(struct rk3576_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3576_cru *cru = priv->cru;
+ int src_clk_div;
+
+ switch (clk_id) {
+ case CLK_SARADC:
+ if (!(OSC_HZ % rate)) {
+ src_clk_div = DIV_ROUND_UP(OSC_HZ, rate);
+ assert(src_clk_div - 1 <= 255);
+ rk_clrsetreg(&cru->clksel_con[58],
+ CLK_SARADC_SEL_MASK |
+ CLK_SARADC_DIV_MASK,
+ (CLK_SARADC_SEL_OSC <<
+ CLK_SARADC_SEL_SHIFT) |
+ (src_clk_div - 1) <<
+ CLK_SARADC_DIV_SHIFT);
+ } else {
+ src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ assert(src_clk_div - 1 <= 255);
+ rk_clrsetreg(&cru->clksel_con[59],
+ CLK_SARADC_SEL_MASK |
+ CLK_SARADC_DIV_MASK,
+ (CLK_SARADC_SEL_GPLL <<
+ CLK_SARADC_SEL_SHIFT) |
+ (src_clk_div - 1) <<
+ CLK_SARADC_DIV_SHIFT);
+ }
+ break;
+ case CLK_TSADC:
+ src_clk_div = DIV_ROUND_UP(OSC_HZ, rate);
+ assert(src_clk_div - 1 <= 255);
+ rk_clrsetreg(&cru->clksel_con[58],
+ CLK_TSADC_DIV_MASK,
+ (src_clk_div - 1) <<
+ CLK_TSADC_DIV_SHIFT);
+ break;
+ default:
+ return -ENOENT;
+ }
+ return rk3576_adc_get_clk(priv, clk_id);
+}
+
+static ulong rk3576_mmc_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 sel, con, prate, div = 0;
+
+ switch (clk_id) {
+ case CCLK_SRC_SDIO:
+ case HCLK_SDIO:
+ con = readl(&cru->clksel_con[104]);
+ div = (con & CCLK_SDIO_SRC_DIV_MASK) >> CCLK_SDIO_SRC_DIV_SHIFT;
+ sel = (con & CCLK_SDIO_SRC_SEL_MASK) >>
+ CCLK_SDIO_SRC_SEL_SHIFT;
+ if (sel == CCLK_SDIO_SRC_SEL_GPLL)
+ prate = priv->gpll_hz;
+ else if (sel == CCLK_SDIO_SRC_SEL_CPLL)
+ prate = priv->cpll_hz;
+ else
+ prate = OSC_HZ;
+ return DIV_TO_RATE(prate, div);
+ case CCLK_SRC_SDMMC0:
+ case HCLK_SDMMC0:
+ con = readl(&cru->clksel_con[105]);
+ div = (con & CCLK_SDMMC0_SRC_DIV_MASK) >> CCLK_SDMMC0_SRC_DIV_SHIFT;
+ sel = (con & CCLK_SDMMC0_SRC_SEL_MASK) >>
+ CCLK_SDMMC0_SRC_SEL_SHIFT;
+ if (sel == CCLK_SDMMC0_SRC_SEL_GPLL)
+ prate = priv->gpll_hz;
+ else if (sel == CCLK_SDMMC0_SRC_SEL_CPLL)
+ prate = priv->cpll_hz;
+ else
+ prate = OSC_HZ;
+ return DIV_TO_RATE(prate, div);
+ case CCLK_SRC_EMMC:
+ case HCLK_EMMC:
+ con = readl(&cru->clksel_con[89]);
+ div = (con & CCLK_EMMC_DIV_MASK) >> CCLK_EMMC_DIV_SHIFT;
+ sel = (con & CCLK_EMMC_SEL_MASK) >>
+ CCLK_EMMC_SEL_SHIFT;
+ if (sel == CCLK_EMMC_SEL_GPLL)
+ prate = priv->gpll_hz;
+ else if (sel == CCLK_EMMC_SEL_CPLL)
+ prate = priv->cpll_hz;
+ else
+ prate = OSC_HZ;
+ return DIV_TO_RATE(prate, div);
+ case BCLK_EMMC:
+ con = readl(&cru->clksel_con[90]);
+ sel = (con & BCLK_EMMC_SEL_MASK) >>
+ BCLK_EMMC_SEL_SHIFT;
+ if (sel == BCLK_EMMC_SEL_200M)
+ prate = 200 * MHz;
+ else if (sel == BCLK_EMMC_SEL_100M)
+ prate = 100 * MHz;
+ else if (sel == BCLK_EMMC_SEL_50M)
+ prate = 50 * MHz;
+ else
+ prate = OSC_HZ;
+ return DIV_TO_RATE(prate, div);
+ case SCLK_FSPI_X2:
+ con = readl(&cru->clksel_con[89]);
+ div = (con & SCLK_FSPI_DIV_MASK) >> SCLK_FSPI_DIV_SHIFT;
+ sel = (con & SCLK_FSPI_SEL_MASK) >>
+ SCLK_FSPI_SEL_SHIFT;
+ if (sel == SCLK_FSPI_SEL_GPLL)
+ prate = priv->gpll_hz;
+ else if (sel == SCLK_FSPI_SEL_CPLL)
+ prate = priv->cpll_hz;
+ else
+ prate = OSC_HZ;
+ return DIV_TO_RATE(prate, div);
+ case SCLK_FSPI1_X2:
+ con = readl(&cru->clksel_con[106]);
+ div = (con & SCLK_FSPI_DIV_MASK) >> SCLK_FSPI_DIV_SHIFT;
+ sel = (con & SCLK_FSPI_SEL_MASK) >>
+ SCLK_FSPI_SEL_SHIFT;
+ if (sel == SCLK_FSPI_SEL_GPLL)
+ prate = priv->gpll_hz;
+ else if (sel == SCLK_FSPI_SEL_CPLL)
+ prate = priv->cpll_hz;
+ else
+ prate = OSC_HZ;
+ return DIV_TO_RATE(prate, div);
+ case DCLK_DECOM:
+ con = readl(&cru->clksel_con[72]);
+ div = (con & DCLK_DECOM_DIV_MASK) >> DCLK_DECOM_DIV_SHIFT;
+ sel = (con & DCLK_DECOM_SEL_MASK) >> DCLK_DECOM_SEL_SHIFT;
+ if (sel == DCLK_DECOM_SEL_SPLL)
+ prate = priv->spll_hz;
+ else
+ prate = priv->gpll_hz;
+ return DIV_TO_RATE(prate, div);
+
+ default:
+ return -ENOENT;
+ }
+}
+
+static ulong rk3576_mmc_set_clk(struct rk3576_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3576_cru *cru = priv->cru;
+ int src_clk, div = 0;
+
+ switch (clk_id) {
+ case CCLK_SRC_SDIO:
+ case CCLK_SRC_SDMMC0:
+ case CCLK_SRC_EMMC:
+ case SCLK_FSPI_X2:
+ case SCLK_FSPI1_X2:
+ case HCLK_SDMMC0:
+ case HCLK_EMMC:
+ case HCLK_SDIO:
+ if (!(OSC_HZ % rate)) {
+ src_clk = SCLK_FSPI_SEL_OSC;
+ div = DIV_ROUND_UP(OSC_HZ, rate);
+ } else if (!(priv->cpll_hz % rate)) {
+ src_clk = SCLK_FSPI_SEL_CPLL;
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ } else {
+ src_clk = SCLK_FSPI_SEL_GPLL;
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ }
+ break;
+ case BCLK_EMMC:
+ if (rate >= 198 * MHz)
+ src_clk = BCLK_EMMC_SEL_200M;
+ else if (rate >= 99 * MHz)
+ src_clk = BCLK_EMMC_SEL_100M;
+ else if (rate >= 50 * MHz)
+ src_clk = BCLK_EMMC_SEL_50M;
+ else
+ src_clk = BCLK_EMMC_SEL_OSC;
+ break;
+ case DCLK_DECOM:
+ if (!(priv->spll_hz % rate)) {
+ src_clk = DCLK_DECOM_SEL_SPLL;
+ div = DIV_ROUND_UP(priv->spll_hz, rate);
+ } else {
+ src_clk = DCLK_DECOM_SEL_GPLL;
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ }
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ switch (clk_id) {
+ case CCLK_SRC_SDIO:
+ case HCLK_SDIO:
+ rk_clrsetreg(&cru->clksel_con[104],
+ CCLK_SDIO_SRC_SEL_MASK |
+ CCLK_SDIO_SRC_DIV_MASK,
+ (src_clk << CCLK_SDIO_SRC_SEL_SHIFT) |
+ (div - 1) << CCLK_SDIO_SRC_DIV_SHIFT);
+ break;
+ case CCLK_SRC_SDMMC0:
+ case HCLK_SDMMC0:
+ rk_clrsetreg(&cru->clksel_con[105],
+ CCLK_SDMMC0_SRC_SEL_MASK |
+ CCLK_SDMMC0_SRC_DIV_MASK,
+ (src_clk << CCLK_SDMMC0_SRC_SEL_SHIFT) |
+ (div - 1) << CCLK_SDMMC0_SRC_DIV_SHIFT);
+ break;
+ case CCLK_SRC_EMMC:
+ case HCLK_EMMC:
+ rk_clrsetreg(&cru->clksel_con[89],
+ CCLK_EMMC_DIV_MASK |
+ CCLK_EMMC_SEL_MASK,
+ (src_clk << CCLK_EMMC_SEL_SHIFT) |
+ (div - 1) << CCLK_EMMC_DIV_SHIFT);
+ break;
+ case SCLK_FSPI_X2:
+ rk_clrsetreg(&cru->clksel_con[89],
+ SCLK_FSPI_DIV_MASK |
+ SCLK_FSPI_SEL_MASK,
+ (src_clk << SCLK_FSPI_SEL_SHIFT) |
+ (div - 1) << SCLK_FSPI_DIV_SHIFT);
+ break;
+ case SCLK_FSPI1_X2:
+ rk_clrsetreg(&cru->clksel_con[106],
+ SCLK_FSPI_DIV_MASK |
+ SCLK_FSPI_SEL_MASK,
+ (src_clk << SCLK_FSPI_SEL_SHIFT) |
+ (div - 1) << SCLK_FSPI_DIV_SHIFT);
+ break;
+ case BCLK_EMMC:
+ rk_clrsetreg(&cru->clksel_con[90],
+ BCLK_EMMC_SEL_MASK,
+ src_clk << BCLK_EMMC_SEL_SHIFT);
+ break;
+ case DCLK_DECOM:
+ rk_clrsetreg(&cru->clksel_con[72],
+ DCLK_DECOM_DIV_MASK |
+ DCLK_DECOM_SEL_MASK,
+ (src_clk << DCLK_DECOM_SEL_SHIFT) |
+ (div - 1) << DCLK_DECOM_DIV_SHIFT);
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ return rk3576_mmc_get_clk(priv, clk_id);
+}
+
+#ifndef CONFIG_SPL_BUILD
+
+static ulong rk3576_aclk_vop_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 div, sel, con, parent = 0;
+
+ switch (clk_id) {
+ case ACLK_VOP_ROOT:
+ case ACLK_VOP:
+ con = readl(&cru->clksel_con[144]);
+ div = (con & ACLK_VOP_ROOT_DIV_MASK) >> ACLK_VOP_ROOT_DIV_SHIFT;
+ sel = (con & ACLK_VOP_ROOT_SEL_MASK) >> ACLK_VOP_ROOT_SEL_SHIFT;
+ if (sel == ACLK_VOP_ROOT_SEL_GPLL)
+ parent = priv->gpll_hz;
+ else if (sel == ACLK_VOP_ROOT_SEL_CPLL)
+ parent = priv->cpll_hz;
+ else if (sel == ACLK_VOP_ROOT_SEL_AUPLL)
+ parent = priv->aupll_hz;
+ else if (sel == ACLK_VOP_ROOT_SEL_SPLL)
+ parent = priv->spll_hz;
+ else if (sel == ACLK_VOP_ROOT_SEL_LPLL)
+ parent = priv->lpll_hz / 2;
+ return DIV_TO_RATE(parent, div);
+ case ACLK_VO0_ROOT:
+ con = readl(&cru->clksel_con[149]);
+ div = (con & ACLK_VO0_ROOT_DIV_MASK) >> ACLK_VO0_ROOT_DIV_SHIFT;
+ sel = (con & ACLK_VO0_ROOT_SEL_MASK) >> ACLK_VO0_ROOT_SEL_SHIFT;
+ if (sel == ACLK_VO0_ROOT_SEL_GPLL)
+ parent = priv->gpll_hz;
+ else if (sel == ACLK_VO0_ROOT_SEL_CPLL)
+ parent = priv->cpll_hz;
+ else if (sel == ACLK_VO0_ROOT_SEL_LPLL)
+ parent = priv->lpll_hz / 2;
+ else if (sel == ACLK_VO0_ROOT_SEL_BPLL)
+ parent = priv->bpll_hz / 4;
+ return DIV_TO_RATE(parent, div);
+ case ACLK_VO1_ROOT:
+ con = readl(&cru->clksel_con[158]);
+ div = (con & ACLK_VO0_ROOT_DIV_MASK) >> ACLK_VO0_ROOT_DIV_SHIFT;
+ sel = (con & ACLK_VO0_ROOT_SEL_MASK) >> ACLK_VO0_ROOT_SEL_SHIFT;
+ if (sel == ACLK_VO0_ROOT_SEL_GPLL)
+ parent = priv->gpll_hz;
+ else if (sel == ACLK_VO0_ROOT_SEL_CPLL)
+ parent = priv->cpll_hz;
+ else if (sel == ACLK_VO0_ROOT_SEL_LPLL)
+ parent = priv->lpll_hz / 2;
+ else if (sel == ACLK_VO0_ROOT_SEL_BPLL)
+ parent = priv->bpll_hz / 4;
+ return DIV_TO_RATE(parent, div);
+ case HCLK_VOP_ROOT:
+ con = readl(&cru->clksel_con[144]);
+ sel = (con & HCLK_VOP_ROOT_SEL_MASK) >> HCLK_VOP_ROOT_SEL_SHIFT;
+ if (sel == HCLK_VOP_ROOT_SEL_200M)
+ return 200 * MHz;
+ else if (sel == HCLK_VOP_ROOT_SEL_100M)
+ return 100 * MHz;
+ else if (sel == HCLK_VOP_ROOT_SEL_50M)
+ return 50 * MHz;
+ else
+ return OSC_HZ;
+ case PCLK_VOP_ROOT:
+ con = readl(&cru->clksel_con[144]);
+ sel = (con & PCLK_VOP_ROOT_SEL_MASK) >> PCLK_VOP_ROOT_SEL_SHIFT;
+ if (sel == PCLK_VOP_ROOT_SEL_100M)
+ return 100 * MHz;
+ else if (sel == PCLK_VOP_ROOT_SEL_50M)
+ return 50 * MHz;
+ else
+ return OSC_HZ;
+
+ default:
+ return -ENOENT;
+ }
+}
+
+static ulong rk3576_aclk_vop_set_clk(struct rk3576_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3576_cru *cru = priv->cru;
+ int src_clk, div;
+
+ switch (clk_id) {
+ case ACLK_VOP_ROOT:
+ case ACLK_VOP:
+ if (rate == 700 * MHz) {
+ src_clk = ACLK_VOP_ROOT_SEL_SPLL;
+ div = 1;
+ } else if (!(priv->cpll_hz % rate)) {
+ src_clk = ACLK_VOP_ROOT_SEL_CPLL;
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ } else {
+ src_clk = ACLK_VOP_ROOT_SEL_GPLL;
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ }
+ rk_clrsetreg(&cru->clksel_con[144],
+ ACLK_VOP_ROOT_DIV_MASK |
+ ACLK_VOP_ROOT_SEL_MASK,
+ (src_clk << ACLK_VOP_ROOT_SEL_SHIFT) |
+ (div - 1) << ACLK_VOP_ROOT_DIV_SHIFT);
+ break;
+ case ACLK_VO0_ROOT:
+ if (!(priv->cpll_hz % rate)) {
+ src_clk = ACLK_VO0_ROOT_SEL_CPLL;
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ } else {
+ src_clk = ACLK_VO0_ROOT_SEL_GPLL;
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ }
+ rk_clrsetreg(&cru->clksel_con[149],
+ ACLK_VO0_ROOT_DIV_MASK |
+ ACLK_VO0_ROOT_SEL_MASK,
+ (src_clk << ACLK_VO0_ROOT_SEL_SHIFT) |
+ (div - 1) << ACLK_VO0_ROOT_DIV_SHIFT);
+ break;
+ case ACLK_VO1_ROOT:
+ if (!(priv->cpll_hz % rate)) {
+ src_clk = ACLK_VO0_ROOT_SEL_CPLL;
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ } else {
+ src_clk = ACLK_VO0_ROOT_SEL_GPLL;
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ }
+ rk_clrsetreg(&cru->clksel_con[158],
+ ACLK_VO0_ROOT_DIV_MASK |
+ ACLK_VO0_ROOT_SEL_MASK,
+ (src_clk << ACLK_VO0_ROOT_SEL_SHIFT) |
+ (div - 1) << ACLK_VO0_ROOT_DIV_SHIFT);
+ break;
+ case HCLK_VOP_ROOT:
+ if (rate == 200 * MHz)
+ src_clk = HCLK_VOP_ROOT_SEL_200M;
+ else if (rate == 100 * MHz)
+ src_clk = HCLK_VOP_ROOT_SEL_100M;
+ else if (rate == 50 * MHz)
+ src_clk = HCLK_VOP_ROOT_SEL_50M;
+ else
+ src_clk = HCLK_VOP_ROOT_SEL_OSC;
+ rk_clrsetreg(&cru->clksel_con[144],
+ HCLK_VOP_ROOT_SEL_MASK,
+ src_clk << HCLK_VOP_ROOT_SEL_SHIFT);
+ break;
+ case PCLK_VOP_ROOT:
+ if (rate == 100 * MHz)
+ src_clk = PCLK_VOP_ROOT_SEL_100M;
+ else if (rate == 50 * MHz)
+ src_clk = PCLK_VOP_ROOT_SEL_50M;
+ else
+ src_clk = PCLK_VOP_ROOT_SEL_OSC;
+ rk_clrsetreg(&cru->clksel_con[144],
+ PCLK_VOP_ROOT_SEL_MASK,
+ src_clk << PCLK_VOP_ROOT_SEL_SHIFT);
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ return rk3576_aclk_vop_get_clk(priv, clk_id);
+}
+
+static ulong rk3576_dclk_vop_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 div, sel, con, parent;
+
+ switch (clk_id) {
+ case DCLK_VP0:
+ case DCLK_VP0_SRC:
+ con = readl(&cru->clksel_con[145]);
+ div = (con & DCLK0_VOP_SRC_DIV_MASK) >> DCLK0_VOP_SRC_DIV_SHIFT;
+ sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT;
+ break;
+ case DCLK_VP1:
+ case DCLK_VP1_SRC:
+ con = readl(&cru->clksel_con[146]);
+ div = (con & DCLK0_VOP_SRC_DIV_MASK) >> DCLK0_VOP_SRC_DIV_SHIFT;
+ sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT;
+ break;
+ case DCLK_VP2:
+ case DCLK_VP2_SRC:
+ con = readl(&cru->clksel_con[147]);
+ div = (con & DCLK0_VOP_SRC_DIV_MASK) >> DCLK0_VOP_SRC_DIV_SHIFT;
+ sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ if (sel == DCLK_VOP_SRC_SEL_VPLL)
+ parent = priv->vpll_hz;
+ else if (sel == DCLK_VOP_SRC_SEL_BPLL)
+ parent = priv->bpll_hz / 4;
+ else if (sel == DCLK_VOP_SRC_SEL_LPLL)
+ parent = priv->lpll_hz / 2;
+ else if (sel == DCLK_VOP_SRC_SEL_GPLL)
+ parent = priv->gpll_hz;
+ else
+ parent = priv->cpll_hz;
+
+ return DIV_TO_RATE(parent, div);
+}
+
+#define RK3576_VOP_PLL_LIMIT_FREQ 600000000
+
+static ulong rk3576_dclk_vop_set_clk(struct rk3576_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3576_cru *cru = priv->cru;
+ ulong pll_rate, now, best_rate = 0;
+ u32 i, conid, con, sel, div, best_div = 0, best_sel = 0;
+ u32 mask, div_shift, sel_shift;
+
+ switch (clk_id) {
+ case DCLK_VP0:
+ case DCLK_VP0_SRC:
+ conid = 145;
+ con = readl(&cru->clksel_con[conid]);
+ sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT;
+ mask = DCLK0_VOP_SRC_SEL_MASK | DCLK0_VOP_SRC_DIV_MASK;
+ div_shift = DCLK0_VOP_SRC_DIV_SHIFT;
+ sel_shift = DCLK0_VOP_SRC_SEL_SHIFT;
+ break;
+ case DCLK_VP1:
+ case DCLK_VP1_SRC:
+ conid = 146;
+ con = readl(&cru->clksel_con[conid]);
+ sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT;
+ mask = DCLK0_VOP_SRC_SEL_MASK | DCLK0_VOP_SRC_DIV_MASK;
+ div_shift = DCLK0_VOP_SRC_DIV_SHIFT;
+ sel_shift = DCLK0_VOP_SRC_SEL_SHIFT;
+ break;
+ case DCLK_VP2:
+ case DCLK_VP2_SRC:
+ conid = 147;
+ con = readl(&cru->clksel_con[conid]);
+ sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT;
+ mask = DCLK0_VOP_SRC_SEL_MASK | DCLK0_VOP_SRC_DIV_MASK;
+ div_shift = DCLK0_VOP_SRC_DIV_SHIFT;
+ sel_shift = DCLK0_VOP_SRC_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ if (sel == DCLK_VOP_SRC_SEL_VPLL) {
+ pll_rate = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL],
+ priv->cru, VPLL);
+ if (pll_rate >= RK3576_VOP_PLL_LIMIT_FREQ && pll_rate % rate == 0) {
+ div = DIV_ROUND_UP(pll_rate, rate);
+ rk_clrsetreg(&cru->clksel_con[conid],
+ mask,
+ DCLK_VOP_SRC_SEL_VPLL << sel_shift |
+ ((div - 1) << div_shift));
+ } else {
+ div = DIV_ROUND_UP(RK3576_VOP_PLL_LIMIT_FREQ, rate);
+ if (div % 2)
+ div = div + 1;
+ rk_clrsetreg(&cru->clksel_con[conid],
+ mask,
+ DCLK_VOP_SRC_SEL_VPLL << sel_shift |
+ ((div - 1) << div_shift));
+ rockchip_pll_set_rate(&rk3576_pll_clks[VPLL],
+ priv->cru, VPLL, div * rate);
+ priv->vpll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL],
+ priv->cru, VPLL);
+ }
+ } else {
+ for (i = 0; i <= DCLK_VOP_SRC_SEL_LPLL; i++) {
+ switch (i) {
+ case DCLK_VOP_SRC_SEL_GPLL:
+ pll_rate = priv->gpll_hz;
+ break;
+ case DCLK_VOP_SRC_SEL_CPLL:
+ pll_rate = priv->cpll_hz;
+ break;
+ case DCLK_VOP_SRC_SEL_BPLL:
+ pll_rate = 0;
+ break;
+ case DCLK_VOP_SRC_SEL_LPLL:
+ pll_rate = 0;
+ break;
+ case DCLK_VOP_SRC_SEL_VPLL:
+ pll_rate = 0;
+ break;
+ default:
+ printf("do not support this vop pll sel\n");
+ return -EINVAL;
+ }
+
+ div = DIV_ROUND_UP(pll_rate, rate);
+ if (div > 255)
+ continue;
+ now = pll_rate / div;
+ if (abs(rate - now) < abs(rate - best_rate)) {
+ best_rate = now;
+ best_div = div;
+ best_sel = i;
+ }
+ debug("p_rate=%lu, best_rate=%lu, div=%u, sel=%u\n",
+ pll_rate, best_rate, best_div, best_sel);
+ }
+
+ if (best_rate) {
+ rk_clrsetreg(&cru->clksel_con[conid],
+ mask,
+ best_sel << sel_shift |
+ (best_div - 1) << div_shift);
+ } else {
+ printf("do not support this vop freq %lu\n", rate);
+ return -EINVAL;
+ }
+ }
+
+ return rk3576_dclk_vop_get_clk(priv, clk_id);
+}
+
+static ulong rk3576_clk_csihost_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 div, sel, con, parent;
+
+ switch (clk_id) {
+ case CLK_DSIHOST0:
+ con = readl(&cru->clksel_con[151]);
+ div = (con & CLK_DSIHOST0_DIV_MASK) >> CLK_DSIHOST0_DIV_SHIFT;
+ sel = (con & CLK_DSIHOST0_SEL_MASK) >> CLK_DSIHOST0_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ if (sel == CLK_DSIHOST0_SEL_VPLL)
+ parent = priv->vpll_hz;
+ else if (sel == CLK_DSIHOST0_SEL_BPLL)
+ parent = priv->bpll_hz / 4;
+ else if (sel == CLK_DSIHOST0_SEL_LPLL)
+ parent = priv->lpll_hz / 2;
+ else if (sel == CLK_DSIHOST0_SEL_GPLL)
+ parent = priv->gpll_hz;
+ else if (sel == CLK_DSIHOST0_SEL_SPLL)
+ parent = priv->spll_hz;
+ else
+ parent = priv->cpll_hz;
+
+ return DIV_TO_RATE(parent, div);
+}
+
+static ulong rk3576_clk_csihost_set_clk(struct rk3576_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3576_cru *cru = priv->cru;
+ ulong pll_rate, now, best_rate = 0;
+ u32 i, con, div, best_div = 0, best_sel = 0;
+ u32 mask, div_shift, sel_shift;
+
+ switch (clk_id) {
+ case CLK_DSIHOST0:
+ con = 151;
+ mask = CLK_DSIHOST0_SEL_MASK | CLK_DSIHOST0_DIV_MASK;
+ div_shift = CLK_DSIHOST0_DIV_SHIFT;
+ sel_shift = CLK_DSIHOST0_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+ for (i = 0; i <= CLK_DSIHOST0_SEL_LPLL; i++) {
+ switch (i) {
+ case CLK_DSIHOST0_SEL_GPLL:
+ pll_rate = priv->gpll_hz;
+ break;
+ case CLK_DSIHOST0_SEL_CPLL:
+ pll_rate = priv->cpll_hz;
+ break;
+ case CLK_DSIHOST0_SEL_BPLL:
+ pll_rate = 0;
+ break;
+ case CLK_DSIHOST0_SEL_LPLL:
+ pll_rate = 0;
+ break;
+ case CLK_DSIHOST0_SEL_VPLL:
+ pll_rate = 0;
+ break;
+ case CLK_DSIHOST0_SEL_SPLL:
+ pll_rate = priv->spll_hz;
+ break;
+ default:
+ printf("do not support this vop pll sel\n");
+ return -EINVAL;
+ }
+
+ div = DIV_ROUND_UP(pll_rate, rate);
+ if (div > 255)
+ continue;
+ now = pll_rate / div;
+ if (abs(rate - now) < abs(rate - best_rate)) {
+ best_rate = now;
+ best_div = div;
+ best_sel = i;
+ }
+ debug("p_rate=%lu, best_rate=%lu, div=%u, sel=%u\n",
+ pll_rate, best_rate, best_div, best_sel);
+ }
+
+ if (best_rate) {
+ rk_clrsetreg(&cru->clksel_con[con],
+ mask,
+ best_sel << sel_shift |
+ (best_div - 1) << div_shift);
+ } else {
+ printf("do not support this vop freq %lu\n", rate);
+ return -EINVAL;
+ }
+
+ return rk3576_clk_csihost_get_clk(priv, clk_id);
+}
+
+static ulong rk3576_dclk_ebc_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 div, sel, con, parent;
+ unsigned long m = 0, n = 0;
+
+ switch (clk_id) {
+ case DCLK_EBC:
+ con = readl(&cru->clksel_con[123]);
+ div = (con & DCLK_EBC_DIV_MASK) >> DCLK_EBC_DIV_SHIFT;
+ sel = (con & DCLK_EBC_SEL_MASK) >> DCLK_EBC_SEL_SHIFT;
+ if (sel == DCLK_EBC_SEL_CPLL)
+ parent = priv->cpll_hz;
+ else if (sel == DCLK_EBC_SEL_VPLL)
+ parent = priv->vpll_hz;
+ else if (sel == DCLK_EBC_SEL_AUPLL)
+ parent = priv->aupll_hz;
+ else if (sel == DCLK_EBC_SEL_LPLL)
+ parent = priv->lpll_hz / 2;
+ else if (sel == DCLK_EBC_SEL_GPLL)
+ parent = priv->gpll_hz;
+ else if (sel == DCLK_EBC_SEL_FRAC_SRC)
+ parent = rk3576_dclk_ebc_get_clk(priv, DCLK_EBC_FRAC_SRC);
+ else
+ parent = OSC_HZ;
+ return DIV_TO_RATE(parent, div);
+ case DCLK_EBC_FRAC_SRC:
+ con = readl(&cru->clksel_con[123]);
+ div = readl(&cru->clksel_con[122]);
+ sel = (con & DCLK_EBC_FRAC_SRC_SEL_MASK) >> DCLK_EBC_FRAC_SRC_SEL_SHIFT;
+ if (sel == DCLK_EBC_FRAC_SRC_SEL_GPLL)
+ parent = priv->gpll_hz;
+ else if (sel == DCLK_EBC_FRAC_SRC_SEL_CPLL)
+ parent = priv->cpll_hz;
+ else if (sel == DCLK_EBC_FRAC_SRC_SEL_VPLL)
+ parent = priv->vpll_hz;
+ else if (sel == DCLK_EBC_FRAC_SRC_SEL_AUPLL)
+ parent = priv->aupll_hz;
+ else
+ parent = OSC_HZ;
+
+ n = div & CLK_UART_FRAC_NUMERATOR_MASK;
+ n >>= CLK_UART_FRAC_NUMERATOR_SHIFT;
+ m = div & CLK_UART_FRAC_DENOMINATOR_MASK;
+ m >>= CLK_UART_FRAC_DENOMINATOR_SHIFT;
+ return parent * n / m;
+ default:
+ return -ENOENT;
+ }
+}
+
+static ulong rk3576_dclk_ebc_set_clk(struct rk3576_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3576_cru *cru = priv->cru;
+ ulong pll_rate, now, best_rate = 0;
+ u32 i, con, sel, div, best_div = 0, best_sel = 0;
+ unsigned long m = 0, n = 0, val;
+
+ switch (clk_id) {
+ case DCLK_EBC:
+ con = readl(&cru->clksel_con[123]);
+ sel = (con & DCLK_EBC_SEL_MASK) >> DCLK_EBC_SEL_SHIFT;
+ if (sel == DCLK_EBC_SEL_VPLL) {
+ pll_rate = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL],
+ priv->cru, VPLL);
+ if (pll_rate >= RK3576_VOP_PLL_LIMIT_FREQ &&
+ pll_rate % rate == 0) {
+ div = DIV_ROUND_UP(pll_rate, rate);
+ rk_clrsetreg(&cru->clksel_con[123],
+ DCLK_EBC_DIV_MASK,
+ (div - 1) << DCLK_EBC_DIV_SHIFT);
+ } else {
+ div = DIV_ROUND_UP(RK3576_VOP_PLL_LIMIT_FREQ,
+ rate);
+ if (div % 2)
+ div = div + 1;
+ rk_clrsetreg(&cru->clksel_con[123],
+ DCLK_EBC_DIV_MASK,
+ (div - 1) << DCLK_EBC_DIV_SHIFT);
+ rockchip_pll_set_rate(&rk3576_pll_clks[VPLL],
+ priv->cru,
+ VPLL, div * rate);
+ priv->vpll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL],
+ priv->cru,
+ VPLL);
+ }
+ } else if (sel == DCLK_EBC_SEL_FRAC_SRC) {
+ rk3576_dclk_ebc_set_clk(priv, DCLK_EBC_FRAC_SRC, rate);
+ div = rk3576_dclk_ebc_get_clk(priv, DCLK_EBC_FRAC_SRC) / rate;
+ rk_clrsetreg(&cru->clksel_con[123],
+ DCLK_EBC_DIV_MASK,
+ (div - 1) << DCLK_EBC_DIV_SHIFT);
+ } else {
+ for (i = 0; i <= DCLK_EBC_SEL_LPLL; i++) {
+ switch (i) {
+ case DCLK_EBC_SEL_GPLL:
+ pll_rate = priv->gpll_hz;
+ break;
+ case DCLK_EBC_SEL_CPLL:
+ pll_rate = priv->cpll_hz;
+ break;
+ case DCLK_EBC_SEL_VPLL:
+ pll_rate = 0;
+ break;
+ case DCLK_EBC_SEL_AUPLL:
+ pll_rate = priv->aupll_hz;
+ break;
+ case DCLK_EBC_SEL_LPLL:
+ pll_rate = 0;
+ break;
+ default:
+ printf("not support ebc pll sel\n");
+ return -EINVAL;
+ }
+
+ div = DIV_ROUND_UP(pll_rate, rate);
+ if (div > 255)
+ continue;
+ now = pll_rate / div;
+ if (abs(rate - now) < abs(rate - best_rate)) {
+ best_rate = now;
+ best_div = div;
+ best_sel = i;
+ }
+ }
+
+ if (best_rate) {
+ rk_clrsetreg(&cru->clksel_con[123],
+ DCLK_EBC_DIV_MASK |
+ DCLK_EBC_SEL_MASK,
+ best_sel <<
+ DCLK_EBC_SEL_SHIFT |
+ (best_div - 1) <<
+ DCLK_EBC_DIV_SHIFT);
+ } else {
+ printf("do not support this vop freq %lu\n",
+ rate);
+ return -EINVAL;
+ }
+ }
+ break;
+ case DCLK_EBC_FRAC_SRC:
+ sel = DCLK_EBC_FRAC_SRC_SEL_GPLL;
+ div = 1;
+ rational_best_approximation(rate, priv->gpll_hz,
+ GENMASK(16 - 1, 0),
+ GENMASK(16 - 1, 0),
+ &m, &n);
+
+ if (m < 4 && m != 0) {
+ if (n % 2 == 0)
+ val = 1;
+ else
+ val = DIV_ROUND_UP(4, m);
+
+ n *= val;
+ m *= val;
+ if (n > 0xffff)
+ n = 0xffff;
+ }
+
+ rk_clrsetreg(&cru->clksel_con[123],
+ DCLK_EBC_FRAC_SRC_SEL_MASK,
+ (sel << DCLK_EBC_FRAC_SRC_SEL_SHIFT));
+ if (m && n) {
+ val = m << CLK_UART_FRAC_NUMERATOR_SHIFT | n;
+ writel(val, &cru->clksel_con[122]);
+ }
+ break;
+ default:
+ return -ENOENT;
+ }
+ return rk3576_dclk_ebc_get_clk(priv, clk_id);
+}
+
+static ulong rk3576_gmac_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 con, div, src, p_rate;
+
+ switch (clk_id) {
+ case CLK_GMAC0_PTP_REF_SRC:
+ case CLK_GMAC0_PTP_REF:
+ con = readl(&cru->clksel_con[105]);
+ div = (con & CLK_GMAC0_PTP_DIV_MASK) >> CLK_GMAC0_PTP_DIV_SHIFT;
+ src = (con & CLK_GMAC0_PTP_SEL_MASK) >> CLK_GMAC0_PTP_SEL_SHIFT;
+ if (src == CLK_GMAC0_PTP_SEL_GPLL)
+ p_rate = priv->gpll_hz;
+ else if (src == CLK_GMAC0_PTP_SEL_CPLL)
+ p_rate = priv->cpll_hz;
+ else
+ p_rate = GMAC0_PTP_REFCLK_IN;
+ return DIV_TO_RATE(p_rate, div);
+ case CLK_GMAC1_PTP_REF_SRC:
+ case CLK_GMAC1_PTP_REF:
+ con = readl(&cru->clksel_con[104]);
+ div = (con & CLK_GMAC1_PTP_DIV_MASK) >> CLK_GMAC0_PTP_DIV_SHIFT;
+ src = (con & CLK_GMAC1_PTP_SEL_MASK) >> CLK_GMAC1_PTP_SEL_SHIFT;
+ if (src == CLK_GMAC1_PTP_SEL_GPLL)
+ p_rate = priv->gpll_hz;
+ else if (src == CLK_GMAC1_PTP_SEL_CPLL)
+ p_rate = priv->cpll_hz;
+ else
+ p_rate = GMAC1_PTP_REFCLK_IN;
+ return DIV_TO_RATE(p_rate, div);
+ case CLK_GMAC0_125M_SRC:
+ con = readl(&cru->clksel_con[30]);
+ div = (con & CLK_GMAC0_125M_DIV_MASK) >> CLK_GMAC0_125M_DIV_SHIFT;
+ return DIV_TO_RATE(priv->cpll_hz, div);
+ case CLK_GMAC1_125M_SRC:
+ con = readl(&cru->clksel_con[31]);
+ div = (con & CLK_GMAC1_125M_DIV_MASK) >> CLK_GMAC1_125M_DIV_SHIFT;
+ return DIV_TO_RATE(priv->cpll_hz, div);
+ default:
+ return -ENOENT;
+ }
+}
+
+static ulong rk3576_gmac_set_clk(struct rk3576_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3576_cru *cru = priv->cru;
+ int div, src;
+
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+
+ switch (clk_id) {
+ case CLK_GMAC0_PTP_REF_SRC:
+ case CLK_GMAC0_PTP_REF:
+ if (rate == GMAC0_PTP_REFCLK_IN) {
+ src = CLK_GMAC0_PTP_SEL_REFIN;
+ div = 1;
+ } else if (!(priv->gpll_hz % rate)) {
+ src = CLK_GMAC0_PTP_SEL_GPLL;
+ div = priv->gpll_hz / rate;
+ } else {
+ src = CLK_GMAC0_PTP_SEL_CPLL;
+ div = priv->cpll_hz / rate;
+ }
+ rk_clrsetreg(&cru->clksel_con[105],
+ CLK_GMAC0_PTP_DIV_MASK | CLK_GMAC0_PTP_SEL_MASK,
+ src << CLK_GMAC0_PTP_SEL_SHIFT |
+ (div - 1) << CLK_GMAC0_PTP_DIV_SHIFT);
+ break;
+ case CLK_GMAC1_PTP_REF_SRC:
+ case CLK_GMAC1_PTP_REF:
+ if (rate == GMAC1_PTP_REFCLK_IN) {
+ src = CLK_GMAC1_PTP_SEL_REFIN;
+ div = 1;
+ } else if (!(priv->gpll_hz % rate)) {
+ src = CLK_GMAC1_PTP_SEL_GPLL;
+ div = priv->gpll_hz / rate;
+ } else {
+ src = CLK_GMAC1_PTP_SEL_CPLL;
+ div = priv->cpll_hz / rate;
+ }
+ rk_clrsetreg(&cru->clksel_con[104],
+ CLK_GMAC1_PTP_DIV_MASK | CLK_GMAC1_PTP_SEL_MASK,
+ src << CLK_GMAC1_PTP_SEL_SHIFT |
+ (div - 1) << CLK_GMAC1_PTP_DIV_SHIFT);
+ break;
+
+ case CLK_GMAC0_125M_SRC:
+ rk_clrsetreg(&cru->clksel_con[30],
+ CLK_GMAC0_125M_DIV_MASK,
+ (div - 1) << CLK_GMAC0_125M_DIV_SHIFT);
+ break;
+ case CLK_GMAC1_125M_SRC:
+ rk_clrsetreg(&cru->clksel_con[31],
+ CLK_GMAC1_125M_DIV_MASK,
+ (div - 1) << CLK_GMAC1_125M_DIV_SHIFT);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rk3576_gmac_get_clk(priv, clk_id);
+}
+
+static ulong rk3576_uart_frac_get_rate(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 reg, con, fracdiv, p_src, p_rate;
+ unsigned long m, n;
+
+ switch (clk_id) {
+ case CLK_UART_FRAC_0:
+ reg = 21;
+ break;
+ case CLK_UART_FRAC_1:
+ reg = 23;
+ break;
+ case CLK_UART_FRAC_2:
+ reg = 25;
+ break;
+ default:
+ return -ENOENT;
+ }
+ con = readl(&cru->clksel_con[reg + 1]);
+ p_src = (con & CLK_UART_SRC_SEL_MASK) >> CLK_UART_SRC_SEL_SHIFT;
+ if (p_src == CLK_UART_SRC_SEL_GPLL)
+ p_rate = priv->gpll_hz;
+ else if (p_src == CLK_UART_SRC_SEL_CPLL)
+ p_rate = priv->cpll_hz;
+ else if (p_src == CLK_UART_SRC_SEL_AUPLL)
+ p_rate = priv->aupll_hz;
+ else
+ p_rate = OSC_HZ;
+
+ fracdiv = readl(&cru->clksel_con[reg]);
+ n = fracdiv & CLK_UART_FRAC_NUMERATOR_MASK;
+ n >>= CLK_UART_FRAC_NUMERATOR_SHIFT;
+ m = fracdiv & CLK_UART_FRAC_DENOMINATOR_MASK;
+ m >>= CLK_UART_FRAC_DENOMINATOR_SHIFT;
+ return p_rate * n / m;
+}
+
+static ulong rk3576_uart_frac_set_rate(struct rk3576_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 reg, clk_src, p_rate;
+ unsigned long m = 0, n = 0, val;
+
+ if (priv->cpll_hz % rate == 0) {
+ clk_src = CLK_UART_SRC_SEL_CPLL;
+ p_rate = priv->cpll_hz;
+ } else if (rate == OSC_HZ) {
+ clk_src = CLK_UART_SRC_SEL_OSC;
+ p_rate = OSC_HZ;
+ } else {
+ clk_src = CLK_UART_SRC_SEL_GPLL;
+ p_rate = priv->cpll_hz;
+ }
+
+ rational_best_approximation(rate, p_rate, GENMASK(16 - 1, 0),
+ GENMASK(16 - 1, 0), &m, &n);
+
+ if (m < 4 && m != 0) {
+ if (n % 2 == 0)
+ val = 1;
+ else
+ val = DIV_ROUND_UP(4, m);
+
+ n *= val;
+ m *= val;
+ if (n > 0xffff)
+ n = 0xffff;
+ }
+
+ switch (clk_id) {
+ case CLK_UART_FRAC_0:
+ reg = 21;
+ break;
+ case CLK_UART_FRAC_1:
+ reg = 23;
+ break;
+ case CLK_UART_FRAC_2:
+ reg = 25;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ rk_clrsetreg(&cru->clksel_con[reg + 1],
+ CLK_UART_SRC_SEL_MASK,
+ (clk_src << CLK_UART_SRC_SEL_SHIFT));
+ if (m && n) {
+ val = m << CLK_UART_FRAC_NUMERATOR_SHIFT | n;
+ writel(val, &cru->clksel_con[reg]);
+ }
+
+ return rk3576_uart_frac_get_rate(priv, clk_id);
+}
+
+static ulong rk3576_uart_get_rate(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 con, div, src, p_rate;
+
+ switch (clk_id) {
+ case SCLK_UART0:
+ con = readl(&cru->clksel_con[60]);
+ break;
+ case SCLK_UART1:
+ con = readl(&cru->pmuclksel_con[8]);
+ src = (con & CLK_UART1_SEL_MASK) >> CLK_UART1_SEL_SHIFT;
+ if (src == CLK_UART1_SEL_OSC)
+ return OSC_HZ;
+ con = readl(&cru->clksel_con[27]);
+ break;
+ case SCLK_UART2:
+ con = readl(&cru->clksel_con[61]);
+ break;
+ case SCLK_UART3:
+ con = readl(&cru->clksel_con[62]);
+ break;
+ case SCLK_UART4:
+ con = readl(&cru->clksel_con[63]);
+ break;
+ case SCLK_UART5:
+ con = readl(&cru->clksel_con[64]);
+ break;
+ case SCLK_UART6:
+ con = readl(&cru->clksel_con[65]);
+ break;
+ case SCLK_UART7:
+ con = readl(&cru->clksel_con[66]);
+ break;
+ case SCLK_UART8:
+ con = readl(&cru->clksel_con[67]);
+ break;
+ case SCLK_UART9:
+ con = readl(&cru->clksel_con[68]);
+ break;
+ case SCLK_UART10:
+ con = readl(&cru->clksel_con[69]);
+ break;
+ case SCLK_UART11:
+ con = readl(&cru->clksel_con[70]);
+ break;
+ default:
+ return -ENOENT;
+ }
+ if (clk_id == SCLK_UART1) {
+ src = (con & CLK_UART1_SRC_SEL_SHIFT) >> CLK_UART1_SRC_SEL_SHIFT;
+ div = (con & CLK_UART1_SRC_DIV_MASK) >> CLK_UART1_SRC_DIV_SHIFT;
+ } else {
+ src = (con & CLK_UART_SEL_MASK) >> CLK_UART_SEL_SHIFT;
+ div = (con & CLK_UART_DIV_MASK) >> CLK_UART_DIV_SHIFT;
+ }
+ if (src == CLK_UART_SEL_GPLL)
+ p_rate = priv->gpll_hz;
+ else if (src == CLK_UART_SEL_CPLL)
+ p_rate = priv->cpll_hz;
+ else if (src == CLK_UART_SEL_AUPLL)
+ p_rate = priv->aupll_hz;
+ else if (src == CLK_UART_SEL_FRAC0)
+ p_rate = rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_0);
+ else if (src == CLK_UART_SEL_FRAC1)
+ p_rate = rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_1);
+ else if (src == CLK_UART_SEL_FRAC2)
+ p_rate = rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_2);
+ else
+ p_rate = OSC_HZ;
+
+ return DIV_TO_RATE(p_rate, div);
+}
+
+static ulong rk3576_uart_set_rate(struct rk3576_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 reg, clk_src = 0, div = 0;
+
+ if (!(priv->gpll_hz % rate)) {
+ clk_src = CLK_UART_SEL_GPLL;
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ } else if (!(priv->cpll_hz % rate)) {
+ clk_src = CLK_UART_SEL_CPLL;
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ } else if (!(rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_0) % rate)) {
+ clk_src = CLK_UART_SEL_FRAC0;
+ div = DIV_ROUND_UP(rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_0), rate);
+ } else if (!(rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_1) % rate)) {
+ clk_src = CLK_UART_SEL_FRAC1;
+ div = DIV_ROUND_UP(rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_1), rate);
+ } else if (!(rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_2) % rate)) {
+ clk_src = CLK_UART_SEL_FRAC2;
+ div = DIV_ROUND_UP(rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_2), rate);
+ } else if (!(OSC_HZ % rate)) {
+ clk_src = CLK_UART_SEL_OSC;
+ div = DIV_ROUND_UP(OSC_HZ, rate);
+ }
+
+ switch (clk_id) {
+ case SCLK_UART0:
+ reg = 60;
+ break;
+ case SCLK_UART1:
+ if (rate == OSC_HZ) {
+ rk_clrsetreg(&cru->pmuclksel_con[8],
+ CLK_UART1_SEL_MASK,
+ CLK_UART1_SEL_OSC << CLK_UART1_SEL_SHIFT);
+ return 0;
+ }
+
+ rk_clrsetreg(&cru->clksel_con[27],
+ CLK_UART1_SRC_SEL_MASK | CLK_UART1_SRC_DIV_MASK,
+ (clk_src << CLK_UART1_SRC_SEL_SHIFT) |
+ ((div - 1) << CLK_UART1_SRC_DIV_SHIFT));
+ rk_clrsetreg(&cru->pmuclksel_con[8],
+ CLK_UART1_SEL_MASK,
+ CLK_UART1_SEL_TOP << CLK_UART1_SEL_SHIFT);
+ return 0;
+ case SCLK_UART2:
+ reg = 61;
+ break;
+ case SCLK_UART3:
+ reg = 62;
+ break;
+ case SCLK_UART4:
+ reg = 63;
+ break;
+ case SCLK_UART5:
+ reg = 64;
+ break;
+ case SCLK_UART6:
+ reg = 65;
+ break;
+ case SCLK_UART7:
+ reg = 66;
+ break;
+ case SCLK_UART8:
+ reg = 67;
+ break;
+ case SCLK_UART9:
+ reg = 68;
+ break;
+ case SCLK_UART10:
+ reg = 69;
+ break;
+ case SCLK_UART11:
+ reg = 70;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ rk_clrsetreg(&cru->clksel_con[reg],
+ CLK_UART_SEL_MASK |
+ CLK_UART_DIV_MASK,
+ (clk_src << CLK_UART_SEL_SHIFT) |
+ ((div - 1) << CLK_UART_DIV_SHIFT));
+
+ return rk3576_uart_get_rate(priv, clk_id);
+}
+#endif
+
+static ulong rk3576_ufs_ref_get_rate(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 src, div;
+
+ src = readl(&cru->pmuclksel_con[3]) & 0x3;
+ div = readl(&cru->pmuclksel_con[1]) & 0xff;
+ if (src == 0)
+ return OSC_HZ;
+ else if (src == 2)
+ return priv->ppll_hz / (div + 1);
+ else
+ return 26000000;
+}
+
+static ulong rk3576_clk_get_rate(struct clk *clk)
+{
+ struct rk3576_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong rate = 0;
+
+ if (!priv->gpll_hz) {
+ printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
+ return -ENOENT;
+ }
+
+ if (!priv->ppll_hz) {
+ priv->ppll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[PPLL],
+ priv->cru, PPLL);
+ }
+
+ switch (clk->id) {
+ case PLL_LPLL:
+ rate = rockchip_pll_get_rate(&rk3576_pll_clks[LPLL], priv->cru,
+ LPLL);
+ priv->lpll_hz = rate;
+ break;
+ case PLL_BPLL:
+ rate = rockchip_pll_get_rate(&rk3576_pll_clks[BPLL], priv->cru,
+ BPLL);
+ priv->bpll_hz = rate;
+ break;
+ case PLL_GPLL:
+ rate = rockchip_pll_get_rate(&rk3576_pll_clks[GPLL], priv->cru,
+ GPLL);
+ break;
+ case PLL_CPLL:
+ rate = rockchip_pll_get_rate(&rk3576_pll_clks[CPLL], priv->cru,
+ CPLL);
+ break;
+ case PLL_VPLL:
+ rate = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL], priv->cru,
+ VPLL);
+ break;
+ case PLL_AUPLL:
+ rate = rockchip_pll_get_rate(&rk3576_pll_clks[AUPLL], priv->cru,
+ AUPLL);
+ break;
+ case PLL_PPLL:
+ rate = rockchip_pll_get_rate(&rk3576_pll_clks[PPLL], priv->cru,
+ PPLL) * 2;
+ break;
+ case ACLK_BUS_ROOT:
+ case HCLK_BUS_ROOT:
+ case PCLK_BUS_ROOT:
+ rate = rk3576_bus_get_clk(priv, clk->id);
+ break;
+ case ACLK_TOP:
+ case HCLK_TOP:
+ case PCLK_TOP_ROOT:
+ case ACLK_TOP_MID:
+ rate = rk3576_top_get_clk(priv, clk->id);
+ break;
+ case CLK_I2C0:
+ case CLK_I2C1:
+ case CLK_I2C2:
+ case CLK_I2C3:
+ case CLK_I2C4:
+ case CLK_I2C5:
+ case CLK_I2C6:
+ case CLK_I2C7:
+ case CLK_I2C8:
+ case CLK_I2C9:
+ rate = rk3576_i2c_get_clk(priv, clk->id);
+ break;
+ case CLK_SPI0:
+ case CLK_SPI1:
+ case CLK_SPI2:
+ case CLK_SPI3:
+ case CLK_SPI4:
+ rate = rk3576_spi_get_clk(priv, clk->id);
+ break;
+ case CLK_PWM1:
+ case CLK_PWM2:
+ case CLK_PMU1PWM:
+ rate = rk3576_pwm_get_clk(priv, clk->id);
+ break;
+ case CLK_SARADC:
+ case CLK_TSADC:
+ rate = rk3576_adc_get_clk(priv, clk->id);
+ break;
+ case CCLK_SRC_SDIO:
+ case CCLK_SRC_SDMMC0:
+ case CCLK_SRC_EMMC:
+ case BCLK_EMMC:
+ case SCLK_FSPI_X2:
+ case SCLK_FSPI1_X2:
+ case DCLK_DECOM:
+ case HCLK_SDMMC0:
+ case HCLK_EMMC:
+ case HCLK_SDIO:
+ rate = rk3576_mmc_get_clk(priv, clk->id);
+ break;
+ case TCLK_EMMC:
+ case TCLK_WDT0:
+ rate = OSC_HZ;
+ break;
+#ifndef CONFIG_SPL_BUILD
+ case ACLK_VOP_ROOT:
+ case ACLK_VOP:
+ case ACLK_VO0_ROOT:
+ case ACLK_VO1_ROOT:
+ case HCLK_VOP_ROOT:
+ case PCLK_VOP_ROOT:
+ rate = rk3576_aclk_vop_get_clk(priv, clk->id);
+ break;
+ case DCLK_VP0:
+ case DCLK_VP0_SRC:
+ case DCLK_VP1:
+ case DCLK_VP1_SRC:
+ case DCLK_VP2:
+ case DCLK_VP2_SRC:
+ rate = rk3576_dclk_vop_get_clk(priv, clk->id);
+ break;
+ case CLK_GMAC0_PTP_REF_SRC:
+ case CLK_GMAC1_PTP_REF_SRC:
+ case CLK_GMAC0_PTP_REF:
+ case CLK_GMAC1_PTP_REF:
+ case CLK_GMAC0_125M_SRC:
+ case CLK_GMAC1_125M_SRC:
+ rate = rk3576_gmac_get_clk(priv, clk->id);
+ break;
+ case CLK_UART_FRAC_0:
+ case CLK_UART_FRAC_1:
+ case CLK_UART_FRAC_2:
+ rate = rk3576_uart_frac_get_rate(priv, clk->id);
+ break;
+ case SCLK_UART0:
+ case SCLK_UART1:
+ case SCLK_UART2:
+ case SCLK_UART3:
+ case SCLK_UART4:
+ case SCLK_UART5:
+ case SCLK_UART6:
+ case SCLK_UART7:
+ case SCLK_UART8:
+ case SCLK_UART9:
+ case SCLK_UART10:
+ case SCLK_UART11:
+ rate = rk3576_uart_get_rate(priv, clk->id);
+ break;
+ case CLK_DSIHOST0:
+ rate = rk3576_clk_csihost_get_clk(priv, clk->id);
+ break;
+ case DCLK_EBC:
+ case DCLK_EBC_FRAC_SRC:
+ rate = rk3576_dclk_ebc_get_clk(priv, clk->id);
+ break;
+#endif
+ case CLK_REF_UFS_CLKOUT:
+ case CLK_REF_OSC_MPHY:
+ rate = rk3576_ufs_ref_get_rate(priv, clk->id);
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ return rate;
+};
+
+static ulong rk3576_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct rk3576_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong ret = 0;
+
+ if (!priv->ppll_hz) {
+ priv->ppll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[PPLL],
+ priv->cru, PPLL);
+ }
+ if (!priv->aupll_hz) {
+ priv->aupll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[AUPLL],
+ priv->cru, AUPLL);
+ }
+
+ switch (clk->id) {
+ case PLL_CPLL:
+ ret = rockchip_pll_set_rate(&rk3576_pll_clks[CPLL], priv->cru,
+ CPLL, rate);
+ priv->cpll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[CPLL],
+ priv->cru, CPLL);
+ break;
+ case PLL_GPLL:
+ ret = rockchip_pll_set_rate(&rk3576_pll_clks[GPLL], priv->cru,
+ GPLL, rate);
+ priv->gpll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[GPLL],
+ priv->cru, GPLL);
+ break;
+ case PLL_VPLL:
+ ret = rockchip_pll_set_rate(&rk3576_pll_clks[VPLL], priv->cru,
+ VPLL, rate);
+ priv->vpll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL],
+ priv->cru, VPLL);
+ break;
+ case PLL_AUPLL:
+ ret = rockchip_pll_set_rate(&rk3576_pll_clks[AUPLL], priv->cru,
+ AUPLL, rate);
+ priv->aupll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[AUPLL],
+ priv->cru, AUPLL);
+ break;
+ case PLL_PPLL:
+ ret = rockchip_pll_set_rate(&rk3576_pll_clks[PPLL], priv->cru,
+ PPLL, rate);
+ priv->ppll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[PPLL],
+ priv->cru, PPLL) * 2;
+ break;
+ case ACLK_BUS_ROOT:
+ case HCLK_BUS_ROOT:
+ case PCLK_BUS_ROOT:
+ ret = rk3576_bus_set_clk(priv, clk->id, rate);
+ break;
+ case ACLK_TOP:
+ case HCLK_TOP:
+ case PCLK_TOP_ROOT:
+ case ACLK_TOP_MID:
+ ret = rk3576_top_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_I2C0:
+ case CLK_I2C1:
+ case CLK_I2C2:
+ case CLK_I2C3:
+ case CLK_I2C4:
+ case CLK_I2C5:
+ case CLK_I2C6:
+ case CLK_I2C7:
+ case CLK_I2C8:
+ case CLK_I2C9:
+ ret = rk3576_i2c_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_SPI0:
+ case CLK_SPI1:
+ case CLK_SPI2:
+ case CLK_SPI3:
+ case CLK_SPI4:
+ ret = rk3576_spi_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_PWM1:
+ case CLK_PWM2:
+ case CLK_PMU1PWM:
+ ret = rk3576_pwm_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_SARADC:
+ case CLK_TSADC:
+ ret = rk3576_adc_set_clk(priv, clk->id, rate);
+ break;
+ case CCLK_SRC_SDIO:
+ case CCLK_SRC_SDMMC0:
+ case CCLK_SRC_EMMC:
+ case BCLK_EMMC:
+ case SCLK_FSPI_X2:
+ case SCLK_FSPI1_X2:
+ case DCLK_DECOM:
+ case HCLK_SDMMC0:
+ case HCLK_EMMC:
+ case HCLK_SDIO:
+ ret = rk3576_mmc_set_clk(priv, clk->id, rate);
+ break;
+ case TCLK_EMMC:
+ case TCLK_WDT0:
+ ret = OSC_HZ;
+ break;
+
+ /* Might occur in cru assigned-clocks, can be ignored here */
+ case CLK_AUDIO_FRAC_0:
+ case CLK_AUDIO_FRAC_1:
+ case CLK_AUDIO_FRAC_0_SRC:
+ case CLK_AUDIO_FRAC_1_SRC:
+ case CLK_CPLL_DIV2:
+ case CLK_CPLL_DIV4:
+ case CLK_CPLL_DIV10:
+ case FCLK_DDR_CM0_CORE:
+ case ACLK_PHP_ROOT:
+ ret = 0;
+ break;
+#ifndef CONFIG_SPL_BUILD
+ case ACLK_VOP_ROOT:
+ case ACLK_VOP:
+ case ACLK_VO0_ROOT:
+ case ACLK_VO1_ROOT:
+ case HCLK_VOP_ROOT:
+ case PCLK_VOP_ROOT:
+ ret = rk3576_aclk_vop_set_clk(priv, clk->id, rate);
+ break;
+ case DCLK_VP0:
+ case DCLK_VP0_SRC:
+ case DCLK_VP1:
+ case DCLK_VP1_SRC:
+ case DCLK_VP2:
+ case DCLK_VP2_SRC:
+ ret = rk3576_dclk_vop_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_GMAC0_PTP_REF_SRC:
+ case CLK_GMAC1_PTP_REF_SRC:
+ case CLK_GMAC0_PTP_REF:
+ case CLK_GMAC1_PTP_REF:
+ case CLK_GMAC0_125M_SRC:
+ case CLK_GMAC1_125M_SRC:
+ ret = rk3576_gmac_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_UART_FRAC_0:
+ case CLK_UART_FRAC_1:
+ case CLK_UART_FRAC_2:
+ ret = rk3576_uart_frac_set_rate(priv, clk->id, rate);
+ break;
+ case SCLK_UART0:
+ case SCLK_UART1:
+ case SCLK_UART2:
+ case SCLK_UART3:
+ case SCLK_UART4:
+ case SCLK_UART5:
+ case SCLK_UART6:
+ case SCLK_UART7:
+ case SCLK_UART8:
+ case SCLK_UART9:
+ case SCLK_UART10:
+ case SCLK_UART11:
+ ret = rk3576_uart_set_rate(priv, clk->id, rate);
+ break;
+ case CLK_DSIHOST0:
+ ret = rk3576_clk_csihost_set_clk(priv, clk->id, rate);
+ break;
+ case DCLK_EBC:
+ case DCLK_EBC_FRAC_SRC:
+ ret = rk3576_dclk_ebc_set_clk(priv, clk->id, rate);
+ break;
+#endif
+ default:
+ return -ENOENT;
+ }
+
+ return ret;
+};
+
+#if (IS_ENABLED(OF_CONTROL)) || (!IS_ENABLED(OF_PLATDATA))
+static int __maybe_unused rk3576_dclk_vop_set_parent(struct clk *clk,
+ struct clk *parent)
+{
+ struct rk3576_clk_priv *priv = dev_get_priv(clk->dev);
+ struct rk3576_cru *cru = priv->cru;
+ u32 sel;
+ const char *clock_dev_name = parent->dev->name;
+
+ if (parent->id == PLL_VPLL)
+ sel = 2;
+ else if (parent->id == PLL_GPLL)
+ sel = 0;
+ else if (parent->id == PLL_CPLL)
+ sel = 1;
+ else if (parent->id == PLL_BPLL)
+ sel = 3;
+ else
+ sel = 4;
+
+ switch (clk->id) {
+ case DCLK_VP0_SRC:
+ rk_clrsetreg(&cru->clksel_con[145], DCLK0_VOP_SRC_SEL_MASK,
+ sel << DCLK0_VOP_SRC_SEL_SHIFT);
+ break;
+ case DCLK_VP1_SRC:
+ rk_clrsetreg(&cru->clksel_con[146], DCLK0_VOP_SRC_SEL_MASK,
+ sel << DCLK0_VOP_SRC_SEL_SHIFT);
+ break;
+ case DCLK_VP2_SRC:
+ rk_clrsetreg(&cru->clksel_con[147], DCLK0_VOP_SRC_SEL_MASK,
+ sel << DCLK0_VOP_SRC_SEL_SHIFT);
+ break;
+ case DCLK_VP0:
+ if (!strcmp(clock_dev_name, "hdmiphypll_clk0"))
+ sel = 1;
+ else
+ sel = 0;
+ rk_clrsetreg(&cru->clksel_con[147], DCLK0_VOP_SEL_MASK,
+ sel << DCLK0_VOP_SEL_SHIFT);
+ break;
+ case DCLK_VP1:
+ if (!strcmp(clock_dev_name, "hdmiphypll_clk0"))
+ sel = 1;
+ else
+ sel = 0;
+ rk_clrsetreg(&cru->clksel_con[147], DCLK1_VOP_SEL_MASK,
+ sel << DCLK1_VOP_SEL_SHIFT);
+ break;
+ case DCLK_VP2:
+ if (!strcmp(clock_dev_name, "hdmiphypll_clk0"))
+ sel = 1;
+ else
+ sel = 0;
+ rk_clrsetreg(&cru->clksel_con[147], DCLK2_VOP_SEL_MASK,
+ sel << DCLK2_VOP_SEL_SHIFT);
+ break;
+ case DCLK_EBC:
+ if (parent->id == PLL_GPLL)
+ sel = 0;
+ else if (parent->id == PLL_CPLL)
+ sel = 1;
+ else if (parent->id == PLL_VPLL)
+ sel = 2;
+ else if (parent->id == PLL_AUPLL)
+ sel = 3;
+ else if (parent->id == PLL_LPLL)
+ sel = 4;
+ else if (parent->id == DCLK_EBC_FRAC_SRC)
+ sel = 5;
+ else
+ sel = 6;
+ rk_clrsetreg(&cru->clksel_con[123], DCLK_EBC_SEL_MASK,
+ sel << DCLK_EBC_SEL_SHIFT);
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int __maybe_unused rk3576_ufs_ref_set_parent(struct clk *clk,
+ struct clk *parent)
+{
+ struct rk3576_clk_priv *priv = dev_get_priv(clk->dev);
+ struct rk3576_cru *cru = priv->cru;
+ u32 sel;
+ const char *clock_dev_name = parent->dev->name;
+
+ if (parent->id == CLK_REF_MPHY_26M)
+ sel = 2;
+ else if (!strcmp(clock_dev_name, "xin24m"))
+ sel = 0;
+ else
+ sel = 1;
+
+ rk_clrsetreg(&cru->pmuclksel_con[3], 0x3, sel << 0);
+ return 0;
+}
+
+static int rk3576_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ switch (clk->id) {
+ case DCLK_VP0_SRC:
+ case DCLK_VP1_SRC:
+ case DCLK_VP2_SRC:
+ case DCLK_VP0:
+ case DCLK_VP1:
+ case DCLK_VP2:
+ case DCLK_EBC:
+ return rk3576_dclk_vop_set_parent(clk, parent);
+ case CLK_REF_OSC_MPHY:
+ return rk3576_ufs_ref_set_parent(clk, parent);
+ case CLK_AUDIO_FRAC_0_SRC:
+ case CLK_AUDIO_FRAC_1_SRC:
+ /* Might occur in cru assigned-clocks, can be ignored here */
+ return 0;
+ default:
+ return -ENOENT;
+ }
+
+ return 0;
+}
+#endif
+
+static struct clk_ops rk3576_clk_ops = {
+ .get_rate = rk3576_clk_get_rate,
+ .set_rate = rk3576_clk_set_rate,
+#if (IS_ENABLED(OF_CONTROL)) || (!IS_ENABLED(OF_PLATDATA))
+ .set_parent = rk3576_clk_set_parent,
+#endif
+};
+
+static void rk3576_clk_init(struct rk3576_clk_priv *priv)
+{
+ int ret;
+
+ priv->spll_hz = 702000000;
+
+ if (priv->cpll_hz != CPLL_HZ) {
+ ret = rockchip_pll_set_rate(&rk3576_pll_clks[CPLL], priv->cru,
+ CPLL, CPLL_HZ);
+ if (!ret)
+ priv->cpll_hz = CPLL_HZ;
+ }
+ if (priv->gpll_hz != GPLL_HZ) {
+ ret = rockchip_pll_set_rate(&rk3576_pll_clks[GPLL], priv->cru,
+ GPLL, GPLL_HZ);
+ if (!ret)
+ priv->gpll_hz = GPLL_HZ;
+ }
+ rk_clrsetreg(&priv->cru->clksel_con[123],
+ DCLK_EBC_FRAC_SRC_SEL_MASK,
+ (DCLK_EBC_FRAC_SRC_SEL_GPLL <<
+ DCLK_EBC_FRAC_SRC_SEL_SHIFT));
+}
+
+static int rk3576_clk_probe(struct udevice *dev)
+{
+ struct rk3576_clk_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->sync_kernel = false;
+
+#ifdef CONFIG_SPL_BUILD
+ /* relase presetn_bigcore_biu/cru/grf */
+ writel(0x1c001c00, 0x26010010);
+ /* set spll to normal mode */
+ writel(BITS_WITH_WMASK(2, 0x7U, 6),
+ RK3576_SCRU_BASE + RK3576_PLL_CON(137));
+ writel(BITS_WITH_WMASK(1, 0x3U, 0),
+ RK3576_SCRU_BASE + RK3576_MODE_CON0);
+ /* fix ppll\aupll\cpll */
+ writel(BITS_WITH_WMASK(2, 0x7U, 6),
+ RK3576_CRU_BASE + RK3576_PMU_PLL_CON(129));
+ writel(BITS_WITH_WMASK(2, 0x7U, 6),
+ RK3576_CRU_BASE + RK3576_PLL_CON(97));
+ writel(BITS_WITH_WMASK(2, 0x7U, 6),
+ RK3576_CRU_BASE + RK3576_PLL_CON(105));
+ writel(BITS_WITH_WMASK(1, 0x3U, 6),
+ RK3576_CRU_BASE + RK3576_MODE_CON0);
+ writel(BITS_WITH_WMASK(1, 0x3U, 8),
+ RK3576_CRU_BASE + RK3576_MODE_CON0);
+ /* init cci */
+ writel(0xffff0000, RK3576_CRU_BASE + RK3576_CCI_CLKSEL_CON(4));
+ rockchip_pll_set_rate(&rk3576_pll_clks[BPLL], priv->cru,
+ BPLL, LPLL_HZ);
+ if (!priv->armclk_enter_hz) {
+ ret = rockchip_pll_set_rate(&rk3576_pll_clks[LPLL], priv->cru,
+ LPLL, LPLL_HZ);
+ priv->armclk_enter_hz =
+ rockchip_pll_get_rate(&rk3576_pll_clks[LPLL],
+ priv->cru, LPLL);
+ priv->armclk_init_hz = priv->armclk_enter_hz;
+ rk_clrsetreg(&priv->cru->litclksel_con[0], CLK_LITCORE_DIV_MASK,
+ 0 << CLK_LITCORE_DIV_SHIFT);
+ }
+ /* init cci */
+ writel(0xffff20cb, RK3576_CRU_BASE + RK3576_CCI_CLKSEL_CON(4));
+
+ /* Change bigcore rm from 4 to 3 */
+ writel(0x001c000c, RK3576_BIGCORE_GRF_BASE + 0x3c);
+ writel(0x001c000c, RK3576_BIGCORE_GRF_BASE + 0x44);
+ writel(0x00020002, RK3576_BIGCORE_GRF_BASE + 0x38);
+ udelay(1);
+ writel(0x00020000, RK3576_BIGCORE_GRF_BASE + 0x38);
+ /* Change litcore rm from 4 to 3 */
+ writel(0x001c000c, RK3576_LITCORE_GRF_BASE + 0x3c);
+ writel(0x001c000c, RK3576_LITCORE_GRF_BASE + 0x44);
+ writel(0x00020002, RK3576_LITCORE_GRF_BASE + 0x38);
+ udelay(1);
+ writel(0x00020000, RK3576_LITCORE_GRF_BASE + 0x38);
+ /* Change cci rm form 4 to 3 */
+ writel(0x001c000c, RK3576_CCI_GRF_BASE + 0x54);
+#endif
+
+ rk3576_clk_init(priv);
+
+ /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
+ ret = clk_set_defaults(dev, 1);
+ if (ret)
+ debug("%s clk_set_defaults failed %d\n", __func__, ret);
+ else
+ priv->sync_kernel = true;
+
+ return 0;
+}
+
+static int rk3576_clk_ofdata_to_platdata(struct udevice *dev)
+{
+ struct rk3576_clk_priv *priv = dev_get_priv(dev);
+
+ priv->cru = dev_read_addr_ptr(dev);
+
+ return 0;
+}
+
+static int rk3576_clk_bind(struct udevice *dev)
+{
+ int ret;
+ struct udevice *sys_child;
+ struct sysreset_reg *priv;
+
+ /* The reset driver does not have a device node, so bind it here */
+ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
+ &sys_child);
+ if (ret) {
+ debug("Warning: No sysreset driver: ret=%d\n", ret);
+ } else {
+ priv = malloc(sizeof(struct sysreset_reg));
+ priv->glb_srst_fst_value = offsetof(struct rk3576_cru,
+ glb_srst_fst);
+ priv->glb_srst_snd_value = offsetof(struct rk3576_cru,
+ glb_srsr_snd);
+ dev_set_priv(sys_child, priv);
+ }
+
+#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
+ ret = offsetof(struct rk3576_cru, softrst_con[0]);
+ ret = rk3576_reset_bind_lut(dev, ret, 32776);
+ if (ret)
+ debug("Warning: software reset driver bind failed\n");
+#endif
+
+ return 0;
+}
+
+static const struct udevice_id rk3576_clk_ids[] = {
+ { .compatible = "rockchip,rk3576-cru" },
+ { }
+};
+
+U_BOOT_DRIVER(rockchip_rk3576_cru) = {
+ .name = "rockchip_rk3576_cru",
+ .id = UCLASS_CLK,
+ .of_match = rk3576_clk_ids,
+ .priv_auto = sizeof(struct rk3576_clk_priv),
+ .of_to_plat = rk3576_clk_ofdata_to_platdata,
+ .ops = &rk3576_clk_ops,
+ .bind = rk3576_clk_bind,
+ .probe = rk3576_clk_probe,
+};
diff --git a/drivers/clk/stm32/clk-stm32mp1.c b/drivers/clk/stm32/clk-stm32mp1.c
index 4044edf..9cb69a0 100644
--- a/drivers/clk/stm32/clk-stm32mp1.c
+++ b/drivers/clk/stm32/clk-stm32mp1.c
@@ -551,6 +551,7 @@
STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI, _DSI_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
diff --git a/drivers/core/Makefile b/drivers/core/Makefile
index 657e589..a549890 100644
--- a/drivers/core/Makefile
+++ b/drivers/core/Makefile
@@ -6,16 +6,16 @@
obj-$(CONFIG_$(PHASE_)ACPIGEN) += acpi.o
obj-$(CONFIG_$(PHASE_)DEVRES) += devres.o
obj-$(CONFIG_$(PHASE_)DM_DEVICE_REMOVE) += device-remove.o
-obj-$(CONFIG_$(XPL_)SIMPLE_BUS) += simple-bus.o
+obj-$(CONFIG_$(PHASE_)SIMPLE_BUS) += simple-bus.o
obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o
obj-$(CONFIG_DM) += dump.o
obj-$(CONFIG_$(PHASE_)REGMAP) += regmap.o
obj-$(CONFIG_$(PHASE_)SYSCON) += syscon-uclass.o
-obj-$(CONFIG_$(XPL_)OF_LIVE) += of_access.o of_addr.o
+obj-$(CONFIG_$(PHASE_)OF_LIVE) += of_access.o of_addr.o
ifndef CONFIG_DM_DEV_READ_INLINE
obj-$(CONFIG_OF_CONTROL) += read.o
endif
-obj-$(CONFIG_$(XPL_)OF_PLATDATA) += read.o
+obj-$(CONFIG_$(PHASE_)OF_PLATDATA) += read.o
obj-$(CONFIG_OF_CONTROL) += of_extra.o ofnode.o read_extra.o ofnode_graph.o
ccflags-$(CONFIG_DM_DEBUG) += -DDEBUG
diff --git a/drivers/core/ofnode_graph.c b/drivers/core/ofnode_graph.c
index 90c92af..175ac76 100644
--- a/drivers/core/ofnode_graph.c
+++ b/drivers/core/ofnode_graph.c
@@ -98,7 +98,7 @@
* @id: id for the endpoint
*
* Return: ofnode in given endpoint or ofnode_null() if not found.
- * reg and port_reg are ignored when they are -1.
+ * reg_id and id are ignored when they are -1.
*/
ofnode ofnode_graph_get_endpoint_by_regs(ofnode parent, int reg_id, int id)
{
diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index f846a35..ce5e61b 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -16,6 +16,7 @@
#include <dm/device.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
+#include <dm/ofnode_graph.h>
#include <dm/uclass.h>
#include <dm/uclass-internal.h>
#include <dm/util.h>
@@ -582,6 +583,24 @@
ret = uclass_find_device_by_phandle(id, parent, name, &dev);
return uclass_get_device_tail(dev, ret, devp);
}
+
+int uclass_get_device_by_endpoint(enum uclass_id class_id, struct udevice *dev,
+ int port_idx, int ep_idx, struct udevice **devp)
+{
+ ofnode node_source = dev_ofnode(dev);
+ ofnode node_dest = ofnode_graph_get_remote_node(node_source, port_idx, ep_idx);
+ struct udevice *target = NULL;
+ int ret;
+
+ if (!ofnode_valid(node_dest))
+ return -EINVAL;
+
+ ret = uclass_find_device_by_ofnode(class_id, node_dest, &target);
+ if (ret)
+ return -ENODEV;
+
+ return uclass_get_device_tail(target, 0, devp);
+}
#endif
/*
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index b19f360..c627f16 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -6,7 +6,7 @@
# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
# Copyright (C) 2014-2025 Altera Corporation <www.altera.com>
-ifdef CONFIG_$(XPL_)ALTERA_SDRAM
+ifdef CONFIG_$(PHASE_)ALTERA_SDRAM
obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o
diff --git a/drivers/ddr/altera/iossm_mailbox.c b/drivers/ddr/altera/iossm_mailbox.c
index db9435d..fc09dde 100644
--- a/drivers/ddr/altera/iossm_mailbox.c
+++ b/drivers/ddr/altera/iossm_mailbox.c
@@ -10,6 +10,7 @@
#include <asm/arch/base_addr_soc64.h>
#include <asm/io.h>
#include <linux/bitfield.h>
+#include <linux/sizes.h>
#include "iossm_mailbox.h"
#define TIMEOUT_120000MS 120000
@@ -87,6 +88,7 @@
/* offset info of ECC_ENABLE_INTF */
#define INTF_ECC_ENABLE_TYPE_MASK GENMASK(1, 0)
+#define INTF_ECC_TYPE_MASK BIT(8)
/* cmd opcode BIST_MEM_INIT_START, BIST performed on full memory address range */
#define BIST_FULL_MEM BIT(6)
@@ -96,6 +98,7 @@
/* offset info of ECC_ERR_STATUS */
#define ECC_ERR_COUNTER_MASK GENMASK(15, 0)
+#define ECC_ERR_OVERFLOW_MASK GENMASK(31, 16)
/* offset info of ECC_ERR_DATA */
#define ECC_ERR_IP_TYPE_MASK GENMASK(24, 22)
@@ -104,9 +107,15 @@
#define ECC_ERR_TYPE_MASK GENMASK(9, 6)
#define ECC_ERR_ADDR_UPPER_MASK GENMASK(5, 0)
#define ECC_ERR_ADDR_LOWER_MASK GENMASK(31, 0)
+#define ECC_FULL_ADDR_UPPER_MASK GENMASK(63, 32)
+#define ECC_FULL_ADDR_LOWER_MASK GENMASK(31, 0)
#define MAX_ECC_ERR_INFO_COUNT 16
+#define BIST_START_ADDR_SPACE_MASK GENMASK(5, 0)
+#define BIST_START_ADDR_LOW_MASK GENMASK(31, 0)
+#define BIST_START_ADDR_HIGH_MASK GENMASK(37, 32)
+
#define IO96B_MB_REQ_SETUP(v, w, x, y, z) \
usr_req.ip_type = v; \
usr_req.ip_id = w; \
@@ -161,6 +170,24 @@
u32 addr_lower;
};
+struct ecc_overflow_error_desc {
+ int bit;
+ const char *msg;
+};
+
+static const struct ecc_overflow_error_desc ecc_overflow_errors[] = {
+ { 0, " - Single-bit error\n" },
+ { 1, " - Multiple single-bit errors\n" },
+ { 2, " - Double-bit error\n" },
+ { 3, " - Multiple double-bit errors\n" },
+ { 8, " - Single-bit error during ECC scrubbing\n" },
+ { 9, " - Write link ECC single-bit error (LPDDR5 only)\n" },
+ { 10, " - Write link ECC double-bit error (LPDDR5 only)\n" },
+ { 11, " - Read link ECC single-bit error (LPDDR5 only)\n" },
+ { 12, " - Read link ECC double-bit error (LPDDR5 only)\n" },
+ { 13, " - RMW read link ECC double-bit error (LPDDR5 only)\n" },
+};
+
static int is_ddr_csr_clkgen_locked(u8 io96b_pll)
{
int ret = 0;
@@ -512,7 +539,7 @@
{
int i, j, ret = 0;
u32 mem_width_info;
- u16 memory_size, total_memory_size = 0;
+ phys_size_t memory_size, total_memory_size = 0;
u32 mem_total_capacity_intf_offset[MAX_MEM_INTERFACE_SUPPORTED] = {
IOSSM_MEM_TOTAL_CAPACITY_INTF0_OFFSET,
@@ -526,8 +553,11 @@
mem_width_info = readl(io96b_ctrl->io96b[i].io96b_csr_addr +
mem_total_capacity_intf_offset[j]);
- memory_size = memory_size +
- FIELD_GET(INTF_CAPACITY_GBITS_MASK, mem_width_info);
+ io96b_ctrl->io96b[i].mb_ctrl.memory_size[j] =
+ FIELD_GET(INTF_CAPACITY_GBITS_MASK, mem_width_info) * SZ_1G / SZ_8;
+
+ if (io96b_ctrl->io96b[i].mb_ctrl.memory_size[j] != 0)
+ memory_size += io96b_ctrl->io96b[i].mb_ctrl.memory_size[j];
}
if (!memory_size) {
@@ -536,8 +566,6 @@
goto err;
}
- io96b_ctrl->io96b[i].size = memory_size;
-
total_memory_size = total_memory_size + memory_size;
}
@@ -556,7 +584,7 @@
{
int i, j, ret = 0;
u32 ecc_enable_intf;
- bool ecc_stat, ecc_stat_set = false;
+ bool ecc_status, ecc_status_set = false, inline_ecc = false;
u32 ecc_enable_intf_offset[MAX_MEM_INTERFACE_SUPPORTED] = {
IOSSM_ECC_ENABLE_INTF0_OFFSET,
@@ -565,6 +593,7 @@
/* Initialize ECC status */
io96b_ctrl->ecc_status = false;
+ io96b_ctrl->inline_ecc = false;
/* Get and ensure all memory interface(s) same ECC status */
for (i = 0; i < io96b_ctrl->num_instance; i++) {
@@ -572,15 +601,21 @@
ecc_enable_intf = readl(io96b_ctrl->io96b[i].io96b_csr_addr +
ecc_enable_intf_offset[j]);
- ecc_stat = (FIELD_GET(INTF_ECC_ENABLE_TYPE_MASK, ecc_enable_intf)
+ ecc_status = (FIELD_GET(INTF_ECC_ENABLE_TYPE_MASK, ecc_enable_intf)
== 0) ? false : true;
+ inline_ecc = FIELD_GET(INTF_ECC_TYPE_MASK, ecc_enable_intf);
- if (!ecc_stat_set) {
- io96b_ctrl->ecc_status = ecc_stat;
- ecc_stat_set = true;
+ if (!ecc_status_set) {
+ io96b_ctrl->ecc_status = ecc_status;
+
+ if (io96b_ctrl->ecc_status)
+ io96b_ctrl->inline_ecc = inline_ecc;
+
+ ecc_status_set = true;
}
- if (ecc_stat != io96b_ctrl->ecc_status) {
+ if (ecc_status != io96b_ctrl->ecc_status ||
+ (io96b_ctrl->ecc_status && inline_ecc != io96b_ctrl->inline_ecc)) {
printf("%s: Mismatch DDR ECC status on IO96B_%d\n", __func__, i);
ret = -EINVAL;
@@ -614,16 +649,28 @@
{
int i, j;
u32 ecc_err_status;
- u16 ecc_err_counter;
+ u16 ecc_err_counter, ecc_overflow_status;
bool ecc_error_flag = false;
/* Get ECC double-bit error status */
for (i = 0; i < io96b_ctrl->num_instance; i++) {
ecc_err_status = readl(io96b_ctrl->io96b[i].io96b_csr_addr +
IOSSM_ECC_ERR_STATUS_OFFSET);
+
ecc_err_counter = FIELD_GET(ECC_ERR_COUNTER_MASK, ecc_err_status);
- debug("%s: ECC error number detected on IO96B_%d: %d\n",
- __func__, i, ecc_err_counter);
+ log_err("%s: ECC error number detected on IO96B_%d: %d\n",
+ __func__, i, ecc_err_counter);
+
+ ecc_overflow_status = FIELD_GET(ECC_ERR_OVERFLOW_MASK, ecc_err_status);
+ if (ecc_overflow_status != 0) {
+ log_err("ECC Error Overflow Flags:\n");
+
+ for (int i = 0; i < ARRAY_SIZE(ecc_overflow_errors); i++) {
+ if (ecc_overflow_status & BIT(ecc_overflow_errors[i].bit)) {
+ log_err("%s", ecc_overflow_errors[i].msg);
+ }
+ }
+ }
if (ecc_err_counter != 0) {
phys_addr_t address;
@@ -647,15 +694,20 @@
ecc_err_data);
err_info.addr_lower = readl(address + sizeof(u32));
- debug("%s: ECC double-bit error detected on IO96B_%d:\n",
- __func__, i);
- debug("- error info address :0x%llx\n", address);
- debug("- error ip type: %d\n", err_info.ip_type);
- debug("- error instance id: %d\n", err_info.instance_id);
- debug("- error source id: %d\n", err_info.source_id);
- debug("- error type: %d\n", err_info.err_type);
- debug("- error address upper: 0x%x\n", err_info.addr_upper);
- debug("- error address lower: 0x%x\n", err_info.addr_lower);
+ log_err(" %s: DDR ECC Error Detected on IO96B_%d number:%d\n",
+ __func__, i, j);
+ log_err(" - error info address :0x%llx\n", address);
+ log_err(" - error ip type: %d\n", err_info.ip_type);
+ log_err(" - error instance id: %d\n", err_info.instance_id);
+ log_err(" - error source id: %d\n", err_info.source_id);
+ log_err(" - error type: %s\n",
+ is_double_bit_error(err_info.err_type) ?
+ "Double-bit error" : "Single-bit error");
+ log_err(" - error address: 0x%016llx\n",
+ (u64)FIELD_PREP(ECC_FULL_ADDR_UPPER_MASK,
+ err_info.addr_upper) |
+ FIELD_PREP(ECC_FULL_ADDR_LOWER_MASK,
+ err_info.addr_lower));
if (is_double_bit_error(err_info.err_type)) {
if (!ecc_error_flag)
@@ -668,12 +720,12 @@
}
if (ecc_error_flag)
- printf("\n%s: ECC double-bit error detected!\n", __func__);
+ log_err("\n%s: ECC double-bit error detected!\n", __func__);
return ecc_error_flag;
}
-int bist_mem_init_start(struct io96b_info *io96b_ctrl)
+int out_of_band_bist_mem_init_start(struct io96b_info *io96b_ctrl)
{
struct io96b_mb_req usr_req;
struct io96b_mb_resp usr_resp;
@@ -746,3 +798,126 @@
err:
return ret;
}
+
+int bist_mem_init_by_addr(struct io96b_info *io96b_ctrl, int inst_id, int intf_id,
+ phys_addr_t base_addr, phys_size_t size)
+{
+ struct io96b_mb_req usr_req;
+ struct io96b_mb_resp usr_resp;
+ int n, ret = 0;
+ bool bist_start, bist_success;
+ u32 mem_exp, mem_init_status_intf, start;
+ phys_size_t chunk_size;
+
+ u32 mem_init_status_offset[MAX_MEM_INTERFACE_SUPPORTED] = {
+ IOSSM_MEM_INIT_STATUS_INTF0_OFFSET,
+ IOSSM_MEM_INIT_STATUS_INTF1_OFFSET
+ };
+
+ /* Check if size is a power of 2 */
+ if (size == 0 || (size & (size - 1)) != 0) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ mem_exp = 0;
+ chunk_size = size;
+
+ while (chunk_size >>= 1)
+ mem_exp++;
+
+ /* Start memory initialization BIST on the specified address range */
+ IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[inst_id].mb_ctrl.ip_type[intf_id],
+ io96b_ctrl->io96b[inst_id].mb_ctrl.ip_id[intf_id],
+ CMD_TRIG_CONTROLLER_OP, BIST_MEM_INIT_START, 0);
+
+ /* CMD_PARAM_0 bit[5:0] = mem_exp */
+ /* CMD_PARAM_0 bit[6]: 0 - on the specified address range */
+ usr_req.cmd_param[0] = FIELD_PREP(BIST_START_ADDR_SPACE_MASK, mem_exp);
+ /* Extract address fields START_ADDR[31:0] */
+ usr_req.cmd_param[1] = FIELD_GET(BIST_START_ADDR_LOW_MASK, base_addr);
+ /* Extract address fields START_ADDR[37:32] */
+ usr_req.cmd_param[2] = FIELD_GET(BIST_START_ADDR_HIGH_MASK, base_addr);
+ /* Initialize memory to all zeros */
+ usr_req.cmd_param[3] = 0;
+
+ bist_start = false;
+ bist_success = false;
+
+ /* Send request to DDR controller */
+ debug("%s:Initializing memory: Addr=0x%llx, Size=2^%u\n", __func__,
+ base_addr, mem_exp);
+ ret = io96b_mb_req(io96b_ctrl->io96b[inst_id].io96b_csr_addr,
+ usr_req, 0, &usr_resp);
+ if (ret)
+ goto err;
+
+ bist_start = IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status)
+ & BIT(0);
+
+ if (!bist_start) {
+ printf("%s: Failed to initialize memory on IO96B_%d\n", __func__,
+ inst_id);
+ printf("%s: BIST_MEM_INIT_START Error code 0x%lx\n", __func__,
+ IOSSM_STATUS_CMD_RESPONSE_ERROR(usr_resp.cmd_resp_status));
+
+ ret = -EINVAL;
+ goto err;
+ }
+
+ /* Polling for the initiated memory initialization BIST status */
+ start = get_timer(0);
+ while (!bist_success) {
+ udelay(1);
+
+ mem_init_status_intf = readl(io96b_ctrl->io96b[inst_id].io96b_csr_addr +
+ mem_init_status_offset[intf_id]);
+
+ bist_success = FIELD_GET(INTF_BIST_STATUS_MASK, mem_init_status_intf);
+
+ if (!bist_success && (get_timer(start) > TIMEOUT)) {
+ printf("%s: Timeout initialize memory on IO96B_%d\n",
+ __func__, inst_id);
+ printf("%s: BIST_MEM_INIT_STATUS Error code 0x%lx\n",
+ __func__,
+ IOSSM_STATUS_CMD_RESPONSE_ERROR(usr_resp.cmd_resp_status));
+
+ ret = -ETIMEDOUT;
+ goto err;
+ }
+ }
+
+ debug("%s:DDR memory initializationat 0x%llx completed.\n", __func__, base_addr);
+
+err:
+ return ret;
+}
+
+int inline_ecc_bist_mem_init(struct io96b_info *io96b_ctrl)
+{
+ int i, j, ret = 0;
+
+ /* Memory initialization BIST performed on all memory interfaces */
+ for (i = 0; i < io96b_ctrl->num_instance; i++) {
+ for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) {
+ ret = bist_mem_init_by_addr(io96b_ctrl, i, j, 0,
+ io96b_ctrl->io96b[i].mb_ctrl.memory_size[j]);
+ if (ret) {
+ printf("Error: Memory init failed at Instance %d, Interface %d\n",
+ i, j);
+ goto err;
+ }
+ }
+ }
+
+err:
+ return ret;
+}
+
+int bist_mem_init_start(struct io96b_info *io96b_ctrl)
+{
+ if (io96b_ctrl->inline_ecc)
+ return inline_ecc_bist_mem_init(io96b_ctrl);
+ else
+ return out_of_band_bist_mem_init_start(io96b_ctrl);
+}
diff --git a/drivers/ddr/altera/iossm_mailbox.h b/drivers/ddr/altera/iossm_mailbox.h
index 6f79478..02d1db2 100644
--- a/drivers/ddr/altera/iossm_mailbox.h
+++ b/drivers/ddr/altera/iossm_mailbox.h
@@ -40,11 +40,13 @@
* @num_mem_interface: Number of memory interfaces instantiated
* @ip_type: IP type implemented on the IO96B
* @ip_instance_id: IP identifier for every IP instance implemented on the IO96B
+ * @memory_size[2]: Memory size for every IP instance implemented on the IO96B
*/
struct io96b_mb_ctrl {
u32 num_mem_interface;
u32 ip_type[2];
u32 ip_id[2];
+ phys_size_t memory_size[2];
};
/* CMD_REQ Register Definition */
@@ -53,6 +55,9 @@
#define CMD_TYPE_MASK GENMASK(23, 16)
#define CMD_OPCODE_MASK GENMASK(15, 0)
+/* Computes the Inline ECC data region size */
+#define CALC_INLINE_ECC_HW_SIZE(size) (((size) * 7) / 8)
+
/*
* IOSSM mailbox request
* @ip_type: IP type for the specified memory interface
@@ -83,13 +88,11 @@
/*
* IO96B instance specific information
*
- * @size: Memory size
* @io96b_csr_addr: IO96B instance CSR address
* @cal_status: IO96B instance calibration status
* @mb_ctrl: IOSSM mailbox required information
*/
struct io96b_instance {
- u16 size;
phys_addr_t io96b_csr_addr;
bool cal_status;
struct io96b_mb_ctrl mb_ctrl;
@@ -102,6 +105,7 @@
* @overall_cal_status: Overall calibration status for all IO96B instance(s)
* @ddr_type: DDR memory type
* @ecc_status: ECC enable status (false = disabled, true = enabled)
+ * @inline_ecc: Inline ECC or Out of Band ECC (false = Out of Band ECC, true = Inline ECC)
* @overall_size: Total DDR memory size
* @io96b[]: IO96B instance specific information
* @ckgen_lock: IO96B GEN PLL lock (false = not locked, true = locked)
@@ -115,7 +119,8 @@
bool overall_cal_status;
const char *ddr_type;
bool ecc_status;
- u16 overall_size;
+ bool inline_ecc;
+ phys_size_t overall_size;
struct io96b_instance io96b[MAX_IO96B_SUPPORTED];
bool ckgen_lock;
u8 num_port;
diff --git a/drivers/ddr/altera/sdram_agilex5.c b/drivers/ddr/altera/sdram_agilex5.c
index 801a6bb..ee66c72 100644
--- a/drivers/ddr/altera/sdram_agilex5.c
+++ b/drivers/ddr/altera/sdram_agilex5.c
@@ -291,7 +291,14 @@
goto err;
}
- hw_size = (phys_size_t)io96b_ctrl->overall_size * SZ_1G / SZ_8;
+ ret = ecc_enable_status(io96b_ctrl);
+ if (ret) {
+ printf("DDR: Failed to get ECC enabled status\n");
+
+ goto err;
+ }
+
+ hw_size = io96b_ctrl->overall_size;
/* Get bank configuration from devicetree */
ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
@@ -303,6 +310,9 @@
goto err;
}
+ if (io96b_ctrl->inline_ecc)
+ hw_size = CALC_INLINE_ECC_HW_SIZE(hw_size);
+
if (gd->ram_size > hw_size) {
printf("DDR: Warning: DRAM size from device tree (%lld MiB) exceeds\n",
gd->ram_size >> 20);
@@ -355,13 +365,6 @@
printf("%s: %lld MiB\n", io96b_ctrl->ddr_type, gd->ram_size >> 20);
- ret = ecc_enable_status(io96b_ctrl);
- if (ret) {
- printf("DDR: Failed to get ECC enabled status\n");
-
- goto err;
- }
-
/* Is HPS cold or warm reset? If yes, Skip full memory initialization if ECC
* enabled to preserve memory content
*/
diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c
index c8c9211..27fbe80 100644
--- a/drivers/ddr/altera/sdram_soc64.c
+++ b/drivers/ddr/altera/sdram_soc64.c
@@ -185,35 +185,51 @@
void sdram_size_check(struct bd_info *bd)
{
phys_size_t total_ram_check = 0;
- phys_size_t ram_check = 0;
- phys_addr_t start = 0;
- phys_size_t size, remaining_size;
int bank;
/* Sanity check ensure correct SDRAM size specified */
debug("DDR: Running SDRAM size sanity check\n");
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ phys_size_t ram_check = 0;
+ phys_addr_t start = 0;
+ phys_size_t remaining_size;
+
start = bd->bi_dram[bank].start;
remaining_size = bd->bi_dram[bank].size;
+ debug("Checking bank %d: start=0x%llx, size=0x%llx\n",
+ bank, start, remaining_size);
+
while (ram_check < bd->bi_dram[bank].size) {
- size = min((phys_addr_t)SZ_1G,
- (phys_addr_t)remaining_size);
+ phys_size_t size, test_size, detected_size;
+
+ size = min((phys_addr_t)SZ_1G, (phys_addr_t)remaining_size);
+
+ if (size < SZ_8) {
+ puts("Invalid size: Memory size required to be multiple\n");
+ puts("of 64-Bit word!\n");
+ hang();
+ }
+
+ /* Adjust size to the nearest power of two to support get_ram_size() */
+ test_size = SZ_8;
+
+ while (test_size * 2 <= size)
+ test_size *= 2;
- /*
- * Ensure the size is power of two, this is requirement
- * to run get_ram_size() / memory test
- */
- if (size != 0 && ((size & (size - 1)) == 0)) {
- ram_check += get_ram_size((void *)
- (start + ram_check), size);
- remaining_size = bd->bi_dram[bank].size -
- ram_check;
- } else {
- puts("DDR: Memory test requires SDRAM size ");
- puts("in power of two!\n");
+ debug("Testing memory at 0x%llx with size 0x%llx\n",
+ start + ram_check, test_size);
+ detected_size = get_ram_size((void *)(start + ram_check), test_size);
+
+ if (detected_size != test_size) {
+ debug("Detected size 0x%llx doesn’t match the test size 0x%llx!\n",
+ detected_size, test_size);
+ puts("Memory testing failed!\n");
hang();
}
+
+ ram_check += detected_size;
+ remaining_size = bd->bi_dram[bank].size - ram_check;
}
total_ram_check += ram_check;
@@ -249,7 +265,7 @@
DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));
- size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) &
+ size *= ((phys_size_t)2 << (hmc_ecc_readl(plat, DDRIOCTRL) &
DDR_HMC_DDRIOCTRL_IOSIZE_MSK));
return size;
diff --git a/drivers/dfu/Makefile b/drivers/dfu/Makefile
index 6e1ab1c..eb4ae5e 100644
--- a/drivers/dfu/Makefile
+++ b/drivers/dfu/Makefile
@@ -3,12 +3,12 @@
# Copyright (C) 2012 Samsung Electronics
# Lukasz Majewski <l.majewski@samsung.com>
-obj-$(CONFIG_$(XPL_)DFU) += dfu.o
-obj-$(CONFIG_$(XPL_)DFU_MMC) += dfu_mmc.o
-obj-$(CONFIG_$(XPL_)DFU_MTD) += dfu_mtd.o
-obj-$(CONFIG_$(XPL_)DFU_NAND) += dfu_nand.o
-obj-$(CONFIG_$(XPL_)DFU_RAM) += dfu_ram.o
-obj-$(CONFIG_$(XPL_)DFU_SF) += dfu_sf.o
-obj-$(CONFIG_$(XPL_)DFU_WRITE_ALT) += dfu_alt.o
-obj-$(CONFIG_$(XPL_)DFU_VIRT) += dfu_virt.o
-obj-$(CONFIG_$(XPL_)DFU_SCSI) += dfu_scsi.o
+obj-$(CONFIG_$(PHASE_)DFU) += dfu.o
+obj-$(CONFIG_$(PHASE_)DFU_MMC) += dfu_mmc.o
+obj-$(CONFIG_$(PHASE_)DFU_MTD) += dfu_mtd.o
+obj-$(CONFIG_$(PHASE_)DFU_NAND) += dfu_nand.o
+obj-$(CONFIG_$(PHASE_)DFU_RAM) += dfu_ram.o
+obj-$(CONFIG_$(PHASE_)DFU_SF) += dfu_sf.o
+obj-$(CONFIG_$(PHASE_)DFU_WRITE_ALT) += dfu_alt.o
+obj-$(CONFIG_$(PHASE_)DFU_VIRT) += dfu_virt.o
+obj-$(CONFIG_$(PHASE_)DFU_SCSI) += dfu_scsi.o
diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig
index 1eb460f..7020757 100644
--- a/drivers/fastboot/Kconfig
+++ b/drivers/fastboot/Kconfig
@@ -1,6 +1,5 @@
menu "Fastboot support"
depends on CMDLINE
- depends on !NET_LWIP
config FASTBOOT
bool
diff --git a/drivers/fastboot/fb_common.c b/drivers/fastboot/fb_common.c
index 12ffb46..68f92c4 100644
--- a/drivers/fastboot/fb_common.c
+++ b/drivers/fastboot/fb_common.c
@@ -183,11 +183,15 @@
switch (command) {
case FASTBOOT_COMMAND_BOOT:
fastboot_boot();
+#if CONFIG_IS_ENABLED(NET)
net_set_state(NETLOOP_SUCCESS);
+#endif
break;
case FASTBOOT_COMMAND_CONTINUE:
+#if CONFIG_IS_ENABLED(NET)
net_set_state(NETLOOP_SUCCESS);
+#endif
break;
case FASTBOOT_COMMAND_REBOOT:
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 8b979f6..9e7b118 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -1,5 +1,5 @@
obj-$(CONFIG_FIRMWARE) += firmware-uclass.o
-obj-$(CONFIG_$(XPL_)ARM_PSCI_FW) += psci.o
+obj-$(CONFIG_$(PHASE_)ARM_PSCI_FW) += psci.o
obj-$(CONFIG_TI_SCI_PROTOCOL) += ti_sci.o
obj-$(CONFIG_SANDBOX) += firmware-sandbox.o
obj-$(CONFIG_ZYNQMP_FIRMWARE) += firmware-zynqmp.o
diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c
index 4b1b80d..2940181 100644
--- a/drivers/firmware/firmware-zynqmp.c
+++ b/drivers/firmware/firmware-zynqmp.c
@@ -5,6 +5,8 @@
* Copyright (C) 2018-2019 Xilinx, Inc.
*/
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
#include <cpu_func.h>
#include <dm.h>
#include <dm/device_compat.h>
@@ -169,6 +171,32 @@
return pm_api_version;
};
+#if defined(CONFIG_ARCH_VERSAL2)
+int zynqmp_pm_ufs_get_txrx_cfgrdy(u32 *value)
+{
+ *value = readl(PMXC_SLCR_BASE_ADDRESS + PMXC_TX_RX_CFG_RDY);
+ return 0;
+}
+
+int zynqmp_pm_ufs_sram_csr_read(u32 *value)
+{
+ *value = readl(PMXC_SLCR_BASE_ADDRESS + PMXC_SRAM_CSR);
+ return 0;
+}
+
+int zynqmp_pm_ufs_sram_csr_write(u32 *value)
+{
+ writel(*value, PMXC_SLCR_BASE_ADDRESS + PMXC_SRAM_CSR);
+ return 0;
+}
+
+int zynqmp_pm_ufs_cal_reg(u32 *value)
+{
+ *value = readl(PMXC_EFUSE_CACHE_BASE_ADDRESS + PMXC_UFS_CAL_1_OFFSET);
+ return 0;
+}
+#endif
+
int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config, u32 value)
{
int ret;
@@ -195,6 +223,52 @@
return ret;
}
+u32 zynqmp_pm_get_bootmode_reg(void)
+{
+ int ret;
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+
+ ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_READ_REG);
+ if (ret) {
+ printf("%s: IOCTL_READ_REG is not supported failed with error code: %d\n"
+ , __func__, ret);
+ return 0;
+ }
+
+ ret = xilinx_pm_request(PM_IOCTL, CRP_BOOT_MODE_REG_NODE, IOCTL_READ_REG,
+ CRP_BOOT_MODE_REG_OFFSET, 0, ret_payload);
+ if (ret) {
+ printf("%s: node 0x%x: get_bootmode 0x%x failed\n",
+ __func__, CRP_BOOT_MODE_REG_NODE, CRP_BOOT_MODE_REG_OFFSET);
+ return 0;
+ }
+
+ return ret_payload[1];
+}
+
+u32 zynqmp_pm_get_pmc_multi_boot_reg(void)
+{
+ int ret;
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+
+ ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_READ_REG);
+ if (ret) {
+ printf("%s: IOCTL_READ_REG is not supported failed with error code: %d\n"
+ , __func__, ret);
+ return 0;
+ }
+
+ ret = xilinx_pm_request(PM_IOCTL, PM_REG_PMC_GLOBAL_NODE, IOCTL_READ_REG,
+ PMC_MULTI_BOOT_MODE_REG_OFFSET, 0, ret_payload);
+ if (ret) {
+ printf("%s: node 0x%x: get_bootmode 0x%x failed\n",
+ __func__, PM_REG_PMC_GLOBAL_NODE, PMC_MULTI_BOOT_MODE_REG_OFFSET);
+ return 0;
+ }
+
+ return ret_payload[1];
+}
+
int zynqmp_pm_feature(const u32 api_id)
{
int ret;
diff --git a/drivers/firmware/scmi/sandbox-scmi_devices.c b/drivers/firmware/scmi/sandbox-scmi_devices.c
index 96c2922..9f253b0 100644
--- a/drivers/firmware/scmi/sandbox-scmi_devices.c
+++ b/drivers/firmware/scmi/sandbox-scmi_devices.c
@@ -163,4 +163,5 @@
.priv_auto = sizeof(struct sandbox_scmi_device_priv),
.remove = sandbox_scmi_devices_remove,
.probe = sandbox_scmi_devices_probe,
+ .flags = DM_FLAG_DEFAULT_PD_CTRL_OFF,
};
diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c b/drivers/firmware/scmi/scmi_agent-uclass.c
index 8c907c3..e6e43ae 100644
--- a/drivers/firmware/scmi/scmi_agent-uclass.c
+++ b/drivers/firmware/scmi/scmi_agent-uclass.c
@@ -427,14 +427,8 @@
break;
case SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN:
if (IS_ENABLED(CONFIG_DM_REGULATOR_SCMI) &&
- scmi_protocol_is_supported(dev, protocol_id)) {
- node = ofnode_find_subnode(node, "regulators");
- if (!ofnode_valid(node)) {
- dev_err(dev, "no regulators node\n");
- return -ENXIO;
- }
+ scmi_protocol_is_supported(dev, protocol_id))
drv = DM_DRIVER_GET(scmi_voltage_domain);
- }
break;
default:
break;
diff --git a/drivers/firmware/scmi/smt.c b/drivers/firmware/scmi/smt.c
index 67d2f45..3253f42 100644
--- a/drivers/firmware/scmi/smt.c
+++ b/drivers/firmware/scmi/smt.c
@@ -20,6 +20,16 @@
#include "smt.h"
+static void scmi_smt_enable_intr(struct scmi_smt *smt, bool enable)
+{
+ struct scmi_smt_header *hdr = (void *)smt->buf;
+
+ if (enable)
+ hdr->flags |= SCMI_SHMEM_FLAG_INTR_ENABLED;
+ else
+ hdr->flags &= ~SCMI_SHMEM_FLAG_INTR_ENABLED;
+}
+
/**
* Get shared memory configuration defined by the referred DT phandle
* Return with a errno compliant value.
@@ -48,6 +58,9 @@
if (!smt->buf)
return -ENOMEM;
+ if (device_is_compatible(dev, "arm,scmi") && ofnode_has_property(dev_ofnode(dev), "mboxes"))
+ scmi_smt_enable_intr(smt, true);
+
#ifdef CONFIG_ARM
if (dcache_status())
mmu_set_region_dcache_behaviour(ALIGN_DOWN((uintptr_t)smt->buf, MMU_SECTION_SIZE),
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index 190a1e3..54d6689 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -696,20 +696,25 @@
MSG_DEVICE_SW_STATE_AUTO_OFF);
}
-static
-int ti_sci_cmd_release_exclusive_devices(const struct ti_sci_handle *handle)
+static int ti_sci_cmd_release_exclusive_devices(void)
{
struct ti_sci_exclusive_dev *dev, *tmp;
struct ti_sci_info *info;
int i, cnt;
- info = handle_to_ti_sci_info(handle);
-
- list_for_each_entry_safe(dev, tmp, &info->dev_list, list) {
- cnt = dev->count;
- debug("%s: id = %d, cnt = %d\n", __func__, dev->id, cnt);
- for (i = 0; i < cnt; i++)
- ti_sci_cmd_put_device(handle, dev->id);
+ /*
+ * Scan all ti_sci_list registrations, since with FIT images, we could
+ * have started with one device tree registration and switched over
+ * to a final version. This prevents exclusive devices identified
+ * during the first probe to be left orphan.
+ */
+ list_for_each_entry(info, &ti_sci_list, list) {
+ list_for_each_entry_safe(dev, tmp, &info->dev_list, list) {
+ cnt = dev->count;
+ debug("%s: id = %d, cnt = %d\n", __func__, dev->id, cnt);
+ for (i = 0; i < cnt; i++)
+ ti_sci_cmd_put_device(&info->handle, dev->id);
+ }
}
return 0;
diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c
index ae06f01..64fda3a 100644
--- a/drivers/fpga/altera.c
+++ b/drivers/fpga/altera.c
@@ -12,6 +12,10 @@
/*
* Altera FPGA support
*/
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \
+ IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include <asm/arch/misc.h>
+#endif
#include <errno.h>
#include <ACEX1K.h>
#include <log.h>
@@ -47,6 +51,43 @@
#endif
};
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \
+ IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)
+int fpga_is_partial_data(int devnum, size_t img_len)
+{
+ /*
+ * The FPGA data (full or partial) is checked by
+ * the SDM hardware, for Intel SDM Mailbox based
+ * devices. Hence always return full bitstream.
+ *
+ * For Cyclone V and Arria 10 family, the bitstream
+ * type parameter is not handled by the driver.
+ */
+ return 0;
+}
+
+int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
+ bitstream_type bstype)
+{
+ int ret_val;
+ int flags = 0;
+
+ ret_val = fpga_load(devnum, (void *)fpgadata, size, bstype, flags);
+
+ /*
+ * Enable the HPS to FPGA bridges when FPGA load is completed
+ * successfully. This is to ensure the FPGA is accessible
+ * by the HPS.
+ */
+ if (!ret_val) {
+ printf("Enable FPGA bridges\n");
+ do_bridge_reset(1, ~0);
+ }
+
+ return ret_val;
+}
+#endif
+
static int altera_validate(Altera_desc *desc, const char *fn)
{
if (!desc) {
diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c
index 1957e8d..d691f13 100644
--- a/drivers/fpga/versalpl.c
+++ b/drivers/fpga/versalpl.c
@@ -41,8 +41,15 @@
buf_lo = lower_32_bits(bin_buf);
buf_hi = upper_32_bits(bin_buf);
- ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
- buf_hi, 0, ret_payload);
+
+ if (desc->family == xilinx_versal2) {
+ ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_hi,
+ buf_lo, 0, ret_payload);
+ } else {
+ ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
+ buf_hi, 0, ret_payload);
+ }
+
if (ret)
printf("PL FPGA LOAD failed with err: 0x%08x\n", ret);
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index d426d3a..d64c14d 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -10,7 +10,7 @@
endif
obj-$(CONFIG_$(PHASE_)DM_GPIO) += gpio-uclass.o
-obj-$(CONFIG_$(XPL_)DM_PCA953X) += pca953x_gpio.o
+obj-$(CONFIG_$(PHASE_)DM_PCA953X) += pca953x_gpio.o
obj-$(CONFIG_ADI_GPIO) += gpio-adi-adsp.o
obj-$(CONFIG_ASPEED_GPIO) += gpio-aspeed.o
@@ -59,12 +59,12 @@
obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o
obj-$(CONFIG_HSDK_CREG_GPIO) += hsdk-creg-gpio.o
obj-$(CONFIG_IMX_RGPIO2P) += imx_rgpio2p.o
-obj-$(CONFIG_$(XPL_)PALMAS_GPIO) += palmas_gpio.o
+obj-$(CONFIG_$(PHASE_)PALMAS_GPIO) += palmas_gpio.o
obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o
obj-$(CONFIG_OCTEON_GPIO) += octeon_gpio.o
obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o
obj-$(CONFIG_MSM_GPIO) += msm_gpio.o
-obj-$(CONFIG_$(XPL_)PCF8575_GPIO) += pcf8575_gpio.o
+obj-$(CONFIG_$(PHASE_)PCF8575_GPIO) += pcf8575_gpio.o
obj-$(CONFIG_$(PHASE_)QCOM_PMIC_GPIO) += qcom_pmic_gpio.o
obj-$(CONFIG_MT7620_GPIO) += mt7620_gpio.o
obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o
@@ -73,11 +73,11 @@
obj-$(CONFIG_SIFIVE_GPIO) += sifive-gpio.o
obj-$(CONFIG_NOMADIK_GPIO) += nmk_gpio.o
obj-$(CONFIG_MAX7320_GPIO) += max7320_gpio.o
-obj-$(CONFIG_$(XPL_)MAX77663_GPIO) += max77663_gpio.o
+obj-$(CONFIG_$(PHASE_)MAX77663_GPIO) += max77663_gpio.o
obj-$(CONFIG_SL28CPLD_GPIO) += sl28cpld-gpio.o
obj-$(CONFIG_ADP5588_GPIO) += adp5588_gpio.o
obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN) += zynqmp_gpio_modepin.o
obj-$(CONFIG_SLG7XL45106_I2C_GPO) += gpio_slg7xl45106.o
obj-$(CONFIG_FTGPIO010) += ftgpio010.o
-obj-$(CONFIG_$(SPL_)ADP5585_GPIO) += adp5585_gpio.o
+obj-$(CONFIG_$(PHASE_)ADP5585_GPIO) += adp5585_gpio.o
obj-$(CONFIG_RZG2L_GPIO) += rzg2l-gpio.o
diff --git a/drivers/gpio/axp_gpio.c b/drivers/gpio/axp_gpio.c
index 6e632c8..181c53b 100644
--- a/drivers/gpio/axp_gpio.c
+++ b/drivers/gpio/axp_gpio.c
@@ -15,6 +15,9 @@
#include <errno.h>
#include <sunxi_gpio.h>
+#define AXP_GPIO_PREFIX "AXP0-"
+#define AXP_GPIO_COUNT 4
+
static int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val);
static u8 axp_get_gpio_ctrl_reg(unsigned pin)
@@ -46,28 +49,14 @@
static int axp_gpio_direction_output(struct udevice *dev, unsigned pin,
int val)
{
- __maybe_unused int ret;
u8 reg;
- switch (pin) {
-#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC
- /* Only available on later PMICs */
- case SUNXI_GPIO_AXP0_VBUS_ENABLE:
- ret = pmic_bus_clrbits(AXP_MISC_CTRL,
- AXP_MISC_CTRL_N_VBUSEN_FUNC);
- if (ret)
- return ret;
-
- return axp_gpio_set_value(dev, pin, val);
-#endif
- default:
- reg = axp_get_gpio_ctrl_reg(pin);
- if (reg == 0)
- return -EINVAL;
+ reg = axp_get_gpio_ctrl_reg(pin);
+ if (reg == 0)
+ return -EINVAL;
- return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
- AXP_GPIO_CTRL_OUTPUT_LOW);
- }
+ return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
+ AXP_GPIO_CTRL_OUTPUT_LOW);
}
static int axp_gpio_get_value(struct udevice *dev, unsigned pin)
@@ -75,25 +64,16 @@
u8 reg, val, mask;
int ret;
- switch (pin) {
-#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC
- /* Only available on later PMICs */
- case SUNXI_GPIO_AXP0_VBUS_ENABLE:
- ret = pmic_bus_read(AXP_VBUS_IPSOUT, &val);
- mask = AXP_VBUS_IPSOUT_DRIVEBUS;
- break;
-#endif
- default:
- reg = axp_get_gpio_ctrl_reg(pin);
- if (reg == 0)
- return -EINVAL;
+ reg = axp_get_gpio_ctrl_reg(pin);
+ if (reg == 0)
+ return -EINVAL;
- ret = pmic_bus_read(AXP_GPIO_STATE, &val);
- mask = 1 << (pin + AXP_GPIO_STATE_OFFSET);
- }
+ ret = pmic_bus_read(AXP_GPIO_STATE, &val);
if (ret)
return ret;
+ mask = 1 << (pin + AXP_GPIO_STATE_OFFSET);
+
return (val & mask) ? 1 : 0;
}
@@ -101,25 +81,12 @@
{
u8 reg;
- switch (pin) {
-#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC
- /* Only available on later PMICs */
- case SUNXI_GPIO_AXP0_VBUS_ENABLE:
- if (val)
- return pmic_bus_setbits(AXP_VBUS_IPSOUT,
- AXP_VBUS_IPSOUT_DRIVEBUS);
- else
- return pmic_bus_clrbits(AXP_VBUS_IPSOUT,
- AXP_VBUS_IPSOUT_DRIVEBUS);
-#endif
- default:
- reg = axp_get_gpio_ctrl_reg(pin);
- if (reg == 0)
- return -EINVAL;
+ reg = axp_get_gpio_ctrl_reg(pin);
+ if (reg == 0)
+ return -EINVAL;
- return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
- AXP_GPIO_CTRL_OUTPUT_LOW);
- }
+ return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
+ AXP_GPIO_CTRL_OUTPUT_LOW);
}
static const struct dm_gpio_ops gpio_axp_ops = {
@@ -134,8 +101,8 @@
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
/* Tell the uclass how many GPIOs we have */
- uc_priv->bank_name = strdup(SUNXI_GPIO_AXP0_PREFIX);
- uc_priv->gpio_count = SUNXI_GPIO_AXP0_GPIO_COUNT;
+ uc_priv->bank_name = AXP_GPIO_PREFIX;
+ uc_priv->gpio_count = AXP_GPIO_COUNT;
return 0;
}
diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c
index cea073b..6783fc7 100644
--- a/drivers/gpio/msm_gpio.c
+++ b/drivers/gpio/msm_gpio.c
@@ -151,6 +151,9 @@
static int msm_gpio_set_flags(struct udevice *dev, unsigned int gpio, ulong flags)
{
+ if (msm_pinctrl_is_reserved(dev_get_parent(dev), gpio))
+ return -EPERM;
+
if (flags & GPIOD_IS_OUT_ACTIVE) {
return msm_gpio_direction_output(dev, gpio, 1);
} else if (flags & GPIOD_IS_OUT) {
@@ -172,12 +175,19 @@
const struct msm_special_pin_data *data;
if (!priv->pin_data->special_pins_data)
- return 0;
+ return -EINVAL;
data = &priv->pin_data->special_pins_data[offset];
- if (!data->io_reg || data->in_bit >= 31)
- return 0;
+ if (!data->io_reg)
+ return -EINVAL;
+
+ if (data->in_bit >= 31) {
+ if (data->out_bit >= 31)
+ return -EINVAL;
+
+ return !!(readl(priv->base + data->io_reg) >> data->out_bit);
+ }
return !!(readl(priv->base + data->io_reg) >> data->in_bit);
}
@@ -186,19 +196,54 @@
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
+ if (msm_pinctrl_is_reserved(dev_get_parent(dev), gpio))
+ return -EPERM;
+
if (qcom_is_special_pin(priv->pin_data, gpio))
return msm_gpio_get_value_special(priv, gpio);
return !!(readl(priv->base + GPIO_IN_OUT_REG(dev, gpio)) >> GPIO_IN);
}
+static int msm_gpio_get_function_special(struct msm_gpio_bank *priv,
+ unsigned int gpio)
+{
+ unsigned int offset = gpio - priv->pin_data->special_pins_start;
+ const struct msm_special_pin_data *data;
+
+ if (!priv->pin_data->special_pins_data)
+ return GPIOF_UNKNOWN;
+
+ data = &priv->pin_data->special_pins_data[offset];
+
+ /* No I/O fields, cannot control/read the I/O value */
+ if (!data->io_reg || (data->out_bit >= 31 && data->in_bit >= 31))
+ return GPIOF_FUNC;
+
+ /* No Output-Enable register, cannot control I/O direction */
+ if (!data->ctl_reg || data->oe_bit >= 31) {
+ if (data->out_bit >= 31)
+ return GPIOF_INPUT;
+ else
+ return GPIOF_OUTPUT;
+ }
+
+ if (readl(priv->base + data->ctl_reg) & BIT(data->oe_bit))
+ return GPIOF_OUTPUT;
+
+ return GPIOF_INPUT;
+}
+
static int msm_gpio_get_function(struct udevice *dev, unsigned int gpio)
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
+ if (msm_pinctrl_is_reserved(dev_get_parent(dev), gpio))
+ return GPIOF_UNKNOWN;
+
/* Always NOP for special pins, assume they're in the correct state */
if (qcom_is_special_pin(priv->pin_data, gpio))
- return 0;
+ return msm_gpio_get_function_special(priv, gpio);
if (readl(priv->base + GPIO_CONFIG_REG(dev, gpio)) & GPIO_OE_ENABLE)
return GPIOF_OUTPUT;
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index 2ca4960..094c45a 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -244,17 +244,7 @@
int sunxi_name_to_gpio(const char *name)
{
unsigned int gpio;
- int ret;
-#if !defined CONFIG_XPL_BUILD && defined CONFIG_AXP_GPIO
- char lookup[8];
-
- if (strcasecmp(name, "AXP0-VBUS-ENABLE") == 0) {
- sprintf(lookup, SUNXI_GPIO_AXP0_PREFIX "%d",
- SUNXI_GPIO_AXP0_VBUS_ENABLE);
- name = lookup;
- }
-#endif
- ret = gpio_lookup_name(name, NULL, NULL, &gpio);
+ int ret = gpio_lookup_name(name, NULL, NULL, &gpio);
return ret ? ret : gpio;
}
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 46e7638..146bc62 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -510,6 +510,15 @@
help
Add support for the OMAP2+ I2C driver.
+config SYS_I2C_OMAP24XX_REPEATED_START
+ bool "Enable I2C repeated start"
+ depends on SYS_I2C_OMAP24XX
+ default y if ARCH_K3
+ help
+ Enable support for repeated start. Updates driver defaults to not
+ send a Stop condition and issue Repeated Start (Sr) for subsequent
+ i2c msgs.
+
config SYS_I2C_RCAR_I2C
bool "Renesas R-Car I2C driver"
depends on (RCAR_GEN2 || RCAR_64) && DM_I2C
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 2713289..42326db 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -2,15 +2,15 @@
#
# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-obj-$(CONFIG_$(XPL_)DM_I2C) += i2c-uclass.o
-ifdef CONFIG_$(XPL_)ACPIGEN
-obj-$(CONFIG_$(XPL_)DM_I2C) += acpi_i2c.o
+obj-$(CONFIG_$(PHASE_)DM_I2C) += i2c-uclass.o
+ifdef CONFIG_$(PHASE_)ACPIGEN
+obj-$(CONFIG_$(PHASE_)DM_I2C) += acpi_i2c.o
endif
-obj-$(CONFIG_$(XPL_)DM_I2C_GPIO) += i2c-gpio.o
-obj-$(CONFIG_$(XPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o
-obj-$(CONFIG_$(XPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o
+obj-$(CONFIG_$(PHASE_)DM_I2C_GPIO) += i2c-gpio.o
+obj-$(CONFIG_$(PHASE_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o
+obj-$(CONFIG_$(PHASE_)I2C_CROS_EC_LDO) += cros_ec_ldo.o
-obj-$(CONFIG_$(XPL_)SYS_I2C_LEGACY) += i2c_core.o
+obj-$(CONFIG_$(PHASE_)SYS_I2C_LEGACY) += i2c_core.o
obj-$(CONFIG_SYS_I2C_ADI) += adi_i2c.o
obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o
obj-$(CONFIG_SYS_I2C_AST2600) += ast2600_i2c.o
@@ -58,4 +58,4 @@
obj-$(CONFIG_SYS_I2C_XILINX_XIIC) += xilinx_xiic.o
obj-$(CONFIG_TEGRA186_BPMP_I2C) += tegra186_bpmp_i2c.o
-obj-$(CONFIG_$(XPL_)I2C_MUX) += muxes/
+obj-$(CONFIG_$(PHASE_)I2C_MUX) += muxes/
diff --git a/drivers/i2c/mtk_i2c.c b/drivers/i2c/mtk_i2c.c
index 3450177..55381db 100644
--- a/drivers/i2c/mtk_i2c.c
+++ b/drivers/i2c/mtk_i2c.c
@@ -143,7 +143,6 @@
[REG_RSV_DEBUG] = 0x44,
[REG_HS] = 0x48,
[REG_SOFTRESET] = 0x50,
- [REG_SOFTRESET] = 0x50,
[REG_DCM_EN] = 0x54,
[REG_DEBUGSTAT] = 0x64,
[REG_DEBUGCTRL] = 0x68,
@@ -879,7 +878,7 @@
}, {
.compatible = "mediatek,mt8518-i2c",
.data = (ulong)&mt8518_soc_data,
- }
+ }, {}
};
U_BOOT_DRIVER(mtk_i2c) = {
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index ebe472e..a6361d3 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -535,12 +535,16 @@
return res;
}
+#if !CONFIG_IS_ENABLED(DM_I2C)
+/*
+ * The legacy I2C functions. These need to get removed once
+ * all users of this driver are converted to DM.
+ */
+
/*
* i2c_read: Function now uses a single I2C read transaction with bulk transfer
* of the requested number of bytes (note that the 'i2c md' command
- * limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is
- * defined in the board config header, this transaction shall be with
- * Repeated Start (Sr) between the address and data phases; otherwise
+ * limits this to 16 bytes anyway).
* Stop-Start (P-S) shall be used (some I2C chips do require a P-S).
* The address (reg offset) may be 0, 1 or 2 bytes long.
* Function now reads correctly from chips that return more than one
@@ -608,16 +612,10 @@
if (alen) {
/* Must write reg offset first */
-#ifdef CONFIG_I2C_REPEATED_START
- /* No stop bit, use Repeated Start (Sr) */
- omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
- I2C_CON_STT | I2C_CON_TRX, OMAP_I2C_CON_REG);
-#else
/* Stop - Start (P-S) */
omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
I2C_CON_STT | I2C_CON_STP | I2C_CON_TRX,
OMAP_I2C_CON_REG);
-#endif
/* Send register offset */
while (1) {
status = wait_for_event(i2c_base, ip_rev, waitdelay);
@@ -836,11 +834,6 @@
return i2c_error;
}
-#if !CONFIG_IS_ENABLED(DM_I2C)
-/*
- * The legacy I2C functions. These need to get removed once
- * all users of this driver are converted to DM.
- */
static void __iomem *omap24_get_base(struct i2c_adapter *adap)
{
switch (adap->hwadapnr) {
@@ -971,28 +964,140 @@
#else /* CONFIG_DM_I2C */
+static int __omap24_i2c_xfer_msg(void __iomem *i2c_base, int ip_rev, int waitdelay,
+ uchar chip, uchar *buffer, int len, u16 i2c_con_reg)
+{
+ int i;
+ u16 status;
+ int i2c_error = 0;
+ int timeout = I2C_TIMEOUT;
+
+ if (len < 0) {
+ printf("%s: data len < 0\n", __func__);
+ return -EINVAL;
+ }
+
+ if (!buffer) {
+ printf("%s: NULL pointer passed\n", __func__);
+ return -EINVAL;
+ }
+
+ if (!(i2c_con_reg & I2C_CON_EN)) {
+ printf("%s: I2C_CON_EN not set\n", __func__);
+ return -EINVAL;
+ }
+
+ /* Set slave address */
+ omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG);
+ /* Read/Write len bytes data */
+ omap_i2c_write_reg(i2c_base, ip_rev, len, OMAP_I2C_CNT_REG);
+ /* Configure the I2C_CON register */
+ omap_i2c_write_reg(i2c_base, ip_rev, i2c_con_reg, OMAP_I2C_CON_REG);
+
+ /* read/write data bytewise */
+ for (i = 0; i < len; i++) {
+ status = wait_for_event(i2c_base, ip_rev, waitdelay);
+ /* Ignore I2C_STAT_RRDY in transmitter mode */
+ if (i2c_con_reg & I2C_CON_TRX)
+ status &= ~I2C_STAT_RRDY;
+ else
+ status &= ~I2C_STAT_XRDY;
+
+ /* Try to identify bus that is not padconf'd for I2C */
+ if (status == I2C_STAT_XRDY) {
+ i2c_error = -EREMOTEIO;
+ printf("%s: pads on bus probably not configured (status=0x%x)\n",
+ __func__, status);
+ goto xfer_exit;
+ }
+ if (status == 0 || (status & I2C_STAT_NACK)) {
+ i2c_error = -EREMOTEIO;
+ printf("%s: error waiting for ACK (status=0x%x)\n",
+ __func__, status);
+ goto xfer_exit;
+ }
+ if (status & I2C_STAT_XRDY) {
+ /* Transmit data */
+ omap_i2c_write_reg(i2c_base, ip_rev,
+ buffer[i], OMAP_I2C_DATA_REG);
+ omap_i2c_write_reg(i2c_base, ip_rev,
+ I2C_STAT_XRDY, OMAP_I2C_STAT_REG);
+ }
+ if (status & I2C_STAT_RRDY) {
+ /* Receive data */
+ *buffer++ = omap_i2c_read_reg(i2c_base, ip_rev,
+ OMAP_I2C_DATA_REG);
+ omap_i2c_write_reg(i2c_base, ip_rev,
+ I2C_STAT_RRDY, OMAP_I2C_STAT_REG);
+ }
+ }
+
+ /*
+ * poll ARDY bit for making sure that last byte really has been
+ * transferred on the bus.
+ */
+ do {
+ status = wait_for_event(i2c_base, ip_rev, waitdelay);
+ } while (!(status & I2C_STAT_ARDY) && timeout--);
+ if (timeout <= 0) {
+ printf("%s: timed out on last byte!\n", __func__);
+ i2c_error = -EREMOTEIO;
+ goto xfer_exit;
+ } else {
+ omap_i2c_write_reg(i2c_base, ip_rev, I2C_STAT_ARDY, OMAP_I2C_STAT_REG);
+ }
+
+ /* If Stop bit set, flush FIFO. */
+ if (i2c_con_reg & I2C_CON_STP)
+ goto xfer_exit;
+
+ return 0;
+
+xfer_exit:
+ flush_fifo(i2c_base, ip_rev);
+ omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
+ return i2c_error;
+}
+
static int omap_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
{
struct omap_i2c *priv = dev_get_priv(bus);
int ret;
+ u16 i2c_con_reg = 0;
- debug("i2c_xfer: %d messages\n", nmsgs);
- for (; nmsgs > 0; nmsgs--, msg++) {
- debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
- if (msg->flags & I2C_M_RD) {
- ret = __omap24_i2c_read(priv->regs, priv->ip_rev,
- priv->waitdelay,
- msg->addr, 0, 0, msg->buf,
- msg->len);
- } else {
- ret = __omap24_i2c_write(priv->regs, priv->ip_rev,
- priv->waitdelay,
- msg->addr, 0, 0, msg->buf,
- msg->len);
- }
+ debug("%s: %d messages\n", __func__, nmsgs);
+ for (int i = 0; i < nmsgs; i++, msg++) {
+ /*
+ * If previous msg sent a Stop or if this is the first msg
+ * Wait until bus not busy
+ */
+ if ((i2c_con_reg & I2C_CON_STP) || (i == 0))
+ if (wait_for_bb(priv->regs, priv->ip_rev, priv->waitdelay))
+ return -EREMOTEIO;
+
+ /* Set Controller mode with Start bit */
+ i2c_con_reg = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT;
+ /* Set Transmitter/Receiver mode if it is a write/read msg */
+ if (msg->flags & I2C_M_RD)
+ i2c_con_reg &= ~I2C_CON_TRX;
+ else
+ i2c_con_reg |= I2C_CON_TRX;
+ /* Send Stop condition (P) by default */
+ if (!IS_ENABLED(CONFIG_SYS_I2C_OMAP24XX_REPEATED_START))
+ i2c_con_reg |= I2C_CON_STP;
+ /* Send Stop if explicitly requested or if this is the last msg */
+ if ((msg->flags & I2C_M_STOP) || (i == nmsgs - 1))
+ i2c_con_reg |= I2C_CON_STP;
+
+ debug("%s: chip=0x%x, len=0x%x, i2c_con_reg=0x%x\n",
+ __func__, msg->addr, msg->len, i2c_con_reg);
+
+ ret = __omap24_i2c_xfer_msg(priv->regs, priv->ip_rev, priv->waitdelay,
+ msg->addr, msg->buf, msg->len,
+ i2c_con_reg);
if (ret) {
- debug("i2c_write: error sending\n");
- return -EREMOTEIO;
+ printf("%s: errored out at msg %d: %d\n", __func__, i, ret);
+ return ret;
}
}
diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig
index c2b365a..c09f0ae 100644
--- a/drivers/input/Kconfig
+++ b/drivers/input/Kconfig
@@ -55,6 +55,12 @@
dt node to define button-event mapping.
For example, an arrows and enter may be implemented to navigate boot menu.
+config CPCAP_POWER_BUTTON
+ bool "Enable power button of CPCAP PMIC support"
+ depends on DM_KEYBOARD && DM_PMIC_CPCAP
+ help
+ Enable support for a dedicated power button of the CPCAP PMIC.
+
config CROS_EC_KEYB
bool "Enable Chrome OS EC keyboard support"
depends on INPUT
diff --git a/drivers/input/Makefile b/drivers/input/Makefile
index 8d4107b..1303fcd 100644
--- a/drivers/input/Makefile
+++ b/drivers/input/Makefile
@@ -7,6 +7,7 @@
obj-$(CONFIG_$(PHASE_)OF_CONTROL) += key_matrix.o
obj-$(CONFIG_$(PHASE_)DM_KEYBOARD) += input.o keyboard-uclass.o
obj-$(CONFIG_BUTTON_KEYBOARD) += button_kbd.o
+obj-$(CONFIG_CPCAP_POWER_BUTTON) += cpcap_pwrbutton.o
ifndef CONFIG_XPL_BUILD
diff --git a/drivers/input/cpcap_pwrbutton.c b/drivers/input/cpcap_pwrbutton.c
new file mode 100644
index 0000000..c8ad39d
--- /dev/null
+++ b/drivers/input/cpcap_pwrbutton.c
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright(C) 2025 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <stdlib.h>
+#include <dm.h>
+#include <input.h>
+#include <keyboard.h>
+#include <power/pmic.h>
+#include <power/cpcap.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/input.h>
+
+static const unsigned int cpcpap_to_reg[] = {
+ CPCAP_REG_INT1,
+ CPCAP_REG_INT2,
+ CPCAP_REG_INT3,
+ CPCAP_REG_INT4,
+};
+
+/**
+ * struct cpcap_pwrbutton_priv
+ *
+ * @bank: id of interrupt bank co-responding to an IRQ register
+ * @id: id of interrupt pin co-responding to the bit in IRQ register
+ * @keycode: linux key code
+ * @old_state: holder of last button state
+ * @skip: holder of keycode skip state. This is required since both pressing
+ * and releasing generate same event and cause key send duplication.
+ */
+struct cpcap_pwrbutton_priv {
+ u32 bank;
+ u32 id;
+
+ u32 keycode;
+
+ bool old_state;
+ bool skip;
+};
+
+static int cpcap_pwrbutton_read_keys(struct input_config *input)
+{
+ struct udevice *dev = input->dev;
+ struct cpcap_pwrbutton_priv *priv = dev_get_priv(dev);
+ u32 value, state_changed;
+ bool state;
+
+ value = pmic_reg_read(dev->parent, cpcpap_to_reg[priv->bank]) &
+ BIT(priv->id);
+
+ /* Interrupt bit is cleared by writing it to interrupt reg */
+ pmic_reg_write(dev->parent, cpcpap_to_reg[priv->bank], BIT(priv->id));
+
+ state = value >> priv->id;
+ state_changed = state != priv->old_state;
+
+ if (state_changed && !priv->skip) {
+ priv->old_state = state;
+ input_add_keycode(input, priv->keycode, state);
+ }
+
+ if (state)
+ priv->skip = !priv->skip;
+
+ return 0;
+}
+
+static int cpcap_pwrbutton_of_to_plat(struct udevice *dev)
+{
+ struct cpcap_pwrbutton_priv *priv = dev_get_priv(dev);
+ ofnode irq_parent;
+ u32 irq_desc;
+ int ret;
+
+ /* Check interrupt parent, driver supports only CPCAP as parent */
+ irq_parent = ofnode_parse_phandle(dev_ofnode(dev), "interrupt-parent", 0);
+ if (!ofnode_device_is_compatible(irq_parent, "motorola,cpcap"))
+ return -EINVAL;
+
+ ret = dev_read_u32(dev, "interrupts", &irq_desc);
+ if (ret)
+ return ret;
+
+ /* IRQ registers are 16 bit wide */
+ priv->bank = irq_desc / 16;
+ priv->id = irq_desc % 16;
+
+ ret = dev_read_u32(dev, "linux,code", &priv->keycode);
+ if (ret)
+ return ret;
+
+ priv->old_state = false;
+ priv->skip = false;
+ return 0;
+}
+
+static int cpcap_pwrbutton_probe(struct udevice *dev)
+{
+ struct keyboard_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct stdio_dev *sdev = &uc_priv->sdev;
+ struct input_config *input = &uc_priv->input;
+ int ret;
+
+ input_init(input, false);
+ input_add_tables(input, false);
+
+ /* Register the device */
+ input->dev = dev;
+ input->read_keys = cpcap_pwrbutton_read_keys;
+ strcpy(sdev->name, "cpcap-pwrbutton");
+ ret = input_stdio_register(sdev);
+ if (ret) {
+ log_debug("%s: input_stdio_register() failed\n", __func__);
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id cpcap_pwrbutton_ids[] = {
+ { .compatible = "motorola,cpcap-pwrbutton" },
+ { }
+};
+
+U_BOOT_DRIVER(cpcap_pwrbutton) = {
+ .name = "cpcap_pwrbutton",
+ .id = UCLASS_KEYBOARD,
+ .of_match = cpcap_pwrbutton_ids,
+ .of_to_plat = cpcap_pwrbutton_of_to_plat,
+ .probe = cpcap_pwrbutton_probe,
+ .priv_auto = sizeof(struct cpcap_pwrbutton_priv),
+};
diff --git a/drivers/led/Makefile b/drivers/led/Makefile
index aa64a38..996753b 100644
--- a/drivers/led/Makefile
+++ b/drivers/led/Makefile
@@ -10,6 +10,6 @@
obj-$(CONFIG_LED_BCM6753) += led_bcm6753.o
obj-$(CONFIG_LED_BCM6858) += led_bcm6858.o
obj-$(CONFIG_LED_PWM) += led_pwm.o
-obj-$(CONFIG_$(XPL_)LED_GPIO) += led_gpio.o
+obj-$(CONFIG_$(PHASE_)LED_GPIO) += led_gpio.o
obj-$(CONFIG_LED_CORTINA) += led_cortina.o
obj-$(CONFIG_LED_LP5562) += led_lp5562.o
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index 574add6..e8c745f 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -3,7 +3,7 @@
# Copyright (c) 2016, NVIDIA CORPORATION.
#
-obj-$(CONFIG_$(XPL_)DM_MAILBOX) += mailbox-uclass.o
+obj-$(CONFIG_$(PHASE_)DM_MAILBOX) += mailbox-uclass.o
obj-$(CONFIG_APPLE_MBOX) += apple-mbox.o
obj-$(CONFIG_IMX_MU_MBOX) += imx-mailbox.o
obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 834e028..0911d2f 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -576,6 +576,7 @@
bool
default y
depends on QFW && SMBIOS && !SANDBOX && !SYSINFO_SMBIOS
+ select BLOBLIST
help
Hidden option to read SMBIOS tables from QEMU.
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 0b81ba2..248068d 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -18,7 +18,7 @@
obj-$(CONFIG_SANDBOX) += swap_case.o
endif
-ifdef CONFIG_$(XPL_)DM_I2C
+ifdef CONFIG_$(PHASE_)DM_I2C
ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
obj-$(CONFIG_USB_HUB_USB251XB) += usb251xb.o
@@ -37,14 +37,14 @@
obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
obj-$(CONFIG_FSL_IIM) += fsl_iim.o
obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o
-obj-$(CONFIG_$(XPL_)FS_LOADER) += fs_loader.o
+obj-$(CONFIG_$(PHASE_)FS_LOADER) += fs_loader.o
obj-$(CONFIG_GATEWORKS_SC) += gsc.o
obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o
obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o
obj-$(CONFIG_GDSYS_SOC) += gdsys_soc.o
obj-$(CONFIG_IRQ) += irq-uclass.o
obj-$(CONFIG_SANDBOX) += irq_sandbox.o irq_sandbox_test.o
-obj-$(CONFIG_$(XPL_)I2C_EEPROM) += i2c_eeprom.o
+obj-$(CONFIG_$(PHASE_)I2C_EEPROM) += i2c_eeprom.o
obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o
obj-$(CONFIG_IMX8) += imx8/
obj-$(CONFIG_IMX_ELE) += imx_ele/
@@ -53,14 +53,14 @@
obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o
obj-$(CONFIG_$(PHASE_)LS2_SFP) += ls2_sfp.o
-obj-$(CONFIG_$(XPL_)MXC_OCOTP) += mxc_ocotp.o
+obj-$(CONFIG_$(PHASE_)MXC_OCOTP) += mxc_ocotp.o
obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
obj-$(CONFIG_NPCM_OTP) += npcm_otp.o
obj-$(CONFIG_NPCM_HOST) += npcm_host_intf.o
obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o
obj-$(CONFIG_P2SB) += p2sb-uclass.o
obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
-obj-$(CONFIG_$(XPL_)PWRSEQ) += pwrseq-uclass.o
+obj-$(CONFIG_$(PHASE_)PWRSEQ) += pwrseq-uclass.o
ifdef CONFIG_QFW
obj-y += qfw.o
obj-$(CONFIG_QFW_ACPI) += qfw_acpi.o
diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c
index 1cad51d..3ac690a 100644
--- a/drivers/misc/cros_ec_sandbox.c
+++ b/drivers/misc/cros_ec_sandbox.c
@@ -15,7 +15,6 @@
#include <log.h>
#include <os.h>
#include <u-boot/sha256.h>
-#include <spi.h>
#include <time.h>
#include <asm/malloc.h>
#include <asm/state.h>
diff --git a/drivers/misc/rockchip-otp.c b/drivers/misc/rockchip-otp.c
index 2123c31..4682042 100644
--- a/drivers/misc/rockchip-otp.c
+++ b/drivers/misc/rockchip-otp.c
@@ -361,6 +361,13 @@
.block_size = 2,
};
+static const struct rockchip_otp_data rk3576_data = {
+ .read = rockchip_rk3588_otp_read,
+ .offset = 0x700,
+ .size = 0x100,
+ .block_size = 4,
+};
+
static const struct rockchip_otp_data rk3588_data = {
.read = rockchip_rk3588_otp_read,
.offset = 0xC00,
@@ -384,10 +391,18 @@
.data = (ulong)&px30_data,
},
{
+ .compatible = "rockchip,rk3528-otp",
+ .data = (ulong)&rk3568_data,
+ },
+ {
.compatible = "rockchip,rk3568-otp",
.data = (ulong)&rk3568_data,
},
{
+ .compatible = "rockchip,rk3576-otp",
+ .data = (ulong)&rk3576_data,
+ },
+ {
.compatible = "rockchip,rk3588-otp",
.data = (ulong)&rk3588_data,
},
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 6740591..38867f3 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -528,6 +528,7 @@
config MMC_SDHCI_ADMA_FORCE_32BIT
bool "Force 32 bit mode for ADMA on 64 bit platforms"
+ depends on MMC_SDHCI_ADMA || SPL_MMC_SDHCI_ADMA
help
This forces SDHCI ADMA to be built for 32 bit descriptors, even
on a 64 bit platform where they would otherwise be assumed to
@@ -537,6 +538,7 @@
config MMC_SDHCI_ADMA_64BIT
bool "Use SHDCI ADMA with 64 bit descriptors"
+ depends on MMC_SDHCI_ADMA || SPL_MMC_SDHCI_ADMA
depends on !MMC_SDHCI_ADMA_FORCE_32BIT
default y if DMA_ADDR_T_64BIT
help
@@ -869,7 +871,7 @@
config MMC_MTK
bool "MediaTek SD/MMC Card Interface support"
- depends on ARCH_MEDIATEK || ARCH_MTMIPS
+ depends on ARCH_MEDIATEK || ARCH_MTMIPS || ARCH_AIROHA
depends on OF_CONTROL
help
This selects the MediaTek(R) Secure digital and Multimedia card Interface.
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 94ed28e..360706f 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -4,17 +4,17 @@
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y += mmc.o
-obj-$(CONFIG_$(XPL_)DM_MMC) += mmc-uclass.o
+obj-$(CONFIG_$(PHASE_)DM_MMC) += mmc-uclass.o
ifdef CONFIG_$(PHASE_)DM_MMC
obj-$(CONFIG_$(PHASE_)BOOTSTD) += mmc_bootdev.o
endif
obj-$(CONFIG_$(PHASE_)MMC_WRITE) += mmc_write.o
-obj-$(CONFIG_$(XPL_)MMC_PWRSEQ) += mmc-pwrseq.o
+obj-$(CONFIG_$(PHASE_)MMC_PWRSEQ) += mmc-pwrseq.o
obj-$(CONFIG_MMC_SDHCI_ADMA_HELPERS) += sdhci-adma.o
-ifndef CONFIG_$(XPL_)BLK
+ifndef CONFIG_$(PHASE_)BLK
obj-y += mmc_legacy.o
endif
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index b4c60a4..0df3568 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -125,12 +125,15 @@
[MMC_LEGACY] = {"ti,otap-del-sel-legacy",
"ti,itap-del-sel-legacy",
0},
- [MMC_HS] = {"ti,otap-del-sel-mmc-hs",
- "ti,itap-del-sel-mms-hs",
+ [MMC_HS] = {"ti,otap-del-sel-mmc-hs26",
+ "ti,itap-del-sel-mmc-hs26",
MMC_CAP(MMC_HS)},
[SD_HS] = {"ti,otap-del-sel-sd-hs",
"ti,itap-del-sel-sd-hs",
MMC_CAP(SD_HS)},
+ [MMC_HS_52] = {"ti,otap-del-sel-mmc-hs",
+ "ti,itap-del-sel-mmc-hs",
+ MMC_CAP(MMC_HS_52)},
[UHS_SDR12] = {"ti,otap-del-sel-sdr12",
"ti,itap-del-sel-sdr12",
MMC_CAP(UHS_SDR12)},
@@ -409,8 +412,7 @@
*/
case SD_HS:
case MMC_HS:
- case UHS_SDR12:
- case UHS_SDR25:
+ case MMC_HS_52:
val &= ~SDHCI_CTRL_HISPD;
default:
break;
@@ -521,13 +523,24 @@
return 0;
}
#endif
+
+void am654_sdhci_set_control_reg(struct sdhci_host *host)
+{
+ struct mmc *mmc = host->mmc;
+
+ sdhci_set_voltage(host);
+
+ if (mmc->selected_mode > MMC_HS_52)
+ sdhci_set_uhs_timing(host);
+}
+
const struct sdhci_ops am654_sdhci_ops = {
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
.platform_execute_tuning = am654_sdhci_execute_tuning,
#endif
.deferred_probe = am654_sdhci_deferred_probe,
.set_ios_post = &am654_sdhci_set_ios_post,
- .set_control_reg = sdhci_set_control_reg,
+ .set_control_reg = am654_sdhci_set_control_reg,
.write_b = am654_sdhci_write_b,
};
@@ -587,7 +600,7 @@
#endif
.deferred_probe = am654_sdhci_deferred_probe,
.set_ios_post = &j721e_4bit_sdhci_set_ios_post,
- .set_control_reg = sdhci_set_control_reg,
+ .set_control_reg = am654_sdhci_set_control_reg,
.write_b = am654_sdhci_write_b,
};
diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
index c8db4f8..2f4dc5b 100644
--- a/drivers/mmc/mmc-uclass.c
+++ b/drivers/mmc/mmc-uclass.c
@@ -83,6 +83,19 @@
return dm_mmc_wait_dat0(mmc->dev, state, timeout_us);
}
+void dm_mmc_send_init_stream(struct udevice *dev)
+{
+ struct dm_mmc_ops *ops = mmc_get_ops(dev);
+
+ if (ops->send_init_stream)
+ ops->send_init_stream(dev);
+}
+
+void mmc_send_init_stream(struct mmc *mmc)
+{
+ dm_mmc_send_init_stream(mmc->dev);
+}
+
static int dm_mmc_get_wp(struct udevice *dev)
{
struct dm_mmc_ops *ops = mmc_get_ops(dev);
@@ -498,22 +511,12 @@
return ret;
}
- ret = device_probe(dev);
- if (ret) {
- debug("Probing %s failed (err=%d)\n", dev->name, ret);
-
- mmc_deinit(mmc);
-
- return ret;
- }
-
return 0;
}
-static int mmc_blk_remove(struct udevice *dev)
+static int mmc_remove(struct udevice *dev)
{
- struct udevice *mmc_dev = dev_get_parent(dev);
- struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc_dev);
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct mmc *mmc = upriv->mmc;
return mmc_deinit(mmc);
@@ -533,7 +536,6 @@
.id = UCLASS_BLK,
.ops = &mmc_blk_ops,
.probe = mmc_blk_probe,
- .remove = mmc_blk_remove,
.flags = DM_FLAG_OS_PREPARE,
};
#endif /* CONFIG_BLK */
@@ -543,4 +545,5 @@
.name = "mmc",
.flags = DM_UC_FLAG_SEQ_ALIAS,
.per_device_auto = sizeof(struct mmc_uclass_priv),
+ .pre_remove = mmc_remove,
};
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 31a7236..cdcf2e0 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1663,6 +1663,10 @@
}
#endif
+static void mmc_send_init_stream(struct mmc *mmc)
+{
+}
+
static int mmc_set_ios(struct mmc *mmc)
{
int ret = 0;
@@ -2550,7 +2554,7 @@
/*
* For MMC cards, set the Relative Address.
- * For SD cards, get the Relatvie Address.
+ * For SD cards, get the Relative Address.
* This also puts the cards into Standby State
*/
if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
@@ -2929,6 +2933,8 @@
retry:
mmc_set_initial_state(mmc);
+ mmc_send_init_stream(mmc);
+
/* Reset the Card */
err = mmc_go_idle(mmc);
@@ -3040,9 +3046,9 @@
return err;
}
-static void __maybe_unused mmc_cyclic_cd_poll(struct cyclic_info *c)
+static void mmc_cyclic_cd_poll(struct cyclic_info *c)
{
- struct mmc *m = CONFIG_IS_ENABLED(CYCLIC, (container_of(c, struct mmc, cyclic)), (NULL));
+ struct mmc *m = container_of(c, struct mmc, cyclic);
if (!m->has_init)
return;
@@ -3073,15 +3079,15 @@
if (!err)
err = mmc_complete_init(mmc);
- if (err)
+ if (err) {
pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start));
+ return err;
+ }
if (CONFIG_IS_ENABLED(CYCLIC, (!mmc->cyclic.func), (NULL))) {
/* Register cyclic function for card detect polling */
- CONFIG_IS_ENABLED(CYCLIC, (cyclic_register(&mmc->cyclic,
- mmc_cyclic_cd_poll,
- 100 * 1000,
- mmc->cfg->name)));
+ cyclic_register(&mmc->cyclic, mmc_cyclic_cd_poll, 100 * 1000,
+ mmc->cfg->name);
}
return err;
@@ -3092,7 +3098,7 @@
u32 caps_filtered;
if (CONFIG_IS_ENABLED(CYCLIC, (mmc->cyclic.func), (NULL)))
- CONFIG_IS_ENABLED(CYCLIC, (cyclic_unregister(&mmc->cyclic)));
+ cyclic_unregister(&mmc->cyclic);
if (!CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) &&
!CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) &&
diff --git a/drivers/mmc/mmc_boot.c b/drivers/mmc/mmc_boot.c
index 367c957..986e6c5 100644
--- a/drivers/mmc/mmc_boot.c
+++ b/drivers/mmc/mmc_boot.c
@@ -8,20 +8,107 @@
#include <mmc.h>
#include "mmc_private.h"
-/*
- * This function changes the size of boot partition and the size of rpmb
- * partition present on EMMC devices.
- *
- * Input Parameters:
- * struct *mmc: pointer for the mmc device strcuture
- * bootsize: size of boot partition
- * rpmbsize: size of rpmb partition
- *
- * Returns 0 on success.
- */
+static int mmc_resize_boot_micron(struct mmc *mmc, unsigned long bootsize,
+ unsigned long rpmbsize)
+{
+ int err;
-int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
- unsigned long rpmbsize)
+ /* Micron eMMC doesn't support resizing RPMB partition */
+ (void)rpmbsize;
+
+ /* BOOT partition size is multiple of 128KB */
+ bootsize = (bootsize * 1024) / 128;
+
+ if (bootsize > 0xff)
+ bootsize = 0xff;
+
+ /* Set EXT_CSD[175] ERASE_GROUP_DEF to 0x01 */
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_ERASE_GROUP_DEF, 0x01);
+ if (err)
+ goto error;
+
+ /* Set EXT_CSD[127:125] for BOOT partition size, [125] is low byte */
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_BOOT_SIZE_MULT_MICRON, bootsize);
+ if (err)
+ goto error;
+
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_BOOT_SIZE_MULT_MICRON + 1, 0x00);
+ if (err)
+ goto error;
+
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_BOOT_SIZE_MULT_MICRON + 2, 0x00);
+ if (err)
+ goto error;
+
+ /* Set EXT_CSD[155] PARTITION_SETTING_COMPLETE to 0x01 */
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_PARTITION_SETTING, 0x01);
+ if (err)
+ goto error;
+
+ return 0;
+
+error:
+ debug("%s: Error = %d\n", __func__, err);
+ return err;
+}
+
+static int mmc_resize_boot_sandisk(struct mmc *mmc, unsigned long bootsize,
+ unsigned long rpmbsize)
+{
+ int err;
+ struct mmc_cmd cmd;
+
+ /* BOOT/RPMB partition size is multiple of 128KB */
+ bootsize = (bootsize * 1024) / 128;
+ rpmbsize = (rpmbsize * 1024) / 128;
+
+ if (bootsize > 0xff)
+ bootsize = 0xff;
+
+ if (rpmbsize > 0xff)
+ rpmbsize = 0xff;
+
+ /* Send BOOT/RPMB resize op code */
+ cmd.cmdidx = MMC_CMD_RES_MAN;
+ cmd.resp_type = MMC_RSP_R1b;
+ cmd.cmdarg = MMC_CMD62_ARG_SANDISK;
+
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+ if (err)
+ goto error;
+
+ /* Arg: BOOT partition size */
+ cmd.cmdidx = MMC_CMD_RES_MAN;
+ cmd.resp_type = MMC_RSP_R1b;
+ cmd.cmdarg = bootsize;
+
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+ if (err)
+ goto error;
+
+ /* Arg: RPMB partition size */
+ cmd.cmdidx = MMC_CMD_RES_MAN;
+ cmd.resp_type = MMC_RSP_R1b;
+ cmd.cmdarg = rpmbsize;
+
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+ if (err)
+ goto error;
+
+ return 0;
+
+error:
+ debug("%s: Error = %d\n", __func__, err);
+ return err;
+}
+
+static int mmc_resize_boot_samsung(struct mmc *mmc, unsigned long bootsize,
+ unsigned long rpmbsize)
{
int err;
struct mmc_cmd cmd;
@@ -32,10 +119,8 @@
cmd.cmdarg = MMC_CMD62_ARG1;
err = mmc_send_cmd(mmc, &cmd, NULL);
- if (err) {
- debug("mmc_boot_partition_size_change: Error1 = %d\n", err);
- return err;
- }
+ if (err)
+ goto error;
/* Boot partition changing mode */
cmd.cmdidx = MMC_CMD_RES_MAN;
@@ -43,10 +128,9 @@
cmd.cmdarg = MMC_CMD62_ARG2;
err = mmc_send_cmd(mmc, &cmd, NULL);
- if (err) {
- debug("mmc_boot_partition_size_change: Error2 = %d\n", err);
- return err;
- }
+ if (err)
+ goto error;
+
/* boot partition size is multiple of 128KB */
bootsize = (bootsize * 1024) / 128;
@@ -56,10 +140,9 @@
cmd.cmdarg = bootsize;
err = mmc_send_cmd(mmc, &cmd, NULL);
- if (err) {
- debug("mmc_boot_partition_size_change: Error3 = %d\n", err);
- return err;
- }
+ if (err)
+ goto error;
+
/* RPMB partition size is multiple of 128KB */
rpmbsize = (rpmbsize * 1024) / 128;
/* Arg: RPMB partition size */
@@ -68,11 +151,43 @@
cmd.cmdarg = rpmbsize;
err = mmc_send_cmd(mmc, &cmd, NULL);
- if (err) {
- debug("mmc_boot_partition_size_change: Error4 = %d\n", err);
- return err;
- }
+ if (err)
+ goto error;
+
return 0;
+
+error:
+ debug("%s: Error = %d\n", __func__, err);
+ return err;
+}
+
+/*
+ * This function changes the size of BOOT partition and the size of RPMB
+ * partition present on eMMC devices.
+ *
+ * Input Parameters:
+ * struct *mmc: pointer for the mmc device strcuture
+ * bootsize: size of BOOT partition
+ * rpmbsize: size of RPMB partition
+ *
+ * Returns 0 on success.
+ */
+
+int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
+ unsigned long rpmbsize)
+{
+ switch (mmc->cid[0] >> 24) {
+ case CID_MANFID_MICRON:
+ return mmc_resize_boot_micron(mmc, bootsize, rpmbsize);
+ case CID_MANFID_SAMSUNG:
+ return mmc_resize_boot_samsung(mmc, bootsize, rpmbsize);
+ case CID_MANFID_SANDISK:
+ return mmc_resize_boot_sandisk(mmc, bootsize, rpmbsize);
+ default:
+ printf("Unsupported manufacturer id 0x%02x\n",
+ mmc->cid[0] >> 24);
+ return -EPERM;
+ }
}
/*
diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c
index c023d15..90fcf26 100644
--- a/drivers/mmc/mmc_write.c
+++ b/drivers/mmc/mmc_write.c
@@ -80,6 +80,8 @@
struct mmc *mmc = find_mmc_device(dev_num);
lbaint_t blk = 0, blk_r = 0;
int timeout_ms = 1000;
+ u32 grpcnt;
+
if (!mmc)
return -1;
@@ -123,6 +125,15 @@
} else {
blk_r = ((blkcnt - blk) > mmc->erase_grp_size) ?
mmc->erase_grp_size : (blkcnt - blk);
+
+ grpcnt = (blkcnt - blk) / mmc->erase_grp_size;
+ /* Max 2GB per spec */
+ if ((blkcnt - blk) > 0x400000)
+ blk_r = 0x400000;
+ else if (grpcnt)
+ blk_r = grpcnt * mmc->erase_grp_size;
+ else
+ blk_r = blkcnt - blk;
}
err = mmc_erase_t(mmc, start + blk, blk_r, erase_args);
if (err)
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index e66ab25..92bc72b 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -780,6 +780,14 @@
return ret;
}
#endif
+
+static void omap_hsmmc_send_init_stream(struct udevice *dev)
+{
+ struct omap_hsmmc_data *priv = dev_get_priv(dev);
+ struct hsmmc *mmc_base = priv->base_addr;
+
+ mmc_init_stream(mmc_base);
+}
#endif
static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
@@ -1515,9 +1523,10 @@
.get_wp = omap_hsmmc_getwp,
#endif
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
- .execute_tuning = omap_hsmmc_execute_tuning,
+ .execute_tuning = omap_hsmmc_execute_tuning,
#endif
- .wait_dat0 = omap_hsmmc_wait_dat0,
+ .send_init_stream = omap_hsmmc_send_init_stream,
+ .wait_dat0 = omap_hsmmc_wait_dat0,
};
#else
static const struct mmc_ops omap_hsmmc_ops = {
diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index 422b8f7..7a72aba 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -171,6 +171,7 @@
static const struct udevice_id rockchip_dwmmc_ids[] = {
{ .compatible = "rockchip,rk2928-dw-mshc" },
{ .compatible = "rockchip,rk3288-dw-mshc" },
+ { .compatible = "rockchip,rk3576-dw-mshc" },
{ }
};
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index da630b9..761e361 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -50,6 +50,10 @@
#define DWCMSHC_EMMC_EMMC_CTRL 0x52c
#define DWCMSHC_CARD_IS_EMMC BIT(0)
#define DWCMSHC_ENHANCED_STROBE BIT(8)
+#define DWCMSHC_EMMC_AT_CTRL 0x540
+#define EMMC_AT_CTRL_TUNE_CLK_STOP_EN BIT(16)
+#define EMMC_AT_CTRL_PRE_CHANGE_DLY 17
+#define EMMC_AT_CTRL_POST_CHANGE_DLY 19
#define DWCMSHC_EMMC_DLL_CTRL 0x800
#define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1)
#define DWCMSHC_EMMC_DLL_RXCLK 0x804
@@ -156,6 +160,9 @@
u32 flags;
u8 hs200_txclk_tapnum;
u8 hs400_txclk_tapnum;
+ u8 hs400_cmdout_tapnum;
+ u8 hs400_strbin_tapnum;
+ u8 ddr50_strbin_delay_num;
};
static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock)
@@ -323,6 +330,11 @@
udelay(1);
sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
+ extra = 0x3 << EMMC_AT_CTRL_POST_CHANGE_DLY |
+ 0x3 << EMMC_AT_CTRL_PRE_CHANGE_DLY |
+ EMMC_AT_CTRL_TUNE_CLK_STOP_EN;
+ sdhci_writel(host, extra, DWCMSHC_EMMC_AT_CTRL);
+
/* Init DLL settings */
extra = DWCMSHC_EMMC_DLL_START_DEFAULT << DWCMSHC_EMMC_DLL_START_POINT |
DWCMSHC_EMMC_DLL_INC_VALUE << DWCMSHC_EMMC_DLL_INC |
@@ -348,7 +360,7 @@
extra = DLL_CMDOUT_SRC_CLK_NEG |
DLL_CMDOUT_BOTH_CLK_EDGE |
DWCMSHC_EMMC_DLL_DLYENA |
- DLL_CMDOUT_TAPNUM_90_DEGREES |
+ data->hs400_cmdout_tapnum |
DLL_CMDOUT_TAPNUM_FROM_SW;
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CMDOUT);
}
@@ -360,7 +372,7 @@
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
extra = DWCMSHC_EMMC_DLL_DLYENA |
- DLL_STRBIN_TAPNUM_DEFAULT |
+ data->hs400_strbin_tapnum |
DLL_STRBIN_TAPNUM_FROM_SW;
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
} else {
@@ -380,7 +392,7 @@
*/
extra = DWCMSHC_EMMC_DLL_DLYENA |
DLL_STRBIN_DELAY_NUM_SEL |
- DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET;
+ data->ddr50_strbin_delay_num << DLL_STRBIN_DELAY_NUM_OFFSET;
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
}
@@ -647,6 +659,17 @@
.set_enhanced_strobe = rk3399_sdhci_set_enhanced_strobe,
};
+static const struct sdhci_data rk3528_data = {
+ .set_ios_post = rk3568_sdhci_set_ios_post,
+ .set_clock = rk3568_sdhci_set_clock,
+ .config_dll = rk3568_sdhci_config_dll,
+ .hs200_txclk_tapnum = 0xc,
+ .hs400_txclk_tapnum = 0x6,
+ .hs400_cmdout_tapnum = 0x6,
+ .hs400_strbin_tapnum = 0x3,
+ .ddr50_strbin_delay_num = 0xa,
+};
+
static const struct sdhci_data rk3568_data = {
.set_ios_post = rk3568_sdhci_set_ios_post,
.set_clock = rk3568_sdhci_set_clock,
@@ -654,6 +677,20 @@
.flags = FLAG_INVERTER_FLAG_IN_RXCLK,
.hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT,
.hs400_txclk_tapnum = 0x8,
+ .hs400_cmdout_tapnum = DLL_CMDOUT_TAPNUM_90_DEGREES,
+ .hs400_strbin_tapnum = DLL_STRBIN_TAPNUM_DEFAULT,
+ .ddr50_strbin_delay_num = DLL_STRBIN_DELAY_NUM_DEFAULT,
+};
+
+static const struct sdhci_data rk3576_data = {
+ .set_ios_post = rk3568_sdhci_set_ios_post,
+ .set_clock = rk3568_sdhci_set_clock,
+ .config_dll = rk3568_sdhci_config_dll,
+ .hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT,
+ .hs400_txclk_tapnum = 0x7,
+ .hs400_cmdout_tapnum = 0x7,
+ .hs400_strbin_tapnum = 0x5,
+ .ddr50_strbin_delay_num = 0xa,
};
static const struct sdhci_data rk3588_data = {
@@ -662,6 +699,9 @@
.config_dll = rk3568_sdhci_config_dll,
.hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT,
.hs400_txclk_tapnum = 0x9,
+ .hs400_cmdout_tapnum = DLL_CMDOUT_TAPNUM_90_DEGREES,
+ .hs400_strbin_tapnum = DLL_STRBIN_TAPNUM_DEFAULT,
+ .ddr50_strbin_delay_num = DLL_STRBIN_DELAY_NUM_DEFAULT,
};
static const struct udevice_id sdhci_ids[] = {
@@ -670,10 +710,18 @@
.data = (ulong)&rk3399_data,
},
{
+ .compatible = "rockchip,rk3528-dwcmshc",
+ .data = (ulong)&rk3528_data,
+ },
+ {
.compatible = "rockchip,rk3568-dwcmshc",
.data = (ulong)&rk3568_data,
},
{
+ .compatible = "rockchip,rk3576-dwcmshc",
+ .data = (ulong)&rk3576_data,
+ },
+ {
.compatible = "rockchip,rk3588-dwcmshc",
.data = (ulong)&rk3588_data,
},
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 4833b51..648dfa4 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -177,8 +177,10 @@
} while (!(stat & SDHCI_INT_DATA_END));
#if (CONFIG_IS_ENABLED(MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
- dma_unmap_single(host->start_addr, data->blocks * data->blocksize,
- mmc_get_dma_dir(data));
+ if (host->flags & USE_DMA) {
+ dma_unmap_single(host->start_addr, data->blocks * data->blocksize,
+ mmc_get_dma_dir(data));
+ }
#endif
return 0;
@@ -547,7 +549,7 @@
sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
}
-static void sdhci_set_voltage(struct sdhci_host *host)
+void sdhci_set_voltage(struct sdhci_host *host)
{
if (IS_ENABLED(CONFIG_MMC_IO_VOLTAGE)) {
struct mmc *mmc = (struct mmc *)host->mmc;
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 951e6ac..06c1e09 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -478,29 +478,29 @@
static int mmc_resource_init(int sdc_no)
{
struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
- struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ void *ccm = (void *)SUNXI_CCM_BASE;
debug("init mmc %d resource\n", sdc_no);
switch (sdc_no) {
case 0:
priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
- priv->mclkreg = &ccm->sd0_clk_cfg;
+ priv->mclkreg = ccm + CCU_MMC0_CLK_CFG;
break;
case 1:
priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
- priv->mclkreg = &ccm->sd1_clk_cfg;
+ priv->mclkreg = ccm + CCU_MMC1_CLK_CFG;
break;
#ifdef SUNXI_MMC2_BASE
case 2:
priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
- priv->mclkreg = &ccm->sd2_clk_cfg;
+ priv->mclkreg = ccm + CCU_MMC2_CLK_CFG;
break;
#endif
#ifdef SUNXI_MMC3_BASE
case 3:
priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
- priv->mclkreg = &ccm->sd3_clk_cfg;
+ priv->mclkreg = ccm + CCU_MMC3_CLK_CFG;
break;
#endif
default:
@@ -545,7 +545,7 @@
struct mmc *sunxi_mmc_init(int sdc_no)
{
- struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ void *ccm = (void *)SUNXI_CCM_BASE;
struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
struct mmc_config *cfg = &priv->cfg;
int ret;
@@ -574,11 +574,11 @@
/* config ahb clock */
debug("init mmc %d clock and io\n", sdc_no);
#if !defined(CONFIG_SUN50I_GEN_H6) && !defined(CONFIG_SUNXI_GEN_NCAT2)
- setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
+ setbits_le32(ccm + CCU_AHB_GATE0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
#ifdef CONFIG_SUNXI_GEN_SUN6I
/* unassert reset */
- setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
+ setbits_le32(ccm + CCU_AHB_RESET0_CFG, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
#endif
#if defined(CONFIG_MACH_SUN9I)
/* sun9i has a mmc-common module, also set the gate and reset there */
@@ -586,9 +586,9 @@
SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
#endif
#else /* CONFIG_SUN50I_GEN_H6 */
- setbits_le32(&ccm->sd_gate_reset, 1 << sdc_no);
+ setbits_le32(ccm + CCU_H6_MMC_GATE_RESET, 1 << sdc_no);
/* unassert reset */
- setbits_le32(&ccm->sd_gate_reset, 1 << (RESET_SHIFT + sdc_no));
+ setbits_le32(ccm + CCU_H6_MMC_GATE_RESET, 1 << (RESET_SHIFT + sdc_no));
#endif
ret = mmc_set_mod_clk(priv, 24000000);
if (ret)
diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c
index 3f8edeb..842d3e7 100644
--- a/drivers/mtd/mtdpart.c
+++ b/drivers/mtd/mtdpart.c
@@ -236,6 +236,10 @@
if (ret)
return ret;
+ if (parts[idx].offset == MTD_OFFSET_NOT_SPECIFIED)
+ parts[idx].offset = cur_off;
+ cur_off += parts[idx].size;
+
if (parts[idx].size == MTD_SIZE_REMAINING)
parts[idx].size = parent->size - parts[idx].offset;
@@ -246,10 +250,6 @@
return -EINVAL;
}
- if (parts[idx].offset == MTD_OFFSET_NOT_SPECIFIED)
- parts[idx].offset = cur_off;
- cur_off += parts[idx].size;
-
parts[idx].ecclayout = parent->ecclayout;
}
@@ -909,11 +909,13 @@
continue;
offset = ofnode_get_addr_size_index_notrans(child, 0, &size);
- if (offset == FDT_ADDR_T_NONE || !size) {
- debug("Missing partition offset/size on \"%s\" partition\n",
+ if (offset == FDT_ADDR_T_NONE) {
+ debug("Missing partition offset on \"%s\" partition\n",
master->name);
continue;
}
+ if (size == MTDPART_SIZ_FULL)
+ size = master->size - offset;
part.name = ofnode_read_string(child, "label");
if (!part.name)
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index f5ddfbf..3a1e7e1 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -941,6 +941,19 @@
return NULL;
}
+static int spinand_setup_slave(struct spinand_device *spinand,
+ const struct spinand_info *spinand_info)
+{
+ struct spi_slave *slave = spinand->slave;
+ struct udevice *bus = slave->dev->parent;
+ struct dm_spi_ops *ops = spi_get_ops(bus);
+
+ if (!ops->setup_for_spinand)
+ return 0;
+
+ return ops->setup_for_spinand(slave, spinand_info);
+}
+
/**
* spinand_match_and_init() - Try to find a match between a device ID and an
* entry in a spinand_info table
@@ -964,6 +977,7 @@
u8 *id = spinand->id.data;
struct nand_device *nand = spinand_to_nand(spinand);
unsigned int i;
+ int ret;
for (i = 0; i < table_size; i++) {
const struct spinand_info *info = &table[i];
@@ -975,6 +989,10 @@
if (memcmp(id + 1, info->devid.id, info->devid.len))
continue;
+ ret = spinand_setup_slave(spinand, info);
+ if (ret)
+ return ret;
+
nand->memorg = table[i].memorg;
nand->eccreq = table[i].eccreq;
spinand->eccinfo = table[i].eccinfo;
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 6f352c5..87a3099 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -655,7 +655,7 @@
return mtd->priv;
}
-#ifndef CONFIG_SPI_FLASH_BAR
+#if !CONFIG_IS_ENABLED(SPI_FLASH_BAR)
static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
{
size_t i;
@@ -739,7 +739,7 @@
nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
}
-#endif /* !CONFIG_SPI_FLASH_BAR */
+#endif /* !CONFIG_IS_ENABLED(SPI_FLASH_BAR) */
/* Enable/disable 4-byte addressing mode. */
static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
@@ -930,7 +930,7 @@
return spi_nor_wait_till_ready_with_timeout(nor, timeout);
}
-#ifdef CONFIG_SPI_FLASH_BAR
+#if CONFIG_IS_ENABLED(SPI_FLASH_BAR)
/*
* This "clean_bar" is necessary in a situation when one was accessing
* spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
@@ -1141,7 +1141,7 @@
nor->spi->flags &= ~SPI_XFER_U_PAGE;
}
}
-#ifdef CONFIG_SPI_FLASH_BAR
+#if CONFIG_IS_ENABLED(SPI_FLASH_BAR)
ret = write_bar(nor, offset);
if (ret < 0)
goto erase_err;
@@ -1175,7 +1175,7 @@
addr_known = false;
erase_err:
-#ifdef CONFIG_SPI_FLASH_BAR
+#if CONFIG_IS_ENABLED(SPI_FLASH_BAR)
err = clean_bar(nor);
if (!ret)
ret = err;
@@ -1630,7 +1630,7 @@
offset /= 2;
}
-#ifdef CONFIG_SPI_FLASH_BAR
+#if CONFIG_IS_ENABLED(SPI_FLASH_BAR)
ret = write_bar(nor, offset);
if (ret < 0)
return log_ret(ret);
@@ -1667,7 +1667,7 @@
ret = 0;
read_err:
-#ifdef CONFIG_SPI_FLASH_BAR
+#if CONFIG_IS_ENABLED(SPI_FLASH_BAR)
ret = clean_bar(nor);
#endif
return ret;
@@ -2016,7 +2016,7 @@
}
}
-#ifdef CONFIG_SPI_FLASH_BAR
+#if CONFIG_IS_ENABLED(SPI_FLASH_BAR)
ret = write_bar(nor, offset);
if (ret < 0)
return ret;
@@ -2090,7 +2090,7 @@
}
write_err:
-#ifdef CONFIG_SPI_FLASH_BAR
+#if CONFIG_IS_ENABLED(SPI_FLASH_BAR)
ret = clean_bar(nor);
#endif
return ret;
@@ -3592,6 +3592,19 @@
mtd->erasesize = info->sector_size;
}
+ if ((JEDEC_MFR(info) == SNOR_MFR_SST) && info->flags & SECT_4K) {
+ nor->erase_opcode = SPINOR_OP_BE_4K;
+ /*
+ * In parallel-memories the erase operation is
+ * performed on both the flashes simultaneously
+ * so, double the erasesize.
+ */
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ mtd->erasesize = 4096 * 2;
+ else
+ mtd->erasesize = 4096;
+ }
+
return 0;
}
@@ -3791,7 +3804,7 @@
int ret;
u8 cr;
-#ifdef CONFIG_SPI_FLASH_BAR
+#if CONFIG_IS_ENABLED(SPI_FLASH_BAR)
return -ENOTSUPP; /* Bank Address Register is not supported */
#endif
/*
@@ -4577,7 +4590,7 @@
if (nor->flags & (SNOR_F_HAS_PARALLEL | SNOR_F_HAS_STACKED))
shift = 1;
if (nor->addr_width == 3 && (mtd->size >> shift) > SZ_16M) {
-#ifndef CONFIG_SPI_FLASH_BAR
+#if !CONFIG_IS_ENABLED(SPI_FLASH_BAR)
/* enable 4-byte addressing if the device exceeds 16MiB */
nor->addr_width = 4;
if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 91ae49c..e7e9778 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -358,10 +358,13 @@
#ifdef CONFIG_SPI_FLASH_MT35XU
{ INFO("mt35xl512aba", 0x2c5a1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
{ INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
- { INFO("mt35xu01gaba", 0x2c5b1b, 0, 128 * 1024, 1024, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mt35xu01gaba", 0x2c5b1b, 0, 128 * 1024, 1024,
+ USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | NO_CHIP_ERASE) },
#endif /* CONFIG_SPI_FLASH_MT35XU */
- { INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
- { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
+ { INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024,
+ USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | NO_CHIP_ERASE) },
+ { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048,
+ USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | NO_CHIP_ERASE) },
#endif
#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
/* Spansion/Cypress -- single (large) sector size only, at least
@@ -414,8 +417,10 @@
{ INFO6("s25fs256t", 0x342b19, 0x0f0890, 128 * 1024, 256,
SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
#ifdef CONFIG_SPI_FLASH_S28HX_T
+ { INFO("s28hl256t", 0x345a19, 0, 256 * 1024, 128, SPI_NOR_OCTAL_DTR_READ) },
{ INFO("s28hl512t", 0x345a1a, 0, 256 * 1024, 256, SPI_NOR_OCTAL_DTR_READ) },
{ INFO("s28hl01gt", 0x345a1b, 0, 256 * 1024, 512, SPI_NOR_OCTAL_DTR_READ) },
+ { INFO("s28hl02gt", 0x345a1c, 0, 256 * 1024, 1024, SPI_NOR_OCTAL_DTR_READ | NO_CHIP_ERASE) },
{ INFO("s28hs256t", 0x345b19, 0, 256 * 1024, 128, SPI_NOR_OCTAL_DTR_READ) },
{ INFO("s28hs512t", 0x345b1a, 0, 256 * 1024, 256, SPI_NOR_OCTAL_DTR_READ) },
{ INFO("s28hs01gt", 0x345b1b, 0, 256 * 1024, 512, SPI_NOR_OCTAL_DTR_READ) },
diff --git a/drivers/mux/Makefile b/drivers/mux/Makefile
index 63770e1..b61f713 100644
--- a/drivers/mux/Makefile
+++ b/drivers/mux/Makefile
@@ -4,4 +4,4 @@
# Jean-Jacques Hiblot <jjhiblot@ti.com>
obj-$(CONFIG_MULTIPLEXER) += mux-uclass.o
-obj-$(CONFIG_$(XPL_)MUX_MMIO) += mmio.o
+obj-$(CONFIG_$(PHASE_)MUX_MMIO) += mmio.o
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 3db784f..4434d36 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -48,7 +48,6 @@
bool "Enable Driver Model for DSA switches"
depends on DM_MDIO
depends on PHY_FIXED
- depends on !NET_LWIP
help
Enable driver model for DSA switches
@@ -122,6 +121,14 @@
This driver supports the Atheros AG7xxx Ethernet MAC. This MAC is
present in the Atheros AR7xxx, AR9xxx and QCA9xxx MIPS chips.
+config AIROHA_ETH
+ bool "Airoha Ethernet QDMA Driver"
+ depends on ARCH_AIROHA
+ select PHYLIB
+ select DM_RESET
+ help
+ This Driver support Airoha Ethernet QDMA Driver
+ Say Y to enable support for the Airoha Ethernet QDMA.
config ALTERA_TSE
bool "Altera Triple-Speed Ethernet MAC support"
@@ -350,7 +357,7 @@
config ETH_SANDBOX
depends on SANDBOX
- depends on NET
+ depends on NET || NET_LWIP
default y
bool "Sandbox: Mocked Ethernet driver"
help
@@ -359,17 +366,6 @@
This driver is particularly useful in the test/dm/eth.c tests
-config ETH_SANDBOX_LWIP
- depends on SANDBOX
- depends on NET_LWIP
- default y
- bool "Sandbox: Mocked Ethernet driver (for NET_LWIP)"
- help
- This driver is meant as a replacement for ETH_SANDBOX when
- the network stack is NET_LWIP rather than NET. It currently
- does nothing, i.e. it drops the sent packets and never receives
- data.
-
config ETH_SANDBOX_RAW
depends on SANDBOX
depends on NET
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index d919d43..67bba3a 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_AG7XXX) += ag7xxx.o
+obj-$(CONFIG_AIROHA_ETH) += airoha_eth.o
obj-$(CONFIG_ALTERA_TSE) += altera_tse.o
obj-$(CONFIG_ASPEED_MDIO) += aspeed_mdio.o
obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o
@@ -40,7 +41,6 @@
obj-$(CONFIG_ETH_SANDBOX) += sandbox.o
obj-$(CONFIG_ETH_SANDBOX_RAW) += sandbox-raw-bus.o
obj-$(CONFIG_ETH_SANDBOX_RAW) += sandbox-raw.o
-obj-$(CONFIG_ETH_SANDBOX_LWIP) += sandbox-lwip.o
obj-$(CONFIG_FEC_MXC) += fec_mxc.o
obj-$(CONFIG_FMAN_ENET) += fm/
obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o
diff --git a/drivers/net/airoha_eth.c b/drivers/net/airoha_eth.c
new file mode 100644
index 0000000..7e35e1f
--- /dev/null
+++ b/drivers/net/airoha_eth.c
@@ -0,0 +1,948 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Based on Linux airoha_eth.c majorly rewritten
+ * and simplified for U-Boot usage for single TX/RX ring.
+ *
+ * Copyright (c) 2024 AIROHA Inc
+ * Author: Lorenzo Bianconi <lorenzo@kernel.org>
+ * Christian Marangi <ansuelsmth@gmail.org>
+ */
+
+#include <dm.h>
+#include <dm/devres.h>
+#include <mapmem.h>
+#include <net.h>
+#include <regmap.h>
+#include <reset.h>
+#include <syscon.h>
+#include <linux/bitfield.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/time.h>
+
+#define AIROHA_MAX_NUM_GDM_PORTS 1
+#define AIROHA_MAX_NUM_QDMA 1
+#define AIROHA_MAX_NUM_RSTS 3
+#define AIROHA_MAX_NUM_XSI_RSTS 4
+
+#define AIROHA_MAX_PACKET_SIZE 2048
+#define AIROHA_NUM_TX_RING 1
+#define AIROHA_NUM_RX_RING 1
+#define AIROHA_NUM_TX_IRQ 1
+#define HW_DSCP_NUM 32
+#define IRQ_QUEUE_LEN 1
+#define TX_DSCP_NUM 16
+#define RX_DSCP_NUM PKTBUFSRX
+
+/* SCU */
+#define SCU_SHARE_FEMEM_SEL 0x958
+
+/* SWITCH */
+#define SWITCH_MFC 0x10
+#define SWITCH_BC_FFP GENMASK(31, 24)
+#define SWITCH_UNM_FFP GENMASK(23, 16)
+#define SWITCH_UNU_FFP GENMASK(15, 8)
+#define SWITCH_PMCR(_n) 0x3000 + ((_n) * 0x100)
+#define SWITCH_IPG_CFG GENMASK(19, 18)
+#define SWITCH_IPG_CFG_NORMAL FIELD_PREP(SWITCH_IPG_CFG, 0x0)
+#define SWITCH_IPG_CFG_SHORT FIELD_PREP(SWITCH_IPG_CFG, 0x1)
+#define SWITCH_IPG_CFG_SHRINK FIELD_PREP(SWITCH_IPG_CFG, 0x2)
+#define SWITCH_MAC_MODE BIT(16)
+#define SWITCH_FORCE_MODE BIT(15)
+#define SWITCH_MAC_TX_EN BIT(14)
+#define SWITCH_MAC_RX_EN BIT(13)
+#define SWITCH_BKOFF_EN BIT(9)
+#define SWITCH_BKPR_EN BIT(8)
+#define SWITCH_FORCE_RX_FC BIT(5)
+#define SWITCH_FORCE_TX_FC BIT(4)
+#define SWITCH_FORCE_SPD GENMASK(3, 2)
+#define SWITCH_FORCE_SPD_10 FIELD_PREP(SWITCH_FORCE_SPD, 0x0)
+#define SWITCH_FORCE_SPD_100 FIELD_PREP(SWITCH_FORCE_SPD, 0x1)
+#define SWITCH_FORCE_SPD_1000 FIELD_PREP(SWITCH_FORCE_SPD, 0x2)
+#define SWITCH_FORCE_DPX BIT(1)
+#define SWITCH_FORCE_LNK BIT(0)
+#define SWITCH_SMACCR0 0x30e4
+#define SMACCR0_MAC2 GENMASK(31, 24)
+#define SMACCR0_MAC3 GENMASK(23, 16)
+#define SMACCR0_MAC4 GENMASK(15, 8)
+#define SMACCR0_MAC5 GENMASK(7, 0)
+#define SWITCH_SMACCR1 0x30e8
+#define SMACCR1_MAC0 GENMASK(15, 8)
+#define SMACCR1_MAC1 GENMASK(7, 0)
+#define SWITCH_PHY_POLL 0x7018
+#define SWITCH_PHY_AP_EN GENMASK(30, 24)
+#define SWITCH_EEE_POLL_EN GENMASK(22, 16)
+#define SWITCH_PHY_PRE_EN BIT(15)
+#define SWITCH_PHY_END_ADDR GENMASK(12, 8)
+#define SWITCH_PHY_ST_ADDR GENMASK(4, 0)
+
+/* FE */
+#define PSE_BASE 0x0100
+#define CSR_IFC_BASE 0x0200
+#define CDM1_BASE 0x0400
+#define GDM1_BASE 0x0500
+#define PPE1_BASE 0x0c00
+
+#define CDM2_BASE 0x1400
+#define GDM2_BASE 0x1500
+
+#define GDM3_BASE 0x1100
+#define GDM4_BASE 0x2500
+
+#define GDM_BASE(_n) \
+ ((_n) == 4 ? GDM4_BASE : \
+ (_n) == 3 ? GDM3_BASE : \
+ (_n) == 2 ? GDM2_BASE : GDM1_BASE)
+
+#define REG_GDM_FWD_CFG(_n) GDM_BASE(_n)
+#define GDM_DROP_CRC_ERR BIT(23)
+#define GDM_IP4_CKSUM BIT(22)
+#define GDM_TCP_CKSUM BIT(21)
+#define GDM_UDP_CKSUM BIT(20)
+#define GDM_UCFQ_MASK GENMASK(15, 12)
+#define GDM_BCFQ_MASK GENMASK(11, 8)
+#define GDM_MCFQ_MASK GENMASK(7, 4)
+#define GDM_OCFQ_MASK GENMASK(3, 0)
+
+/* QDMA */
+#define REG_QDMA_GLOBAL_CFG 0x0004
+#define GLOBAL_CFG_RX_2B_OFFSET_MASK BIT(31)
+#define GLOBAL_CFG_DMA_PREFERENCE_MASK GENMASK(30, 29)
+#define GLOBAL_CFG_CPU_TXR_RR_MASK BIT(28)
+#define GLOBAL_CFG_DSCP_BYTE_SWAP_MASK BIT(27)
+#define GLOBAL_CFG_PAYLOAD_BYTE_SWAP_MASK BIT(26)
+#define GLOBAL_CFG_MULTICAST_MODIFY_FP_MASK BIT(25)
+#define GLOBAL_CFG_OAM_MODIFY_MASK BIT(24)
+#define GLOBAL_CFG_RESET_MASK BIT(23)
+#define GLOBAL_CFG_RESET_DONE_MASK BIT(22)
+#define GLOBAL_CFG_MULTICAST_EN_MASK BIT(21)
+#define GLOBAL_CFG_IRQ1_EN_MASK BIT(20)
+#define GLOBAL_CFG_IRQ0_EN_MASK BIT(19)
+#define GLOBAL_CFG_LOOPCNT_EN_MASK BIT(18)
+#define GLOBAL_CFG_RD_BYPASS_WR_MASK BIT(17)
+#define GLOBAL_CFG_QDMA_LOOPBACK_MASK BIT(16)
+#define GLOBAL_CFG_LPBK_RXQ_SEL_MASK GENMASK(13, 8)
+#define GLOBAL_CFG_CHECK_DONE_MASK BIT(7)
+#define GLOBAL_CFG_TX_WB_DONE_MASK BIT(6)
+#define GLOBAL_CFG_MAX_ISSUE_NUM_MASK GENMASK(5, 4)
+#define GLOBAL_CFG_RX_DMA_BUSY_MASK BIT(3)
+#define GLOBAL_CFG_RX_DMA_EN_MASK BIT(2)
+#define GLOBAL_CFG_TX_DMA_BUSY_MASK BIT(1)
+#define GLOBAL_CFG_TX_DMA_EN_MASK BIT(0)
+
+#define REG_FWD_DSCP_BASE 0x0010
+#define REG_FWD_BUF_BASE 0x0014
+
+#define REG_HW_FWD_DSCP_CFG 0x0018
+#define HW_FWD_DSCP_PAYLOAD_SIZE_MASK GENMASK(29, 28)
+#define HW_FWD_DSCP_SCATTER_LEN_MASK GENMASK(17, 16)
+#define HW_FWD_DSCP_MIN_SCATTER_LEN_MASK GENMASK(15, 0)
+
+#define REG_INT_STATUS(_n) \
+ (((_n) == 4) ? 0x0730 : \
+ ((_n) == 3) ? 0x0724 : \
+ ((_n) == 2) ? 0x0720 : \
+ ((_n) == 1) ? 0x0024 : 0x0020)
+
+#define REG_TX_IRQ_BASE(_n) ((_n) ? 0x0048 : 0x0050)
+
+#define REG_TX_IRQ_CFG(_n) ((_n) ? 0x004c : 0x0054)
+#define TX_IRQ_THR_MASK GENMASK(27, 16)
+#define TX_IRQ_DEPTH_MASK GENMASK(11, 0)
+
+#define REG_IRQ_CLEAR_LEN(_n) ((_n) ? 0x0064 : 0x0058)
+#define IRQ_CLEAR_LEN_MASK GENMASK(7, 0)
+
+#define REG_TX_RING_BASE(_n) \
+ (((_n) < 8) ? 0x0100 + ((_n) << 5) : 0x0b00 + (((_n) - 8) << 5))
+
+#define REG_TX_CPU_IDX(_n) \
+ (((_n) < 8) ? 0x0108 + ((_n) << 5) : 0x0b08 + (((_n) - 8) << 5))
+
+#define TX_RING_CPU_IDX_MASK GENMASK(15, 0)
+
+#define REG_TX_DMA_IDX(_n) \
+ (((_n) < 8) ? 0x010c + ((_n) << 5) : 0x0b0c + (((_n) - 8) << 5))
+
+#define TX_RING_DMA_IDX_MASK GENMASK(15, 0)
+
+#define IRQ_RING_IDX_MASK GENMASK(20, 16)
+#define IRQ_DESC_IDX_MASK GENMASK(15, 0)
+
+#define REG_RX_RING_BASE(_n) \
+ (((_n) < 16) ? 0x0200 + ((_n) << 5) : 0x0e00 + (((_n) - 16) << 5))
+
+#define REG_RX_RING_SIZE(_n) \
+ (((_n) < 16) ? 0x0204 + ((_n) << 5) : 0x0e04 + (((_n) - 16) << 5))
+
+#define RX_RING_THR_MASK GENMASK(31, 16)
+#define RX_RING_SIZE_MASK GENMASK(15, 0)
+
+#define REG_RX_CPU_IDX(_n) \
+ (((_n) < 16) ? 0x0208 + ((_n) << 5) : 0x0e08 + (((_n) - 16) << 5))
+
+#define RX_RING_CPU_IDX_MASK GENMASK(15, 0)
+
+#define REG_RX_DMA_IDX(_n) \
+ (((_n) < 16) ? 0x020c + ((_n) << 5) : 0x0e0c + (((_n) - 16) << 5))
+
+#define REG_RX_DELAY_INT_IDX(_n) \
+ (((_n) < 16) ? 0x0210 + ((_n) << 5) : 0x0e10 + (((_n) - 16) << 5))
+
+#define RX_DELAY_INT_MASK GENMASK(15, 0)
+
+#define RX_RING_DMA_IDX_MASK GENMASK(15, 0)
+
+#define REG_LMGR_INIT_CFG 0x1000
+#define LMGR_INIT_START BIT(31)
+#define LMGR_SRAM_MODE_MASK BIT(30)
+#define HW_FWD_PKTSIZE_OVERHEAD_MASK GENMASK(27, 20)
+#define HW_FWD_DESC_NUM_MASK GENMASK(16, 0)
+
+/* CTRL */
+#define QDMA_DESC_DONE_MASK BIT(31)
+#define QDMA_DESC_DROP_MASK BIT(30) /* tx: drop - rx: overflow */
+#define QDMA_DESC_MORE_MASK BIT(29) /* more SG elements */
+#define QDMA_DESC_DEI_MASK BIT(25)
+#define QDMA_DESC_NO_DROP_MASK BIT(24)
+#define QDMA_DESC_LEN_MASK GENMASK(15, 0)
+/* DATA */
+#define QDMA_DESC_NEXT_ID_MASK GENMASK(15, 0)
+/* TX MSG0 */
+#define QDMA_ETH_TXMSG_MIC_IDX_MASK BIT(30)
+#define QDMA_ETH_TXMSG_SP_TAG_MASK GENMASK(29, 14)
+#define QDMA_ETH_TXMSG_ICO_MASK BIT(13)
+#define QDMA_ETH_TXMSG_UCO_MASK BIT(12)
+#define QDMA_ETH_TXMSG_TCO_MASK BIT(11)
+#define QDMA_ETH_TXMSG_TSO_MASK BIT(10)
+#define QDMA_ETH_TXMSG_FAST_MASK BIT(9)
+#define QDMA_ETH_TXMSG_OAM_MASK BIT(8)
+#define QDMA_ETH_TXMSG_CHAN_MASK GENMASK(7, 3)
+#define QDMA_ETH_TXMSG_QUEUE_MASK GENMASK(2, 0)
+/* TX MSG1 */
+#define QDMA_ETH_TXMSG_NO_DROP BIT(31)
+#define QDMA_ETH_TXMSG_METER_MASK GENMASK(30, 24) /* 0x7f no meters */
+#define QDMA_ETH_TXMSG_FPORT_MASK GENMASK(23, 20)
+#define QDMA_ETH_TXMSG_NBOQ_MASK GENMASK(19, 15)
+#define QDMA_ETH_TXMSG_HWF_MASK BIT(14)
+#define QDMA_ETH_TXMSG_HOP_MASK BIT(13)
+#define QDMA_ETH_TXMSG_PTP_MASK BIT(12)
+#define QDMA_ETH_TXMSG_ACNT_G1_MASK GENMASK(10, 6) /* 0x1f do not count */
+#define QDMA_ETH_TXMSG_ACNT_G0_MASK GENMASK(5, 0) /* 0x3f do not count */
+
+/* RX MSG1 */
+#define QDMA_ETH_RXMSG_DEI_MASK BIT(31)
+#define QDMA_ETH_RXMSG_IP6_MASK BIT(30)
+#define QDMA_ETH_RXMSG_IP4_MASK BIT(29)
+#define QDMA_ETH_RXMSG_IP4F_MASK BIT(28)
+#define QDMA_ETH_RXMSG_L4_VALID_MASK BIT(27)
+#define QDMA_ETH_RXMSG_L4F_MASK BIT(26)
+#define QDMA_ETH_RXMSG_SPORT_MASK GENMASK(25, 21)
+#define QDMA_ETH_RXMSG_CRSN_MASK GENMASK(20, 16)
+#define QDMA_ETH_RXMSG_PPE_ENTRY_MASK GENMASK(15, 0)
+
+struct airoha_qdma_desc {
+ __le32 rsv;
+ __le32 ctrl;
+ __le32 addr;
+ __le32 data;
+ __le32 msg0;
+ __le32 msg1;
+ __le32 msg2;
+ __le32 msg3;
+};
+
+struct airoha_qdma_fwd_desc {
+ __le32 addr;
+ __le32 ctrl0;
+ __le32 ctrl1;
+ __le32 ctrl2;
+ __le32 msg0;
+ __le32 msg1;
+ __le32 rsv0;
+ __le32 rsv1;
+};
+
+struct airoha_queue {
+ struct airoha_qdma_desc *desc;
+ u16 head;
+
+ int ndesc;
+};
+
+struct airoha_tx_irq_queue {
+ struct airoha_qdma *qdma;
+
+ int size;
+ u32 *q;
+};
+
+struct airoha_qdma {
+ struct airoha_eth *eth;
+ void __iomem *regs;
+
+ struct airoha_tx_irq_queue q_tx_irq[AIROHA_NUM_TX_IRQ];
+
+ struct airoha_queue q_tx[AIROHA_NUM_TX_RING];
+ struct airoha_queue q_rx[AIROHA_NUM_RX_RING];
+
+ /* descriptor and packet buffers for qdma hw forward */
+ struct {
+ void *desc;
+ void *q;
+ } hfwd;
+};
+
+struct airoha_gdm_port {
+ struct airoha_qdma *qdma;
+ int id;
+};
+
+struct airoha_eth {
+ void __iomem *fe_regs;
+ void __iomem *switch_regs;
+
+ struct reset_ctl_bulk rsts;
+ struct reset_ctl_bulk xsi_rsts;
+
+ struct airoha_qdma qdma[AIROHA_MAX_NUM_QDMA];
+ struct airoha_gdm_port *ports[AIROHA_MAX_NUM_GDM_PORTS];
+};
+
+static u32 airoha_rr(void __iomem *base, u32 offset)
+{
+ return readl(base + offset);
+}
+
+static void airoha_wr(void __iomem *base, u32 offset, u32 val)
+{
+ writel(val, base + offset);
+}
+
+static u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val)
+{
+ val |= (airoha_rr(base, offset) & ~mask);
+ airoha_wr(base, offset, val);
+
+ return val;
+}
+
+#define airoha_fe_rr(eth, offset) \
+ airoha_rr((eth)->fe_regs, (offset))
+#define airoha_fe_wr(eth, offset, val) \
+ airoha_wr((eth)->fe_regs, (offset), (val))
+#define airoha_fe_rmw(eth, offset, mask, val) \
+ airoha_rmw((eth)->fe_regs, (offset), (mask), (val))
+#define airoha_fe_set(eth, offset, val) \
+ airoha_rmw((eth)->fe_regs, (offset), 0, (val))
+#define airoha_fe_clear(eth, offset, val) \
+ airoha_rmw((eth)->fe_regs, (offset), (val), 0)
+
+#define airoha_qdma_rr(qdma, offset) \
+ airoha_rr((qdma)->regs, (offset))
+#define airoha_qdma_wr(qdma, offset, val) \
+ airoha_wr((qdma)->regs, (offset), (val))
+#define airoha_qdma_rmw(qdma, offset, mask, val) \
+ airoha_rmw((qdma)->regs, (offset), (mask), (val))
+#define airoha_qdma_set(qdma, offset, val) \
+ airoha_rmw((qdma)->regs, (offset), 0, (val))
+#define airoha_qdma_clear(qdma, offset, val) \
+ airoha_rmw((qdma)->regs, (offset), (val), 0)
+
+#define airoha_switch_wr(eth, offset, val) \
+ airoha_wr((eth)->switch_regs, (offset), (val))
+
+static void airoha_fe_maccr_init(struct airoha_eth *eth)
+{
+ int p;
+
+ for (p = 1; p <= ARRAY_SIZE(eth->ports); p++) {
+ /* Disable any kind of CRC drop or offload */
+ airoha_fe_wr(eth, REG_GDM_FWD_CFG(p), 0);
+ }
+}
+
+static int airoha_fe_init(struct airoha_eth *eth)
+{
+ airoha_fe_maccr_init(eth);
+
+ return 0;
+}
+
+static void airoha_qdma_reset_rx_desc(struct airoha_queue *q, int index,
+ uchar *rx_packet)
+{
+ struct airoha_qdma_desc *desc;
+ u32 val;
+
+ desc = &q->desc[index];
+ index = (index + 1) % q->ndesc;
+
+ dma_map_single(rx_packet, PKTSIZE_ALIGN, DMA_TO_DEVICE);
+
+ WRITE_ONCE(desc->msg0, cpu_to_le32(0));
+ WRITE_ONCE(desc->msg1, cpu_to_le32(0));
+ WRITE_ONCE(desc->msg2, cpu_to_le32(0));
+ WRITE_ONCE(desc->msg3, cpu_to_le32(0));
+ WRITE_ONCE(desc->addr, cpu_to_le32(virt_to_phys(rx_packet)));
+ WRITE_ONCE(desc->data, cpu_to_le32(index));
+ val = FIELD_PREP(QDMA_DESC_LEN_MASK, PKTSIZE_ALIGN);
+ WRITE_ONCE(desc->ctrl, cpu_to_le32(val));
+
+ dma_map_single(desc, sizeof(*desc), DMA_TO_DEVICE);
+}
+
+static void airoha_qdma_init_rx_desc(struct airoha_queue *q)
+{
+ int i;
+
+ for (i = 0; i < q->ndesc; i++)
+ airoha_qdma_reset_rx_desc(q, i, net_rx_packets[i]);
+}
+
+static int airoha_qdma_init_rx_queue(struct airoha_queue *q,
+ struct airoha_qdma *qdma, int ndesc)
+{
+ int qid = q - &qdma->q_rx[0];
+ unsigned long dma_addr;
+
+ q->ndesc = ndesc;
+ q->head = 0;
+
+ q->desc = dma_alloc_coherent(q->ndesc * sizeof(*q->desc), &dma_addr);
+ if (!q->desc)
+ return -ENOMEM;
+
+ memset(q->desc, 0, q->ndesc * sizeof(*q->desc));
+ dma_map_single(q->desc, q->ndesc * sizeof(*q->desc), DMA_TO_DEVICE);
+
+ airoha_qdma_wr(qdma, REG_RX_RING_BASE(qid), dma_addr);
+ airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid),
+ RX_RING_SIZE_MASK,
+ FIELD_PREP(RX_RING_SIZE_MASK, ndesc));
+
+ airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid), RX_RING_THR_MASK,
+ FIELD_PREP(RX_RING_THR_MASK, 0));
+ airoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid), RX_RING_CPU_IDX_MASK,
+ FIELD_PREP(RX_RING_CPU_IDX_MASK, q->ndesc - 1));
+ airoha_qdma_rmw(qdma, REG_RX_DMA_IDX(qid), RX_RING_DMA_IDX_MASK,
+ FIELD_PREP(RX_RING_DMA_IDX_MASK, q->head));
+
+ return 0;
+}
+
+static int airoha_qdma_init_rx(struct airoha_qdma *qdma)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) {
+ int err;
+
+ err = airoha_qdma_init_rx_queue(&qdma->q_rx[i], qdma,
+ RX_DSCP_NUM);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+static int airoha_qdma_init_tx_queue(struct airoha_queue *q,
+ struct airoha_qdma *qdma, int size)
+{
+ int qid = q - &qdma->q_tx[0];
+ unsigned long dma_addr;
+
+ q->ndesc = size;
+ q->head = 0;
+
+ q->desc = dma_alloc_coherent(q->ndesc * sizeof(*q->desc), &dma_addr);
+ if (!q->desc)
+ return -ENOMEM;
+
+ memset(q->desc, 0, q->ndesc * sizeof(*q->desc));
+ dma_map_single(q->desc, q->ndesc * sizeof(*q->desc), DMA_TO_DEVICE);
+
+ airoha_qdma_wr(qdma, REG_TX_RING_BASE(qid), dma_addr);
+ airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), TX_RING_CPU_IDX_MASK,
+ FIELD_PREP(TX_RING_CPU_IDX_MASK, q->head));
+ airoha_qdma_rmw(qdma, REG_TX_DMA_IDX(qid), TX_RING_DMA_IDX_MASK,
+ FIELD_PREP(TX_RING_DMA_IDX_MASK, q->head));
+
+ return 0;
+}
+
+static int airoha_qdma_tx_irq_init(struct airoha_tx_irq_queue *irq_q,
+ struct airoha_qdma *qdma, int size)
+{
+ int id = irq_q - &qdma->q_tx_irq[0];
+ unsigned long dma_addr;
+
+ irq_q->q = dma_alloc_coherent(size * sizeof(u32), &dma_addr);
+ if (!irq_q->q)
+ return -ENOMEM;
+
+ memset(irq_q->q, 0xffffffff, size * sizeof(u32));
+ irq_q->size = size;
+ irq_q->qdma = qdma;
+
+ dma_map_single(irq_q->q, size * sizeof(u32), DMA_TO_DEVICE);
+
+ airoha_qdma_wr(qdma, REG_TX_IRQ_BASE(id), dma_addr);
+ airoha_qdma_rmw(qdma, REG_TX_IRQ_CFG(id), TX_IRQ_DEPTH_MASK,
+ FIELD_PREP(TX_IRQ_DEPTH_MASK, size));
+
+ return 0;
+}
+
+static int airoha_qdma_init_tx(struct airoha_qdma *qdma)
+{
+ int i, err;
+
+ for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) {
+ err = airoha_qdma_tx_irq_init(&qdma->q_tx_irq[i], qdma,
+ IRQ_QUEUE_LEN);
+ if (err)
+ return err;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) {
+ err = airoha_qdma_init_tx_queue(&qdma->q_tx[i], qdma,
+ TX_DSCP_NUM);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma)
+{
+ unsigned long dma_addr;
+ u32 status;
+ int size;
+
+ size = HW_DSCP_NUM * sizeof(struct airoha_qdma_fwd_desc);
+ qdma->hfwd.desc = dma_alloc_coherent(size, &dma_addr);
+ if (!qdma->hfwd.desc)
+ return -ENOMEM;
+
+ memset(qdma->hfwd.desc, 0, size);
+ dma_map_single(qdma->hfwd.desc, size, DMA_TO_DEVICE);
+
+ airoha_qdma_wr(qdma, REG_FWD_DSCP_BASE, dma_addr);
+
+ size = AIROHA_MAX_PACKET_SIZE * HW_DSCP_NUM;
+ qdma->hfwd.q = dma_alloc_coherent(size, &dma_addr);
+ if (!qdma->hfwd.q)
+ return -ENOMEM;
+
+ memset(qdma->hfwd.q, 0, size);
+ dma_map_single(qdma->hfwd.q, size, DMA_TO_DEVICE);
+
+ airoha_qdma_wr(qdma, REG_FWD_BUF_BASE, dma_addr);
+
+ airoha_qdma_rmw(qdma, REG_HW_FWD_DSCP_CFG,
+ HW_FWD_DSCP_PAYLOAD_SIZE_MASK |
+ HW_FWD_DSCP_MIN_SCATTER_LEN_MASK,
+ FIELD_PREP(HW_FWD_DSCP_PAYLOAD_SIZE_MASK, 0) |
+ FIELD_PREP(HW_FWD_DSCP_MIN_SCATTER_LEN_MASK, 1));
+ airoha_qdma_rmw(qdma, REG_LMGR_INIT_CFG,
+ LMGR_INIT_START | LMGR_SRAM_MODE_MASK |
+ HW_FWD_DESC_NUM_MASK,
+ FIELD_PREP(HW_FWD_DESC_NUM_MASK, HW_DSCP_NUM) |
+ LMGR_INIT_START);
+
+ udelay(1000);
+ return read_poll_timeout(airoha_qdma_rr, status,
+ !(status & LMGR_INIT_START), USEC_PER_MSEC,
+ 30 * USEC_PER_MSEC, qdma,
+ REG_LMGR_INIT_CFG);
+}
+
+static int airoha_qdma_hw_init(struct airoha_qdma *qdma)
+{
+ int i;
+
+ /* clear pending irqs */
+ for (i = 0; i < 2; i++)
+ airoha_qdma_wr(qdma, REG_INT_STATUS(i), 0xffffffff);
+
+ airoha_qdma_wr(qdma, REG_QDMA_GLOBAL_CFG,
+ GLOBAL_CFG_CPU_TXR_RR_MASK |
+ GLOBAL_CFG_PAYLOAD_BYTE_SWAP_MASK |
+ GLOBAL_CFG_IRQ0_EN_MASK |
+ GLOBAL_CFG_TX_WB_DONE_MASK |
+ FIELD_PREP(GLOBAL_CFG_MAX_ISSUE_NUM_MASK, 3));
+
+ /* disable qdma rx delay interrupt */
+ for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) {
+ if (!qdma->q_rx[i].ndesc)
+ continue;
+
+ airoha_qdma_clear(qdma, REG_RX_DELAY_INT_IDX(i),
+ RX_DELAY_INT_MASK);
+ }
+
+ return 0;
+}
+
+static int airoha_qdma_init(struct udevice *dev,
+ struct airoha_eth *eth,
+ struct airoha_qdma *qdma)
+{
+ int err;
+
+ qdma->eth = eth;
+ qdma->regs = dev_remap_addr_name(dev, "qdma0");
+ if (IS_ERR(qdma->regs))
+ return PTR_ERR(qdma->regs);
+
+ err = airoha_qdma_init_rx(qdma);
+ if (err)
+ return err;
+
+ err = airoha_qdma_init_tx(qdma);
+ if (err)
+ return err;
+
+ err = airoha_qdma_init_hfwd_queues(qdma);
+ if (err)
+ return err;
+
+ return airoha_qdma_hw_init(qdma);
+}
+
+static int airoha_hw_init(struct udevice *dev,
+ struct airoha_eth *eth)
+{
+ int ret, i;
+
+ /* disable xsi */
+ ret = reset_assert_bulk(ð->xsi_rsts);
+ if (ret)
+ return ret;
+
+ ret = reset_assert_bulk(ð->rsts);
+ if (ret)
+ return ret;
+
+ mdelay(20);
+
+ ret = reset_deassert_bulk(ð->rsts);
+ if (ret)
+ return ret;
+
+ mdelay(20);
+
+ ret = airoha_fe_init(eth);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) {
+ ret = airoha_qdma_init(dev, eth, ð->qdma[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int airoha_switch_init(struct udevice *dev, struct airoha_eth *eth)
+{
+ ofnode switch_node;
+ fdt_addr_t addr;
+
+ switch_node = ofnode_by_compatible(ofnode_null(), "airoha,en7581-switch");
+ if (!ofnode_valid(switch_node))
+ return -EINVAL;
+
+ addr = ofnode_get_addr(switch_node);
+ if (addr == FDT_ADDR_T_NONE)
+ return -ENOMEM;
+
+ /* Switch doesn't have a DEV, gets address and setup Flood and CPU port */
+ eth->switch_regs = map_sysmem(addr, 0);
+
+ /* Set FLOOD, no CPU switch register */
+ airoha_switch_wr(eth, SWITCH_MFC, SWITCH_BC_FFP | SWITCH_UNM_FFP |
+ SWITCH_UNU_FFP);
+
+ /* Set CPU 6 PMCR */
+ airoha_switch_wr(eth, SWITCH_PMCR(6),
+ SWITCH_IPG_CFG_SHORT | SWITCH_MAC_MODE |
+ SWITCH_FORCE_MODE | SWITCH_MAC_TX_EN |
+ SWITCH_MAC_RX_EN | SWITCH_BKOFF_EN | SWITCH_BKPR_EN |
+ SWITCH_FORCE_RX_FC | SWITCH_FORCE_TX_FC |
+ SWITCH_FORCE_SPD_1000 | SWITCH_FORCE_DPX |
+ SWITCH_FORCE_LNK);
+
+ /* Sideband signal error for Port 3, which need the auto polling */
+ airoha_switch_wr(eth, SWITCH_PHY_POLL,
+ FIELD_PREP(SWITCH_PHY_AP_EN, 0x7f) |
+ FIELD_PREP(SWITCH_EEE_POLL_EN, 0x7f) |
+ SWITCH_PHY_PRE_EN |
+ FIELD_PREP(SWITCH_PHY_END_ADDR, 0xc) |
+ FIELD_PREP(SWITCH_PHY_ST_ADDR, 0x8));
+
+ return 0;
+}
+
+static int airoha_eth_probe(struct udevice *dev)
+{
+ struct airoha_eth *eth = dev_get_priv(dev);
+ struct regmap *scu_regmap;
+ ofnode scu_node;
+ int ret;
+
+ scu_node = ofnode_by_compatible(ofnode_null(), "airoha,en7581-scu");
+ if (!ofnode_valid(scu_node))
+ return -EINVAL;
+
+ scu_regmap = syscon_node_to_regmap(scu_node);
+ if (IS_ERR(scu_regmap))
+ return PTR_ERR(scu_regmap);
+
+ /* It seems by default the FEMEM_SEL is set to Memory (0x1)
+ * preventing any access to any QDMA and FrameEngine register
+ * reporting all 0xdeadbeef (poor cow :( )
+ */
+ regmap_write(scu_regmap, SCU_SHARE_FEMEM_SEL, 0x0);
+
+ eth->fe_regs = dev_remap_addr_name(dev, "fe");
+ if (!eth->fe_regs)
+ return -ENOMEM;
+
+ eth->rsts.resets = devm_kcalloc(dev, AIROHA_MAX_NUM_RSTS,
+ sizeof(struct reset_ctl), GFP_KERNEL);
+ if (!eth->rsts.resets)
+ return -ENOMEM;
+ eth->rsts.count = AIROHA_MAX_NUM_RSTS;
+
+ eth->xsi_rsts.resets = devm_kcalloc(dev, AIROHA_MAX_NUM_XSI_RSTS,
+ sizeof(struct reset_ctl), GFP_KERNEL);
+ if (!eth->xsi_rsts.resets)
+ return -ENOMEM;
+ eth->xsi_rsts.count = AIROHA_MAX_NUM_XSI_RSTS;
+
+ ret = reset_get_by_name(dev, "fe", ð->rsts.resets[0]);
+ if (ret)
+ return ret;
+
+ ret = reset_get_by_name(dev, "pdma", ð->rsts.resets[1]);
+ if (ret)
+ return ret;
+
+ ret = reset_get_by_name(dev, "qdma", ð->rsts.resets[2]);
+ if (ret)
+ return ret;
+
+ ret = reset_get_by_name(dev, "hsi0-mac", ð->xsi_rsts.resets[0]);
+ if (ret)
+ return ret;
+
+ ret = reset_get_by_name(dev, "hsi1-mac", ð->xsi_rsts.resets[1]);
+ if (ret)
+ return ret;
+
+ ret = reset_get_by_name(dev, "hsi-mac", ð->xsi_rsts.resets[2]);
+ if (ret)
+ return ret;
+
+ ret = reset_get_by_name(dev, "xfp-mac", ð->xsi_rsts.resets[3]);
+ if (ret)
+ return ret;
+
+ ret = airoha_hw_init(dev, eth);
+ if (ret)
+ return ret;
+
+ return airoha_switch_init(dev, eth);
+}
+
+static int airoha_eth_init(struct udevice *dev)
+{
+ struct airoha_eth *eth = dev_get_priv(dev);
+ struct airoha_qdma *qdma = ð->qdma[0];
+ struct airoha_queue *q;
+ int qid;
+
+ qid = 0;
+ q = &qdma->q_rx[qid];
+
+ airoha_qdma_init_rx_desc(q);
+
+ airoha_qdma_set(qdma, REG_QDMA_GLOBAL_CFG,
+ GLOBAL_CFG_TX_DMA_EN_MASK |
+ GLOBAL_CFG_RX_DMA_EN_MASK);
+
+ return 0;
+}
+
+static void airoha_eth_stop(struct udevice *dev)
+{
+ struct airoha_eth *eth = dev_get_priv(dev);
+ struct airoha_qdma *qdma = ð->qdma[0];
+
+ airoha_qdma_clear(qdma, REG_QDMA_GLOBAL_CFG,
+ GLOBAL_CFG_TX_DMA_EN_MASK |
+ GLOBAL_CFG_RX_DMA_EN_MASK);
+}
+
+static int airoha_eth_send(struct udevice *dev, void *packet, int length)
+{
+ struct airoha_eth *eth = dev_get_priv(dev);
+ struct airoha_qdma *qdma = ð->qdma[0];
+ struct airoha_qdma_desc *desc;
+ struct airoha_queue *q;
+ dma_addr_t dma_addr;
+ u32 msg0, msg1;
+ int qid, index;
+ u8 fport;
+ u32 val;
+ int i;
+
+ dma_addr = dma_map_single(packet, length, DMA_TO_DEVICE);
+
+ qid = 0;
+ q = &qdma->q_tx[qid];
+ desc = &q->desc[q->head];
+ index = (q->head + 1) % q->ndesc;
+
+ fport = 1;
+
+ msg0 = 0;
+ msg1 = FIELD_PREP(QDMA_ETH_TXMSG_FPORT_MASK, fport) |
+ FIELD_PREP(QDMA_ETH_TXMSG_METER_MASK, 0x7f);
+
+ val = FIELD_PREP(QDMA_DESC_LEN_MASK, length);
+ WRITE_ONCE(desc->ctrl, cpu_to_le32(val));
+ WRITE_ONCE(desc->addr, cpu_to_le32(dma_addr));
+ val = FIELD_PREP(QDMA_DESC_NEXT_ID_MASK, index);
+ WRITE_ONCE(desc->data, cpu_to_le32(val));
+ WRITE_ONCE(desc->msg0, cpu_to_le32(msg0));
+ WRITE_ONCE(desc->msg1, cpu_to_le32(msg1));
+ WRITE_ONCE(desc->msg2, cpu_to_le32(0xffff));
+
+ dma_map_single(desc, sizeof(*desc), DMA_TO_DEVICE);
+
+ airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), TX_RING_CPU_IDX_MASK,
+ FIELD_PREP(TX_RING_CPU_IDX_MASK, index));
+
+ for (i = 0; i < 100; i++) {
+ dma_unmap_single(virt_to_phys(desc), sizeof(*desc),
+ DMA_FROM_DEVICE);
+ if (desc->ctrl & QDMA_DESC_DONE_MASK)
+ break;
+
+ udelay(1);
+ }
+
+ /* Return error if for some reason the descriptor never ACK */
+ if (!(desc->ctrl & QDMA_DESC_DONE_MASK))
+ return -EAGAIN;
+
+ q->head = index;
+ airoha_qdma_rmw(qdma, REG_IRQ_CLEAR_LEN(0),
+ IRQ_CLEAR_LEN_MASK, 1);
+
+ return 0;
+}
+
+static int airoha_eth_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct airoha_eth *eth = dev_get_priv(dev);
+ struct airoha_qdma *qdma = ð->qdma[0];
+ struct airoha_qdma_desc *desc;
+ struct airoha_queue *q;
+ u16 length;
+ int qid;
+
+ qid = 0;
+ q = &qdma->q_rx[qid];
+ desc = &q->desc[q->head];
+
+ dma_unmap_single(virt_to_phys(desc), sizeof(*desc),
+ DMA_FROM_DEVICE);
+
+ if (!(desc->ctrl & QDMA_DESC_DONE_MASK))
+ return -EAGAIN;
+
+ length = FIELD_GET(QDMA_DESC_LEN_MASK, desc->ctrl);
+ dma_unmap_single(desc->addr, length,
+ DMA_FROM_DEVICE);
+
+ *packetp = phys_to_virt(desc->addr);
+
+ return length;
+}
+
+static int arht_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+ struct airoha_eth *eth = dev_get_priv(dev);
+ struct airoha_qdma *qdma = ð->qdma[0];
+ struct airoha_queue *q;
+ int qid;
+
+ if (!packet)
+ return 0;
+
+ qid = 0;
+ q = &qdma->q_rx[qid];
+
+ dma_map_single(packet, length, DMA_TO_DEVICE);
+
+ airoha_qdma_reset_rx_desc(q, q->head, packet);
+
+ airoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid), RX_RING_CPU_IDX_MASK,
+ FIELD_PREP(RX_RING_CPU_IDX_MASK, q->head));
+ q->head = (q->head + 1) % q->ndesc;
+
+ return 0;
+}
+
+static int arht_eth_write_hwaddr(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct airoha_eth *eth = dev_get_priv(dev);
+ unsigned char *mac = pdata->enetaddr;
+ u32 macaddr_lsb, macaddr_msb;
+
+ macaddr_lsb = FIELD_PREP(SMACCR0_MAC2, mac[2]) |
+ FIELD_PREP(SMACCR0_MAC3, mac[3]) |
+ FIELD_PREP(SMACCR0_MAC4, mac[4]) |
+ FIELD_PREP(SMACCR0_MAC5, mac[5]);
+ macaddr_msb = FIELD_PREP(SMACCR1_MAC1, mac[1]) |
+ FIELD_PREP(SMACCR1_MAC0, mac[0]);
+
+ /* Set MAC for Switch */
+ airoha_switch_wr(eth, SWITCH_SMACCR0, macaddr_lsb);
+ airoha_switch_wr(eth, SWITCH_SMACCR1, macaddr_msb);
+
+ return 0;
+}
+
+static const struct udevice_id airoha_eth_ids[] = {
+ { .compatible = "airoha,en7581-eth" },
+};
+
+static const struct eth_ops airoha_eth_ops = {
+ .start = airoha_eth_init,
+ .stop = airoha_eth_stop,
+ .send = airoha_eth_send,
+ .recv = airoha_eth_recv,
+ .free_pkt = arht_eth_free_pkt,
+ .write_hwaddr = arht_eth_write_hwaddr,
+};
+
+U_BOOT_DRIVER(airoha_eth) = {
+ .name = "airoha-eth",
+ .id = UCLASS_ETH,
+ .of_match = airoha_eth_ids,
+ .probe = airoha_eth_probe,
+ .ops = &airoha_eth_ops,
+ .priv_auto = sizeof(struct airoha_eth),
+ .plat_auto = sizeof(struct eth_pdata),
+};
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index b4ec361..0cfe093 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1173,7 +1173,7 @@
eqos->config->ops->eqos_inval_buffer(packet, length);
- if ((eqos->rx_desc_idx & idx_mask) == idx_mask) {
+ if (eqos->started && (eqos->rx_desc_idx & idx_mask) == idx_mask) {
for (idx = eqos->rx_desc_idx - idx_mask;
idx <= eqos->rx_desc_idx;
idx++) {
@@ -1612,10 +1612,18 @@
#endif
#if IS_ENABLED(CONFIG_DWC_ETH_QOS_ROCKCHIP)
{
+ .compatible = "rockchip,rk3528-gmac",
+ .data = (ulong)&eqos_rockchip_config
+ },
+ {
.compatible = "rockchip,rk3568-gmac",
.data = (ulong)&eqos_rockchip_config
},
{
+ .compatible = "rockchip,rk3576-gmac",
+ .data = (ulong)&eqos_rockchip_config
+ },
+ {
.compatible = "rockchip,rk3588-gmac",
.data = (ulong)&eqos_rockchip_config
},
diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c
index f3a0f63..d646d3e 100644
--- a/drivers/net/dwc_eth_qos_rockchip.c
+++ b/drivers/net/dwc_eth_qos_rockchip.c
@@ -50,6 +50,132 @@
(((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
+#define RK3528_VO_GRF_GMAC_CON 0x0018
+#define RK3528_VPU_GRF_GMAC_CON5 0x0018
+#define RK3528_VPU_GRF_GMAC_CON6 0x001c
+
+#define RK3528_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
+#define RK3528_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
+#define RK3528_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
+#define RK3528_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
+
+#define RK3528_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8)
+#define RK3528_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0)
+
+#define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1)
+#define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8)
+#define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8)
+
+#define RK3528_GMAC1_CLK_SELECT_CRU GRF_CLR_BIT(12)
+#define RK3528_GMAC1_CLK_SELECT_IO GRF_BIT(12)
+
+#define RK3528_GMAC0_CLK_RMII_DIV2 GRF_BIT(3)
+#define RK3528_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(3)
+#define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10)
+#define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10)
+
+#define RK3528_GMAC1_CLK_RGMII_DIV1 (GRF_CLR_BIT(11) | GRF_CLR_BIT(10))
+#define RK3528_GMAC1_CLK_RGMII_DIV5 (GRF_BIT(11) | GRF_BIT(10))
+#define RK3528_GMAC1_CLK_RGMII_DIV50 (GRF_BIT(11) | GRF_CLR_BIT(10))
+
+#define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2)
+#define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2)
+#define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9)
+#define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9)
+
+static int rk3528_set_to_rgmii(struct udevice *dev,
+ int tx_delay, int rx_delay)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct rockchip_platform_data *data = pdata->priv_pdata;
+
+ regmap_write(data->grf, RK3528_VPU_GRF_GMAC_CON5,
+ RK3528_GMAC1_PHY_INTF_SEL_RGMII);
+
+ regmap_write(data->grf, RK3528_VPU_GRF_GMAC_CON5,
+ DELAY_ENABLE(RK3528, tx_delay, rx_delay));
+
+ regmap_write(data->grf, RK3528_VPU_GRF_GMAC_CON6,
+ RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) |
+ RK3528_GMAC_CLK_TX_DL_CFG(tx_delay));
+
+ return 0;
+}
+
+static int rk3528_set_to_rmii(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct rockchip_platform_data *data = pdata->priv_pdata;
+
+ if (data->id == 1)
+ regmap_write(data->grf, RK3528_VPU_GRF_GMAC_CON5,
+ RK3528_GMAC1_PHY_INTF_SEL_RMII);
+ else
+ regmap_write(data->grf, RK3528_VO_GRF_GMAC_CON,
+ RK3528_GMAC0_PHY_INTF_SEL_RMII |
+ RK3528_GMAC0_CLK_RMII_DIV2);
+
+ return 0;
+}
+
+static int rk3528_set_gmac_speed(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct rockchip_platform_data *data = pdata->priv_pdata;
+ u32 val, reg;
+
+ switch (eqos->phy->speed) {
+ case SPEED_10:
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
+ val = data->id == 1 ? RK3528_GMAC1_CLK_RMII_DIV20 :
+ RK3528_GMAC0_CLK_RMII_DIV20;
+ else
+ val = RK3528_GMAC1_CLK_RGMII_DIV50;
+ break;
+ case SPEED_100:
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
+ val = data->id == 1 ? RK3528_GMAC1_CLK_RMII_DIV2 :
+ RK3528_GMAC0_CLK_RMII_DIV2;
+ else
+ val = RK3528_GMAC1_CLK_RGMII_DIV5;
+ break;
+ case SPEED_1000:
+ if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII)
+ val = RK3528_GMAC1_CLK_RGMII_DIV1;
+ else
+ return -EINVAL;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ reg = data->id == 1 ? RK3528_VPU_GRF_GMAC_CON5 :
+ RK3528_VO_GRF_GMAC_CON;
+ regmap_write(data->grf, reg, val);
+
+ return 0;
+}
+
+static void rk3528_set_clock_selection(struct udevice *dev, bool enable)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct rockchip_platform_data *data = pdata->priv_pdata;
+ u32 val;
+
+ if (data->id == 1) {
+ val = data->clock_input ? RK3528_GMAC1_CLK_SELECT_IO :
+ RK3528_GMAC1_CLK_SELECT_CRU;
+ val |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE :
+ RK3528_GMAC1_CLK_RMII_GATE;
+ regmap_write(data->grf, RK3528_VPU_GRF_GMAC_CON5, val);
+ } else {
+ val = enable ? RK3528_GMAC0_CLK_RMII_NOGATE :
+ RK3528_GMAC0_CLK_RMII_GATE;
+ regmap_write(data->grf, RK3528_VO_GRF_GMAC_CON, val);
+ }
+}
+
#define RK3568_GRF_GMAC0_CON0 0x0380
#define RK3568_GRF_GMAC0_CON1 0x0384
#define RK3568_GRF_GMAC1_CON0 0x0388
@@ -134,6 +260,145 @@
return 0;
}
+/* VCCIO0_1_3_IOC */
+#define RK3576_VCCIO0_1_3_IOC_CON2 0x6408
+#define RK3576_VCCIO0_1_3_IOC_CON3 0x640c
+#define RK3576_VCCIO0_1_3_IOC_CON4 0x6410
+#define RK3576_VCCIO0_1_3_IOC_CON5 0x6414
+
+#define RK3576_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
+#define RK3576_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
+#define RK3576_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
+#define RK3576_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
+
+#define RK3576_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
+#define RK3576_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+
+/* SDGMAC_GRF */
+#define RK3576_GRF_GMAC_CON0 0x0020
+#define RK3576_GRF_GMAC_CON1 0x0024
+
+#define RK3576_GMAC_RMII_MODE GRF_BIT(3)
+#define RK3576_GMAC_RGMII_MODE GRF_CLR_BIT(3)
+
+#define RK3576_GMAC_CLK_SELECT_IO GRF_BIT(7)
+#define RK3576_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(7)
+
+#define RK3576_GMAC_CLK_RMII_DIV2 GRF_BIT(5)
+#define RK3576_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(5)
+
+#define RK3576_GMAC_CLK_RGMII_DIV1 \
+ (GRF_CLR_BIT(6) | GRF_CLR_BIT(5))
+#define RK3576_GMAC_CLK_RGMII_DIV5 \
+ (GRF_BIT(6) | GRF_BIT(5))
+#define RK3576_GMAC_CLK_RGMII_DIV50 \
+ (GRF_BIT(6) | GRF_CLR_BIT(5))
+
+#define RK3576_GMAC_CLK_RMII_GATE GRF_BIT(4)
+#define RK3576_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(4)
+
+static int rk3576_set_to_rgmii(struct udevice *dev,
+ int tx_delay, int rx_delay)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct rockchip_platform_data *data = pdata->priv_pdata;
+ u32 offset_con;
+
+ offset_con = data->id == 1 ? RK3576_GRF_GMAC_CON1 :
+ RK3576_GRF_GMAC_CON0;
+
+ regmap_write(data->grf, offset_con, RK3576_GMAC_RGMII_MODE);
+
+ offset_con = data->id == 1 ? RK3576_VCCIO0_1_3_IOC_CON4 :
+ RK3576_VCCIO0_1_3_IOC_CON2;
+
+ /* m0 && m1 delay enabled */
+ regmap_write(data->php_grf, offset_con,
+ DELAY_ENABLE(RK3576, tx_delay, rx_delay));
+ regmap_write(data->php_grf, offset_con + 0x4,
+ DELAY_ENABLE(RK3576, tx_delay, rx_delay));
+
+ /* m0 && m1 delay value */
+ regmap_write(data->php_grf, offset_con,
+ RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) |
+ RK3576_GMAC_CLK_RX_DL_CFG(rx_delay));
+ regmap_write(data->php_grf, offset_con + 0x4,
+ RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) |
+ RK3576_GMAC_CLK_RX_DL_CFG(rx_delay));
+
+ return 0;
+}
+
+static int rk3576_set_to_rmii(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct rockchip_platform_data *data = pdata->priv_pdata;
+ u32 offset_con;
+
+ offset_con = data->id == 1 ? RK3576_GRF_GMAC_CON1 :
+ RK3576_GRF_GMAC_CON0;
+
+ regmap_write(data->grf, offset_con, RK3576_GMAC_RMII_MODE);
+
+ return 0;
+}
+
+static int rk3576_set_gmac_speed(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct rockchip_platform_data *data = pdata->priv_pdata;
+ u32 val = 0, offset_con;
+
+ switch (eqos->phy->speed) {
+ case SPEED_10:
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
+ val = RK3576_GMAC_CLK_RMII_DIV20;
+ else
+ val = RK3576_GMAC_CLK_RGMII_DIV50;
+ break;
+ case SPEED_100:
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
+ val = RK3576_GMAC_CLK_RMII_DIV2;
+ else
+ val = RK3576_GMAC_CLK_RGMII_DIV5;
+ break;
+ case SPEED_1000:
+ if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII)
+ val = RK3576_GMAC_CLK_RGMII_DIV1;
+ else
+ return -EINVAL;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ offset_con = data->id == 1 ? RK3576_GRF_GMAC_CON1 :
+ RK3576_GRF_GMAC_CON0;
+
+ regmap_write(data->grf, offset_con, val);
+
+ return 0;
+}
+
+static void rk3576_set_clock_selection(struct udevice *dev, bool enable)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct rockchip_platform_data *data = pdata->priv_pdata;
+
+ u32 val = data->clock_input ? RK3576_GMAC_CLK_SELECT_IO :
+ RK3576_GMAC_CLK_SELECT_CRU;
+ u32 offset_con;
+
+ val |= enable ? RK3576_GMAC_CLK_RMII_NOGATE :
+ RK3576_GMAC_CLK_RMII_GATE;
+
+ offset_con = data->id == 1 ? RK3576_GRF_GMAC_CON1 :
+ RK3576_GRF_GMAC_CON0;
+
+ regmap_write(data->grf, offset_con, val);
+}
+
#define RK3588_DELAY_ENABLE(id, tx, rx) \
(((tx) ? RK3588_GMAC_TXCLK_DLY_ENABLE(id) : RK3588_GMAC_TXCLK_DLY_DISABLE(id)) | \
((rx) ? RK3588_GMAC_RXCLK_DLY_ENABLE(id) : RK3588_GMAC_RXCLK_DLY_DISABLE(id)))
@@ -270,6 +535,18 @@
static const struct rk_gmac_ops rk_gmac_ops[] = {
{
+ .compatible = "rockchip,rk3528-gmac",
+ .set_to_rgmii = rk3528_set_to_rgmii,
+ .set_to_rmii = rk3528_set_to_rmii,
+ .set_gmac_speed = rk3528_set_gmac_speed,
+ .set_clock_selection = rk3528_set_clock_selection,
+ .regs = {
+ 0xffbd0000, /* gmac0 */
+ 0xffbe0000, /* gmac1 */
+ 0x0, /* sentinel */
+ },
+ },
+ {
.compatible = "rockchip,rk3568-gmac",
.set_to_rgmii = rk3568_set_to_rgmii,
.set_to_rmii = rk3568_set_to_rmii,
@@ -281,6 +558,18 @@
},
},
{
+ .compatible = "rockchip,rk3576-gmac",
+ .set_to_rgmii = rk3576_set_to_rgmii,
+ .set_to_rmii = rk3576_set_to_rmii,
+ .set_gmac_speed = rk3576_set_gmac_speed,
+ .set_clock_selection = rk3576_set_clock_selection,
+ .regs = {
+ 0x2a220000, /* gmac0 */
+ 0x2a230000, /* gmac1 */
+ 0x0, /* sentinel */
+ },
+ },
+ {
.compatible = "rockchip,rk3588-gmac",
.set_to_rgmii = rk3588_set_to_rgmii,
.set_to_rmii = rk3588_set_to_rmii,
@@ -357,7 +646,8 @@
goto err_free;
}
- if (device_is_compatible(dev, "rockchip,rk3588-gmac")) {
+ if (device_is_compatible(dev, "rockchip,rk3588-gmac") ||
+ device_is_compatible(dev, "rockchip,rk3576-gmac")) {
data->php_grf =
syscon_regmap_lookup_by_phandle(dev, "rockchip,php-grf");
if (IS_ERR(data->php_grf)) {
diff --git a/drivers/net/sandbox-lwip.c b/drivers/net/sandbox-lwip.c
deleted file mode 100644
index 3721033..0000000
--- a/drivers/net/sandbox-lwip.c
+++ /dev/null
@@ -1,85 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2015 National Instruments
- *
- * (C) Copyright 2015
- * Joe Hershberger <joe.hershberger@ni.com>
- */
-
-#include <dm.h>
-#include <log.h>
-#include <malloc.h>
-#include <net.h>
-#include <asm/eth.h>
-#include <asm/global_data.h>
-#include <asm/test.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int sb_lwip_eth_start(struct udevice *dev)
-{
- debug("eth_sandbox_lwip: Start\n");
-
- return 0;
-}
-
-static int sb_lwip_eth_send(struct udevice *dev, void *packet, int length)
-{
- debug("eth_sandbox_lwip: Send packet %d\n", length);
-
- return -ENOTSUPP;
-}
-
-static int sb_lwip_eth_recv(struct udevice *dev, int flags, uchar **packetp)
-{
- return -EAGAIN;
-}
-
-static int sb_lwip_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
-{
- return 0;
-}
-
-static void sb_lwip_eth_stop(struct udevice *dev)
-{
-}
-
-static int sb_lwip_eth_write_hwaddr(struct udevice *dev)
-{
- return 0;
-}
-
-static const struct eth_ops sb_eth_ops = {
- .start = sb_lwip_eth_start,
- .send = sb_lwip_eth_send,
- .recv = sb_lwip_eth_recv,
- .free_pkt = sb_lwip_eth_free_pkt,
- .stop = sb_lwip_eth_stop,
- .write_hwaddr = sb_lwip_eth_write_hwaddr,
-};
-
-static int sb_lwip_eth_remove(struct udevice *dev)
-{
- return 0;
-}
-
-static int sb_lwip_eth_of_to_plat(struct udevice *dev)
-{
- return 0;
-}
-
-static const struct udevice_id sb_eth_ids[] = {
- { .compatible = "sandbox,eth" },
- { }
-};
-
-U_BOOT_DRIVER(eth_sandbox) = {
- .name = "eth_lwip_sandbox",
- .id = UCLASS_ETH,
- .of_match = sb_eth_ids,
- .of_to_plat = sb_lwip_eth_of_to_plat,
- .remove = sb_lwip_eth_remove,
- .ops = &sb_eth_ops,
- .priv_auto = 0,
- .plat_auto = sizeof(struct eth_pdata),
-};
diff --git a/drivers/net/sandbox.c b/drivers/net/sandbox.c
index fe3627d..2011fd3 100644
--- a/drivers/net/sandbox.c
+++ b/drivers/net/sandbox.c
@@ -9,13 +9,84 @@
#include <dm.h>
#include <log.h>
#include <malloc.h>
-#include <net.h>
#include <asm/eth.h>
#include <asm/global_data.h>
#include <asm/test.h>
+#include <asm/types.h>
+
+/*
+ * Structure definitions for network protocols. Since this file is used for
+ * both NET and NET_LWIP, and given that the two network stacks do have
+ * conflicting types (for instance struct icmp_hdr), it is on purpose that the
+ * structures are defined locally with minimal dependencies -- <asm/types.h> is
+ * included for the bit types and that's it.
+ */
+
+#define ETHADDR_LEN 6
+#define IP4_LEN 4
+
+struct ethhdr {
+ u8 dst[ETHADDR_LEN];
+ u8 src[ETHADDR_LEN];
+ u16 protlen;
+} __attribute__((packed));
+
+#define ETHHDR_SIZE (sizeof(struct ethhdr))
+
+struct arphdr {
+ u16 htype;
+ u16 ptype;
+ u8 hlen;
+ u8 plen;
+ u16 op;
+} __attribute__((packed));
+
+#define ARPHDR_SIZE (sizeof(struct arphdr))
+
+#define ARP_REQUEST 1
+#define ARP_REPLY 2
+
+struct arpdata {
+ u8 sha[ETHADDR_LEN];
+ u32 spa;
+ u8 tha[ETHADDR_LEN];
+ u32 tpa;
+} __attribute__((packed));
+
+#define ARPDATA_SIZE (sizeof(struct arpdata))
+
+struct iphdr {
+ u8 hl_v;
+ u8 tos;
+ u16 len;
+ u16 id;
+ u16 off;
+ u8 ttl;
+ u8 prot;
+ u16 sum;
+ u32 src;
+ u32 dst;
+} __attribute__((packed));
+
+#define IPHDR_SIZE (sizeof(struct iphdr))
+
+struct icmphdr {
+ u8 type;
+ u8 code;
+ u16 checksum;
+ u16 id;
+ u16 sequence;
+} __attribute__((packed));
+
+#define ICMPHDR_SIZE (sizeof(struct icmphdr))
+
+#define ICMP_ECHO_REQUEST 8
+#define ICMP_ECHO_REPLY 0
+#define IPPROTO_ICMP 1
DECLARE_GLOBAL_DATA_PTR;
+static const u8 null_ethaddr[6];
static bool skip_timeout;
/*
@@ -59,17 +130,19 @@
unsigned int len)
{
struct eth_sandbox_priv *priv = dev_get_priv(dev);
- struct ethernet_hdr *eth = packet;
- struct arp_hdr *arp;
- struct ethernet_hdr *eth_recv;
- struct arp_hdr *arp_recv;
+ struct ethhdr *eth = packet;
+ struct arphdr *arp;
+ struct arpdata *arpd;
+ struct ethhdr *eth_recv;
+ struct arphdr *arp_recv;
+ struct arpdata *arp_recvd;
- if (ntohs(eth->et_protlen) != PROT_ARP)
+ if (ntohs(eth->protlen) != PROT_ARP)
return -EAGAIN;
- arp = packet + ETHER_HDR_SIZE;
+ arp = packet + ETHHDR_SIZE;
- if (ntohs(arp->ar_op) != ARPOP_REQUEST)
+ if (ntohs(arp->op) != ARP_REQUEST)
return -EAGAIN;
/* Don't allow the buffer to overrun */
@@ -77,27 +150,29 @@
return 0;
/* store this as the assumed IP of the fake host */
- priv->fake_host_ipaddr = net_read_ip(&arp->ar_tpa);
+ arpd = (struct arpdata *)(arp + 1);
+ priv->fake_host_ipaddr.s_addr = arpd->tpa;
/* Formulate a fake response */
eth_recv = (void *)priv->recv_packet_buffer[priv->recv_packets];
- memcpy(eth_recv->et_dest, eth->et_src, ARP_HLEN);
- memcpy(eth_recv->et_src, priv->fake_host_hwaddr, ARP_HLEN);
- eth_recv->et_protlen = htons(PROT_ARP);
+ memcpy(eth_recv->dst, eth->src, ETHADDR_LEN);
+ memcpy(eth_recv->src, priv->fake_host_hwaddr, ETHADDR_LEN);
+ eth_recv->protlen = htons(PROT_ARP);
- arp_recv = (void *)eth_recv + ETHER_HDR_SIZE;
- arp_recv->ar_hrd = htons(ARP_ETHER);
- arp_recv->ar_pro = htons(PROT_IP);
- arp_recv->ar_hln = ARP_HLEN;
- arp_recv->ar_pln = ARP_PLEN;
- arp_recv->ar_op = htons(ARPOP_REPLY);
- memcpy(&arp_recv->ar_sha, priv->fake_host_hwaddr, ARP_HLEN);
- net_write_ip(&arp_recv->ar_spa, priv->fake_host_ipaddr);
- memcpy(&arp_recv->ar_tha, &arp->ar_sha, ARP_HLEN);
- net_copy_ip(&arp_recv->ar_tpa, &arp->ar_spa);
+ arp_recv = (void *)eth_recv + ETHHDR_SIZE;
+ arp_recv->htype = htons(ARP_ETHER);
+ arp_recv->ptype = htons(PROT_IP);
+ arp_recv->hlen = ETHADDR_LEN;
+ arp_recv->plen = IP4_LEN;
+ arp_recv->op = htons(ARP_REPLY);
+ arp_recvd = (struct arpdata *)(arp_recv + 1);
+ memcpy(&arp_recvd->sha, priv->fake_host_hwaddr, ETHADDR_LEN);
+ arp_recvd->spa = priv->fake_host_ipaddr.s_addr;
+ memcpy(&arp_recvd->tha, &arpd->sha, ETHADDR_LEN);
+ arp_recvd->tpa = arpd->spa;
- priv->recv_packet_length[priv->recv_packets] =
- ETHER_HDR_SIZE + ARP_HDR_SIZE;
+ priv->recv_packet_length[priv->recv_packets] = ETHHDR_SIZE +
+ ARPHDR_SIZE + ARPDATA_SIZE;
++priv->recv_packets;
return 0;
@@ -114,22 +189,22 @@
unsigned int len)
{
struct eth_sandbox_priv *priv = dev_get_priv(dev);
- struct ethernet_hdr *eth = packet;
- struct ip_udp_hdr *ip;
- struct icmp_hdr *icmp;
- struct ethernet_hdr *eth_recv;
- struct ip_udp_hdr *ipr;
- struct icmp_hdr *icmpr;
+ struct ethhdr *eth = packet;
+ struct iphdr *ip;
+ struct icmphdr *icmp;
+ struct ethhdr *eth_recv;
+ struct iphdr *ipr;
+ struct icmphdr *icmpr;
- if (ntohs(eth->et_protlen) != PROT_IP)
+ if (ntohs(eth->protlen) != PROT_IP)
return -EAGAIN;
- ip = packet + ETHER_HDR_SIZE;
+ ip = packet + ETHHDR_SIZE;
- if (ip->ip_p != IPPROTO_ICMP)
+ if (ip->prot != IPPROTO_ICMP)
return -EAGAIN;
- icmp = (struct icmp_hdr *)&ip->udp_src;
+ icmp = (struct icmphdr *)(ip + 1);
if (icmp->type != ICMP_ECHO_REQUEST)
return -EAGAIN;
@@ -141,19 +216,19 @@
/* reply to the ping */
eth_recv = (void *)priv->recv_packet_buffer[priv->recv_packets];
memcpy(eth_recv, packet, len);
- ipr = (void *)eth_recv + ETHER_HDR_SIZE;
- icmpr = (struct icmp_hdr *)&ipr->udp_src;
- memcpy(eth_recv->et_dest, eth->et_src, ARP_HLEN);
- memcpy(eth_recv->et_src, priv->fake_host_hwaddr, ARP_HLEN);
- ipr->ip_sum = 0;
- ipr->ip_off = 0;
- net_copy_ip((void *)&ipr->ip_dst, &ip->ip_src);
- net_write_ip((void *)&ipr->ip_src, priv->fake_host_ipaddr);
- ipr->ip_sum = compute_ip_checksum(ipr, IP_HDR_SIZE);
+ ipr = (void *)eth_recv + ETHHDR_SIZE;
+ icmpr = (struct icmphdr *)(ipr + 1);
+ memcpy(eth_recv->dst, eth->src, ETHADDR_LEN);
+ memcpy(eth_recv->src, priv->fake_host_hwaddr, ETHADDR_LEN);
+ ipr->sum = 0;
+ ipr->off = 0;
+ ipr->dst = ip->src;
+ ipr->src = priv->fake_host_ipaddr.s_addr;
+ ipr->sum = compute_ip_checksum(ipr, IPHDR_SIZE);
icmpr->type = ICMP_ECHO_REPLY;
icmpr->checksum = 0;
- icmpr->checksum = compute_ip_checksum(icmpr, ICMP_HDR_SIZE);
+ icmpr->checksum = compute_ip_checksum(icmpr, ICMPHDR_SIZE);
priv->recv_packet_length[priv->recv_packets] = len;
++priv->recv_packets;
@@ -171,8 +246,9 @@
int sandbox_eth_recv_arp_req(struct udevice *dev)
{
struct eth_sandbox_priv *priv = dev_get_priv(dev);
- struct ethernet_hdr *eth_recv;
- struct arp_hdr *arp_recv;
+ struct ethhdr *eth_recv;
+ struct arphdr *arp_recv;
+ struct arpdata *arp_recvd;
/* Don't allow the buffer to overrun */
if (priv->recv_packets >= PKTBUFSRX)
@@ -180,23 +256,24 @@
/* Formulate a fake request */
eth_recv = (void *)priv->recv_packet_buffer[priv->recv_packets];
- memcpy(eth_recv->et_dest, net_bcast_ethaddr, ARP_HLEN);
- memcpy(eth_recv->et_src, priv->fake_host_hwaddr, ARP_HLEN);
- eth_recv->et_protlen = htons(PROT_ARP);
+ memcpy(eth_recv->dst, net_bcast_ethaddr, ETHADDR_LEN);
+ memcpy(eth_recv->src, priv->fake_host_hwaddr, ETHADDR_LEN);
+ eth_recv->protlen = htons(PROT_ARP);
- arp_recv = (void *)eth_recv + ETHER_HDR_SIZE;
- arp_recv->ar_hrd = htons(ARP_ETHER);
- arp_recv->ar_pro = htons(PROT_IP);
- arp_recv->ar_hln = ARP_HLEN;
- arp_recv->ar_pln = ARP_PLEN;
- arp_recv->ar_op = htons(ARPOP_REQUEST);
- memcpy(&arp_recv->ar_sha, priv->fake_host_hwaddr, ARP_HLEN);
- net_write_ip(&arp_recv->ar_spa, priv->fake_host_ipaddr);
- memcpy(&arp_recv->ar_tha, net_null_ethaddr, ARP_HLEN);
- net_write_ip(&arp_recv->ar_tpa, net_ip);
+ arp_recv = (void *)eth_recv + ETHHDR_SIZE;
+ arp_recv->htype = htons(ARP_ETHER);
+ arp_recv->ptype = htons(PROT_IP);
+ arp_recv->hlen = ETHADDR_LEN;
+ arp_recv->plen = IP4_LEN;
+ arp_recv->op = htons(ARP_REQUEST);
+ arp_recvd = (struct arpdata *)(arp_recv + 1);
+ memcpy(&arp_recvd->sha, priv->fake_host_hwaddr, ETHADDR_LEN);
+ arp_recvd->spa = priv->fake_host_ipaddr.s_addr;
+ memcpy(&arp_recvd->tha, null_ethaddr, ETHADDR_LEN);
+ arp_recvd->tpa = net_ip.s_addr;
priv->recv_packet_length[priv->recv_packets] =
- ETHER_HDR_SIZE + ARP_HDR_SIZE;
+ ETHHDR_SIZE + ARPHDR_SIZE + ARPDATA_SIZE;
++priv->recv_packets;
return 0;
@@ -212,9 +289,10 @@
int sandbox_eth_recv_ping_req(struct udevice *dev)
{
struct eth_sandbox_priv *priv = dev_get_priv(dev);
- struct ethernet_hdr *eth_recv;
- struct ip_udp_hdr *ipr;
- struct icmp_hdr *icmpr;
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct ethhdr *eth_recv;
+ struct iphdr *ipr;
+ struct icmphdr *icmpr;
/* Don't allow the buffer to overrun */
if (priv->recv_packets >= PKTBUFSRX)
@@ -223,31 +301,31 @@
/* Formulate a fake ping */
eth_recv = (void *)priv->recv_packet_buffer[priv->recv_packets];
- memcpy(eth_recv->et_dest, net_ethaddr, ARP_HLEN);
- memcpy(eth_recv->et_src, priv->fake_host_hwaddr, ARP_HLEN);
- eth_recv->et_protlen = htons(PROT_IP);
+ memcpy(eth_recv->dst, pdata->enetaddr, ETHADDR_LEN);
+ memcpy(eth_recv->src, priv->fake_host_hwaddr, ETHADDR_LEN);
+ eth_recv->protlen = htons(PROT_IP);
- ipr = (void *)eth_recv + ETHER_HDR_SIZE;
- ipr->ip_hl_v = 0x45;
- ipr->ip_len = htons(IP_ICMP_HDR_SIZE);
- ipr->ip_off = htons(IP_FLAGS_DFRAG);
- ipr->ip_p = IPPROTO_ICMP;
- ipr->ip_sum = 0;
- net_write_ip(&ipr->ip_src, priv->fake_host_ipaddr);
- net_write_ip(&ipr->ip_dst, net_ip);
- ipr->ip_sum = compute_ip_checksum(ipr, IP_HDR_SIZE);
+ ipr = (void *)eth_recv + ETHHDR_SIZE;
+ ipr->hl_v = 0x45;
+ ipr->len = htons(IPHDR_SIZE + ICMPHDR_SIZE);
+ ipr->off = htons(IP_FLAGS_DFRAG);
+ ipr->prot = IPPROTO_ICMP;
+ ipr->sum = 0;
+ ipr->src = priv->fake_host_ipaddr.s_addr;
+ ipr->dst = net_ip.s_addr;
+ ipr->sum = compute_ip_checksum(ipr, IPHDR_SIZE);
- icmpr = (struct icmp_hdr *)&ipr->udp_src;
+ icmpr = (struct icmphdr *)(ipr + 1);
icmpr->type = ICMP_ECHO_REQUEST;
icmpr->code = 0;
icmpr->checksum = 0;
- icmpr->un.echo.id = 0;
- icmpr->un.echo.sequence = htons(1);
- icmpr->checksum = compute_ip_checksum(icmpr, ICMP_HDR_SIZE);
+ icmpr->id = 0;
+ icmpr->sequence = htons(1);
+ icmpr->checksum = compute_ip_checksum(icmpr, ICMPHDR_SIZE);
priv->recv_packet_length[priv->recv_packets] =
- ETHER_HDR_SIZE + IP_ICMP_HDR_SIZE;
+ ETHHDR_SIZE + IPHDR_SIZE + ICMPHDR_SIZE;
++priv->recv_packets;
return 0;
@@ -398,7 +476,7 @@
debug("eth_sandbox %s: Write HW ADDR - %pM\n", dev->name,
pdata->enetaddr);
- memcpy(priv->fake_host_hwaddr, pdata->enetaddr, ARP_HLEN);
+ memcpy(priv->fake_host_hwaddr, pdata->enetaddr, ETHADDR_LEN);
return 0;
}
diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
index 3c62fc0..9b69f36 100644
--- a/drivers/net/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ti/am65-cpsw-nuss.c
@@ -438,6 +438,12 @@
port->port_sgmii_base + AM65_CPSW_SGMII_CONTROL_REG);
}
+ ret = phy_config(priv->phydev);
+ if (ret < 0) {
+ dev_err(dev, "phy_config failed: %d", ret);
+ goto err_dis_rx;
+ }
+
ret = phy_startup(priv->phydev);
if (ret) {
dev_err(dev, "phy_startup failed\n");
@@ -639,9 +645,6 @@
phydev->advertising = phydev->supported;
priv->phydev = phydev;
- ret = phy_config(phydev);
- if (ret < 0)
- dev_err(dev, "phy_config() failed: %d", ret);
return ret;
}
diff --git a/drivers/nvme/Makefile b/drivers/nvme/Makefile
index 8c32cfb..5f8ed79 100644
--- a/drivers/nvme/Makefile
+++ b/drivers/nvme/Makefile
@@ -4,4 +4,4 @@
obj-y += nvme-uclass.o nvme.o nvme_show.o
obj-$(CONFIG_NVME_APPLE) += nvme_apple.o
-obj-$(CONFIG_$(XPL_)NVME_PCI) += nvme_pci.o
+obj-$(CONFIG_$(PHASE_)NVME_PCI) += nvme_pci.o
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 4f876d3..4090491 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -67,6 +67,7 @@
config PCI_MAP_SYSTEM_MEMORY
bool "Map local system memory from a virtual base address"
depends on MIPS
+ default y if !ARCH_MAP_SYSMEM
help
Say Y if base address of system memory is being used as a virtual address
instead of a physical address (e.g. on MIPS). The PCI core will then remap
@@ -75,6 +76,15 @@
This should only be required on MIPS where CFG_SYS_SDRAM_BASE is still
being used as virtual address.
+config PCI_BRIDGE_MEM_ALIGNMENT
+ hex "Alignment boundary of PCI memory resource allocation"
+ default 0x10000 if TARGET_BOSTON
+ default 0x100000
+ help
+ Specify a boundary for alignment of PCI memory resource allocation,
+ this is normally 0x100000 (1MB) but can be reduced to accommodate
+ hardware with tight bridge range if hardware allows.
+
config PCI_SRIOV
bool "Enable Single Root I/O Virtualization support for PCI"
help
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index e68e31a..4a1c782 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -373,8 +373,8 @@
dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff);
if (pci_mem) {
- /* Round memory allocator to 1MB boundary */
- pciauto_region_align(pci_mem, 0x100000);
+ /* Round memory allocator */
+ pciauto_region_align(pci_mem, CONFIG_PCI_BRIDGE_MEM_ALIGNMENT);
/*
* Set up memory and I/O filter limits, assume 32-bit
@@ -388,8 +388,8 @@
}
if (pci_prefetch) {
- /* Round memory allocator to 1MB boundary */
- pciauto_region_align(pci_prefetch, 0x100000);
+ /* Round memory allocator */
+ pciauto_region_align(pci_prefetch, CONFIG_PCI_BRIDGE_MEM_ALIGNMENT);
/*
* Set up memory and I/O filter limits, assume 32-bit
@@ -466,8 +466,8 @@
dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus - dev_seq(ctlr));
if (pci_mem) {
- /* Round memory allocator to 1MB boundary */
- pciauto_region_align(pci_mem, 0x100000);
+ /* Round memory allocator */
+ pciauto_region_align(pci_mem, CONFIG_PCI_BRIDGE_MEM_ALIGNMENT);
dm_pci_write_config16(dev, PCI_MEMORY_LIMIT,
((pci_mem->bus_lower - 1) >> 16) &
@@ -481,8 +481,8 @@
&prefechable_64);
prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
- /* Round memory allocator to 1MB boundary */
- pciauto_region_align(pci_prefetch, 0x100000);
+ /* Round memory allocator */
+ pciauto_region_align(pci_prefetch, CONFIG_PCI_BRIDGE_MEM_ALIGNMENT);
dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT,
(((pci_prefetch->bus_lower - 1) >> 16) &
diff --git a/drivers/pci/pcie_cdns_ti.c b/drivers/pci/pcie_cdns_ti.c
index 41469a1..9d1d123 100644
--- a/drivers/pci/pcie_cdns_ti.c
+++ b/drivers/pci/pcie_cdns_ti.c
@@ -19,6 +19,7 @@
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/log2.h>
+#include <linux/sizes.h>
#include <power-domain.h>
#include <regmap.h>
#include <syscon.h>
@@ -834,11 +835,21 @@
.max_lanes = 2,
};
+static const struct pcie_cdns_ti_data am64_pcie_rc_data = {
+ .mode = PCIE_MODE_RC,
+ .quirk_detect_quiet_flag = true,
+ .max_lanes = 1,
+};
+
static const struct udevice_id pcie_cdns_ti_ids[] = {
{
.compatible = "ti,j7200-pcie-host",
.data = (ulong)&j7200_pcie_rc_data,
},
+ {
+ .compatible = "ti,am64-pcie-host",
+ .data = (ulong)&am64_pcie_rc_data,
+ },
{},
};
diff --git a/drivers/pci/pcie_xilinx.c b/drivers/pci/pcie_xilinx.c
index a674ab0..63058e8 100644
--- a/drivers/pci/pcie_xilinx.c
+++ b/drivers/pci/pcie_xilinx.c
@@ -18,14 +18,19 @@
*/
struct xilinx_pcie {
void *cfg_base;
+ pci_size_t size;
+ int first_busno;
};
/* Register definitions */
-#define XILINX_PCIE_REG_PSCR 0x144
-#define XILINX_PCIE_REG_PSCR_LNKUP BIT(11)
-#define XILINX_PCIE_REG_RPSC 0x148
-#define XILINX_PCIE_REG_RPSC_BEN BIT(0)
-
+#define XILINX_PCIE_REG_BRIDGE_INFO 0x130
+#define XILINX_PCIE_REG_BRIDGE_INFO_ECAMSZ_SHIFT 16
+#define XILINX_PCIE_REG_BRIDGE_INFO_ECAMSZ_MASK (0x7 << 16)
+#define XILINX_PCIE_REG_INT_MASK 0x13c
+#define XILINX_PCIE_REG_PSCR 0x144
+#define XILINX_PCIE_REG_PSCR_LNKUP BIT(11)
+#define XILINX_PCIE_REG_RPSC 0x148
+#define XILINX_PCIE_REG_RPSC_BEN BIT(0)
/**
* pcie_xilinx_link_up() - Check whether the PCIe link is up
* @pcie: Pointer to the PCI controller state
@@ -61,14 +66,18 @@
uint offset, void **paddress)
{
struct xilinx_pcie *pcie = dev_get_priv(udev);
- unsigned int bus = PCI_BUS(bdf);
+ unsigned int bus = PCI_BUS(bdf) - pcie->first_busno;
unsigned int dev = PCI_DEV(bdf);
unsigned int func = PCI_FUNC(bdf);
+ int num_buses = DIV_ROUND_UP(pcie->size, 1 << 16);
void *addr;
if ((bus > 0) && !pcie_xilinx_link_up(pcie))
return -ENODEV;
+ if (bus > num_buses)
+ return -ENODEV;
+
/*
* Busses 0 (host-PCIe bridge) & 1 (its immediate child) are
* limited to a single device each.
@@ -142,20 +151,37 @@
struct xilinx_pcie *pcie = dev_get_priv(dev);
fdt_addr_t addr;
fdt_size_t size;
- u32 rpsc;
addr = dev_read_addr_size(dev, &size);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
- pcie->cfg_base = devm_ioremap(dev, addr, size);
- if (IS_ERR(pcie->cfg_base))
- return PTR_ERR(pcie->cfg_base);
+ pcie->cfg_base = map_physmem(addr, size, MAP_NOCACHE);
+ if (!pcie->cfg_base)
+ return -ENOMEM;
+ pcie->size = size;
+ return 0;
+}
- /* Enable the Bridge enable bit */
- rpsc = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_RPSC);
+static int pci_xilinx_probe(struct udevice *dev)
+{
+ struct xilinx_pcie *pcie = dev_get_priv(dev);
+ u32 rpsc;
+ int num_buses = DIV_ROUND_UP(pcie->size, 1 << 16);
+
+ pcie->first_busno = dev_seq(dev);
+
+ /* Disable all interrupts */
+ writel(0, pcie->cfg_base + XILINX_PCIE_REG_INT_MASK);
+
+ /* Enable the bridge */
+ rpsc = readl(pcie->cfg_base + XILINX_PCIE_REG_RPSC);
rpsc |= XILINX_PCIE_REG_RPSC_BEN;
- __raw_writel(rpsc, pcie->cfg_base + XILINX_PCIE_REG_RPSC);
+ writel(rpsc, pcie->cfg_base + XILINX_PCIE_REG_RPSC);
+
+ /* Enable access to all possible subordinate buses */
+ writel((0 << 0) | (1 << 8) | (num_buses << 16),
+ pcie->cfg_base + PCI_PRIMARY_BUS);
return 0;
}
@@ -176,5 +202,6 @@
.of_match = pcie_xilinx_ids,
.ops = &pcie_xilinx_ops,
.of_to_plat = pcie_xilinx_of_to_plat,
+ .probe = pci_xilinx_probe,
.priv_auto = sizeof(struct xilinx_pcie),
};
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index ce4ea28..b4d01fc 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -8,8 +8,8 @@
obj-y += rockchip/
obj-y += socionext/
-obj-$(CONFIG_$(XPL_)PHY) += phy-uclass.o
-obj-$(CONFIG_$(XPL_)NOP_PHY) += nop-phy.o
+obj-$(CONFIG_$(PHASE_)PHY) += phy-uclass.o
+obj-$(CONFIG_$(PHASE_)NOP_PHY) += nop-phy.o
obj-$(CONFIG_MIPI_DPHY_HELPERS) += phy-core-mipi-dphy.o
obj-$(CONFIG_AB8500_USB_PHY) += phy-ab8500-usb.o
obj-$(CONFIG_APPLE_ATCPHY) += phy-apple-atc.o
@@ -19,7 +19,7 @@
obj-$(CONFIG_BCM6368_USBH_PHY) += bcm6368-usbh-phy.o
obj-$(CONFIG_BCM_SR_PCIE_PHY) += phy-bcm-sr-pcie.o
obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o
-obj-$(CONFIG_$(XPL_)PIPE3_PHY) += ti-pipe3-phy.o
+obj-$(CONFIG_$(PHASE_)PIPE3_PHY) += ti-pipe3-phy.o
obj-$(CONFIG_AM654_PHY) += phy-ti-am654.o
obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o
obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index b9306c9..3acffb4 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -85,41 +85,14 @@
int missing_phys;
};
-struct sun4i_usb_phy_info {
- const char *gpio_vbus;
- const char *gpio_vbus_det;
- const char *gpio_id_det;
-} phy_info[] = {
- {
- .gpio_vbus = CONFIG_USB0_VBUS_PIN,
- .gpio_vbus_det = CONFIG_USB0_VBUS_DET,
- .gpio_id_det = CONFIG_USB0_ID_DET,
- },
- {
- .gpio_vbus = CONFIG_USB1_VBUS_PIN,
- .gpio_vbus_det = NULL,
- .gpio_id_det = NULL,
- },
- {
- .gpio_vbus = CONFIG_USB2_VBUS_PIN,
- .gpio_vbus_det = NULL,
- .gpio_id_det = NULL,
- },
- {
- .gpio_vbus = CONFIG_USB3_VBUS_PIN,
- .gpio_vbus_det = NULL,
- .gpio_id_det = NULL,
- },
-};
-
struct sun4i_usb_phy_plat {
void __iomem *pmu;
- struct gpio_desc gpio_vbus;
struct gpio_desc gpio_vbus_det;
struct gpio_desc gpio_id_det;
struct clk clocks;
struct clk clk2;
struct reset_ctl resets;
+ struct udevice *vbus;
int id;
};
@@ -208,6 +181,7 @@
{
struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
+ int ret;
if (initial_usb_scan_delay) {
mdelay(initial_usb_scan_delay);
@@ -220,8 +194,9 @@
return 0;
}
- if (dm_gpio_is_valid(&usb_phy->gpio_vbus))
- dm_gpio_set_value(&usb_phy->gpio_vbus, 1);
+ ret = regulator_set_enable_if_allowed(usb_phy->vbus, true);
+ if (ret)
+ return ret;
return 0;
}
@@ -230,9 +205,11 @@
{
struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
+ int ret;
- if (dm_gpio_is_valid(&usb_phy->gpio_vbus))
- dm_gpio_set_value(&usb_phy->gpio_vbus, 0);
+ ret = regulator_set_enable_if_allowed(usb_phy->vbus, false);
+ if (ret)
+ return ret;
return 0;
}
@@ -481,48 +458,39 @@
data->usb_phy = plat;
for (i = 0; i < data->cfg->num_phys; i++) {
struct sun4i_usb_phy_plat *phy = &plat[i];
- struct sun4i_usb_phy_info *info = &phy_info[i];
- char name[16];
+ char name[32];
if (data->cfg->missing_phys & BIT(i))
continue;
- ret = dm_gpio_lookup_name(info->gpio_vbus, &phy->gpio_vbus);
- if (ret == 0) {
- ret = dm_gpio_request(&phy->gpio_vbus, "usb_vbus");
- if (ret)
- return ret;
- ret = dm_gpio_set_dir_flags(&phy->gpio_vbus,
- GPIOD_IS_OUT);
+ snprintf(name, sizeof(name), "usb%d_vbus-supply", i);
+ ret = device_get_supply_regulator(dev, name, &phy->vbus);
+ if (phy->vbus) {
+ ret = regulator_set_enable_if_allowed(phy->vbus, false);
if (ret)
return ret;
- ret = dm_gpio_set_value(&phy->gpio_vbus, 0);
- if (ret)
- return ret;
}
- ret = dm_gpio_lookup_name(info->gpio_vbus_det,
- &phy->gpio_vbus_det);
- if (ret == 0) {
- ret = dm_gpio_request(&phy->gpio_vbus_det,
- "usb_vbus_det");
- if (ret)
- return ret;
- ret = dm_gpio_set_dir_flags(&phy->gpio_vbus_det,
- GPIOD_IS_IN);
- if (ret)
+ if (i == 0) {
+ ret = gpio_request_by_name(dev, "usb0_vbus_det-gpios",
+ 0, &phy->gpio_vbus_det,
+ GPIOD_IS_IN);
+ if (ret && ret != -ENOENT) {
+ dev_err(dev,
+ "failed to get VBUS detect GPIO: %d\n",
+ ret);
return ret;
- }
+ }
- ret = dm_gpio_lookup_name(info->gpio_id_det, &phy->gpio_id_det);
- if (ret == 0) {
- ret = dm_gpio_request(&phy->gpio_id_det, "usb_id_det");
- if (ret)
- return ret;
- ret = dm_gpio_set_dir_flags(&phy->gpio_id_det,
- GPIOD_IS_IN | GPIOD_PULL_UP);
- if (ret)
+ ret = gpio_request_by_name(dev, "usb0_id_det-gpios", 0,
+ &phy->gpio_id_det,
+ GPIOD_IS_IN | GPIOD_PULL_UP);
+ if (ret && ret != -ENOENT) {
+ dev_err(dev,
+ "failed to get ID detect GPIO: %d\n",
+ ret);
return ret;
+ }
}
if (data->cfg->dedicated_clocks)
diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile
index e0da41c..2b1e517 100644
--- a/drivers/phy/cadence/Makefile
+++ b/drivers/phy/cadence/Makefile
@@ -1,2 +1,2 @@
-obj-$(CONFIG_$(XPL_)PHY_CADENCE_SIERRA) += phy-cadence-sierra.o
-obj-$(CONFIG_$(XPL_)PHY_CADENCE_TORRENT) += phy-cadence-torrent.o
+obj-$(CONFIG_$(PHASE_)PHY_CADENCE_SIERRA) += phy-cadence-sierra.o
+obj-$(CONFIG_$(PHASE_)PHY_CADENCE_TORRENT) += phy-cadence-torrent.o
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index 43f6e02..88b33de 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -40,11 +40,13 @@
struct rockchip_usb2phy_cfg {
unsigned int reg;
struct usb2phy_reg clkout_ctl;
+ struct usb2phy_reg clkout_ctl_phy;
const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
};
struct rockchip_usb2phy {
struct regmap *reg_base;
+ struct regmap *phy_base;
struct clk phyclk;
const struct rockchip_usb2phy_cfg *phy_cfg;
};
@@ -165,6 +167,22 @@
.of_xlate = rockchip_usb2phy_of_xlate,
};
+static void rockchip_usb2phy_clkout_ctl(struct clk *clk, struct regmap **base,
+ const struct usb2phy_reg **clkout_ctl)
+{
+ struct udevice *parent = dev_get_parent(clk->dev);
+ struct rockchip_usb2phy *priv = dev_get_priv(parent);
+ const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg;
+
+ if (priv->phy_cfg->clkout_ctl_phy.enable) {
+ *base = priv->phy_base;
+ *clkout_ctl = &phy_cfg->clkout_ctl_phy;
+ } else {
+ *base = priv->reg_base;
+ *clkout_ctl = &phy_cfg->clkout_ctl;
+ }
+}
+
/**
* round_rate() - Adjust a rate to the exact rate a clock can provide.
* @clk: The clock to manipulate.
@@ -185,13 +203,14 @@
*/
int rockchip_usb2phy_clk_enable(struct clk *clk)
{
- struct udevice *parent = dev_get_parent(clk->dev);
- struct rockchip_usb2phy *priv = dev_get_priv(parent);
- const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg;
+ const struct usb2phy_reg *clkout_ctl;
+ struct regmap *base;
+
+ rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl);
/* turn on 480m clk output if it is off */
- if (!property_enabled(priv->reg_base, &phy_cfg->clkout_ctl)) {
- property_enable(priv->reg_base, &phy_cfg->clkout_ctl, true);
+ if (!property_enabled(base, clkout_ctl)) {
+ property_enable(base, clkout_ctl, true);
/* waiting for the clk become stable */
usleep_range(1200, 1300);
@@ -208,12 +227,13 @@
*/
int rockchip_usb2phy_clk_disable(struct clk *clk)
{
- struct udevice *parent = dev_get_parent(clk->dev);
- struct rockchip_usb2phy *priv = dev_get_priv(parent);
- const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg;
+ const struct usb2phy_reg *clkout_ctl;
+ struct regmap *base;
+
+ rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl);
/* turn off 480m clk output */
- property_enable(priv->reg_base, &phy_cfg->clkout_ctl, false);
+ property_enable(base, clkout_ctl, false);
return 0;
}
@@ -281,7 +301,10 @@
return ret;
}
- return 0;
+ if (priv->phy_cfg->clkout_ctl_phy.enable)
+ ret = regmap_init_mem_index(dev_ofnode(dev), &priv->phy_base, 0);
+
+ return ret;
}
static int rockchip_usb2phy_bind(struct udevice *dev)
@@ -389,6 +412,22 @@
{ /* sentinel */ }
};
+static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = {
+ {
+ .reg = 0xffdf0000,
+ .clkout_ctl_phy = { 0x041c, 7, 2, 0, 0x27 },
+ .port_cfgs = {
+ [USB2PHY_PORT_OTG] = {
+ .phy_sus = { 0x004c, 1, 0, 2, 1 },
+ },
+ [USB2PHY_PORT_HOST] = {
+ .phy_sus = { 0x005c, 1, 0, 2, 1 },
+ }
+ },
+ },
+ { /* sentinel */ }
+};
+
static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
{
.reg = 0xfe8a0000,
@@ -471,6 +510,10 @@
.data = (ulong)&rk3399_usb2phy_cfgs,
},
{
+ .compatible = "rockchip,rk3528-usb2phy",
+ .data = (ulong)&rk3528_phy_cfgs,
+ },
+ {
.compatible = "rockchip,rk3568-usb2phy",
.data = (ulong)&rk3568_phy_cfgs,
},
diff --git a/drivers/phy/ti/Makefile b/drivers/phy/ti/Makefile
index 699901f..169036a 100644
--- a/drivers/phy/ti/Makefile
+++ b/drivers/phy/ti/Makefile
@@ -1 +1 @@
-obj-$(CONFIG_$(XPL_)PHY_J721E_WIZ) += phy-j721e-wiz.o
+obj-$(CONFIG_$(PHASE_)PHY_J721E_WIZ) += phy-j721e-wiz.o
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 6deb6aa..a8eba65 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -1,14 +1,14 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y += pinctrl-uclass.o
-obj-$(CONFIG_$(XPL_)PINCTRL_GENERIC) += pinctrl-generic.o
+obj-$(CONFIG_$(PHASE_)PINCTRL_GENERIC) += pinctrl-generic.o
obj-$(CONFIG_PINCTRL_ADI) += pinctrl-adi-adsp.o
obj-$(CONFIG_PINCTRL_APPLE) += pinctrl-apple.o
obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o
obj-y += nxp/
-obj-$(CONFIG_$(XPL_)PINCTRL_ROCKCHIP) += rockchip/
+obj-$(CONFIG_$(PHASE_)PINCTRL_ROCKCHIP) += rockchip/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_ATH79) += ath79/
obj-$(CONFIG_PINCTRL_INTEL) += intel/
@@ -18,7 +18,7 @@
obj-$(CONFIG_ARCH_RENESAS) += renesas/
obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/
-obj-$(CONFIG_$(XPL_)PINCTRL_TEGRA) += tegra/
+obj-$(CONFIG_$(PHASE_)PINCTRL_TEGRA) += tegra/
obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
obj-$(CONFIG_PINCTRL_PIC32) += pinctrl_pic32.o
obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/
@@ -32,7 +32,7 @@
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o
obj-$(CONFIG_PINCTRL_STM32) += pinctrl_stm32.o
-obj-$(CONFIG_$(XPL_)PINCTRL_STMFX) += pinctrl-stmfx.o
+obj-$(CONFIG_$(PHASE_)PINCTRL_STMFX) += pinctrl-stmfx.o
obj-y += broadcom/
obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o
obj-$(CONFIG_PINCTRL_STARFIVE) += starfive/
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index e24287c..e567cb1 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -61,6 +61,13 @@
help
Say Y here to enable support for pinctrl on the Snapdragon SC7280 SoC,
+config PINCTRL_QCOM_SDM660
+ bool "Qualcomm SDM630/660 Pinctrl"
+ select PINCTRL_QCOM
+ help
+ Say Y here to enable support for pinctrl on the Snapdragon 630/636/660
+ SoCs, as well as the associated GPIO driver.
+
config PINCTRL_QCOM_SDM845
bool "Qualcomm SDM845 Pinctrl"
select PINCTRL_QCOM
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 65d1845..6ffc6d4 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -11,6 +11,7 @@
obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o
obj-$(CONFIG_PINCTRL_QCOM_SA8775P) += pinctrl-sa8775p.o
obj-$(CONFIG_PINCTRL_QCOM_SC7280) += pinctrl-sc7280.o
+obj-$(CONFIG_PINCTRL_QCOM_SDM660) += pinctrl-sdm660.o
obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o
obj-$(CONFIG_PINCTRL_QCOM_SM6115) += pinctrl-sm6115.o
obj-$(CONFIG_PINCTRL_QCOM_SM8150) += pinctrl-sm8150.o
diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c
index 24d0319..c95db56 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcom.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcom.c
@@ -15,14 +15,18 @@
#include <asm/gpio.h>
#include <dm/pinctrl.h>
#include <linux/bitops.h>
+#include <linux/bitmap.h>
#include <linux/bug.h>
#include <mach/gpio.h>
#include "pinctrl-qcom.h"
+#define MSM_PINCTRL_MAX_PINS 256
+
struct msm_pinctrl_priv {
phys_addr_t base;
struct msm_pinctrl_data *data;
+ DECLARE_BITMAP(reserved_map, MSM_PINCTRL_MAX_PINS);
};
#define GPIO_CONFIG_REG(priv, x) \
@@ -71,13 +75,60 @@
return priv->data->get_function_name(dev, selector);
}
+static int msm_pinctrl_parse_ranges(struct udevice *dev)
+{
+ struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+ ofnode node = dev_ofnode(dev);
+ int ret, count, i;
+ u32 *ranges;
+
+ if (ofnode_read_prop(node, "gpio-reserved-ranges", &count)) {
+ if (count % 2 == 1) {
+ dev_err(dev, "gpio-reserved-ranges must be a multiple of 2\n");
+ return -EINVAL;
+ }
+
+ ranges = malloc(count);
+ if (!ranges)
+ return -ENOMEM;
+
+ ret = ofnode_read_u32_array(node, "gpio-reserved-ranges", ranges, count / 4);
+ if (ret) {
+ dev_err(dev, "failed to read gpio-reserved-ranges array (%d)\n", ret);
+ return ret;
+ }
+
+ for (i = 0; i < count / 4; i += 2) {
+ if (ranges[i] >= MSM_PINCTRL_MAX_PINS ||
+ (ranges[i] + ranges[i + 1]) >= MSM_PINCTRL_MAX_PINS) {
+ dev_err(dev, "invalid reserved-range (%d;%d)\n",
+ ranges[i], ranges[i + 1]);
+ return -EINVAL;
+ }
+
+ bitmap_set(priv->reserved_map, ranges[i], ranges[i + 1]);
+ }
+
+ free(ranges);
+ }
+
+ return 0;
+}
+
static int msm_pinctrl_probe(struct udevice *dev)
{
struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+ int ret;
priv->base = dev_read_addr(dev);
priv->data = (struct msm_pinctrl_data *)dev_get_driver_data(dev);
+ ret = msm_pinctrl_parse_ranges(dev);
+ if (ret) {
+ printf("Couldn't parse reserved GPIO ranges!\n");
+ return ret;
+ }
+
return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
}
@@ -97,6 +148,9 @@
if (func < 0)
return func;
+ if (msm_pinctrl_is_reserved(dev, pin_selector))
+ return -EPERM;
+
/* Always NOP for special pins, assume they're in the correct state */
if (qcom_is_special_pin(&priv->data->pin_data, pin_selector))
return 0;
@@ -145,6 +199,9 @@
{
struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+ if (msm_pinctrl_is_reserved(dev, pin_selector))
+ return -EPERM;
+
if (qcom_is_special_pin(&priv->data->pin_data, pin_selector))
return msm_pinconf_set_special(priv, pin_selector, param, argument);
@@ -241,3 +298,13 @@
.ops = &msm_pinctrl_ops,
.probe = msm_pinctrl_probe,
};
+
+bool msm_pinctrl_is_reserved(struct udevice *dev, unsigned int pin)
+{
+ struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+
+ if (pin >= MSM_PINCTRL_MAX_PINS)
+ return false;
+
+ return test_bit(pin, priv->reserved_map);
+}
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm660.c b/drivers/pinctrl/qcom/pinctrl-sdm660.c
new file mode 100644
index 0000000..646d848
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sdm660.c
@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm SDM630/660 TLMM pinctrl
+ *
+ */
+
+#include <dm.h>
+#include "pinctrl-qcom.h"
+
+#define TLMM_BASE 0x03100000
+#define SOUTH (0x03100000 - TLMM_BASE) /* 0x0 */
+#define CENTER (0x03500000 - TLMM_BASE) /* 0x400000 */
+#define NORTH (0x03900000 - TLMM_BASE) /* 0x800000 */
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+
+static const struct pinctrl_function sdm660_pinctrl_functions[] = {
+ { "gpio", 0 },
+ { "blsp_uart2", 3 }, /* gpio 4 and 5, used for debug uart */
+};
+
+static const unsigned int sdm660_pin_offsets[] = {
+ [0] = SOUTH,
+ [1] = SOUTH,
+ [2] = SOUTH,
+ [3] = SOUTH,
+ [4] = NORTH,
+ [5] = SOUTH,
+ [6] = SOUTH,
+ [7] = SOUTH,
+ [8] = NORTH,
+ [9] = NORTH,
+ [10] = NORTH,
+ [11] = NORTH,
+ [12] = NORTH,
+ [13] = NORTH,
+ [14] = NORTH,
+ [15] = NORTH,
+ [16] = CENTER,
+ [17] = CENTER,
+ [18] = CENTER,
+ [19] = CENTER,
+ [20] = SOUTH,
+ [21] = SOUTH,
+ [22] = CENTER,
+ [23] = CENTER,
+ [24] = NORTH,
+ [25] = NORTH,
+ [26] = NORTH,
+ [27] = NORTH,
+ [28] = CENTER,
+ [29] = CENTER,
+ [30] = CENTER,
+ [31] = CENTER,
+ [32] = SOUTH,
+ [33] = SOUTH,
+ [34] = SOUTH,
+ [35] = SOUTH,
+ [36] = SOUTH,
+ [37] = SOUTH,
+ [38] = SOUTH,
+ [39] = SOUTH,
+ [40] = SOUTH,
+ [41] = SOUTH,
+ [42] = SOUTH,
+ [43] = SOUTH,
+ [44] = SOUTH,
+ [45] = SOUTH,
+ [46] = SOUTH,
+ [47] = SOUTH,
+ [48] = SOUTH,
+ [49] = SOUTH,
+ [50] = SOUTH,
+ [51] = SOUTH,
+ [52] = SOUTH,
+ [53] = NORTH,
+ [54] = NORTH,
+ [55] = SOUTH,
+ [56] = SOUTH,
+ [57] = SOUTH,
+ [58] = SOUTH,
+ [59] = NORTH,
+ [60] = NORTH,
+ [61] = NORTH,
+ [62] = NORTH,
+ [63] = NORTH,
+ [64] = SOUTH,
+ [65] = SOUTH,
+ [66] = NORTH,
+ [67] = NORTH,
+ [68] = NORTH,
+ [69] = NORTH,
+ [70] = NORTH,
+ [71] = NORTH,
+ [72] = NORTH,
+ [73] = NORTH,
+ [74] = NORTH,
+ [75] = NORTH,
+ [76] = NORTH,
+ [77] = NORTH,
+ [78] = NORTH,
+ [79] = SOUTH,
+ [80] = SOUTH,
+ [81] = CENTER,
+ [82] = CENTER,
+ [83] = SOUTH,
+ [84] = SOUTH,
+ [85] = SOUTH,
+ [86] = SOUTH,
+ [87] = SOUTH,
+ [88] = SOUTH,
+ [89] = SOUTH,
+ [90] = SOUTH,
+ [91] = SOUTH,
+ [92] = SOUTH,
+ [93] = SOUTH,
+ [94] = SOUTH,
+ [95] = SOUTH,
+ [96] = SOUTH,
+ [97] = SOUTH,
+ [98] = SOUTH,
+ [99] = SOUTH,
+ [100] = SOUTH,
+ [101] = SOUTH,
+ [102] = SOUTH,
+ [103] = SOUTH,
+ [104] = SOUTH,
+ [105] = SOUTH,
+ [106] = SOUTH,
+ [107] = SOUTH,
+ [108] = SOUTH,
+ [109] = SOUTH,
+ [110] = SOUTH,
+ [111] = SOUTH,
+ [112] = SOUTH,
+ [113] = SOUTH,
+};
+
+/*
+ * Special pins - eMMC/SD related: [114..120], in total 7 special pins
+ */
+
+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
+ { \
+ .name = pg_name, \
+ .ctl_reg = ctl, \
+ .io_reg = 0, \
+ .pull_bit = pull, \
+ .drv_bit = drv, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = -1, \
+ }
+
+/* All SDC pins are in the NORTH tile */
+static const struct msm_special_pin_data sdm660_special_pins_data[] = {
+ SDC_QDSD_PINGROUP("sdc1_clk", NORTH + 0x9a000, 13, 6),
+ SDC_QDSD_PINGROUP("sdc1_cmd", NORTH + 0x9a000, 11, 3),
+ SDC_QDSD_PINGROUP("sdc1_data", NORTH + 0x9a000, 9, 0),
+ SDC_QDSD_PINGROUP("sdc2_clk", NORTH + 0x9b000, 14, 6),
+ SDC_QDSD_PINGROUP("sdc2_cmd", NORTH + 0x9b000, 11, 3),
+ SDC_QDSD_PINGROUP("sdc2_data", NORTH + 0x9b000, 9, 0),
+ SDC_QDSD_PINGROUP("sdc1_rclk", NORTH + 0x9a000, 15, 0),
+};
+
+static const char *sdm660_get_function_name(struct udevice *dev, unsigned int selector)
+{
+ return sdm660_pinctrl_functions[selector].name;
+}
+
+static const char *sdm660_get_pin_name(struct udevice *dev, unsigned int selector)
+{
+ static const char * const special_pins_names[] = {
+ "sdc1_clk", "sdc1_cmd", "sdc1_data",
+ "sdc2_clk", "sdc2_cmd", "sdc2_data",
+ "sdc1_rclk"
+ };
+
+ if (selector >= 114 && selector <= 120)
+ snprintf(pin_name, MAX_PIN_NAME_LEN, special_pins_names[selector - 114]);
+ else
+ snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
+
+ return pin_name;
+}
+
+static int sdm660_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector)
+{
+ if (selector >= 0 && selector < ARRAY_SIZE(sdm660_pinctrl_functions))
+ return sdm660_pinctrl_functions[selector].val;
+ return -EINVAL;
+}
+
+struct msm_pinctrl_data sdm660_data = {
+ .pin_data = {
+ .pin_offsets = sdm660_pin_offsets,
+ .pin_count = ARRAY_SIZE(sdm660_pin_offsets) + ARRAY_SIZE(sdm660_special_pins_data),
+ .special_pins_start = 114,
+ .special_pins_data = sdm660_special_pins_data,
+ },
+ .functions_count = ARRAY_SIZE(sdm660_pinctrl_functions),
+ .get_function_name = sdm660_get_function_name,
+ .get_function_mux = sdm660_get_function_mux,
+ .get_pin_name = sdm660_get_pin_name,
+};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+ {
+ .compatible = "qcom,sdm630-pinctrl",
+ .data = (ulong)&sdm660_data
+ },
+ {
+ .compatible = "qcom,sdm660-pinctrl",
+ .data = (ulong)&sdm660_data
+ },
+ { /* Sentinel */ }
+};
+
+U_BOOT_DRIVER(pinctrl_ssdm660) = {
+ .name = "pinctrl_sdm660",
+ .id = UCLASS_NOP,
+ .of_match = msm_pinctrl_ids,
+ .ops = &msm_pinctrl_ops,
+ .bind = msm_pinctrl_bind,
+};
diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
index c91f650..e17415e 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -14,7 +14,9 @@
obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
+obj-$(CONFIG_ROCKCHIP_RK3528) += pinctrl-rk3528.o
obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o
+obj-$(CONFIG_ROCKCHIP_RK3576) += pinctrl-rk3576.o
obj-$(CONFIG_ROCKCHIP_RK3588) += pinctrl-rk3588.o
obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o
obj-$(CONFIG_ROCKCHIP_RV1126) += pinctrl-rv1126.o
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3528.c b/drivers/pinctrl/rockchip/pinctrl-rk3528.c
new file mode 100644
index 0000000..a3e1f0b
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3528.c
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <regmap.h>
+#include <syscon.h>
+
+#include "pinctrl-rockchip.h"
+#include <dt-bindings/pinctrl/rockchip.h>
+
+static int rk3528_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int iomux_num = (pin / 8);
+ struct regmap *regmap;
+ int reg, mask;
+ u8 bit;
+ u32 data, rmask;
+
+ regmap = priv->regmap_base;
+ reg = bank->iomux[iomux_num].offset;
+ if ((pin % 8) >= 4)
+ reg += 0x4;
+ bit = (pin % 4) * 4;
+ mask = 0xf;
+
+ data = (mask << (bit + 16));
+ rmask = data | (data >> 16);
+ data |= (mux & mask) << bit;
+
+ return regmap_update_bits(regmap, reg, rmask, data);
+}
+
+#define RK3528_DRV_BITS_PER_PIN 8
+#define RK3528_DRV_PINS_PER_REG 2
+#define RK3528_DRV_GPIO0_OFFSET 0x100
+#define RK3528_DRV_GPIO1_OFFSET 0x20120
+#define RK3528_DRV_GPIO2_OFFSET 0x30160
+#define RK3528_DRV_GPIO3_OFFSET 0x20190
+#define RK3528_DRV_GPIO4_OFFSET 0x101C0
+
+static void rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ *regmap = priv->regmap_base;
+
+ if (bank->bank_num == 0) {
+ *reg = RK3528_DRV_GPIO0_OFFSET;
+ } else if (bank->bank_num == 1) {
+ *reg = RK3528_DRV_GPIO1_OFFSET;
+ } else if (bank->bank_num == 2) {
+ *reg = RK3528_DRV_GPIO2_OFFSET;
+ } else if (bank->bank_num == 3) {
+ *reg = RK3528_DRV_GPIO3_OFFSET;
+ } else if (bank->bank_num == 4) {
+ *reg = RK3528_DRV_GPIO4_OFFSET;
+ } else {
+ *reg = 0;
+ debug("unsupported bank_num %d\n", bank->bank_num);
+ }
+
+ *reg += ((pin_num / RK3528_DRV_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3528_DRV_PINS_PER_REG;
+ *bit *= RK3528_DRV_BITS_PER_PIN;
+}
+
+static int rk3528_set_drive(struct rockchip_pin_bank *bank,
+ int pin_num, int strength)
+{
+ struct regmap *regmap;
+ int reg;
+ u32 data, rmask;
+ u8 bit;
+ int drv = (1 << (strength + 1)) - 1;
+
+ rk3528_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RK3528_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+ rmask = data | (data >> 16);
+ data |= (drv << bit);
+
+ return regmap_update_bits(regmap, reg, rmask, data);
+}
+
+#define RK3528_PULL_BITS_PER_PIN 2
+#define RK3528_PULL_PINS_PER_REG 8
+#define RK3528_PULL_GPIO0_OFFSET 0x200
+#define RK3528_PULL_GPIO1_OFFSET 0x20210
+#define RK3528_PULL_GPIO2_OFFSET 0x30220
+#define RK3528_PULL_GPIO3_OFFSET 0x20230
+#define RK3528_PULL_GPIO4_OFFSET 0x10240
+
+static void rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ *regmap = priv->regmap_base;
+
+ if (bank->bank_num == 0) {
+ *reg = RK3528_PULL_GPIO0_OFFSET;
+ } else if (bank->bank_num == 1) {
+ *reg = RK3528_PULL_GPIO1_OFFSET;
+ } else if (bank->bank_num == 2) {
+ *reg = RK3528_PULL_GPIO2_OFFSET;
+ } else if (bank->bank_num == 3) {
+ *reg = RK3528_PULL_GPIO3_OFFSET;
+ } else if (bank->bank_num == 4) {
+ *reg = RK3528_PULL_GPIO4_OFFSET;
+ } else {
+ *reg = 0;
+ debug("unsupported bank_num %d\n", bank->bank_num);
+ }
+
+ *reg += ((pin_num / RK3528_PULL_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3528_PULL_PINS_PER_REG;
+ *bit *= RK3528_PULL_BITS_PER_PIN;
+}
+
+static int rk3528_set_pull(struct rockchip_pin_bank *bank,
+ int pin_num, int pull)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u8 bit, type;
+ u32 data, rmask;
+
+ if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+ return -EOPNOTSUPP;
+
+ rk3528_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+ type = bank->pull_type[pin_num / 8];
+ ret = rockchip_translate_pull_value(type, pull);
+ if (ret < 0) {
+ debug("unsupported pull setting %d\n", pull);
+ return ret;
+ }
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RK3528_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+ rmask = data | (data >> 16);
+ data |= (ret << bit);
+
+ return regmap_update_bits(regmap, reg, rmask, data);
+}
+
+#define RK3528_SMT_BITS_PER_PIN 1
+#define RK3528_SMT_PINS_PER_REG 8
+#define RK3528_SMT_GPIO0_OFFSET 0x400
+#define RK3528_SMT_GPIO1_OFFSET 0x20410
+#define RK3528_SMT_GPIO2_OFFSET 0x30420
+#define RK3528_SMT_GPIO3_OFFSET 0x20430
+#define RK3528_SMT_GPIO4_OFFSET 0x10440
+
+static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num,
+ struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ *regmap = priv->regmap_base;
+
+ if (bank->bank_num == 0) {
+ *reg = RK3528_SMT_GPIO0_OFFSET;
+ } else if (bank->bank_num == 1) {
+ *reg = RK3528_SMT_GPIO1_OFFSET;
+ } else if (bank->bank_num == 2) {
+ *reg = RK3528_SMT_GPIO2_OFFSET;
+ } else if (bank->bank_num == 3) {
+ *reg = RK3528_SMT_GPIO3_OFFSET;
+ } else if (bank->bank_num == 4) {
+ *reg = RK3528_SMT_GPIO4_OFFSET;
+ } else {
+ *reg = 0;
+ debug("unsupported bank_num %d\n", bank->bank_num);
+ }
+
+ *reg += ((pin_num / RK3528_SMT_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3528_SMT_PINS_PER_REG;
+ *bit *= RK3528_SMT_BITS_PER_PIN;
+
+ return 0;
+}
+
+static int rk3528_set_schmitt(struct rockchip_pin_bank *bank,
+ int pin_num, int enable)
+{
+ struct regmap *regmap;
+ int reg;
+ u32 data, rmask;
+ u8 bit;
+
+ rk3528_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RK3528_SMT_BITS_PER_PIN) - 1) << (bit + 16);
+ rmask = data | (data >> 16);
+ data |= (enable << bit);
+
+ return regmap_update_bits(regmap, reg, rmask, data);
+}
+
+static struct rockchip_pin_bank rk3528_pin_banks[] = {
+ PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0, 0, 0, 0),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x20020, 0x20028, 0x20030, 0x20038),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x30040, 0, 0, 0),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x20060, 0x20068, 0x20070, 0),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x10080, 0x10088, 0x10090, 0x10098),
+};
+
+static const struct rockchip_pin_ctrl rk3528_pin_ctrl = {
+ .pin_banks = rk3528_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3528_pin_banks),
+ .grf_mux_offset = 0x0,
+ .set_mux = rk3528_set_mux,
+ .set_pull = rk3528_set_pull,
+ .set_drive = rk3528_set_drive,
+ .set_schmitt = rk3528_set_schmitt,
+};
+
+static const struct udevice_id rk3528_pinctrl_ids[] = {
+ {
+ .compatible = "rockchip,rk3528-pinctrl",
+ .data = (ulong)&rk3528_pin_ctrl
+ },
+ { }
+};
+
+U_BOOT_DRIVER(rockchip_rk3528_pinctrl) = {
+ .name = "rockchip_rk3528_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = rk3528_pinctrl_ids,
+ .priv_auto = sizeof(struct rockchip_pinctrl_priv),
+ .ops = &rockchip_pinctrl_ops,
+#if CONFIG_IS_ENABLED(OF_REAL)
+ .bind = dm_scan_fdt_dev,
+#endif
+ .probe = rockchip_pinctrl_probe,
+};
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3576.c b/drivers/pinctrl/rockchip/pinctrl-rk3576.c
new file mode 100644
index 0000000..66e1142
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3576.c
@@ -0,0 +1,278 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2024 Rockchip Electronics Co., Ltd
+ */
+
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <regmap.h>
+#include <syscon.h>
+
+#include "pinctrl-rockchip.h"
+#include <dt-bindings/pinctrl/rockchip.h>
+
+static int rk3576_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int iomux_num = (pin / 8);
+ struct regmap *regmap;
+ int reg, mask;
+ u8 bit;
+ u32 data, rmask;
+
+ regmap = priv->regmap_base;
+ reg = bank->iomux[iomux_num].offset;
+ if ((pin % 8) >= 4)
+ reg += 0x4;
+ bit = (pin % 4) * 4;
+ mask = 0xf;
+
+ data = (mask << (bit + 16));
+ rmask = data | (data >> 16);
+ data |= (mux & mask) << bit;
+
+ if (bank->bank_num == 0 && pin >= RK_PB4 && pin <= RK_PB7)
+ reg += 0x1FF4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */
+
+ return regmap_update_bits(regmap, reg, rmask, data);
+}
+
+#define RK3576_DRV_BITS_PER_PIN 4
+#define RK3576_DRV_PINS_PER_REG 4
+#define RK3576_DRV_GPIO0_AL_OFFSET 0x10
+#define RK3576_DRV_GPIO0_BH_OFFSET 0x2014
+#define RK3576_DRV_GPIO1_OFFSET 0x6020
+#define RK3576_DRV_GPIO2_OFFSET 0x6040
+#define RK3576_DRV_GPIO3_OFFSET 0x6060
+#define RK3576_DRV_GPIO4_AL_OFFSET 0x6080
+#define RK3576_DRV_GPIO4_CL_OFFSET 0xA090
+#define RK3576_DRV_GPIO4_DL_OFFSET 0xB098
+
+static void rk3576_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ *regmap = priv->regmap_base;
+ if (bank->bank_num == 0 && pin_num < 12) {
+ *reg = RK3576_DRV_GPIO0_AL_OFFSET;
+ } else if (bank->bank_num == 0) {
+ *reg = RK3576_DRV_GPIO0_BH_OFFSET - 0xc;
+ } else if (bank->bank_num == 1) {
+ *reg = RK3576_DRV_GPIO1_OFFSET;
+ } else if (bank->bank_num == 2) {
+ *reg = RK3576_DRV_GPIO2_OFFSET;
+ } else if (bank->bank_num == 3) {
+ *reg = RK3576_DRV_GPIO3_OFFSET;
+ } else if (bank->bank_num == 4 && pin_num < 16) {
+ *reg = RK3576_DRV_GPIO4_AL_OFFSET;
+ } else if (bank->bank_num == 4 && pin_num < 24) {
+ *reg = RK3576_DRV_GPIO4_CL_OFFSET - 0x10;
+ } else if (bank->bank_num == 4) {
+ *reg = RK3576_DRV_GPIO4_DL_OFFSET - 0x18;
+ } else {
+ *reg = 0;
+ debug("unsupported bank_num %d\n", bank->bank_num);
+ }
+
+ *reg += ((pin_num / RK3576_DRV_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3576_DRV_PINS_PER_REG;
+ *bit *= RK3576_DRV_BITS_PER_PIN;
+}
+
+static int rk3576_set_drive(struct rockchip_pin_bank *bank,
+ int pin_num, int strength)
+{
+ struct regmap *regmap;
+ int reg;
+ u32 data, rmask;
+ u8 bit;
+ int drv = ((strength & BIT(2)) >> 2) | ((strength & BIT(0)) << 2) | (strength & BIT(1));
+
+ rk3576_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RK3576_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+ rmask = data | (data >> 16);
+ data |= (drv << bit);
+
+ return regmap_update_bits(regmap, reg, rmask, data);
+}
+
+#define RK3576_PULL_BITS_PER_PIN 2
+#define RK3576_PULL_PINS_PER_REG 8
+#define RK3576_PULL_GPIO0_AL_OFFSET 0x20
+#define RK3576_PULL_GPIO0_BH_OFFSET 0x2028
+#define RK3576_PULL_GPIO1_OFFSET 0x6110
+#define RK3576_PULL_GPIO2_OFFSET 0x6120
+#define RK3576_PULL_GPIO3_OFFSET 0x6130
+#define RK3576_PULL_GPIO4_AL_OFFSET 0x6140
+#define RK3576_PULL_GPIO4_CL_OFFSET 0xA148
+#define RK3576_PULL_GPIO4_DL_OFFSET 0xB14C
+
+static void rk3576_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ *regmap = priv->regmap_base;
+ if (bank->bank_num == 0 && pin_num < 12) {
+ *reg = RK3576_PULL_GPIO0_AL_OFFSET;
+ } else if (bank->bank_num == 0) {
+ *reg = RK3576_PULL_GPIO0_BH_OFFSET - 0x4;
+ } else if (bank->bank_num == 1) {
+ *reg = RK3576_PULL_GPIO1_OFFSET;
+ } else if (bank->bank_num == 2) {
+ *reg = RK3576_PULL_GPIO2_OFFSET;
+ } else if (bank->bank_num == 3) {
+ *reg = RK3576_PULL_GPIO3_OFFSET;
+ } else if (bank->bank_num == 4 && pin_num < 16) {
+ *reg = RK3576_PULL_GPIO4_AL_OFFSET;
+ } else if (bank->bank_num == 4 && pin_num < 24) {
+ *reg = RK3576_PULL_GPIO4_CL_OFFSET - 0x8;
+ } else if (bank->bank_num == 4) {
+ *reg = RK3576_PULL_GPIO4_DL_OFFSET - 0xc;
+ } else {
+ *reg = 0;
+ debug("unsupported bank_num %d\n", bank->bank_num);
+ }
+
+ *reg += ((pin_num / RK3576_PULL_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3576_PULL_PINS_PER_REG;
+ *bit *= RK3576_PULL_BITS_PER_PIN;
+}
+
+static int rk3576_set_pull(struct rockchip_pin_bank *bank,
+ int pin_num, int pull)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u8 bit, type;
+ u32 data, rmask;
+
+ if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+ return -ENOTSUPP;
+
+ rk3576_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+ type = 1; /* FIXME: was always set to 1 in vendor kernel */
+ ret = rockchip_translate_pull_value(type, pull);
+ if (ret < 0) {
+ debug("unsupported pull setting %d\n", pull);
+ return ret;
+ }
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RK3576_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+ rmask = data | (data >> 16);
+ data |= (ret << bit);
+
+ return regmap_update_bits(regmap, reg, rmask, data);
+}
+
+#define RK3576_SMT_BITS_PER_PIN 1
+#define RK3576_SMT_PINS_PER_REG 8
+#define RK3576_SMT_GPIO0_AL_OFFSET 0x30
+#define RK3576_SMT_GPIO0_BH_OFFSET 0x2040
+#define RK3576_SMT_GPIO1_OFFSET 0x6210
+#define RK3576_SMT_GPIO2_OFFSET 0x6220
+#define RK3576_SMT_GPIO3_OFFSET 0x6230
+#define RK3576_SMT_GPIO4_AL_OFFSET 0x6240
+#define RK3576_SMT_GPIO4_CL_OFFSET 0xA248
+#define RK3576_SMT_GPIO4_DL_OFFSET 0xB24C
+
+static void rk3576_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num,
+ struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ *regmap = priv->regmap_base;
+ if (bank->bank_num == 0 && pin_num < 12) {
+ *reg = RK3576_SMT_GPIO0_AL_OFFSET;
+ } else if (bank->bank_num == 0) {
+ *reg = RK3576_SMT_GPIO0_BH_OFFSET - 0x4;
+ } else if (bank->bank_num == 1) {
+ *reg = RK3576_SMT_GPIO1_OFFSET;
+ } else if (bank->bank_num == 2) {
+ *reg = RK3576_SMT_GPIO2_OFFSET;
+ } else if (bank->bank_num == 3) {
+ *reg = RK3576_SMT_GPIO3_OFFSET;
+ } else if (bank->bank_num == 4 && pin_num < 16) {
+ *reg = RK3576_SMT_GPIO4_AL_OFFSET;
+ } else if (bank->bank_num == 4 && pin_num < 24) {
+ *reg = RK3576_SMT_GPIO4_CL_OFFSET - 0x8;
+ } else if (bank->bank_num == 4) {
+ *reg = RK3576_SMT_GPIO4_DL_OFFSET - 0xc;
+ } else {
+ *reg = 0;
+ debug("unsupported bank_num %d\n", bank->bank_num);
+ }
+
+ *reg += ((pin_num / RK3576_SMT_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3576_SMT_PINS_PER_REG;
+ *bit *= RK3576_SMT_BITS_PER_PIN;
+}
+
+static int rk3576_set_schmitt(struct rockchip_pin_bank *bank,
+ int pin_num, int enable)
+{
+ struct regmap *regmap;
+ int reg;
+ u32 data, rmask;
+ u8 bit;
+
+ rk3576_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RK3576_SMT_BITS_PER_PIN) - 1) << (bit + 16);
+ rmask = data | (data >> 16);
+ data |= (enable << bit);
+
+ return regmap_update_bits(regmap, reg, rmask, data);
+}
+
+static struct rockchip_pin_bank rk3576_pin_banks[] = {
+ RK3576_PIN_BANK_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_4BIT,
+ 0, 0x8, 0x2004, 0x200C),
+ RK3576_PIN_BANK_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
+ 0x4020, 0x4028, 0x4030, 0x4038),
+ RK3576_PIN_BANK_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
+ 0x4040, 0x4048, 0x4050, 0x4058),
+ RK3576_PIN_BANK_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
+ 0x4060, 0x4068, 0x4070, 0x4078),
+ RK3576_PIN_BANK_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
+ 0x4080, 0x4088, 0xA390, 0xB398),
+};
+
+static const struct rockchip_pin_ctrl rk3576_pin_ctrl = {
+ .pin_banks = rk3576_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3576_pin_banks),
+ .grf_mux_offset = 0x0,
+ .set_mux = rk3576_set_mux,
+ .set_pull = rk3576_set_pull,
+ .set_drive = rk3576_set_drive,
+ .set_schmitt = rk3576_set_schmitt,
+};
+
+static const struct udevice_id rk3576_pinctrl_ids[] = {
+ {
+ .compatible = "rockchip,rk3576-pinctrl",
+ .data = (ulong)&rk3576_pin_ctrl
+ },
+ { }
+};
+
+U_BOOT_DRIVER(pinctrl_rk3576) = {
+ .name = "rockchip_rk3576_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = rk3576_pinctrl_ids,
+ .priv_auto = sizeof(struct rockchip_pinctrl_priv),
+ .ops = &rockchip_pinctrl_ops,
+#if CONFIG_IS_ENABLED(OF_REAL)
+ .bind = dm_scan_fdt_dev,
+#endif
+ .probe = rockchip_pinctrl_probe,
+};
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/drivers/pinctrl/rockchip/pinctrl-rockchip.h
index df7bc68..5e3c9c9 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h
@@ -458,6 +458,9 @@
#define MR_PMUGRF(ID, PIN, FUNC, REG, VAL) \
PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_PMUGRF)
+#define RK3576_PIN_BANK_FLAGS(ID, PIN, LABEL, M, O1, O2, O3, O4) \
+ PIN_BANK_IOMUX_FLAGS_OFFSET(ID, PIN, LABEL, M, M, M, M, O1, O2, O3, O4)
+
#define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \
PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P)
diff --git a/drivers/pinctrl/tegra/funcmux-tegra20.c b/drivers/pinctrl/tegra/funcmux-tegra20.c
index 951ae19..f60d5aa 100644
--- a/drivers/pinctrl/tegra/funcmux-tegra20.c
+++ b/drivers/pinctrl/tegra/funcmux-tegra20.c
@@ -62,8 +62,15 @@
pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
bad_config = 0;
break;
+ case FUNCMUX_UART1_SDB_SDD:
+ pinmux_set_func(PMUX_PINGRP_SDB, PMUX_FUNC_UARTA);
+ pinmux_set_func(PMUX_PINGRP_SDD, PMUX_FUNC_UARTA);
+ pinmux_tristate_disable(PMUX_PINGRP_SDB);
+ pinmux_tristate_disable(PMUX_PINGRP_SDD);
+ bad_config = 0;
+ break;
}
- if (!bad_config) {
+ if (!bad_config && config != FUNCMUX_UART1_SDB_SDD) {
/*
* Tegra appears to boot with function UARTA pre-
* selected on mux group SDB. If two mux groups are
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
index b04be16..bc02825 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
@@ -14,7 +14,7 @@
static void tegra_pinctrl_set_drive(struct udevice *config, int drvcnt)
{
struct pmux_drvgrp_config *drive_group;
- int i, ret, pad_id;
+ int i, ret, pad_id, count = 0;
const char **pads;
drive_group = kmalloc_array(drvcnt, sizeof(*drive_group), GFP_KERNEL);
@@ -46,21 +46,32 @@
goto exit;
}
+ /*
+ * i goes through all drive instances defined, while
+ * count is increased only if a valid configuration is found
+ */
for (i = 0; i < drvcnt; i++) {
for (pad_id = 0; pad_id < PMUX_DRVGRP_COUNT; pad_id++)
if (tegra_pinctrl_to_drvgrp[pad_id])
if (!strcmp(pads[i], tegra_pinctrl_to_drvgrp[pad_id])) {
- drive_group[i].drvgrp = pad_id;
+ drive_group[count].drvgrp = pad_id;
break;
}
- debug("%s drvmap: %d, %d, %d, %d, %d\n", pads[i],
- drive_group[i].drvgrp, drive_group[i].slwf,
- drive_group[i].slwr, drive_group[i].drvup,
- drive_group[i].drvdn);
+ if (pad_id == PMUX_DRVGRP_COUNT) {
+ log_debug("%s: drive %s is not valid\n", __func__, pads[i]);
+ continue;
+ }
+
+ log_debug("%s(%d) drvmap: %d, %d, %d, %d, %d\n", pads[count], count,
+ drive_group[count].drvgrp, drive_group[count].slwf,
+ drive_group[count].slwr, drive_group[count].drvup,
+ drive_group[count].drvdn);
+
+ count++;
}
- pinmux_config_drvgrp_table(drive_group, drvcnt);
+ pinmux_config_drvgrp_table(drive_group, count);
free(pads);
exit:
@@ -71,7 +82,7 @@
static void tegra_pinctrl_set_mipipad(struct udevice *config, int padcnt)
{
struct pmux_mipipadctrlgrp_config *mipipad_group;
- int i, ret, pad_id;
+ int i, ret, pad_id, count = 0;
const char *function;
const char **pads;
@@ -89,6 +100,11 @@
if (!strcmp(function, tegra_pinctrl_to_func[i]))
break;
+ if (!function || i == PMUX_FUNC_COUNT) {
+ log_debug("%s: pin function is not defined or is not valid\n", __func__);
+ goto exit;
+ }
+
mipipad_group[0].func = i;
for (i = 1; i < padcnt; i++)
@@ -100,16 +116,27 @@
goto exit;
}
+ /*
+ * i goes through all pin instances defined, while
+ * count is increased only if a valid configuration is found
+ */
for (i = 0; i < padcnt; i++) {
for (pad_id = 0; pad_id < PMUX_MIPIPADCTRLGRP_COUNT; pad_id++)
if (tegra_pinctrl_to_mipipadgrp[pad_id])
if (!strcmp(pads[i], tegra_pinctrl_to_mipipadgrp[pad_id])) {
- mipipad_group[i].grp = pad_id;
+ mipipad_group[count].grp = pad_id;
break;
}
+
+ if (pad_id == PMUX_MIPIPADCTRLGRP_COUNT) {
+ log_debug("%s: drive %s is not valid\n", __func__, pads[i]);
+ continue;
+ }
+
+ count++;
}
- pinmux_config_mipipadctrlgrp_table(mipipad_group, padcnt);
+ pinmux_config_mipipadctrlgrp_table(mipipad_group, count);
free(pads);
exit:
@@ -122,7 +149,7 @@
static void tegra_pinctrl_set_pin(struct udevice *config, int pincnt)
{
struct pmux_pingrp_config *pinmux_group;
- int i, ret, pin_id;
+ int i, ret, pin_id, count = 0;
const char *function;
const char **pins;
@@ -140,6 +167,11 @@
if (!strcmp(function, tegra_pinctrl_to_func[i]))
break;
+ if (!function || i == PMUX_FUNC_COUNT) {
+ log_debug("%s: pin function is not defined or is not valid\n", __func__);
+ goto exit;
+ }
+
pinmux_group[0].func = i;
pinmux_group[0].pull = dev_read_u32_default(config, "nvidia,pull", PMUX_PULL_NORMAL);
@@ -178,20 +210,31 @@
goto exit;
}
+ /*
+ * i goes through all pin instances defined, while
+ * count is increased only if a valid configuration is found
+ */
for (i = 0; i < pincnt; i++) {
for (pin_id = 0; pin_id < PMUX_PINGRP_COUNT; pin_id++)
if (tegra_pinctrl_to_pingrp[pin_id])
if (!strcmp(pins[i], tegra_pinctrl_to_pingrp[pin_id])) {
- pinmux_group[i].pingrp = pin_id;
+ pinmux_group[count].pingrp = pin_id;
break;
}
+ if (pin_id == PMUX_PINGRP_COUNT) {
+ log_debug("%s: pin %s is not valid\n", __func__, pins[i]);
+ continue;
+ }
+
- debug("%s pinmap: %d, %d, %d, %d\n", pins[i],
- pinmux_group[i].pingrp, pinmux_group[i].func,
- pinmux_group[i].pull, pinmux_group[i].tristate);
+ log_debug("%s(%d) pinmap: %d, %d, %d, %d\n", pins[count], count,
+ pinmux_group[count].pingrp, pinmux_group[count].func,
+ pinmux_group[count].pull, pinmux_group[count].tristate);
+
+ count++;
}
- pinmux_config_pingrp_table(pinmux_group, pincnt);
+ pinmux_config_pingrp_table(pinmux_group, count);
free(pins);
exit:
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra20.c b/drivers/pinctrl/tegra/pinctrl-tegra20.c
index d59b3ec..c32d590 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra20.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra20.c
@@ -37,6 +37,11 @@
if (!strcmp(pins[i], tegra_pinctrl_to_pingrp[pin_id]))
break;
+ if (pin_id == PMUX_PINGRP_COUNT) {
+ log_debug("%s: %s(%d) is not valid\n", __func__, pins[i], pin_id);
+ continue;
+ }
+
if (pull >= 0)
pinmux_set_pullupdown(pin_id, pull);
@@ -58,13 +63,16 @@
const char **pins;
function = dev_read_string(config, "nvidia,function");
- if (function)
+ if (function) {
for (i = 0; i < PMUX_FUNC_COUNT; i++)
if (tegra_pinctrl_to_func[i])
if (!strcmp(function, tegra_pinctrl_to_func[i]))
break;
- func_id = i;
+ func_id = i;
+ } else {
+ func_id = PMUX_FUNC_COUNT;
+ }
count = dev_read_string_list(config, "nvidia,pins", &pins);
if (count < 0) {
@@ -78,6 +86,12 @@
if (!strcmp(pins[i], tegra_pinctrl_to_pingrp[pin_id]))
break;
+ if (func_id == PMUX_FUNC_COUNT || pin_id == PMUX_PINGRP_COUNT) {
+ log_debug("%s: pin %s(%d) or function %s(%d) is not valid\n",
+ __func__, pins[i], pin_id, function, func_id);
+ continue;
+ }
+
debug("%s(%d) muxed to %s(%d)\n", pins[i], pin_id, function, func_id);
pinmux_set_func(pin_id, func_id);
diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
index bd82d2f..5f5218b 100644
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -47,6 +47,13 @@
help
Enable support for manipulating NXP i.MX8MP on-SoC HSIOMIX block controller.
+config IMX8MP_MEDIAMIX_BLKCTRL
+ bool "Enable i.MX8MP MEDIAMIX domain driver"
+ depends on POWER_DOMAIN && IMX8MP
+ select CLK
+ help
+ Enable support for manipulating NXP i.MX8MP on-SoC MEDIAMIX block controller.
+
config MTK_POWER_DOMAIN
bool "Enable the MediaTek power domain driver"
depends on POWER_DOMAIN && ARCH_MEDIATEK
diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
index 110646c..4d20c97 100644
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@@ -3,12 +3,13 @@
# Copyright (c) 2016, NVIDIA CORPORATION.
#
-obj-$(CONFIG_$(XPL_)POWER_DOMAIN) += power-domain-uclass.o
+obj-$(CONFIG_$(PHASE_)POWER_DOMAIN) += power-domain-uclass.o
obj-$(CONFIG_APPLE_PMGR_POWER_DOMAIN) += apple-pmgr.o
obj-$(CONFIG_BCM6328_POWER_DOMAIN) += bcm6328-power-domain.o
obj-$(CONFIG_IMX8_POWER_DOMAIN) += imx8-power-domain-legacy.o imx8-power-domain.o
obj-$(CONFIG_IMX8M_POWER_DOMAIN) += imx8m-power-domain.o
obj-$(CONFIG_IMX8MP_HSIOMIX_BLKCTRL) += imx8mp-hsiomix.o
+obj-$(CONFIG_IMX8MP_MEDIAMIX_BLKCTRL) += imx8mp-mediamix.o
obj-$(CONFIG_MTK_POWER_DOMAIN) += mtk-power-domain.o
obj-$(CONFIG_MESON_GX_VPU_POWER_DOMAIN) += meson-gx-pwrc-vpu.o
obj-$(CONFIG_MESON_EE_POWER_DOMAIN) += meson-ee-pwrc.o
diff --git a/drivers/power/domain/imx8m-power-domain.c b/drivers/power/domain/imx8m-power-domain.c
index c22fbe6..b44aae7 100644
--- a/drivers/power/domain/imx8m-power-domain.c
+++ b/drivers/power/domain/imx8m-power-domain.c
@@ -40,6 +40,7 @@
#define IMX8MN_MIPI_A53_DOMAIN BIT(2)
#define IMX8MP_HSIOMIX_A53_DOMAIN BIT(19)
+#define IMX8MP_MEDIAMIX_A53_DOMAIN BIT(12)
#define IMX8MP_USB2_PHY_A53_DOMAIN BIT(5)
#define IMX8MP_USB1_PHY_A53_DOMAIN BIT(4)
#define IMX8MP_PCIE_PHY_A53_DOMAIN BIT(3)
@@ -63,6 +64,7 @@
#define IMX8MN_MIPI_SW_Pxx_REQ BIT(0)
#define IMX8MP_HSIOMIX_Pxx_REQ BIT(17)
+#define IMX8MP_MEDIAMIX_Pxx_REQ BIT(10)
#define IMX8MP_USB2_PHY_Pxx_REQ BIT(3)
#define IMX8MP_USB1_PHY_Pxx_REQ BIT(2)
#define IMX8MP_PCIE_PHY_SW_Pxx_REQ BIT(1)
@@ -81,6 +83,9 @@
#define IMX8MP_HSIOMIX_PWRDNACKN BIT(28)
#define IMX8MP_HSIOMIX_PWRDNREQN BIT(12)
+#define IMX8MP_MEDIAMIX_PWRDNACKN BIT(30)
+#define IMX8MP_MEDIAMIX_PWRDNREQN BIT(14)
+
/*
* The PGC offset values in Reference Manual
* (Rev. 1, 01/2018 and the older ones) GPC chapter's
@@ -101,6 +106,7 @@
#define IMX8MP_PGC_PCIE 13
#define IMX8MP_PGC_USB1 14
#define IMX8MP_PGC_USB2 15
+#define IMX8MP_PGC_MEDIAMIX 22
#define IMX8MP_PGC_HSIOMIX 29
#define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
@@ -303,6 +309,17 @@
.pgc = BIT(IMX8MP_PGC_HSIOMIX),
.keep_clocks = true,
},
+
+ [IMX8MP_POWER_DOMAIN_MEDIAMIX] = {
+ .bits = {
+ .pxx = IMX8MP_MEDIAMIX_Pxx_REQ,
+ .map = IMX8MP_MEDIAMIX_A53_DOMAIN,
+ .hskreq = IMX8MP_MEDIAMIX_PWRDNREQN,
+ .hskack = IMX8MP_MEDIAMIX_PWRDNACKN,
+ },
+ .pgc = BIT(IMX8MP_PGC_MEDIAMIX),
+ .keep_clocks = true,
+ },
};
static const struct imx_pgc_regs imx8mp_pgc_regs = {
@@ -489,8 +506,12 @@
static int imx8m_power_domain_probe(struct udevice *dev)
{
struct imx8m_power_domain_plat *pdata = dev_get_plat(dev);
+ struct power_domain_plat *plat = dev_get_uclass_plat(dev);
int ret;
+ /* Every subdomain has its own device node */
+ plat->subdomains = 1;
+
/* Nothing to do for non-"power-domain" driver instances. */
if (!strstr(dev->name, "power-domain"))
return 0;
diff --git a/drivers/power/domain/imx8mp-hsiomix.c b/drivers/power/domain/imx8mp-hsiomix.c
index 455ad53..1ca4388 100644
--- a/drivers/power/domain/imx8mp-hsiomix.c
+++ b/drivers/power/domain/imx8mp-hsiomix.c
@@ -201,8 +201,12 @@
static int imx8mp_hsiomix_probe(struct udevice *dev)
{
struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev);
+ struct power_domain_plat *plat = dev_get_uclass_plat(dev);
int ret;
+ /* Definitions are in imx8mp-power.h */
+ plat->subdomains = 5;
+
priv->base = dev_read_addr_ptr(dev);
ret = clk_get_by_name(dev, "usb", &priv->clk_usb);
diff --git a/drivers/power/domain/imx8mp-mediamix.c b/drivers/power/domain/imx8mp-mediamix.c
new file mode 100644
index 0000000..504c22f
--- /dev/null
+++ b/drivers/power/domain/imx8mp-mediamix.c
@@ -0,0 +1,212 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * i.MX8 MEDIAMIX control block driver
+ * Copyright (C) 2024 Miquel Raynal <miquel.raynal@bootlin.com>
+ * Inspired from Marek Vasut <marex@denx.de> work on the hsiomix driver.
+ */
+
+#include <asm/io.h>
+#include <clk.h>
+#include <dm.h>
+#include <power-domain-uclass.h>
+#include <linux/delay.h>
+
+#include <dt-bindings/power/imx8mp-power.h>
+
+#define BLK_SFT_RSTN 0x0
+#define BLK_CLK_EN 0x4
+
+struct imx8mp_mediamix_priv {
+ void __iomem *base;
+ struct clk clk_apb;
+ struct clk clk_axi;
+ struct clk clk_disp2;
+ struct power_domain pd_bus;
+ struct power_domain pd_lcdif2;
+};
+
+static int imx8mp_mediamix_on(struct power_domain *power_domain)
+{
+ struct udevice *dev = power_domain->dev;
+ struct imx8mp_mediamix_priv *priv = dev_get_priv(dev);
+ struct power_domain *domain;
+ struct clk *clk;
+ u32 reset;
+ int ret;
+
+ switch (power_domain->id) {
+ case IMX8MP_MEDIABLK_PD_LCDIF_2:
+ domain = &priv->pd_lcdif2;
+ clk = &priv->clk_disp2;
+ reset = BIT(11) | BIT(12) | BIT(24);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* Make sure bus domain is awake */
+ ret = power_domain_on(&priv->pd_bus);
+ if (ret)
+ return ret;
+
+ /* Put devices into reset */
+ clrbits_le32(priv->base + BLK_SFT_RSTN, reset);
+
+ /* Enable upstream clocks */
+ ret = clk_enable(&priv->clk_apb);
+ if (ret)
+ goto dis_bus_pd;
+
+ ret = clk_enable(&priv->clk_axi);
+ if (ret)
+ goto dis_apb_clk;
+
+ /* Enable blk-ctrl clock to allow reset to propagate */
+ ret = clk_enable(clk);
+ if (ret)
+ goto dis_axi_clk;
+ setbits_le32(priv->base + BLK_CLK_EN, reset);
+
+ /* Power up upstream GPC domain */
+ ret = power_domain_on(domain);
+ if (ret)
+ goto dis_lcdif_clk;
+
+ /* Wait for reset to propagate */
+ udelay(5);
+
+ /* Release reset */
+ setbits_le32(priv->base + BLK_SFT_RSTN, reset);
+
+ return 0;
+
+dis_lcdif_clk:
+ clk_disable(clk);
+dis_axi_clk:
+ clk_disable(&priv->clk_axi);
+dis_apb_clk:
+ clk_disable(&priv->clk_apb);
+dis_bus_pd:
+ power_domain_off(&priv->pd_bus);
+
+ return ret;
+}
+
+static int imx8mp_mediamix_off(struct power_domain *power_domain)
+{
+ struct udevice *dev = power_domain->dev;
+ struct imx8mp_mediamix_priv *priv = dev_get_priv(dev);
+ struct power_domain *domain;
+ struct clk *clk;
+ u32 reset;
+
+ switch (power_domain->id) {
+ case IMX8MP_MEDIABLK_PD_LCDIF_2:
+ domain = &priv->pd_lcdif2;
+ clk = &priv->clk_disp2;
+ reset = BIT(11) | BIT(12) | BIT(24);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* Put devices into reset and disable clocks */
+ clrbits_le32(priv->base + BLK_SFT_RSTN, reset);
+ clrbits_le32(priv->base + BLK_CLK_EN, reset);
+
+ /* Power down upstream GPC domain */
+ power_domain_off(domain);
+
+ clk_disable(clk);
+ clk_disable(&priv->clk_axi);
+ clk_disable(&priv->clk_apb);
+
+ /* Allow bus domain to suspend */
+ power_domain_off(&priv->pd_bus);
+
+ return 0;
+}
+
+static int imx8mp_mediamix_of_xlate(struct power_domain *power_domain,
+ struct ofnode_phandle_args *args)
+{
+ power_domain->id = args->args[0];
+
+ return 0;
+}
+
+static int imx8mp_mediamix_bind(struct udevice *dev)
+{
+ /* Bind child lcdif */
+ return dm_scan_fdt_dev(dev);
+}
+
+static int imx8mp_mediamix_probe(struct udevice *dev)
+{
+ struct power_domain_plat *plat = dev_get_uclass_plat(dev);
+ struct imx8mp_mediamix_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ /* Definitions are in imx8mp-power.h */
+ plat->subdomains = 9;
+
+ priv->base = dev_read_addr_ptr(dev);
+
+ ret = clk_get_by_name(dev, "apb", &priv->clk_apb);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_get_by_name(dev, "axi", &priv->clk_axi);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_get_by_name(dev, "disp2", &priv->clk_disp2);
+ if (ret < 0)
+ return ret;
+
+ ret = power_domain_get_by_name(dev, &priv->pd_bus, "bus");
+ if (ret < 0)
+ return ret;
+
+ ret = power_domain_get_by_name(dev, &priv->pd_lcdif2, "lcdif2");
+ if (ret < 0)
+ goto free_bus_pd;
+
+ return 0;
+
+free_bus_pd:
+ power_domain_free(&priv->pd_bus);
+ return ret;
+}
+
+static int imx8mp_mediamix_remove(struct udevice *dev)
+{
+ struct imx8mp_mediamix_priv *priv = dev_get_priv(dev);
+
+ power_domain_free(&priv->pd_lcdif2);
+ power_domain_free(&priv->pd_bus);
+
+ return 0;
+}
+
+static const struct udevice_id imx8mp_mediamix_ids[] = {
+ { .compatible = "fsl,imx8mp-media-blk-ctrl" },
+ { }
+};
+
+struct power_domain_ops imx8mp_mediamix_ops = {
+ .on = imx8mp_mediamix_on,
+ .off = imx8mp_mediamix_off,
+ .of_xlate = imx8mp_mediamix_of_xlate,
+};
+
+U_BOOT_DRIVER(imx8mp_mediamix) = {
+ .name = "imx8mp_mediamix",
+ .id = UCLASS_POWER_DOMAIN,
+ .of_match = imx8mp_mediamix_ids,
+ .bind = imx8mp_mediamix_bind,
+ .probe = imx8mp_mediamix_probe,
+ .remove = imx8mp_mediamix_remove,
+ .priv_auto = sizeof(struct imx8mp_mediamix_priv),
+ .ops = &imx8mp_mediamix_ops,
+};
diff --git a/drivers/power/domain/power-domain-uclass.c b/drivers/power/domain/power-domain-uclass.c
index 938bd8c..d9fa8ad 100644
--- a/drivers/power/domain/power-domain-uclass.c
+++ b/drivers/power/domain/power-domain-uclass.c
@@ -12,6 +12,10 @@
#include <power-domain-uclass.h>
#include <dm/device-internal.h>
+struct power_domain_priv {
+ int *on_count;
+};
+
static inline struct power_domain_ops *power_domain_dev_ops(struct udevice *dev)
{
return (struct power_domain_ops *)dev->driver->ops;
@@ -107,22 +111,67 @@
return ops->rfree ? ops->rfree(power_domain) : 0;
}
-int power_domain_on(struct power_domain *power_domain)
+int power_domain_on_lowlevel(struct power_domain *power_domain)
{
+ struct power_domain_priv *priv = dev_get_uclass_priv(power_domain->dev);
+ struct power_domain_plat *plat = dev_get_uclass_plat(power_domain->dev);
struct power_domain_ops *ops = power_domain_dev_ops(power_domain->dev);
+ int *on_count = plat->subdomains ? &priv->on_count[power_domain->id] : NULL;
+ int ret;
- debug("%s(power_domain=%p)\n", __func__, power_domain);
+ /* Refcounting is not enabled on all drivers by default */
+ if (on_count) {
+ debug("Enable power domain %s.%ld: %d -> %d (%s)\n",
+ power_domain->dev->name, power_domain->id, *on_count, *on_count + 1,
+ (((*on_count + 1) > 1) ? "EALREADY" : "todo"));
+
+ (*on_count)++;
+ if (*on_count > 1)
+ return -EALREADY;
+ }
- return ops->on ? ops->on(power_domain) : 0;
+ ret = ops->on ? ops->on(power_domain) : 0;
+ if (ret) {
+ if (on_count)
+ (*on_count)--;
+ return ret;
+ }
+
+ return 0;
}
-int power_domain_off(struct power_domain *power_domain)
+int power_domain_off_lowlevel(struct power_domain *power_domain)
{
+ struct power_domain_priv *priv = dev_get_uclass_priv(power_domain->dev);
+ struct power_domain_plat *plat = dev_get_uclass_plat(power_domain->dev);
struct power_domain_ops *ops = power_domain_dev_ops(power_domain->dev);
+ int *on_count = plat->subdomains ? &priv->on_count[power_domain->id] : NULL;
+ int ret;
- debug("%s(power_domain=%p)\n", __func__, power_domain);
+ /* Refcounting is not enabled on all drivers by default */
+ if (on_count) {
+ debug("Disable power domain %s.%ld: %d -> %d (%s%s)\n",
+ power_domain->dev->name, power_domain->id, *on_count, *on_count - 1,
+ (((*on_count) <= 0) ? "EALREADY" : ""),
+ (((*on_count - 1) > 0) ? "BUSY" : "todo"));
+
+ if (*on_count <= 0)
+ return -EALREADY;
+
+ (*on_count)--;
+ if (*on_count > 0)
+ return -EBUSY;
+ }
+
+ ret = ops->off ? ops->off(power_domain) : 0;
+ if (ret) {
+ if (on_count)
+ (*on_count)++;
- return ops->off ? ops->off(power_domain) : 0;
+ return ret;
+ }
+
+ return 0;
}
#if CONFIG_IS_ENABLED(OF_REAL)
@@ -177,7 +226,36 @@
}
#endif /* OF_REAL */
+static int power_domain_post_probe(struct udevice *dev)
+{
+ struct power_domain_priv *priv = dev_get_uclass_priv(dev);
+ struct power_domain_plat *plat = dev_get_uclass_plat(dev);
+
+ if (plat->subdomains) {
+ priv->on_count = calloc(sizeof(int), plat->subdomains);
+ if (!priv->on_count)
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+static int power_domain_pre_remove(struct udevice *dev)
+{
+ struct power_domain_priv *priv = dev_get_uclass_priv(dev);
+ struct power_domain_plat *plat = dev_get_uclass_plat(dev);
+
+ if (plat->subdomains)
+ free(priv->on_count);
+
+ return 0;
+}
+
UCLASS_DRIVER(power_domain) = {
.id = UCLASS_POWER_DOMAIN,
.name = "power_domain",
+ .post_probe = power_domain_post_probe,
+ .pre_remove = power_domain_pre_remove,
+ .per_device_auto = sizeof(struct power_domain_priv),
+ .per_device_plat_auto = sizeof(struct power_domain_plat),
};
diff --git a/drivers/power/domain/sandbox-power-domain-test.c b/drivers/power/domain/sandbox-power-domain-test.c
index 08c15ef..df06300 100644
--- a/drivers/power/domain/sandbox-power-domain-test.c
+++ b/drivers/power/domain/sandbox-power-domain-test.c
@@ -34,6 +34,20 @@
return power_domain_off(&sbrt->pd);
}
+int sandbox_power_domain_test_on_ll(struct udevice *dev)
+{
+ struct sandbox_power_domain_test *sbrt = dev_get_priv(dev);
+
+ return power_domain_on_lowlevel(&sbrt->pd);
+}
+
+int sandbox_power_domain_test_off_ll(struct udevice *dev)
+{
+ struct sandbox_power_domain_test *sbrt = dev_get_priv(dev);
+
+ return power_domain_off_lowlevel(&sbrt->pd);
+}
+
int sandbox_power_domain_test_free(struct udevice *dev)
{
struct sandbox_power_domain_test *sbrt = dev_get_priv(dev);
@@ -51,4 +65,5 @@
.id = UCLASS_MISC,
.of_match = sandbox_power_domain_test_ids,
.priv_auto = sizeof(struct sandbox_power_domain_test),
+ .flags = DM_FLAG_DEFAULT_PD_CTRL_OFF,
};
diff --git a/drivers/power/domain/sandbox-power-domain.c b/drivers/power/domain/sandbox-power-domain.c
index 9dd490b..a803165 100644
--- a/drivers/power/domain/sandbox-power-domain.c
+++ b/drivers/power/domain/sandbox-power-domain.c
@@ -64,8 +64,12 @@
static int sandbox_power_domain_probe(struct udevice *dev)
{
+ struct power_domain_plat *plat = dev_get_uclass_plat(dev);
+
debug("%s(dev=%p)\n", __func__, dev);
+ plat->subdomains = 1;
+
return 0;
}
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index bbcbcee..5a61cd4 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -295,6 +295,16 @@
Driver binding info: doc/device-tree-bindings/pmic/sandbox.txt
+config DM_PMIC_CPCAP
+ bool "Enable Driver Model for Motorola CPCAP"
+ help
+ The CPCAP is a Motorola/ST-Ericsson creation, a multifunctional IC
+ whose main purpose is power control. It was used in a wide variety of
+ Motorola products, both Tegra and OMAP based. The most notable devices
+ using this PMIC are the Motorola Droid 4, Atrix 4G, and Droid X2.
+ Unlike most PMICs, this one is not I2C based; it uses the SPI bus. The
+ core driver provides both read and write access to the device registers.
+
config PMIC_S5M8767
bool "Enable Driver Model for the Samsung S5M8767 PMIC"
---help---
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index bc138f5..2210b1a 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -4,41 +4,42 @@
# Lukasz Majewski <l.majewski@samsung.com>
obj-$(CONFIG_$(PHASE_)DM_PMIC) += pmic-uclass.o
-obj-$(CONFIG_$(XPL_)DM_PMIC_FAN53555) += fan53555.o
-obj-$(CONFIG_$(XPL_)DM_PMIC_DA9063) += da9063.o
-obj-$(CONFIG_$(XPL_)DM_PMIC_MAX77663) += max77663.o
+obj-$(CONFIG_$(PHASE_)DM_PMIC_FAN53555) += fan53555.o
+obj-$(CONFIG_$(PHASE_)DM_PMIC_DA9063) += da9063.o
+obj-$(CONFIG_$(PHASE_)DM_PMIC_MAX77663) += max77663.o
obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o
obj-$(CONFIG_DM_PMIC_MC34708) += mc34708.o
-obj-$(CONFIG_$(XPL_)DM_PMIC_BD71837) += bd71837.o
-obj-$(CONFIG_$(XPL_)DM_PMIC_MP5416) += mp5416.o
-obj-$(CONFIG_$(XPL_)DM_PMIC_PFUZE100) += pfuze100.o
-obj-$(CONFIG_$(XPL_)DM_PMIC_PCA9450) += pca9450.o
+obj-$(CONFIG_$(PHASE_)DM_PMIC_BD71837) += bd71837.o
+obj-$(CONFIG_$(PHASE_)DM_PMIC_MP5416) += mp5416.o
+obj-$(CONFIG_$(PHASE_)DM_PMIC_PFUZE100) += pfuze100.o
+obj-$(CONFIG_$(PHASE_)DM_PMIC_PCA9450) += pca9450.o
obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o
obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
obj-$(CONFIG_PMIC_AB8500) += ab8500.o
obj-$(CONFIG_PMIC_ACT8846) += act8846.o
obj-$(CONFIG_PMIC_AS3722) += as3722.o as3722_gpio.o
-obj-$(CONFIG_$(XPL_)PMIC_AXP) += axp.o
+obj-$(CONFIG_$(PHASE_)PMIC_AXP) += axp.o
obj-$(CONFIG_PMIC_MAX8997) += max8997.o
obj-$(CONFIG_PMIC_QCOM) += pmic_qcom.o
obj-$(CONFIG_$(PHASE_)PMIC_RK8XX) += rk8xx.o
-obj-$(CONFIG_$(XPL_)PMIC_RN5T567) += rn5t567.o
+obj-$(CONFIG_$(PHASE_)PMIC_RN5T567) += rn5t567.o
obj-$(CONFIG_PMIC_TPS65090) += tps65090.o
obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o
obj-$(CONFIG_DM_PMIC_TPS65910) += pmic_tps65910_dm.o
-obj-$(CONFIG_$(XPL_)DM_PMIC_TPS80031) += tps80031.o
-obj-$(CONFIG_$(XPL_)PMIC_PALMAS) += palmas.o
-obj-$(CONFIG_$(XPL_)PMIC_LP873X) += lp873x.o
-obj-$(CONFIG_$(XPL_)PMIC_LP87565) += lp87565.o
+obj-$(CONFIG_$(PHASE_)DM_PMIC_TPS80031) += tps80031.o
+obj-$(CONFIG_$(PHASE_)PMIC_PALMAS) += palmas.o
+obj-$(CONFIG_$(PHASE_)PMIC_LP873X) += lp873x.o
+obj-$(CONFIG_$(PHASE_)PMIC_LP87565) += lp87565.o
obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o
obj-$(CONFIG_PMIC_TPS65217) += pmic_tps65217.o
obj-$(CONFIG_PMIC_TPS65219) += tps65219.o
obj-$(CONFIG_PMIC_TPS65941) += tps65941.o
obj-$(CONFIG_PMIC_RAA215300) += raa215300.o
obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
+obj-$(CONFIG_$(PHASE_)DM_PMIC_CPCAP) += cpcap.o
-ifeq ($(CONFIG_$(XPL_)POWER_LEGACY),y)
+ifeq ($(CONFIG_$(PHASE_)POWER_LEGACY),y)
obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o
obj-$(CONFIG_POWER_PCA9450) += pmic_pca9450.o
obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
@@ -47,5 +48,5 @@
obj-$(CONFIG_POWER_MC34VR500) += pmic_mc34vr500.o
endif
-obj-$(CONFIG_$(XPL_)POWER_TPS62362) += pmic_tps62362.o
+obj-$(CONFIG_$(PHASE_)POWER_TPS62362) += pmic_tps62362.o
obj-$(CONFIG_SPL_POWER_TPS65910) += pmic_tps65910.o
diff --git a/drivers/power/pmic/axp.c b/drivers/power/pmic/axp.c
index 521a39d..c300fd2 100644
--- a/drivers/power/pmic/axp.c
+++ b/drivers/power/pmic/axp.c
@@ -51,6 +51,7 @@
{ "cldo", "axp_regulator" },
{ "dc", "axp_regulator" },
{ "dldo", "axp_regulator" },
+ { "drivevbus", "axp_drivevbus" },
{ "eldo", "axp_regulator" },
{ "fldo", "axp_regulator" },
{ "ldo", "axp_regulator" },
diff --git a/drivers/power/pmic/cpcap.c b/drivers/power/pmic/cpcap.c
new file mode 100644
index 0000000..f2076af
--- /dev/null
+++ b/drivers/power/pmic/cpcap.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2025 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+#include <dm/lists.h>
+#include <log.h>
+#include <power/pmic.h>
+#include <power/cpcap.h>
+#include <spi.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+
+static const struct pmic_child_info pmic_children_info[] = {
+ { .prefix = "sw", .driver = CPCAP_SW_DRIVER },
+ { .prefix = "v", .driver = CPCAP_LDO_DRIVER },
+ { },
+};
+
+static int cpcap_write(struct udevice *dev, uint reg, const uint8_t *buff, int len)
+{
+ u8 buf[4];
+ u16 data = *(u16 *)buff;
+ int ret;
+
+ buf[0] = ((reg >> 8) & 0xff) | 0x80;
+ buf[1] = reg & 0xff;
+ buf[2] = data >> 8 & 0xff;
+ buf[3] = data & 0xff;
+
+ ret = dm_spi_xfer(dev, 32, buf, NULL, SPI_XFER_ONCE);
+
+ log_debug("%s: reg 0x%x, data 0x%04x, ret %d\n", __func__, reg, data, ret);
+
+ return ret;
+}
+
+static int cpcap_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+ u8 buf[4];
+ int ret;
+
+ buf[0] = (reg >> 8) & 0xff;
+ buf[1] = reg & 0xff;
+ buf[2] = 0;
+ buf[3] = 0;
+
+ ret = dm_spi_xfer(dev, 32, buf, buf, SPI_XFER_ONCE);
+ *buff = (buf[2] << 8) | buf[3];
+
+ log_debug("%s: reg 0x%x, data 0x%04x, ret %d\n", __func__, reg, *buff, ret);
+ return ret;
+}
+
+static int cpcap_bind(struct udevice *dev)
+{
+ ofnode regulators_node;
+ int children;
+
+ /* Regulator device node of PMIC */
+ regulators_node = dev_read_subnode(dev, "regulator");
+ if (!ofnode_valid(regulators_node)) {
+ log_err("%s regulator subnode not found!\n", dev->name);
+ return -ENXIO;
+ }
+
+ /* Actual regulators container */
+ regulators_node = ofnode_find_subnode(regulators_node, "regulators");
+ if (!ofnode_valid(regulators_node)) {
+ log_err("%s regulators subnode not found!\n", dev->name);
+ return -ENXIO;
+ }
+
+ debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
+
+ children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+ if (!children)
+ log_err("%s - no child found\n", dev->name);
+
+ return dm_scan_fdt_dev(dev);
+}
+
+static int cpcap_probe(struct udevice *dev)
+{
+ struct spi_slave *slave = dev_get_parent_priv(dev);
+ int ret;
+
+ ret = spi_claim_bus(slave);
+ if (ret) {
+ log_err("SPI bus allocation failed (%d)\n", ret);
+ return ret;
+ }
+
+ u16 id = pmic_reg_read(dev, CPCAP_REG_VERSC1);
+
+ u16 ven = (id >> 6) & 0x7;
+ u16 rev = ((id >> 3) & 0x7) | ((id << 3) & 0x38);
+
+ log_debug("%s: vendor %s rev: %i.%i (%x)\n", __func__,
+ ven == CPCAP_VENDOR_ST ? "ST" : "TI",
+ CPCAP_REVISION_MAJOR(rev), CPCAP_REVISION_MINOR(rev),
+ rev);
+ return 0;
+}
+
+static struct dm_pmic_ops cpcap_ops = {
+ .read = cpcap_read,
+ .write = cpcap_write,
+};
+
+static const struct udevice_id cpcap_ids[] = {
+ { .compatible = "motorola,cpcap" },
+ { .compatible = "st,6556002" },
+ { }
+};
+
+U_BOOT_DRIVER(pmic_cpcap) = {
+ .name = "cpcap_pmic",
+ .id = UCLASS_PMIC,
+ .of_match = cpcap_ids,
+ .bind = cpcap_bind,
+ .probe = cpcap_probe,
+ .ops = &cpcap_ops,
+};
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index bab6831..95912ef 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -57,6 +57,13 @@
Enable support in SPL for the regulators (DCDCs, LDOs) in the
X-Powers AXP152, AXP2xx, and AXP8xx PMICs.
+config REGULATOR_AXP_DRIVEVBUS
+ bool "Enable driver for X-Powers AXP PMIC drivevbus"
+ depends on DM_REGULATOR && PMIC_AXP
+ help
+ Enable support for sensing or driving the USB VBUS on
+ X-Powers AXP2xx and AXP8xx PMICs.
+
config REGULATOR_AXP_USB_POWER
bool "Enable driver for X-Powers AXP PMIC USB power supply"
depends on DM_REGULATOR && PMIC_AXP
@@ -493,3 +500,12 @@
Enable this option to support controlling the VBUS supply in
the USB PHY peripheral of the Renesas RZ/G2L SoC. This option
is required in order to use the USB OTG port.
+
+config DM_REGULATOR_CPCAP
+ bool "Enable driver for CPCAP PMIC regulators"
+ depends on DM_REGULATOR && DM_PMIC_CPCAP
+ ---help---
+ Enable implementation of driver-model regulator uclass features for
+ REGULATOR CPCAP. The driver supports both DC-to-DC Step-Down Switching
+ (SW) Regulators and Low-Dropout Linear (LDO) Regulators found in CPCAP
+ PMIC and implements get/set api for voltage and state.
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index 054a93e..0ee5d90 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -4,23 +4,24 @@
# Przemyslaw Marczak <p.marczak@samsung.com>
#
-obj-$(CONFIG_$(XPL_)DM_REGULATOR) += regulator-uclass.o
+obj-$(CONFIG_$(PHASE_)DM_REGULATOR) += regulator-uclass.o
obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o
-obj-$(CONFIG_$(XPL_)REGULATOR_AXP) += axp_regulator.o
-obj-$(CONFIG_$(XPL_)REGULATOR_AXP_USB_POWER) += axp_usb_power.o
-obj-$(CONFIG_$(XPL_)DM_REGULATOR_DA9063) += da9063.o
-obj-$(CONFIG_$(XPL_)DM_REGULATOR_MAX77663) += max77663_regulator.o
+obj-$(CONFIG_$(PHASE_)REGULATOR_AXP) += axp_regulator.o
+obj-$(CONFIG_$(PHASE_)REGULATOR_AXP_DRIVEVBUS) += axp_drivevbus.o
+obj-$(CONFIG_$(PHASE_)REGULATOR_AXP_USB_POWER) += axp_usb_power.o
+obj-$(CONFIG_$(PHASE_)DM_REGULATOR_DA9063) += da9063.o
+obj-$(CONFIG_$(PHASE_)DM_REGULATOR_MAX77663) += max77663_regulator.o
obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
obj-$(CONFIG_DM_REGULATOR_NPCM8XX) += npcm8xx_regulator.o
-obj-$(CONFIG_$(XPL_)DM_PMIC_PFUZE100) += pfuze100.o
-obj-$(CONFIG_$(XPL_)DM_REGULATOR_BD71837) += bd71837.o
-obj-$(CONFIG_$(XPL_)DM_REGULATOR_PCA9450) += pca9450.o
-obj-$(CONFIG_$(XPL_)REGULATOR_PWM) += pwm_regulator.o
-obj-$(CONFIG_$(XPL_)DM_REGULATOR_FAN53555) += fan53555.o
-obj-$(CONFIG_$(XPL_)DM_REGULATOR_COMMON) += regulator_common.o
-obj-$(CONFIG_$(XPL_)DM_REGULATOR_FIXED) += fixed.o
-obj-$(CONFIG_$(XPL_)DM_REGULATOR_GPIO) += gpio-regulator.o
+obj-$(CONFIG_$(PHASE_)DM_PMIC_PFUZE100) += pfuze100.o
+obj-$(CONFIG_$(PHASE_)DM_REGULATOR_BD71837) += bd71837.o
+obj-$(CONFIG_$(PHASE_)DM_REGULATOR_PCA9450) += pca9450.o
+obj-$(CONFIG_$(PHASE_)REGULATOR_PWM) += pwm_regulator.o
+obj-$(CONFIG_$(PHASE_)DM_REGULATOR_FAN53555) += fan53555.o
+obj-$(CONFIG_$(PHASE_)DM_REGULATOR_COMMON) += regulator_common.o
+obj-$(CONFIG_$(PHASE_)DM_REGULATOR_FIXED) += fixed.o
+obj-$(CONFIG_$(PHASE_)DM_REGULATOR_GPIO) += gpio-regulator.o
obj-$(CONFIG_DM_REGULATOR_QCOM_RPMH) += qcom-rpmh-regulator.o
obj-$(CONFIG_DM_REGULATOR_QCOM_USB_VBUS) += qcom_usb_vbus_regulator.o
obj-$(CONFIG_$(PHASE_)REGULATOR_RK8XX) += rk8xx.o
@@ -28,19 +29,20 @@
obj-$(CONFIG_REGULATOR_S5M8767) += s5m8767.o
obj-$(CONFIG_DM_REGULATOR_SANDBOX) += sandbox.o
obj-$(CONFIG_REGULATOR_TPS65090) += tps65090_regulator.o
-obj-$(CONFIG_$(XPL_)DM_REGULATOR_PALMAS) += palmas_regulator.o
-obj-$(CONFIG_$(XPL_)DM_REGULATOR_PBIAS) += pbias_regulator.o
-obj-$(CONFIG_$(XPL_)DM_REGULATOR_LP873X) += lp873x_regulator.o
-obj-$(CONFIG_$(XPL_)DM_REGULATOR_LP87565) += lp87565_regulator.o
-obj-$(CONFIG_$(XPL_)DM_REGULATOR_STM32_VREFBUF) += stm32-vrefbuf.o
+obj-$(CONFIG_$(PHASE_)DM_REGULATOR_PALMAS) += palmas_regulator.o
+obj-$(CONFIG_$(PHASE_)DM_REGULATOR_PBIAS) += pbias_regulator.o
+obj-$(CONFIG_$(PHASE_)DM_REGULATOR_LP873X) += lp873x_regulator.o
+obj-$(CONFIG_$(PHASE_)DM_REGULATOR_LP87565) += lp87565_regulator.o
+obj-$(CONFIG_$(PHASE_)DM_REGULATOR_STM32_VREFBUF) += stm32-vrefbuf.o
obj-$(CONFIG_DM_REGULATOR_TPS65910) += tps65910_regulator.o
-obj-$(CONFIG_$(XPL_)DM_REGULATOR_TPS65911) += tps65911_regulator.o
+obj-$(CONFIG_$(PHASE_)DM_REGULATOR_TPS65911) += tps65911_regulator.o
obj-$(CONFIG_DM_REGULATOR_TPS62360) += tps62360_regulator.o
-obj-$(CONFIG_$(XPL_)DM_REGULATOR_TPS6287X) += tps6287x_regulator.o
-obj-$(CONFIG_$(XPL_)DM_REGULATOR_TPS80031) += tps80031_regulator.o
-obj-$(CONFIG_$(XPL_)DM_REGULATOR_STPMIC1) += stpmic1.o
+obj-$(CONFIG_$(PHASE_)DM_REGULATOR_TPS6287X) += tps6287x_regulator.o
+obj-$(CONFIG_$(PHASE_)DM_REGULATOR_TPS80031) += tps80031_regulator.o
+obj-$(CONFIG_$(PHASE_)DM_REGULATOR_STPMIC1) += stpmic1.o
obj-$(CONFIG_DM_REGULATOR_TPS65941) += tps65941_regulator.o
obj-$(CONFIG_DM_REGULATOR_SCMI) += scmi_regulator.o
-obj-$(CONFIG_$(XPL_)DM_REGULATOR_ANATOP) += anatop_regulator.o
+obj-$(CONFIG_$(PHASE_)DM_REGULATOR_ANATOP) += anatop_regulator.o
obj-$(CONFIG_DM_REGULATOR_TPS65219) += tps65219_regulator.o
obj-$(CONFIG_REGULATOR_RZG2L_USBPHY) += rzg2l-usbphy-regulator.o
+obj-$(CONFIG_$(PHASE_)DM_REGULATOR_CPCAP) += cpcap_regulator.o
diff --git a/drivers/power/regulator/axp_drivevbus.c b/drivers/power/regulator/axp_drivevbus.c
new file mode 100644
index 0000000..c463de8
--- /dev/null
+++ b/drivers/power/regulator/axp_drivevbus.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <dm.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+
+#define AXP_VBUS_IPSOUT 0x30
+#define AXP_VBUS_IPSOUT_DRIVEBUS BIT(2)
+#define AXP_MISC_CTRL 0x8f
+#define AXP_MISC_CTRL_N_VBUSEN_FUNC BIT(4)
+
+static int axp_drivevbus_get_enable(struct udevice *dev)
+{
+ int ret;
+
+ ret = pmic_reg_read(dev->parent, AXP_VBUS_IPSOUT);
+ if (ret < 0)
+ return ret;
+
+ return !!(ret & AXP_VBUS_IPSOUT_DRIVEBUS);
+}
+
+static int axp_drivevbus_set_enable(struct udevice *dev, bool enable)
+{
+ return pmic_clrsetbits(dev->parent, AXP_VBUS_IPSOUT,
+ AXP_VBUS_IPSOUT_DRIVEBUS,
+ enable ? AXP_VBUS_IPSOUT_DRIVEBUS : 0);
+}
+
+static const struct dm_regulator_ops axp_drivevbus_ops = {
+ .get_enable = axp_drivevbus_get_enable,
+ .set_enable = axp_drivevbus_set_enable,
+};
+
+static int axp_drivevbus_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_plat *uc_plat = dev_get_uclass_plat(dev);
+ int ret;
+
+ uc_plat->type = REGULATOR_TYPE_FIXED;
+
+ if (dev_read_bool(dev->parent, "x-powers,drive-vbus-en")) {
+ ret = pmic_clrsetbits(dev->parent, AXP_MISC_CTRL,
+ AXP_MISC_CTRL_N_VBUSEN_FUNC, 0);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+U_BOOT_DRIVER(axp_drivevbus) = {
+ .name = "axp_drivevbus",
+ .id = UCLASS_REGULATOR,
+ .probe = axp_drivevbus_probe,
+ .ops = &axp_drivevbus_ops,
+};
diff --git a/drivers/power/regulator/cpcap_regulator.c b/drivers/power/regulator/cpcap_regulator.c
new file mode 100644
index 0000000..04cd665
--- /dev/null
+++ b/drivers/power/regulator/cpcap_regulator.c
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright(C) 2025 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/cpcap.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+
+/* CPCAP_REG_ASSIGN2 bits - Resource Assignment 2 */
+#define CPCAP_BIT_VSDIO_SEL BIT(15)
+#define CPCAP_BIT_VDIG_SEL BIT(14)
+#define CPCAP_BIT_VCAM_SEL BIT(13)
+#define CPCAP_BIT_SW6_SEL BIT(12)
+#define CPCAP_BIT_SW5_SEL BIT(11)
+#define CPCAP_BIT_SW4_SEL BIT(10)
+#define CPCAP_BIT_SW3_SEL BIT(9)
+#define CPCAP_BIT_SW2_SEL BIT(8)
+#define CPCAP_BIT_SW1_SEL BIT(7)
+
+/* CPCAP_REG_ASSIGN3 bits - Resource Assignment 3 */
+#define CPCAP_BIT_VUSBINT2_SEL BIT(15)
+#define CPCAP_BIT_VUSBINT1_SEL BIT(14)
+#define CPCAP_BIT_VVIB_SEL BIT(13)
+#define CPCAP_BIT_VWLAN1_SEL BIT(12)
+#define CPCAP_BIT_VRF1_SEL BIT(11)
+#define CPCAP_BIT_VHVIO_SEL BIT(10)
+#define CPCAP_BIT_VDAC_SEL BIT(9)
+#define CPCAP_BIT_VUSB_SEL BIT(8)
+#define CPCAP_BIT_VSIM_SEL BIT(7)
+#define CPCAP_BIT_VRFREF_SEL BIT(6)
+#define CPCAP_BIT_VPLL_SEL BIT(5)
+#define CPCAP_BIT_VFUSE_SEL BIT(4)
+#define CPCAP_BIT_VCSI_SEL BIT(3)
+#define CPCAP_BIT_SPARE_14_2 BIT(2)
+#define CPCAP_BIT_VWLAN2_SEL BIT(1)
+#define CPCAP_BIT_VRF2_SEL BIT(0)
+#define CPCAP_BIT_NONE 0
+
+/* CPCAP_REG_ASSIGN4 bits - Resource Assignment 4 */
+#define CPCAP_BIT_VAUDIO_SEL BIT(0)
+
+/*
+ * Off mode configuration bit. Used currently only by SW5 on omap4. There's
+ * the following comment in Motorola Linux kernel tree for it:
+ *
+ * When set in the regulator mode, the regulator assignment will be changed
+ * to secondary when the regulator is disabled. The mode will be set back to
+ * primary when the regulator is turned on.
+ */
+#define CPCAP_REG_OFF_MODE_SEC BIT(15)
+
+#define CPCAP_REG(_reg, _assignment_reg, _assignment_mask, _mode_mask, \
+ _volt_mask, _volt_shft, _mode_val, _off_mode_val, _val_tbl, \
+ _mode_cntr, _volt_trans_time, _turn_on_time, _bit_offset) { \
+ .reg = CPCAP_REG_##_reg, \
+ .assignment_reg = CPCAP_REG_##_assignment_reg, \
+ .assignment_mask = CPCAP_BIT_##_assignment_mask, \
+ .mode_mask = _mode_mask, \
+ .volt_mask = _volt_mask, \
+ .volt_shft = _volt_shft, \
+ .mode_val = _mode_val, \
+ .off_mode_val = _off_mode_val, \
+ .val_tbl_sz = ARRAY_SIZE(_val_tbl), \
+ .val_tbl = _val_tbl, \
+ .mode_cntr = _mode_cntr, \
+ .volt_trans_time = _volt_trans_time, \
+ .turn_on_time = _turn_on_time, \
+ .bit_offset_from_cpcap_lowest_voltage = _bit_offset, \
+}
+
+static const struct cpcap_regulator_data tegra20_regulators[CPCAP_REGULATORS_COUNT] = {
+ /* BUCK */
+ [CPCAP_SW1] = CPCAP_REG(S1C1, ASSIGN2, SW1_SEL, 0x6f00, 0x007f,
+ 0, 0x6800, 0, sw1_val_tbl, 0, 0, 1500, 0x0c),
+ [CPCAP_SW2] = CPCAP_REG(S2C1, ASSIGN2, SW2_SEL, 0x6f00, 0x007f,
+ 0, 0x4804, 0, sw2_sw4_val_tbl, 0, 0, 1500, 0x18),
+ [CPCAP_SW3] = CPCAP_REG(S3C, ASSIGN2, SW3_SEL, 0x0578, 0x0003,
+ 0, 0x043c, 0, sw3_val_tbl, 0, 0, 0, 0),
+ [CPCAP_SW4] = CPCAP_REG(S4C1, ASSIGN2, SW4_SEL, 0x6f00, 0x007f,
+ 0, 0x4909, 0, sw2_sw4_val_tbl, 0, 0, 1500, 0x18),
+ [CPCAP_SW5] = CPCAP_REG(S5C, ASSIGN2, SW5_SEL, 0x0028, 0x0000,
+ 0, 0x0020, 0, sw5_val_tbl, 0, 0, 1500, 0),
+ [CPCAP_SW6] = CPCAP_REG(S6C, ASSIGN2, SW6_SEL, 0x0000, 0x0000,
+ 0, 0, 0, unknown_val_tbl, 0, 0, 0, 0),
+ /* LDO */
+ [CPCAP_VCAM] = CPCAP_REG(VCAMC, ASSIGN2, VCAM_SEL, 0x0087, 0x0030,
+ 4, 0x7, 0, vcam_val_tbl, 0, 420, 1000, 0),
+ [CPCAP_VCSI] = CPCAP_REG(VCSIC, ASSIGN3, VCSI_SEL, 0x0047, 0x0010,
+ 4, 0x7, 0, vcsi_val_tbl, 0, 350, 1000, 0),
+ [CPCAP_VDAC] = CPCAP_REG(VDACC, ASSIGN3, VDAC_SEL, 0x0087, 0x0030,
+ 4, 0x0, 0, vdac_val_tbl, 0, 420, 1000, 0),
+ [CPCAP_VDIG] = CPCAP_REG(VDIGC, ASSIGN2, VDIG_SEL, 0x0087, 0x0030,
+ 4, 0x0, 0, vdig_val_tbl, 0, 420, 1000, 0),
+ [CPCAP_VFUSE] = CPCAP_REG(VFUSEC, ASSIGN3, VFUSE_SEL, 0x00a0, 0x000f,
+ 0, 0x0, 0, vfuse_val_tbl, 0, 420, 1000, 0),
+ [CPCAP_VHVIO] = CPCAP_REG(VHVIOC, ASSIGN3, VHVIO_SEL, 0x0017, 0x0000,
+ 0, 0x2, 0, vhvio_val_tbl, 0, 0, 1000, 0),
+ [CPCAP_VSDIO] = CPCAP_REG(VSDIOC, ASSIGN2, VSDIO_SEL, 0x0087, 0x0038,
+ 3, 0x2, 0, vsdio_val_tbl, 0, 420, 1000, 0),
+ [CPCAP_VPLL] = CPCAP_REG(VPLLC, ASSIGN3, VPLL_SEL, 0x0047, 0x0018,
+ 3, 0x1, 0, vpll_val_tbl, 0, 420, 100, 0),
+ [CPCAP_VRF1] = CPCAP_REG(VRF1C, ASSIGN3, VRF1_SEL, 0x00ac, 0x0002,
+ 1, 0x0, 0, vrf1_val_tbl, 0, 10, 1000, 0),
+ [CPCAP_VRF2] = CPCAP_REG(VRF2C, ASSIGN3, VRF2_SEL, 0x0023, 0x0008,
+ 3, 0x0, 0, vrf2_val_tbl, 0, 10, 1000, 0),
+ [CPCAP_VRFREF] = CPCAP_REG(VRFREFC, ASSIGN3, VRFREF_SEL, 0x0023, 0x0008,
+ 3, 0x0, 0, vrfref_val_tbl, 0, 420, 100, 0),
+ [CPCAP_VWLAN1] = CPCAP_REG(VWLAN1C, ASSIGN3, VWLAN1_SEL, 0x0047, 0x0010,
+ 4, 0x0, 0, vwlan1_val_tbl, 0, 420, 1000, 0),
+ [CPCAP_VWLAN2] = CPCAP_REG(VWLAN2C, ASSIGN3, VWLAN2_SEL, 0x020c, 0x00c0,
+ 6, 0xd, 0, vwlan2_val_tbl, 0, 420, 1000, 0),
+ [CPCAP_VSIM] = CPCAP_REG(VSIMC, ASSIGN3, NONE, 0x0023, 0x0008,
+ 3, 0x0, 0, vsim_val_tbl, 0, 420, 1000, 0),
+ [CPCAP_VSIMCARD] = CPCAP_REG(VSIMC, ASSIGN3, NONE, 0x1e80, 0x0008,
+ 3, 0x1E00, 0, vsimcard_val_tbl, 0, 420, 1000, 0),
+ [CPCAP_VVIB] = CPCAP_REG(VVIBC, ASSIGN3, VVIB_SEL, 0x0001, 0x000c,
+ 2, 0x1, 0, vvib_val_tbl, 0, 500, 500, 0),
+ [CPCAP_VUSB] = CPCAP_REG(VUSBC, ASSIGN3, VUSB_SEL, 0x011c, 0x0040,
+ 6, 0xc, 0, vusb_val_tbl, 0, 0, 1000, 0),
+ [CPCAP_VAUDIO] = CPCAP_REG(VAUDIOC, ASSIGN4, VAUDIO_SEL, 0x0016, 0x0001,
+ 0, 0x5, 0, vaudio_val_tbl, 0, 0, 1000, 0),
+};
+
+static int cpcap_regulator_get_value(struct udevice *dev)
+{
+ const struct cpcap_regulator_data *regulator =
+ &tegra20_regulators[dev->driver_data];
+ int value, volt_shift = regulator->volt_shft;
+
+ value = pmic_reg_read(dev->parent, regulator->reg);
+ if (value < 0)
+ return value;
+
+ if (!(value & regulator->mode_mask))
+ return 0;
+
+ value &= regulator->volt_mask;
+ value -= regulator->bit_offset_from_cpcap_lowest_voltage;
+
+ return regulator->val_tbl[value >> volt_shift];
+}
+
+static int cpcap_regulator_set_value(struct udevice *dev, int uV)
+{
+ const struct cpcap_regulator_data *regulator =
+ &tegra20_regulators[dev->driver_data];
+ int value, ret, volt_shift = regulator->volt_shft;
+
+ if (dev->driver_data == CPCAP_VRF1) {
+ if (uV > 2500000)
+ value = 0;
+ else
+ value = regulator->volt_mask;
+ } else {
+ for (value = 0; value < regulator->val_tbl_sz; value++)
+ if (regulator->val_tbl[value] >= uV)
+ break;
+
+ if (value >= regulator->val_tbl_sz)
+ value = regulator->val_tbl_sz;
+
+ value <<= volt_shift;
+ value += regulator->bit_offset_from_cpcap_lowest_voltage;
+ }
+
+ ret = pmic_clrsetbits(dev->parent, regulator->reg, regulator->volt_mask,
+ value);
+ if (ret)
+ return ret;
+
+ if (regulator->volt_trans_time)
+ udelay(regulator->volt_trans_time);
+
+ return 0;
+}
+
+static int cpcap_regulator_get_enable(struct udevice *dev)
+{
+ const struct cpcap_regulator_data *regulator =
+ &tegra20_regulators[dev->driver_data];
+ int value;
+
+ value = pmic_reg_read(dev->parent, regulator->reg);
+ if (value < 0)
+ return value;
+
+ return (value & regulator->mode_mask) ? 1 : 0;
+}
+
+static int cpcap_regulator_set_enable(struct udevice *dev, bool enable)
+{
+ const struct cpcap_regulator_data *regulator =
+ &tegra20_regulators[dev->driver_data];
+ int ret;
+
+ if (enable) {
+ ret = pmic_clrsetbits(dev->parent, regulator->reg, regulator->mode_mask,
+ regulator->mode_val);
+ if (ret)
+ return ret;
+ }
+
+ if (regulator->mode_val & CPCAP_REG_OFF_MODE_SEC) {
+ ret = pmic_clrsetbits(dev->parent, regulator->assignment_reg,
+ regulator->assignment_mask,
+ enable ? 0 : regulator->assignment_mask);
+ if (ret)
+ return ret;
+ }
+
+ if (!enable) {
+ ret = pmic_clrsetbits(dev->parent, regulator->reg, regulator->mode_mask,
+ regulator->off_mode_val);
+ if (ret)
+ return ret;
+ }
+
+ if (regulator->turn_on_time)
+ udelay(regulator->turn_on_time);
+
+ return 0;
+}
+
+static int cpcap_regulator_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
+ int id;
+
+ for (id = 0; id < CPCAP_REGULATORS_COUNT; id++)
+ if (cpcap_regulator_to_name[id])
+ if (!strcmp(dev->name, cpcap_regulator_to_name[id]))
+ break;
+
+ switch (id) {
+ case CPCAP_SW1 ... CPCAP_SW6:
+ uc_pdata->type = REGULATOR_TYPE_BUCK;
+ break;
+
+ case CPCAP_VCAM ... CPCAP_VAUDIO:
+ uc_pdata->type = REGULATOR_TYPE_LDO;
+ break;
+
+ default:
+ log_err("CPCAP: Invalid regulator ID\n");
+ return -ENODEV;
+ }
+
+ dev->driver_data = id;
+ return 0;
+}
+
+static const struct dm_regulator_ops cpcap_regulator_ops = {
+ .get_value = cpcap_regulator_get_value,
+ .set_value = cpcap_regulator_set_value,
+ .get_enable = cpcap_regulator_get_enable,
+ .set_enable = cpcap_regulator_set_enable,
+};
+
+U_BOOT_DRIVER(cpcap_sw) = {
+ .name = CPCAP_SW_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &cpcap_regulator_ops,
+ .probe = cpcap_regulator_probe,
+};
+
+U_BOOT_DRIVER(cpcap_ldo) = {
+ .name = CPCAP_LDO_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &cpcap_regulator_ops,
+ .probe = cpcap_regulator_probe,
+};
diff --git a/drivers/power/regulator/scmi_regulator.c b/drivers/power/regulator/scmi_regulator.c
index 99f6506..79db1a6 100644
--- a/drivers/power/regulator/scmi_regulator.c
+++ b/drivers/power/regulator/scmi_regulator.c
@@ -175,12 +175,19 @@
static int scmi_regulator_bind(struct udevice *dev)
{
struct driver *drv;
+ ofnode regul_node;
ofnode node;
int ret;
+ regul_node = ofnode_find_subnode(dev_ofnode(dev), "regulators");
+ if (!ofnode_valid(regul_node)) {
+ dev_err(dev, "no regulators node\n");
+ return -ENXIO;
+ }
+
drv = DM_DRIVER_GET(scmi_regulator);
- ofnode_for_each_subnode(node, dev_ofnode(dev)) {
+ ofnode_for_each_subnode(node, regul_node) {
ret = device_bind(dev, drv, ofnode_get_name(node),
NULL, node, NULL);
if (ret)
diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
index 36dc050..fd94aad 100644
--- a/drivers/ram/rockchip/Makefile
+++ b/drivers/ram/rockchip/Makefile
@@ -13,7 +13,9 @@
obj-$(CONFIG_ROCKCHIP_RK3308) = sdram_rk3308.o
obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o sdram_pctl_px30.o sdram_phy_px30.o
obj-$(CONFIG_ROCKCHIP_RK3399) += sdram_rk3399.o
+obj-$(CONFIG_ROCKCHIP_RK3528) += sdram_rk3528.o
obj-$(CONFIG_ROCKCHIP_RK3568) += sdram_rk3568.o
+obj-$(CONFIG_ROCKCHIP_RK3576) += sdram_rk3576.o
obj-$(CONFIG_ROCKCHIP_RK3588) += sdram_rk3588.o
obj-$(CONFIG_ROCKCHIP_RV1126) += sdram_rv1126.o sdram_pctl_px30.o
obj-$(CONFIG_ROCKCHIP_SDRAM_COMMON) += sdram_common.o
diff --git a/drivers/ram/rockchip/sdram_rk3528.c b/drivers/ram/rockchip/sdram_rk3528.c
new file mode 100644
index 0000000..89d325b
--- /dev/null
+++ b/drivers/ram/rockchip/sdram_rk3528.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright Contributors to the U-Boot project.
+
+#include <dm.h>
+#include <ram.h>
+#include <asm/arch-rockchip/sdram.h>
+
+#define PMUGRF_BASE 0xff370000
+#define OS_REG18_REG 0x248
+
+static int rk3528_dmc_get_info(struct udevice *dev, struct ram_info *info)
+{
+ info->base = CFG_SYS_SDRAM_BASE;
+ info->size = rockchip_sdram_size(PMUGRF_BASE + OS_REG18_REG);
+
+ return 0;
+}
+
+static struct ram_ops rk3528_dmc_ops = {
+ .get_info = rk3528_dmc_get_info,
+};
+
+static const struct udevice_id rk3528_dmc_ids[] = {
+ { .compatible = "rockchip,rk3528-dmc" },
+ { }
+};
+
+U_BOOT_DRIVER(rockchip_rk3528_dmc) = {
+ .name = "rockchip_rk3528_dmc",
+ .id = UCLASS_RAM,
+ .of_match = rk3528_dmc_ids,
+ .ops = &rk3528_dmc_ops,
+};
diff --git a/drivers/ram/rockchip/sdram_rk3576.c b/drivers/ram/rockchip/sdram_rk3576.c
new file mode 100644
index 0000000..5a66032
--- /dev/null
+++ b/drivers/ram/rockchip/sdram_rk3576.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dm.h>
+#include <ram.h>
+#include <asm/arch-rockchip/sdram.h>
+
+#define PMU1GRF_BASE 0x26026000
+#define OS_REG2_REG 0x208
+
+static int rk3576_dmc_get_info(struct udevice *dev, struct ram_info *info)
+{
+ info->base = CFG_SYS_SDRAM_BASE;
+ info->size = rockchip_sdram_size(PMU1GRF_BASE + OS_REG2_REG);
+
+ return 0;
+}
+
+static struct ram_ops rk3576_dmc_ops = {
+ .get_info = rk3576_dmc_get_info,
+};
+
+static const struct udevice_id rk3576_dmc_ids[] = {
+ { .compatible = "rockchip,rk3576-dmc" },
+ { }
+};
+
+U_BOOT_DRIVER(rockchip_rk3576_dmc) = {
+ .name = "rockchip_rk3576_dmc",
+ .id = UCLASS_RAM,
+ .of_match = rk3576_dmc_ids,
+ .ops = &rk3576_dmc_ops,
+};
diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
index bd94ea7..47bd57c 100644
--- a/drivers/remoteproc/Makefile
+++ b/drivers/remoteproc/Makefile
@@ -4,7 +4,7 @@
# Texas Instruments Incorporated - https://www.ti.com/
#
-obj-$(CONFIG_$(XPL_)REMOTEPROC) += rproc-uclass.o rproc-elf-loader.o
+obj-$(CONFIG_$(PHASE_)REMOTEPROC) += rproc-uclass.o rproc-elf-loader.o
# Remote proc drivers - Please keep this list alphabetically sorted.
obj-$(CONFIG_K3_SYSTEM_CONTROLLER) += k3_system_controller.o
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index b949439..1dd3cd9 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -17,7 +17,7 @@
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o
obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o
-obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3588.o
+obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3528.o rst-rk3576.o rst-rk3588.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
index 76d1080..e57729f 100644
--- a/drivers/reset/reset-socfpga.c
+++ b/drivers/reset/reset-socfpga.c
@@ -23,6 +23,7 @@
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/sizes.h>
+#include <linux/kconfig.h>
#define BANK_INCREMENT 4
#define NR_BANKS 8
@@ -114,6 +115,8 @@
if (socfpga_reset_keep_enabled()) {
puts("Deasserting all peripheral resets\n");
writel(0, data->modrst_base + 4);
+ if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_ARRIA10))
+ writel(0, data->modrst_base + 8);
}
return 0;
diff --git a/drivers/reset/rst-rk3528.c b/drivers/reset/rst-rk3528.c
new file mode 100644
index 0000000..f6e760d
--- /dev/null
+++ b/drivers/reset/rst-rk3528.c
@@ -0,0 +1,302 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ * Based on Sebastian Reichel's implementation for RK3588
+ */
+
+#include <dm.h>
+#include <asm/arch-rockchip/clock.h>
+#include <dt-bindings/reset/rockchip,rk3528-cru.h>
+
+/* 0xFF4A0000 + 0x0A00 */
+#define RK3528_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
+
+/* mapping table for reset ID to register offset */
+static const int rk3528_register_offset[] = {
+ /* CRU_SOFTRST_CON03 */
+ RK3528_CRU_RESET_OFFSET(SRST_CORE0_PO, 3, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE1_PO, 3, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE2_PO, 3, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE3_PO, 3, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE0, 3, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE1, 3, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE2, 3, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE3, 3, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_NL2, 3, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE_BIU, 3, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE_CRYPTO, 3, 10),
+
+ /* CRU_SOFTRST_CON05 */
+ RK3528_CRU_RESET_OFFSET(SRST_P_DBG, 5, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_POT_DBG, 5, 14),
+ RK3528_CRU_RESET_OFFSET(SRST_NT_DBG, 5, 15),
+
+ /* CRU_SOFTRST_CON06 */
+ RK3528_CRU_RESET_OFFSET(SRST_P_CORE_GRF, 6, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_P_DAPLITE_BIU, 6, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_P_CPU_BIU, 6, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 6, 7),
+
+ /* CRU_SOFTRST_CON08 */
+ RK3528_CRU_RESET_OFFSET(SRST_A_BUS_VOPGL_BIU, 8, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_A_BUS_H_BIU, 8, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_A_SYSMEM_BIU, 8, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 8, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 8, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 8, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_P_DFT2APB, 8, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_P_BUS_GRF, 8, 15),
+
+ /* CRU_SOFTRST_CON09 */
+ RK3528_CRU_RESET_OFFSET(SRST_A_BUS_M_BIU, 9, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_A_GIC, 9, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 9, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_A_DMAC, 9, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_P_TIMER, 9, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_TIMER0, 9, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_TIMER1, 9, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_TIMER2, 9, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_TIMER3, 9, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_TIMER4, 9, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_TIMER5, 9, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_P_JDBCK_DAP, 9, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_JDBCK_DAP, 9, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_P_WDT_NS, 9, 15),
+
+ /* CRU_SOFTRST_CON10 */
+ RK3528_CRU_RESET_OFFSET(SRST_T_WDT_NS, 10, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_H_TRNG_NS, 10, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_P_UART0, 10, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_S_UART0, 10, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_PKA_CRYPTO, 10, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_A_CRYPTO, 10, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_H_CRYPTO, 10, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 10, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 10, 14),
+
+ /* CRU_SOFTRST_CON11 */
+ RK3528_CRU_RESET_OFFSET(SRST_P_PWM0, 11, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_PWM0, 11, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_P_PWM1, 11, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_PWM1, 11, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_P_SCR, 11, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_A_DCF, 11, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_P_INTMUX, 11, 12),
+
+ /* CRU_SOFTRST_CON25 */
+ RK3528_CRU_RESET_OFFSET(SRST_A_VPU_BIU, 25, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_H_VPU_BIU, 25, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_P_VPU_BIU, 25, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_A_VPU, 25, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_H_VPU, 25, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_P_CRU_PCIE, 25, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_P_VPU_GRF, 25, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_H_SFC, 25, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_S_SFC, 25, 14),
+ RK3528_CRU_RESET_OFFSET(SRST_C_EMMC, 25, 15),
+
+ /* CRU_SOFTRST_CON26 */
+ RK3528_CRU_RESET_OFFSET(SRST_H_EMMC, 26, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_A_EMMC, 26, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_B_EMMC, 26, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_T_EMMC, 26, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_P_GPIO1, 26, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO1, 26, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_A_VPU_L_BIU, 26, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_P_VPU_IOC, 26, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S0, 26, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S0, 26, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S2, 26, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S2, 26, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_P_ACODEC, 26, 13),
+
+ /* CRU_SOFTRST_CON27 */
+ RK3528_CRU_RESET_OFFSET(SRST_P_GPIO3, 27, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO3, 27, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_P_SPI1, 27, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_SPI1, 27, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_P_UART2, 27, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_S_UART2, 27, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_P_UART5, 27, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_S_UART5, 27, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_P_UART6, 27, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_S_UART6, 27, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_P_UART7, 27, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_S_UART7, 27, 14),
+ RK3528_CRU_RESET_OFFSET(SRST_P_I2C3, 27, 15),
+
+ /* CRU_SOFTRST_CON28 */
+ RK3528_CRU_RESET_OFFSET(SRST_I2C3, 28, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_P_I2C5, 28, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_I2C5, 28, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_P_I2C6, 28, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_I2C6, 28, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_A_MAC, 28, 5),
+
+ /* CRU_SOFTRST_CON30 */
+ RK3528_CRU_RESET_OFFSET(SRST_P_PCIE, 30, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_PCIE_PIPE_PHY, 30, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_PCIE_POWER_UP, 30, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_P_PCIE_PHY, 30, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_P_PIPE_GRF, 30, 7),
+
+ /* CRU_SOFTRST_CON32 */
+ RK3528_CRU_RESET_OFFSET(SRST_H_SDIO0, 32, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_H_SDIO1, 32, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_TS_0, 32, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_TS_1, 32, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_P_CAN2, 32, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_CAN2, 32, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_P_CAN3, 32, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_CAN3, 32, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_P_SARADC, 32, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_SARADC, 32, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_SARADC_PHY, 32, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_P_TSADC, 32, 14),
+ RK3528_CRU_RESET_OFFSET(SRST_TSADC, 32, 15),
+
+ /* CRU_SOFTRST_CON33 */
+ RK3528_CRU_RESET_OFFSET(SRST_A_USB3OTG, 33, 1),
+
+ /* CRU_SOFTRST_CON34 */
+ RK3528_CRU_RESET_OFFSET(SRST_A_GPU_BIU, 34, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 34, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_A_GPU, 34, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_GPU, 34, 9),
+
+ /* CRU_SOFTRST_CON36 */
+ RK3528_CRU_RESET_OFFSET(SRST_H_RKVENC_BIU, 36, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_A_RKVENC_BIU, 36, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_BIU, 36, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_H_RKVENC, 36, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_A_RKVENC, 36, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE_RKVENC, 36, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S1, 36, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S1, 36, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_P_I2C1, 36, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_I2C1, 36, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_P_I2C0, 36, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_I2C0, 36, 14),
+
+ /* CRU_SOFTRST_CON37 */
+ RK3528_CRU_RESET_OFFSET(SRST_P_SPI0, 37, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_SPI0, 37, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_P_GPIO4, 37, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO4, 37, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_IOC, 37, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_H_SPDIF, 37, 14),
+ RK3528_CRU_RESET_OFFSET(SRST_M_SPDIF, 37, 15),
+
+ /* CRU_SOFTRST_CON38 */
+ RK3528_CRU_RESET_OFFSET(SRST_H_PDM, 38, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_M_PDM, 38, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_P_UART1, 38, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_S_UART1, 38, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_P_UART3, 38, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_S_UART3, 38, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_GRF, 38, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_P_CAN0, 38, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_CAN0, 38, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_P_CAN1, 38, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_CAN1, 38, 10),
+
+ /* CRU_SOFTRST_CON39 */
+ RK3528_CRU_RESET_OFFSET(SRST_A_VO_BIU, 39, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_H_VO_BIU, 39, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_P_VO_BIU, 39, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_H_RGA2E, 39, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_A_RGA2E, 39, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE_RGA2E, 39, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_H_VDPP, 39, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_A_VDPP, 39, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE_VDPP, 39, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_P_VO_GRF, 39, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_P_CRU, 39, 15),
+
+ /* CRU_SOFTRST_CON40 */
+ RK3528_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 40, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_H_VOP, 40, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_D_VOP0, 40, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_D_VOP1, 40, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_A_VOP, 40, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_P_HDMI, 40, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_HDMI, 40, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_P_HDMIPHY, 40, 14),
+ RK3528_CRU_RESET_OFFSET(SRST_H_HDCP_KEY, 40, 15),
+
+ /* CRU_SOFTRST_CON41 */
+ RK3528_CRU_RESET_OFFSET(SRST_A_HDCP, 41, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_H_HDCP, 41, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_P_HDCP, 41, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_H_CVBS, 41, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_D_CVBS_VOP, 41, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_D_4X_CVBS_VOP, 41, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER, 41, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_H_JPEG_DECODER, 41, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_A_VO_L_BIU, 41, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_A_MAC_VO, 41, 10),
+
+ /* CRU_SOFTRST_CON42 */
+ RK3528_CRU_RESET_OFFSET(SRST_A_JPEG_BIU, 42, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S3, 42, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S3, 42, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_MACPHY, 42, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_P_VCDCPHY, 42, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_P_GPIO2, 42, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO2, 42, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_P_VO_IOC, 42, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_H_SDMMC0, 42, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 42, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 42, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_USER_OTPC_NS, 42, 13),
+
+ /* CRU_SOFTRST_CON43 */
+ RK3528_CRU_RESET_OFFSET(SRST_HDMIHDP0, 43, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_H_USBHOST, 43, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_H_USBHOST_ARB, 43, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_HOST_UTMI, 43, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_P_UART4, 43, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_S_UART4, 43, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_P_I2C4, 43, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_I2C4, 43, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_P_I2C7, 43, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_I2C7, 43, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_P_USBPHY, 43, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_USBPHY_POR, 43, 14),
+ RK3528_CRU_RESET_OFFSET(SRST_USBPHY_OTG, 43, 15),
+
+ /* CRU_SOFTRST_CON44 */
+ RK3528_CRU_RESET_OFFSET(SRST_USBPHY_HOST, 44, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY_CRU, 44, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_H_RKVDEC_BIU, 44, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_A_RKVDEC_BIU, 44, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_A_RKVDEC, 44, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_H_RKVDEC, 44, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_HEVC_CA_RKVDEC, 44, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_RKVDEC, 44, 12),
+
+ /* CRU_SOFTRST_CON45 */
+ RK3528_CRU_RESET_OFFSET(SRST_P_DDR_BIU, 45, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_P_DDRC, 45, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_P_DDRMON, 45, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_TIMER_DDRMON, 45, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_P_MSCH_BIU, 45, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_P_DDR_GRF, 45, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_P_DDR_HWLP, 45, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY, 45, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_MSCH_BIU, 45, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL, 45, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_DDR_UPCTL, 45, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_DDRMON, 45, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_A_DDR_SCRAMBLE, 45, 14),
+ RK3528_CRU_RESET_OFFSET(SRST_A_SPLIT, 45, 15),
+
+ /* CRU_SOFTRST_CON46 */
+ RK3528_CRU_RESET_OFFSET(SRST_DDR_PHY, 46, 0),
+};
+
+int rk3528_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number)
+{
+ return rockchip_reset_bind_lut(pdev, rk3528_register_offset,
+ reg_offset, reg_number);
+}
diff --git a/drivers/reset/rst-rk3576.c b/drivers/reset/rst-rk3576.c
new file mode 100644
index 0000000..a6b83a2
--- /dev/null
+++ b/drivers/reset/rst-rk3576.c
@@ -0,0 +1,647 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2024 Collabora Ltd.
+ * Author: Detlev Casanova <detlev.casanova@collabora.com>
+ * Based on Sebastian Reichel's implementation for RK3588
+ */
+
+#include <dm.h>
+#include <asm/arch-rockchip/clock.h>
+#include <dt-bindings/reset/rockchip,rk3576-cru.h>
+
+/* 0x27200000 + 0x0A00 */
+#define RK3576_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + (reg) * 16 + (bit))
+/* 0x27208000 + 0x0A00 */
+#define RK3576_PHPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000 * 4 + (reg) * 16 + (bit))
+/* 0x27210000 + 0x0A00 */
+#define RK3576_SECURENSCRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000 * 4 + (reg) * 16 + (bit))
+/* 0x27220000 + 0x0A00 */
+#define RK3576_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000 * 4 + (reg) * 16 + (bit))
+
+/* mapping table for reset ID to register offset */
+static const int rk3576_register_offset[] = {
+ /* SOFTRST_CON01 */
+ RK3576_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_P_TOP_BIU, 1, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_A_TOP_MID_BIU, 1, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_A_SECURE_HIGH_BIU, 1, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_H_TOP_BIU, 1, 14),
+
+ /* SOFTRST_CON02 */
+ RK3576_CRU_RESET_OFFSET(SRST_H_VO0VOP_CHANNEL_BIU, 2, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_A_VO0VOP_CHANNEL_BIU, 2, 1),
+
+ /* SOFTRST_CON06 */
+ RK3576_CRU_RESET_OFFSET(SRST_BISRINTF, 6, 2),
+
+ /* SOFTRST_CON07 */
+ RK3576_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_0, 7, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_1, 7, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_0, 7, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_1, 7, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_0, 7, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_1, 7, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_0, 7, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_1, 7, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SAI0_8CH, 7, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SAI0_8CH, 7, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX0, 7, 14),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX0, 7, 15),
+
+ /* SOFTRST_CON08 */
+ RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX1, 8, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX1, 8, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SAI1_8CH, 8, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SAI1_8CH, 8, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SAI2_2CH, 8, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SAI2_2CH, 8, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SAI3_2CH, 8, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SAI3_2CH, 8, 14),
+
+ /* SOFTRST_CON09 */
+ RK3576_CRU_RESET_OFFSET(SRST_M_SAI4_2CH, 9, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SAI4_2CH, 9, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_H_ACDCDIG_DSM, 9, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_M_ACDCDIG_DSM, 9, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_PDM1, 9, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_H_PDM1, 9, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_M_PDM1, 9, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX0, 9, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX0, 9, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX1, 9, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX1, 9, 12),
+
+ /* SOFTRST_CON11 */
+ RK3576_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 11, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 11, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_P_CRU, 11, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_H_CAN0, 11, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_CAN0, 11, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_H_CAN1, 11, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_CAN1, 11, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2BUS, 11, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_P_VCCIO_IOC, 11, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 11, 14),
+ RK3576_CRU_RESET_OFFSET(SRST_KEY_SHIFT, 11, 15),
+
+ /* SOFTRST_CON12 */
+ RK3576_CRU_RESET_OFFSET(SRST_P_I2C1, 12, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_P_I2C2, 12, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_P_I2C3, 12, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_P_I2C4, 12, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_P_I2C5, 12, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_P_I2C6, 12, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_P_I2C7, 12, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_P_I2C8, 12, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_P_I2C9, 12, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_P_WDT_BUSMCU, 12, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_T_WDT_BUSMCU, 12, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_A_GIC, 12, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_I2C1, 12, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_I2C2, 12, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_I2C3, 12, 14),
+ RK3576_CRU_RESET_OFFSET(SRST_I2C4, 12, 15),
+
+ /* SOFTRST_CON13 */
+ RK3576_CRU_RESET_OFFSET(SRST_I2C5, 13, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_I2C6, 13, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_I2C7, 13, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_I2C8, 13, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_I2C9, 13, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_P_SARADC, 13, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_SARADC, 13, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_P_TSADC, 13, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_TSADC, 13, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_P_UART0, 13, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_P_UART2, 13, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_P_UART3, 13, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_P_UART4, 13, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_P_UART5, 13, 14),
+ RK3576_CRU_RESET_OFFSET(SRST_P_UART6, 13, 15),
+
+ /* SOFTRST_CON14 */
+ RK3576_CRU_RESET_OFFSET(SRST_P_UART7, 14, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_P_UART8, 14, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_P_UART9, 14, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_P_UART10, 14, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_P_UART11, 14, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_S_UART0, 14, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_S_UART2, 14, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_S_UART3, 14, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_S_UART4, 14, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_S_UART5, 14, 15),
+
+ /* SOFTRST_CON15 */
+ RK3576_CRU_RESET_OFFSET(SRST_S_UART6, 15, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_S_UART7, 15, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_S_UART8, 15, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_S_UART9, 15, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_S_UART10, 15, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_S_UART11, 15, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_P_SPI0, 15, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_P_SPI1, 15, 14),
+ RK3576_CRU_RESET_OFFSET(SRST_P_SPI2, 15, 15),
+
+ /* SOFTRST_CON16 */
+ RK3576_CRU_RESET_OFFSET(SRST_P_SPI3, 16, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_P_SPI4, 16, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_SPI0, 16, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_SPI1, 16, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_SPI2, 16, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_SPI3, 16, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_SPI4, 16, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_P_WDT0, 16, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_T_WDT0, 16, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_P_SYS_GRF, 16, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_P_PWM1, 16, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_PWM1, 16, 11),
+
+ /* SOFTRST_CON17 */
+ RK3576_CRU_RESET_OFFSET(SRST_P_BUSTIMER0, 17, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_P_BUSTIMER1, 17, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_TIMER0, 17, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_TIMER1, 17, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_TIMER2, 17, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_TIMER3, 17, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_TIMER4, 17, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_TIMER5, 17, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_P_BUSIOC, 17, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_P_MAILBOX0, 17, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_P_GPIO1, 17, 15),
+
+ /* SOFTRST_CON18 */
+ RK3576_CRU_RESET_OFFSET(SRST_GPIO1, 18, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_P_GPIO2, 18, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_GPIO2, 18, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_P_GPIO3, 18, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_GPIO3, 18, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_P_GPIO4, 18, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_GPIO4, 18, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DECOM, 18, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_P_DECOM, 18, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_D_DECOM, 18, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_TIMER6, 18, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_TIMER7, 18, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_TIMER8, 18, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_TIMER9, 18, 14),
+ RK3576_CRU_RESET_OFFSET(SRST_TIMER10, 18, 15),
+
+ /* SOFTRST_CON19 */
+ RK3576_CRU_RESET_OFFSET(SRST_TIMER11, 19, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DMAC0, 19, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DMAC1, 19, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DMAC2, 19, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 19, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_REF_PVTPLL_BUS, 19, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_H_I3C0, 19, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_H_I3C1, 19, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_H_BUS_CM0_BIU, 19, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_F_BUS_CM0_CORE, 19, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_T_BUS_CM0_JTAG, 19, 13),
+
+ /* SOFTRST_CON20 */
+ RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2PMU, 20, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2DDR, 20, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_BUS, 20, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_P_PWM2, 20, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_PWM2, 20, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_FREQ_PWM1, 20, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_COUNTER_PWM1, 20, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_I3C0, 20, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_I3C1, 20, 13),
+
+ /* SOFTRST_CON21 */
+ RK3576_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH0, 21, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_P_DDR_BIU, 21, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH0, 21, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH0, 21, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 21, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_DFI_CH0, 21, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_DDR_MON_CH0, 21, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_P_DDR_HWLP_CH0, 21, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH1, 21, 14),
+ RK3576_CRU_RESET_OFFSET(SRST_P_DDR_HWLP_CH1, 21, 15),
+
+ /* SOFTRST_CON22 */
+ RK3576_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH1, 22, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH1, 22, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_DFI_CH1, 22, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH0, 22, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH1, 22, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_DDR_MON_CH1, 22, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_DDR_SCRAMBLE_CH0, 22, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_DDR_SCRAMBLE_CH1, 22, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_P_AHB2APB, 22, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_H_AHB2APB, 22, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_H_DDR_BIU, 22, 14),
+ RK3576_CRU_RESET_OFFSET(SRST_F_DDR_CM0_CORE, 22, 15),
+
+ /* SOFTRST_CON23 */
+ RK3576_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH0, 23, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH1, 23, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_DDR_TIMER0, 23, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_DDR_TIMER1, 23, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_T_WDT_DDR, 23, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_P_WDT, 23, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_P_TIMER, 23, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_T_DDR_CM0_JTAG, 23, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_P_DDR_GRF, 23, 11),
+
+ /* SOFTRST_CON25 */
+ RK3576_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH0, 25, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_0_CH0, 25, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_1_CH0, 25, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_2_CH0, 25, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_3_CH0, 25, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_4_CH0, 25, 6),
+
+ /* SOFTRST_CON26 */
+ RK3576_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH1, 26, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_0_CH1, 26, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_1_CH1, 26, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_2_CH1, 26, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_3_CH1, 26, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_4_CH1, 26, 6),
+
+ /* SOFTRST_CON27 */
+ RK3576_CRU_RESET_OFFSET(SRST_REF_PVTPLL_DDR, 27, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_DDR, 27, 1),
+
+ /* SOFTRST_CON28 */
+ RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0, 28, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0_BIU, 28, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_L_RKNN0_BIU, 28, 12),
+
+ /* SOFTRST_CON29 */
+ RK3576_CRU_RESET_OFFSET(SRST_A_RKNN1, 29, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_A_RKNN1_BIU, 29, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_L_RKNN1_BIU, 29, 3),
+
+ /* SOFTRST_CON31 */
+ RK3576_CRU_RESET_OFFSET(SRST_NPU_DAP, 31, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_L_NPUSUBSYS_BIU, 31, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_P_NPUTOP_BIU, 31, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_P_NPU_TIMER, 31, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_NPUTIMER0, 31, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_NPUTIMER1, 31, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_P_NPU_WDT, 31, 14),
+ RK3576_CRU_RESET_OFFSET(SRST_T_NPU_WDT, 31, 15),
+
+ /* SOFTRST_CON32 */
+ RK3576_CRU_RESET_OFFSET(SRST_A_RKNN_CBUF, 32, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_A_RVCORE0, 32, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_P_NPU_GRF, 32, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_NPU, 32, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_NPU_PVTPLL, 32, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_H_NPU_CM0_BIU, 32, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_F_NPU_CM0_CORE, 32, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_T_NPU_CM0_JTAG, 32, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_A_RKNNTOP_BIU, 32, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_H_RKNN_CBUF, 32, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_H_RKNNTOP_BIU, 32, 13),
+
+ /* SOFTRST_CON33 */
+ RK3576_CRU_RESET_OFFSET(SRST_H_NVM_BIU, 33, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_A_NVM_BIU, 33, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_S_FSPI, 33, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_H_FSPI, 33, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_C_EMMC, 33, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_H_EMMC, 33, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_A_EMMC, 33, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_B_EMMC, 33, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_T_EMMC, 33, 12),
+
+ /* SOFTRST_CON34 */
+ RK3576_CRU_RESET_OFFSET(SRST_P_GRF, 34, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_P_PHP_BIU, 34, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 34, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_P_PCIE0, 34, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_PCIE0_POWER_UP, 34, 15),
+
+ /* SOFTRST_CON35 */
+ RK3576_CRU_RESET_OFFSET(SRST_A_USB3OTG1, 35, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_A_MMU0, 35, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU0, 35, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_A_MMU1, 35, 14),
+
+ /* SOFTRST_CON36 */
+ RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU1, 36, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_P_PCIE1, 36, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_PCIE1_POWER_UP, 36, 9),
+
+ /* SOFTRST_CON37 */
+ RK3576_CRU_RESET_OFFSET(SRST_RXOOB0, 37, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_RXOOB1, 37, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_PMALIVE0, 37, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_PMALIVE1, 37, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_A_SATA0, 37, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_A_SATA1, 37, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_ASIC1, 37, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_ASIC0, 37, 7),
+
+ /* SOFTRST_CON40 */
+ RK3576_CRU_RESET_OFFSET(SRST_P_CSIDPHY1, 40, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_SCAN_CSIDPHY1, 40, 3),
+
+ /* SOFTRST_CON42 */
+ RK3576_CRU_RESET_OFFSET(SRST_P_SDGMAC_GRF, 42, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_P_SDGMAC_BIU, 42, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_A_SDGMAC_BIU, 42, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SDGMAC_BIU, 42, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_A_GMAC0, 42, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_A_GMAC1, 42, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_P_GMAC0, 42, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_P_GMAC1, 42, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SDIO, 42, 12),
+
+ /* SOFTRST_CON43 */
+ RK3576_CRU_RESET_OFFSET(SRST_H_SDMMC0, 43, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_S_FSPI1, 43, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_H_FSPI1, 43, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DSMC_BIU, 43, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DSMC, 43, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_P_DSMC, 43, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_H_HSGPIO, 43, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_HSGPIO, 43, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_A_HSGPIO, 43, 13),
+
+ /* SOFTRST_CON45 */
+ RK3576_CRU_RESET_OFFSET(SRST_H_RKVDEC, 45, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_H_RKVDEC_BIU, 45, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_A_RKVDEC_BIU, 45, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_RKVDEC_HEVC_CA, 45, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_RKVDEC_CORE, 45, 9),
+
+ /* SOFTRST_CON47 */
+ RK3576_CRU_RESET_OFFSET(SRST_A_USB_BIU, 47, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_P_USBUFS_BIU, 47, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_A_USB3OTG0, 47, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_A_UFS_BIU, 47, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_A_MMU2, 47, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU2, 47, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_A_UFS_SYS, 47, 15),
+
+ /* SOFTRST_CON48 */
+ RK3576_CRU_RESET_OFFSET(SRST_A_UFS, 48, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_P_USBUFS_GRF, 48, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_P_UFS_GRF, 48, 2),
+
+ /* SOFTRST_CON49 */
+ RK3576_CRU_RESET_OFFSET(SRST_H_VPU_BIU, 49, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_A_JPEG_BIU, 49, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_A_RGA_BIU, 49, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_A_VDPP_BIU, 49, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_A_EBC_BIU, 49, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_H_RGA2E_0, 49, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_A_RGA2E_0, 49, 14),
+ RK3576_CRU_RESET_OFFSET(SRST_CORE_RGA2E_0, 49, 15),
+
+ /* SOFTRST_CON50 */
+ RK3576_CRU_RESET_OFFSET(SRST_A_JPEG, 50, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_H_JPEG, 50, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_H_VDPP, 50, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_A_VDPP, 50, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_CORE_VDPP, 50, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_H_RGA2E_1, 50, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_A_RGA2E_1, 50, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_CORE_RGA2E_1, 50, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_H_EBC, 50, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_A_EBC, 50, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_D_EBC, 50, 12),
+
+ /* SOFTRST_CON51 */
+ RK3576_CRU_RESET_OFFSET(SRST_H_VEPU0_BIU, 51, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_A_VEPU0_BIU, 51, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_H_VEPU0, 51, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_A_VEPU0, 51, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_VEPU0_CORE, 51, 6),
+
+ /* SOFTRST_CON53 */
+ RK3576_CRU_RESET_OFFSET(SRST_A_VI_BIU, 53, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_H_VI_BIU, 53, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_P_VI_BIU, 53, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_D_VICAP, 53, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_A_VICAP, 53, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_H_VICAP, 53, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_ISP0, 53, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_ISP0_VICAP, 53, 11),
+
+ /* SOFTRST_CON54 */
+ RK3576_CRU_RESET_OFFSET(SRST_CORE_VPSS, 54, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_0, 54, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_1, 54, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_2, 54, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_3, 54, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_4, 54, 8),
+
+ /* SOFTRST_CON59 */
+ RK3576_CRU_RESET_OFFSET(SRST_CIFIN, 59, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_VICAP_I0CLK, 59, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_VICAP_I1CLK, 59, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_VICAP_I2CLK, 59, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_VICAP_I3CLK, 59, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_VICAP_I4CLK, 59, 5),
+
+ /* SOFTRST_CON61 */
+ RK3576_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 61, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_A_VOP2_BIU, 61, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_H_VOP_BIU, 61, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_P_VOP_BIU, 61, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_H_VOP, 61, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_A_VOP, 61, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_D_VP0, 61, 13),
+
+ /* SOFTRST_CON62 */
+ RK3576_CRU_RESET_OFFSET(SRST_D_VP1, 62, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_D_VP2, 62, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_P_VOP2_BIU, 62, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_P_VOPGRF, 62, 3),
+
+ /* SOFTRST_CON63 */
+ RK3576_CRU_RESET_OFFSET(SRST_H_VO0_BIU, 63, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_P_VO0_BIU, 63, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_A_HDCP0_BIU, 63, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_P_VO0_GRF, 63, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_A_HDCP0, 63, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_H_HDCP0, 63, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_HDCP0, 63, 14),
+
+ /* SOFTRST_CON64 */
+ RK3576_CRU_RESET_OFFSET(SRST_P_DSIHOST0, 64, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_DSIHOST0, 64, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_P_HDMITX0, 64, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_HDMITX0_REF, 64, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_P_EDP0, 64, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_EDP0_24M, 64, 14),
+
+ /* SOFTRST_CON65 */
+ RK3576_CRU_RESET_OFFSET(SRST_M_SAI5_8CH, 65, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SAI5_8CH, 65, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SAI6_8CH, 65, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SAI6_8CH, 65, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX2, 65, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX2, 65, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX2, 65, 14),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX2, 65, 15),
+
+ /* SOFTRST_CON66 */
+ RK3576_CRU_RESET_OFFSET(SRST_H_SAI8_8CH, 66, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SAI8_8CH, 66, 2),
+
+ /* SOFTRST_CON67 */
+ RK3576_CRU_RESET_OFFSET(SRST_H_VO1_BIU, 67, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_P_VO1_BIU, 67, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SAI7_8CH, 67, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SAI7_8CH, 67, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX3, 67, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX4, 67, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX5, 67, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX3, 67, 14),
+
+ /* SOFTRST_CON68 */
+ RK3576_CRU_RESET_OFFSET(SRST_DP0, 68, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_P_VO1_GRF, 68, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 68, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_A_HDCP1, 68, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_H_HDCP1, 68, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_HDCP1, 68, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SAI9_8CH, 68, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SAI9_8CH, 68, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX4, 68, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX5, 68, 13),
+
+ /* SOFTRST_CON69 */
+ RK3576_CRU_RESET_OFFSET(SRST_GPU, 69, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_A_S_GPU_BIU, 69, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_A_M0_GPU_BIU, 69, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 69, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_P_GPU_GRF, 69, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_GPU_PVTPLL, 69, 14),
+ RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_GPU, 69, 15),
+
+ /* SOFTRST_CON72 */
+ RK3576_CRU_RESET_OFFSET(SRST_A_CENTER_BIU, 72, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 72, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM, 72, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM_BIU, 72, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_H_CENTER_BIU, 72, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_P_CENTER_GRF, 72, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 72, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_P_SHAREMEM, 72, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_P_CENTER_BIU, 72, 12),
+
+ /* SOFTRST_CON75 */
+ RK3576_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY0, 75, 1),
+
+ /* SOFTRST_CON78 */
+ RK3576_CRU_RESET_OFFSET(SRST_DP0_PIXELCLK, 78, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_PHY_DP0_TX, 78, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_DP1_PIXELCLK, 78, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_DP2_PIXELCLK, 78, 4),
+
+ /* SOFTRST_CON79 */
+ RK3576_CRU_RESET_OFFSET(SRST_H_VEPU1_BIU, 79, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_A_VEPU1_BIU, 79, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_H_VEPU1, 79, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_A_VEPU1, 79, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_VEPU1_CORE, 79, 5),
+
+ /* PPLL_SOFTRST_CON00 */
+ RK3576_PHPCRU_RESET_OFFSET(SRST_P_PHPPHY_CRU, 0, 1),
+ RK3576_PHPCRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CHIP_TOP, 0, 3),
+ RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY0, 0, 5),
+ RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY0_GRF, 0, 6),
+ RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY1, 0, 7),
+ RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY1_GRF, 0, 8),
+
+ /* PPLL_SOFTRST_CON01 */
+ RK3576_PHPCRU_RESET_OFFSET(SRST_PCIE0_PIPE_PHY, 1, 5),
+ RK3576_PHPCRU_RESET_OFFSET(SRST_PCIE1_PIPE_PHY, 1, 8),
+
+ /* SECURENS_SOFTRST_CON00 */
+ RK3576_SECURENSCRU_RESET_OFFSET(SRST_H_CRYPTO_NS, 0, 3),
+ RK3576_SECURENSCRU_RESET_OFFSET(SRST_H_TRNG_NS, 0, 4),
+ RK3576_SECURENSCRU_RESET_OFFSET(SRST_P_OTPC_NS, 0, 8),
+ RK3576_SECURENSCRU_RESET_OFFSET(SRST_OTPC_NS, 0, 9),
+
+ /* PMU1_SOFTRST_CON00 */
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_HDPTX_GRF, 0, 0),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_HDPTX_APB, 0, 1),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY, 0, 2),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_DCPHY_GRF, 0, 3),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_BOT0_APB2ASB, 0, 4),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_BOT1_APB2ASB, 0, 5),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_USB2DEBUG, 0, 6),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CSIPHY_GRF, 0, 7),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CSIPHY, 0, 8),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_0, 0, 9),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_1, 0, 10),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBDP_GRF, 0, 11),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBDPPHY, 0, 12),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_INIT, 0, 15),
+
+ /* PMU1_SOFTRST_CON01 */
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_CMN, 1, 0),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_LANE, 1, 1),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_PCS, 1, 2),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY, 1, 3),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY, 1, 4),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_SCAN_CSIPHY, 1, 5),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_VCCIO6_IOC, 1, 6),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_0, 1, 7),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_1, 1, 8),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_INIT, 1, 9),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_CMN, 1, 10),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_LANE, 1, 11),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_HDMITXHDP, 1, 13),
+
+ /* PMU1_SOFTRST_CON02 */
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_MPHY_INIT, 2, 0),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MPHY_GRF, 2, 1),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_VCCIO7_IOC, 2, 3),
+
+ /* PMU1_SOFTRST_CON03 */
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 3, 9),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_NIU, 3, 10),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU_CM0_BIU, 3, 11),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU_CM0_CORE, 3, 12),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU_CM0_JTAG, 3, 13),
+
+ /* PMU1_SOFTRST_CON04 */
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CRU_PMU1, 4, 1),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_GRF, 4, 3),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_IOC, 4, 4),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1WDT, 4, 5),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_T_PMU1WDT, 4, 6),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMUTIMER, 4, 7),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER0, 4, 9),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER1, 4, 10),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1PWM, 4, 11),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU1PWM, 4, 12),
+
+ /* PMU1_SOFTRST_CON05 */
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_I2C0, 5, 1),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_I2C0, 5, 2),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_S_UART1, 5, 5),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_UART1, 5, 6),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_PDM0, 5, 13),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PDM0, 5, 15),
+
+ /* PMU1_SOFTRST_CON06 */
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_M_PDM0, 6, 0),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_H_VAD, 6, 1),
+
+ /* PMU1_SOFTRST_CON07 */
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU0GRF, 7, 4),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU0IOC, 7, 5),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_GPIO0, 7, 6),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_DB_GPIO0, 7, 7),
+};
+
+int rk3576_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number)
+{
+ return rockchip_reset_bind_lut(pdev, rk3576_register_offset,
+ reg_offset, reg_number);
+}
diff --git a/drivers/rng/rockchip_rng.c b/drivers/rng/rockchip_rng.c
index 2426648..d854ea9 100644
--- a/drivers/rng/rockchip_rng.c
+++ b/drivers/rng/rockchip_rng.c
@@ -70,6 +70,27 @@
#define TRNG_v1_VERSION_CODE 0x46BC
/* end of TRNG V1 register define */
+/* start of RKRNG register define */
+#define RKRNG_CTRL 0x0010
+#define RKRNG_CTRL_INST_REQ BIT(0)
+#define RKRNG_CTRL_RESEED_REQ BIT(1)
+#define RKRNG_CTRL_TEST_REQ BIT(2)
+#define RKRNG_CTRL_SW_DRNG_REQ BIT(3)
+#define RKRNG_CTRL_SW_TRNG_REQ BIT(4)
+
+#define RKRNG_STATE 0x0014
+#define RKRNG_STATE_INST_ACK BIT(0)
+#define RKRNG_STATE_RESEED_ACK BIT(1)
+#define RKRNG_STATE_TEST_ACK BIT(2)
+#define RKRNG_STATE_SW_DRNG_ACK BIT(3)
+#define RKRNG_STATE_SW_TRNG_ACK BIT(4)
+
+/* DRNG_DATA_0 ~ DNG_DATA_7 */
+#define RKRNG_DRNG_DATA_0 0x0070
+#define RKRNG_DRNG_DATA_7 0x008C
+
+/* end of RKRNG register define */
+
#define RK_RNG_TIME_OUT 50000 /* max 50ms */
#define trng_write(pdata, pos, val) writel(val, (pdata)->base + (pos))
@@ -228,6 +249,49 @@
return retval;
}
+static int rkrng_init(struct udevice *dev)
+{
+ struct rk_rng_plat *pdata = dev_get_priv(dev);
+ u32 reg = 0;
+
+ rk_clrreg(pdata->base + RKRNG_CTRL, 0xffff);
+
+ reg = trng_read(pdata, RKRNG_STATE);
+ trng_write(pdata, RKRNG_STATE, reg);
+
+ return 0;
+}
+
+static int rkrng_rng_read(struct udevice *dev, void *data, size_t len)
+{
+ struct rk_rng_plat *pdata = dev_get_priv(dev);
+ u32 reg = 0;
+ int retval;
+
+ if (len > RK_HW_RNG_MAX)
+ return -EINVAL;
+
+ reg = RKRNG_CTRL_SW_DRNG_REQ;
+
+ rk_clrsetreg(pdata->base + RKRNG_CTRL, 0xffff, reg);
+
+ retval = readl_poll_timeout(pdata->base + RKRNG_STATE, reg,
+ (reg & RKRNG_STATE_SW_DRNG_ACK),
+ RK_RNG_TIME_OUT);
+ if (retval)
+ goto exit;
+
+ trng_write(pdata, RKRNG_STATE, reg);
+
+ rk_rng_read_regs(pdata->base + RKRNG_DRNG_DATA_0, data, len);
+
+exit:
+ /* close TRNG */
+ rk_clrreg(pdata->base + RKRNG_CTRL, 0xffff);
+
+ return retval;
+}
+
static int rockchip_rng_read(struct udevice *dev, void *data, size_t len)
{
unsigned char *buf = data;
@@ -295,6 +359,11 @@
.rk_rng_read = rk_trngv1_rng_read,
};
+static const struct rk_rng_soc_data rkrng_soc_data = {
+ .rk_rng_init = rkrng_init,
+ .rk_rng_read = rkrng_rng_read,
+};
+
static const struct dm_rng_ops rockchip_rng_ops = {
.read = rockchip_rng_read,
};
@@ -313,13 +382,21 @@
.data = (ulong)&rk_cryptov1_soc_data,
},
{
+ .compatible = "rockchip,rk3568-rng",
+ .data = (ulong)&rk_cryptov2_soc_data,
+ },
+ {
.compatible = "rockchip,cryptov2-rng",
.data = (ulong)&rk_cryptov2_soc_data,
},
{
- .compatible = "rockchip,trngv1",
+ .compatible = "rockchip,rk3588-rng",
.data = (ulong)&rk_trngv1_soc_data,
},
+ {
+ .compatible = "rockchip,rkrng",
+ .data = (ulong)&rkrng_soc_data,
+ },
{},
};
diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c
index cd0b84c..7d022ce 100644
--- a/drivers/scsi/scsi.c
+++ b/drivers/scsi/scsi.c
@@ -28,6 +28,10 @@
#define SCSI_MAX_BLK 0xFFFF
#define SCSI_LBA48_READ 0xFFFFFFF
+#define SCSI_UNMAP_PARAM_RESERVED 0
+#define SCSI_UNMAP_PARAM_LEN 22
+#define SCSI_UNMAP_PARAM_DATA_LEN 16
+
static void scsi_print_error(struct scsi_cmd *pccb)
{
/* Dummy function that could print an error for debugging */
@@ -78,6 +82,23 @@
pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
}
+static void scsi_setup_sync_cache(struct scsi_cmd *pccb, lbaint_t start,
+ unsigned short blocks)
+{
+ pccb->cmd[0] = SCSI_SYNC_CACHE;
+ pccb->cmd[1] = 0;
+ pccb->cmd[2] = (unsigned char)(start >> 24) & 0xff;
+ pccb->cmd[3] = (unsigned char)(start >> 16) & 0xff;
+ pccb->cmd[4] = (unsigned char)(start >> 8) & 0xff;
+ pccb->cmd[5] = (unsigned char)start & 0xff;
+ pccb->cmd[6] = 0;
+ pccb->cmd[7] = (unsigned char)(blocks >> 8) & 0xff;
+ pccb->cmd[8] = (unsigned char)blocks & 0xff;
+ pccb->cmd[9] = 0;
+ pccb->cmdlen = 10;
+ pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+}
+
static void scsi_setup_read_ext(struct scsi_cmd *pccb, lbaint_t start,
unsigned short blocks)
{
@@ -90,7 +111,7 @@
pccb->cmd[6] = 0;
pccb->cmd[7] = (unsigned char)(blocks >> 8) & 0xff;
pccb->cmd[8] = (unsigned char)blocks & 0xff;
- pccb->cmd[6] = 0;
+ pccb->cmd[9] = 0;
pccb->cmdlen = 10;
pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
debug("scsi_setup_read_ext: cmd: %02X %02X startblk %02X%02X%02X%02X blccnt %02X%02X\n",
@@ -121,6 +142,51 @@
pccb->cmd[7], pccb->cmd[8]);
}
+static void scsi_setup_erase_ext(struct scsi_cmd *pccb, lbaint_t start,
+ unsigned short blocks)
+{
+ u8 *param = tempbuff;
+ const u8 param_size = 24;
+
+ memset(param, 0, param_size);
+ param[0] = SCSI_UNMAP_PARAM_RESERVED;
+ param[1] = SCSI_UNMAP_PARAM_LEN;
+ param[2] = SCSI_UNMAP_PARAM_RESERVED;
+ param[3] = SCSI_UNMAP_PARAM_DATA_LEN;
+
+ param[8] = 0x0;
+ param[9] = 0x0;
+ param[10] = 0x0;
+ param[11] = 0x0;
+ param[12] = (start >> 24) & 0xff;
+ param[13] = (start >> 16) & 0xff;
+ param[14] = (start >> 8) & 0xff;
+ param[15] = (start) & 0xff;
+ param[16] = (blocks >> 24) & 0xff;
+ param[17] = (blocks >> 16) & 0xff;
+ param[18] = (blocks >> 8) & 0xff;
+ param[19] = (blocks) & 0xff;
+
+ memset(pccb->cmd, 0, sizeof(pccb->cmd));
+ pccb->cmd[0] = SCSI_UNMAP;
+ pccb->cmd[1] = 0;
+ pccb->cmd[6] = 0;
+ pccb->cmd[7] = 0;
+ pccb->cmd[8] = param_size;
+ pccb->cmd[9] = 0;
+ pccb->cmdlen = 10;
+
+ pccb->pdata = param;
+ pccb->datalen = param_size;
+ pccb->dma_dir = DMA_TO_DEVICE;
+
+ debug("%s: cmd: %02X %02X startblk %02X%02X%02X%02X blccnt %02X%02X\n",
+ __func__,
+ pccb->cmd[0], pccb->cmd[1],
+ pccb->cmd[2], pccb->cmd[3], pccb->cmd[4], pccb->cmd[5],
+ pccb->cmd[7], pccb->cmd[8]);
+}
+
static ulong scsi_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
void *buffer)
{
@@ -240,11 +306,59 @@
}
buf_addr += pccb->datalen;
} while (blks != 0);
+
+ /* Flush the SCSI cache so we don't lose data on board reset. */
+ scsi_setup_sync_cache(pccb, 0, 0);
+ if (scsi_exec(bdev, pccb))
+ scsi_print_error(pccb);
+
debug("%s: end startblk " LBAF ", blccnt %x buffer %lX\n",
__func__, start, smallblks, buf_addr);
return blkcnt;
}
+/*******************************************************************************
+ * scsi_erase
+ */
+static ulong scsi_erase(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt)
+{
+ struct blk_desc *block_dev = dev_get_uclass_plat(dev);
+ struct udevice *bdev = dev->parent;
+ struct scsi_plat *uc_plat = dev_get_uclass_plat(bdev);
+ lbaint_t start, blks, max_blks;
+ struct scsi_cmd *pccb = (struct scsi_cmd *)&tempccb;
+
+ /* Setup device */
+ pccb->target = block_dev->target;
+ pccb->lun = block_dev->lun;
+ start = blknr;
+ blks = blkcnt;
+ if (uc_plat->max_bytes_per_req)
+ max_blks = uc_plat->max_bytes_per_req / block_dev->blksz;
+ else
+ max_blks = SCSI_MAX_BLK;
+
+ debug("\n%s: dev %d startblk " LBAF ", blccnt " LBAF "\n",
+ __func__, block_dev->devnum, start, blks);
+ do {
+ if (blks > max_blks) {
+ scsi_setup_erase_ext(pccb, start, max_blks);
+ start += max_blks;
+ blks -= max_blks;
+ } else {
+ scsi_setup_erase_ext(pccb, start, blks);
+ start += blks;
+ blks = 0;
+ }
+ if (scsi_exec(bdev, pccb)) {
+ scsi_print_error(pccb);
+ blkcnt -= blks;
+ break;
+ }
+ } while (blks != 0);
+ return blkcnt;
+}
+
#if IS_ENABLED(CONFIG_BOUNCE_BUFFER)
static int scsi_buffer_aligned(struct udevice *dev, struct bounce_buffer *state)
{
@@ -592,6 +706,7 @@
static const struct blk_ops scsi_blk_ops = {
.read = scsi_read,
.write = scsi_write,
+ .erase = scsi_erase,
#if IS_ENABLED(CONFIG_BOUNCE_BUFFER)
.buffer_aligned = scsi_buffer_aligned,
#endif /* CONFIG_BOUNCE_BUFFER */
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 8413052..589b526 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -519,6 +519,8 @@
default 0x0 if DEBUG_UART_SANDBOX
default 0xff000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQMP
default 0xe0000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQ
+ default 0xff000000 if DEBUG_UART_PL011 && ARCH_VERSAL
+ default 0xf1920000 if DEBUG_UART_PL011 && (ARCH_VERSAL_NET || ARCH_VERSAL2)
help
This is the base address of your UART for memory-mapped UARTs.
@@ -554,6 +556,7 @@
default 0 if DEBUG_MVEBU_A3700_UART
default 100000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQMP
default 50000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQ
+ default 100000000 if DEBUG_UART_PL011 && (ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2)
help
The UART input clock determines the speed of the internal UART
circuitry. The baud rate is derived from this by dividing the input
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 2ef8ba2..c32e3fc 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -11,7 +11,7 @@
obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o
obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o
-obj-$(CONFIG_$(XPL_)SYS_NS16550_SERIAL) += serial_ns16550.o
+obj-$(CONFIG_$(PHASE_)SYS_NS16550_SERIAL) += serial_ns16550.o
obj-$(CONFIG_ALTERA_UART) += altera_uart.o
obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index f475f34..a3513f0 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -59,6 +59,15 @@
Enable the ADI (Analog Devices) SPI controller driver. This
driver enables the support for SC5XX spi controller.
+config AIROHA_SNFI_SPI
+ bool "Airoha SPI memory controller driver"
+ depends on SPI_MEM
+ help
+ Enable the Airoha SPI memory controller driver. This driver is
+ originally based on the Airoha SNFI IP core. It can only be
+ used to access SPI memory devices like SPI-NOR or SPI-NAND on
+ platforms embedding this IP core, like AN7581.
+
config ALTERA_SPI
bool "Altera SPI driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 21895d4..da91b18 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -20,6 +20,7 @@
endif
obj-$(CONFIG_ADI_SPI3) += adi_spi3.o
+obj-$(CONFIG_AIROHA_SNFI_SPI) += airoha_snfi_spi.o
obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
obj-$(CONFIG_APPLE_SPI) += apple_spi.o
obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
diff --git a/drivers/spi/airoha_snfi_spi.c b/drivers/spi/airoha_snfi_spi.c
new file mode 100644
index 0000000..3ea25b2
--- /dev/null
+++ b/drivers/spi/airoha_snfi_spi.c
@@ -0,0 +1,718 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2024 AIROHA Inc
+ *
+ * Based on spi-airoha-snfi.c on Linux
+ *
+ * Author: Lorenzo Bianconi <lorenzo@kernel.org>
+ * Author: Ray Liu <ray.liu@airoha.com>
+ */
+
+#include <asm/unaligned.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/devres.h>
+#include <linux/bitfield.h>
+#include <linux/dma-mapping.h>
+#include <linux/mtd/spinand.h>
+#include <linux/time.h>
+#include <regmap.h>
+#include <spi.h>
+#include <spi-mem.h>
+
+/* SPI */
+#define REG_SPI_CTRL_READ_MODE 0x0000
+#define REG_SPI_CTRL_READ_IDLE_EN 0x0004
+#define REG_SPI_CTRL_SIDLY 0x0008
+#define REG_SPI_CTRL_CSHEXT 0x000c
+#define REG_SPI_CTRL_CSLEXT 0x0010
+
+#define REG_SPI_CTRL_MTX_MODE_TOG 0x0014
+#define SPI_CTRL_MTX_MODE_TOG GENMASK(3, 0)
+
+#define REG_SPI_CTRL_RDCTL_FSM 0x0018
+#define SPI_CTRL_RDCTL_FSM GENMASK(3, 0)
+
+#define REG_SPI_CTRL_MACMUX_SEL 0x001c
+
+#define REG_SPI_CTRL_MANUAL_EN 0x0020
+#define SPI_CTRL_MANUAL_EN BIT(0)
+
+#define REG_SPI_CTRL_OPFIFO_EMPTY 0x0024
+#define SPI_CTRL_OPFIFO_EMPTY BIT(0)
+
+#define REG_SPI_CTRL_OPFIFO_WDATA 0x0028
+#define SPI_CTRL_OPFIFO_LEN GENMASK(8, 0)
+#define SPI_CTRL_OPFIFO_OP GENMASK(13, 9)
+
+#define REG_SPI_CTRL_OPFIFO_FULL 0x002c
+#define SPI_CTRL_OPFIFO_FULL BIT(0)
+
+#define REG_SPI_CTRL_OPFIFO_WR 0x0030
+#define SPI_CTRL_OPFIFO_WR BIT(0)
+
+#define REG_SPI_CTRL_DFIFO_FULL 0x0034
+#define SPI_CTRL_DFIFO_FULL BIT(0)
+
+#define REG_SPI_CTRL_DFIFO_WDATA 0x0038
+#define SPI_CTRL_DFIFO_WDATA GENMASK(7, 0)
+
+#define REG_SPI_CTRL_DFIFO_EMPTY 0x003c
+#define SPI_CTRL_DFIFO_EMPTY BIT(0)
+
+#define REG_SPI_CTRL_DFIFO_RD 0x0040
+#define SPI_CTRL_DFIFO_RD BIT(0)
+
+#define REG_SPI_CTRL_DFIFO_RDATA 0x0044
+#define SPI_CTRL_DFIFO_RDATA GENMASK(7, 0)
+
+#define REG_SPI_CTRL_DUMMY 0x0080
+#define SPI_CTRL_CTRL_DUMMY GENMASK(3, 0)
+
+#define REG_SPI_CTRL_PROBE_SEL 0x0088
+#define REG_SPI_CTRL_INTERRUPT 0x0090
+#define REG_SPI_CTRL_INTERRUPT_EN 0x0094
+#define REG_SPI_CTRL_SI_CK_SEL 0x009c
+#define REG_SPI_CTRL_SW_CFGNANDADDR_VAL 0x010c
+#define REG_SPI_CTRL_SW_CFGNANDADDR_EN 0x0110
+#define REG_SPI_CTRL_SFC_STRAP 0x0114
+
+#define REG_SPI_CTRL_NFI2SPI_EN 0x0130
+#define SPI_CTRL_NFI2SPI_EN BIT(0)
+
+/* NFI2SPI */
+#define REG_SPI_NFI_CNFG 0x0000
+#define SPI_NFI_DMA_MODE BIT(0)
+#define SPI_NFI_READ_MODE BIT(1)
+#define SPI_NFI_DMA_BURST_EN BIT(2)
+#define SPI_NFI_HW_ECC_EN BIT(8)
+#define SPI_NFI_AUTO_FDM_EN BIT(9)
+#define SPI_NFI_OPMODE GENMASK(14, 12)
+
+#define REG_SPI_NFI_PAGEFMT 0x0004
+#define SPI_NFI_PAGE_SIZE GENMASK(1, 0)
+#define SPI_NFI_SPARE_SIZE GENMASK(5, 4)
+
+#define REG_SPI_NFI_CON 0x0008
+#define SPI_NFI_FIFO_FLUSH BIT(0)
+#define SPI_NFI_RST BIT(1)
+#define SPI_NFI_RD_TRIG BIT(8)
+#define SPI_NFI_WR_TRIG BIT(9)
+#define SPI_NFI_SEC_NUM GENMASK(15, 12)
+
+#define REG_SPI_NFI_INTR_EN 0x0010
+#define SPI_NFI_RD_DONE_EN BIT(0)
+#define SPI_NFI_WR_DONE_EN BIT(1)
+#define SPI_NFI_RST_DONE_EN BIT(2)
+#define SPI_NFI_ERASE_DONE_EN BIT(3)
+#define SPI_NFI_BUSY_RETURN_EN BIT(4)
+#define SPI_NFI_ACCESS_LOCK_EN BIT(5)
+#define SPI_NFI_AHB_DONE_EN BIT(6)
+#define SPI_NFI_ALL_IRQ_EN \
+ (SPI_NFI_RD_DONE_EN | SPI_NFI_WR_DONE_EN | \
+ SPI_NFI_RST_DONE_EN | SPI_NFI_ERASE_DONE_EN | \
+ SPI_NFI_BUSY_RETURN_EN | SPI_NFI_ACCESS_LOCK_EN | \
+ SPI_NFI_AHB_DONE_EN)
+
+#define REG_SPI_NFI_INTR 0x0014
+#define SPI_NFI_AHB_DONE BIT(6)
+
+#define REG_SPI_NFI_CMD 0x0020
+
+#define REG_SPI_NFI_ADDR_NOB 0x0030
+#define SPI_NFI_ROW_ADDR_NOB GENMASK(6, 4)
+
+#define REG_SPI_NFI_STA 0x0060
+#define REG_SPI_NFI_FIFOSTA 0x0064
+#define REG_SPI_NFI_STRADDR 0x0080
+#define REG_SPI_NFI_FDM0L 0x00a0
+#define REG_SPI_NFI_FDM0M 0x00a4
+#define REG_SPI_NFI_FDM7L 0x00d8
+#define REG_SPI_NFI_FDM7M 0x00dc
+#define REG_SPI_NFI_FIFODATA0 0x0190
+#define REG_SPI_NFI_FIFODATA1 0x0194
+#define REG_SPI_NFI_FIFODATA2 0x0198
+#define REG_SPI_NFI_FIFODATA3 0x019c
+#define REG_SPI_NFI_MASTERSTA 0x0224
+
+#define REG_SPI_NFI_SECCUS_SIZE 0x022c
+#define SPI_NFI_CUS_SEC_SIZE GENMASK(12, 0)
+#define SPI_NFI_CUS_SEC_SIZE_EN BIT(16)
+
+#define REG_SPI_NFI_RD_CTL2 0x0510
+#define REG_SPI_NFI_RD_CTL3 0x0514
+
+#define REG_SPI_NFI_PG_CTL1 0x0524
+#define SPI_NFI_PG_LOAD_CMD GENMASK(15, 8)
+
+#define REG_SPI_NFI_PG_CTL2 0x0528
+#define REG_SPI_NFI_NOR_PROG_ADDR 0x052c
+#define REG_SPI_NFI_NOR_RD_ADDR 0x0534
+
+#define REG_SPI_NFI_SNF_MISC_CTL 0x0538
+#define SPI_NFI_DATA_READ_WR_MODE GENMASK(18, 16)
+
+#define REG_SPI_NFI_SNF_MISC_CTL2 0x053c
+#define SPI_NFI_READ_DATA_BYTE_NUM GENMASK(12, 0)
+#define SPI_NFI_PROG_LOAD_BYTE_NUM GENMASK(28, 16)
+
+#define REG_SPI_NFI_SNF_STA_CTL1 0x0550
+#define SPI_NFI_READ_FROM_CACHE_DONE BIT(25)
+#define SPI_NFI_LOAD_TO_CACHE_DONE BIT(26)
+
+#define REG_SPI_NFI_SNF_STA_CTL2 0x0554
+
+#define REG_SPI_NFI_SNF_NFI_CNFG 0x055c
+#define SPI_NFI_SPI_MODE BIT(0)
+
+/* SPI NAND Protocol OP */
+#define SPI_NAND_OP_GET_FEATURE 0x0f
+#define SPI_NAND_OP_SET_FEATURE 0x1f
+#define SPI_NAND_OP_PAGE_READ 0x13
+#define SPI_NAND_OP_READ_FROM_CACHE_SINGLE 0x03
+#define SPI_NAND_OP_READ_FROM_CACHE_SINGLE_FAST 0x0b
+#define SPI_NAND_OP_READ_FROM_CACHE_DUAL 0x3b
+#define SPI_NAND_OP_READ_FROM_CACHE_QUAD 0x6b
+#define SPI_NAND_OP_WRITE_ENABLE 0x06
+#define SPI_NAND_OP_WRITE_DISABLE 0x04
+#define SPI_NAND_OP_PROGRAM_LOAD_SINGLE 0x02
+#define SPI_NAND_OP_PROGRAM_LOAD_QUAD 0x32
+#define SPI_NAND_OP_PROGRAM_LOAD_RAMDOM_SINGLE 0x84
+#define SPI_NAND_OP_PROGRAM_LOAD_RAMDON_QUAD 0x34
+#define SPI_NAND_OP_PROGRAM_EXECUTE 0x10
+#define SPI_NAND_OP_READ_ID 0x9f
+#define SPI_NAND_OP_BLOCK_ERASE 0xd8
+#define SPI_NAND_OP_RESET 0xff
+#define SPI_NAND_OP_DIE_SELECT 0xc2
+
+#define SPI_NAND_CACHE_SIZE (SZ_4K + SZ_256)
+#define SPI_MAX_TRANSFER_SIZE 511
+
+enum airoha_snand_mode {
+ SPI_MODE_AUTO,
+ SPI_MODE_MANUAL,
+ SPI_MODE_DMA,
+};
+
+enum airoha_snand_cs {
+ SPI_CHIP_SEL_HIGH,
+ SPI_CHIP_SEL_LOW,
+};
+
+struct airoha_snand_priv {
+ struct regmap *regmap_ctrl;
+ struct regmap *regmap_nfi;
+ struct clk *spi_clk;
+
+ struct {
+ size_t page_size;
+ size_t sec_size;
+ u8 sec_num;
+ u8 spare_size;
+ } nfi_cfg;
+};
+
+static int airoha_snand_set_fifo_op(struct airoha_snand_priv *priv,
+ u8 op_cmd, int op_len)
+{
+ int err;
+ u32 val;
+
+ err = regmap_write(priv->regmap_ctrl, REG_SPI_CTRL_OPFIFO_WDATA,
+ FIELD_PREP(SPI_CTRL_OPFIFO_LEN, op_len) |
+ FIELD_PREP(SPI_CTRL_OPFIFO_OP, op_cmd));
+ if (err)
+ return err;
+
+ err = regmap_read_poll_timeout(priv->regmap_ctrl,
+ REG_SPI_CTRL_OPFIFO_FULL,
+ val, !(val & SPI_CTRL_OPFIFO_FULL),
+ 0, 250 * USEC_PER_MSEC);
+ if (err)
+ return err;
+
+ err = regmap_write(priv->regmap_ctrl, REG_SPI_CTRL_OPFIFO_WR,
+ SPI_CTRL_OPFIFO_WR);
+ if (err)
+ return err;
+
+ return regmap_read_poll_timeout(priv->regmap_ctrl,
+ REG_SPI_CTRL_OPFIFO_EMPTY,
+ val, (val & SPI_CTRL_OPFIFO_EMPTY),
+ 0, 250 * USEC_PER_MSEC);
+}
+
+static int airoha_snand_set_cs(struct airoha_snand_priv *priv, u8 cs)
+{
+ return airoha_snand_set_fifo_op(priv, cs, sizeof(cs));
+}
+
+static int airoha_snand_write_data_to_fifo(struct airoha_snand_priv *priv,
+ const u8 *data, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ int err;
+ u32 val;
+
+ /* 1. Wait until dfifo is not full */
+ err = regmap_read_poll_timeout(priv->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_FULL, val,
+ !(val & SPI_CTRL_DFIFO_FULL),
+ 0, 250 * USEC_PER_MSEC);
+ if (err)
+ return err;
+
+ /* 2. Write data to register DFIFO_WDATA */
+ err = regmap_write(priv->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_WDATA,
+ FIELD_PREP(SPI_CTRL_DFIFO_WDATA, data[i]));
+ if (err)
+ return err;
+
+ /* 3. Wait until dfifo is not full */
+ err = regmap_read_poll_timeout(priv->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_FULL, val,
+ !(val & SPI_CTRL_DFIFO_FULL),
+ 0, 250 * USEC_PER_MSEC);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+static int airoha_snand_read_data_from_fifo(struct airoha_snand_priv *priv,
+ u8 *ptr, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ int err;
+ u32 val;
+
+ /* 1. wait until dfifo is not empty */
+ err = regmap_read_poll_timeout(priv->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_EMPTY, val,
+ !(val & SPI_CTRL_DFIFO_EMPTY),
+ 0, 250 * USEC_PER_MSEC);
+ if (err)
+ return err;
+
+ /* 2. read from dfifo to register DFIFO_RDATA */
+ err = regmap_read(priv->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_RDATA, &val);
+ if (err)
+ return err;
+
+ ptr[i] = FIELD_GET(SPI_CTRL_DFIFO_RDATA, val);
+ /* 3. enable register DFIFO_RD to read next byte */
+ err = regmap_write(priv->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_RD, SPI_CTRL_DFIFO_RD);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+static int airoha_snand_set_mode(struct airoha_snand_priv *priv,
+ enum airoha_snand_mode mode)
+{
+ int err;
+
+ switch (mode) {
+ case SPI_MODE_MANUAL: {
+ u32 val;
+
+ err = regmap_write(priv->regmap_ctrl,
+ REG_SPI_CTRL_NFI2SPI_EN, 0);
+ if (err)
+ return err;
+
+ err = regmap_write(priv->regmap_ctrl,
+ REG_SPI_CTRL_READ_IDLE_EN, 0);
+ if (err)
+ return err;
+
+ err = regmap_read_poll_timeout(priv->regmap_ctrl,
+ REG_SPI_CTRL_RDCTL_FSM, val,
+ !(val & SPI_CTRL_RDCTL_FSM),
+ 0, 250 * USEC_PER_MSEC);
+ if (err)
+ return err;
+
+ err = regmap_write(priv->regmap_ctrl,
+ REG_SPI_CTRL_MTX_MODE_TOG, 9);
+ if (err)
+ return err;
+
+ err = regmap_write(priv->regmap_ctrl,
+ REG_SPI_CTRL_MANUAL_EN, SPI_CTRL_MANUAL_EN);
+ if (err)
+ return err;
+ break;
+ }
+ case SPI_MODE_DMA:
+ err = regmap_write(priv->regmap_ctrl,
+ REG_SPI_CTRL_NFI2SPI_EN,
+ SPI_CTRL_MANUAL_EN);
+ if (err < 0)
+ return err;
+
+ err = regmap_write(priv->regmap_ctrl,
+ REG_SPI_CTRL_MTX_MODE_TOG, 0x0);
+ if (err < 0)
+ return err;
+
+ err = regmap_write(priv->regmap_ctrl,
+ REG_SPI_CTRL_MANUAL_EN, 0x0);
+ if (err < 0)
+ return err;
+ break;
+ case SPI_MODE_AUTO:
+ default:
+ break;
+ }
+
+ return regmap_write(priv->regmap_ctrl, REG_SPI_CTRL_DUMMY, 0);
+}
+
+static int airoha_snand_write_data(struct airoha_snand_priv *priv, u8 cmd,
+ const u8 *data, int len)
+{
+ int i, data_len;
+
+ for (i = 0; i < len; i += data_len) {
+ int err;
+
+ data_len = min(len - i, SPI_MAX_TRANSFER_SIZE);
+ err = airoha_snand_set_fifo_op(priv, cmd, data_len);
+ if (err)
+ return err;
+
+ err = airoha_snand_write_data_to_fifo(priv, &data[i],
+ data_len);
+ if (err < 0)
+ return err;
+ }
+
+ return 0;
+}
+
+static int airoha_snand_read_data(struct airoha_snand_priv *priv, u8 *data,
+ int len)
+{
+ int i, data_len;
+
+ for (i = 0; i < len; i += data_len) {
+ int err;
+
+ data_len = min(len - i, SPI_MAX_TRANSFER_SIZE);
+ err = airoha_snand_set_fifo_op(priv, 0xc, data_len);
+ if (err)
+ return err;
+
+ err = airoha_snand_read_data_from_fifo(priv, &data[i],
+ data_len);
+ if (err < 0)
+ return err;
+ }
+
+ return 0;
+}
+
+static int airoha_snand_nfi_init(struct airoha_snand_priv *priv)
+{
+ int err;
+
+ /* switch to SNFI mode */
+ err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_SNF_NFI_CNFG,
+ SPI_NFI_SPI_MODE);
+ if (err)
+ return err;
+
+ /* Enable DMA */
+ return regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_INTR_EN,
+ SPI_NFI_ALL_IRQ_EN, SPI_NFI_AHB_DONE_EN);
+}
+
+static int airoha_snand_nfi_config(struct airoha_snand_priv *priv)
+{
+ int err;
+ u32 val;
+
+ err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_CON,
+ SPI_NFI_FIFO_FLUSH | SPI_NFI_RST);
+ if (err)
+ return err;
+
+ /* auto FDM */
+ err = regmap_clear_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_AUTO_FDM_EN);
+ if (err)
+ return err;
+
+ /* HW ECC */
+ err = regmap_clear_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_HW_ECC_EN);
+ if (err)
+ return err;
+
+ /* DMA Burst */
+ err = regmap_set_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_DMA_BURST_EN);
+ if (err)
+ return err;
+
+ /* page format */
+ switch (priv->nfi_cfg.spare_size) {
+ case 26:
+ val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x1);
+ break;
+ case 27:
+ val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x2);
+ break;
+ case 28:
+ val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x3);
+ break;
+ default:
+ val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x0);
+ break;
+ }
+
+ err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_PAGEFMT,
+ SPI_NFI_SPARE_SIZE, val);
+ if (err)
+ return err;
+
+ switch (priv->nfi_cfg.page_size) {
+ case 2048:
+ val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x1);
+ break;
+ case 4096:
+ val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x2);
+ break;
+ default:
+ val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x0);
+ break;
+ }
+
+ err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_PAGEFMT,
+ SPI_NFI_PAGE_SIZE, val);
+ if (err)
+ return err;
+
+ /* sec num */
+ val = FIELD_PREP(SPI_NFI_SEC_NUM, priv->nfi_cfg.sec_num);
+ err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CON,
+ SPI_NFI_SEC_NUM, val);
+ if (err)
+ return err;
+
+ /* enable cust sec size */
+ err = regmap_set_bits(priv->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE,
+ SPI_NFI_CUS_SEC_SIZE_EN);
+ if (err)
+ return err;
+
+ /* set cust sec size */
+ val = FIELD_PREP(SPI_NFI_CUS_SEC_SIZE, priv->nfi_cfg.sec_size);
+ return regmap_update_bits(priv->regmap_nfi,
+ REG_SPI_NFI_SECCUS_SIZE,
+ SPI_NFI_CUS_SEC_SIZE, val);
+}
+
+static int airoha_snand_adjust_op_size(struct spi_slave *slave,
+ struct spi_mem_op *op)
+{
+ size_t max_len;
+
+ max_len = 1 + op->addr.nbytes + op->dummy.nbytes;
+ if (max_len >= 160)
+ return -EOPNOTSUPP;
+
+ if (op->data.nbytes > 160 - max_len)
+ op->data.nbytes = 160 - max_len;
+
+ return 0;
+}
+
+static bool airoha_snand_supports_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
+{
+ if (!spi_mem_default_supports_op(slave, op))
+ return false;
+
+ if (op->cmd.buswidth != 1)
+ return false;
+
+ return (!op->addr.nbytes || op->addr.buswidth == 1) &&
+ (!op->dummy.nbytes || op->dummy.buswidth == 1) &&
+ (!op->data.nbytes || op->data.buswidth == 1);
+}
+
+static int airoha_snand_exec_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
+{
+ u8 data[8], cmd, opcode = op->cmd.opcode;
+ struct udevice *bus = slave->dev->parent;
+ struct airoha_snand_priv *priv;
+ int i, err;
+
+ priv = dev_get_priv(bus);
+
+ /* switch to manual mode */
+ err = airoha_snand_set_mode(priv, SPI_MODE_MANUAL);
+ if (err < 0)
+ return err;
+
+ err = airoha_snand_set_cs(priv, SPI_CHIP_SEL_LOW);
+ if (err < 0)
+ return err;
+
+ /* opcode */
+ err = airoha_snand_write_data(priv, 0x8, &opcode, sizeof(opcode));
+ if (err)
+ return err;
+
+ /* addr part */
+ cmd = opcode == SPI_NAND_OP_GET_FEATURE ? 0x11 : 0x8;
+ put_unaligned_be64(op->addr.val, data);
+
+ for (i = ARRAY_SIZE(data) - op->addr.nbytes;
+ i < ARRAY_SIZE(data); i++) {
+ err = airoha_snand_write_data(priv, cmd, &data[i],
+ sizeof(data[0]));
+ if (err)
+ return err;
+ }
+
+ /* dummy */
+ data[0] = 0xff;
+ for (i = 0; i < op->dummy.nbytes; i++) {
+ err = airoha_snand_write_data(priv, 0x8, &data[0],
+ sizeof(data[0]));
+ if (err)
+ return err;
+ }
+
+ /* data */
+ if (op->data.dir == SPI_MEM_DATA_IN) {
+ err = airoha_snand_read_data(priv, op->data.buf.in,
+ op->data.nbytes);
+ if (err)
+ return err;
+ } else {
+ err = airoha_snand_write_data(priv, 0x8, op->data.buf.out,
+ op->data.nbytes);
+ if (err)
+ return err;
+ }
+
+ return airoha_snand_set_cs(priv, SPI_CHIP_SEL_HIGH);
+}
+
+static int airoha_snand_probe(struct udevice *dev)
+{
+ struct airoha_snand_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = regmap_init_mem_index(dev_ofnode(dev), &priv->regmap_ctrl, 0);
+ if (ret) {
+ dev_err(dev, "failed to init spi ctrl regmap\n");
+ return ret;
+ }
+
+ ret = regmap_init_mem_index(dev_ofnode(dev), &priv->regmap_nfi, 1);
+ if (ret) {
+ dev_err(dev, "failed to init spi nfi regmap\n");
+ return ret;
+ }
+
+ priv->spi_clk = devm_clk_get(dev, "spi");
+ if (IS_ERR(priv->spi_clk)) {
+ dev_err(dev, "unable to get spi clk\n");
+ return PTR_ERR(priv->regmap_ctrl);
+ }
+ clk_enable(priv->spi_clk);
+
+ return airoha_snand_nfi_init(priv);
+}
+
+static int airoha_snand_nfi_set_speed(struct udevice *bus, uint speed)
+{
+ struct airoha_snand_priv *priv = dev_get_priv(bus);
+ int ret;
+
+ ret = clk_set_rate(priv->spi_clk, speed);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int airoha_snand_nfi_set_mode(struct udevice *bus, uint mode)
+{
+ return 0;
+}
+
+static int airoha_snand_nfi_setup(struct spi_slave *slave,
+ const struct spinand_info *spinand_info)
+{
+ struct udevice *bus = slave->dev->parent;
+ struct airoha_snand_priv *priv;
+ u32 sec_size, sec_num;
+ int pagesize, oobsize;
+
+ priv = dev_get_priv(bus);
+
+ pagesize = spinand_info->memorg.pagesize;
+ oobsize = spinand_info->memorg.oobsize;
+
+ if (pagesize == 2 * 1024)
+ sec_num = 4;
+ else if (pagesize == 4 * 1024)
+ sec_num = 8;
+ else
+ sec_num = 1;
+
+ sec_size = (pagesize + oobsize) / sec_num;
+
+ /* init default value */
+ priv->nfi_cfg.sec_size = sec_size;
+ priv->nfi_cfg.sec_num = sec_num;
+ priv->nfi_cfg.page_size = round_down(sec_size * sec_num, 1024);
+ priv->nfi_cfg.spare_size = 16;
+
+ return airoha_snand_nfi_config(priv);
+}
+
+static const struct spi_controller_mem_ops airoha_snand_mem_ops = {
+ .adjust_op_size = airoha_snand_adjust_op_size,
+ .supports_op = airoha_snand_supports_op,
+ .exec_op = airoha_snand_exec_op,
+};
+
+static const struct dm_spi_ops airoha_snfi_spi_ops = {
+ .mem_ops = &airoha_snand_mem_ops,
+ .set_speed = airoha_snand_nfi_set_speed,
+ .set_mode = airoha_snand_nfi_set_mode,
+ .setup_for_spinand = airoha_snand_nfi_setup,
+};
+
+static const struct udevice_id airoha_snand_ids[] = {
+ { .compatible = "airoha,en7581-snand" },
+ { }
+};
+
+U_BOOT_DRIVER(airoha_snfi_spi) = {
+ .name = "airoha-snfi-spi",
+ .id = UCLASS_SPI,
+ .of_match = airoha_snand_ids,
+ .ops = &airoha_snfi_spi_ops,
+ .priv_auto = sizeof(struct airoha_snand_priv),
+ .probe = airoha_snand_probe,
+};
diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c
index 816916d..fbeb0c6 100644
--- a/drivers/spi/cadence_ospi_versal.c
+++ b/drivers/spi/cadence_ospi_versal.c
@@ -204,3 +204,22 @@
~VERSAL_OSPI_LINEAR_MODE, VERSAL_AXI_MUX_SEL);
}
}
+
+int cadence_device_reset(struct udevice *bus)
+{
+ struct cadence_spi_priv *priv = dev_get_priv(bus);
+ u32 reg;
+
+ reg = readl(priv->regbase + CQSPI_REG_CONFIG);
+ reg |= CQSPI_REG_CONFIG_RESET_CFG_FLD_MASK;
+ writel(reg, priv->regbase + CQSPI_REG_CONFIG);
+
+ writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, priv->regbase + CQSPI_REG_CONFIG);
+ udelay(5);
+ writel(reg | CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, priv->regbase + CQSPI_REG_CONFIG);
+ udelay(150);
+ writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, priv->regbase + CQSPI_REG_CONFIG);
+ udelay(1200);
+
+ return 0;
+}
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 623904e..9edbfaa 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -27,12 +27,20 @@
#define CQSPI_READ 2
#define CQSPI_WRITE 3
+/* Quirks */
+#define CQSPI_DISABLE_STIG_MODE BIT(0)
+
__weak int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
const struct spi_mem_op *op)
{
return 0;
}
+__weak int cadence_device_reset(struct udevice *dev)
+{
+ return 0;
+}
+
__weak int cadence_qspi_flash_reset(struct udevice *dev)
{
return 0;
@@ -217,6 +225,7 @@
priv->tsd2d_ns = plat->tsd2d_ns;
priv->tchsh_ns = plat->tchsh_ns;
priv->tslch_ns = plat->tslch_ns;
+ priv->quirks = plat->quirks;
if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE))
xilinx_pm_request(PM_REQUEST_NODE, PM_DEV_OSPI,
@@ -251,6 +260,9 @@
priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz);
+ if (device_is_compatible(bus, "amd,versal2-ospi"))
+ return cadence_device_reset(bus);
+
/* Reset ospi flash device */
return cadence_qspi_flash_reset(bus);
@@ -307,12 +319,16 @@
* which is unsupported on some flash devices during register
* reads, prefer STIG mode for such small reads.
*/
- if (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
+ if (!op->addr.nbytes ||
+ (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX &&
+ !(priv->quirks & CQSPI_DISABLE_STIG_MODE)))
mode = CQSPI_STIG_READ;
else
mode = CQSPI_READ;
} else {
- if (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
+ if (!op->addr.nbytes || !op->data.buf.out ||
+ (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX &&
+ !(priv->quirks & CQSPI_DISABLE_STIG_MODE)))
mode = CQSPI_STIG_WRITE;
else
mode = CQSPI_WRITE;
@@ -427,6 +443,10 @@
plat->read_delay = ofnode_read_s32_default(subnode, "cdns,read-delay",
-1);
+ const struct cqspi_driver_platdata *drvdata =
+ (struct cqspi_driver_platdata *)dev_get_driver_data(bus);
+ plat->quirks = drvdata->quirks;
+
debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
__func__, plat->regbase, plat->ahbbase, plat->max_hz,
plat->page_size);
@@ -449,9 +469,21 @@
*/
};
+static const struct cqspi_driver_platdata cdns_qspi = {
+ .quirks = CQSPI_DISABLE_STIG_MODE,
+};
+
static const struct udevice_id cadence_spi_ids[] = {
- { .compatible = "cdns,qspi-nor" },
- { .compatible = "ti,am654-ospi" },
+ {
+ .compatible = "cdns,qspi-nor",
+ .data = (ulong)&cdns_qspi,
+ },
+ {
+ .compatible = "ti,am654-ospi"
+ },
+ {
+ .compatible = "amd,versal2-ospi"
+ },
{ }
};
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index 1f9125c..80510f2 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -45,6 +45,8 @@
#define CQSPI_REG_CONFIG_CLK_POL BIT(1)
#define CQSPI_REG_CONFIG_CLK_PHA BIT(2)
#define CQSPI_REG_CONFIG_PHY_ENABLE_MASK BIT(3)
+#define CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK BIT(5)
+#define CQSPI_REG_CONFIG_RESET_CFG_FLD_MASK BIT(6)
#define CQSPI_REG_CONFIG_DIRECT BIT(7)
#define CQSPI_REG_CONFIG_DECODE BIT(9)
#define CQSPI_REG_CONFIG_ENBL_DMA BIT(15)
@@ -220,6 +222,7 @@
u32 tsd2d_ns;
u32 tchsh_ns;
u32 tslch_ns;
+ u32 quirks;
bool is_dma;
};
@@ -251,6 +254,7 @@
u32 tsd2d_ns;
u32 tchsh_ns;
u32 tslch_ns;
+ u32 quirks;
u8 edge_mode;
u8 dll_mode;
bool extra_dummy;
@@ -266,6 +270,11 @@
bool dtr;
};
+struct cqspi_driver_platdata {
+ u32 hwcaps_mask;
+ u32 quirks;
+};
+
/* Functions call declaration */
void cadence_qspi_apb_controller_init(struct cadence_spi_priv *priv);
void cadence_qspi_apb_controller_enable(void *reg_base_addr);
@@ -310,5 +319,6 @@
int cadence_qspi_flash_reset(struct udevice *dev);
ofnode cadence_qspi_get_subnode(struct udevice *dev);
void cadence_qspi_apb_enable_linear_mode(bool enable);
+int cadence_device_reset(struct udevice *dev);
#endif /* __CADENCE_QSPI_H__ */
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index f2f69cf..b579699 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -747,6 +747,10 @@
goto failrd;
}
+ /* Wait til QSPI is idle */
+ if (!cadence_qspi_wait_idle(priv->regbase))
+ return -EIO;
+
return 0;
failrd:
@@ -914,6 +918,11 @@
if (bounce_buf)
free(bounce_buf);
+
+ /* Wait til QSPI is idle */
+ if (!cadence_qspi_wait_idle(priv->regbase))
+ return -EIO;
+
return 0;
failwr:
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index c7f5548..65ab3e3 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -472,7 +472,13 @@
op->addr.nbytes) {
for (i = 0; i < ARRAY_SIZE(lutval); i++)
qspi_writel(q, lutval[i], base + QUADSPI_AHB_LUT_REG(i));
+
+ qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT_AHB),
+ q->iobase + QUADSPI_BFGENCR);
}
+ } else {
+ qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT),
+ q->iobase + QUADSPI_BFGENCR);
}
/* lock LUT */
@@ -737,13 +743,6 @@
qspi_writel(q, 0, base + QUADSPI_BUF1IND);
qspi_writel(q, 0, base + QUADSPI_BUF2IND);
- if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP))
- qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT_AHB),
- q->iobase + QUADSPI_BFGENCR);
- else
- qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT),
- q->iobase + QUADSPI_BFGENCR);
-
qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);
qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8),
diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c
index d54a504..097d916 100644
--- a/drivers/spi/tegra20_slink.c
+++ b/drivers/spi/tegra20_slink.c
@@ -29,7 +29,10 @@
#define SLINK_CMD_IDLE_SCLK_PULL_LOW (2 << 24)
#define SLINK_CMD_IDLE_SCLK_PULL_HIGH (3 << 24)
#define SLINK_CMD_IDLE_SCLK_MASK (3 << 24)
+#define SLINK_CMD_CS_POL3 BIT(23)
+#define SLINK_CMD_CS_POL2 BIT(22)
#define SLINK_CMD_CK_SDA BIT(21)
+#define SLINK_CMD_CS_POL1 BIT(20)
#define SLINK_CMD_CS_POL BIT(13)
#define SLINK_CMD_CS_VAL BIT(12)
#define SLINK_CMD_CS_SOFT BIT(11)
@@ -64,6 +67,13 @@
#define SPI_TIMEOUT 1000
#define TEGRA_SPI_MAX_FREQ 52000000
+unsigned int cmd_cs_pol_bit[] = {
+ SLINK_CMD_CS_POL,
+ SLINK_CMD_CS_POL1,
+ SLINK_CMD_CS_POL2,
+ SLINK_CMD_CS_POL3,
+};
+
struct spi_regs {
u32 command; /* SLINK_COMMAND_0 register */
u32 command2; /* SLINK_COMMAND2_0 reg */
@@ -155,6 +165,14 @@
writel(reg, ®s->status);
debug("%s: STATUS = %08x\n", __func__, readl(®s->status));
+ /* Update the polarity bits */
+ if (priv->mode & SPI_CS_HIGH)
+ setbits_le32(&priv->regs->command,
+ cmd_cs_pol_bit[spi_chip_select(dev)]);
+ else
+ clrbits_le32(&priv->regs->command,
+ cmd_cs_pol_bit[spi_chip_select(dev)]);
+
/* Set master mode and sw controlled CS */
reg = readl(®s->command);
reg |= SLINK_CMD_M_S | SLINK_CMD_CS_SOFT;
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 475540f..4972905 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -71,6 +71,27 @@
Support for system poweroff using a GPIO pin. This can be used
for systems having a single GPIO to trigger a system poweroff.
+config SPL_POWEROFF_GPIO
+ bool "Enable support for GPIO poweroff driver in SPL"
+ depends on DM_GPIO && SPL
+ help
+ Support for system poweroff using a GPIO pin in SPL. This can be used
+ for systems having a single GPIO to trigger a system poweroff.
+
+config TPL_POWEROFF_GPIO
+ bool "Enable support for GPIO poweroff driver in TPL"
+ depends on DM_GPIO && TPL
+ help
+ Support for system poweroff using a GPIO pin in TPL. This can be used
+ for systems having a single GPIO to trigger a system poweroff.
+
+config VPL_POWEROFF_GPIO
+ bool "Enable support for GPIO poweroff driver in VPL"
+ depends on DM_GPIO && VPL
+ help
+ Support for system poweroff using a GPIO pin in VPL. This can be used
+ for systems having a single GPIO to trigger a system poweroff.
+
config SYSRESET_GPIO
bool "Enable support for GPIO reset driver"
depends on DM_GPIO
@@ -79,6 +100,30 @@
example on Microblaze where reset logic can be controlled via GPIO
pin which triggers cpu reset.
+config SPL_SYSRESET_GPIO
+ bool "Enable support for GPIO reset driver in SPL"
+ depends on DM_GPIO && SPL
+ help
+ Reset support via GPIO pin connected reset logic in SPL. This is used
+ for example on Microblaze where reset logic can be controlled via
+ GPIO pin which triggers cpu reset.
+
+config TPL_SYSRESET_GPIO
+ bool "Enable support for GPIO reset driver in TPL"
+ depends on DM_GPIO && TPL
+ help
+ Reset support via GPIO pin connected reset logic in TPL. This is used
+ for example on Microblaze where reset logic can be controlled via
+ GPIO pin which triggers cpu reset.
+
+config VPL_SYSRESET_GPIO
+ bool "Enable support for GPIO reset driver in VPL"
+ depends on DM_GPIO && VPL
+ help
+ Reset support via GPIO pin connected reset logic in VPL. This is used
+ for example on Microblaze where reset logic can be controlled via
+ GPIO pin which triggers cpu reset.
+
config SYSRESET_MAX77663
bool "Enable support for MAX77663 PMIC System Reset"
depends on DM_PMIC_MAX77663
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index 796fc9e..ded91a4 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -8,8 +8,8 @@
obj-$(CONFIG_ARCH_STI) += sysreset_sti.o
obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
obj-$(CONFIG_SYSRESET_CV1800B) += sysreset_cv1800b.o
-obj-$(CONFIG_POWEROFF_GPIO) += poweroff_gpio.o
-obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o
+obj-$(CONFIG_$(PHASE_)POWEROFF_GPIO) += poweroff_gpio.o
+obj-$(CONFIG_$(PHASE_)SYSRESET_GPIO) += sysreset_gpio.o
obj-$(CONFIG_$(PHASE_)SYSRESET_MAX77663) += sysreset_max77663.o
obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o
obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index 7a847e8..21db0d3 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -5,14 +5,14 @@
obj-y += timer-uclass.o
obj-$(CONFIG_ADI_SC5XX_TIMER) += adi_sc5xx_timer.o
obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
-obj-$(CONFIG_$(XPL_)ANDES_PLMT_TIMER) += andes_plmt_timer.o
+obj-$(CONFIG_$(PHASE_)ANDES_PLMT_TIMER) += andes_plmt_timer.o
obj-$(CONFIG_ARC_TIMER) += arc_timer.o
obj-$(CONFIG_ARM_TWD_TIMER) += arm_twd_timer.o
obj-$(CONFIG_AST_TIMER) += ast_timer.o
obj-$(CONFIG_AST_IBEX_TIMER) += ast_ibex_timer.o
obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o
-obj-$(CONFIG_$(XPL_)ATMEL_PIT_TIMER) += atmel_pit_timer.o
-obj-$(CONFIG_$(XPL_)ATMEL_TCB_TIMER) += atmel_tcb_timer.o
+obj-$(CONFIG_$(PHASE_)ATMEL_PIT_TIMER) += atmel_pit_timer.o
+obj-$(CONFIG_$(PHASE_)ATMEL_TCB_TIMER) += atmel_tcb_timer.o
obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o
obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o
obj-$(CONFIG_FTTMR010_TIMER) += fttmr010_timer.o
@@ -27,7 +27,7 @@
obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o
obj-$(CONFIG_SP804_TIMER) += sp804_timer.o
-obj-$(CONFIG_$(XPL_)RISCV_ACLINT) += riscv_aclint_timer.o
+obj-$(CONFIG_$(PHASE_)RISCV_ACLINT) += riscv_aclint_timer.o
obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
obj-$(CONFIG_STM32_TIMER) += stm32_timer.o
obj-$(CONFIG_TEGRA_TIMER) += tegra-timer.o
diff --git a/drivers/tpm/cr50_i2c.c b/drivers/tpm/cr50_i2c.c
index 08ec179..5b2d5cc 100644
--- a/drivers/tpm/cr50_i2c.c
+++ b/drivers/tpm/cr50_i2c.c
@@ -737,9 +737,13 @@
static int cr50_i2c_open(struct udevice *dev)
{
+ struct cr50_priv *priv = dev_get_priv(dev);
char buf[80];
int ret;
+ if (priv->locality != -1)
+ return -EBUSY;
+
ret = process_reset(dev);
if (ret)
return log_msg_ret("reset", ret);
diff --git a/drivers/ufs/ufs-amd-versal2.c b/drivers/ufs/ufs-amd-versal2.c
index bfd844e..1c5ed53 100644
--- a/drivers/ufs/ufs-amd-versal2.c
+++ b/drivers/ufs/ufs-amd-versal2.c
@@ -19,8 +19,6 @@
#include "ufshcd-dwc.h"
#include "ufshci-dwc.h"
-#define VERSAL2_UFS_DEVICE_ID 4
-
#define SRAM_CSR_INIT_DONE_MASK BIT(0)
#define SRAM_CSR_EXT_LD_DONE_MASK BIT(1)
#define SRAM_CSR_BYPASS_MASK BIT(2)
@@ -32,19 +30,12 @@
#define TIMEOUT_MICROSEC 1000000L
-#define IOCTL_UFS_TXRX_CFGRDY_GET 40
-#define IOCTL_UFS_SRAM_CSR_SEL 41
-
-#define PM_UFS_SRAM_CSR_WRITE 0
-#define PM_UFS_SRAM_CSR_READ 1
-
struct ufs_versal2_priv {
struct ufs_hba *hba;
struct reset_ctl *rstc;
struct reset_ctl *rstphy;
u32 phy_mode;
u32 host_clk;
- u32 pd_dev_id;
u8 attcompval0;
u8 attcompval1;
u8 ctlecompval0;
@@ -102,41 +93,6 @@
return 0;
}
-int versal2_pm_ufs_get_txrx_cfgrdy(u32 node_id, u32 *value)
-{
- u32 ret_payload[PAYLOAD_ARG_CNT];
- int ret;
-
- if (!value)
- return -EINVAL;
-
- ret = xilinx_pm_request(PM_IOCTL, node_id, IOCTL_UFS_TXRX_CFGRDY_GET,
- 0, 0, ret_payload);
- *value = ret_payload[1];
-
- return ret;
-}
-
-int versal2_pm_ufs_sram_csr_sel(u32 node_id, u32 type, u32 *value)
-{
- u32 ret_payload[PAYLOAD_ARG_CNT];
- int ret;
-
- if (!value)
- return -EINVAL;
-
- if (type == PM_UFS_SRAM_CSR_READ) {
- ret = xilinx_pm_request(PM_IOCTL, node_id, IOCTL_UFS_SRAM_CSR_SEL,
- type, 0, ret_payload);
- *value = ret_payload[1];
- } else {
- ret = xilinx_pm_request(PM_IOCTL, node_id, IOCTL_UFS_SRAM_CSR_SEL,
- type, *value, 0);
- }
-
- return ret;
-}
-
static int ufs_versal2_enable_phy(struct ufs_hba *hba)
{
u32 offset, reg;
@@ -281,7 +237,7 @@
time_left = TIMEOUT_MICROSEC;
do {
time_left--;
- ret = versal2_pm_ufs_get_txrx_cfgrdy(priv->pd_dev_id, ®);
+ ret = zynqmp_pm_ufs_get_txrx_cfgrdy(®);
if (ret)
return ret;
@@ -312,8 +268,7 @@
time_left = TIMEOUT_MICROSEC;
do {
time_left--;
- ret = versal2_pm_ufs_sram_csr_sel(priv->pd_dev_id,
- PM_UFS_SRAM_CSR_READ, ®);
+ ret = zynqmp_pm_ufs_sram_csr_read(®);
if (ret)
return ret;
@@ -341,10 +296,10 @@
struct ufs_versal2_priv *priv = dev_get_priv(hba->dev);
struct clk clk;
unsigned long core_clk_rate = 0;
+ u32 cal;
int ret = 0;
priv->phy_mode = UFSHCD_DWC_PHY_MODE_ROM;
- priv->pd_dev_id = VERSAL2_UFS_DEVICE_ID;
ret = clk_get_by_name(hba->dev, "core_clk", &clk);
if (ret) {
@@ -371,6 +326,15 @@
return PTR_ERR(priv->rstphy);
}
+ ret = zynqmp_pm_ufs_cal_reg(&cal);
+ if (ret)
+ return ret;
+
+ priv->attcompval0 = (u8)cal;
+ priv->attcompval1 = (u8)(cal >> 8);
+ priv->ctlecompval0 = (u8)(cal >> 16);
+ priv->ctlecompval1 = (u8)(cal >> 24);
+
return ret;
}
@@ -397,8 +361,7 @@
return ret;
}
- ret = versal2_pm_ufs_sram_csr_sel(priv->pd_dev_id,
- PM_UFS_SRAM_CSR_READ, &sram_csr);
+ ret = zynqmp_pm_ufs_sram_csr_read(&sram_csr);
if (ret)
return ret;
@@ -410,8 +373,7 @@
return -EINVAL;
}
- ret = versal2_pm_ufs_sram_csr_sel(priv->pd_dev_id,
- PM_UFS_SRAM_CSR_WRITE, &sram_csr);
+ ret = zynqmp_pm_ufs_sram_csr_write(&sram_csr);
if (ret)
return ret;
diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile
index 1f00f23..dea5316 100644
--- a/drivers/usb/cdns3/Makefile
+++ b/drivers/usb/cdns3/Makefile
@@ -4,9 +4,9 @@
obj-$(CONFIG_USB_CDNS3) += cdns3.o
-cdns3-$(CONFIG_$(XPL_)USB_CDNS3_GADGET) += gadget.o ep0.o
+cdns3-$(CONFIG_$(PHASE_)USB_CDNS3_GADGET) += gadget.o ep0.o
-cdns3-$(CONFIG_$(XPL_)USB_CDNS3_HOST) += host.o
+cdns3-$(CONFIG_$(PHASE_)USB_CDNS3_HOST) += host.o
obj-$(CONFIG_USB_CDNS3_STARFIVE) += cdns3-starfive.o
obj-$(CONFIG_USB_CDNS3_TI) += cdns3-ti.o
diff --git a/drivers/usb/common/Makefile b/drivers/usb/common/Makefile
index 11cc465..4c597c1 100644
--- a/drivers/usb/common/Makefile
+++ b/drivers/usb/common/Makefile
@@ -3,7 +3,7 @@
# (C) Copyright 2016 Freescale Semiconductor, Inc.
#
-obj-$(CONFIG_$(XPL_)DM_USB) += common.o
+obj-$(CONFIG_$(PHASE_)DM_USB) += common.o
obj-$(CONFIG_USB_ISP1760) += usb_urb.o
obj-$(CONFIG_USB_MUSB_HOST) += usb_urb.o
obj-$(CONFIG_USB_MUSB_GADGET) += usb_urb.o
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
index 985206e..a619cd3 100644
--- a/drivers/usb/dwc3/Makefile
+++ b/drivers/usb/dwc3/Makefile
@@ -6,11 +6,11 @@
obj-$(CONFIG_USB_DWC3_GADGET) += gadget.o ep0.o
-obj-$(CONFIG_$(XPL_)USB_DWC3_AM62) += dwc3-am62.o
+obj-$(CONFIG_$(PHASE_)USB_DWC3_AM62) += dwc3-am62.o
obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o
obj-$(CONFIG_USB_DWC3_MESON_G12A) += dwc3-meson-g12a.o
obj-$(CONFIG_USB_DWC3_MESON_GXL) += dwc3-meson-gxl.o
-obj-$(CONFIG_$(XPL_)USB_DWC3_GENERIC) += dwc3-generic.o
+obj-$(CONFIG_$(PHASE_)USB_DWC3_GENERIC) += dwc3-generic.o
obj-$(CONFIG_USB_DWC3_UNIPHIER) += dwc3-uniphier.o
obj-$(CONFIG_USB_DWC3_LAYERSCAPE) += dwc3-layerscape.o
obj-$(CONFIG_USB_DWC3_PHY_OMAP) += ti_usb_phy.o
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 477ecd0..2b01113 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -1635,7 +1635,7 @@
/*
* Special workaround for NXP UUU tool in SPL.
*
- * The tool excepts the interrupt-in endpoint to be ep1in,
+ * The tool expects the interrupt-in endpoint to be ep1in,
* otherwise it crashes. This is a result of the previous
* hard-coded EP setup in drivers/usb/gadget/epautoconf.c
* which did special-case EP allocation for SPL builds,
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index c815764..46a8314 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -85,6 +85,7 @@
default 0x330e if ROCKCHIP_RK3308
default 0x350a if ROCKCHIP_RK3568
default 0x350b if ROCKCHIP_RK3588
+ default 0x350c if ROCKCHIP_RK3528
default 0x0
help
Product ID of the USB device emulated, reported to the host device.
diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
index a77037a..f9326f0 100644
--- a/drivers/usb/gadget/atmel_usba_udc.c
+++ b/drivers/usb/gadget/atmel_usba_udc.c
@@ -1443,6 +1443,7 @@
{ .compatible = "atmel,at91sam9rl-udc" },
{ .compatible = "atmel,at91sam9g45-udc" },
{ .compatible = "atmel,sama5d3-udc" },
+ { .compatible = "microchip,sam9x60-udc" },
{}
};
diff --git a/drivers/usb/gadget/f_acm.c b/drivers/usb/gadget/f_acm.c
index f18c6a0..8f72560 100644
--- a/drivers/usb/gadget/f_acm.c
+++ b/drivers/usb/gadget/f_acm.c
@@ -238,18 +238,21 @@
return -ENODEV;
f_acm->ep_in = ep;
+ ep->driver_data = c->cdev; /* claim */
ep = usb_ep_autoconfig(gadget, &acm_fs_out_desc);
if (!ep)
return -ENODEV;
f_acm->ep_out = ep;
+ ep->driver_data = c->cdev; /* claim */
ep = usb_ep_autoconfig(gadget, &acm_fs_notify_desc);
if (!ep)
return -ENODEV;
f_acm->ep_notify = ep;
+ ep->driver_data = c->cdev; /* claim */
if (gadget_is_dualspeed(gadget)) {
/* Assume endpoint addresses are the same for both speeds */
@@ -660,6 +663,7 @@
{
g_dnl_unregister();
g_dnl_clear_detach();
+ dev->priv = NULL;
return 0;
}
diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c
index d3fc4ac..71dc58d 100644
--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -284,7 +284,6 @@
#define kthread_create(...) __builtin_return_address(0)
#define wait_for_completion(...) do {} while (0)
-struct kref {int x; };
struct completion {int x; };
struct fsg_dev;
@@ -345,8 +344,6 @@
/* Vendor (8 chars), product (16 chars), release (4
* hexadecimal digits) and NUL byte */
char inquiry_string[8 + 16 + 4 + 1];
-
- struct kref ref;
};
struct fsg_config {
@@ -2436,7 +2433,7 @@
return 0;
}
-static void fsg_common_release(struct kref *ref);
+static void fsg_common_release(struct fsg_common *common);
static struct fsg_common *fsg_common_init(struct fsg_common *common,
struct usb_composite_dev *cdev)
@@ -2548,16 +2545,12 @@
common->nluns = i + 1;
error_release:
common->state = FSG_STATE_TERMINATED; /* The thread is dead */
- /* Call fsg_common_release() directly, ref might be not
- * initialised */
- fsg_common_release(&common->ref);
+ fsg_common_release(common);
return ERR_PTR(rc);
}
-static void fsg_common_release(struct kref *ref)
+static void fsg_common_release(struct fsg_common *common)
{
- struct fsg_common *common = container_of(ref, struct fsg_common, ref);
-
/* If the thread isn't already dead, tell it to exit now */
if (common->state != FSG_STATE_TERMINATED) {
raise_exception(common, FSG_STATE_EXIT);
@@ -2571,8 +2564,6 @@
/* In error recovery common->nluns may be zero. */
for (; i; --i, ++lun)
fsg_lun_close(lun);
-
- kfree(common->luns);
}
{
@@ -2648,6 +2639,7 @@
raise_exception(fsg->common, FSG_STATE_CONFIG_CHANGE);
}
+ fsg_common_release(fsg->common);
free(fsg->function.descriptors);
free(fsg->function.hs_descriptors);
kfree(fsg);
@@ -2751,6 +2743,8 @@
struct fsg_common *fsg_common;
fsg_common = fsg_common_init(NULL, c->cdev);
+ if (IS_ERR(fsg_common))
+ return PTR_ERR(fsg_common);
fsg_common->vendor_name = 0;
fsg_common->product_name = 0;
diff --git a/drivers/usb/gadget/udc/Makefile b/drivers/usb/gadget/udc/Makefile
index 4b6a8fd..56b9b12 100644
--- a/drivers/usb/gadget/udc/Makefile
+++ b/drivers/usb/gadget/udc/Makefile
@@ -2,9 +2,9 @@
#
# USB peripheral controller drivers
-ifndef CONFIG_$(XPL_)DM_USB_GADGET
+ifndef CONFIG_$(PHASE_)DM_USB_GADGET
obj-$(CONFIG_USB_DWC3_GADGET) += udc-core.o
endif
-obj-$(CONFIG_$(XPL_)DM_USB_GADGET) += udc-core.o
+obj-$(CONFIG_$(PHASE_)DM_USB_GADGET) += udc-core.o
obj-y += udc-uclass.o
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 902d68d..ef4ce62 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -3,7 +3,7 @@
# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-ifdef CONFIG_$(XPL_)DM_USB
+ifdef CONFIG_$(PHASE_)DM_USB
obj-y += usb-uclass.o
obj-$(CONFIG_SANDBOX) += usb-sandbox.o
endif
diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c
index bfec303..7247245 100644
--- a/drivers/usb/host/usb-uclass.c
+++ b/drivers/usb/host/usb-uclass.c
@@ -9,6 +9,7 @@
#define LOG_CATEGORY UCLASS_USB
#include <bootdev.h>
+#include <uthread.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
@@ -17,6 +18,7 @@
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dm/uclass-internal.h>
+#include <time.h>
static bool asynch_allowed;
@@ -172,6 +174,10 @@
return ops->get_max_xfer_size(bus, size);
}
+#if CONFIG_IS_ENABLED(UTHREAD)
+static struct uthread_mutex mutex = UTHREAD_MUTEX_INITIALIZER;
+#endif
+
int usb_stop(void)
{
struct udevice *bus;
@@ -180,10 +186,14 @@
struct usb_uclass_priv *uc_priv;
int err = 0, ret;
+ uthread_mutex_lock(&mutex);
+
/* De-activate any devices that have been activated */
ret = uclass_get(UCLASS_USB, &uc);
- if (ret)
+ if (ret) {
+ uthread_mutex_unlock(&mutex);
return ret;
+ }
uc_priv = uclass_get_priv(uc);
@@ -218,28 +228,23 @@
uc_priv->companion_device_count = 0;
usb_started = 0;
+ uthread_mutex_unlock(&mutex);
+
return err;
}
-static void usb_scan_bus(struct udevice *bus, bool recurse)
+static void _usb_scan_bus(void *arg)
{
+ struct udevice *bus = (struct udevice *)arg;
struct usb_bus_priv *priv;
struct udevice *dev;
int ret;
priv = dev_get_uclass_priv(bus);
- assert(recurse); /* TODO: Support non-recusive */
-
- printf("scanning bus %s for devices... ", bus->name);
- debug("\n");
ret = usb_scan_device(bus, 0, USB_SPEED_FULL, &dev);
if (ret)
- printf("failed, error %d\n", ret);
- else if (priv->next_addr == 0)
- printf("No USB Device found\n");
- else
- printf("%d USB Device(s) found\n", priv->next_addr);
+ printf("Scanning bus %s failed, error %d\n", bus->name, ret);
}
static void remove_inactive_children(struct uclass *uc, struct udevice *bus)
@@ -287,64 +292,127 @@
return 0;
}
+static void _usb_init_bus(void *arg)
+{
+ struct udevice *bus = (struct udevice *)arg;
+ int ret;
+
+ /* init low_level USB */
+
+ /*
+ * For Sandbox, we need scan the device tree each time when we
+ * start the USB stack, in order to re-create the emulated USB
+ * devices and bind drivers for them before we actually do the
+ * driver probe.
+ *
+ * For USB onboard HUB, we need to do some non-trivial init
+ * like enabling a power regulator, before enumeration.
+ */
+ if (IS_ENABLED(CONFIG_SANDBOX) ||
+ IS_ENABLED(CONFIG_USB_ONBOARD_HUB)) {
+ ret = dm_scan_fdt_dev(bus);
+ if (ret) {
+ printf("Bus %s: USB device scan from fdt failed (%d)\n",
+ bus->name, ret);
+ return;
+ }
+ }
+
+ ret = device_probe(bus);
+ if (ret == -ENODEV) { /* No such device. */
+ printf("Bus %s: Port not available.\n", bus->name);
+ return;
+ }
+
+ if (ret) { /* Other error. */
+ printf("Bus %s: probe failed, error %d\n", bus->name, ret);
+ return;
+ }
+
+ usb_probe_companion(bus);
+}
+
+static int nthr;
+static int grp_id;
+
+static void usb_init_bus(struct udevice *bus)
+{
+ if (!grp_id)
+ grp_id = uthread_grp_new_id();
+ if (!uthread_create(NULL, _usb_init_bus, (void *)bus, 0, grp_id))
+ nthr++;
+}
+
+static void usb_scan_bus(struct udevice *bus, bool recurse)
+{
+ if (!grp_id)
+ grp_id = uthread_grp_new_id();
+ if (!uthread_create(NULL, _usb_scan_bus, (void *)bus, 0, grp_id))
+ nthr++;
+}
+
+static void usb_report_devices(struct uclass *uc)
+{
+ struct usb_bus_priv *priv;
+ struct udevice *bus;
+
+ uclass_foreach_dev(bus, uc) {
+ if (!device_active(bus))
+ continue;
+ priv = dev_get_uclass_priv(bus);
+ printf("Bus %s: ", bus->name);
+ if (priv->next_addr == 0)
+ printf("No USB Device found\n");
+ else
+ printf("%d USB Device(s) found\n", priv->next_addr);
+ }
+}
+
+static void run_threads(void)
+{
+#if CONFIG_IS_ENABLED(UTHREAD)
+ if (!nthr)
+ return;
+ while (!uthread_grp_done(grp_id))
+ uthread_schedule();
+ nthr = 0;
+ grp_id = 0;
+#endif
+}
+
int usb_init(void)
{
int controllers_initialized = 0;
+ unsigned long t0 = timer_get_us();
struct usb_uclass_priv *uc_priv;
struct usb_bus_priv *priv;
struct udevice *bus;
struct uclass *uc;
int ret;
+ uthread_mutex_lock(&mutex);
+
+ if (usb_started) {
+ ret = 0;
+ goto out;
+ }
+
asynch_allowed = 1;
ret = uclass_get(UCLASS_USB, &uc);
if (ret)
- return ret;
+ goto out;
uc_priv = uclass_get_priv(uc);
uclass_foreach_dev(bus, uc) {
- /* init low_level USB */
- printf("Bus %s: ", bus->name);
-
- /*
- * For Sandbox, we need scan the device tree each time when we
- * start the USB stack, in order to re-create the emulated USB
- * devices and bind drivers for them before we actually do the
- * driver probe.
- *
- * For USB onboard HUB, we need to do some non-trivial init
- * like enabling a power regulator, before enumeration.
- */
- if (IS_ENABLED(CONFIG_SANDBOX) ||
- IS_ENABLED(CONFIG_USB_ONBOARD_HUB)) {
- ret = dm_scan_fdt_dev(bus);
- if (ret) {
- printf("USB device scan from fdt failed (%d)", ret);
- continue;
- }
- }
-
- ret = device_probe(bus);
- if (ret == -ENODEV) { /* No such device. */
- puts("Port not available.\n");
- controllers_initialized++;
- continue;
- }
-
- if (ret) { /* Other error. */
- printf("probe failed, error %d\n", ret);
- continue;
- }
+ usb_init_bus(bus);
+ }
- ret = usb_probe_companion(bus);
- if (ret)
- continue;
+ if (CONFIG_IS_ENABLED(UTHREAD))
+ run_threads();
- controllers_initialized++;
- usb_started = true;
- }
+ usb_started = true;
/*
* lowlevel init done, now scan the bus for devices i.e. search HUBs
@@ -354,11 +422,16 @@
if (!device_active(bus))
continue;
+ controllers_initialized++;
+
priv = dev_get_uclass_priv(bus);
if (!priv->companion)
usb_scan_bus(bus, true);
}
+ if (CONFIG_IS_ENABLED(UTHREAD))
+ run_threads();
+
/*
* Now that the primary controllers have been scanned and have handed
* over any devices they do not understand to their companions, scan
@@ -375,21 +448,34 @@
}
}
- debug("scan end\n");
+ if (CONFIG_IS_ENABLED(UTHREAD))
+ run_threads();
+
+ usb_report_devices(uc);
/* Remove any devices that were not found on this scan */
remove_inactive_children(uc, bus);
ret = uclass_get(UCLASS_USB_HUB, &uc);
if (ret)
- return ret;
+ goto out;
+
remove_inactive_children(uc, bus);
/* if we were not able to find at least one working bus, bail out */
if (controllers_initialized == 0)
printf("No USB controllers found\n");
+ debug("USB initialized in %ld ms\n",
+ (timer_get_us() - t0) / 1000);
+
+ uthread_mutex_unlock(&mutex);
+
return usb_started ? 0 : -ENOENT;
+out:
+ uthread_mutex_unlock(&mutex);
+
+ return ret;
}
int usb_setup_ehci_gadget(struct ehci_ctrl **ctlrp)
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index df60730..80508fb 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -89,15 +89,33 @@
config VIDEO_COPY
bool "Enable copying the frame buffer to a hardware copy"
+ select VIDEO_DAMAGE
help
On some machines (e.g. x86), reading from the frame buffer is very
slow because it is uncached. To improve performance, this feature
allows the frame buffer to be kept in cached memory (allocated by
U-Boot) and then copied to the hardware frame-buffer as needed.
+ It uses the VIDEO_DAMAGE feature to keep track of regions to copy
+ and will only copy actually touched regions.
To use this, your video driver must set @copy_base in
struct video_uc_plat.
+config VIDEO_DAMAGE
+ bool "Enable damage tracking of frame buffer regions"
+ help
+ On some machines (most ARM), the display frame buffer resides in
+ RAM. To make the display controller pick up screen updates, we
+ have to flush frame buffer contents from CPU caches into RAM which
+ can be a slow operation.
+
+ This feature adds damage tracking to collect information about regions
+ that received updates. When we want to sync, we then only flush
+ regions of the frame buffer that were modified before, speeding up
+ screen refreshes significantly.
+
+ It is also used by VIDEO_COPY to identify which regions changed.
+
config BACKLIGHT_PWM
bool "Generic PWM based Backlight Driver"
depends on BACKLIGHT && DM_PWM
@@ -495,6 +513,7 @@
config ATMEL_LCD
bool "Atmel LCD panel support"
+ imply VIDEO_DAMAGE
depends on ARCH_AT91
config ATMEL_LCD_BGR555
@@ -504,6 +523,7 @@
config VIDEO_BCM2835
bool "Display support for BCM2835"
+ imply VIDEO_DAMAGE
help
The graphics processor already sets up the display so this driver
simply checks the resolution and then sets up the frame buffer with
@@ -529,6 +549,16 @@
Say Y here if you want to enable support for Himax HX8394
dsi 4dl panel.
+config VIDEO_LCD_MOT
+ tristate "Atrix 4G and Droid X2 540x960 DSI video mode panel"
+ depends on PANEL && BACKLIGHT
+ select VIDEO_MIPI_DSI
+ help
+ Say Y here if you want to enable support for the LCD panel module for
+ Motorola Atrix 4G or Droid X2. Exact panel vendor and model are
+ unknown. The panel has a 540x960 resolution and uses 24 bit RGB per
+ pixel.
+
config VIDEO_LCD_ORISETECH_OTM8009A
bool "OTM8009A DSI LCD panel support"
select VIDEO_MIPI_DSI
@@ -685,6 +715,7 @@
config VIDEO_MVEBU
bool "Armada XP LCD controller"
+ imply VIDEO_DAMAGE
---help---
Support for the LCD controller integrated in the Marvell
Armada XP SoC.
@@ -725,9 +756,19 @@
config ATMEL_HLCD
bool "Enable ATMEL video support using HLCDC"
+ imply VIDEO_DAMAGE
help
HLCDC supports video output to an attached LCD panel.
+config BACKLIGHT_LM3532
+ bool "Backlight Driver for LM3532"
+ depends on BACKLIGHT
+ select DM_I2C
+ help
+ Say Y to enable the backlight driver for National Semiconductor / TI
+ LM3532 Lighting Power chip. Only backlight functions is supported as
+ for now. Supported backlight level range is from 1 to 255.
+
config BACKLIGHT_LM3533
bool "Backlight Driver for LM3533"
depends on BACKLIGHT
@@ -809,22 +850,15 @@
source "drivers/video/tidss/Kconfig"
-config VIDEO_TEGRA124
- bool "Enable video support on Tegra124"
- help
- Tegra124 supports many video output options including eDP and
- HDMI. At present only eDP is supported by U-Boot. This option
- enables this support which can be used on devices which
- have an eDP display connected.
-
source "drivers/video/bridge/Kconfig"
-source "drivers/video/tegra20/Kconfig"
+source "drivers/video/tegra/Kconfig"
source "drivers/video/imx/Kconfig"
config VIDEO_MXS
bool "Enable video support on i.MX28/i.MX6UL/i.MX7 SoCs"
+ imply VIDEO_DAMAGE
help
Enable framebuffer driver for i.MX28/i.MX6UL/i.MX7 processors
@@ -887,6 +921,7 @@
config VIDEO_SIMPLE
bool "Simple display driver for preconfigured display"
+ imply VIDEO_DAMAGE
help
Enables a simple generic display driver which utilizes the
simple-framebuffer devicetree bindings.
@@ -905,6 +940,7 @@
config VIDEO_MCDE_SIMPLE
bool "Simple driver for ST-Ericsson MCDE with preconfigured display"
+ imply VIDEO_DAMAGE
help
Enables a simple display driver for ST-Ericsson MCDE
(Multichannel Display Engine), which reads the configuration from
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 6073bc5..fbdb058 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -29,13 +29,13 @@
endif
+obj-$(CONFIG_BACKLIGHT_LM3532) += lm3532_backlight.o
obj-$(CONFIG_BACKLIGHT_LM3533) += lm3533_backlight.o
obj-$(CONFIG_BACKLIGHT_LP855x) += lp855x_backlight.o
obj-${CONFIG_EXYNOS_FB} += exynos/
obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/
obj-${CONFIG_VIDEO_STM32} += stm32/
-obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
-obj-${CONFIG_$(XPL_)VIDEO_TIDSS} += tidss/
+obj-${CONFIG_$(PHASE_)VIDEO_TIDSS} += tidss/
obj-y += ti/
obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
@@ -53,13 +53,14 @@
obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o
obj-$(CONFIG_VIDEO_DW_MIPI_DSI) += dw_mipi_dsi.o
obj-$(CONFIG_VIDEO_EFI) += efi.o
-obj-$(CONFIG_VIDEO_IPUV3) += imx/
+obj-y += imx/
obj-$(CONFIG_VIDEO_IVYBRIDGE_IGD) += ivybridge_igd.o
obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o
obj-$(CONFIG_VIDEO_LCD_ENDEAVORU) += endeavoru-panel.o
obj-$(CONFIG_VIDEO_LCD_HIMAX_HX8394) += himax-hx8394.o
obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
obj-$(CONFIG_VIDEO_LCD_LG_LD070WX3) += lg-ld070wx3.o
+obj-$(CONFIG_VIDEO_LCD_MOT) += mot-panel.o
obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o
obj-$(CONFIG_VIDEO_LCD_RENESAS_R61307) += renesas-r61307.o
@@ -85,4 +86,4 @@
obj-y += bridge/
obj-y += sunxi/
-obj-y += tegra20/
+obj-y += tegra/
diff --git a/drivers/video/console_normal.c b/drivers/video/console_normal.c
index 6f4194a..07db613 100644
--- a/drivers/video/console_normal.c
+++ b/drivers/video/console_normal.c
@@ -35,9 +35,11 @@
fill_pixel_and_goto_next(&dst, clr, pbytes, pbytes);
end = dst;
- ret = vidconsole_sync_copy(dev, line, end);
- if (ret)
- return ret;
+ video_damage(dev->parent,
+ 0,
+ fontdata->height * row,
+ vid_priv->xsize,
+ fontdata->height);
return 0;
}
@@ -51,14 +53,17 @@
void *dst;
void *src;
int size;
- int ret;
dst = vid_priv->fb + rowdst * fontdata->height * vid_priv->line_length;
src = vid_priv->fb + rowsrc * fontdata->height * vid_priv->line_length;
size = fontdata->height * vid_priv->line_length * count;
- ret = vidconsole_memmove(dev, dst, src, size);
- if (ret)
- return ret;
+ memmove(dst, src, size);
+
+ video_damage(dev->parent,
+ 0,
+ fontdata->height * rowdst,
+ vid_priv->xsize,
+ fontdata->height * count);
return 0;
}
@@ -91,9 +96,11 @@
if (ret)
return ret;
- ret = vidconsole_sync_copy(dev, start, line);
- if (ret)
- return ret;
+ video_damage(dev->parent,
+ x,
+ y,
+ fontdata->width,
+ fontdata->height);
return VID_TO_POS(fontdata->width);
}
diff --git a/drivers/video/console_rotate.c b/drivers/video/console_rotate.c
index a3f8c63..886b25d 100644
--- a/drivers/video/console_rotate.c
+++ b/drivers/video/console_rotate.c
@@ -21,7 +21,6 @@
int pbytes = VNBYTES(vid_priv->bpix);
void *start, *dst, *line;
int i, j;
- int ret;
start = vid_priv->fb + vid_priv->line_length -
(row + 1) * fontdata->height * pbytes;
@@ -32,9 +31,12 @@
fill_pixel_and_goto_next(&dst, clr, pbytes, pbytes);
line += vid_priv->line_length;
}
- ret = vidconsole_sync_copy(dev, start, line);
- if (ret)
- return ret;
+
+ video_damage(dev->parent,
+ vid_priv->xsize - ((row + 1) * fontdata->height),
+ 0,
+ fontdata->height,
+ vid_priv->ysize);
return 0;
}
@@ -48,7 +50,7 @@
int pbytes = VNBYTES(vid_priv->bpix);
void *dst;
void *src;
- int j, ret;
+ int j;
dst = vid_priv->fb + vid_priv->line_length -
(rowdst + count) * fontdata->height * pbytes;
@@ -56,14 +58,17 @@
(rowsrc + count) * fontdata->height * pbytes;
for (j = 0; j < vid_priv->ysize; j++) {
- ret = vidconsole_memmove(dev, dst, src,
- fontdata->height * pbytes * count);
- if (ret)
- return ret;
+ memmove(dst, src, fontdata->height * pbytes * count);
src += vid_priv->line_length;
dst += vid_priv->line_length;
}
+ video_damage(dev->parent,
+ vid_priv->xsize - ((rowdst + count) * fontdata->height),
+ 0,
+ count * fontdata->height,
+ vid_priv->ysize);
+
return 0;
}
@@ -93,9 +98,11 @@
return ret;
/* We draw backwards from 'start, so account for the first line */
- ret = vidconsole_sync_copy(dev, start - vid_priv->line_length, line);
- if (ret)
- return ret;
+ video_damage(dev->parent,
+ vid_priv->xsize - y - fontdata->height,
+ linenum - 1,
+ fontdata->height,
+ fontdata->width);
return VID_TO_POS(fontdata->width);
}
@@ -107,7 +114,7 @@
struct video_fontdata *fontdata = priv->fontdata;
void *start, *line, *dst, *end;
int pixels = fontdata->height * vid_priv->xsize;
- int i, ret;
+ int i;
int pbytes = VNBYTES(vid_priv->bpix);
start = vid_priv->fb + vid_priv->ysize * vid_priv->line_length -
@@ -117,9 +124,12 @@
for (i = 0; i < pixels; i++)
fill_pixel_and_goto_next(&dst, clr, pbytes, pbytes);
end = dst;
- ret = vidconsole_sync_copy(dev, start, end);
- if (ret)
- return ret;
+
+ video_damage(dev->parent,
+ 0,
+ vid_priv->ysize - (row + 1) * fontdata->height,
+ vid_priv->xsize,
+ fontdata->height);
return 0;
}
@@ -139,8 +149,13 @@
vid_priv->line_length;
src = end - (rowsrc + count) * fontdata->height *
vid_priv->line_length;
- vidconsole_memmove(dev, dst, src,
- fontdata->height * vid_priv->line_length * count);
+ memmove(dst, src, fontdata->height * vid_priv->line_length * count);
+
+ video_damage(dev->parent,
+ 0,
+ vid_priv->ysize - (rowdst + count) * fontdata->height,
+ vid_priv->xsize,
+ count * fontdata->height);
return 0;
}
@@ -170,10 +185,11 @@
if (ret)
return ret;
- /* Add 4 bytes to allow for the first pixel writen */
- ret = vidconsole_sync_copy(dev, start + 4, line);
- if (ret)
- return ret;
+ video_damage(dev->parent,
+ x - fontdata->width + 1,
+ linenum - fontdata->height + 1,
+ fontdata->width,
+ fontdata->height);
return VID_TO_POS(fontdata->width);
}
@@ -185,7 +201,7 @@
struct video_fontdata *fontdata = priv->fontdata;
int pbytes = VNBYTES(vid_priv->bpix);
void *start, *dst, *line;
- int i, j, ret;
+ int i, j;
start = vid_priv->fb + row * fontdata->height * pbytes;
line = start;
@@ -195,9 +211,12 @@
fill_pixel_and_goto_next(&dst, clr, pbytes, pbytes);
line += vid_priv->line_length;
}
- ret = vidconsole_sync_copy(dev, start, line);
- if (ret)
- return ret;
+
+ video_damage(dev->parent,
+ row * fontdata->height,
+ 0,
+ fontdata->height,
+ vid_priv->ysize);
return 0;
}
@@ -211,20 +230,23 @@
int pbytes = VNBYTES(vid_priv->bpix);
void *dst;
void *src;
- int j, ret;
+ int j;
dst = vid_priv->fb + rowdst * fontdata->height * pbytes;
src = vid_priv->fb + rowsrc * fontdata->height * pbytes;
for (j = 0; j < vid_priv->ysize; j++) {
- ret = vidconsole_memmove(dev, dst, src,
- fontdata->height * pbytes * count);
- if (ret)
- return ret;
+ memmove(dst, src, fontdata->height * pbytes * count);
src += vid_priv->line_length;
dst += vid_priv->line_length;
}
+ video_damage(dev->parent,
+ rowdst * fontdata->height,
+ 0,
+ count * fontdata->height,
+ vid_priv->ysize);
+
return 0;
}
@@ -252,11 +274,13 @@
ret = fill_char_horizontally(pfont, &line, vid_priv, fontdata, NORMAL_DIRECTION);
if (ret)
return ret;
- /* Add a line to allow for the first pixels writen */
- ret = vidconsole_sync_copy(dev, start + vid_priv->line_length, line);
- if (ret)
- return ret;
+ video_damage(dev->parent,
+ y,
+ linenum - fontdata->width + 1,
+ fontdata->height,
+ fontdata->width);
+
return VID_TO_POS(fontdata->width);
}
diff --git a/drivers/video/console_truetype.c b/drivers/video/console_truetype.c
index 17a2981..980baee 100644
--- a/drivers/video/console_truetype.c
+++ b/drivers/video/console_truetype.c
@@ -190,10 +190,10 @@
static int console_truetype_set_row(struct udevice *dev, uint row, int clr)
{
struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent);
+ struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev);
struct console_tt_priv *priv = dev_get_priv(dev);
struct console_tt_metrics *met = priv->cur_met;
void *end, *line;
- int ret;
line = vid_priv->fb + row * met->font_size * vid_priv->line_length;
end = line + met->font_size * vid_priv->line_length;
@@ -229,9 +229,12 @@
default:
return -ENOSYS;
}
- ret = vidconsole_sync_copy(dev, line, end);
- if (ret)
- return ret;
+
+ video_damage(dev->parent,
+ 0,
+ vc_priv->y_charsize * row,
+ vid_priv->xsize,
+ vc_priv->y_charsize);
return 0;
}
@@ -240,24 +243,28 @@
uint rowsrc, uint count)
{
struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent);
+ struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev);
struct console_tt_priv *priv = dev_get_priv(dev);
struct console_tt_metrics *met = priv->cur_met;
void *dst;
void *src;
- int i, diff, ret;
+ int i, diff;
dst = vid_priv->fb + rowdst * met->font_size * vid_priv->line_length;
src = vid_priv->fb + rowsrc * met->font_size * vid_priv->line_length;
- ret = vidconsole_memmove(dev, dst, src, met->font_size *
- vid_priv->line_length * count);
- if (ret)
- return ret;
+ memmove(dst, src, met->font_size * vid_priv->line_length * count);
/* Scroll up our position history */
diff = (rowsrc - rowdst) * met->font_size;
for (i = 0; i < priv->pos_ptr; i++)
priv->pos[i].ypos -= diff;
+ video_damage(dev->parent,
+ 0,
+ vc_priv->y_charsize * rowdst,
+ vid_priv->xsize,
+ vc_priv->y_charsize * count);
+
return 0;
}
@@ -278,7 +285,7 @@
u8 *bits, *data;
int advance;
void *start, *end, *line;
- int row, ret;
+ int row;
/* First get some basic metrics about this character */
stbtt_GetCodepointHMetrics(font, cp, &advance, &lsb);
@@ -418,9 +425,13 @@
line += vid_priv->line_length;
}
- ret = vidconsole_sync_copy(dev, start, line);
- if (ret)
- return ret;
+
+ video_damage(dev->parent,
+ VID_TO_PIXEL(x) + xoff,
+ y + met->baseline + yoff,
+ width,
+ height);
+
free(data);
return width_frac;
@@ -851,7 +862,6 @@
uint row, width, height, xoff;
void *start, *line;
uint out, val;
- int ret;
if (xpl_phase() <= PHASE_SPL)
return -ENOSYS;
@@ -941,9 +951,8 @@
line += vid_priv->line_length;
}
- ret = vidconsole_sync_copy(dev, start, line);
- if (ret)
- return ret;
+
+ video_damage(dev->parent, x, y, width, height);
return video_sync(vid, true);
}
diff --git a/drivers/video/exynos/Kconfig b/drivers/video/exynos/Kconfig
index 599d19d..a2cf752 100644
--- a/drivers/video/exynos/Kconfig
+++ b/drivers/video/exynos/Kconfig
@@ -12,6 +12,7 @@
config EXYNOS_FB
bool "Exynos FIMD support"
+ imply VIDEO_DAMAGE
config EXYNOS_MIPI_DSIM
bool "Exynos MIPI DSI support"
diff --git a/drivers/video/imx/Kconfig b/drivers/video/imx/Kconfig
index 34e8b64..4a1927c 100644
--- a/drivers/video/imx/Kconfig
+++ b/drivers/video/imx/Kconfig
@@ -2,6 +2,7 @@
config VIDEO_IPUV3
bool "i.MX IPUv3 Core video support"
depends on VIDEO && (MX5 || MX6)
+ imply VIDEO_DAMAGE
help
This enables framebuffer driver for i.MX processors working
on the IPUv3(Image Processing Unit) internal graphic processor.
@@ -13,3 +14,12 @@
config IMX_HDMI
bool "Enable HDMI support in IPUv3"
depends on VIDEO_IPUV3
+
+config IMX_LDB
+ bool "Freescale i.MX8MP LDB bridge"
+ depends on VIDEO_BRIDGE
+ help
+ Support for i.MX8MP DPI-to-LVDS on-SoC encoder.
+
+config IMX_LCDIF
+ bool "i.MX LCDIFv3 LCD controller"
diff --git a/drivers/video/imx/Makefile b/drivers/video/imx/Makefile
index 179ea65..1edf5a6 100644
--- a/drivers/video/imx/Makefile
+++ b/drivers/video/imx/Makefile
@@ -3,4 +3,6 @@
# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-obj-y += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
+obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
+obj-$(CONFIG_IMX_LDB) += ldb.o
+obj-$(CONFIG_IMX_LCDIF) += lcdif.o
diff --git a/drivers/video/imx/lcdif.c b/drivers/video/imx/lcdif.c
new file mode 100644
index 0000000..9f4fc7f
--- /dev/null
+++ b/drivers/video/imx/lcdif.c
@@ -0,0 +1,314 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * i.MX8 LCD interface driver inspired from the Linux driver
+ * Copyright 2019 NXP
+ * Copyright 2024 Bootlin
+ * Adapted by Miquel Raynal <miquel.raynal@bootlin.com>
+ */
+
+#include <asm/io.h>
+#include <asm/mach-imx/dma.h>
+#include <clk.h>
+#include <dm.h>
+#include <panel.h>
+#include <power-domain.h>
+#include <video.h>
+#include <video_bridge.h>
+#include <linux/delay.h>
+
+#include "../videomodes.h"
+
+#define LCDIFV3_CTRL 0x0
+#define LCDIFV3_CTRL_SET 0x4
+#define LCDIFV3_CTRL_CLR 0x8
+#define CTRL_INV_HS BIT(0)
+#define CTRL_INV_VS BIT(1)
+#define CTRL_INV_DE BIT(2)
+#define CTRL_INV_PXCK BIT(3)
+#define CTRL_CLK_GATE BIT(30)
+#define CTRL_SW_RESET BIT(31)
+
+#define LCDIFV3_DISP_PARA 0x10
+#define DISP_PARA_DISP_MODE_NORMAL 0
+#define DISP_PARA_LINE_PATTERN_RGB_YUV 0
+#define DISP_PARA_DISP_ON BIT(31)
+
+#define LCDIFV3_DISP_SIZE 0x14
+#define DISP_SIZE_DELTA_X(x) ((x) & 0xffff)
+#define DISP_SIZE_DELTA_Y(x) ((x) << 16)
+
+#define LCDIFV3_HSYN_PARA 0x18
+#define HSYN_PARA_FP_H(x) ((x) & 0xffff)
+#define HSYN_PARA_BP_H(x) ((x) << 16)
+
+#define LCDIFV3_VSYN_PARA 0x1C
+#define VSYN_PARA_FP_V(x) ((x) & 0xffff)
+#define VSYN_PARA_BP_V(x) ((x) << 16)
+
+#define LCDIFV3_VSYN_HSYN_WIDTH 0x20
+#define VSYN_HSYN_PW_H(x) ((x) & 0xffff)
+#define VSYN_HSYN_PW_V(x) ((x) << 16)
+
+#define LCDIFV3_CTRLDESCL0_1 0x200
+#define CTRLDESCL0_1_WIDTH(x) ((x) & 0xffff)
+#define CTRLDESCL0_1_HEIGHT(x) ((x) << 16)
+
+#define LCDIFV3_CTRLDESCL0_3 0x208
+#define CTRLDESCL0_3_PITCH(x) ((x) & 0xFFFF)
+
+#define LCDIFV3_CTRLDESCL_LOW0_4 0x20C
+#define LCDIFV3_CTRLDESCL_HIGH0_4 0x210
+
+#define LCDIFV3_CTRLDESCL0_5 0x214
+#define CTRLDESCL0_5_YUV_FORMAT(x) (((x) & 0x3) << 14)
+#define CTRLDESCL0_5_BPP(x) (((x) & 0xf) << 24)
+#define BPP32_ARGB8888 0x9
+#define CTRLDESCL0_5_SHADOW_LOAD_EN BIT(30)
+#define CTRLDESCL0_5_EN BIT(31)
+
+struct lcdifv3_priv {
+ void __iomem *base;
+ struct clk pix_clk;
+ struct power_domain pd;
+ struct udevice *panel;
+ struct udevice *bridge;
+};
+
+static void lcdifv3_set_mode(struct lcdifv3_priv *priv,
+ struct display_timing *timings)
+{
+ u32 reg;
+
+ writel(DISP_SIZE_DELTA_X(timings->hactive.typ) |
+ DISP_SIZE_DELTA_Y(timings->vactive.typ),
+ priv->base + LCDIFV3_DISP_SIZE);
+
+ writel(HSYN_PARA_FP_H(timings->hfront_porch.typ) |
+ HSYN_PARA_BP_H(timings->hback_porch.typ),
+ priv->base + LCDIFV3_HSYN_PARA);
+
+ writel(VSYN_PARA_BP_V(timings->vback_porch.typ) |
+ VSYN_PARA_FP_V(timings->vfront_porch.typ),
+ priv->base + LCDIFV3_VSYN_PARA);
+
+ writel(VSYN_HSYN_PW_H(timings->hsync_len.typ) |
+ VSYN_HSYN_PW_V(timings->vsync_len.typ),
+ priv->base + LCDIFV3_VSYN_HSYN_WIDTH);
+
+ writel(CTRLDESCL0_1_WIDTH(timings->hactive.typ) |
+ CTRLDESCL0_1_HEIGHT(timings->vactive.typ),
+ priv->base + LCDIFV3_CTRLDESCL0_1);
+
+ if (timings->flags & DISPLAY_FLAGS_HSYNC_LOW)
+ writel(CTRL_INV_HS, priv->base + LCDIFV3_CTRL_SET);
+ else
+ writel(CTRL_INV_HS, priv->base + LCDIFV3_CTRL_CLR);
+
+ if (timings->flags & DISPLAY_FLAGS_VSYNC_LOW)
+ writel(CTRL_INV_VS, priv->base + LCDIFV3_CTRL_SET);
+ else
+ writel(CTRL_INV_VS, priv->base + LCDIFV3_CTRL_CLR);
+
+ if (timings->flags & DISPLAY_FLAGS_DE_LOW)
+ writel(CTRL_INV_DE, priv->base + LCDIFV3_CTRL_SET);
+ else
+ writel(CTRL_INV_DE, priv->base + LCDIFV3_CTRL_CLR);
+
+ if (timings->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
+ writel(CTRL_INV_PXCK, priv->base + LCDIFV3_CTRL_SET);
+ else
+ writel(CTRL_INV_PXCK, priv->base + LCDIFV3_CTRL_CLR);
+
+ writel(0, priv->base + LCDIFV3_DISP_PARA);
+
+ reg = readl(priv->base + LCDIFV3_CTRLDESCL0_5);
+ reg &= ~(CTRLDESCL0_5_BPP(0xf) | CTRLDESCL0_5_YUV_FORMAT(0x3));
+ reg |= CTRLDESCL0_5_BPP(BPP32_ARGB8888);
+ writel(reg, priv->base + LCDIFV3_CTRLDESCL0_5);
+}
+
+static void lcdifv3_enable_controller(struct lcdifv3_priv *priv)
+{
+ u32 reg;
+
+ reg = readl(priv->base + LCDIFV3_DISP_PARA);
+ reg |= DISP_PARA_DISP_ON;
+ writel(reg, priv->base + LCDIFV3_DISP_PARA);
+
+ reg = readl(priv->base + LCDIFV3_CTRLDESCL0_5);
+ reg |= CTRLDESCL0_5_EN;
+ writel(reg, priv->base + LCDIFV3_CTRLDESCL0_5);
+}
+
+static int lcdifv3_video_sync(struct udevice *dev)
+{
+ struct lcdifv3_priv *priv = dev_get_priv(dev);
+ u32 reg;
+
+ reg = readl(priv->base + LCDIFV3_CTRLDESCL0_5);
+ reg |= CTRLDESCL0_5_SHADOW_LOAD_EN;
+ writel(reg, priv->base + LCDIFV3_CTRLDESCL0_5);
+
+ return 0;
+}
+
+static void lcdifv3_init(struct udevice *dev, struct display_timing *timings)
+{
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
+ struct lcdifv3_priv *priv = dev_get_priv(dev);
+
+ clk_set_rate(&priv->pix_clk, timings->pixelclock.typ);
+
+ writel(CTRL_SW_RESET | CTRL_CLK_GATE, priv->base + LCDIFV3_CTRL_CLR);
+ udelay(10);
+
+ lcdifv3_set_mode(priv, timings);
+
+ writel(plat->base & 0xFFFFFFFF, priv->base + LCDIFV3_CTRLDESCL_LOW0_4);
+ writel(plat->base >> 32, priv->base + LCDIFV3_CTRLDESCL_HIGH0_4);
+
+ writel(CTRLDESCL0_3_PITCH(timings->hactive.typ * 4), /* 32bpp */
+ priv->base + LCDIFV3_CTRLDESCL0_3);
+
+ lcdifv3_enable_controller(priv);
+}
+
+static int lcdifv3_video_probe(struct udevice *dev)
+{
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
+ struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct lcdifv3_priv *priv = dev_get_priv(dev);
+ struct clk axi_clk, disp_axi_clk;
+ struct display_timing timings;
+ u32 fb_start, fb_end;
+ int ret;
+
+ ret = power_domain_get(dev, &priv->pd);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_get_by_name(dev, "pix", &priv->pix_clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_get_by_name(dev, "axi", &axi_clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_get_by_name(dev, "disp_axi", &disp_axi_clk);
+ if (ret < 0)
+ return ret;
+
+ ret = power_domain_on(&priv->pd);
+ if (ret)
+ return ret;
+
+ ret = clk_enable(&priv->pix_clk);
+ if (ret)
+ goto dis_pd;
+
+ ret = clk_enable(&axi_clk);
+ if (ret)
+ goto dis_pix_clk;
+
+ ret = clk_enable(&disp_axi_clk);
+ if (ret)
+ goto dis_axi_clk;
+
+ priv->base = dev_remap_addr(dev);
+ if (!priv->base) {
+ ret = -EINVAL;
+ goto dis_clks;
+ }
+
+ /* Attach bridge */
+ ret = uclass_get_device_by_endpoint(UCLASS_VIDEO_BRIDGE, dev,
+ -1, -1, &priv->bridge);
+ if (ret)
+ goto dis_clks;
+
+ ret = video_bridge_attach(priv->bridge);
+ if (ret)
+ goto dis_clks;
+
+ ret = video_bridge_set_backlight(priv->bridge, 80);
+ if (ret)
+ goto dis_clks;
+
+ /* Attach panels */
+ ret = uclass_get_device_by_endpoint(UCLASS_PANEL, priv->bridge,
+ 1, -1, &priv->panel);
+ if (ret) {
+ ret = uclass_get_device_by_endpoint(UCLASS_PANEL, priv->bridge,
+ 2, -1, &priv->panel);
+ if (ret)
+ goto dis_clks;
+ }
+
+ ret = panel_get_display_timing(priv->panel, &timings);
+ if (ret) {
+ ret = ofnode_decode_display_timing(dev_ofnode(priv->panel),
+ 0, &timings);
+ if (ret) {
+ printf("Cannot decode panel timings (%d)\n", ret);
+ goto dis_clks;
+ }
+ }
+
+ lcdifv3_init(dev, &timings);
+
+ /* Only support 32bpp for now */
+ uc_priv->bpix = VIDEO_BPP32;
+ uc_priv->xsize = timings.hactive.typ;
+ uc_priv->ysize = timings.vactive.typ;
+
+ /* Enable dcache for the frame buffer */
+ fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
+ fb_end = ALIGN(plat->base + plat->size, 1 << MMU_SECTION_SHIFT);
+ mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
+ DCACHE_WRITEBACK);
+ video_set_flush_dcache(dev, true);
+
+ return 0;
+
+dis_clks:
+ clk_disable(&disp_axi_clk);
+dis_axi_clk:
+ clk_disable(&axi_clk);
+dis_pix_clk:
+ clk_disable(&priv->pix_clk);
+dis_pd:
+ power_domain_off(&priv->pd);
+
+ return ret;
+}
+
+static int lcdifv3_video_bind(struct udevice *dev)
+{
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
+
+ /* Max size supported by LCDIF */
+ plat->size = 1920 * 1080 * VNBYTES(VIDEO_BPP32);
+
+ return 0;
+}
+
+static const struct udevice_id lcdifv3_video_ids[] = {
+ { .compatible = "fsl,imx8mp-lcdif" },
+ { }
+};
+
+static struct video_ops lcdifv3_video_ops = {
+ .video_sync = lcdifv3_video_sync,
+};
+
+U_BOOT_DRIVER(lcdifv3_video) = {
+ .name = "lcdif",
+ .id = UCLASS_VIDEO,
+ .of_match = lcdifv3_video_ids,
+ .bind = lcdifv3_video_bind,
+ .ops = &lcdifv3_video_ops,
+ .probe = lcdifv3_video_probe,
+ .priv_auto = sizeof(struct lcdifv3_priv),
+ .flags = DM_FLAG_PRE_RELOC | DM_FLAG_OS_PREPARE,
+};
diff --git a/drivers/video/imx/ldb.c b/drivers/video/imx/ldb.c
new file mode 100644
index 0000000..e918341
--- /dev/null
+++ b/drivers/video/imx/ldb.c
@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Derived work from:
+ * Philippe Cornu <philippe.cornu@st.com>
+ * Yannick Fertre <yannick.fertre@st.com>
+ * Adapted by Miquel Raynal <miquel.raynal@bootlin.com>
+ */
+
+#define LOG_CATEGORY UCLASS_VIDEO_BRIDGE
+
+#include <clk.h>
+#include <dm.h>
+#include <log.h>
+#include <panel.h>
+#include <video_bridge.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+#define LDB_CTRL_CH0_ENABLE BIT(0)
+#define LDB_CTRL_CH1_ENABLE BIT(2)
+#define LDB_CTRL_CH0_DATA_WIDTH BIT(5)
+#define LDB_CTRL_CH0_BIT_MAPPING BIT(6)
+#define LDB_CTRL_CH1_DATA_WIDTH BIT(7)
+#define LDB_CTRL_CH1_BIT_MAPPING BIT(8)
+#define LDB_CTRL_DI0_VSYNC_POLARITY BIT(9)
+#define LDB_CTRL_DI1_VSYNC_POLARITY BIT(10)
+
+#define LVDS_CTRL_CH0_EN BIT(0)
+#define LVDS_CTRL_CH1_EN BIT(1)
+#define LVDS_CTRL_VBG_EN BIT(2)
+#define LVDS_CTRL_PRE_EMPH_EN BIT(4)
+#define LVDS_CTRL_PRE_EMPH_ADJ(n) (((n) & 0x7) << 5)
+#define LVDS_CTRL_CC_ADJ(n) (((n) & 0x7) << 11)
+
+struct imx_ldb_priv {
+ struct clk ldb_clk;
+ void __iomem *ldb_ctrl;
+ void __iomem *lvds_ctrl;
+ struct udevice *lvds1;
+ struct udevice *lvds2;
+};
+
+static int imx_ldb_set_backlight(struct udevice *dev, int percent)
+{
+ struct imx_ldb_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ if (priv->lvds1) {
+ ret = panel_enable_backlight(priv->lvds1);
+ if (ret) {
+ debug("ldb: Cannot enable lvds1 backlight\n");
+ return ret;
+ }
+
+ ret = panel_set_backlight(priv->lvds1, percent);
+ if (ret)
+ return ret;
+ }
+
+ if (priv->lvds2) {
+ ret = panel_enable_backlight(priv->lvds2);
+ if (ret) {
+ debug("ldb: Cannot enable lvds2 backlight\n");
+ return ret;
+ }
+
+ ret = panel_set_backlight(priv->lvds2, percent);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int imx_ldb_of_to_plat(struct udevice *dev)
+{
+ struct imx_ldb_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ uclass_get_device_by_endpoint(UCLASS_PANEL, dev, 1, -1, &priv->lvds1);
+ uclass_get_device_by_endpoint(UCLASS_PANEL, dev, 2, -1, &priv->lvds2);
+ if (!priv->lvds1 && !priv->lvds2) {
+ debug("ldb: No remote panel for '%s' (ret=%d)\n",
+ dev_read_name(dev), ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+/* The block has a mysterious x7 internal divisor (x3.5 in dual configuration) */
+#define IMX_LDB_INTERNAL_DIVISOR(x) (((x) * 70) / 10)
+#define IMX_LDB_INTERNAL_DIVISOR_DUAL(x) (((x) * 35) / 10)
+
+static ulong imx_ldb_input_rate(struct imx_ldb_priv *priv,
+ struct display_timing *timings)
+{
+ ulong target_rate = timings->pixelclock.typ;
+
+ if (priv->lvds1 && priv->lvds2)
+ return IMX_LDB_INTERNAL_DIVISOR_DUAL(target_rate);
+
+ return IMX_LDB_INTERNAL_DIVISOR(target_rate);
+}
+
+static int imx_ldb_attach(struct udevice *dev)
+{
+ struct imx_ldb_priv *priv = dev_get_priv(dev);
+ struct display_timing timings;
+ bool format_jeida = false;
+ bool format_24bpp = true;
+ u32 ldb_ctrl = 0, lvds_ctrl;
+ ulong ldb_rate;
+ int ret;
+
+ /* TODO: update the 24bpp/jeida booleans with proper checks when they
+ * will be supported.
+ */
+ if (priv->lvds1) {
+ ret = panel_get_display_timing(priv->lvds1, &timings);
+ if (ret) {
+ ret = ofnode_decode_display_timing(dev_ofnode(priv->lvds1),
+ 0, &timings);
+ if (ret) {
+ printf("Cannot decode lvds1 timings (%d)\n", ret);
+ return ret;
+ }
+ }
+
+ ldb_ctrl |= LDB_CTRL_CH0_ENABLE;
+ if (format_24bpp)
+ ldb_ctrl |= LDB_CTRL_CH0_DATA_WIDTH;
+ if (format_jeida)
+ ldb_ctrl |= LDB_CTRL_CH0_BIT_MAPPING;
+ if (timings.flags & DISPLAY_FLAGS_VSYNC_HIGH)
+ ldb_ctrl |= LDB_CTRL_DI0_VSYNC_POLARITY;
+ }
+
+ if (priv->lvds2) {
+ ret = panel_get_display_timing(priv->lvds2, &timings);
+ if (ret) {
+ ret = ofnode_decode_display_timing(dev_ofnode(priv->lvds2),
+ 0, &timings);
+ if (ret) {
+ printf("Cannot decode lvds2 timings (%d)\n", ret);
+ return ret;
+ }
+ }
+
+ ldb_ctrl |= LDB_CTRL_CH1_ENABLE;
+ if (format_24bpp)
+ ldb_ctrl |= LDB_CTRL_CH1_DATA_WIDTH;
+ if (format_jeida)
+ ldb_ctrl |= LDB_CTRL_CH1_BIT_MAPPING;
+ if (timings.flags & DISPLAY_FLAGS_VSYNC_HIGH)
+ ldb_ctrl |= LDB_CTRL_DI1_VSYNC_POLARITY;
+ }
+
+ /*
+ * Not all pixel clocks will work, as the final rate (after internal
+ * integer division) should be identical to the LCDIF clock, otherwise
+ * the rendering will appear resized/shimmering.
+ */
+ ldb_rate = imx_ldb_input_rate(priv, &timings);
+ clk_set_rate(&priv->ldb_clk, ldb_rate);
+
+ writel(ldb_ctrl, priv->ldb_ctrl);
+
+ lvds_ctrl = LVDS_CTRL_CC_ADJ(2) | LVDS_CTRL_PRE_EMPH_EN |
+ LVDS_CTRL_PRE_EMPH_ADJ(3) | LVDS_CTRL_VBG_EN;
+ writel(lvds_ctrl, priv->lvds_ctrl);
+
+ /* Wait for VBG to stabilize. */
+ udelay(15);
+
+ if (priv->lvds1)
+ lvds_ctrl |= LVDS_CTRL_CH0_EN;
+ if (priv->lvds2)
+ lvds_ctrl |= LVDS_CTRL_CH1_EN;
+
+ writel(lvds_ctrl, priv->lvds_ctrl);
+
+ return 0;
+}
+
+static int imx_ldb_probe(struct udevice *dev)
+{
+ struct imx_ldb_priv *priv = dev_get_priv(dev);
+ struct udevice *parent = dev_get_parent(dev);
+ fdt_addr_t parent_addr, child_addr;
+ int ret;
+
+ ret = clk_get_by_name(dev, "ldb", &priv->ldb_clk);
+ if (ret < 0)
+ return ret;
+
+ parent_addr = dev_read_addr(parent);
+ if (parent_addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ child_addr = dev_read_addr_name(dev, "ldb");
+ if (child_addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->ldb_ctrl = map_physmem(parent_addr + child_addr, 0, MAP_NOCACHE);
+ if (!priv->ldb_ctrl)
+ return -EINVAL;
+
+ child_addr = dev_read_addr_name(dev, "lvds");
+ if (child_addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->lvds_ctrl = map_physmem(parent_addr + child_addr, 0, MAP_NOCACHE);
+ if (!priv->lvds_ctrl)
+ return -EINVAL;
+
+ ret = clk_enable(&priv->ldb_clk);
+ if (ret)
+ return ret;
+
+ ret = video_bridge_set_active(dev, true);
+ if (ret)
+ goto dis_clk;
+
+ return 0;
+
+dis_clk:
+ clk_disable(&priv->ldb_clk);
+
+ return ret;
+}
+
+struct video_bridge_ops imx_ldb_ops = {
+ .attach = imx_ldb_attach,
+ .set_backlight = imx_ldb_set_backlight,
+};
+
+static const struct udevice_id imx_ldb_ids[] = {
+ { .compatible = "fsl,imx8mp-ldb"},
+ { }
+};
+
+U_BOOT_DRIVER(imx_ldb) = {
+ .name = "imx-lvds-display-bridge",
+ .id = UCLASS_VIDEO_BRIDGE,
+ .of_match = imx_ldb_ids,
+ .probe = imx_ldb_probe,
+ .of_to_plat = imx_ldb_of_to_plat,
+ .ops = &imx_ldb_ops,
+ .priv_auto = sizeof(struct imx_ldb_priv),
+};
diff --git a/drivers/video/lm3532_backlight.c b/drivers/video/lm3532_backlight.c
new file mode 100644
index 0000000..81b3b91
--- /dev/null
+++ b/drivers/video/lm3532_backlight.c
@@ -0,0 +1,380 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * TI LM3532 LED driver
+ *
+ * Copyright (c) 2019 Texas Instruments Incorporated
+ * Copyright (c) 2025 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#define LOG_CATEGORY UCLASS_PANEL_BACKLIGHT
+
+#include <backlight.h>
+#include <dm.h>
+#include <dm/ofnode.h>
+#include <i2c.h>
+#include <log.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <asm/gpio.h>
+#include <power/regulator.h>
+
+#define LM3532_BL_MODE_MANUAL 0x00
+#define LM3532_BL_MODE_ALS 0x01
+
+#define LM3532_REG_OUTPUT_CFG 0x10
+#define LM3532_REG_STARTSHUT_RAMP 0x11
+#define LM3532_REG_RT_RAMP 0x12
+#define LM3532_REG_PWM_A_CFG 0x13
+#define LM3532_REG_PWM_B_CFG 0x14
+#define LM3532_REG_PWM_C_CFG 0x15
+#define LM3532_REG_ZONE_CFG_A 0x16
+#define LM3532_REG_CTRL_A_FS_CURR 0x17
+#define LM3532_REG_ZONE_CFG_B 0x18
+#define LM3532_REG_CTRL_B_FS_CURR 0x19
+#define LM3532_REG_ZONE_CFG_C 0x1a
+#define LM3532_REG_CTRL_C_FS_CURR 0x1b
+#define LM3532_REG_ENABLE 0x1d
+#define LM3532_ALS_CONFIG 0x23
+#define LM3532_REG_ZN_0_HI 0x60
+#define LM3532_REG_ZN_0_LO 0x61
+#define LM3532_REG_ZN_1_HI 0x62
+#define LM3532_REG_ZN_1_LO 0x63
+#define LM3532_REG_ZN_2_HI 0x64
+#define LM3532_REG_ZN_2_LO 0x65
+#define LM3532_REG_ZN_3_HI 0x66
+#define LM3532_REG_ZN_3_LO 0x67
+#define LM3532_REG_ZONE_TRGT_A 0x70
+#define LM3532_REG_ZONE_TRGT_B 0x75
+#define LM3532_REG_ZONE_TRGT_C 0x7a
+#define LM3532_REG_MAX 0x7e
+
+/* Control Enable */
+#define LM3532_CTRL_A_ENABLE BIT(0)
+#define LM3532_CTRL_B_ENABLE BIT(1)
+#define LM3532_CTRL_C_ENABLE BIT(2)
+
+/* PWM Zone Control */
+#define LM3532_PWM_ZONE_MASK 0x7c
+#define LM3532_PWM_ZONE_0_EN BIT(2)
+#define LM3532_PWM_ZONE_1_EN BIT(3)
+#define LM3532_PWM_ZONE_2_EN BIT(4)
+#define LM3532_PWM_ZONE_3_EN BIT(5)
+#define LM3532_PWM_ZONE_4_EN BIT(6)
+
+/* Brightness Configuration */
+#define LM3532_I2C_CTRL BIT(0)
+#define LM3532_ALS_CTRL 0
+#define LM3532_LINEAR_MAP BIT(1)
+#define LM3532_ZONE_MASK (BIT(2) | BIT(3) | BIT(4))
+#define LM3532_ZONE_0 0
+#define LM3532_ZONE_1 BIT(2)
+#define LM3532_ZONE_2 BIT(3)
+#define LM3532_ZONE_3 (BIT(2) | BIT(3))
+#define LM3532_ZONE_4 BIT(4)
+
+#define LM3532_ENABLE_ALS BIT(3)
+#define LM3532_ALS_SEL_SHIFT 6
+
+/* Zone Boundary Register */
+#define LM3532_ALS_WINDOW_mV 2000
+#define LM3532_ALS_ZB_MAX 4
+#define LM3532_ALS_OFFSET_mV 2
+
+#define LM3532_CONTROL_A 0
+#define LM3532_CONTROL_B 1
+#define LM3532_CONTROL_C 2
+#define LM3532_MAX_CONTROL_BANKS 3
+#define LM3532_MAX_LED_STRINGS 3
+
+#define LM3532_OUTPUT_CFG_MASK 0x3
+#define LM3532_BRT_VAL_ADJUST 8
+#define LM3532_RAMP_DOWN_SHIFT 3
+
+#define LM3532_NUM_RAMP_VALS 8
+#define LM3532_NUM_AVG_VALS 8
+#define LM3532_NUM_IMP_VALS 32
+
+#define LM3532_FS_CURR_MIN 5000
+#define LM3532_FS_CURR_MAX 29800
+#define LM3532_FS_CURR_STEP 800
+
+struct lm3532_bank_data {
+ int control_bank;
+ int mode;
+ int ctrl_brt_pointer;
+ int num_leds;
+ int full_scale_current;
+ u32 present:1;
+ u32 led_strings[LM3532_MAX_CONTROL_BANKS];
+};
+
+struct lm3532_backlight_priv {
+ struct gpio_desc enable_gpio;
+ struct udevice *regulator;
+
+ u32 runtime_ramp_up;
+ u32 runtime_ramp_down;
+
+ struct lm3532_bank_data bank[LM3532_MAX_CONTROL_BANKS];
+};
+
+/* This device does not like i2c md so use this instead */
+static void __maybe_unused dump_i2c(struct udevice *dev)
+{
+ int i, c;
+
+ for (i = 0; i < 0x10; i++) {
+ printf("00%02x: %02x", i * 0x10, dm_i2c_reg_read(dev, i * 0x10));
+ for (c = 1; c < 0xf; c++)
+ printf(" %02x", dm_i2c_reg_read(dev, i * 0x10 + c));
+ printf(" %02x\n", dm_i2c_reg_read(dev, i * 0x10 + 0xf));
+ }
+}
+
+static int lm3532_backlight_enable(struct udevice *dev)
+{
+ struct lm3532_backlight_priv *priv = dev_get_priv(dev);
+ int ret, i;
+
+ for (i = 0; i < LM3532_MAX_CONTROL_BANKS; i++) {
+ if (priv->bank[i].present) {
+ u32 ctrl_en_val = BIT(priv->bank[i].control_bank);
+
+ ret = dm_i2c_reg_clrset(dev, LM3532_REG_ENABLE,
+ ctrl_en_val, ctrl_en_val);
+ if (ret) {
+ log_debug("%s: failed to set ctrl: %d\n",
+ __func__, ret);
+ return ret;
+ }
+ }
+ }
+
+ regulator_set_enable_if_allowed(priv->regulator, 1);
+
+ return 0;
+}
+
+static int lm3532_backlight_set_brightness(struct udevice *dev, int percent)
+{
+ struct lm3532_backlight_priv *priv = dev_get_priv(dev);
+ struct lm3532_bank_data *bank;
+ int ret, i;
+
+ for (i = 0; i < LM3532_MAX_CONTROL_BANKS; i++) {
+ if (priv->bank[i].present) {
+ bank = &priv->bank[i];
+ u32 brightness_reg = LM3532_REG_ZONE_TRGT_A +
+ bank->control_bank * 5 +
+ (bank->ctrl_brt_pointer >> 2);
+
+ ret = dm_i2c_reg_write(dev, brightness_reg, percent);
+ if (ret) {
+ log_debug("%s: failed to set brightness: %d\n",
+ __func__, ret);
+ return ret;
+ }
+ }
+ }
+
+ return 0;
+}
+
+static const int ramp_table[LM3532_NUM_RAMP_VALS] = { 8, 1024, 2048, 4096, 8192,
+ 16384, 32768, 65536 };
+static int lm3532_get_ramp_index(int ramp_time)
+{
+ int i;
+
+ if (ramp_time <= ramp_table[0])
+ return 0;
+
+ if (ramp_time > ramp_table[LM3532_NUM_RAMP_VALS - 1])
+ return LM3532_NUM_RAMP_VALS - 1;
+
+ for (i = 1; i < LM3532_NUM_RAMP_VALS; i++) {
+ if (ramp_time == ramp_table[i])
+ return i;
+
+ /* Find an approximate index by looking up the table */
+ if (ramp_time > ramp_table[i - 1] &&
+ ramp_time < ramp_table[i]) {
+ if (ramp_time - ramp_table[i - 1] < ramp_table[i] - ramp_time)
+ return i - 1;
+ else
+ return i;
+ }
+ }
+
+ return 0;
+}
+
+static int lm3532_backlight_of_to_plat(struct udevice *dev)
+{
+ struct lm3532_backlight_priv *priv = dev_get_priv(dev);
+ u32 ramp_time, reg;
+ ofnode child;
+ int ret;
+
+ ret = gpio_request_by_name(dev, "enable-gpios", 0,
+ &priv->enable_gpio, GPIOD_IS_OUT);
+ if (ret) {
+ log_debug("%s: could not decode enable-gpios (%d)\n", __func__, ret);
+ return ret;
+ }
+
+ ret = device_get_supply_regulator(dev, "vin-supply", &priv->regulator);
+ if (ret) {
+ log_debug("%s: vin regulator not defined: %d\n", __func__, ret);
+ if (ret != -ENOENT)
+ return log_ret(ret);
+ }
+
+ ramp_time = dev_read_u32_default(dev, "ramp-up-us", 0);
+ priv->runtime_ramp_up = lm3532_get_ramp_index(ramp_time);
+
+ ramp_time = dev_read_u32_default(dev, "ramp-down-us", 0);
+ priv->runtime_ramp_down = lm3532_get_ramp_index(ramp_time);
+
+ /* Backlight is one of children but has no dedicated driver */
+ ofnode_for_each_subnode(child, dev_ofnode(dev)) {
+ ret = ofnode_read_u32(child, "reg", ®);
+ if (ret || reg > LM3532_CONTROL_C) {
+ log_debug("%s: control bank invalid %d\n", __func__, reg);
+ continue;
+ }
+
+ struct lm3532_bank_data *bank = &priv->bank[reg];
+
+ bank->control_bank = reg;
+ bank->present = 1;
+ bank->mode = ofnode_read_u32_default(child, "ti,led-mode",
+ LM3532_BL_MODE_MANUAL);
+ bank->mode = LM3532_BL_MODE_ALS ? LM3532_ALS_CTRL : LM3532_I2C_CTRL;
+
+ if (ofnode_read_bool(child, "ti,linear-mapping-mode"))
+ bank->mode |= LM3532_LINEAR_MAP;
+
+ bank->num_leds = ofnode_read_size(child, "led-sources");
+ bank->num_leds /= sizeof(u32);
+ if (bank->num_leds > LM3532_MAX_LED_STRINGS) {
+ log_debug("%s: too many LED string defined %d\n",
+ __func__, bank->num_leds);
+ continue;
+ }
+
+ ret = ofnode_read_u32_array(child, "led-sources",
+ bank->led_strings,
+ bank->num_leds);
+ if (ret) {
+ log_debug("%s: led-sources property missing %d\n",
+ __func__, ret);
+ continue;
+ }
+
+ ret = ofnode_read_u32(child, "led-max-microamp",
+ &bank->full_scale_current);
+ if (ret)
+ log_debug("%s: failed getting led-max-microamp %d\n",
+ __func__, ret);
+ else
+ bank->full_scale_current = min(bank->full_scale_current,
+ LM3532_FS_CURR_MAX);
+ }
+
+ return 0;
+}
+
+static int lm3532_backlight_init_registers(struct udevice *dev,
+ struct lm3532_bank_data *bank)
+{
+ struct lm3532_backlight_priv *priv = dev_get_priv(dev);
+ u32 brightness_config_val, runtime_ramp_val;
+ u32 output_cfg_val = 0, output_cfg_shift = 0, output_cfg_mask = 0;
+ int fs_current_reg, fs_current_val;
+ int ret, i;
+
+ if (!bank->present)
+ return 0;
+
+ u32 brightness_config_reg = LM3532_REG_ZONE_CFG_A + bank->control_bank * 2;
+ /*
+ * This could be hard coded to the default value but the control
+ * brightness register may have changed during boot.
+ */
+ ret = dm_i2c_reg_read(dev, brightness_config_reg);
+ if (ret < 0)
+ return ret;
+
+ bank->ctrl_brt_pointer = ret & ~LM3532_ZONE_MASK;
+ brightness_config_val = bank->ctrl_brt_pointer | bank->mode;
+
+ ret = dm_i2c_reg_write(dev, brightness_config_reg, brightness_config_val);
+ if (ret)
+ return ret;
+
+ if (bank->full_scale_current) {
+ fs_current_reg = LM3532_REG_CTRL_A_FS_CURR + bank->control_bank * 2;
+ fs_current_val = (bank->full_scale_current - LM3532_FS_CURR_MIN) /
+ LM3532_FS_CURR_STEP;
+
+ ret = dm_i2c_reg_write(dev, fs_current_reg, fs_current_val);
+ if (ret)
+ return ret;
+ }
+
+ for (i = 0; i < bank->num_leds; i++) {
+ output_cfg_shift = bank->led_strings[i] * 2;
+ output_cfg_val |= (bank->control_bank << output_cfg_shift);
+ output_cfg_mask |= LM3532_OUTPUT_CFG_MASK << output_cfg_shift;
+ }
+
+ ret = dm_i2c_reg_clrset(dev, LM3532_REG_OUTPUT_CFG, output_cfg_mask,
+ output_cfg_val);
+ if (ret)
+ return ret;
+
+ runtime_ramp_val = priv->runtime_ramp_up |
+ (priv->runtime_ramp_down << LM3532_RAMP_DOWN_SHIFT);
+
+ return dm_i2c_reg_write(dev, LM3532_REG_RT_RAMP, runtime_ramp_val);
+}
+
+static int lm3532_backlight_probe(struct udevice *dev)
+{
+ struct lm3532_backlight_priv *priv = dev_get_priv(dev);
+ int ret, i;
+
+ if (device_get_uclass_id(dev->parent) != UCLASS_I2C)
+ return -EPROTONOSUPPORT;
+
+ dm_gpio_set_value(&priv->enable_gpio, 1);
+
+ for (i = 0; i < LM3532_MAX_CONTROL_BANKS; i++) {
+ ret = lm3532_backlight_init_registers(dev, &priv->bank[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct backlight_ops lm3532_backlight_ops = {
+ .enable = lm3532_backlight_enable,
+ .set_brightness = lm3532_backlight_set_brightness,
+};
+
+static const struct udevice_id lm3532_backlight_ids[] = {
+ { .compatible = "ti,lm3532" },
+ { }
+};
+
+U_BOOT_DRIVER(lm3532_backlight) = {
+ .name = "lm3532_backlight",
+ .id = UCLASS_PANEL_BACKLIGHT,
+ .of_match = lm3532_backlight_ids,
+ .of_to_plat = lm3532_backlight_of_to_plat,
+ .probe = lm3532_backlight_probe,
+ .ops = &lm3532_backlight_ops,
+ .priv_auto = sizeof(struct lm3532_backlight_priv),
+};
diff --git a/drivers/video/meson/Kconfig b/drivers/video/meson/Kconfig
index 3c2d72d..fcf486c 100644
--- a/drivers/video/meson/Kconfig
+++ b/drivers/video/meson/Kconfig
@@ -8,5 +8,6 @@
bool "Enable Amlogic Meson video support"
depends on VIDEO
select DISPLAY
+ imply VIDEO_DAMAGE
help
Enable Amlogic Meson Video Processing Unit video support.
diff --git a/drivers/video/mot-panel.c b/drivers/video/mot-panel.c
new file mode 100644
index 0000000..a911495
--- /dev/null
+++ b/drivers/video/mot-panel.c
@@ -0,0 +1,308 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Motorola ATRIX 4G and DROID X2 DSI panel driver
+ * Exact manufacturer and model unknown
+ *
+ * Copyright (c) 2025 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <backlight.h>
+#include <dm.h>
+#include <panel.h>
+#include <log.h>
+#include <misc.h>
+#include <mipi_display.h>
+#include <mipi_dsi.h>
+#include <asm/gpio.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <power/regulator.h>
+
+struct mot_panel_priv {
+ struct udevice *vdd;
+ struct udevice *vddio;
+
+ struct udevice *backlight;
+
+ struct gpio_desc reset_gpio;
+};
+
+#define dsi_generic_write_seq(dsi, cmd, seq...) do { \
+ static const u8 b[] = { cmd, seq }; \
+ int ret; \
+ ret = mipi_dsi_dcs_write_buffer(dsi, b, ARRAY_SIZE(b)); \
+ if (ret < 0) \
+ return ret; \
+ } while (0)
+
+static struct display_timing default_timing = {
+ .pixelclock.typ = 38250000,
+ .hactive.typ = 540,
+ .hfront_porch.typ = 32,
+ .hback_porch.typ = 32,
+ .hsync_len.typ = 16,
+ .vactive.typ = 960,
+ .vfront_porch.typ = 12,
+ .vback_porch.typ = 12,
+ .vsync_len.typ = 8,
+};
+
+static int mot_es2(struct mipi_dsi_device *dsi)
+{
+ int ret;
+
+ dsi_generic_write_seq(dsi, 0x55, 0x01);
+
+ ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
+ if (ret < 0) {
+ log_debug("%s: failed to exit sleep mode: %d\n", __func__, ret);
+ return ret;
+ }
+ mdelay(120);
+
+ dsi_generic_write_seq(dsi, 0xf4, 0x00, 0xbb, 0x46, 0x53, 0x0c, 0x49,
+ 0x74, 0x29, 0x12, 0x15, 0x2f, 0x2f, 0x04);
+ dsi_generic_write_seq(dsi, 0xf8, 0x4b, 0x04, 0x10, 0x1a, 0x2c, 0x2c,
+ 0x2c, 0x2c, 0x14, 0x12);
+
+ dsi_generic_write_seq(dsi, 0xb5, 0x03, 0x7f, 0x00, 0x80, 0xc7, 0x00);
+ dsi_generic_write_seq(dsi, 0xb7, 0x66, 0xf6, 0x46, 0x9f, 0x90, 0x99,
+ 0xff, 0x80, 0x6d, 0x01);
+
+ /* Gamma R */
+ dsi_generic_write_seq(dsi, 0xf9, 0x04);
+ dsi_generic_write_seq(dsi, 0xfa, 0x00, 0x2f, 0x30, 0x12, 0x0e, 0x0c,
+ 0x22, 0x27, 0x31, 0x2e, 0x07, 0x0f);
+ dsi_generic_write_seq(dsi, 0xfb, 0x00, 0x2f, 0x30, 0x12, 0x0e, 0x0c,
+ 0x22, 0x27, 0x31, 0x2e, 0x07, 0x0f);
+
+ /* Gamma G */
+ dsi_generic_write_seq(dsi, 0xf9, 0x02);
+ dsi_generic_write_seq(dsi, 0xfa, 0x00, 0x2f, 0x37, 0x15, 0x15, 0x11,
+ 0x1f, 0x25, 0x2d, 0x2a, 0x05, 0x0f);
+ dsi_generic_write_seq(dsi, 0xfb, 0x00, 0x2f, 0x37, 0x15, 0x15, 0x11,
+ 0x1f, 0x25, 0x2d, 0x2a, 0x05, 0x0f);
+
+ /* Gamma B */
+ dsi_generic_write_seq(dsi, 0xf9, 0x01);
+ dsi_generic_write_seq(dsi, 0xfa, 0x00, 0x2f, 0x3f, 0x16, 0x1f, 0x15,
+ 0x1f, 0x25, 0x2d, 0x2b, 0x06, 0x0b);
+ dsi_generic_write_seq(dsi, 0xfb, 0x00, 0x2f, 0x3f, 0x16, 0x1f, 0x15,
+ 0x1f, 0x25, 0x2d, 0x2b, 0x06, 0x0b);
+
+ /* Gamma W */
+ dsi_generic_write_seq(dsi, 0xf9, 0x20);
+ dsi_generic_write_seq(dsi, 0xfa, 0x00, 0x2f, 0x34, 0x15, 0x1a, 0x11,
+ 0x1f, 0x23, 0x2d, 0x29, 0x02, 0x08);
+ dsi_generic_write_seq(dsi, 0xfb, 0x00, 0x2f, 0x34, 0x15, 0x1a, 0x11,
+ 0x1f, 0x23, 0x2d, 0x29, 0x02, 0x08);
+
+ dsi_generic_write_seq(dsi, 0x53, 0x2c);
+ dsi_generic_write_seq(dsi, 0x35, 0x00);
+
+ return 0;
+}
+
+static int __maybe_unused mot_es4(struct mipi_dsi_device *dsi)
+{
+ int ret;
+
+ dsi_generic_write_seq(dsi, 0xd2, 0x04, 0x53);
+ dsi_generic_write_seq(dsi, 0xd2, 0x05, 0x53);
+ dsi_generic_write_seq(dsi, 0x55, 0x01);
+
+ ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
+ if (ret < 0) {
+ log_debug("%s: failed to exit sleep mode: %d\n", __func__, ret);
+ return ret;
+ }
+ mdelay(120);
+
+ dsi_generic_write_seq(dsi, 0xb5, 0x03, 0x7f, 0x0a, 0x80, 0xff, 0x00);
+ dsi_generic_write_seq(dsi, 0xb7, 0x7a, 0xf7, 0x4d, 0x91, 0x90, 0xb3,
+ 0xff, 0x80, 0x6d, 0x01);
+ dsi_generic_write_seq(dsi, 0xf4, 0x00, 0xbb, 0x46, 0x53, 0x0c, 0x49,
+ 0x74, 0x29, 0x12, 0x15, 0x37, 0x37, 0x04);
+ dsi_generic_write_seq(dsi, 0xf8, 0x0a, 0x04, 0x10, 0x2a, 0x35, 0x35,
+ 0x35, 0x35, 0x21, 0x1a);
+
+ /* Gamma R */
+ dsi_generic_write_seq(dsi, 0xf9, 0x04);
+ dsi_generic_write_seq(dsi, 0xfa, 0x08, 0x1c, 0x1b, 0x0f, 0x0f, 0x0a,
+ 0x1e, 0x22, 0x27, 0x26, 0x07, 0x0d);
+ dsi_generic_write_seq(dsi, 0xfb, 0x08, 0x3c, 0x27, 0x0f, 0x0f, 0x0a,
+ 0x1e, 0x26, 0x31, 0x2f, 0x07, 0x0b);
+
+ /* Gamma G */
+ dsi_generic_write_seq(dsi, 0xf9, 0x02);
+ dsi_generic_write_seq(dsi, 0xfa, 0x30, 0x14, 0x0f, 0x00, 0x06, 0x02,
+ 0x1e, 0x22, 0x27, 0x27, 0x08, 0x10);
+ dsi_generic_write_seq(dsi, 0xfb, 0x30, 0x35, 0x0f, 0x00, 0x0a, 0x02,
+ 0x1c, 0x23, 0x31, 0x2f, 0x08, 0x0e);
+
+ /* Gamma B */
+ dsi_generic_write_seq(dsi, 0xf9, 0x01);
+ dsi_generic_write_seq(dsi, 0xfa, 0x12, 0x1b, 0x26, 0x0e, 0x12, 0x0b,
+ 0x1e, 0x22, 0x27, 0x27, 0x06, 0x0c);
+ dsi_generic_write_seq(dsi, 0xfb, 0x12, 0x3b, 0x2c, 0x12, 0x12, 0x0e,
+ 0x1e, 0x26, 0x31, 0x2f, 0x06, 0x0d);
+
+ /* Gamma W */
+ dsi_generic_write_seq(dsi, 0xf9, 0x20);
+ dsi_generic_write_seq(dsi, 0xfa, 0x37, 0x1b, 0x09, 0x01, 0x06, 0x04,
+ 0x19, 0x19, 0x22, 0x24, 0x04, 0x15);
+ dsi_generic_write_seq(dsi, 0xfb, 0x37, 0x3b, 0x17, 0x01, 0x0a, 0x04,
+ 0x19, 0x1d, 0x2c, 0x2c, 0x04, 0x13);
+
+ dsi_generic_write_seq(dsi, 0x53, 0x2c);
+ dsi_generic_write_seq(dsi, 0x35, 0x00);
+ dsi_generic_write_seq(dsi, 0xc3, 0x01, 0x4e);
+
+ return 0;
+}
+
+static int mot_panel_enable_backlight(struct udevice *dev)
+{
+ struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+ struct mipi_dsi_device *dsi = plat->device;
+ int ret;
+
+ dsi_generic_write_seq(dsi, 0xf0, 0x5a, 0x5a);
+ dsi_generic_write_seq(dsi, 0xf1, 0x5a, 0x5a);
+ dsi_generic_write_seq(dsi, 0xd0, 0x8e);
+
+ ret = mot_es2(dsi);
+ if (ret)
+ return ret;
+
+ ret = mipi_dsi_dcs_set_display_on(dsi);
+ if (ret < 0) {
+ log_debug("%s: failed to set display on: %d\n", __func__, ret);
+ return ret;
+ }
+ mdelay(20);
+
+ return 0;
+}
+
+static int mot_panel_set_backlight(struct udevice *dev, int percent)
+{
+ struct mot_panel_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = backlight_enable(priv->backlight);
+ if (ret)
+ return ret;
+
+ mdelay(5);
+
+ return backlight_set_brightness(priv->backlight, percent);
+}
+
+static int mot_panel_timings(struct udevice *dev, struct display_timing *timing)
+{
+ memcpy(timing, &default_timing, sizeof(*timing));
+ return 0;
+}
+
+static int mot_panel_of_to_plat(struct udevice *dev)
+{
+ struct mot_panel_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
+ "backlight", &priv->backlight);
+ if (ret) {
+ log_debug("%s: cannot get backlight: ret = %d\n", __func__, ret);
+ return ret;
+ }
+
+ ret = device_get_supply_regulator(dev, "vdd-supply", &priv->vdd);
+ if (ret) {
+ log_debug("%s: cannot get vdd-supply: ret = %d\n", __func__, ret);
+ return ret;
+ }
+
+ ret = device_get_supply_regulator(dev, "vddio-supply", &priv->vddio);
+ if (ret) {
+ log_debug("%s: cannot get vddio-supply: ret = %d\n", __func__, ret);
+ return ret;
+ }
+
+ ret = gpio_request_by_name(dev, "reset-gpios", 0,
+ &priv->reset_gpio, GPIOD_IS_OUT);
+ if (ret) {
+ log_debug("%s: could not decode reser-gpios (%d)\n", __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int mot_panel_hw_init(struct udevice *dev)
+{
+ struct mot_panel_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = regulator_set_enable_if_allowed(priv->vddio, 1);
+ if (ret) {
+ log_debug("%s: enabling vddio-supply failed (%d)\n", __func__, ret);
+ return ret;
+ }
+
+ ret = regulator_set_enable_if_allowed(priv->vdd, 1);
+ if (ret) {
+ log_debug("%s: enabling vdd-supply failed (%d)\n", __func__, ret);
+ return ret;
+ }
+
+ ret = dm_gpio_set_value(&priv->reset_gpio, 1);
+ if (ret) {
+ log_debug("%s: error entering reset (%d)\n", __func__, ret);
+ return ret;
+ }
+ mdelay(50);
+
+ ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+ if (ret) {
+ log_debug("%s: error exiting reset (%d)\n", __func__, ret);
+ return ret;
+ }
+ mdelay(10);
+
+ return 0;
+}
+
+static int mot_panel_probe(struct udevice *dev)
+{
+ struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+
+ /* fill characteristics of DSI data link */
+ plat->lanes = 2;
+ plat->format = MIPI_DSI_FMT_RGB888;
+ plat->mode_flags = MIPI_DSI_MODE_LPM;
+
+ return mot_panel_hw_init(dev);
+}
+
+static const struct panel_ops mot_panel_ops = {
+ .enable_backlight = mot_panel_enable_backlight,
+ .set_backlight = mot_panel_set_backlight,
+ .get_display_timing = mot_panel_timings,
+};
+
+static const struct udevice_id mot_panel_ids[] = {
+ { .compatible = "motorola,mot-panel" },
+ { }
+};
+
+U_BOOT_DRIVER(mot_panel) = {
+ .name = "mot_panel",
+ .id = UCLASS_PANEL,
+ .of_match = mot_panel_ids,
+ .ops = &mot_panel_ops,
+ .of_to_plat = mot_panel_of_to_plat,
+ .probe = mot_panel_probe,
+ .plat_auto = sizeof(struct mipi_dsi_panel_plat),
+ .priv_auto = sizeof(struct mot_panel_priv),
+};
diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig
index 01804dc..0f4550a 100644
--- a/drivers/video/rockchip/Kconfig
+++ b/drivers/video/rockchip/Kconfig
@@ -11,6 +11,7 @@
menuconfig VIDEO_ROCKCHIP
bool "Enable Rockchip Video Support"
depends on VIDEO
+ imply VIDEO_DAMAGE
help
Rockchip SoCs provide video output capabilities for High-Definition
Multimedia Interface (HDMI), Low-voltage Differential Signalling
diff --git a/drivers/video/stm32/Kconfig b/drivers/video/stm32/Kconfig
index 4806606..c354c40 100644
--- a/drivers/video/stm32/Kconfig
+++ b/drivers/video/stm32/Kconfig
@@ -8,6 +8,7 @@
menuconfig VIDEO_STM32
bool "Enable STM32 video support"
depends on VIDEO
+ imply VIDEO_DAMAGE
help
STM32 supports many video output options including RGB and
DSI. This option enables these supports which can be used on
diff --git a/drivers/video/tegra/Kconfig b/drivers/video/tegra/Kconfig
new file mode 100644
index 0000000..1a328407
--- /dev/null
+++ b/drivers/video/tegra/Kconfig
@@ -0,0 +1,52 @@
+config HOST1X_TEGRA
+ bool "NVIDIA Tegra host1x BUS support"
+ depends on SIMPLE_BUS
+
+config VIDEO_TEGRA
+ bool "Enable Display Controller support on Tegra devices"
+ depends on OF_CONTROL
+ select HOST1X_TEGRA
+ help
+ Enable support for Display Controller found in Tegra SoC. The
+ Display Controller Complex integrates two independent display
+ controllers. Each display controller is capable of interfacing
+ to an external display device, which can be a parallel interface
+ or SPI LCD, DVI, an HDMI HDTV, RGB monitor or a MIPI DSI LCD.
+ Direct interface is supported directly to most LCD displays with
+ TFT or TFT-like interface.
+
+config VIDEO_DSI_TEGRA
+ bool "Enable DSI controller support on Tegra devices"
+ depends on VIDEO_BRIDGE && PANEL && DM_GPIO
+ select VIDEO_TEGRA
+ select VIDEO_MIPI_DSI
+ help
+ Enable support for the Display Serial Interface (DSI) found in
+ Tegra SoC. It is a MIPI standard serial bitstream, intended to
+ provide a low pin count interface to a display panel.
+
+config VIDEO_HDMI_TEGRA
+ bool "Enable HDMI support on Tegra devices"
+ depends on VIDEO_BRIDGE && DM_I2C
+ select I2C_EDID
+ select VIDEO_TEGRA
+ help
+ Enable support for the High-Definition Multimedia Interface (HDMI)
+ found in Tegra SoC.
+
+config TEGRA_BACKLIGHT_PWM
+ bool "Enable Tegra DC PWM backlight support"
+ depends on BACKLIGHT
+ select VIDEO_TEGRA
+ help
+ Enable support for the Display Controller dependent PWM backlight
+ found in the Tegra SoC and usually used with DSI panels.
+
+config VIDEO_TEGRA124
+ bool "Enable video support on Tegra124"
+ imply VIDEO_DAMAGE
+ help
+ Tegra124 supports many video output options including eDP and
+ HDMI. At present only eDP is supported by U-Boot. This option
+ enables this support which can be used on devices which
+ have an eDP display connected.
diff --git a/drivers/video/tegra/Makefile b/drivers/video/tegra/Makefile
new file mode 100644
index 0000000..3c50a0b
--- /dev/null
+++ b/drivers/video/tegra/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_HOST1X_TEGRA) += host1x.o
+obj-$(CONFIG_VIDEO_TEGRA) += dc.o
+obj-$(CONFIG_VIDEO_DSI_TEGRA) += dsi.o mipi.o mipi-phy.o
+obj-$(CONFIG_VIDEO_HDMI_TEGRA) += hdmi.o
+obj-$(CONFIG_TEGRA_BACKLIGHT_PWM) += dc-pwm-backlight.o
+
+obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
diff --git a/drivers/video/tegra/TODO b/drivers/video/tegra/TODO
new file mode 100644
index 0000000..1c8c238
--- /dev/null
+++ b/drivers/video/tegra/TODO
@@ -0,0 +1,5 @@
+Existence of separate Tegra124 video implementations is not an ideal solution
+since generic video setup for Tegra already has Tegra124 support of some degree.
+It is not possible at the time of this note is written to integrate T124 SOR
+and DP without possible regressions. Tegra124 setup for SOR and DP should be
+incorporated into existing setup once such opportunity occurs.
diff --git a/drivers/video/tegra20/tegra-pwm-backlight.c b/drivers/video/tegra/dc-pwm-backlight.c
similarity index 99%
rename from drivers/video/tegra20/tegra-pwm-backlight.c
rename to drivers/video/tegra/dc-pwm-backlight.c
index 998f0df..eff10b5 100644
--- a/drivers/video/tegra20/tegra-pwm-backlight.c
+++ b/drivers/video/tegra/dc-pwm-backlight.c
@@ -15,7 +15,7 @@
#include <asm/io.h>
#include <asm/gpio.h>
-#include "tegra-dc.h"
+#include "dc.h"
#define TEGRA_PWM_BL_MIN_BRIGHTNESS 0x10
#define TEGRA_PWM_BL_MAX_BRIGHTNESS 0xFF
diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra/dc.c
similarity index 99%
rename from drivers/video/tegra20/tegra-dc.c
rename to drivers/video/tegra/dc.c
index 1f43153..f0e3d2c 100644
--- a/drivers/video/tegra20/tegra-dc.c
+++ b/drivers/video/tegra/dc.c
@@ -19,7 +19,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/powergate.h>
-#include "tegra-dc.h"
+#include "dc.h"
/* Holder of Tegra per-SOC DC differences */
struct tegra_dc_soc_info {
diff --git a/drivers/video/tegra20/tegra-dc.h b/drivers/video/tegra/dc.h
similarity index 100%
rename from drivers/video/tegra20/tegra-dc.h
rename to drivers/video/tegra/dc.h
diff --git a/drivers/video/tegra20/tegra-dsi.c b/drivers/video/tegra/dsi.c
similarity index 99%
rename from drivers/video/tegra20/tegra-dsi.c
rename to drivers/video/tegra/dsi.c
index a2a22fa..bc30886 100644
--- a/drivers/video/tegra20/tegra-dsi.c
+++ b/drivers/video/tegra/dsi.c
@@ -24,8 +24,8 @@
#include <asm/arch/clock.h>
#include <asm/arch-tegra/clk_rst.h>
-#include "tegra-dc.h"
-#include "tegra-dsi.h"
+#include "dc.h"
+#include "dsi.h"
#include "mipi-phy.h"
/* List of supported DSI bridges */
@@ -1129,6 +1129,7 @@
};
static const struct udevice_id tegra_dsi_bridge_ids[] = {
+ { .compatible = "nvidia,tegra20-dsi", .data = DSI_V0 },
{ .compatible = "nvidia,tegra30-dsi", .data = DSI_V0 },
{ .compatible = "nvidia,tegra114-dsi", .data = DSI_V1 },
{ .compatible = "nvidia,tegra124-dsi", .data = DSI_V1 },
diff --git a/drivers/video/tegra20/tegra-dsi.h b/drivers/video/tegra/dsi.h
similarity index 100%
rename from drivers/video/tegra20/tegra-dsi.h
rename to drivers/video/tegra/dsi.h
diff --git a/drivers/video/tegra20/tegra-hdmi.c b/drivers/video/tegra/hdmi.c
similarity index 99%
rename from drivers/video/tegra20/tegra-hdmi.c
rename to drivers/video/tegra/hdmi.c
index bda6991..bfb48b2 100644
--- a/drivers/video/tegra20/tegra-hdmi.c
+++ b/drivers/video/tegra/hdmi.c
@@ -22,8 +22,8 @@
#include <asm/io.h>
#include <asm/arch/clock.h>
-#include "tegra-dc.h"
-#include "tegra-hdmi.h"
+#include "dc.h"
+#include "hdmi.h"
#define DDCCI_ENTRY_ADDR 0x37
#define DDCCI_SOURSE_ADDR 0x51
diff --git a/drivers/video/tegra20/tegra-hdmi.h b/drivers/video/tegra/hdmi.h
similarity index 100%
rename from drivers/video/tegra20/tegra-hdmi.h
rename to drivers/video/tegra/hdmi.h
diff --git a/drivers/video/tegra20/tegra-host1x.c b/drivers/video/tegra/host1x.c
similarity index 100%
rename from drivers/video/tegra20/tegra-host1x.c
rename to drivers/video/tegra/host1x.c
diff --git a/drivers/video/tegra20/mipi-phy.c b/drivers/video/tegra/mipi-phy.c
similarity index 100%
rename from drivers/video/tegra20/mipi-phy.c
rename to drivers/video/tegra/mipi-phy.c
diff --git a/drivers/video/tegra20/mipi-phy.h b/drivers/video/tegra/mipi-phy.h
similarity index 100%
rename from drivers/video/tegra20/mipi-phy.h
rename to drivers/video/tegra/mipi-phy.h
diff --git a/drivers/video/tegra20/tegra-mipi.c b/drivers/video/tegra/mipi.c
similarity index 100%
rename from drivers/video/tegra20/tegra-mipi.c
rename to drivers/video/tegra/mipi.c
diff --git a/drivers/video/tegra124/Makefile b/drivers/video/tegra/tegra124/Makefile
similarity index 100%
rename from drivers/video/tegra124/Makefile
rename to drivers/video/tegra/tegra124/Makefile
diff --git a/drivers/video/tegra124/display.c b/drivers/video/tegra/tegra124/display.c
similarity index 100%
rename from drivers/video/tegra124/display.c
rename to drivers/video/tegra/tegra124/display.c
diff --git a/drivers/video/tegra124/displayport.h b/drivers/video/tegra/tegra124/displayport.h
similarity index 100%
rename from drivers/video/tegra124/displayport.h
rename to drivers/video/tegra/tegra124/displayport.h
diff --git a/drivers/video/tegra124/dp.c b/drivers/video/tegra/tegra124/dp.c
similarity index 100%
rename from drivers/video/tegra124/dp.c
rename to drivers/video/tegra/tegra124/dp.c
diff --git a/drivers/video/tegra124/sor.c b/drivers/video/tegra/tegra124/sor.c
similarity index 100%
rename from drivers/video/tegra124/sor.c
rename to drivers/video/tegra/tegra124/sor.c
diff --git a/drivers/video/tegra124/sor.h b/drivers/video/tegra/tegra124/sor.h
similarity index 100%
rename from drivers/video/tegra124/sor.h
rename to drivers/video/tegra/tegra124/sor.h
diff --git a/drivers/video/tegra20/Kconfig b/drivers/video/tegra20/Kconfig
deleted file mode 100644
index 598f9ea..0000000
--- a/drivers/video/tegra20/Kconfig
+++ /dev/null
@@ -1,38 +0,0 @@
-config HOST1X_TEGRA
- bool "NVIDIA Tegra host1x BUS support"
- depends on SIMPLE_BUS
-
-config VIDEO_TEGRA20
- bool "Enable Display Controller support on Tegra20 and Tegra 30"
- depends on OF_CONTROL
- select HOST1X_TEGRA
- help
- T20/T30 support video output to an attached LCD panel as well as
- other options such as HDMI. Only the LCD is supported in U-Boot.
- This option enables this support which can be used on devices which
- have an LCD display connected.
-
-config VIDEO_DSI_TEGRA30
- bool "Enable Tegra 30 DSI support"
- depends on VIDEO_BRIDGE && PANEL && DM_GPIO
- select VIDEO_TEGRA20
- select VIDEO_MIPI_DSI
- help
- T30 has native support for DSI panels. This option enables support
- for such panels which can be used on endeavoru and tf600t.
-
-config VIDEO_HDMI_TEGRA
- bool "Enable Tegra HDMI support"
- depends on VIDEO_BRIDGE && DM_I2C
- select I2C_EDID
- select VIDEO_TEGRA20
- help
- Tegra has native support for HDMI. This option enables support
- for such connection and can be used for any supported device.
-
-config TEGRA_BACKLIGHT_PWM
- bool "Enable Tegra DC PWM backlight support"
- depends on BACKLIGHT
- select VIDEO_TEGRA20
- help
- Tegra DC dependent backlight.
diff --git a/drivers/video/tegra20/Makefile b/drivers/video/tegra20/Makefile
deleted file mode 100644
index 7852140..0000000
--- a/drivers/video/tegra20/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-$(CONFIG_HOST1X_TEGRA) += tegra-host1x.o
-obj-$(CONFIG_VIDEO_TEGRA20) += tegra-dc.o
-obj-$(CONFIG_VIDEO_DSI_TEGRA30) += tegra-dsi.o tegra-mipi.o mipi-phy.o
-obj-$(CONFIG_VIDEO_HDMI_TEGRA) += tegra-hdmi.o
-obj-$(CONFIG_TEGRA_BACKLIGHT_PWM) += tegra-pwm-backlight.o
diff --git a/drivers/video/tidss/Kconfig b/drivers/video/tidss/Kconfig
index 95086f3..3291b3c 100644
--- a/drivers/video/tidss/Kconfig
+++ b/drivers/video/tidss/Kconfig
@@ -11,6 +11,7 @@
menuconfig VIDEO_TIDSS
bool "Enable TIDSS video support"
depends on VIDEO
+ imply VIDEO_DAMAGE
help
TIDSS supports video output options LVDS and
DPI . This option enables these supports which can be used on
diff --git a/drivers/video/tidss/Makefile b/drivers/video/tidss/Makefile
index f0cbe1d..3381a5f 100644
--- a/drivers/video/tidss/Makefile
+++ b/drivers/video/tidss/Makefile
@@ -9,4 +9,4 @@
# Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
-obj-${CONFIG_$(XPL_)VIDEO_TIDSS} = tidss_drv.o
+obj-${CONFIG_$(PHASE_)VIDEO_TIDSS} = tidss_drv.o
diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c
index ebe96bf..a1dfd35 100644
--- a/drivers/video/vidconsole-uclass.c
+++ b/drivers/video/vidconsole-uclass.c
@@ -761,22 +761,6 @@
.per_device_auto = sizeof(struct vidconsole_priv),
};
-#ifdef CONFIG_VIDEO_COPY
-int vidconsole_sync_copy(struct udevice *dev, void *from, void *to)
-{
- struct udevice *vid = dev_get_parent(dev);
-
- return video_sync_copy(vid, from, to);
-}
-
-int vidconsole_memmove(struct udevice *dev, void *dst, const void *src,
- int size)
-{
- memmove(dst, src, size);
- return vidconsole_sync_copy(dev, dst, dst + size);
-}
-#endif
-
int vidconsole_clear_and_reset(struct udevice *dev)
{
int ret;
diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c
index c684c99..503cdb9 100644
--- a/drivers/video/video-uclass.c
+++ b/drivers/video/video-uclass.c
@@ -171,7 +171,7 @@
struct video_priv *priv = dev_get_uclass_priv(dev);
void *start, *line;
int pixels = xend - xstart;
- int row, i, ret;
+ int row, i;
start = priv->fb + ystart * priv->line_length;
start += xstart * VNBYTES(priv->bpix);
@@ -210,9 +210,8 @@
}
line += priv->line_length;
}
- ret = video_sync_copy(dev, start, line);
- if (ret)
- return ret;
+
+ video_damage(dev, xstart, ystart, xend - xstart, yend - ystart);
return 0;
}
@@ -233,7 +232,6 @@
int video_fill(struct udevice *dev, u32 colour)
{
struct video_priv *priv = dev_get_uclass_priv(dev);
- int ret;
switch (priv->bpix) {
case VIDEO_BPP16:
@@ -260,9 +258,8 @@
memset(priv->fb, colour, priv->fb_size);
break;
}
- ret = video_sync_copy(dev, priv->fb, priv->fb + priv->fb_size);
- if (ret)
- return ret;
+
+ video_damage(dev, 0, 0, priv->xsize, priv->ysize);
return video_sync(dev, false);
}
@@ -369,6 +366,95 @@
priv->colour_bg = video_index_to_colour(priv, back);
}
+/* Notify about changes in the frame buffer */
+#ifdef CONFIG_VIDEO_DAMAGE
+void video_damage(struct udevice *vid, int x, int y, int width, int height)
+{
+ struct video_priv *priv = dev_get_uclass_priv(vid);
+ int xend = x + width;
+ int yend = y + height;
+
+ if (x > priv->xsize)
+ return;
+
+ if (y > priv->ysize)
+ return;
+
+ if (xend > priv->xsize)
+ xend = priv->xsize;
+
+ if (yend > priv->ysize)
+ yend = priv->ysize;
+
+ /* Span a rectangle across all old and new damage */
+ priv->damage.xstart = min(x, priv->damage.xstart);
+ priv->damage.ystart = min(y, priv->damage.ystart);
+ priv->damage.xend = max(xend, priv->damage.xend);
+ priv->damage.yend = max(yend, priv->damage.yend);
+}
+#endif
+
+static void video_flush_dcache(struct udevice *vid, bool use_copy)
+{
+ struct video_priv *priv = dev_get_uclass_priv(vid);
+ ulong fb = use_copy ? (ulong)priv->copy_fb : (ulong)priv->fb;
+ uint cacheline_size = 32;
+
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+ cacheline_size = CONFIG_SYS_CACHELINE_SIZE;
+#endif
+
+ if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ return;
+
+ if (!priv->flush_dcache)
+ return;
+
+ if (!IS_ENABLED(CONFIG_VIDEO_DAMAGE)) {
+ flush_dcache_range(fb, ALIGN(fb + priv->fb_size,
+ cacheline_size));
+
+ return;
+ }
+
+ if (priv->damage.xend && priv->damage.yend) {
+ int lstart = priv->damage.xstart * VNBYTES(priv->bpix);
+ int lend = priv->damage.xend * VNBYTES(priv->bpix);
+ int y;
+
+ for (y = priv->damage.ystart; y < priv->damage.yend; y++) {
+ ulong start = fb + (y * priv->line_length) + lstart;
+ ulong end = start + lend - lstart;
+
+ start = ALIGN_DOWN(start, cacheline_size);
+ end = ALIGN(end, cacheline_size);
+
+ flush_dcache_range(start, end);
+ }
+ }
+}
+
+static void video_flush_copy(struct udevice *vid)
+{
+ struct video_priv *priv = dev_get_uclass_priv(vid);
+
+ if (!priv->copy_fb)
+ return;
+
+ if (priv->damage.xend && priv->damage.yend) {
+ int lstart = priv->damage.xstart * VNBYTES(priv->bpix);
+ int lend = priv->damage.xend * VNBYTES(priv->bpix);
+ int y;
+
+ for (y = priv->damage.ystart; y < priv->damage.yend; y++) {
+ ulong offset = (y * priv->line_length) + lstart;
+ ulong len = lend - lstart;
+
+ memcpy(priv->copy_fb + offset, priv->fb + offset, len);
+ }
+ }
+}
+
/* Flush video activity to the caches */
int video_sync(struct udevice *vid, bool force)
{
@@ -376,6 +462,9 @@
struct video_ops *ops = video_get_ops(vid);
int ret;
+ if (IS_ENABLED(CONFIG_VIDEO_COPY))
+ video_flush_copy(vid);
+
if (ops && ops->video_sync) {
ret = ops->video_sync(vid);
if (ret)
@@ -386,22 +475,23 @@
get_timer(priv->last_sync) < CONFIG_VIDEO_SYNC_MS)
return 0;
- /*
- * flush_dcache_range() is declared in common.h but it seems that some
- * architectures do not actually implement it. Is there a way to find
- * out whether it exists? For now, ARM is safe.
- */
-#if defined(CONFIG_ARM) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
- if (priv->flush_dcache) {
- flush_dcache_range((ulong)priv->fb,
- ALIGN((ulong)priv->fb + priv->fb_size,
- CONFIG_SYS_CACHELINE_SIZE));
- }
-#elif defined(CONFIG_VIDEO_SANDBOX_SDL)
+ video_flush_dcache(vid, false);
+
+ if (IS_ENABLED(CONFIG_VIDEO_COPY))
+ video_flush_dcache(vid, true);
+
+#if defined(CONFIG_VIDEO_SANDBOX_SDL)
sandbox_sdl_sync(priv->fb);
#endif
priv->last_sync = get_timer(0);
+ if (IS_ENABLED(CONFIG_VIDEO_DAMAGE)) {
+ priv->damage.xstart = priv->xsize;
+ priv->damage.ystart = priv->ysize;
+ priv->damage.xend = 0;
+ priv->damage.yend = 0;
+ }
+
return 0;
}
@@ -453,69 +543,6 @@
return priv->ysize;
}
-#ifdef CONFIG_VIDEO_COPY
-int video_sync_copy(struct udevice *dev, void *from, void *to)
-{
- struct video_priv *priv = dev_get_uclass_priv(dev);
-
- if (priv->copy_fb) {
- long offset, size;
-
- /* Find the offset of the first byte to copy */
- if ((ulong)to > (ulong)from) {
- size = to - from;
- offset = from - priv->fb;
- } else {
- size = from - to;
- offset = to - priv->fb;
- }
-
- /*
- * Allow a bit of leeway for valid requests somewhere near the
- * frame buffer
- */
- if (offset < -priv->fb_size || offset > 2 * priv->fb_size) {
-#ifdef DEBUG
- char str[120];
-
- snprintf(str, sizeof(str),
- "[** FAULT sync_copy fb=%p, from=%p, to=%p, offset=%lx]",
- priv->fb, from, to, offset);
- console_puts_select_stderr(true, str);
-#endif
- return -EFAULT;
- }
-
- /*
- * Silently crop the memcpy. This allows callers to avoid doing
- * this themselves. It is common for the end pointer to go a
- * few lines after the end of the frame buffer, since most of
- * the update algorithms terminate a line after their last write
- */
- if (offset + size > priv->fb_size) {
- size = priv->fb_size - offset;
- } else if (offset < 0) {
- size += offset;
- offset = 0;
- }
-
- memcpy(priv->copy_fb + offset, priv->fb + offset, size);
- }
-
- return 0;
-}
-
-int video_sync_copy_all(struct udevice *dev)
-{
- struct video_priv *priv = dev_get_uclass_priv(dev);
-
- video_sync_copy(dev, priv->fb, priv->fb + priv->fb_size);
-
- return 0;
-}
-
-#endif
-
#define SPLASH_DECL(_name) \
extern u8 __splash_ ## _name ## _begin[]; \
extern u8 __splash_ ## _name ## _end[]
diff --git a/drivers/video/video_bmp.c b/drivers/video/video_bmp.c
index ad512d9..1f267d4 100644
--- a/drivers/video/video_bmp.c
+++ b/drivers/video/video_bmp.c
@@ -267,7 +267,6 @@
enum video_format eformat;
struct bmp_color_table_entry *palette;
int hdr_size;
- int ret;
if (!bmp || !(bmp->header.signature[0] == 'B' &&
bmp->header.signature[1] == 'M')) {
@@ -459,11 +458,7 @@
break;
};
- /* Find the position of the top left of the image in the framebuffer */
- fb = (uchar *)(priv->fb + y * priv->line_length + x * bpix / 8);
- ret = video_sync_copy(dev, start, fb);
- if (ret)
- return log_ret(ret);
+ video_damage(dev, x, y, width, height);
return video_sync(dev, false);
}
diff --git a/drivers/watchdog/sunxi_wdt.c b/drivers/watchdog/sunxi_wdt.c
index 8eeac93..467db5f 100644
--- a/drivers/watchdog/sunxi_wdt.c
+++ b/drivers/watchdog/sunxi_wdt.c
@@ -153,10 +153,21 @@
.wdt_key_val = 0x16aa0000,
};
+static const struct sunxi_wdt_reg sun55i_wdt_reg = {
+ .wdt_ctrl = 0x0c,
+ .wdt_cfg = 0x10,
+ .wdt_mode = 0x14,
+ .wdt_timeout_shift = 4,
+ .wdt_reset_mask = 0x03,
+ .wdt_reset_val = 0x01,
+ .wdt_key_val = 0x16aa0000,
+};
+
static const struct udevice_id sunxi_wdt_ids[] = {
{ .compatible = "allwinner,sun4i-a10-wdt", .data = (ulong)&sun4i_wdt_reg },
{ .compatible = "allwinner,sun6i-a31-wdt", .data = (ulong)&sun6i_wdt_reg },
{ .compatible = "allwinner,sun20i-d1-wdt", .data = (ulong)&sun20i_wdt_reg },
+ { .compatible = "allwinner,sun55i-a523-wdt", .data = (ulong)&sun55i_wdt_reg },
{ /* sentinel */ }
};
diff --git a/dts/upstream/Bindings/arm/rockchip.yaml b/dts/upstream/Bindings/arm/rockchip.yaml
index 522a6f0..0f4ca08 100644
--- a/dts/upstream/Bindings/arm/rockchip.yaml
+++ b/dts/upstream/Bindings/arm/rockchip.yaml
@@ -236,6 +236,11 @@
- firefly,roc-rk3399-pc-plus
- const: rockchip,rk3399
+ - description: Firefly ROC-RK3576-PC
+ items:
+ - const: firefly,roc-rk3576-pc
+ - const: rockchip,rk3576
+
- description: Firefly Station M2
items:
- const: firefly,rk3566-roc-pc
diff --git a/dts/upstream/Bindings/clock/rockchip,rk3528-cru.yaml b/dts/upstream/Bindings/clock/rockchip,rk3528-cru.yaml
new file mode 100644
index 0000000..5a3ec90
--- /dev/null
+++ b/dts/upstream/Bindings/clock/rockchip,rk3528-cru.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3528-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RK3528 Clock and Reset Controller
+
+maintainers:
+ - Yao Zi <ziyao@disroot.org>
+
+description: |
+ The RK3528 clock controller generates the clock and also implements a reset
+ controller for SoC peripherals. For example, it provides SCLK_UART0 and
+ PCLK_UART0 as well as SRST_P_UART0 and SRST_S_UART0 for the first UART
+ module.
+ Each clock is assigned an identifier, consumer nodes can use it to specify
+ the clock. All available clock and reset IDs are defined in dt-binding
+ headers.
+
+properties:
+ compatible:
+ const: rockchip,rk3528-cru
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: External 24MHz oscillator clock
+ - description: >
+ 50MHz clock generated by PHY module, for generating GMAC0 clocks only.
+
+ clock-names:
+ items:
+ - const: xin24m
+ - const: gmac0
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@ff4a0000 {
+ compatible = "rockchip,rk3528-cru";
+ reg = <0xff4a0000 0x30000>;
+ clocks = <&xin24m>, <&gmac0_clk>;
+ clock-names = "xin24m", "gmac0";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/dts/upstream/include/dt-bindings/clock/rockchip,rk3528-cru.h b/dts/upstream/include/dt-bindings/clock/rockchip,rk3528-cru.h
new file mode 100644
index 0000000..55a448f
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/rockchip,rk3528-cru.h
@@ -0,0 +1,453 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
+ * Author: Joseph Chen <chenjh@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
+
+/* cru-clocks indices */
+#define PLL_APLL 0
+#define PLL_CPLL 1
+#define PLL_GPLL 2
+#define PLL_PPLL 3
+#define PLL_DPLL 4
+#define ARMCLK 5
+#define XIN_OSC0_HALF 6
+#define CLK_MATRIX_50M_SRC 7
+#define CLK_MATRIX_100M_SRC 8
+#define CLK_MATRIX_150M_SRC 9
+#define CLK_MATRIX_200M_SRC 10
+#define CLK_MATRIX_250M_SRC 11
+#define CLK_MATRIX_300M_SRC 12
+#define CLK_MATRIX_339M_SRC 13
+#define CLK_MATRIX_400M_SRC 14
+#define CLK_MATRIX_500M_SRC 15
+#define CLK_MATRIX_600M_SRC 16
+#define CLK_UART0_SRC 17
+#define CLK_UART0_FRAC 18
+#define SCLK_UART0 19
+#define CLK_UART1_SRC 20
+#define CLK_UART1_FRAC 21
+#define SCLK_UART1 22
+#define CLK_UART2_SRC 23
+#define CLK_UART2_FRAC 24
+#define SCLK_UART2 25
+#define CLK_UART3_SRC 26
+#define CLK_UART3_FRAC 27
+#define SCLK_UART3 28
+#define CLK_UART4_SRC 29
+#define CLK_UART4_FRAC 30
+#define SCLK_UART4 31
+#define CLK_UART5_SRC 32
+#define CLK_UART5_FRAC 33
+#define SCLK_UART5 34
+#define CLK_UART6_SRC 35
+#define CLK_UART6_FRAC 36
+#define SCLK_UART6 37
+#define CLK_UART7_SRC 38
+#define CLK_UART7_FRAC 39
+#define SCLK_UART7 40
+#define CLK_I2S0_2CH_SRC 41
+#define CLK_I2S0_2CH_FRAC 42
+#define MCLK_I2S0_2CH_SAI_SRC 43
+#define CLK_I2S3_8CH_SRC 44
+#define CLK_I2S3_8CH_FRAC 45
+#define MCLK_I2S3_8CH_SAI_SRC 46
+#define CLK_I2S1_8CH_SRC 47
+#define CLK_I2S1_8CH_FRAC 48
+#define MCLK_I2S1_8CH_SAI_SRC 49
+#define CLK_I2S2_2CH_SRC 50
+#define CLK_I2S2_2CH_FRAC 51
+#define MCLK_I2S2_2CH_SAI_SRC 52
+#define CLK_SPDIF_SRC 53
+#define CLK_SPDIF_FRAC 54
+#define MCLK_SPDIF_SRC 55
+#define DCLK_VOP_SRC0 56
+#define DCLK_VOP_SRC1 57
+#define CLK_HSM 58
+#define CLK_CORE_SRC_ACS 59
+#define CLK_CORE_SRC_PVTMUX 60
+#define CLK_CORE_SRC 61
+#define CLK_CORE 62
+#define ACLK_M_CORE_BIU 63
+#define CLK_CORE_PVTPLL_SRC 64
+#define PCLK_DBG 65
+#define SWCLKTCK 66
+#define CLK_SCANHS_CORE 67
+#define CLK_SCANHS_ACLKM_CORE 68
+#define CLK_SCANHS_PCLK_DBG 69
+#define CLK_SCANHS_PCLK_CPU_BIU 70
+#define PCLK_CPU_ROOT 71
+#define PCLK_CORE_GRF 72
+#define PCLK_DAPLITE_BIU 73
+#define PCLK_CPU_BIU 74
+#define CLK_REF_PVTPLL_CORE 75
+#define ACLK_BUS_VOPGL_ROOT 76
+#define ACLK_BUS_VOPGL_BIU 77
+#define ACLK_BUS_H_ROOT 78
+#define ACLK_BUS_H_BIU 79
+#define ACLK_BUS_ROOT 80
+#define HCLK_BUS_ROOT 81
+#define PCLK_BUS_ROOT 82
+#define ACLK_BUS_M_ROOT 83
+#define ACLK_SYSMEM_BIU 84
+#define CLK_TIMER_ROOT 85
+#define ACLK_BUS_BIU 86
+#define HCLK_BUS_BIU 87
+#define PCLK_BUS_BIU 88
+#define PCLK_DFT2APB 89
+#define PCLK_BUS_GRF 90
+#define ACLK_BUS_M_BIU 91
+#define ACLK_GIC 92
+#define ACLK_SPINLOCK 93
+#define ACLK_DMAC 94
+#define PCLK_TIMER 95
+#define CLK_TIMER0 96
+#define CLK_TIMER1 97
+#define CLK_TIMER2 98
+#define CLK_TIMER3 99
+#define CLK_TIMER4 100
+#define CLK_TIMER5 101
+#define PCLK_JDBCK_DAP 102
+#define CLK_JDBCK_DAP 103
+#define PCLK_WDT_NS 104
+#define TCLK_WDT_NS 105
+#define HCLK_TRNG_NS 106
+#define PCLK_UART0 107
+#define PCLK_DMA2DDR 108
+#define ACLK_DMA2DDR 109
+#define PCLK_PWM0 110
+#define CLK_PWM0 111
+#define CLK_CAPTURE_PWM0 112
+#define PCLK_PWM1 113
+#define CLK_PWM1 114
+#define CLK_CAPTURE_PWM1 115
+#define PCLK_SCR 116
+#define ACLK_DCF 117
+#define PCLK_INTMUX 118
+#define CLK_PPLL_I 119
+#define CLK_PPLL_MUX 120
+#define CLK_PPLL_100M_MATRIX 121
+#define CLK_PPLL_50M_MATRIX 122
+#define CLK_REF_PCIE_INNER_PHY 123
+#define CLK_REF_PCIE_100M_PHY 124
+#define ACLK_VPU_L_ROOT 125
+#define CLK_GMAC1_VPU_25M 126
+#define CLK_PPLL_125M_MATRIX 127
+#define ACLK_VPU_ROOT 128
+#define HCLK_VPU_ROOT 129
+#define PCLK_VPU_ROOT 130
+#define ACLK_VPU_BIU 131
+#define HCLK_VPU_BIU 132
+#define PCLK_VPU_BIU 133
+#define ACLK_VPU 134
+#define HCLK_VPU 135
+#define PCLK_CRU_PCIE 136
+#define PCLK_VPU_GRF 137
+#define HCLK_SFC 138
+#define SCLK_SFC 139
+#define CCLK_SRC_EMMC 140
+#define HCLK_EMMC 141
+#define ACLK_EMMC 142
+#define BCLK_EMMC 143
+#define TCLK_EMMC 144
+#define PCLK_GPIO1 145
+#define DBCLK_GPIO1 146
+#define ACLK_VPU_L_BIU 147
+#define PCLK_VPU_IOC 148
+#define HCLK_SAI_I2S0 149
+#define MCLK_SAI_I2S0 150
+#define HCLK_SAI_I2S2 151
+#define MCLK_SAI_I2S2 152
+#define PCLK_ACODEC 153
+#define MCLK_ACODEC_TX 154
+#define PCLK_GPIO3 155
+#define DBCLK_GPIO3 156
+#define PCLK_SPI1 157
+#define CLK_SPI1 158
+#define SCLK_IN_SPI1 159
+#define PCLK_UART2 160
+#define PCLK_UART5 161
+#define PCLK_UART6 162
+#define PCLK_UART7 163
+#define PCLK_I2C3 164
+#define CLK_I2C3 165
+#define PCLK_I2C5 166
+#define CLK_I2C5 167
+#define PCLK_I2C6 168
+#define CLK_I2C6 169
+#define ACLK_MAC_VPU 170
+#define PCLK_MAC_VPU 171
+#define CLK_GMAC1_RMII_VPU 172
+#define CLK_GMAC1_SRC_VPU 173
+#define PCLK_PCIE 174
+#define CLK_PCIE_AUX 175
+#define ACLK_PCIE 176
+#define HCLK_PCIE_SLV 177
+#define HCLK_PCIE_DBI 178
+#define PCLK_PCIE_PHY 179
+#define PCLK_PIPE_GRF 180
+#define CLK_PIPE_USB3OTG_COMBO 181
+#define CLK_UTMI_USB3OTG 182
+#define CLK_PCIE_PIPE_PHY 183
+#define CCLK_SRC_SDIO0 184
+#define HCLK_SDIO0 185
+#define CCLK_SRC_SDIO1 186
+#define HCLK_SDIO1 187
+#define CLK_TS_0 188
+#define CLK_TS_1 189
+#define PCLK_CAN2 190
+#define CLK_CAN2 191
+#define PCLK_CAN3 192
+#define CLK_CAN3 193
+#define PCLK_SARADC 194
+#define CLK_SARADC 195
+#define PCLK_TSADC 196
+#define CLK_TSADC 197
+#define CLK_TSADC_TSEN 198
+#define ACLK_USB3OTG 199
+#define CLK_REF_USB3OTG 200
+#define CLK_SUSPEND_USB3OTG 201
+#define ACLK_GPU_ROOT 202
+#define PCLK_GPU_ROOT 203
+#define ACLK_GPU_BIU 204
+#define PCLK_GPU_BIU 205
+#define ACLK_GPU 206
+#define CLK_GPU_PVTPLL_SRC 207
+#define ACLK_GPU_MALI 208
+#define HCLK_RKVENC_ROOT 209
+#define ACLK_RKVENC_ROOT 210
+#define PCLK_RKVENC_ROOT 211
+#define HCLK_RKVENC_BIU 212
+#define ACLK_RKVENC_BIU 213
+#define PCLK_RKVENC_BIU 214
+#define HCLK_RKVENC 215
+#define ACLK_RKVENC 216
+#define CLK_CORE_RKVENC 217
+#define HCLK_SAI_I2S1 218
+#define MCLK_SAI_I2S1 219
+#define PCLK_I2C1 220
+#define CLK_I2C1 221
+#define PCLK_I2C0 222
+#define CLK_I2C0 223
+#define CLK_UART_JTAG 224
+#define PCLK_SPI0 225
+#define CLK_SPI0 226
+#define SCLK_IN_SPI0 227
+#define PCLK_GPIO4 228
+#define DBCLK_GPIO4 229
+#define PCLK_RKVENC_IOC 230
+#define HCLK_SPDIF 231
+#define MCLK_SPDIF 232
+#define HCLK_PDM 233
+#define MCLK_PDM 234
+#define PCLK_UART1 235
+#define PCLK_UART3 236
+#define PCLK_RKVENC_GRF 237
+#define PCLK_CAN0 238
+#define CLK_CAN0 239
+#define PCLK_CAN1 240
+#define CLK_CAN1 241
+#define ACLK_VO_ROOT 242
+#define HCLK_VO_ROOT 243
+#define PCLK_VO_ROOT 244
+#define ACLK_VO_BIU 245
+#define HCLK_VO_BIU 246
+#define PCLK_VO_BIU 247
+#define HCLK_RGA2E 248
+#define ACLK_RGA2E 249
+#define CLK_CORE_RGA2E 250
+#define HCLK_VDPP 251
+#define ACLK_VDPP 252
+#define CLK_CORE_VDPP 253
+#define PCLK_VO_GRF 254
+#define PCLK_CRU 255
+#define ACLK_VOP_ROOT 256
+#define ACLK_VOP_BIU 257
+#define HCLK_VOP 258
+#define DCLK_VOP0 259
+#define DCLK_VOP1 260
+#define ACLK_VOP 261
+#define PCLK_HDMI 262
+#define CLK_SFR_HDMI 263
+#define CLK_CEC_HDMI 264
+#define CLK_SPDIF_HDMI 265
+#define CLK_HDMIPHY_TMDSSRC 266
+#define CLK_HDMIPHY_PREP 267
+#define PCLK_HDMIPHY 268
+#define HCLK_HDCP_KEY 269
+#define ACLK_HDCP 270
+#define HCLK_HDCP 271
+#define PCLK_HDCP 272
+#define HCLK_CVBS 273
+#define DCLK_CVBS 274
+#define DCLK_4X_CVBS 275
+#define ACLK_JPEG_DECODER 276
+#define HCLK_JPEG_DECODER 277
+#define ACLK_VO_L_ROOT 278
+#define ACLK_VO_L_BIU 279
+#define ACLK_MAC_VO 280
+#define PCLK_MAC_VO 281
+#define CLK_GMAC0_SRC 282
+#define CLK_GMAC0_RMII_50M 283
+#define CLK_GMAC0_TX 284
+#define CLK_GMAC0_RX 285
+#define ACLK_JPEG_ROOT 286
+#define ACLK_JPEG_BIU 287
+#define HCLK_SAI_I2S3 288
+#define MCLK_SAI_I2S3 289
+#define CLK_MACPHY 290
+#define PCLK_VCDCPHY 291
+#define PCLK_GPIO2 292
+#define DBCLK_GPIO2 293
+#define PCLK_VO_IOC 294
+#define CCLK_SRC_SDMMC0 295
+#define HCLK_SDMMC0 296
+#define PCLK_OTPC_NS 297
+#define CLK_SBPI_OTPC_NS 298
+#define CLK_USER_OTPC_NS 299
+#define CLK_HDMIHDP0 300
+#define HCLK_USBHOST 301
+#define HCLK_USBHOST_ARB 302
+#define CLK_USBHOST_OHCI 303
+#define CLK_USBHOST_UTMI 304
+#define PCLK_UART4 305
+#define PCLK_I2C4 306
+#define CLK_I2C4 307
+#define PCLK_I2C7 308
+#define CLK_I2C7 309
+#define PCLK_USBPHY 310
+#define CLK_REF_USBPHY 311
+#define HCLK_RKVDEC_ROOT 312
+#define ACLK_RKVDEC_ROOT_NDFT 313
+#define PCLK_DDRPHY_CRU 314
+#define HCLK_RKVDEC_BIU 315
+#define ACLK_RKVDEC_BIU 316
+#define ACLK_RKVDEC 317
+#define HCLK_RKVDEC 318
+#define CLK_HEVC_CA_RKVDEC 319
+#define ACLK_RKVDEC_PVTMUX_ROOT 320
+#define CLK_RKVDEC_PVTPLL_SRC 321
+#define PCLK_DDR_ROOT 322
+#define PCLK_DDR_BIU 323
+#define PCLK_DDRC 324
+#define PCLK_DDRMON 325
+#define CLK_TIMER_DDRMON 326
+#define PCLK_MSCH_BIU 327
+#define PCLK_DDR_GRF 328
+#define PCLK_DDR_HWLP 329
+#define PCLK_DDRPHY 330
+#define CLK_MSCH_BIU 331
+#define ACLK_DDR_UPCTL 332
+#define CLK_DDR_UPCTL 333
+#define CLK_DDRMON 334
+#define ACLK_DDR_SCRAMBLE 335
+#define ACLK_SPLIT 336
+#define CLK_DDRC_SRC 337
+#define CLK_DDR_PHY 338
+#define PCLK_OTPC_S 339
+#define CLK_SBPI_OTPC_S 340
+#define CLK_USER_OTPC_S 341
+#define PCLK_KEYREADER 342
+#define PCLK_BUS_SGRF 343
+#define PCLK_STIMER 344
+#define CLK_STIMER0 345
+#define CLK_STIMER1 346
+#define PCLK_WDT_S 347
+#define TCLK_WDT_S 348
+#define HCLK_TRNG_S 349
+#define HCLK_BOOTROM 350
+#define PCLK_DCF 351
+#define ACLK_SYSMEM 352
+#define HCLK_TSP 353
+#define ACLK_TSP 354
+#define CLK_CORE_TSP 355
+#define CLK_OTPC_ARB 356
+#define PCLK_OTP_MASK 357
+#define CLK_PMC_OTP 358
+#define PCLK_PMU_ROOT 359
+#define HCLK_PMU_ROOT 360
+#define PCLK_I2C2 361
+#define CLK_I2C2 362
+#define HCLK_PMU_BIU 363
+#define PCLK_PMU_BIU 364
+#define FCLK_MCU 365
+#define RTC_CLK_MCU 366
+#define PCLK_OSCCHK 367
+#define CLK_PMU_MCU_JTAG 368
+#define PCLK_PMU 369
+#define PCLK_GPIO0 370
+#define DBCLK_GPIO0 371
+#define XIN_OSC0_DIV 372
+#define CLK_DEEPSLOW 373
+#define CLK_DDR_FAIL_SAFE 374
+#define PCLK_PMU_HP_TIMER 375
+#define CLK_PMU_HP_TIMER 376
+#define CLK_PMU_32K_HP_TIMER 377
+#define PCLK_PMU_IOC 378
+#define PCLK_PMU_CRU 379
+#define PCLK_PMU_GRF 380
+#define PCLK_PMU_WDT 381
+#define TCLK_PMU_WDT 382
+#define PCLK_PMU_MAILBOX 383
+#define PCLK_SCRKEYGEN 384
+#define CLK_SCRKEYGEN 385
+#define CLK_PVTM_OSCCHK 386
+#define CLK_REFOUT 387
+#define CLK_PVTM_PMU 388
+#define PCLK_PVTM_PMU 389
+#define PCLK_PMU_SGRF 390
+#define HCLK_PMU_SRAM 391
+#define CLK_UART0 392
+#define CLK_UART1 393
+#define CLK_UART2 394
+#define CLK_UART3 395
+#define CLK_UART4 396
+#define CLK_UART5 397
+#define CLK_UART6 398
+#define CLK_UART7 399
+#define MCLK_I2S0_2CH_SAI_SRC_PRE 400
+#define MCLK_I2S1_8CH_SAI_SRC_PRE 401
+#define MCLK_I2S2_2CH_SAI_SRC_PRE 402
+#define MCLK_I2S3_8CH_SAI_SRC_PRE 403
+#define MCLK_SDPDIF_SRC_PRE 404
+
+/* scmi-clocks indices */
+#define SCMI_PCLK_KEYREADER 0
+#define SCMI_HCLK_KLAD 1
+#define SCMI_PCLK_KLAD 2
+#define SCMI_HCLK_TRNG_S 3
+#define SCMI_HCLK_CRYPTO_S 4
+#define SCMI_PCLK_WDT_S 5
+#define SCMI_TCLK_WDT_S 6
+#define SCMI_PCLK_STIMER 7
+#define SCMI_CLK_STIMER0 8
+#define SCMI_CLK_STIMER1 9
+#define SCMI_PCLK_OTP_MASK 10
+#define SCMI_PCLK_OTPC_S 11
+#define SCMI_CLK_SBPI_OTPC_S 12
+#define SCMI_CLK_USER_OTPC_S 13
+#define SCMI_CLK_PMC_OTP 14
+#define SCMI_CLK_OTPC_ARB 15
+#define SCMI_CLK_CORE_TSP 16
+#define SCMI_ACLK_TSP 17
+#define SCMI_HCLK_TSP 18
+#define SCMI_PCLK_DCF 19
+#define SCMI_CLK_DDR 20
+#define SCMI_CLK_CPU 21
+#define SCMI_CLK_GPU 22
+#define SCMI_CORE_CRYPTO 23
+#define SCMI_ACLK_CRYPTO 24
+#define SCMI_PKA_CRYPTO 25
+#define SCMI_HCLK_CRYPTO 26
+#define SCMI_CORE_CRYPTO_S 27
+#define SCMI_ACLK_CRYPTO_S 28
+#define SCMI_PKA_CRYPTO_S 29
+#define SCMI_CORE_KLAD 30
+#define SCMI_ACLK_KLAD 31
+#define SCMI_HCLK_TRNG 32
+
+#endif // _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
diff --git a/dts/upstream/include/dt-bindings/reset/rockchip,rk3528-cru.h b/dts/upstream/include/dt-bindings/reset/rockchip,rk3528-cru.h
new file mode 100644
index 0000000..6b024c5
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/reset/rockchip,rk3528-cru.h
@@ -0,0 +1,241 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
+ * Author: Joseph Chen <chenjh@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H
+#define _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H
+
+#define SRST_CORE0_PO 0
+#define SRST_CORE1_PO 1
+#define SRST_CORE2_PO 2
+#define SRST_CORE3_PO 3
+#define SRST_CORE0 4
+#define SRST_CORE1 5
+#define SRST_CORE2 6
+#define SRST_CORE3 7
+#define SRST_NL2 8
+#define SRST_CORE_BIU 9
+#define SRST_CORE_CRYPTO 10
+#define SRST_P_DBG 11
+#define SRST_POT_DBG 12
+#define SRST_NT_DBG 13
+#define SRST_P_CORE_GRF 14
+#define SRST_P_DAPLITE_BIU 15
+#define SRST_P_CPU_BIU 16
+#define SRST_REF_PVTPLL_CORE 17
+#define SRST_A_BUS_VOPGL_BIU 18
+#define SRST_A_BUS_H_BIU 19
+#define SRST_A_SYSMEM_BIU 20
+#define SRST_A_BUS_BIU 21
+#define SRST_H_BUS_BIU 22
+#define SRST_P_BUS_BIU 23
+#define SRST_P_DFT2APB 24
+#define SRST_P_BUS_GRF 25
+#define SRST_A_BUS_M_BIU 26
+#define SRST_A_GIC 27
+#define SRST_A_SPINLOCK 28
+#define SRST_A_DMAC 29
+#define SRST_P_TIMER 30
+#define SRST_TIMER0 31
+#define SRST_TIMER1 32
+#define SRST_TIMER2 33
+#define SRST_TIMER3 34
+#define SRST_TIMER4 35
+#define SRST_TIMER5 36
+#define SRST_P_JDBCK_DAP 37
+#define SRST_JDBCK_DAP 38
+#define SRST_P_WDT_NS 39
+#define SRST_T_WDT_NS 40
+#define SRST_H_TRNG_NS 41
+#define SRST_P_UART0 42
+#define SRST_S_UART0 43
+#define SRST_PKA_CRYPTO 44
+#define SRST_A_CRYPTO 45
+#define SRST_H_CRYPTO 46
+#define SRST_P_DMA2DDR 47
+#define SRST_A_DMA2DDR 48
+#define SRST_P_PWM0 49
+#define SRST_PWM0 50
+#define SRST_P_PWM1 51
+#define SRST_PWM1 52
+#define SRST_P_SCR 53
+#define SRST_A_DCF 54
+#define SRST_P_INTMUX 55
+#define SRST_A_VPU_BIU 56
+#define SRST_H_VPU_BIU 57
+#define SRST_P_VPU_BIU 58
+#define SRST_A_VPU 59
+#define SRST_H_VPU 60
+#define SRST_P_CRU_PCIE 61
+#define SRST_P_VPU_GRF 62
+#define SRST_H_SFC 63
+#define SRST_S_SFC 64
+#define SRST_C_EMMC 65
+#define SRST_H_EMMC 66
+#define SRST_A_EMMC 67
+#define SRST_B_EMMC 68
+#define SRST_T_EMMC 69
+#define SRST_P_GPIO1 70
+#define SRST_DB_GPIO1 71
+#define SRST_A_VPU_L_BIU 72
+#define SRST_P_VPU_IOC 73
+#define SRST_H_SAI_I2S0 74
+#define SRST_M_SAI_I2S0 75
+#define SRST_H_SAI_I2S2 76
+#define SRST_M_SAI_I2S2 77
+#define SRST_P_ACODEC 78
+#define SRST_P_GPIO3 79
+#define SRST_DB_GPIO3 80
+#define SRST_P_SPI1 81
+#define SRST_SPI1 82
+#define SRST_P_UART2 83
+#define SRST_S_UART2 84
+#define SRST_P_UART5 85
+#define SRST_S_UART5 86
+#define SRST_P_UART6 87
+#define SRST_S_UART6 88
+#define SRST_P_UART7 89
+#define SRST_S_UART7 90
+#define SRST_P_I2C3 91
+#define SRST_I2C3 92
+#define SRST_P_I2C5 93
+#define SRST_I2C5 94
+#define SRST_P_I2C6 95
+#define SRST_I2C6 96
+#define SRST_A_MAC 97
+#define SRST_P_PCIE 98
+#define SRST_PCIE_PIPE_PHY 99
+#define SRST_PCIE_POWER_UP 100
+#define SRST_P_PCIE_PHY 101
+#define SRST_P_PIPE_GRF 102
+#define SRST_H_SDIO0 103
+#define SRST_H_SDIO1 104
+#define SRST_TS_0 105
+#define SRST_TS_1 106
+#define SRST_P_CAN2 107
+#define SRST_CAN2 108
+#define SRST_P_CAN3 109
+#define SRST_CAN3 110
+#define SRST_P_SARADC 111
+#define SRST_SARADC 112
+#define SRST_SARADC_PHY 113
+#define SRST_P_TSADC 114
+#define SRST_TSADC 115
+#define SRST_A_USB3OTG 116
+#define SRST_A_GPU_BIU 117
+#define SRST_P_GPU_BIU 118
+#define SRST_A_GPU 119
+#define SRST_REF_PVTPLL_GPU 120
+#define SRST_H_RKVENC_BIU 121
+#define SRST_A_RKVENC_BIU 122
+#define SRST_P_RKVENC_BIU 123
+#define SRST_H_RKVENC 124
+#define SRST_A_RKVENC 125
+#define SRST_CORE_RKVENC 126
+#define SRST_H_SAI_I2S1 127
+#define SRST_M_SAI_I2S1 128
+#define SRST_P_I2C1 129
+#define SRST_I2C1 130
+#define SRST_P_I2C0 131
+#define SRST_I2C0 132
+#define SRST_P_SPI0 133
+#define SRST_SPI0 134
+#define SRST_P_GPIO4 135
+#define SRST_DB_GPIO4 136
+#define SRST_P_RKVENC_IOC 137
+#define SRST_H_SPDIF 138
+#define SRST_M_SPDIF 139
+#define SRST_H_PDM 140
+#define SRST_M_PDM 141
+#define SRST_P_UART1 142
+#define SRST_S_UART1 143
+#define SRST_P_UART3 144
+#define SRST_S_UART3 145
+#define SRST_P_RKVENC_GRF 146
+#define SRST_P_CAN0 147
+#define SRST_CAN0 148
+#define SRST_P_CAN1 149
+#define SRST_CAN1 150
+#define SRST_A_VO_BIU 151
+#define SRST_H_VO_BIU 152
+#define SRST_P_VO_BIU 153
+#define SRST_H_RGA2E 154
+#define SRST_A_RGA2E 155
+#define SRST_CORE_RGA2E 156
+#define SRST_H_VDPP 157
+#define SRST_A_VDPP 158
+#define SRST_CORE_VDPP 159
+#define SRST_P_VO_GRF 160
+#define SRST_P_CRU 161
+#define SRST_A_VOP_BIU 162
+#define SRST_H_VOP 163
+#define SRST_D_VOP0 164
+#define SRST_D_VOP1 165
+#define SRST_A_VOP 166
+#define SRST_P_HDMI 167
+#define SRST_HDMI 168
+#define SRST_P_HDMIPHY 169
+#define SRST_H_HDCP_KEY 170
+#define SRST_A_HDCP 171
+#define SRST_H_HDCP 172
+#define SRST_P_HDCP 173
+#define SRST_H_CVBS 174
+#define SRST_D_CVBS_VOP 175
+#define SRST_D_4X_CVBS_VOP 176
+#define SRST_A_JPEG_DECODER 177
+#define SRST_H_JPEG_DECODER 178
+#define SRST_A_VO_L_BIU 179
+#define SRST_A_MAC_VO 180
+#define SRST_A_JPEG_BIU 181
+#define SRST_H_SAI_I2S3 182
+#define SRST_M_SAI_I2S3 183
+#define SRST_MACPHY 184
+#define SRST_P_VCDCPHY 185
+#define SRST_P_GPIO2 186
+#define SRST_DB_GPIO2 187
+#define SRST_P_VO_IOC 188
+#define SRST_H_SDMMC0 189
+#define SRST_P_OTPC_NS 190
+#define SRST_SBPI_OTPC_NS 191
+#define SRST_USER_OTPC_NS 192
+#define SRST_HDMIHDP0 193
+#define SRST_H_USBHOST 194
+#define SRST_H_USBHOST_ARB 195
+#define SRST_HOST_UTMI 196
+#define SRST_P_UART4 197
+#define SRST_S_UART4 198
+#define SRST_P_I2C4 199
+#define SRST_I2C4 200
+#define SRST_P_I2C7 201
+#define SRST_I2C7 202
+#define SRST_P_USBPHY 203
+#define SRST_USBPHY_POR 204
+#define SRST_USBPHY_OTG 205
+#define SRST_USBPHY_HOST 206
+#define SRST_P_DDRPHY_CRU 207
+#define SRST_H_RKVDEC_BIU 208
+#define SRST_A_RKVDEC_BIU 209
+#define SRST_A_RKVDEC 210
+#define SRST_H_RKVDEC 211
+#define SRST_HEVC_CA_RKVDEC 212
+#define SRST_REF_PVTPLL_RKVDEC 213
+#define SRST_P_DDR_BIU 214
+#define SRST_P_DDRC 215
+#define SRST_P_DDRMON 216
+#define SRST_TIMER_DDRMON 217
+#define SRST_P_MSCH_BIU 218
+#define SRST_P_DDR_GRF 219
+#define SRST_P_DDR_HWLP 220
+#define SRST_P_DDRPHY 221
+#define SRST_MSCH_BIU 222
+#define SRST_A_DDR_UPCTL 223
+#define SRST_DDR_UPCTL 224
+#define SRST_DDRMON 225
+#define SRST_A_DDR_SCRAMBLE 226
+#define SRST_A_SPLIT 227
+#define SRST_DDR_PHY 228
+
+#endif // _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H
diff --git a/dts/upstream/src/arm64/rockchip/rk3528-pinctrl.dtsi b/dts/upstream/src/arm64/rockchip/rk3528-pinctrl.dtsi
new file mode 100644
index 0000000..ea05136
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3528-pinctrl.dtsi
@@ -0,0 +1,1397 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rockchip-pinconf.dtsi"
+
+/*
+ * This file is auto generated by pin2dts tool, please keep these code
+ * by adding changes at end of this file.
+ */
+&pinctrl {
+ arm {
+ /omit-if-no-ref/
+ arm_pins: arm-pins {
+ rockchip,pins =
+ /* arm_avs */
+ <4 RK_PC4 3 &pcfg_pull_none>;
+ };
+ };
+
+ clk {
+ /omit-if-no-ref/
+ clkm0_32k_out: clkm0-32k-out {
+ rockchip,pins =
+ /* clkm0_32k_out */
+ <3 RK_PC3 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ clkm1_32k_out: clkm1-32k-out {
+ rockchip,pins =
+ /* clkm1_32k_out */
+ <1 RK_PC3 1 &pcfg_pull_none>;
+ };
+ };
+
+ emmc {
+ /omit-if-no-ref/
+ emmc_rstnout: emmc-rstnout {
+ rockchip,pins =
+ /* emmc_rstn */
+ <1 RK_PD6 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins =
+ /* emmc_d0 */
+ <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d1 */
+ <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d2 */
+ <1 RK_PC6 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d3 */
+ <1 RK_PC7 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d4 */
+ <1 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d5 */
+ <1 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d6 */
+ <1 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d7 */
+ <1 RK_PD3 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ emmc_clk: emmc-clk {
+ rockchip,pins =
+ /* emmc_clk */
+ <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ emmc_cmd: emmc-cmd {
+ rockchip,pins =
+ /* emmc_cmd */
+ <1 RK_PD4 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ emmc_strb: emmc-strb {
+ rockchip,pins =
+ /* emmc_strb */
+ <1 RK_PD7 1 &pcfg_pull_none>;
+ };
+ };
+
+ eth {
+ /omit-if-no-ref/
+ eth_pins: eth-pins {
+ rockchip,pins =
+ /* eth_clk_25m_out */
+ <3 RK_PB5 2 &pcfg_pull_none_drv_level_2>;
+ };
+ };
+
+ fephy {
+ /omit-if-no-ref/
+ fephym0_led_dpx: fephym0-led_dpx {
+ rockchip,pins =
+ /* fephy_led_dpx_m0 */
+ <4 RK_PB5 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ fephym0_led_link: fephym0-led_link {
+ rockchip,pins =
+ /* fephy_led_link_m0 */
+ <4 RK_PC0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ fephym0_led_spd: fephym0-led_spd {
+ rockchip,pins =
+ /* fephy_led_spd_m0 */
+ <4 RK_PB7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ fephym1_led_dpx: fephym1-led_dpx {
+ rockchip,pins =
+ /* fephy_led_dpx_m1 */
+ <2 RK_PA4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ fephym1_led_link: fephym1-led_link {
+ rockchip,pins =
+ /* fephy_led_link_m1 */
+ <2 RK_PA6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ fephym1_led_spd: fephym1-led_spd {
+ rockchip,pins =
+ /* fephy_led_spd_m1 */
+ <2 RK_PA5 5 &pcfg_pull_none>;
+ };
+ };
+
+ fspi {
+ /omit-if-no-ref/
+ fspi_pins: fspi-pins {
+ rockchip,pins =
+ /* fspi_clk */
+ <1 RK_PD5 2 &pcfg_pull_none>,
+ /* fspi_d0 */
+ <1 RK_PC4 2 &pcfg_pull_none>,
+ /* fspi_d1 */
+ <1 RK_PC5 2 &pcfg_pull_none>,
+ /* fspi_d2 */
+ <1 RK_PC6 2 &pcfg_pull_none>,
+ /* fspi_d3 */
+ <1 RK_PC7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ fspi_csn0: fspi-csn0 {
+ rockchip,pins =
+ /* fspi_csn0 */
+ <1 RK_PD0 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ fspi_csn1: fspi-csn1 {
+ rockchip,pins =
+ /* fspi_csn1 */
+ <1 RK_PD1 2 &pcfg_pull_none>;
+ };
+ };
+
+ gpu {
+ /omit-if-no-ref/
+ gpu_pins: gpu-pins {
+ rockchip,pins =
+ /* gpu_avs */
+ <4 RK_PC3 3 &pcfg_pull_none>;
+ };
+ };
+
+ hdmi {
+ /omit-if-no-ref/
+ hdmi_pins: hdmi-pins {
+ rockchip,pins =
+ /* hdmi_tx_cec */
+ <0 RK_PA3 1 &pcfg_pull_none>,
+ /* hdmi_tx_hpd */
+ <0 RK_PA2 1 &pcfg_pull_none>,
+ /* hdmi_tx_scl */
+ <0 RK_PA4 1 &pcfg_pull_none>,
+ /* hdmi_tx_sda */
+ <0 RK_PA5 1 &pcfg_pull_none>;
+ };
+ };
+
+ hsm {
+ /omit-if-no-ref/
+ hsmm0_pins: hsmm0-pins {
+ rockchip,pins =
+ /* hsm_clk_out_m0 */
+ <2 RK_PA2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hsmm1_pins: hsmm1-pins {
+ rockchip,pins =
+ /* hsm_clk_out_m1 */
+ <1 RK_PA4 3 &pcfg_pull_none>;
+ };
+ };
+
+ i2c0 {
+ /omit-if-no-ref/
+ i2c0m0_xfer: i2c0m0-xfer {
+ rockchip,pins =
+ /* i2c0_scl_m0 */
+ <4 RK_PC4 2 &pcfg_pull_none_smt>,
+ /* i2c0_sda_m0 */
+ <4 RK_PC3 2 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c0m1_xfer: i2c0m1-xfer {
+ rockchip,pins =
+ /* i2c0_scl_m1 */
+ <4 RK_PA1 2 &pcfg_pull_none_smt>,
+ /* i2c0_sda_m1 */
+ <4 RK_PA0 2 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c1 {
+ /omit-if-no-ref/
+ i2c1m0_xfer: i2c1m0-xfer {
+ rockchip,pins =
+ /* i2c1_scl_m0 */
+ <4 RK_PA3 2 &pcfg_pull_none_smt>,
+ /* i2c1_sda_m0 */
+ <4 RK_PA2 2 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c1m1_xfer: i2c1m1-xfer {
+ rockchip,pins =
+ /* i2c1_scl_m1 */
+ <4 RK_PC5 4 &pcfg_pull_none_smt>,
+ /* i2c1_sda_m1 */
+ <4 RK_PC6 4 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c2 {
+ /omit-if-no-ref/
+ i2c2m0_xfer: i2c2m0-xfer {
+ rockchip,pins =
+ /* i2c2_scl_m0 */
+ <0 RK_PA4 2 &pcfg_pull_none_smt>,
+ /* i2c2_sda_m0 */
+ <0 RK_PA5 2 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c2m1_xfer: i2c2m1-xfer {
+ rockchip,pins =
+ /* i2c2_scl_m1 */
+ <1 RK_PA5 3 &pcfg_pull_none_smt>,
+ /* i2c2_sda_m1 */
+ <1 RK_PA6 3 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c3 {
+ /omit-if-no-ref/
+ i2c3m0_xfer: i2c3m0-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m0 */
+ <1 RK_PA0 2 &pcfg_pull_none_smt>,
+ /* i2c3_sda_m0 */
+ <1 RK_PA1 2 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c3m1_xfer: i2c3m1-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m1 */
+ <3 RK_PC1 5 &pcfg_pull_none_smt>,
+ /* i2c3_sda_m1 */
+ <3 RK_PC3 5 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c4 {
+ /omit-if-no-ref/
+ i2c4_xfer: i2c4-xfer {
+ rockchip,pins =
+ /* i2c4_scl */
+ <2 RK_PA0 4 &pcfg_pull_none_smt>,
+ /* i2c4_sda */
+ <2 RK_PA1 4 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c5 {
+ /omit-if-no-ref/
+ i2c5m0_xfer: i2c5m0-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m0 */
+ <1 RK_PB2 3 &pcfg_pull_none_smt>,
+ /* i2c5_sda_m0 */
+ <1 RK_PB3 3 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c5m1_xfer: i2c5m1-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m1 */
+ <1 RK_PD2 3 &pcfg_pull_none_smt>,
+ /* i2c5_sda_m1 */
+ <1 RK_PD3 3 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c6 {
+ /omit-if-no-ref/
+ i2c6m0_xfer: i2c6m0-xfer {
+ rockchip,pins =
+ /* i2c6_scl_m0 */
+ <3 RK_PB2 5 &pcfg_pull_none_smt>,
+ /* i2c6_sda_m0 */
+ <3 RK_PB3 5 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c6m1_xfer: i2c6m1-xfer {
+ rockchip,pins =
+ /* i2c6_scl_m1 */
+ <1 RK_PD4 3 &pcfg_pull_none_smt>,
+ /* i2c6_sda_m1 */
+ <1 RK_PD7 3 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c7 {
+ /omit-if-no-ref/
+ i2c7_xfer: i2c7-xfer {
+ rockchip,pins =
+ /* i2c7_scl */
+ <2 RK_PA5 4 &pcfg_pull_none_smt>,
+ /* i2c7_sda */
+ <2 RK_PA6 4 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2s0 {
+ /omit-if-no-ref/
+ i2s0m0_lrck: i2s0m0-lrck {
+ rockchip,pins =
+ /* i2s0_lrck_m0 */
+ <3 RK_PB6 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m0_mclk: i2s0m0-mclk {
+ rockchip,pins =
+ /* i2s0_mclk_m0 */
+ <3 RK_PB4 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m0_sclk: i2s0m0-sclk {
+ rockchip,pins =
+ /* i2s0_sclk_m0 */
+ <3 RK_PB5 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m0_sdi: i2s0m0-sdi {
+ rockchip,pins =
+ /* i2s0m0_sdi */
+ <3 RK_PB7 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ i2s0m0_sdo: i2s0m0-sdo {
+ rockchip,pins =
+ /* i2s0m0_sdo */
+ <3 RK_PC0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m1_lrck: i2s0m1-lrck {
+ rockchip,pins =
+ /* i2s0_lrck_m1 */
+ <1 RK_PB6 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m1_mclk: i2s0m1-mclk {
+ rockchip,pins =
+ /* i2s0_mclk_m1 */
+ <1 RK_PB4 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m1_sclk: i2s0m1-sclk {
+ rockchip,pins =
+ /* i2s0_sclk_m1 */
+ <1 RK_PB5 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m1_sdi: i2s0m1-sdi {
+ rockchip,pins =
+ /* i2s0m1_sdi */
+ <1 RK_PB7 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ i2s0m1_sdo: i2s0m1-sdo {
+ rockchip,pins =
+ /* i2s0m1_sdo */
+ <1 RK_PC0 1 &pcfg_pull_none>;
+ };
+ };
+
+ i2s1 {
+ /omit-if-no-ref/
+ i2s1_lrck: i2s1-lrck {
+ rockchip,pins =
+ /* i2s1_lrck */
+ <4 RK_PA6 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s1_mclk: i2s1-mclk {
+ rockchip,pins =
+ /* i2s1_mclk */
+ <4 RK_PA4 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s1_sclk: i2s1-sclk {
+ rockchip,pins =
+ /* i2s1_sclk */
+ <4 RK_PA5 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s1_sdi0: i2s1-sdi0 {
+ rockchip,pins =
+ /* i2s1_sdi0 */
+ <4 RK_PB4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1_sdi1: i2s1-sdi1 {
+ rockchip,pins =
+ /* i2s1_sdi1 */
+ <4 RK_PB3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1_sdi2: i2s1-sdi2 {
+ rockchip,pins =
+ /* i2s1_sdi2 */
+ <4 RK_PA3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1_sdi3: i2s1-sdi3 {
+ rockchip,pins =
+ /* i2s1_sdi3 */
+ <4 RK_PA2 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1_sdo0: i2s1-sdo0 {
+ rockchip,pins =
+ /* i2s1_sdo0 */
+ <4 RK_PA7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1_sdo1: i2s1-sdo1 {
+ rockchip,pins =
+ /* i2s1_sdo1 */
+ <4 RK_PB0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1_sdo2: i2s1-sdo2 {
+ rockchip,pins =
+ /* i2s1_sdo2 */
+ <4 RK_PB1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1_sdo3: i2s1-sdo3 {
+ rockchip,pins =
+ /* i2s1_sdo3 */
+ <4 RK_PB2 1 &pcfg_pull_none>;
+ };
+ };
+
+ jtag {
+ /omit-if-no-ref/
+ jtagm0_pins: jtagm0-pins {
+ rockchip,pins =
+ /* jtag_cpu_tck_m0 */
+ <2 RK_PA2 2 &pcfg_pull_none>,
+ /* jtag_cpu_tms_m0 */
+ <2 RK_PA3 2 &pcfg_pull_none>,
+ /* jtag_mcu_tck_m0 */
+ <2 RK_PA4 2 &pcfg_pull_none>,
+ /* jtag_mcu_tms_m0 */
+ <2 RK_PA5 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ jtagm1_pins: jtagm1-pins {
+ rockchip,pins =
+ /* jtag_cpu_tck_m1 */
+ <4 RK_PD0 2 &pcfg_pull_none>,
+ /* jtag_cpu_tms_m1 */
+ <4 RK_PC7 2 &pcfg_pull_none>,
+ /* jtag_mcu_tck_m1 */
+ <4 RK_PD0 3 &pcfg_pull_none>,
+ /* jtag_mcu_tms_m1 */
+ <4 RK_PC7 3 &pcfg_pull_none>;
+ };
+ };
+
+ pcie {
+ /omit-if-no-ref/
+ pciem0_pins: pciem0-pins {
+ rockchip,pins =
+ /* pcie_clkreqn_m0 */
+ <3 RK_PA6 5 &pcfg_pull_none>,
+ /* pcie_perstn_m0 */
+ <3 RK_PB0 5 &pcfg_pull_none>,
+ /* pcie_waken_m0 */
+ <3 RK_PA7 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pciem1_pins: pciem1-pins {
+ rockchip,pins =
+ /* pcie_clkreqn_m1 */
+ <1 RK_PA0 4 &pcfg_pull_none>,
+ /* pcie_perstn_m1 */
+ <1 RK_PA2 4 &pcfg_pull_none>,
+ /* pcie_waken_m1 */
+ <1 RK_PA1 4 &pcfg_pull_none>;
+ };
+ };
+
+ pdm {
+ /omit-if-no-ref/
+ pdm_clk0: pdm-clk0 {
+ rockchip,pins =
+ /* pdm_clk0 */
+ <4 RK_PB5 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm_clk1: pdm-clk1 {
+ rockchip,pins =
+ /* pdm_clk1 */
+ <4 RK_PA4 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm_sdi0: pdm-sdi0 {
+ rockchip,pins =
+ /* pdm_sdi0 */
+ <4 RK_PB2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm_sdi1: pdm-sdi1 {
+ rockchip,pins =
+ /* pdm_sdi1 */
+ <4 RK_PB1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm_sdi2: pdm-sdi2 {
+ rockchip,pins =
+ /* pdm_sdi2 */
+ <4 RK_PB3 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm_sdi3: pdm-sdi3 {
+ rockchip,pins =
+ /* pdm_sdi3 */
+ <4 RK_PC1 3 &pcfg_pull_none>;
+ };
+ };
+
+ pmu {
+ /omit-if-no-ref/
+ pmu_pins: pmu-pins {
+ rockchip,pins =
+ /* pmu_debug */
+ <4 RK_PA0 4 &pcfg_pull_none>;
+ };
+ };
+
+ pwm0 {
+ /omit-if-no-ref/
+ pwm0m0_pins: pwm0m0-pins {
+ rockchip,pins =
+ /* pwm0_m0 */
+ <4 RK_PC3 1 &pcfg_pull_none_drv_level_0>;
+ };
+
+ /omit-if-no-ref/
+ pwm0m1_pins: pwm0m1-pins {
+ rockchip,pins =
+ /* pwm0_m1 */
+ <1 RK_PA2 5 &pcfg_pull_none_drv_level_0>;
+ };
+ };
+
+ pwm1 {
+ /omit-if-no-ref/
+ pwm1m0_pins: pwm1m0-pins {
+ rockchip,pins =
+ /* pwm1_m0 */
+ <4 RK_PC4 1 &pcfg_pull_none_drv_level_0>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m1_pins: pwm1m1-pins {
+ rockchip,pins =
+ /* pwm1_m1 */
+ <1 RK_PA3 4 &pcfg_pull_none_drv_level_0>;
+ };
+ };
+
+ pwm2 {
+ /omit-if-no-ref/
+ pwm2m0_pins: pwm2m0-pins {
+ rockchip,pins =
+ /* pwm2_m0 */
+ <4 RK_PC5 1 &pcfg_pull_none_drv_level_0>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m1_pins: pwm2m1-pins {
+ rockchip,pins =
+ /* pwm2_m1 */
+ <1 RK_PA7 2 &pcfg_pull_none_drv_level_0>;
+ };
+ };
+
+ pwm3 {
+ /omit-if-no-ref/
+ pwm3m0_pins: pwm3m0-pins {
+ rockchip,pins =
+ /* pwm3_m0 */
+ <4 RK_PC6 1 &pcfg_pull_none_drv_level_0>;
+ };
+
+ /omit-if-no-ref/
+ pwm3m1_pins: pwm3m1-pins {
+ rockchip,pins =
+ /* pwm3_m1 */
+ <2 RK_PA4 3 &pcfg_pull_none_drv_level_0>;
+ };
+ };
+
+ pwm4 {
+ /omit-if-no-ref/
+ pwm4m0_pins: pwm4m0-pins {
+ rockchip,pins =
+ /* pwm4_m0 */
+ <4 RK_PB7 1 &pcfg_pull_none_drv_level_0>;
+ };
+
+ /omit-if-no-ref/
+ pwm4m1_pins: pwm4m1-pins {
+ rockchip,pins =
+ /* pwm4_m1 */
+ <1 RK_PA4 2 &pcfg_pull_none_drv_level_0>;
+ };
+ };
+
+ pwm5 {
+ /omit-if-no-ref/
+ pwm5m0_pins: pwm5m0-pins {
+ rockchip,pins =
+ /* pwm5_m0 */
+ <4 RK_PC0 1 &pcfg_pull_none_drv_level_0>;
+ };
+
+ /omit-if-no-ref/
+ pwm5m1_pins: pwm5m1-pins {
+ rockchip,pins =
+ /* pwm5_m1 */
+ <3 RK_PC3 1 &pcfg_pull_none_drv_level_0>;
+ };
+ };
+
+ pwm6 {
+ /omit-if-no-ref/
+ pwm6m0_pins: pwm6m0-pins {
+ rockchip,pins =
+ /* pwm6_m0 */
+ <4 RK_PC1 1 &pcfg_pull_none_drv_level_0>;
+ };
+
+ /omit-if-no-ref/
+ pwm6m1_pins: pwm6m1-pins {
+ rockchip,pins =
+ /* pwm6_m1 */
+ <1 RK_PC3 3 &pcfg_pull_none_drv_level_0>;
+ };
+
+ /omit-if-no-ref/
+ pwm6m2_pins: pwm6m2-pins {
+ rockchip,pins =
+ /* pwm6_m2 */
+ <3 RK_PC1 1 &pcfg_pull_none_drv_level_0>;
+ };
+ };
+
+ pwm7 {
+ /omit-if-no-ref/
+ pwm7m0_pins: pwm7m0-pins {
+ rockchip,pins =
+ /* pwm7_m0 */
+ <4 RK_PC2 1 &pcfg_pull_none_drv_level_0>;
+ };
+
+ /omit-if-no-ref/
+ pwm7m1_pins: pwm7m1-pins {
+ rockchip,pins =
+ /* pwm7_m1 */
+ <1 RK_PC2 2 &pcfg_pull_none_drv_level_0>;
+ };
+ };
+
+ pwr {
+ /omit-if-no-ref/
+ pwr_pins: pwr-pins {
+ rockchip,pins =
+ /* pwr_ctrl0 */
+ <4 RK_PC2 2 &pcfg_pull_none>,
+ /* pwr_ctrl1 */
+ <4 RK_PB6 1 &pcfg_pull_none>;
+ };
+ };
+
+ ref {
+ /omit-if-no-ref/
+ refm0_pins: refm0-pins {
+ rockchip,pins =
+ /* ref_clk_out_m0 */
+ <0 RK_PA1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ refm1_pins: refm1-pins {
+ rockchip,pins =
+ /* ref_clk_out_m1 */
+ <3 RK_PC3 6 &pcfg_pull_none>;
+ };
+ };
+
+ rgmii {
+ /omit-if-no-ref/
+ rgmii_miim: rgmii-miim {
+ rockchip,pins =
+ /* rgmii_mdc */
+ <3 RK_PB6 2 &pcfg_pull_none_drv_level_2>,
+ /* rgmii_mdio */
+ <3 RK_PB7 2 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ rgmii_rx_bus2: rgmii-rx_bus2 {
+ rockchip,pins =
+ /* rgmii_rxd0 */
+ <3 RK_PA3 2 &pcfg_pull_none>,
+ /* rgmii_rxd1 */
+ <3 RK_PA2 2 &pcfg_pull_none>,
+ /* rgmii_rxdv_crs */
+ <3 RK_PC2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ rgmii_tx_bus2: rgmii-tx_bus2 {
+ rockchip,pins =
+ /* rgmii_txd0 */
+ <3 RK_PA1 2 &pcfg_pull_none_drv_level_2>,
+ /* rgmii_txd1 */
+ <3 RK_PA0 2 &pcfg_pull_none_drv_level_2>,
+ /* rgmii_txen */
+ <3 RK_PC0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ rgmii_rgmii_clk: rgmii-rgmii_clk {
+ rockchip,pins =
+ /* rgmii_rxclk */
+ <3 RK_PA5 2 &pcfg_pull_none>,
+ /* rgmii_txclk */
+ <3 RK_PA4 2 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ rgmii_rgmii_bus: rgmii-rgmii_bus {
+ rockchip,pins =
+ /* rgmii_rxd2 */
+ <3 RK_PA7 2 &pcfg_pull_none>,
+ /* rgmii_rxd3 */
+ <3 RK_PA6 2 &pcfg_pull_none>,
+ /* rgmii_txd2 */
+ <3 RK_PB1 2 &pcfg_pull_none_drv_level_2>,
+ /* rgmii_txd3 */
+ <3 RK_PB0 2 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ rgmii_clk: rgmii-clk {
+ rockchip,pins =
+ /* rgmii_clk */
+ <3 RK_PB4 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ rgmii_txer: rgmii-txer {
+ rockchip,pins =
+ /* rgmii_txer */
+ <3 RK_PC1 2 &pcfg_pull_none>;
+ };
+ };
+
+ scr {
+ /omit-if-no-ref/
+ scrm0_pins: scrm0-pins {
+ rockchip,pins =
+ /* scr_clk_m0 */
+ <1 RK_PA2 3 &pcfg_pull_none>,
+ /* scr_data_m0 */
+ <1 RK_PA1 3 &pcfg_pull_none>,
+ /* scr_detn_m0 */
+ <1 RK_PA0 3 &pcfg_pull_none>,
+ /* scr_rstn_m0 */
+ <1 RK_PA3 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ scrm1_pins: scrm1-pins {
+ rockchip,pins =
+ /* scr_clk_m1 */
+ <2 RK_PA5 3 &pcfg_pull_none>,
+ /* scr_data_m1 */
+ <2 RK_PA3 4 &pcfg_pull_none>,
+ /* scr_detn_m1 */
+ <2 RK_PA6 3 &pcfg_pull_none>,
+ /* scr_rstn_m1 */
+ <2 RK_PA4 4 &pcfg_pull_none>;
+ };
+ };
+
+ sdio0 {
+ /omit-if-no-ref/
+ sdio0_bus4: sdio0-bus4 {
+ rockchip,pins =
+ /* sdio0_d0 */
+ <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
+ /* sdio0_d1 */
+ <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
+ /* sdio0_d2 */
+ <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
+ /* sdio0_d3 */
+ <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdio0_clk: sdio0-clk {
+ rockchip,pins =
+ /* sdio0_clk */
+ <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdio0_cmd: sdio0-cmd {
+ rockchip,pins =
+ /* sdio0_cmd */
+ <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdio0_det: sdio0-det {
+ rockchip,pins =
+ /* sdio0_det */
+ <1 RK_PA6 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ sdio0_pwren: sdio0-pwren {
+ rockchip,pins =
+ /* sdio0_pwren */
+ <1 RK_PA7 1 &pcfg_pull_none>;
+ };
+ };
+
+ sdio1 {
+ /omit-if-no-ref/
+ sdio1_bus4: sdio1-bus4 {
+ rockchip,pins =
+ /* sdio1_d0 */
+ <3 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
+ /* sdio1_d1 */
+ <3 RK_PA7 1 &pcfg_pull_up_drv_level_2>,
+ /* sdio1_d2 */
+ <3 RK_PB0 1 &pcfg_pull_up_drv_level_2>,
+ /* sdio1_d3 */
+ <3 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdio1_clk: sdio1-clk {
+ rockchip,pins =
+ /* sdio1_clk */
+ <3 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdio1_cmd: sdio1-cmd {
+ rockchip,pins =
+ /* sdio1_cmd */
+ <3 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdio1_det: sdio1-det {
+ rockchip,pins =
+ /* sdio1_det */
+ <3 RK_PB3 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ sdio1_pwren: sdio1-pwren {
+ rockchip,pins =
+ /* sdio1_pwren */
+ <3 RK_PB2 1 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc {
+ /omit-if-no-ref/
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins =
+ /* sdmmc_d0 */
+ <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc_d1 */
+ <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc_d2 */
+ <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc_d3 */
+ <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins =
+ /* sdmmc_clk */
+ <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins =
+ /* sdmmc_cmd */
+ <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc_det: sdmmc-det {
+ rockchip,pins =
+ /* sdmmc_detn */
+ <2 RK_PA6 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc_pwren: sdmmc-pwren {
+ rockchip,pins =
+ /* sdmmc_pwren */
+ <4 RK_PA1 1 &pcfg_pull_none>;
+ };
+ };
+
+ spdif {
+ /omit-if-no-ref/
+ spdifm0_pins: spdifm0-pins {
+ rockchip,pins =
+ /* spdif_tx_m0 */
+ <4 RK_PA0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm1_pins: spdifm1-pins {
+ rockchip,pins =
+ /* spdif_tx_m1 */
+ <1 RK_PC3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm2_pins: spdifm2-pins {
+ rockchip,pins =
+ /* spdif_tx_m2 */
+ <3 RK_PC3 2 &pcfg_pull_none>;
+ };
+ };
+
+ spi0 {
+ /omit-if-no-ref/
+ spi0_pins: spi0-pins {
+ rockchip,pins =
+ /* spi0_clk */
+ <4 RK_PB4 2 &pcfg_pull_none_drv_level_2>,
+ /* spi0_miso */
+ <4 RK_PB3 2 &pcfg_pull_none_drv_level_2>,
+ /* spi0_mosi */
+ <4 RK_PB2 2 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ spi0_csn0: spi0-csn0 {
+ rockchip,pins =
+ /* spi0_csn0 */
+ <4 RK_PB6 2 &pcfg_pull_none_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ spi0_csn1: spi0-csn1 {
+ rockchip,pins =
+ /* spi0_csn1 */
+ <4 RK_PC1 2 &pcfg_pull_none_drv_level_2>;
+ };
+ };
+
+ spi1 {
+ /omit-if-no-ref/
+ spi1_pins: spi1-pins {
+ rockchip,pins =
+ /* spi1_clk */
+ <1 RK_PB6 2 &pcfg_pull_none_drv_level_2>,
+ /* spi1_miso */
+ <1 RK_PC0 2 &pcfg_pull_none_drv_level_2>,
+ /* spi1_mosi */
+ <1 RK_PB7 2 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ spi1_csn0: spi1-csn0 {
+ rockchip,pins =
+ /* spi1_csn0 */
+ <1 RK_PC1 1 &pcfg_pull_none_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ spi1_csn1: spi1-csn1 {
+ rockchip,pins =
+ /* spi1_csn1 */
+ <1 RK_PC2 1 &pcfg_pull_none_drv_level_2>;
+ };
+ };
+
+ tsi0 {
+ /omit-if-no-ref/
+ tsi0_pins: tsi0-pins {
+ rockchip,pins =
+ /* tsi0_clkin */
+ <3 RK_PB2 3 &pcfg_pull_none>,
+ /* tsi0_d0 */
+ <3 RK_PB1 3 &pcfg_pull_none>,
+ /* tsi0_d1 */
+ <3 RK_PB5 3 &pcfg_pull_none>,
+ /* tsi0_d2 */
+ <3 RK_PB6 3 &pcfg_pull_none>,
+ /* tsi0_d3 */
+ <3 RK_PB7 3 &pcfg_pull_none>,
+ /* tsi0_d4 */
+ <3 RK_PA3 3 &pcfg_pull_none>,
+ /* tsi0_d5 */
+ <3 RK_PA2 3 &pcfg_pull_none>,
+ /* tsi0_d6 */
+ <3 RK_PA1 3 &pcfg_pull_none>,
+ /* tsi0_d7 */
+ <3 RK_PA0 3 &pcfg_pull_none>,
+ /* tsi0_fail */
+ <3 RK_PC0 3 &pcfg_pull_none>,
+ /* tsi0_sync */
+ <3 RK_PB4 3 &pcfg_pull_none>,
+ /* tsi0_valid */
+ <3 RK_PB3 3 &pcfg_pull_none>;
+ };
+ };
+
+ tsi1 {
+ /omit-if-no-ref/
+ tsi1_pins: tsi1-pins {
+ rockchip,pins =
+ /* tsi1_clkin */
+ <3 RK_PA5 3 &pcfg_pull_none>,
+ /* tsi1_d0 */
+ <3 RK_PA4 3 &pcfg_pull_none>,
+ /* tsi1_sync */
+ <3 RK_PA7 3 &pcfg_pull_none>,
+ /* tsi1_valid */
+ <3 RK_PA6 3 &pcfg_pull_none>;
+ };
+ };
+
+ uart0 {
+ /omit-if-no-ref/
+ uart0m0_xfer: uart0m0-xfer {
+ rockchip,pins =
+ /* uart0_rx_m0 */
+ <4 RK_PC7 1 &pcfg_pull_up>,
+ /* uart0_tx_m0 */
+ <4 RK_PD0 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart0m1_xfer: uart0m1-xfer {
+ rockchip,pins =
+ /* uart0_rx_m1 */
+ <2 RK_PA0 2 &pcfg_pull_up>,
+ /* uart0_tx_m1 */
+ <2 RK_PA1 2 &pcfg_pull_up>;
+ };
+ };
+
+ uart1 {
+ /omit-if-no-ref/
+ uart1m0_xfer: uart1m0-xfer {
+ rockchip,pins =
+ /* uart1_rx_m0 */
+ <4 RK_PA7 2 &pcfg_pull_up>,
+ /* uart1_tx_m0 */
+ <4 RK_PA6 2 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart1m1_xfer: uart1m1-xfer {
+ rockchip,pins =
+ /* uart1_rx_m1 */
+ <4 RK_PC6 2 &pcfg_pull_up>,
+ /* uart1_tx_m1 */
+ <4 RK_PC5 2 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart1_ctsn: uart1-ctsn {
+ rockchip,pins =
+ /* uart1_ctsn */
+ <4 RK_PA4 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart1_rtsn: uart1-rtsn {
+ rockchip,pins =
+ /* uart1_rtsn */
+ <4 RK_PA5 2 &pcfg_pull_none>;
+ };
+ };
+
+ uart2 {
+ /omit-if-no-ref/
+ uart2m0_xfer: uart2m0-xfer {
+ rockchip,pins =
+ /* uart2_rx_m0 */
+ <3 RK_PA0 1 &pcfg_pull_up>,
+ /* uart2_tx_m0 */
+ <3 RK_PA1 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart2m0_ctsn: uart2m0-ctsn {
+ rockchip,pins =
+ /* uart2m0_ctsn */
+ <3 RK_PA3 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart2m0_rtsn: uart2m0-rtsn {
+ rockchip,pins =
+ /* uart2m0_rtsn */
+ <3 RK_PA2 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart2m1_xfer: uart2m1-xfer {
+ rockchip,pins =
+ /* uart2_rx_m1 */
+ <1 RK_PB0 1 &pcfg_pull_up>,
+ /* uart2_tx_m1 */
+ <1 RK_PB1 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart2m1_ctsn: uart2m1-ctsn {
+ rockchip,pins =
+ /* uart2m1_ctsn */
+ <1 RK_PB3 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart2m1_rtsn: uart2m1-rtsn {
+ rockchip,pins =
+ /* uart2m1_rtsn */
+ <1 RK_PB2 1 &pcfg_pull_none>;
+ };
+ };
+
+ uart3 {
+ /omit-if-no-ref/
+ uart3m0_xfer: uart3m0-xfer {
+ rockchip,pins =
+ /* uart3_rx_m0 */
+ <4 RK_PB0 2 &pcfg_pull_up>,
+ /* uart3_tx_m0 */
+ <4 RK_PB1 2 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart3m1_xfer: uart3m1-xfer {
+ rockchip,pins =
+ /* uart3_rx_m1 */
+ <4 RK_PB7 3 &pcfg_pull_up>,
+ /* uart3_tx_m1 */
+ <4 RK_PC0 3 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart3_ctsn: uart3-ctsn {
+ rockchip,pins =
+ /* uart3_ctsn */
+ <4 RK_PA3 3 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart3_rtsn: uart3-rtsn {
+ rockchip,pins =
+ /* uart3_rtsn */
+ <4 RK_PA2 3 &pcfg_pull_none>;
+ };
+ };
+
+ uart4 {
+ /omit-if-no-ref/
+ uart4_xfer: uart4-xfer {
+ rockchip,pins =
+ /* uart4_rx */
+ <2 RK_PA2 3 &pcfg_pull_up>,
+ /* uart4_tx */
+ <2 RK_PA3 3 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart4_ctsn: uart4-ctsn {
+ rockchip,pins =
+ /* uart4_ctsn */
+ <2 RK_PA1 3 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart4_rtsn: uart4-rtsn {
+ rockchip,pins =
+ /* uart4_rtsn */
+ <2 RK_PA0 3 &pcfg_pull_none>;
+ };
+ };
+
+ uart5 {
+ /omit-if-no-ref/
+ uart5m0_xfer: uart5m0-xfer {
+ rockchip,pins =
+ /* uart5_rx_m0 */
+ <1 RK_PA2 2 &pcfg_pull_up>,
+ /* uart5_tx_m0 */
+ <1 RK_PA3 2 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart5m0_ctsn: uart5m0-ctsn {
+ rockchip,pins =
+ /* uart5m0_ctsn */
+ <1 RK_PA6 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart5m0_rtsn: uart5m0-rtsn {
+ rockchip,pins =
+ /* uart5m0_rtsn */
+ <1 RK_PA5 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart5m1_xfer: uart5m1-xfer {
+ rockchip,pins =
+ /* uart5_rx_m1 */
+ <1 RK_PD4 2 &pcfg_pull_up>,
+ /* uart5_tx_m1 */
+ <1 RK_PD7 2 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart5m1_ctsn: uart5m1-ctsn {
+ rockchip,pins =
+ /* uart5m1_ctsn */
+ <1 RK_PD3 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart5m1_rtsn: uart5m1-rtsn {
+ rockchip,pins =
+ /* uart5m1_rtsn */
+ <1 RK_PD2 2 &pcfg_pull_none>;
+ };
+ };
+
+ uart6 {
+ /omit-if-no-ref/
+ uart6m0_xfer: uart6m0-xfer {
+ rockchip,pins =
+ /* uart6_rx_m0 */
+ <3 RK_PA7 4 &pcfg_pull_up>,
+ /* uart6_tx_m0 */
+ <3 RK_PA6 4 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart6m1_xfer: uart6m1-xfer {
+ rockchip,pins =
+ /* uart6_rx_m1 */
+ <3 RK_PC3 4 &pcfg_pull_up>,
+ /* uart6_tx_m1 */
+ <3 RK_PC1 4 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart6_ctsn: uart6-ctsn {
+ rockchip,pins =
+ /* uart6_ctsn */
+ <3 RK_PA4 4 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart6_rtsn: uart6-rtsn {
+ rockchip,pins =
+ /* uart6_rtsn */
+ <3 RK_PA5 4 &pcfg_pull_none>;
+ };
+ };
+
+ uart7 {
+ /omit-if-no-ref/
+ uart7m0_xfer: uart7m0-xfer {
+ rockchip,pins =
+ /* uart7_rx_m0 */
+ <3 RK_PB3 4 &pcfg_pull_up>,
+ /* uart7_tx_m0 */
+ <3 RK_PB2 4 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart7m0_ctsn: uart7m0-ctsn {
+ rockchip,pins =
+ /* uart7m0_ctsn */
+ <3 RK_PB0 4 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart7m0_rtsn: uart7m0-rtsn {
+ rockchip,pins =
+ /* uart7m0_rtsn */
+ <3 RK_PB1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart7m1_xfer: uart7m1-xfer {
+ rockchip,pins =
+ /* uart7_rx_m1 */
+ <1 RK_PB3 4 &pcfg_pull_up>,
+ /* uart7_tx_m1 */
+ <1 RK_PB2 4 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart7m1_ctsn: uart7m1-ctsn {
+ rockchip,pins =
+ /* uart7m1_ctsn */
+ <1 RK_PB0 4 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart7m1_rtsn: uart7m1-rtsn {
+ rockchip,pins =
+ /* uart7m1_rtsn */
+ <1 RK_PB1 4 &pcfg_pull_none>;
+ };
+ };
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
index d2cdb63..57a446b 100644
--- a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
@@ -6,17 +6,150 @@
*/
/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
#include "rk3528.dtsi"
/ {
model = "Radxa E20C";
compatible = "radxa,e20c", "rockchip,rk3528";
+ aliases {
+ mmc0 = &sdhci;
+ };
+
chosen {
stdout-path = "serial0:1500000n8";
};
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ button-maskrom {
+ label = "MASKROM";
+ linux,code = <KEY_SETUP>;
+ press-threshold-microvolt = <0>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_key>;
+
+ button-user {
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
+ label = "USER";
+ linux,code = <BTN_1>;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&lan_led_g>, <&sys_led_g>, <&wan_led_g>;
+
+ led-lan {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_LAN;
+ gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "netdev";
+ };
+
+ led-sys {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "on";
+ function = LED_FUNCTION_HEARTBEAT;
+ gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-wan {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_WAN;
+ gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "netdev";
+ };
+ };
+
+ vcc_1v8: regulator-1v8-vcc {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ };
+
+ vcc_3v3: regulator-3v3-vcc {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_sys: regulator-5v0-vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+};
+
+&pinctrl {
+ gpio-keys {
+ user_key: user-key {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ leds {
+ lan_led_g: lan-led-g {
+ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ sys_led_g: sys-led-g {
+ rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wan_led_g: wan-led-g {
+ rockchip,pins = <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ no-sd;
+ no-sdio;
+ non-removable;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
};
&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0m0_xfer>;
status = "okay";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3528.dtsi b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
index e58faa9..26c3559 100644
--- a/dts/upstream/src/arm64/rockchip/rk3528.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
@@ -4,8 +4,12 @@
* Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
*/
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/clock/rockchip,rk3528-cru.h>
+#include <dt-bindings/reset/rockchip,rk3528-cru.h>
/ {
compatible = "rockchip,rk3528";
@@ -15,6 +19,11 @@
#size-cells = <2>;
aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
@@ -51,6 +60,7 @@
reg = <0x0>;
device_type = "cpu";
enable-method = "psci";
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
};
cpu1: cpu@1 {
@@ -58,6 +68,7 @@
reg = <0x1>;
device_type = "cpu";
enable-method = "psci";
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
};
cpu2: cpu@2 {
@@ -65,6 +76,7 @@
reg = <0x2>;
device_type = "cpu";
enable-method = "psci";
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
};
cpu3: cpu@3 {
@@ -72,14 +84,42 @@
reg = <0x3>;
device_type = "cpu";
enable-method = "psci";
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
};
};
+ firmware {
+ scmi: scmi {
+ compatible = "arm,scmi-smc";
+ arm,smc-id = <0x82000010>;
+ shmem = <&scmi_shmem>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+ };
+ };
+
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ scmi_shmem: shmem@10f000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x0010f000 0x0 0x100>;
+ no-map;
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@@ -95,6 +135,13 @@
#clock-cells = <0>;
};
+ gmac0_clk: clock-gmac50m {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ clock-output-names = "gmac0";
+ #clock-cells = <0>;
+ };
+
soc {
compatible = "simple-bus";
ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>;
@@ -114,10 +161,219 @@
#interrupt-cells = <3>;
};
+ qos_crypto_a: qos@ff200000 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff200000 0x0 0x20>;
+ };
+
+ qos_crypto_p: qos@ff200080 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff200080 0x0 0x20>;
+ };
+
+ qos_dcf: qos@ff200100 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff200100 0x0 0x20>;
+ };
+
+ qos_dft2apb: qos@ff200200 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff200200 0x0 0x20>;
+ };
+
+ qos_dma2ddr: qos@ff200280 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff200280 0x0 0x20>;
+ };
+
+ qos_dmac: qos@ff200300 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff200300 0x0 0x20>;
+ };
+
+ qos_keyreader: qos@ff200380 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff200380 0x0 0x20>;
+ };
+
+ qos_cpu: qos@ff210000 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff210000 0x0 0x20>;
+ };
+
+ qos_debug: qos@ff210080 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff210080 0x0 0x20>;
+ };
+
+ qos_gpu_m0: qos@ff220000 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff220000 0x0 0x20>;
+ };
+
+ qos_gpu_m1: qos@ff220080 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff220080 0x0 0x20>;
+ };
+
+ qos_pmu_mcu: qos@ff240000 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff240000 0x0 0x20>;
+ };
+
+ qos_rkvdec: qos@ff250000 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff250000 0x0 0x20>;
+ };
+
+ qos_rkvenc: qos@ff260000 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff260000 0x0 0x20>;
+ };
+
+ qos_gmac0: qos@ff270000 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff270000 0x0 0x20>;
+ };
+
+ qos_hdcp: qos@ff270080 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff270080 0x0 0x20>;
+ };
+
+ qos_jpegdec: qos@ff270100 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff270100 0x0 0x20>;
+ };
+
+ qos_rga2_m0ro: qos@ff270200 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff270200 0x0 0x20>;
+ };
+
+ qos_rga2_m0wo: qos@ff270280 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff270280 0x0 0x20>;
+ };
+
+ qos_sdmmc0: qos@ff270300 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff270300 0x0 0x20>;
+ };
+
+ qos_usb2host: qos@ff270380 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff270380 0x0 0x20>;
+ };
+
+ qos_vdpp: qos@ff270480 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff270480 0x0 0x20>;
+ };
+
+ qos_vop: qos@ff270500 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff270500 0x0 0x20>;
+ };
+
+ qos_emmc: qos@ff280000 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff280000 0x0 0x20>;
+ };
+
+ qos_fspi: qos@ff280080 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff280080 0x0 0x20>;
+ };
+
+ qos_gmac1: qos@ff280100 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff280100 0x0 0x20>;
+ };
+
+ qos_pcie: qos@ff280180 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff280180 0x0 0x20>;
+ };
+
+ qos_sdio0: qos@ff280200 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff280200 0x0 0x20>;
+ };
+
+ qos_sdio1: qos@ff280280 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff280280 0x0 0x20>;
+ };
+
+ qos_tsp: qos@ff280300 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff280300 0x0 0x20>;
+ };
+
+ qos_usb3otg: qos@ff280380 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff280380 0x0 0x20>;
+ };
+
+ qos_vpu: qos@ff280400 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff280400 0x0 0x20>;
+ };
+
+ cru: clock-controller@ff4a0000 {
+ compatible = "rockchip,rk3528-cru";
+ reg = <0x0 0xff4a0000 0x0 0x30000>;
+ assigned-clocks =
+ <&cru XIN_OSC0_DIV>, <&cru PLL_GPLL>,
+ <&cru PLL_PPLL>, <&cru PLL_CPLL>,
+ <&cru ARMCLK>, <&cru CLK_MATRIX_250M_SRC>,
+ <&cru CLK_MATRIX_500M_SRC>,
+ <&cru CLK_MATRIX_50M_SRC>,
+ <&cru CLK_MATRIX_100M_SRC>,
+ <&cru CLK_MATRIX_150M_SRC>,
+ <&cru CLK_MATRIX_200M_SRC>,
+ <&cru CLK_MATRIX_300M_SRC>,
+ <&cru CLK_MATRIX_339M_SRC>,
+ <&cru CLK_MATRIX_400M_SRC>,
+ <&cru CLK_MATRIX_600M_SRC>,
+ <&cru CLK_PPLL_50M_MATRIX>,
+ <&cru CLK_PPLL_100M_MATRIX>,
+ <&cru CLK_PPLL_125M_MATRIX>,
+ <&cru ACLK_BUS_VOPGL_ROOT>;
+ assigned-clock-rates =
+ <32768>, <1188000000>,
+ <1000000000>, <996000000>,
+ <408000000>, <250000000>,
+ <500000000>,
+ <50000000>,
+ <100000000>,
+ <150000000>,
+ <200000000>,
+ <300000000>,
+ <340000000>,
+ <400000000>,
+ <600000000>,
+ <50000000>,
+ <100000000>,
+ <125000000>,
+ <500000000>;
+ clocks = <&xin24m>, <&gmac0_clk>;
+ clock-names = "xin24m", "gmac0";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ ioc_grf: syscon@ff540000 {
+ compatible = "rockchip,rk3528-ioc-grf", "syscon";
+ reg = <0x0 0xff540000 0x0 0x40000>;
+ };
+
uart0: serial@ff9f0000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xff9f0000 0x0 0x100>;
- clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -127,6 +383,8 @@
uart1: serial@ff9f8000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xff9f8000 0x0 0x100>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -136,6 +394,8 @@
uart2: serial@ffa00000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xffa00000 0x0 0x100>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -144,6 +404,8 @@
uart3: serial@ffa08000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+ clock-names = "baudclk", "apb_pclk";
reg = <0x0 0xffa08000 0x0 0x100>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -153,6 +415,8 @@
uart4: serial@ffa10000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xffa10000 0x0 0x100>;
+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -162,6 +426,8 @@
uart5: serial@ffa18000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xffa18000 0x0 0x100>;
+ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -171,6 +437,8 @@
uart6: serial@ffa20000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xffa20000 0x0 0x100>;
+ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -180,10 +448,118 @@
uart7: serial@ffa28000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xffa28000 0x0 0x100>;
+ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
+
+ saradc: adc@ffae0000 {
+ compatible = "rockchip,rk3528-saradc";
+ reg = <0x0 0xffae0000 0x0 0x10000>;
+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&cru SRST_P_SARADC>;
+ reset-names = "saradc-apb";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
+ sdhci: mmc@ffbf0000 {
+ compatible = "rockchip,rk3528-dwcmshc",
+ "rockchip,rk3588-dwcmshc";
+ reg = <0x0 0xffbf0000 0x0 0x10000>;
+ assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>,
+ <&cru CCLK_SRC_EMMC>;
+ assigned-clock-rates = <200000000>, <24000000>,
+ <200000000>;
+ clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>,
+ <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
+ <&cru TCLK_EMMC>;
+ clock-names = "core", "bus", "axi", "block", "timer";
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <200000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>,
+ <&emmc_strb>;
+ resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
+ <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
+ <&cru SRST_T_EMMC>;
+ reset-names = "core", "bus", "axi", "block", "timer";
+ status = "disabled";
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3528-pinctrl";
+ rockchip,grf = <&ioc_grf>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio0: gpio@ff610000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xff610000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@ffaf0000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffaf0000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@ffb00000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffb00000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@ffb10000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffb10000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@ffb20000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffb20000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 128 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
};
};
+
+#include "rk3528-pinctrl.dtsi"
diff --git a/dts/upstream/src/arm64/rockchip/rk3576-roc-pc.dts b/dts/upstream/src/arm64/rockchip/rk3576-roc-pc.dts
new file mode 100644
index 0000000..612b7bb
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3576-roc-pc.dts
@@ -0,0 +1,736 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Firefly Technology Co. Ltd
+ * Copyright (c) 2024 Heiko Stuebner <heiko@sntech.de>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/usb/pd.h>
+#include "rk3576.dtsi"
+
+/ {
+ model = "Firefly ROC-RK3576-PC";
+ compatible = "firefly,roc-rk3576-pc", "rockchip,rk3576";
+
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ };
+
+ chosen {
+ stdout-path = "serial0:1500000n8";
+ };
+
+ adc-keys-0 {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ button-maskrom {
+ label = "Maskrom";
+ linux,code = <KEY_SETUP>;
+ press-threshold-microvolt = <17000>;
+ };
+ };
+
+ adc-keys-1 {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ button-recovery {
+ label = "Recovery";
+ linux,code = <KEY_VENDOR>;
+ press-threshold-microvolt = <17000>;
+ };
+ };
+
+ vbus5v0_typec: regulator-vbus5v0-typec {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_otg0_pwren_h>;
+ regulator-name = "vbus5v0_typec";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_device_s0>;
+ };
+
+ vcc12v_dcin: regulator-vcc12v-dcin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc1v2_ufs_vccq_s0: regulator-vcc1v2-ufs-vccq-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v2_ufs_vccq_s0";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ vin-supply = <&vcc5v0_sys_s5>;
+ };
+
+ vcc1v8_ufs_vccq2_s0: regulator-vcc1v8-ufs-vccq2-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8_ufs_vccq2_s0";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_1v8_s3>;
+ };
+
+ vcc3v3_pcie: regulator-vcc3v3-pcie {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pwren_h>;
+ regulator-name = "vcc3v3_pcie";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc3v3_rtc_s5: regulator-vcc3v3-rtc-s5 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_rtc_s5";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys_s5>;
+ };
+
+ vcc5v0_device_s0: regulator-vcc5v0-device-s0 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5vd_en>;
+ regulator-name = "vcc5v0_device";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_sys_s5: regulator-vcc5v0-sys-s5 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_usb20_host1: regulator-vcc5v0-usb20-host1 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb3_host_pwren_h>;
+ regulator-name = "vcc5v0_host1";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_device_s0>;
+ };
+
+ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc5v0_sys_s5>;
+ };
+
+ vcc_1v8_s0: regulator-vcc-1v8-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v8_s0";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_1v8_s3>;
+ };
+
+ vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_2v0_pldo_s3";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ vin-supply = <&vcc5v0_sys_s5>;
+ };
+
+ vcc_3v3_s0: regulator-vcc-3v3-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3_s0";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+ vcc_ufs_s0: regulator-vcc-ufs-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_ufs_s0";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys_s5>;
+ };
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big_s0>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_big_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big_s0>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu_big_s0>;
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu_s0>;
+ status = "okay";
+};
+
+&gmac0 {
+ clock_in_out = "output";
+ pinctrl-names = "default";
+ pinctrl-0 = <ð0m0_miim
+ ð0m0_tx_bus2
+ ð0m0_rx_bus2
+ ð0m0_rgmii_clk
+ ð0m0_rgmii_bus
+ ðm0_clk0_25m_out>;
+ /* Use rgmii-rxid mode to disable rx delay inside Soc */
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&rgmii_phy0>;
+ tx_delay = <0x21>;
+ status = "okay";
+};
+
+&mdio0 {
+ status = "okay";
+
+ rgmii_phy0: phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ clocks = <&cru REFCLKO25M_GMAC0_OUT>;
+ /* Reset time is 20ms, 100ms for rtl8211f */
+ reset-delay-us = <20000>;
+ reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
+ reset-post-delay-us = <100000>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ pmic@23 {
+ compatible = "rockchip,rk806";
+ reg = <0x23>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+ system-power-controller;
+
+ vcc1-supply = <&vcc5v0_sys_s5>;
+ vcc2-supply = <&vcc5v0_sys_s5>;
+ vcc3-supply = <&vcc5v0_sys_s5>;
+ vcc4-supply = <&vcc5v0_sys_s5>;
+ vcc5-supply = <&vcc5v0_sys_s5>;
+ vcc6-supply = <&vcc5v0_sys_s5>;
+ vcc7-supply = <&vcc5v0_sys_s5>;
+ vcc8-supply = <&vcc5v0_sys_s5>;
+ vcc9-supply = <&vcc5v0_sys_s5>;
+ vcc10-supply = <&vcc5v0_sys_s5>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc5v0_sys_s5>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcc5v0_sys_s5>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs1_slp: dvs1-slp-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun1";
+ };
+
+ rk806_dvs1_pwrdn: dvs1-pwrdn-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun2";
+ };
+
+ rk806_dvs1_rst: dvs1-rst-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun3";
+ };
+
+ rk806_dvs2_slp: dvs2-slp-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun1";
+ };
+
+ rk806_dvs2_pwrdn: dvs2-pwrdn-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun2";
+ };
+
+ rk806_dvs2_rst: dvs2-rst-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun3";
+ };
+
+ rk806_dvs2_dvs: dvs2-dvs-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun4";
+ };
+
+ rk806_dvs2_gpio: dvs2-gpio-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun5";
+ };
+
+ rk806_dvs3_slp: dvs3-slp-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun1";
+ };
+
+ rk806_dvs3_pwrdn: dvs3-pwrdn-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun2";
+ };
+
+ rk806_dvs3_rst: dvs3-rst-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun3";
+ };
+
+ rk806_dvs3_dvs: dvs3-dvs-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun4";
+ };
+
+ rk806_dvs3_gpio: dvs3-gpio-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun5";
+ };
+
+ regulators {
+ vdd_cpu_big_s0: dcdc-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_big_s0";
+ regulator-enable-ramp-delay = <400>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_npu_s0: dcdc-reg2 {
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_npu_s0";
+ regulator-enable-ramp-delay = <400>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: dcdc-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_lit_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_3v3_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vdd_gpu_s0: dcdc-reg5 {
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_gpu_s0";
+ regulator-enable-ramp-delay = <400>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vddq_ddr_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_logic_s0: dcdc-reg7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <800000>;
+ regulator-name = "vdd_logic_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: dcdc-reg8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vdd2_ddr_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg10 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vdd_ddr_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca_1v8_s0: pldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca_1v8_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pldo2_s0: pldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca1v8_pldo2_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_1v2_s0: pldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vdda_1v2_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca_3v3_s0: pldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcca_3v3_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_sd_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pldo6_s3: pldo-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca1v8_pldo6_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "vdd_0v75_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdda_ddr_pll_s0: nldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdda_ddr_pll_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v75_hdmi_s0: nldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <837500>;
+ regulator-max-microvolt = <837500>;
+ regulator-name = "vdda0v75_hdmi_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v85_s0: nldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdda_0v85_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v75_s0: nldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "vdda_0v75_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ /* pc9202 watchdog@3c with enable-gpio gpio0-c3 */
+
+ /* hnyetek,husb311 typec-portc@4e */
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-output-names = "hym8563";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtc_int_l>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>;
+ wakeup-source;
+ };
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8_s0>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ max-frequency = <200000000>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ full-pwr-cycle-in-suspend;
+ status = "okay";
+};
+
+&sdmmc {
+ max-frequency = <200000000>;
+ no-sdio;
+ no-mmc;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ sd-uhs-sdr104;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&pinctrl {
+ hym8563 {
+ rtc_int_l: rtc-int-l {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ power {
+ vcc5vd_en: vcc5vd-en {
+ rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie_pwren_h: pcie-pwren-h {
+ rockchip,pins = <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ hub_reset_h: hub-reset-h {
+ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usb3_host_pwren_h: usb3-host-pwren-h {
+ rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usb_otg0_pwren_h: usb-otg0-pwren-h {
+ rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usbc0_int_l: usbc0-int-l {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ watchdog {
+ wd_en: wd-en {
+ rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0m0_xfer>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4m1_xfer &uart4m1_ctsn>;
+ status = "okay";
+};
+
+/* On the extension pin header */
+&uart6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart6m3_xfer>;
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3576.dtsi b/dts/upstream/src/arm64/rockchip/rk3576.dtsi
index 4dde954..29b4779 100644
--- a/dts/upstream/src/arm64/rockchip/rk3576.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3576.dtsi
@@ -1260,6 +1260,45 @@
status = "disabled";
};
+ otp: otp@2a580000 {
+ compatible = "rockchip,rk3576-otp";
+ reg = <0x0 0x2a580000 0x0 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
+ <&cru CLK_OTP_PHY_G>;
+ clock-names = "otp", "apb_pclk", "phy";
+ resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>;
+ reset-names = "otp", "apb";
+
+ /* Data cells */
+ cpu_code: cpu-code@2 {
+ reg = <0x02 0x2>;
+ };
+ otp_cpu_version: cpu-version@5 {
+ reg = <0x05 0x1>;
+ bits = <3 3>;
+ };
+ otp_id: id@a {
+ reg = <0x0a 0x10>;
+ };
+ cpub_leakage: cpub-leakage@1e {
+ reg = <0x1e 0x1>;
+ };
+ cpul_leakage: cpul-leakage@1f {
+ reg = <0x1f 0x1>;
+ };
+ npu_leakage: npu-leakage@20 {
+ reg = <0x20 0x1>;
+ };
+ gpu_leakage: gpu-leakage@21 {
+ reg = <0x21 0x1>;
+ };
+ log_leakage: log-leakage@22 {
+ reg = <0x22 0x1>;
+ };
+ };
+
gic: interrupt-controller@2a701000 {
compatible = "arm,gic-400";
reg = <0x0 0x2a701000 0 0x10000>,
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi
index c3abdfb..2623afa 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi
@@ -1921,6 +1921,14 @@
status = "disabled";
};
+ rng@fe378000 {
+ compatible = "rockchip,rk3588-rng";
+ reg = <0x0 0xfe378000 0x0 0x200>;
+ interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>;
+ resets = <&scmi_reset 48>;
+ };
+
i2s0_8ch: i2s@fe470000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfe470000 0x0 0x1000>;
diff --git a/dts/upstream/src/mips/Makefile b/dts/upstream/src/mips/Makefile
new file mode 100644
index 0000000..9a8f6aa
--- /dev/null
+++ b/dts/upstream/src/mips/Makefile
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+include $(srctree)/scripts/Makefile.dts
+
+targets += $(dtb-y)
+
+# Add any required device tree compiler flags here
+DTC_FLAGS += -a 0x8
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+ @:
+
+clean-files := */*.dtb */*.dtbo
diff --git a/env/Kconfig b/env/Kconfig
index 4438f0b..9507aee 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -485,7 +485,7 @@
string "Device and partition for where to store the environemt in FAT"
depends on ENV_IS_IN_FAT
default "0:1" if TI_COMMON_CMD_OPTIONS
- default "0:auto" if ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET
+ default "0:auto" if ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2
default ":auto" if ARCH_SUNXI
default "0" if ARCH_AT91
help
diff --git a/env/common.c b/env/common.c
index a58955a..8612258 100644
--- a/env/common.c
+++ b/env/common.c
@@ -16,6 +16,7 @@
#include <asm/global_data.h>
#include <linux/printk.h>
#include <linux/stddef.h>
+#include <mapmem.h>
#include <search.h>
#include <errno.h>
#include <malloc.h>
@@ -368,6 +369,18 @@
return env_get_from_linear(default_environment, name, buf, len);
}
+static int env_update_fdt_addr_from_bloblist(void)
+{
+ /*
+ * fdt_addr is by default used by booti, bootm and bootefi,
+ * thus set it to point to the fdt embedded in a bloblist if it exists.
+ */
+ if (!CONFIG_IS_ENABLED(BLOBLIST) || gd->fdt_src != FDTSRC_BLOBLIST)
+ return 0;
+
+ return env_set_hex("fdt_addr", (uintptr_t)map_to_sysmem(gd->fdt_blob));
+}
+
void env_set_default(const char *s, int flags)
{
if (s) {
@@ -392,6 +405,10 @@
gd->flags |= GD_FLG_ENV_READY;
gd->flags |= GD_FLG_ENV_DEFAULT;
+
+ /* This has to be done after GD_FLG_ENV_READY is set */
+ if (env_update_fdt_addr_from_bloblist())
+ pr_err("Failed to set fdt_addr to point at DTB\n");
}
/* [re]set individual variables to their value in the default environment */
@@ -437,7 +454,9 @@
if (himport_r(&env_htab, (char *)ep->data, ENV_SIZE, '\0', flags, 0,
0, NULL)) {
gd->flags |= GD_FLG_ENV_READY;
- return 0;
+
+ /* This has to be done after GD_FLG_ENV_READY is set */
+ return env_update_fdt_addr_from_bloblist();
}
pr_err("Cannot import environment: errno = %d\n", errno);
diff --git a/env/mmc.c b/env/mmc.c
index 2ef15fb..8848371 100644
--- a/env/mmc.c
+++ b/env/mmc.c
@@ -553,7 +553,7 @@
static int env_mmc_load(void)
{
- if (IS_ENABLED(CONFIG_ENV_IS_EMBEDDED))
+ if (IS_ENABLED(ENV_IS_EMBEDDED))
return 0;
else if (IS_ENABLED(CONFIG_SYS_REDUNDAND_ENVIRONMENT))
return env_mmc_load_redundant();
diff --git a/fs/exfat/io.c b/fs/exfat/io.c
index 81e8282..c56f567 100644
--- a/fs/exfat/io.c
+++ b/fs/exfat/io.c
@@ -597,15 +597,13 @@
}
#ifdef __UBOOT__
+#define PATH_MAX FS_DIRENT_NAME_LEN
+
struct exfat_dir_stream {
+ char dirname[PATH_MAX];
struct fs_dir_stream fs_dirs;
struct fs_dirent dirent;
-
- struct exfat_node* node;
- struct exfat_iterator it;
- /* State tracker flags for emulated . and .. dirents */
- bool dot;
- bool dotdot;
+ int offset;
};
int exfat_fs_probe(struct blk_desc *fs_dev_desc,
@@ -626,8 +624,6 @@
return ret;
}
-#define PATH_MAX FS_DIRENT_NAME_LEN
-
/* Adapted from uclibc 1.0.35 */
static char *exfat_realpath(const char *path, char got_path[])
{
@@ -721,31 +717,31 @@
int exfat_fs_opendir(const char *filename, struct fs_dir_stream **dirsp)
{
struct exfat_dir_stream *dirs;
+ struct exfat_node *dnode;
int err;
- dirs = calloc(1, sizeof(*dirs));
- if (!dirs)
- return -ENOMEM;
-
- err = exfat_lookup_realpath(&ctxt.ef, &dirs->node, filename);
+ err = exfat_lookup_realpath(&ctxt.ef, &dnode, filename);
if (err)
- goto err_out;
+ return err;
- if (!(dirs->node->attrib & EXFAT_ATTRIB_DIR)) {
+ if (!(dnode->attrib & EXFAT_ATTRIB_DIR))
err = -ENOTDIR;
- goto err_out;
- }
- err = exfat_opendir(&ctxt.ef, dirs->node, &dirs->it);
+ exfat_put_node(&ctxt.ef, dnode);
+
if (err)
- goto err_out;
+ return err;
+
+ dirs = calloc(1, sizeof(*dirs));
+ if (!dirs)
+ return -ENOMEM;
+
+ strcpy(dirs->dirname, filename);
+ dirs->offset = -1;
*dirsp = &dirs->fs_dirs;
return 0;
-err_out:
- free(dirs);
- return err;
}
int exfat_fs_readdir(struct fs_dir_stream *fs_dirs, struct fs_dirent **dentp)
@@ -753,50 +749,77 @@
struct exfat_dir_stream *dirs =
container_of(fs_dirs, struct exfat_dir_stream, fs_dirs);
struct fs_dirent *dent = &dirs->dirent;
- struct exfat_node* node;
+ struct exfat_node *dnode, *node;
+ struct exfat_iterator it;
+ int offset = 0;
+ int err;
+
+ err = exfat_lookup_realpath(&ctxt.ef, &dnode, dirs->dirname);
+ if (err)
+ return err;
+
+ if (!(dnode->attrib & EXFAT_ATTRIB_DIR)) {
+ err = -ENOTDIR;
+ goto err_out;
+ }
/* Emulate current directory ./ */
- if (!dirs->dot) {
- dirs->dot = true;
+ if (dirs->offset == -1) {
+ dirs->offset++;
snprintf(dent->name, FS_DIRENT_NAME_LEN, ".");
dent->type = FS_DT_DIR;
*dentp = dent;
- return 0;
+ goto err_out;
}
/* Emulate parent directory ../ */
- if (!dirs->dotdot) {
- dirs->dotdot = true;
+ if (dirs->offset == 0) {
+ dirs->offset++;
snprintf(dent->name, FS_DIRENT_NAME_LEN, "..");
dent->type = FS_DT_DIR;
*dentp = dent;
- return 0;
+ goto err_out;
}
+ err = exfat_opendir(&ctxt.ef, dnode, &it);
+ if (err)
+ goto err_out;
+
+ *dentp = NULL;
+
/* Read actual directory content */
- node = exfat_readdir(&dirs->it);
- if (!node) { /* No more content, reset . and .. emulation */
- dirs->dot = false;
- dirs->dotdot = false;
- return 1;
- }
+ while ((node = exfat_readdir(&it))) {
+ if (dirs->offset != ++offset) {
+ exfat_put_node(&ctxt.ef, node);
+ continue;
+ }
- exfat_get_name(node, dent->name);
- if (node->attrib & EXFAT_ATTRIB_DIR) {
- dent->type = FS_DT_DIR;
- } else {
- dent->type = FS_DT_REG;
- dent->size = node->size;
+ exfat_get_name(node, dent->name);
+ if (node->attrib & EXFAT_ATTRIB_DIR) {
+ dent->type = FS_DT_DIR;
+ } else {
+ dent->type = FS_DT_REG;
+ dent->size = node->size;
+ }
+ exfat_put_node(&ctxt.ef, node);
+ *dentp = dent;
+ dirs->offset++;
+ break;
}
- *dentp = dent;
+ exfat_closedir(&ctxt.ef, &it);
- return 0;
+err_out:
+ exfat_put_node(&ctxt.ef, dnode);
+ return err;
}
void exfat_fs_closedir(struct fs_dir_stream *fs_dirs)
{
- free(fs_dirs);
+ struct exfat_dir_stream *dirs =
+ container_of(fs_dirs, struct exfat_dir_stream, fs_dirs);
+
+ free(dirs);
}
int exfat_fs_ls(const char *dirname)
@@ -852,11 +875,11 @@
err = exfat_lookup_realpath(&ctxt.ef, &node, filename);
if (err)
- return err;
+ return 0;
exfat_put_node(&ctxt.ef, node);
- return 0;
+ return 1;
}
int exfat_fs_size(const char *filename, loff_t *size)
@@ -898,9 +921,7 @@
*actread = sz;
- exfat_put_node(&ctxt.ef, node);
-
- return exfat_flush_node(&ctxt.ef, node);
+ err = exfat_flush_node(&ctxt.ef, node);
exit:
exfat_put_node(&ctxt.ef, node);
return err;
@@ -992,6 +1013,11 @@
return err;
}
+int exfat_fs_rename(const char *old_path, const char *new_path)
+{
+ return exfat_rename(&ctxt.ef, old_path, new_path);
+}
+
void exfat_fs_close(void)
{
exfat_unmount(&ctxt.ef);
diff --git a/fs/exfat/lookup.c b/fs/exfat/lookup.c
index 9867aab..1d9aae9 100644
--- a/fs/exfat/lookup.c
+++ b/fs/exfat/lookup.c
@@ -218,8 +218,9 @@
exfat_put_node(ef, *parent);
*parent = *node;
}
+#ifndef __UBOOT__
exfat_bug("impossible");
-#ifdef __UBOOT__
+#else
return 0;
#endif
}
diff --git a/fs/fat/Makefile b/fs/fat/Makefile
index 7414b36..3e73904 100644
--- a/fs/fat/Makefile
+++ b/fs/fat/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_$(XPL_)FS_FAT) = fat.o
-obj-$(CONFIG_$(XPL_)FAT_WRITE) = fat_write.o
+obj-$(CONFIG_$(PHASE_)FS_FAT) = fat.o
+obj-$(CONFIG_$(PHASE_)FAT_WRITE) = fat_write.o
diff --git a/fs/fs.c b/fs/fs.c
index 0b62217..1f36872 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -401,6 +401,7 @@
.ln = fs_ln_unsupported,
.unlink = exfat_fs_unlink,
.mkdir = exfat_fs_mkdir,
+ .rename = exfat_fs_rename,
},
#endif
{
diff --git a/fs/squashfs/Makefile b/fs/squashfs/Makefile
index 0772e1a..c71c9d4 100644
--- a/fs/squashfs/Makefile
+++ b/fs/squashfs/Makefile
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_$(XPL_)FS_SQUASHFS) = sqfs.o \
+obj-$(CONFIG_$(PHASE_)FS_SQUASHFS) = sqfs.o \
sqfs_inode.o \
sqfs_dir.o \
sqfs_decompressor.o
diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c
index 7c36468..2dcdd60 100644
--- a/fs/squashfs/sqfs.c
+++ b/fs/squashfs/sqfs.c
@@ -949,7 +949,7 @@
goto out;
}
- token_list = malloc(token_count * sizeof(char *));
+ token_list = calloc(token_count, sizeof(char *));
if (!token_list) {
ret = -EINVAL;
goto out;
@@ -987,9 +987,11 @@
*dirsp = (struct fs_dir_stream *)dirs;
out:
- for (j = 0; j < token_count; j++)
- free(token_list[j]);
- free(token_list);
+ if (token_list) {
+ for (j = 0; j < token_count; j++)
+ free(token_list[j]);
+ free(token_list);
+ }
free(pos_list);
free(path);
if (ret) {
diff --git a/include/ahci.h b/include/ahci.h
index d4f0f3c..eb05cc6 100644
--- a/include/ahci.h
+++ b/include/ahci.h
@@ -137,8 +137,8 @@
void __iomem *port_mmio;
struct ahci_cmd_hdr *cmd_slot;
struct ahci_sg *cmd_tbl_sg;
- ulong cmd_tbl;
- u32 rx_fis;
+ void *cmd_tbl;
+ void *rx_fis;
};
/**
diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h
index 024b1ad..d597879 100644
--- a/include/asm-generic/sections.h
+++ b/include/asm-generic/sections.h
@@ -28,6 +28,8 @@
extern char __efi_helloworld_end[];
extern char __efi_var_file_begin[];
extern char __efi_var_file_end[];
+extern char __efi_capsule_sig_begin[];
+extern char __efi_capsule_sig_end[];
/* Private data used by of-platdata devices/uclasses */
extern char __priv_data_start[], __priv_data_end[];
diff --git a/include/axp221.h b/include/axp221.h
index 32b988f..8a4a3cc 100644
--- a/include/axp221.h
+++ b/include/axp221.h
@@ -53,10 +53,6 @@
#ifdef CONFIG_AXP221_POWER
#define AXP_POWER_STATUS 0x00
#define AXP_POWER_STATUS_ALDO_IN BIT(0)
-#define AXP_VBUS_IPSOUT 0x30
-#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2)
-#define AXP_MISC_CTRL 0x8f
-#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4)
#define AXP_GPIO0_CTRL 0x90
#define AXP_GPIO1_CTRL 0x92
#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */
diff --git a/include/axp809.h b/include/axp809.h
index 71a7cb2..3bd71b3 100644
--- a/include/axp809.h
+++ b/include/axp809.h
@@ -47,10 +47,6 @@
#ifdef CONFIG_AXP809_POWER
#define AXP_POWER_STATUS 0x00
#define AXP_POWER_STATUS_ALDO_IN BIT(0)
-#define AXP_VBUS_IPSOUT 0x30
-#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2)
-#define AXP_MISC_CTRL 0x8f
-#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4)
#define AXP_GPIO0_CTRL 0x90
#define AXP_GPIO1_CTRL 0x92
#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */
diff --git a/include/axp818.h b/include/axp818.h
index 08ac35d..b3a9686 100644
--- a/include/axp818.h
+++ b/include/axp818.h
@@ -61,10 +61,6 @@
#ifdef CONFIG_AXP818_POWER
#define AXP_POWER_STATUS 0x00
#define AXP_POWER_STATUS_ALDO_IN BIT(0)
-#define AXP_VBUS_IPSOUT 0x30
-#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2)
-#define AXP_MISC_CTRL 0x8f
-#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4)
#define AXP_GPIO0_CTRL 0x90
#define AXP_GPIO1_CTRL 0x92
#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 19d3c72..cf43fc0 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -138,11 +138,10 @@
"setenv fdtfile am335x-evm.dtb; fi; " \
"if test $board_name = A335X_SK; then " \
"setenv fdtfile am335x-evmsk.dtb; fi; " \
- "if test $board_name = A335_ICE; then " \
- "setenv fdtfile am335x-icev2.dtb; " \
- "if test $ice_mii = mii; then " \
- "setenv pxe_label_override Pruss; fi;" \
- "fi; " \
+ "if test $board_name = A335_ICE && test $ice_mii = rmii; then " \
+ "setenv fdtfile am335x-icev2.dtb; fi; " \
+ "if test $board_name = A335_ICE && test $ice_mii = mii; then " \
+ "setenv fdtfile am335x-icev2-prueth.dtb; fi; " \
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine device tree to use; fi; \0" \
"init_console=" \
diff --git a/include/configs/amd_versal2.h b/include/configs/amd_versal2.h
index 6a40bbd..1ade6ad 100644
--- a/include/configs/amd_versal2.h
+++ b/include/configs/amd_versal2.h
@@ -105,6 +105,14 @@
#define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \
"jtag "
+#define BOOT_TARGET_DEVICES_UFS(func) func(UFS, ufs, 0)
+
+#define BOOTENV_DEV_UFS(devtypeu, devtypel, instance) \
+ "bootcmd_" #devtypel "=" #devtypel " init " #instance "; scsi scan;\0"
+
+#define BOOTENV_DEV_NAME_UFS(devtypeu, devtypel, instance) \
+ "ufs "
+
#define BOOT_TARGET_DEVICES_DFU_USB(func) func(DFU_USB, dfu_usb, 0)
#define BOOTENV_DEV_DFU_USB(devtypeu, devtypel, instance) \
@@ -117,11 +125,19 @@
#define BOOTENV_DEV_NAME_DFU_USB(devtypeu, devtypel, instance) \
""
+#if defined(CONFIG_USB_STORAGE)
+#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) func(USB, usb, 1)
+#else
+#define BOOT_TARGET_DEVICES_USB(func)
+#endif
+
#define BOOT_TARGET_DEVICES(func) \
BOOT_TARGET_DEVICES_JTAG(func) \
BOOT_TARGET_DEVICES_MMC(func) \
+ BOOT_TARGET_DEVICES_UFS(func) \
BOOT_TARGET_DEVICES_XSPI(func) \
BOOT_TARGET_DEVICES_DFU_USB(func) \
+ BOOT_TARGET_DEVICES_USB(func) \
BOOT_TARGET_DEVICES_PXE(func) \
BOOT_TARGET_DEVICES_DHCP(func)
diff --git a/include/configs/anbernic-rgxx3-rk3566.h b/include/configs/anbernic-rgxx3-rk3566.h
index 3c4ea4e..3d9e05a 100644
--- a/include/configs/anbernic-rgxx3-rk3566.h
+++ b/include/configs/anbernic-rgxx3-rk3566.h
@@ -3,10 +3,10 @@
#ifndef __ANBERNIC_RGXX3_RK3566_H
#define __ANBERNIC_RGXX3_RK3566_H
-#include <configs/rk3568_common.h>
-
#define ROCKCHIP_DEVICE_SETTINGS \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
+#include <configs/rk3568_common.h>
+
#endif
diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h
index 4c690a1..dbb9881 100644
--- a/include/configs/apalis-tk1.h
+++ b/include/configs/apalis-tk1.h
@@ -12,9 +12,6 @@
#include "tegra124-common.h"
-/* Board-specific serial config */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-
#define FDT_MODULE "apalis-v1.2"
#define FDT_MODULE_V1_0 "apalis"
diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h
deleted file mode 100644
index 87a679e..0000000
--- a/include/configs/apalis_t30.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2014-2016 Marcel Ziswiler
- *
- * Configuration settings for the Toradex Apalis T30 modules.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/sizes.h>
-
-#include "tegra30-common.h"
-
-/*
- * Board-specific serial config
- *
- * Apalis UART1: NVIDIA UARTA
- * Apalis UART2: NVIDIA UARTD
- * Apalis UART3: NVIDIA UARTB
- * Apalis UART4: NVIDIA UARTC
- */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/beaver.h b/include/configs/beaver.h
deleted file mode 100644
index e622b71..0000000
--- a/include/configs/beaver.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/sizes.h>
-
-#include "tegra30-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "NVIDIA Beaver"
-
-/* Board-specific serial config */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/brzynq.h b/include/configs/brzynq.h
new file mode 100644
index 0000000..e2ebb2f
--- /dev/null
+++ b/include/configs/brzynq.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Config file for BR Zynq board
+ *
+ * Copyright (C) 2024
+ * B&R Industrial Automation GmbH - http://www.br-automation.com/
+ */
+
+#ifndef __CONFIG_BRZYNQ_H__
+#define __CONFIG_BRZYNQ_H__
+
+/* Increase PHY_ANEG_TIMEOUT since the FPGA needs some setup time */
+#if IS_ENABLED(CONFIG_SPL_FPGA)
+#define PHY_ANEG_TIMEOUT 8000
+#endif
+
+/* Use top mapped SRAM */
+#define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000
+#define CFG_SYS_INIT_RAM_SIZE 0x2000
+
+#endif /* __CONFIG_BRZYNQ_H__ */
diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h
index 4d95f3f..7120a44 100644
--- a/include/configs/capricorn-common.h
+++ b/include/configs/capricorn-common.h
@@ -10,8 +10,6 @@
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-#include "siemens-env-common.h"
-
/* SPL config */
#ifdef CONFIG_XPL_BUILD
#define CFG_MALLOC_F_ADDR 0x00120000
@@ -36,57 +34,9 @@
#define AHAB_ENV "sec_boot=no\0"
#endif
-#define MFG_ENV_SETTINGS_DEFAULT \
- "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
- "rdinit=/linuxrc " \
- "clk_ignore_unused "\
- "\0" \
- "kboot=booti\0"\
- "bootcmd_mfg=run mfgtool_args;" \
- "if iminfo ${initrd_addr}; then " \
- "if test ${tee} = yes; then " \
- "bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; " \
- "else " \
- "booti ${loadaddr} ${initrd_addr} ${fdt_addr}; " \
- "fi; " \
- "else " \
- "echo \"Run fastboot ...\"; fastboot 0; " \
- "fi;\0"
-
-/* Boot M4 */
-#define M4_BOOT_ENV \
- "m4_0_image=m4_0.bin\0" \
- "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} " \
- "${loadaddr} ${m4_0_image}\0" \
- "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
-
-#define CFG_MFG_ENV_SETTINGS \
- MFG_ENV_SETTINGS_DEFAULT \
- "initrd_addr=0x83100000\0" \
- "initrd_high=0xffffffffffffffff\0" \
- "emmc_dev=0\0"
-
/* Initial environment variables */
#define CFG_EXTRA_ENV_SETTINGS \
- CFG_MFG_ENV_SETTINGS \
- M4_BOOT_ENV \
- AHAB_ENV \
- ENV_COMMON \
- "script=boot.scr\0" \
- "image=Image\0" \
- "panel=NULL\0" \
- "console=ttyLP2\0" \
- "fdt_addr=0x83000000\0" \
- "fdt_high=0xffffffffffffffff\0" \
- "cntr_addr=0x88000000\0" \
- "cntr_file=os_cntr_signed.bin\0" \
- "initrd_addr=0x83800000\0" \
- "initrd_high=0xffffffffffffffff\0" \
- "netdev=eth0\0" \
- "nfsopts=vers=3,udp,rsize=4096,wsize=4096,nolock rw\0" \
- "hostname=capricorn\0" \
- ENV_EMMC \
- ENV_NET
+ AHAB_ENV
/* Default location for tftp and bootm */
diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h
deleted file mode 100644
index 3412b88..0000000
--- a/include/configs/cardhu.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/sizes.h>
-
-#include "tegra30-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "NVIDIA Cardhu"
-
-/* Board-specific serial config */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h
deleted file mode 100644
index fbd38b7..0000000
--- a/include/configs/cei-tk1-som.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * (c) Copyright 2016, Data61
- * Commonwealth Scientific and Industrial Research Organisation (CSIRO)
- *
- * Based on jetson-tk1.h which is:
- * (C) Copyright 2013-2014
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/sizes.h>
-
-#include "tegra124-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "CEI tk1-som"
-
-/* Board-specific serial config */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h
deleted file mode 100644
index bc616d1..0000000
--- a/include/configs/colibri_t20.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2012 Lucas Stach
- *
- * Configuration settings for the Toradex Colibri T20 modules.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "tegra20-common.h"
-
-/* Board-specific serial config */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h
deleted file mode 100644
index 1f47466..0000000
--- a/include/configs/colibri_t30.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2013-2016 Stefan Agner
- *
- * Configuration settings for the Toradex Colibri T30 modules.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/sizes.h>
-
-#include "tegra30-common.h"
-
-/* High-level configuration options */
-
-/*
- * Board-specific serial config
- *
- * Colibri UART-A: NVIDIA UARTA
- * Colibri UART-B: NVIDIA UARTD
- * Colibri UART-C: NVIDIA UARTB
- */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h
deleted file mode 100644
index 0955541..0000000
--- a/include/configs/dalmore.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/sizes.h>
-
-#include "tegra114-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "NVIDIA Dalmore"
-
-/* Board-specific serial config */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-
-/* Environment in eMMC, at the end of 2nd "boot sector" */
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h
index 00102cd..c31c6c5 100644
--- a/include/configs/dragonboard410c.h
+++ b/include/configs/dragonboard410c.h
@@ -18,15 +18,4 @@
#define PHYS_SDRAM_1_SIZE SZ_1G
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
-/* Environment */
-#define BOOT_TARGET_DEVICES(func) \
- func(USB, usb, 0) \
- func(MMC, mmc, 1) \
- func(MMC, mmc, 0) \
- func(DHCP, dhcp, na)
-
-#include <config_distro_bootcmd.h>
-
-#define CFG_EXTRA_ENV_SETTINGS BOOTENV
-
#endif
diff --git a/include/configs/endeavoru.h b/include/configs/endeavoru.h
deleted file mode 100644
index 33d0021..0000000
--- a/include/configs/endeavoru.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * (C) Copyright 2010,2012
- * NVIDIA Corporation <www.nvidia.com>
- *
- * (C) Copyright 2022
- * Svyatoslav Ryhel <clamor95@gmail.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "tegra30-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "HTC One X"
-
-/* Board-specific serial config */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/evb_rk3568.h b/include/configs/evb_rk3568.h
index a0f2383..9070160 100644
--- a/include/configs/evb_rk3568.h
+++ b/include/configs/evb_rk3568.h
@@ -6,10 +6,10 @@
#ifndef __EVB_RK3568_H
#define __EVB_RK3568_H
-#include <configs/rk3568_common.h>
-
#define ROCKCHIP_DEVICE_SETTINGS \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
+#include <configs/rk3568_common.h>
+
#endif
diff --git a/include/configs/evb_rk3588.h b/include/configs/evb_rk3588.h
index 4568e2c..5ff1ddb 100644
--- a/include/configs/evb_rk3588.h
+++ b/include/configs/evb_rk3588.h
@@ -6,10 +6,10 @@
#ifndef __EVB_RK3588_H
#define __EVB_RK3588_H
-#include <configs/rk3588_common.h>
-
#define ROCKCHIP_DEVICE_SETTINGS \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
+#include <configs/rk3588_common.h>
+
#endif
diff --git a/include/configs/giedi.h b/include/configs/giedi.h
deleted file mode 100644
index 19a795b..0000000
--- a/include/configs/giedi.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2019 Siemens AG
- *
- */
-
-#ifndef __GIEDI_H
-#define __GIEDI_H
-
-#include "capricorn-common.h"
-
-/* DDR3 board total DDR is 1 GB */
-#undef PHYS_SDRAM_1_SIZE
-#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */
-
-#endif /* __GIEDI_H */
diff --git a/include/configs/grouper.h b/include/configs/grouper.h
deleted file mode 100644
index b6ef6ff..0000000
--- a/include/configs/grouper.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "tegra30-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "ASUS Google Nexus 7 (2012)"
-
-/* Board-specific serial config */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/harmony.h b/include/configs/harmony.h
deleted file mode 100644
index cae7acd..0000000
--- a/include/configs/harmony.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010-2012
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/sizes.h>
-#include "tegra20-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "NVIDIA Harmony"
-
-/* Board-specific serial config */
-
-/* UARTD: keyboard satellite board UART, default */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-#ifdef CONFIG_TEGRA_ENABLE_UARTA
-/* UARTA: debug board UART */
-#define CFG_SYS_NS16550_COM2 NV_PA_APB_UARTA_BASE
-#endif
-
-/* NAND support */
-
-/* Environment in NAND (which is 512M), aligned to start of last sector */
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/ideapad-yoga-11.h b/include/configs/ideapad-yoga-11.h
deleted file mode 100644
index c4e6b2a..0000000
--- a/include/configs/ideapad-yoga-11.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "tegra30-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "Lenovo Ideapad Yoga 11"
-
-/* Board-specific serial config */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h
deleted file mode 100644
index 9858f8f..0000000
--- a/include/configs/jetson-tk1.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * (C) Copyright 2013-2014
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/sizes.h>
-
-#include "tegra124-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "NVIDIA Jetson TK1"
-
-/* Board-specific serial config */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/khadas-edge2-rk3588s.h b/include/configs/khadas-edge2-rk3588s.h
index d279cf3..fe8461d 100644
--- a/include/configs/khadas-edge2-rk3588s.h
+++ b/include/configs/khadas-edge2-rk3588s.h
@@ -6,10 +6,10 @@
#ifndef __KHADAS_EDGE2_RK3588_H
#define __KHADAS_EDGE2_RK3588_H
-#include <configs/rk3588_common.h>
-
#define ROCKCHIP_DEVICE_SETTINGS \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
+#include <configs/rk3588_common.h>
+
#endif /* __KHADAS_EDGE2_RK3588_H */
diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h
deleted file mode 100644
index 8dbe741..0000000
--- a/include/configs/medcom-wide.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
- * (C) Copyright 2011-2012
- * Avionic Design GmbH <www.avionic-design.de>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "tegra20-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "Avionic Design Medcom-Wide"
-
-/* Board-specific serial config */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-
-/* NAND support */
-
-/* Environment in NAND, aligned to start of last sector */
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/mocha.h b/include/configs/mocha.h
index 1c2eb90..7255f31 100644
--- a/include/configs/mocha.h
+++ b/include/configs/mocha.h
@@ -10,12 +10,6 @@
#include "tegra124-common.h"
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "Xiaomi Mocha"
-
-/* Board-specific serial config */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-
#ifdef CONFIG_TEGRA_SUPPORT_NON_SECURE
#define CFG_PRAM 0x38400 /* 225 MB */
#endif
diff --git a/include/configs/mot.h b/include/configs/mot.h
new file mode 100644
index 0000000..018672c
--- /dev/null
+++ b/include/configs/mot.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2023
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+#include "tegra20-common.h"
+
+/* Tegra common post configuration overwrites text env in the board */
+#define BOARD_EXTRA_ENV_SETTINGS \
+ "stdin=serial,tegra-kbc,button-kbd,cpcap-pwrbutton\0"
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h
deleted file mode 100644
index c04d402..0000000
--- a/include/configs/nyan-big.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2014
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/sizes.h>
-
-#include "tegra124-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "Google/NVIDIA Nyan-big"
-
-/* Board-specific serial config */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/ouya.h b/include/configs/ouya.h
deleted file mode 100644
index cc86c10..0000000
--- a/include/configs/ouya.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * (C) Copyright 2010,2012
- * NVIDIA Corporation <www.nvidia.com>
- *
- * (C) Copyright 2025
- * Svyatoslav Ryhel <clamor95@gmail.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "tegra30-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "Ouya Game Console"
-
-/* Board-specific serial config */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h
deleted file mode 100644
index a29d713..0000000
--- a/include/configs/p2371-0000.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013-2015
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef _P2371_0000_H
-#define _P2371_0000_H
-
-#include <linux/sizes.h>
-
-#include "tegra210-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "NVIDIA P2371-0000"
-
-/* Board-specific serial config */
-
-/* Environment in eMMC, at the end of 2nd "boot sector" */
-
-#include "tegra-common-post.h"
-
-#endif /* _P2371_0000_H */
diff --git a/include/configs/p2371-2180.h b/include/configs/p2371-2180.h
deleted file mode 100644
index 0b077ab..0000000
--- a/include/configs/p2371-2180.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013-2015
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef _P2371_2180_H
-#define _P2371_2180_H
-
-#include <linux/sizes.h>
-
-#include "tegra210-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "NVIDIA P2371-2180"
-
-/* Board-specific serial config */
-
-/* Environment in eMMC, at the end of 2nd "boot sector" */
-
-#include "tegra-common-post.h"
-
-#endif /* _P2371_2180_H */
diff --git a/include/configs/p2571.h b/include/configs/p2571.h
deleted file mode 100644
index 5155aa7..0000000
--- a/include/configs/p2571.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013-2015
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef _P2571_H
-#define _P2571_H
-
-#include <linux/sizes.h>
-
-#include "tegra210-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "NVIDIA P2571"
-
-/* Board-specific serial config */
-
-/* Environment in eMMC, at the end of 2nd "boot sector" */
-
-#include "tegra-common-post.h"
-
-#endif /* _P2571_H */
diff --git a/include/configs/p2771-0000.h b/include/configs/p2771-0000.h
deleted file mode 100644
index fc1b7c0..0000000
--- a/include/configs/p2771-0000.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2013-2016, NVIDIA CORPORATION.
- */
-
-#ifndef _P2771_0000_H
-#define _P2771_0000_H
-
-#include <linux/sizes.h>
-
-#include "tegra186-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "NVIDIA P2771-0000"
-
-/* Environment in eMMC, at the end of 2nd "boot sector" */
-
-#include "tegra-common-post.h"
-
-#endif
diff --git a/include/configs/p3450-0000.h b/include/configs/p3450-0000.h
deleted file mode 100644
index 1138c1d..0000000
--- a/include/configs/p3450-0000.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2018-2019 NVIDIA Corporation.
- */
-
-#ifndef _P3450_0000_H
-#define _P3450_0000_H
-
-#include <linux/sizes.h>
-
-#include "tegra210-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "NVIDIA P3450-0000"
-
-/* Board-specific serial config */
-
-/* General networking support */
-#include "tegra-common-post.h"
-
-#endif /* _P3450_0000_H */
diff --git a/include/configs/paz00.h b/include/configs/paz00.h
deleted file mode 100644
index 950b321..0000000
--- a/include/configs/paz00.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/sizes.h>
-#include "tegra20-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "Compal Paz00"
-
-/* Board-specific serial config */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-
-/* Environment in eMMC, at the end of 2nd "boot sector" */
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/picasso.h b/include/configs/picasso.h
deleted file mode 100644
index a58c7e5..0000000
--- a/include/configs/picasso.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
- *
- * (C) Copyright 2024
- * Svyatoslav Ryhel <clamor95@gmail.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "tegra20-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "Acer Iconia Tab A500"
-
-/* Board-specific serial config */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/plutux.h b/include/configs/plutux.h
deleted file mode 100644
index 30bfce9..0000000
--- a/include/configs/plutux.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
- * (C) Copyright 2011-2012
- * Avionic Design GmbH <www.avionic-design.de>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "tegra20-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "Avionic Design Plutux"
-
-/* Board-specific serial config */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-
-/* NAND support */
-
-/* Environment in NAND, aligned to start of last sector */
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/powkiddy-x55-rk3566.h b/include/configs/powkiddy-x55-rk3566.h
index 4b25c6a..8ace435 100644
--- a/include/configs/powkiddy-x55-rk3566.h
+++ b/include/configs/powkiddy-x55-rk3566.h
@@ -3,10 +3,10 @@
#ifndef __POWKIDDY_X55_RK3566_H
#define __POWKIDDY_X55_RK3566_H
-#include <configs/rk3568_common.h>
-
#define ROCKCHIP_DEVICE_SETTINGS \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
+#include <configs/rk3568_common.h>
+
#endif
diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h
index 13ed901..d053900 100644
--- a/include/configs/px30_common.h
+++ b/include/configs/px30_common.h
@@ -20,6 +20,7 @@
"scriptaddr=0x00500000\0" \
"pxefile_addr_r=0x00600000\0" \
"fdt_addr_r=0x08300000\0" \
+ "fdtoverlay_addr_r=0x08400000\0" \
"kernel_addr_r=0x00280000\0" \
"ramdisk_addr_r=0x0a200000\0" \
"kernel_comp_addr_r=0x03e80000\0" \
diff --git a/include/configs/qc750.h b/include/configs/qc750.h
deleted file mode 100644
index ad9f914..0000000
--- a/include/configs/qc750.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * (C) Copyright 2010,2012
- * NVIDIA Corporation <www.nvidia.com>
- *
- * (C) Copyright 2023
- * Svyatoslav Ryhel <clamor95@gmail.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "tegra30-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "Wexler QC750"
-
-/* Board-specific serial config */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/rk3528_common.h b/include/configs/rk3528_common.h
new file mode 100644
index 0000000..f7dc6ec
--- /dev/null
+++ b/include/configs/rk3528_common.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* Copyright Contributors to the U-Boot project. */
+
+#ifndef __CONFIG_RK3528_COMMON_H
+#define __CONFIG_RK3528_COMMON_H
+
+#define CFG_CPUID_OFFSET 0xa
+
+#include "rockchip-common.h"
+
+#define CFG_IRAM_BASE 0xfe480000
+
+#define CFG_SYS_SDRAM_BASE 0
+#define SDRAM_MAX_SIZE 0xfc000000
+
+#ifndef ROCKCHIP_DEVICE_SETTINGS
+#define ROCKCHIP_DEVICE_SETTINGS
+#endif
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "scriptaddr=0x00c00000\0" \
+ "script_offset_f=0xffe000\0" \
+ "script_size_f=0x2000\0" \
+ "pxefile_addr_r=0x00e00000\0" \
+ "kernel_addr_r=0x02000000\0" \
+ "kernel_comp_addr_r=0x0a000000\0" \
+ "fdt_addr_r=0x12000000\0" \
+ "fdtoverlay_addr_r=0x12100000\0" \
+ "ramdisk_addr_r=0x12180000\0" \
+ "kernel_comp_size=0x8000000\0"
+
+#define CFG_EXTRA_ENV_SETTINGS \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ ENV_MEM_LAYOUT_SETTINGS \
+ ROCKCHIP_DEVICE_SETTINGS \
+ "boot_targets=" BOOT_TARGETS "\0"
+
+#endif /* __CONFIG_RK3528_COMMON_H */
diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h
index 09b7b71..b2a35db 100644
--- a/include/configs/rk3568_common.h
+++ b/include/configs/rk3568_common.h
@@ -15,6 +15,10 @@
#define CFG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xf0000000
+#ifndef ROCKCHIP_DEVICE_SETTINGS
+#define ROCKCHIP_DEVICE_SETTINGS
+#endif
+
#define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x00c00000\0" \
"script_offset_f=0xffe000\0" \
@@ -29,7 +33,6 @@
#define CFG_EXTRA_ENV_SETTINGS \
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
- "partitions=" PARTS_DEFAULT \
ENV_MEM_LAYOUT_SETTINGS \
ROCKCHIP_DEVICE_SETTINGS \
"boot_targets=" BOOT_TARGETS "\0"
diff --git a/include/configs/rk3576_common.h b/include/configs/rk3576_common.h
new file mode 100644
index 0000000..14d1d86
--- /dev/null
+++ b/include/configs/rk3576_common.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2024 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __CONFIG_RK3576_COMMON_H
+#define __CONFIG_RK3576_COMMON_H
+
+#define CFG_CPUID_OFFSET 0xa
+
+#include "rockchip-common.h"
+
+#define CFG_IRAM_BASE 0x3ff80000
+
+#define CFG_SYS_SDRAM_BASE 0x40000000
+/* Used by board_get_usable_ram_top(), space below the 4G address boundary */
+#define SDRAM_MAX_SIZE (SZ_4G - CFG_SYS_SDRAM_BASE)
+
+#ifndef ROCKCHIP_DEVICE_SETTINGS
+#define ROCKCHIP_DEVICE_SETTINGS
+#endif
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "scriptaddr=0x40c00000\0" \
+ "script_offset_f=0xffe000\0" \
+ "script_size_f=0x2000\0" \
+ "pxefile_addr_r=0x40e00000\0" \
+ "kernel_addr_r=0x42000000\0" \
+ "kernel_comp_addr_r=0x4a000000\0" \
+ "fdt_addr_r=0x52000000\0" \
+ "fdtoverlay_addr_r=0x52100000\0" \
+ "ramdisk_addr_r=0x52180000\0" \
+ "kernel_comp_size=0x8000000\0"
+
+#define CFG_EXTRA_ENV_SETTINGS \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ ENV_MEM_LAYOUT_SETTINGS \
+ ROCKCHIP_DEVICE_SETTINGS \
+ "boot_targets=" BOOT_TARGETS "\0"
+
+#endif /* __CONFIG_RK3576_COMMON_H */
diff --git a/include/configs/rk3588_common.h b/include/configs/rk3588_common.h
index e6654c2..2f0d40d 100644
--- a/include/configs/rk3588_common.h
+++ b/include/configs/rk3588_common.h
@@ -14,6 +14,10 @@
#define CFG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xf0000000
+#ifndef ROCKCHIP_DEVICE_SETTINGS
+#define ROCKCHIP_DEVICE_SETTINGS
+#endif
+
#define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x00c00000\0" \
"script_offset_f=0xffe000\0" \
@@ -28,7 +32,6 @@
#define CFG_EXTRA_ENV_SETTINGS \
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
- "partitions=" PARTS_DEFAULT \
ENV_MEM_LAYOUT_SETTINGS \
ROCKCHIP_DEVICE_SETTINGS \
"boot_targets=" BOOT_TARGETS "\0"
diff --git a/include/configs/roc-pc-rk3576.h b/include/configs/roc-pc-rk3576.h
new file mode 100644
index 0000000..77c95f0
--- /dev/null
+++ b/include/configs/roc-pc-rk3576.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __ROC_PC_RK3576_H
+#define __ROC_PC_RK3576_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#include <configs/rk3576_common.h>
+
+#endif
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
deleted file mode 100644
index 8e98620..0000000
--- a/include/configs/seaboard.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/sizes.h>
-
-#include "tegra20-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "NVIDIA Seaboard"
-
-/* Board-specific serial config */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-
-/* Environment in eMMC, at the end of 2nd "boot sector" */
-
-/* NAND support */
-
-/* Max number of NAND devices */
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h
index 00ec9ef..e6f8dee 100644
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h
@@ -30,7 +30,7 @@
#include <config_distro_bootcmd.h>
#define CFG_EXTRA_ENV_SETTINGS \
"kernel_addr_r=0xC0008000\0" \
- "fdtfile="CONFIG_DEFAULT_DEVICE_TREE".dtb\0" \
+ "fdtfile="CONFIG_DEFAULT_FDT_FILE".dtb\0" \
"fdt_addr_r=0xC0408000\0" \
"scriptaddr=0xC0418000\0" \
"pxefile_addr_r=0xC0428000\0" \
diff --git a/include/configs/stm32mp25_common.h b/include/configs/stm32mp25_common.h
index ec980ee..b42316f 100644
--- a/include/configs/stm32mp25_common.h
+++ b/include/configs/stm32mp25_common.h
@@ -21,4 +21,106 @@
*/
#define CFG_SYS_BOOTMAPSZ SZ_256M
+/*****************************************************************************/
+#ifdef CONFIG_DISTRO_DEFAULTS
+/*****************************************************************************/
+
+#ifdef CONFIG_NET
+#define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
+#else
+#define BOOT_TARGET_PXE(func)
+#endif
+
+#ifdef CONFIG_CMD_MMC
+#define BOOT_TARGET_MMC0(func) func(MMC, mmc, 0)
+#define BOOT_TARGET_MMC1(func) func(MMC, mmc, 1)
+#define BOOT_TARGET_MMC2(func) func(MMC, mmc, 2)
+#else
+#define BOOT_TARGET_MMC0(func)
+#define BOOT_TARGET_MMC1(func)
+#define BOOT_TARGET_MMC2(func)
+#endif
+
+#ifdef CONFIG_CMD_UBIFS
+#define BOOT_TARGET_UBIFS(func) func(UBIFS, ubifs, 0, UBI, boot)
+#else
+#define BOOT_TARGET_UBIFS(func)
+#endif
+
+#ifdef CONFIG_CMD_USB
+#define BOOT_TARGET_USB(func) func(USB, usb, 0)
+#else
+#define BOOT_TARGET_USB(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+ BOOT_TARGET_MMC1(func) \
+ BOOT_TARGET_UBIFS(func) \
+ BOOT_TARGET_MMC0(func) \
+ BOOT_TARGET_MMC2(func) \
+ BOOT_TARGET_USB(func) \
+ BOOT_TARGET_PXE(func)
+
+/*
+ * default bootcmd for stm32mp25:
+ * for serial/usb: execute the stm32prog command
+ * for mmc boot (eMMC, SD card), distro boot on the same mmc device
+ * for NAND or SPI-NAND boot, distro boot with UBIFS on UBI partition
+ * for other boot, use the default distro order in ${boot_targets}
+ */
+#define STM32MP_BOOTCMD "bootcmd_stm32mp=" \
+ "echo \"Boot over ${boot_device}${boot_instance}!\";" \
+ "if test ${boot_device} = serial || test ${boot_device} = usb;" \
+ "then stm32prog ${boot_device} ${boot_instance}; " \
+ "else " \
+ "run env_check;" \
+ "if test ${boot_device} = mmc;" \
+ "then env set boot_targets \"mmc${boot_instance}\"; fi;" \
+ "if test ${boot_device} = nand ||" \
+ " test ${boot_device} = spi-nand ;" \
+ "then env set boot_targets ubifs0; fi;" \
+ "run distro_bootcmd;" \
+ "fi;\0"
+
+#ifndef STM32MP_BOARD_EXTRA_ENV
+#define STM32MP_BOARD_EXTRA_ENV
+#endif
+
+#define STM32MP_EXTRA \
+ "env_check=if env info -p -d -q; then env save; fi\0" \
+ "boot_net_usb_start=true\0"
+/*
+ * memory layout for 96MB uncompressed/compressed kernel,
+ * 1M fdt, 1M script, 1M pxe and 1M for overlay
+ * and the ramdisk at the end.
+ */
+#define __KERNEL_COMP_ADDR_R __stringify(0x84000000)
+#define __KERNEL_COMP_SIZE_R __stringify(0x04000000)
+#define __KERNEL_ADDR_R __stringify(0x8a000000)
+#define __FDT_ADDR_R __stringify(0x90000000)
+#define __SCRIPT_ADDR_R __stringify(0x90100000)
+#define __PXEFILE_ADDR_R __stringify(0x90200000)
+#define __FDTOVERLAY_ADDR_R __stringify(0x90300000)
+#define __RAMDISK_ADDR_R __stringify(0x90400000)
+
+#define STM32MP_MEM_LAYOUT \
+ "kernel_addr_r=" __KERNEL_ADDR_R "\0" \
+ "fdt_addr_r=" __FDT_ADDR_R "\0" \
+ "scriptaddr=" __SCRIPT_ADDR_R "\0" \
+ "pxefile_addr_r=" __PXEFILE_ADDR_R "\0" \
+ "fdtoverlay_addr_r=" __FDTOVERLAY_ADDR_R "\0" \
+ "ramdisk_addr_r=" __RAMDISK_ADDR_R "\0" \
+ "kernel_comp_addr_r=" __KERNEL_COMP_ADDR_R "\0" \
+ "kernel_comp_size=" __KERNEL_COMP_SIZE_R "\0"
+
+#include <config_distro_bootcmd.h>
+#define CFG_EXTRA_ENV_SETTINGS \
+ STM32MP_MEM_LAYOUT \
+ STM32MP_BOOTCMD \
+ BOOTENV \
+ STM32MP_EXTRA \
+ STM32MP_BOARD_EXTRA_ENV
+
+#endif
+
#endif /* __CONFIG_STM32MP25_COMMMON_H */
diff --git a/include/configs/stm32mp25_st_common.h b/include/configs/stm32mp25_st_common.h
new file mode 100644
index 0000000..ab5a4a9
--- /dev/null
+++ b/include/configs/stm32mp25_st_common.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
+/*
+ * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ *
+ * Configuration settings for the STMicroelectonics STM32MP25x boards
+ */
+
+#ifndef __CONFIG_STM32MP25_ST_COMMON_H__
+#define __CONFIG_STM32MP25_ST_COMMON_H__
+
+#define STM32MP_BOARD_EXTRA_ENV \
+ "usb_pgood_delay=2000\0" \
+ "console=ttySTM0\0"
+
+#include <configs/stm32mp25_common.h>
+
+#ifdef CFG_EXTRA_ENV_SETTINGS
+/*
+ * default bootcmd for stm32mp25 STMicroelectronics boards:
+ * for serial/usb: execute the stm32prog command
+ * for mmc boot (eMMC, SD card), distro boot on the same mmc device
+ * for nand or spi-nand boot, distro boot with ubifs on UBI partition or
+ * sdcard
+ * for nor boot, distro boot on SD card = mmc0 ONLY !
+ */
+#define ST_STM32MP25_BOOTCMD "bootcmd_stm32mp=" \
+ "echo \"Boot over ${boot_device}${boot_instance}!\";" \
+ "if test ${boot_device} = serial || test ${boot_device} = usb;" \
+ "then stm32prog ${boot_device} ${boot_instance}; " \
+ "else " \
+ "run env_check;" \
+ "if test ${boot_device} = mmc;" \
+ "then env set boot_targets \"mmc${boot_instance}\"; fi;" \
+ "if test ${boot_device} = nand ||" \
+ " test ${boot_device} = spi-nand ;" \
+ "then env set boot_targets ubifs0 mmc0; fi;" \
+ "if test ${boot_device} = nor;" \
+ "then env set boot_targets mmc0; fi;" \
+ "run distro_bootcmd;" \
+ "fi;\0"
+
+#undef CFG_EXTRA_ENV_SETTINGS
+#define CFG_EXTRA_ENV_SETTINGS \
+ STM32MP_MEM_LAYOUT \
+ ST_STM32MP25_BOOTCMD \
+ BOOTENV \
+ STM32MP_EXTRA \
+ STM32MP_BOARD_EXTRA_ENV
+
+#endif
+#endif
diff --git a/include/configs/surface-rt.h b/include/configs/surface-rt.h
deleted file mode 100644
index 1f0837e..0000000
--- a/include/configs/surface-rt.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
- *
- * Copyright (c) 2021, Open Surface RT
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "tegra30-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "Microsoft Surface RT"
-
-/* Board-specific serial config */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h
deleted file mode 100644
index 5e49abb..0000000
--- a/include/configs/tec-ng.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013
- * Avionic Design GmbH <www.avionic-design.de>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "tegra30-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "Avionic Design Tamonten™ NG Evaluation Carrier"
-
-/* Board-specific serial config */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/tec.h b/include/configs/tec.h
deleted file mode 100644
index 05dd7c9..0000000
--- a/include/configs/tec.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
- * (C) Copyright 2011-2012
- * Avionic Design GmbH <www.avionic-design.de>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "tegra20-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier"
-
-/* Board-specific serial config */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-
-/* NAND support */
-
-/* Environment in NAND, aligned to start of last sector */
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/tegra.h b/include/configs/tegra.h
new file mode 100644
index 0000000..77bc389
--- /dev/null
+++ b/include/configs/tegra.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2025
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ *
+ * Generic device header which can be used with SYS_CONFIG_NAME
+ * for any Tegra device (T20, T30, T114, T124, T186 or T210).
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#ifdef CONFIG_TEGRA20
+#include "tegra20-common.h"
+#elif CONFIG_TEGRA30
+#include "tegra30-common.h"
+#elif CONFIG_TEGRA114
+#include "tegra114-common.h"
+#elif CONFIG_TEGRA124
+#include "tegra124-common.h"
+#elif CONFIG_TEGRA186
+#include "tegra186-common.h"
+#elif CONFIG_TEGRA210
+#include "tegra210-common.h"
+#endif
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/tegratab.h b/include/configs/tegratab.h
new file mode 100644
index 0000000..afab01e
--- /dev/null
+++ b/include/configs/tegratab.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Copyright (c) 2023, Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tegra114-common.h"
+
+#ifdef CONFIG_TEGRA_SUPPORT_NON_SECURE
+ #define CFG_PRAM 0x21c00 /* 135 MB */
+#endif
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h
index 0627617..5530d36 100644
--- a/include/configs/topic_miami.h
+++ b/include/configs/topic_miami.h
@@ -9,75 +9,67 @@
#ifndef __CONFIG_TOPIC_MIAMI_H
#define __CONFIG_TOPIC_MIAMI_H
-/* Speed up boot time by ignoring the environment which we never used */
+#ifndef CONFIG_XPL_BUILD
-#include "zynq-common.h"
+#ifdef CONFIG_CMD_MMC
+#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
+#else
+#define BOOT_TARGET_DEVICES_MMC(func)
+#endif
-/* Fixup settings */
+#ifdef CONFIG_CMD_USB
+#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
+#else
+#define BOOT_TARGET_DEVICES_USB(func)
+#endif
-/* Setup proper boot sequences for Miami boards */
+#if defined(CONFIG_ZYNQ_QSPI)
+# define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na)
+#else
+# define BOOT_TARGET_DEVICES_QSPI(func)
+#endif
-#if defined(CONFIG_USB_HOST)
-# define EXTRA_ENV_USB \
- "usbreset=i2c dev 1 && i2c mw 41 1 ff && i2c mw 41 3 fe && "\
- "i2c mw 41 1 fe && i2c mw 41 1 ff\0" \
- "usbboot=run usbreset && if usb start; then " \
- "echo Booting from USB... && " \
- "if load usb 0 0x1900000 ${bootscript}; then "\
- "source 0x1900000; fi; " \
- "load usb 0 ${kernel_addr} ${kernel_image} && " \
- "load usb 0 ${devicetree_addr} ${devicetree_image} && " \
- "load usb 0 ${ramdisk_load_address} ${ramdisk_image} && " \
- "bootm ${kernel_addr} ${ramdisk_load_address} "\
- "${devicetree_addr}; " \
- "fi\0"
- /* Note that addresses here should match the addresses in the env */
-# define DFU_ALT_INFO \
- "dfu_alt_info=" \
- "uImage ram 0x2080000 0x500000;" \
- "devicetree.dtb ram 0x2000000 0x20000;" \
- "uramdisk.image.gz ram 0x4000000 0x10000000\0" \
- "dfu_ram=run usbreset && dfu 0 ram 0\0" \
- "thor_ram=run usbreset && thordown 0 ram 0\0"
+#ifdef CONFIG_CMD_UBIFS
+# define BOOT_TARGET_DEVICES_UBIFS(func) func(UBIFS, ubifs, 0, qspi-rootfs, qspi-rootfs)
#else
-# define EXTRA_ENV_USB
+# define BOOT_TARGET_DEVICES_UBIFS(func)
#endif
+#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \
+ "bootcmd_qspi=sf probe && " \
+ "sf read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \
+ "echo QSPI: Trying to boot script at ${scriptaddr} && " \
+ "source ${scriptaddr}; echo QSPI: SCRIPT FAILED: continuing...;\0"
+
-#undef CFG_EXTRA_ENV_SETTINGS
+#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \
+ "qspi "
+
+#define BOOT_TARGET_DEVICES(func) \
+ BOOT_TARGET_DEVICES_MMC(func) \
+ BOOT_TARGET_DEVICES_UBIFS(func) \
+ BOOT_TARGET_DEVICES_QSPI(func)
+
+#include <config_distro_bootcmd.h>
+
+#endif /* CONFIG_XPL_BUILD */
+
+/* Default environment */
+#ifndef CFG_EXTRA_ENV_SETTINGS
#define CFG_EXTRA_ENV_SETTINGS \
- "kernel_image=uImage\0" \
- "kernel_addr=0x2080000\0" \
- "ramdisk_image=uramdisk.image.gz\0" \
- "ramdisk_load_address=0x4000000\0" \
- "devicetree_image=devicetree.dtb\0" \
- "devicetree_addr=0x2000000\0" \
- "bitstream_image=fpga.bin\0" \
- "bootscript=autorun.scr\0" \
- "loadbit_addr=0x100000\0" \
- "loadbootenv_addr=0x2000000\0" \
- "kernel_size=0x440000\0" \
- "devicetree_size=0x10000\0" \
- "boot_size=0xF00000\0" \
- "fdt_high=0x20000000\0" \
- "initrd_high=0x20000000\0" \
- "mmc_loadbit=echo Loading bitstream from SD/MMC/eMMC to RAM.. && " \
- "mmcinfo && " \
- "load mmc 0 ${loadbit_addr} ${bitstream_image} && " \
- "fpga load 0 ${loadbit_addr} ${filesize}\0" \
- "qspiboot=echo Booting from QSPI flash... && " \
- "sf probe && " \
- "sf read ${devicetree_addr} 0xA0000 ${devicetree_size} && " \
- "sf read ${kernel_addr} 0xC0000 ${kernel_size} && " \
- "bootm ${kernel_addr} - ${devicetree_addr}\0" \
- "sdboot=if mmcinfo; then " \
- "setenv bootargs console=ttyPS0,115200 " \
- "root=/dev/mmcblk0p2 rw rootfstype=ext4 " \
- "rootwait quiet ; " \
- "load mmc 0 ${kernel_addr} ${kernel_image}&& " \
- "load mmc 0 ${devicetree_addr} ${devicetree_image}&& " \
- "bootm ${kernel_addr} - ${devicetree_addr}; " \
- "fi\0" \
- EXTRA_ENV_USB \
- DFU_ALT_INFO
+ "scriptaddr=0x3000000\0" \
+ "script_offset_f=0xf0000\0" \
+ "script_size_f=0x10000\0" \
+ "fdt_addr_r=0x1f00000\0" \
+ "pxefile_addr_r=0x2000000\0" \
+ "kernel_addr_r=0x2000000\0" \
+ "ramdisk_addr_r=0x3100000\0" \
+ BOOTENV
+#endif
+
+#include "zynq-common.h"
+
+/* Detect RAM size */
+#define CFG_SYS_SDRAM_BASE 0
+#define CFG_SYS_SDRAM_SIZE 0x40000000
#endif /* __CONFIG_TOPIC_MIAMI_H */
diff --git a/include/configs/toradex-smarc-imx8mp.h b/include/configs/toradex-smarc-imx8mp.h
new file mode 100644
index 0000000..3d5fb85
--- /dev/null
+++ b/include/configs/toradex-smarc-imx8mp.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* Copyright (C) 2024 Toradex */
+
+#ifndef __TORADEX_SMARC_IMX8MP_H
+#define __TORADEX_SMARC_IMX8MP_H
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+
+#define CFG_SYS_UBOOT_BASE \
+ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#ifdef CONFIG_SPL_BUILD
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CFG_MALLOC_F_ADDR 0x184000
+#endif /* CONFIG_SPL_BUILD */
+
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE SZ_512K
+
+/* i.MX 8M Plus supports max. 8GB memory in two albeit consecutive banks */
+#define CFG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM 0x40000000
+#define PHYS_SDRAM_SIZE (SZ_2G + SZ_1G)
+#define PHYS_SDRAM_2 0x100000000
+#define PHYS_SDRAM_2_SIZE (SZ_4G + SZ_1G)
+
+#endif /* __TORADEX_SMARC_IMX8MP_H */
diff --git a/include/configs/toybrick_rk3588.h b/include/configs/toybrick_rk3588.h
index faa2e6c..0056508 100644
--- a/include/configs/toybrick_rk3588.h
+++ b/include/configs/toybrick_rk3588.h
@@ -6,10 +6,10 @@
#ifndef __TOYBRICK_RK3588_H
#define __TOYBRICK_RK3588_H
-#include <configs/rk3588_common.h>
-
#define ROCKCHIP_DEVICE_SETTINGS \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
+#include <configs/rk3588_common.h>
+
#endif
diff --git a/include/configs/transformer-t114.h b/include/configs/transformer-t114.h
new file mode 100644
index 0000000..2fbf341
--- /dev/null
+++ b/include/configs/transformer-t114.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Copyright (c) 2023, Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tegra114-common.h"
+
+#ifdef CONFIG_TEGRA_SUPPORT_NON_SECURE
+ #define CFG_PRAM 0x20000 /* 128 MB */
+#endif
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/transformer-t20.h b/include/configs/transformer-t20.h
deleted file mode 100644
index 6a3d9b2..0000000
--- a/include/configs/transformer-t20.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
- *
- * (C) Copyright 2022
- * Svyatoslav Ryhel <clamor95@gmail.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "tegra20-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "ASUS Transformer"
-
-/* Board-specific serial config */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/transformer-t30.h b/include/configs/transformer-t30.h
deleted file mode 100644
index 792b958..0000000
--- a/include/configs/transformer-t30.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * (C) Copyright 2010,2012
- * NVIDIA Corporation <www.nvidia.com>
- *
- * (C) Copyright 2022
- * Svyatoslav Ryhel <clamor95@gmail.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "tegra30-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "ASUS Transformer"
-
-/* Board-specific serial config */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h
deleted file mode 100644
index 7d1ff2a..0000000
--- a/include/configs/trimslice.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010-2012
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/sizes.h>
-#include "tegra20-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "Compulab Trimslice"
-
-/* Board-specific serial config */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-
-/* SPI */
-
-/* Environment in SPI */
-/* 1MiB flash, environment located as high as possible */
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/venice2.h b/include/configs/venice2.h
deleted file mode 100644
index 353b5ea..0000000
--- a/include/configs/venice2.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013-2014
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/sizes.h>
-
-#include "tegra124-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "NVIDIA Venice2"
-
-/* Board-specific serial config */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-
-/* Environment in eMMC, at the end of 2nd "boot sector" */
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/ventana.h b/include/configs/ventana.h
deleted file mode 100644
index 1d9c60c..0000000
--- a/include/configs/ventana.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/sizes.h>
-#include "tegra20-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "NVIDIA Ventana"
-
-/* Board-specific serial config */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-
-/* Environment in eMMC, at the end of 2nd "boot sector" */
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/x3-t30.h b/include/configs/x3-t30.h
deleted file mode 100644
index c152af9..0000000
--- a/include/configs/x3-t30.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * (C) Copyright 2010,2012
- * NVIDIA Corporation <www.nvidia.com>
- *
- * (C) Copyright 2022
- * Svyatoslav Ryhel <clamor95@gmail.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "tegra30-common.h"
-
-/* High-level configuration options */
-#define CFG_TEGRA_BOARD_STRING "LG X3 Board"
-
-/* Board-specific serial config */
-#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 93ae589..94273d0 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -46,7 +46,10 @@
#ifdef CONFIG_XPL_BUILD
#define BOOTENV
-#else
+#endif
+
+/* Only use this section if no BOOTENV has been configured yet */
+#ifndef BOOTENV
#ifdef CONFIG_CMD_MMC
#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
@@ -167,7 +170,8 @@
BOOT_TARGET_DEVICES_DHCP(func)
#include <config_distro_bootcmd.h>
-#endif /* CONFIG_XPL_BUILD */
+
+#endif /* BOOTENV */
/* Default environment */
#ifndef CFG_EXTRA_ENV_SETTINGS
diff --git a/include/dm/uclass.h b/include/dm/uclass.h
index c279304..8fdd727 100644
--- a/include/dm/uclass.h
+++ b/include/dm/uclass.h
@@ -334,6 +334,30 @@
struct udevice **devp);
/**
+ * uclass_get_device_by_endpoint() - Get a uclass device for a remote endpoint
+ *
+ * This searches through the parents of the specified remote endpoint
+ * for the first device matching the uclass. Said otherwise, this helper
+ * goes through the graph (endpoint) representation and searches for
+ * matching devices. Endpoints can be subnodes of the "port" node or
+ * subnodes of ports identified with a reg property, themselves in a
+ * "ports" container.
+ *
+ * The device is probed to activate it ready for use.
+ *
+ * @class_id: uclass ID to look up
+ * @dev: Device to start from
+ * @port_idx: Index of the port to follow, -1 if there is a single 'port'
+ * node without reg.
+ * @ep_idx: Index of the endpoint to follow, -1 if there is a single 'endpoint'
+ * node without reg.
+ * @target: Returns pointer to the first device matching the expected uclass.
+ * Return: 0 if OK, -ve on error
+ */
+int uclass_get_device_by_endpoint(enum uclass_id class_id, struct udevice *dev,
+ int port_idx, int ep_idx, struct udevice **target);
+
+/**
* uclass_first_device() - Get the first device in a uclass
*
* The device returned is probed if necessary, and ready for use
diff --git a/include/dt-bindings/clock/stih407-clks.h b/include/dt-bindings/clock/stih407-clks.h
deleted file mode 100644
index 082edd9..0000000
--- a/include/dt-bindings/clock/stih407-clks.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * This header provides constants clk index STMicroelectronics
- * STiH407 SoC.
- */
-#ifndef _DT_BINDINGS_CLK_STIH407
-#define _DT_BINDINGS_CLK_STIH407
-
-/* CLOCKGEN A0 */
-#define CLK_IC_LMI0 0
-#define CLK_IC_LMI1 1
-
-/* CLOCKGEN C0 */
-#define CLK_ICN_GPU 0
-#define CLK_FDMA 1
-#define CLK_NAND 2
-#define CLK_HVA 3
-#define CLK_PROC_STFE 4
-#define CLK_PROC_TP 5
-#define CLK_RX_ICN_DMU 6
-#define CLK_RX_ICN_DISP_0 6
-#define CLK_RX_ICN_DISP_1 6
-#define CLK_RX_ICN_HVA 7
-#define CLK_RX_ICN_TS 7
-#define CLK_ICN_CPU 8
-#define CLK_TX_ICN_DMU 9
-#define CLK_TX_ICN_HVA 9
-#define CLK_TX_ICN_TS 9
-#define CLK_ICN_COMPO 9
-#define CLK_MMC_0 10
-#define CLK_MMC_1 11
-#define CLK_JPEGDEC 12
-#define CLK_ICN_REG 13
-#define CLK_TRACE_A9 13
-#define CLK_PTI_STM 13
-#define CLK_EXT2F_A9 13
-#define CLK_IC_BDISP_0 14
-#define CLK_IC_BDISP_1 15
-#define CLK_PP_DMU 16
-#define CLK_VID_DMU 17
-#define CLK_DSS_LPC 18
-#define CLK_ST231_AUD_0 19
-#define CLK_ST231_GP_0 19
-#define CLK_ST231_GP_1 20
-#define CLK_ST231_DMU 21
-#define CLK_ICN_LMI 22
-#define CLK_TX_ICN_DISP_0 23
-#define CLK_TX_ICN_DISP_1 23
-#define CLK_ICN_SBC 24
-#define CLK_STFE_FRC2 25
-#define CLK_ETH_PHY 26
-#define CLK_ETH_REF_PHYCLK 27
-#define CLK_FLASH_PROMIP 28
-#define CLK_MAIN_DISP 29
-#define CLK_AUX_DISP 30
-#define CLK_COMPO_DVP 31
-
-/* CLOCKGEN D0 */
-#define CLK_PCM_0 0
-#define CLK_PCM_1 1
-#define CLK_PCM_2 2
-#define CLK_SPDIFF 3
-
-/* CLOCKGEN D2 */
-#define CLK_PIX_MAIN_DISP 0
-#define CLK_PIX_PIP 1
-#define CLK_PIX_GDP1 2
-#define CLK_PIX_GDP2 3
-#define CLK_PIX_GDP3 4
-#define CLK_PIX_GDP4 5
-#define CLK_PIX_AUX_DISP 6
-#define CLK_DENC 7
-#define CLK_PIX_HDDAC 8
-#define CLK_HDDAC 9
-#define CLK_SDDAC 10
-#define CLK_PIX_DVO 11
-#define CLK_DVO 12
-#define CLK_PIX_HDMI 13
-#define CLK_TMDS_HDMI 14
-#define CLK_REF_HDMIPHY 15
-
-/* CLOCKGEN D3 */
-#define CLK_STFE_FRC1 0
-#define CLK_TSOUT_0 1
-#define CLK_TSOUT_1 2
-#define CLK_MCHI 3
-#define CLK_VSENS_COMPO 4
-#define CLK_FRC1_REMOTE 5
-#define CLK_LPC_0 6
-#define CLK_LPC_1 7
-#endif
diff --git a/include/dt-bindings/clock/stih410-clks.h b/include/dt-bindings/clock/stih410-clks.h
deleted file mode 100644
index 2097a4b..0000000
--- a/include/dt-bindings/clock/stih410-clks.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This header provides constants clk index STMicroelectronics
- * STiH410 SoC.
- */
-#ifndef _DT_BINDINGS_CLK_STIH410
-#define _DT_BINDINGS_CLK_STIH410
-
-#include "stih407-clks.h"
-
-/* STiH410 introduces new clock outputs compared to STiH407 */
-
-/* CLOCKGEN C0 */
-#define CLK_TX_ICN_HADES 32
-#define CLK_RX_ICN_HADES 33
-#define CLK_ICN_REG_16 34
-#define CLK_PP_HADES 35
-#define CLK_CLUST_HADES 36
-#define CLK_HWPE_HADES 37
-#define CLK_FC_HADES 38
-
-/* CLOCKGEN D0 */
-#define CLK_PCMR10_MASTER 4
-#define CLK_USB2_PHY 5
-
-#endif
diff --git a/include/dt-bindings/mfd/st-lpc.h b/include/dt-bindings/mfd/st-lpc.h
deleted file mode 100644
index d05894a..0000000
--- a/include/dt-bindings/mfd/st-lpc.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * This header provides shared DT/Driver defines for ST's LPC device
- *
- * Copyright (C) 2014 STMicroelectronics -- All Rights Reserved
- *
- * Author: Lee Jones <lee.jones@linaro.org> for STMicroelectronics
- */
-
-#ifndef __DT_BINDINGS_ST_LPC_H__
-#define __DT_BINDINGS_ST_LPC_H__
-
-#define ST_LPC_MODE_RTC 0
-#define ST_LPC_MODE_WDT 1
-#define ST_LPC_MODE_CLKSRC 2
-
-#endif /* __DT_BINDINGS_ST_LPC_H__ */
diff --git a/include/dt-bindings/reset/stih407-resets.h b/include/dt-bindings/reset/stih407-resets.h
deleted file mode 100644
index 4ab3a1c..0000000
--- a/include/dt-bindings/reset/stih407-resets.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * This header provides constants for the reset controller
- * based peripheral powerdown requests on the STMicroelectronics
- * STiH407 SoC.
- */
-#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH407
-#define _DT_BINDINGS_RESET_CONTROLLER_STIH407
-
-/* Powerdown requests control 0 */
-#define STIH407_EMISS_POWERDOWN 0
-#define STIH407_NAND_POWERDOWN 1
-
-/* Synp GMAC PowerDown */
-#define STIH407_ETH1_POWERDOWN 2
-
-/* Powerdown requests control 1 */
-#define STIH407_USB3_POWERDOWN 3
-#define STIH407_USB2_PORT1_POWERDOWN 4
-#define STIH407_USB2_PORT0_POWERDOWN 5
-#define STIH407_PCIE1_POWERDOWN 6
-#define STIH407_PCIE0_POWERDOWN 7
-#define STIH407_SATA1_POWERDOWN 8
-#define STIH407_SATA0_POWERDOWN 9
-
-/* Reset defines */
-#define STIH407_ETH1_SOFTRESET 0
-#define STIH407_MMC1_SOFTRESET 1
-#define STIH407_PICOPHY_SOFTRESET 2
-#define STIH407_IRB_SOFTRESET 3
-#define STIH407_PCIE0_SOFTRESET 4
-#define STIH407_PCIE1_SOFTRESET 5
-#define STIH407_SATA0_SOFTRESET 6
-#define STIH407_SATA1_SOFTRESET 7
-#define STIH407_MIPHY0_SOFTRESET 8
-#define STIH407_MIPHY1_SOFTRESET 9
-#define STIH407_MIPHY2_SOFTRESET 10
-#define STIH407_SATA0_PWR_SOFTRESET 11
-#define STIH407_SATA1_PWR_SOFTRESET 12
-#define STIH407_DELTA_SOFTRESET 13
-#define STIH407_BLITTER_SOFTRESET 14
-#define STIH407_HDTVOUT_SOFTRESET 15
-#define STIH407_HDQVDP_SOFTRESET 16
-#define STIH407_VDP_AUX_SOFTRESET 17
-#define STIH407_COMPO_SOFTRESET 18
-#define STIH407_HDMI_TX_PHY_SOFTRESET 19
-#define STIH407_JPEG_DEC_SOFTRESET 20
-#define STIH407_VP8_DEC_SOFTRESET 21
-#define STIH407_GPU_SOFTRESET 22
-#define STIH407_HVA_SOFTRESET 23
-#define STIH407_ERAM_HVA_SOFTRESET 24
-#define STIH407_LPM_SOFTRESET 25
-#define STIH407_KEYSCAN_SOFTRESET 26
-#define STIH407_USB2_PORT0_SOFTRESET 27
-#define STIH407_USB2_PORT1_SOFTRESET 28
-#define STIH407_ST231_AUD_SOFTRESET 29
-#define STIH407_ST231_DMU_SOFTRESET 30
-#define STIH407_ST231_GP0_SOFTRESET 31
-#define STIH407_ST231_GP1_SOFTRESET 32
-
-/* Picophy reset defines */
-#define STIH407_PICOPHY0_RESET 0
-#define STIH407_PICOPHY1_RESET 1
-#define STIH407_PICOPHY2_RESET 2
-
-#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH407 */
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 5f76978..84e8cfe 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -597,10 +597,12 @@
void *efi_get_configuration_table(const efi_guid_t *guid);
/* Install device tree */
efi_status_t efi_install_fdt(void *fdt);
+/* Install initrd */
+efi_status_t efi_install_initrd(void *initrd, size_t initd_sz);
/* Execute loaded UEFI image */
efi_status_t do_bootefi_exec(efi_handle_t handle, void *load_options);
/* Run loaded UEFI image with given fdt */
-efi_status_t efi_binary_run(void *image, size_t size, void *fdt);
+efi_status_t efi_binary_run(void *image, size_t size, void *fdt, void *initrd, size_t initrd_sz);
/**
* efi_bootflow_run() - Run a bootflow containing an EFI application
@@ -667,7 +669,7 @@
struct efi_service_binding_protocol *http_service_binding);
/* Called by bootefi to make the watchdog available */
efi_status_t efi_watchdog_register(void);
-efi_status_t efi_initrd_register(void);
+efi_status_t efi_initrd_register(struct efi_device_path *dp_initrd);
efi_status_t efi_initrd_deregister(void);
/* Called by bootefi to make SMBIOS tables available */
/**
diff --git a/include/exfat.h b/include/exfat.h
index 7e43bee..75fce5b 100644
--- a/include/exfat.h
+++ b/include/exfat.h
@@ -20,5 +20,6 @@
int exfat_fs_mkdir(const char *dirname);
int exfat_fs_write(const char *filename, void *buf, loff_t offset,
loff_t len, loff_t *actwrite);
+int exfat_fs_rename(const char *old_path, const char *new_path);
#endif /* _EXFAT_H */
diff --git a/include/initcall.h b/include/initcall.h
index 62d3bb6..220a55a 100644
--- a/include/initcall.h
+++ b/include/initcall.h
@@ -8,31 +8,34 @@
#include <asm/types.h>
#include <event.h>
+#include <hang.h>
_Static_assert(EVT_COUNT < 256, "Can only support 256 event types with 8 bits");
-/**
- * init_fnc_t - Init function
- *
- * Return: 0 if OK -ve on error
- */
-typedef int (*init_fnc_t)(void);
+#define INITCALL(_call) \
+ do { \
+ if (_call()) { \
+ printf("%s(): initcall %s() failed\n", __func__, \
+ #_call); \
+ hang(); \
+ } \
+ } while (0)
-/* Top bit indicates that the initcall is an event */
-#define INITCALL_IS_EVENT GENMASK(BITS_PER_LONG - 1, 8)
-#define INITCALL_EVENT_TYPE GENMASK(7, 0)
-
-#define INITCALL_EVENT(_type) (void *)((_type) | INITCALL_IS_EVENT)
+#define INITCALL_EVT(_evt) \
+ do { \
+ if (event_notify_null(_evt)) { \
+ printf("%s(): event %d/%s failed\n", __func__, _evt, \
+ event_type_name(_evt)) ; \
+ hang(); \
+ } \
+ } while (0)
-/**
- * initcall_run_list() - Run through a list of function calls
- *
- * This calls functions one after the other, stopping at the first error, or
- * when NULL is obtained.
- *
- * @init_sequence: NULL-terminated init sequence to run
- * Return: 0 if OK, or -ve error code from the first failure
- */
-int initcall_run_list(const init_fnc_t init_sequence[]);
+#if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
+#define WATCHDOG_INIT() INITCALL(init_func_watchdog_init)
+#define WATCHDOG_RESET() INITCALL(init_func_watchdog_reset)
+#else
+#define WATCHDOG_INIT()
+#define WATCHDOG_RESET()
+#endif
#endif
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 5ea2171..2677579 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -219,6 +219,8 @@
const struct clk_ops *mux_ops;
const struct clk_ops *rate_ops;
const struct clk_ops *gate_ops;
+
+ struct udevice *dev;
};
#define to_clk_composite(_clk) container_of(_clk, struct clk_composite, clk)
diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h
index a54eff4..6455335 100644
--- a/include/linux/intel-smc.h
+++ b/include/linux/intel-smc.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2017-2018, Intel Corporation
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*/
#ifndef __INTEL_SMC_H
@@ -482,10 +483,16 @@
* Call register usage:
* a0 INTEL_SIP_SMC_HPS_SET_BRIDGES
* a1 Set bridges status:
- * 0 - Disable
- * 1 - Enable
- * a2-7 not used
- *
+ * Bit 0: 0 - Disable, 1 - Enable
+ * Bit 1: 1 - Has mask value in a2
+ * a2 Mask value
+ * Bit 0: soc2fpga
+ * Bit 1: lwhps2fpga
+ * Bit 2: fpga2soc
+ * Bit 3: f2sdram0 (For Stratix 10 only)
+ * Bit 4: f2sdram1 (For Stratix 10 only)
+ * Bit 5: f2sdram2 (For Stratix 10 only)
+ * a3-7 not used
* Return status
* a0 INTEL_SIP_SMC_STATUS_OK
*/
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index b8b207f..4eef4ab 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -569,7 +569,7 @@
u8 rdsr_dummy;
u8 rdsr_addr_nbytes;
u8 addr_mode_nbytes;
-#ifdef CONFIG_SPI_FLASH_BAR
+#if CONFIG_IS_ENABLED(SPI_FLASH_BAR)
u8 bank_read_cmd;
u8 bank_write_cmd;
u8 bank_curr;
diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
index 13b5a52..6fe6fd5 100644
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -17,7 +17,7 @@
#include <linux/spi/spi.h>
#include <linux/spi/spi-mem.h>
#else
-#include <spi.h>
+#include <linux/bitops.h>
#include <spi-mem.h>
#include <linux/mtd/nand.h>
#endif
diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h
index 8e4c43c..aa4d105 100644
--- a/include/linux/soc/ti/ti_sci_protocol.h
+++ b/include/linux/soc/ti/ti_sci_protocol.h
@@ -143,7 +143,7 @@
u32 reset_state);
int (*get_device_resets)(const struct ti_sci_handle *handle, u32 id,
u32 *reset_state);
- int (*release_exclusive_devices)(const struct ti_sci_handle *handle);
+ int (*release_exclusive_devices)(void);
};
/**
diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h
index c7927df..fe79bf6 100644
--- a/include/linux/usb/gadget.h
+++ b/include/linux/usb/gadget.h
@@ -179,6 +179,7 @@
const struct usb_ep_ops *ops;
struct list_head ep_list;
struct usb_ep_caps caps;
+ bool enabled;
unsigned maxpacket:16;
unsigned maxpacket_limit:16;
unsigned max_streams:16;
@@ -230,7 +231,18 @@
static inline int usb_ep_enable(struct usb_ep *ep,
const struct usb_endpoint_descriptor *desc)
{
- return ep->ops->enable(ep, desc);
+ int ret;
+
+ if (ep->enabled)
+ return 0;
+
+ ret = ep->ops->enable(ep, desc);
+ if (ret)
+ return ret;
+
+ ep->enabled = true;
+
+ return 0;
}
/**
@@ -247,7 +259,18 @@
*/
static inline int usb_ep_disable(struct usb_ep *ep)
{
- return ep->ops->disable(ep);
+ int ret;
+
+ if (!ep->enabled)
+ return 0;
+
+ ret = ep->ops->disable(ep);
+ if (ret)
+ return ret;
+
+ ep->enabled = false;
+
+ return 0;
}
/**
diff --git a/include/lmb.h b/include/lmb.h
index 0d316c6..606a92c 100644
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -27,9 +27,9 @@
* %LMB_NONOTIFY: Do not notify other modules of changes to this memory region
*/
#define LMB_NONE 0
-#define LMB_NOMAP BIT(0)
-#define LMB_NOOVERWRITE BIT(1)
-#define LMB_NONOTIFY BIT(2)
+#define LMB_NOMAP BIT(1)
+#define LMB_NOOVERWRITE BIT(2)
+#define LMB_NONOTIFY BIT(3)
/**
* enum lmb_map_op - memory map operation
diff --git a/include/mmc.h b/include/mmc.h
index 81bccb4..eead666 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -79,6 +79,10 @@
#define IS_SD(x) ((x)->version & SD_VERSION_SD)
#define IS_MMC(x) ((x)->version & MMC_VERSION_MMC)
+#define CID_MANFID_MICRON 0x13
+#define CID_MANFID_SAMSUNG 0x15
+#define CID_MANFID_SANDISK 0x45
+
#define MMC_DATA_READ 1
#define MMC_DATA_WRITE 2
@@ -112,6 +116,7 @@
#define MMC_CMD62_ARG1 0xefac62ec
#define MMC_CMD62_ARG2 0xcbaea7
+#define MMC_CMD62_ARG_SANDISK 0x254ddec4
#define SD_CMD_SEND_RELATIVE_ADDR 3
#define SD_CMD_SWITCH_FUNC 6
@@ -205,6 +210,7 @@
/*
* EXT_CSD fields
*/
+#define EXT_CSD_BOOT_SIZE_MULT_MICRON 125 /* R/W, vendor specific field */
#define EXT_CSD_ENH_START_ADDR 136 /* R/W */
#define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */
#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
@@ -488,6 +494,14 @@
int (*set_ios)(struct udevice *dev);
/**
+ * send_init_stream() - send the initialization stream: 74 clock cycles
+ * This is used after power up before sending the first command
+ *
+ * @dev: Device to update
+ */
+ void (*send_init_stream)(struct udevice *dev);
+
+ /**
* get_cd() - See whether a card is present
*
* @dev: Device to check
@@ -566,6 +580,7 @@
/* Transition functions for compatibility */
int mmc_set_ios(struct mmc *mmc);
+void mmc_send_init_stream(struct mmc *mmc);
int mmc_getcd(struct mmc *mmc);
int mmc_getwp(struct mmc *mmc);
int mmc_execute_tuning(struct mmc *mmc, uint opcode);
@@ -759,7 +774,11 @@
enum bus_mode user_speed_mode; /* input speed mode from user */
- CONFIG_IS_ENABLED(CYCLIC, (struct cyclic_info cyclic));
+ /*
+ * If CONFIG_CYCLIC is not set, struct cyclic_info is
+ * zero-size structure and does not add any space here.
+ */
+ struct cyclic_info cyclic;
};
#if CONFIG_IS_ENABLED(DM_MMC)
diff --git a/include/net-common.h b/include/net-common.h
index 30860f5..e536968 100644
--- a/include/net-common.h
+++ b/include/net-common.h
@@ -471,6 +471,9 @@
int net_init(void);
+/* Called when a network operation fails to know if it should be re-tried */
+int net_start_again(void);
+
/* NET compatibility */
enum proto_t;
int net_loop(enum proto_t protocol);
@@ -490,6 +493,18 @@
*/
int dhcp_run(ulong addr, const char *fname, bool autoload);
+
+/**
+ * do_ping - Run the ping command
+ *
+ * @cmdtp: Unused
+ * @flag: Command flags (CMD_FLAG_...)
+ * @argc: Number of arguments
+ * @argv: List of arguments
+ * Return: result (see enum command_ret_t)
+ */
+int do_ping(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
+
/**
* do_tftpb - Run the tftpboot command
*
diff --git a/include/net-legacy.h b/include/net-legacy.h
index bc0f0cd..5178099 100644
--- a/include/net-legacy.h
+++ b/include/net-legacy.h
@@ -347,9 +347,6 @@
int net_loop(enum proto_t);
-/* Load failed. Start again. */
-int net_start_again(void);
-
/* Get size of the ethernet header when we send */
int net_eth_hdr_size(void);
diff --git a/include/net-lwip.h b/include/net-lwip.h
index 64e5c72..b762956 100644
--- a/include/net-lwip.h
+++ b/include/net-lwip.h
@@ -10,7 +10,14 @@
TFTPGET
};
-void net_lwip_set_current(void);
+static inline int eth_is_on_demand_init(void)
+{
+ return 1;
+}
+
+int eth_init_state_only(void); /* Set active state */
+
+int net_lwip_eth_start(void);
struct netif *net_lwip_new_netif(struct udevice *udev);
struct netif *net_lwip_new_netif_noip(struct udevice *udev);
void net_lwip_remove_netif(struct netif *netif);
@@ -27,7 +34,6 @@
int do_dhcp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
int do_dns(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
-int do_ping(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
int do_wget(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]);
#endif /* __NET_LWIP_H__ */
diff --git a/include/net6.h b/include/net6.h
index 1ed989e..2ceeaba 100644
--- a/include/net6.h
+++ b/include/net6.h
@@ -90,6 +90,16 @@
0x00, 0x00, 0x00, 0x00, \
0x00, 0x00, 0x00, 0x00, \
0x00, 0x00, 0x00, 0x02 } } }
+/*
+ * With IPv6, the broadcast MAC address is not used. Instead, it should use
+ * the multicast address (see RFC RFC2464 section 7)
+ */
+#define IPV6_ALL_NODE_ETH_ADDR(_ip6_addr) {0x33, \
+ 0x33, \
+ _ip6_addr.in6_u.u6_addr8[12], \
+ _ip6_addr.in6_u.u6_addr8[13], \
+ _ip6_addr.in6_u.u6_addr8[14], \
+ _ip6_addr.in6_u.u6_addr8[15]}
#define IPV6_LINK_LOCAL_PREFIX 0xfe80
#define IPV6_LINK_LOCAL_MASK 0xffb0 /* The first 10-bit of address mask. */
diff --git a/include/power-domain.h b/include/power-domain.h
index 1852507..7fd2c5e 100644
--- a/include/power-domain.h
+++ b/include/power-domain.h
@@ -66,6 +66,15 @@
};
/**
+ * struct power_domain_plat - Per device accessible structure
+ * @subdomains: Number of subdomains covered by this device, required
+ * for refcounting
+ */
+struct power_domain_plat {
+ int subdomains;
+};
+
+/**
* power_domain_get - Get/request the power domain for a device.
*
* This looks up and requests a power domain. Each device is assumed to have
@@ -147,38 +156,82 @@
#endif
/**
- * power_domain_on - Enable power to a power domain.
+ * power_domain_on_lowlevel - Enable power to a power domain (with refcounting)
*
* @power_domain: A power domain struct that was previously successfully
* requested by power_domain_get().
- * Return: 0 if OK, or a negative error code.
+ * Return: 0 if the transition has been performed correctly,
+ * -EALREADY if the domain is already on,
+ * a negative error code otherwise.
*/
#if CONFIG_IS_ENABLED(POWER_DOMAIN)
-int power_domain_on(struct power_domain *power_domain);
+int power_domain_on_lowlevel(struct power_domain *power_domain);
#else
-static inline int power_domain_on(struct power_domain *power_domain)
+static inline int power_domain_on_lowlevel(struct power_domain *power_domain)
{
return -ENOSYS;
}
#endif
/**
- * power_domain_off - Disable power to a power domain.
+ * power_domain_on - Enable power to a power domain (ignores the actual state
+ * of the power domain)
*
* @power_domain: A power domain struct that was previously successfully
* requested by power_domain_get().
- * Return: 0 if OK, or a negative error code.
+ * Return: a negative error code upon error during the transition, 0 otherwise.
+ */
+static inline int power_domain_on(struct power_domain *power_domain)
+{
+ int ret;
+
+ ret = power_domain_on_lowlevel(power_domain);
+ if (ret == -EALREADY)
+ ret = 0;
+
+ return ret;
+}
+
+/**
+ * power_domain_off_lowlevel - Disable power to a power domain (with refcounting)
+ *
+ * @power_domain: A power domain struct that was previously successfully
+ * requested by power_domain_get().
+ * Return: 0 if the transition has been performed correctly,
+ * -EALREADY if the domain is already off,
+ * -EBUSY if another device is keeping the domain on (but the refcounter
+ * is decremented),
+ * a negative error code otherwise.
*/
#if CONFIG_IS_ENABLED(POWER_DOMAIN)
-int power_domain_off(struct power_domain *power_domain);
+int power_domain_off_lowlevel(struct power_domain *power_domain);
#else
-static inline int power_domain_off(struct power_domain *power_domain)
+static inline int power_domain_off_lowlevel(struct power_domain *power_domain)
{
return -ENOSYS;
}
#endif
/**
+ * power_domain_off - Disable power to a power domain (ignores the actual state
+ * of the power domain)
+ *
+ * @power_domain: A power domain struct that was previously successfully
+ * requested by power_domain_get().
+ * Return: a negative error code upon error during the transition, 0 otherwise.
+ */
+static inline int power_domain_off(struct power_domain *power_domain)
+{
+ int ret;
+
+ ret = power_domain_off_lowlevel(power_domain);
+ if (ret == -EALREADY || ret == -EBUSY)
+ ret = 0;
+
+ return ret;
+}
+
+/**
* dev_power_domain_on - Enable power domains for a device .
*
* @dev: The client device.
diff --git a/include/power/cpcap.h b/include/power/cpcap.h
new file mode 100644
index 0000000..bb0e28c
--- /dev/null
+++ b/include/power/cpcap.h
@@ -0,0 +1,373 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+#ifndef _CPCAP_H_
+#define _CPCAP_H_
+
+#define CPCAP_VENDOR_ST 0
+#define CPCAP_VENDOR_TI 1
+
+#define CPCAP_REVISION_MAJOR(r) (((r) >> 4) + 1)
+#define CPCAP_REVISION_MINOR(r) ((r) & 0xf)
+
+#define CPCAP_REVISION_1_0 0x08
+#define CPCAP_REVISION_1_1 0x09
+#define CPCAP_REVISION_2_0 0x10
+#define CPCAP_REVISION_2_1 0x11
+#define CPCAP_REVISION_3_1 0x19
+
+/* CPCAP registers */
+#define CPCAP_REG_INT1 0x0000 /* Interrupt 1 */
+#define CPCAP_REG_INT2 0x0004 /* Interrupt 2 */
+#define CPCAP_REG_INT3 0x0008 /* Interrupt 3 */
+#define CPCAP_REG_INT4 0x000c /* Interrupt 4 */
+#define CPCAP_REG_INTM1 0x0010 /* Interrupt Mask 1 */
+#define CPCAP_REG_INTM2 0x0014 /* Interrupt Mask 2 */
+#define CPCAP_REG_INTM3 0x0018 /* Interrupt Mask 3 */
+#define CPCAP_REG_INTM4 0x001c /* Interrupt Mask 4 */
+#define CPCAP_REG_INTS1 0x0020 /* Interrupt Sense 1 */
+#define CPCAP_REG_INTS2 0x0024 /* Interrupt Sense 2 */
+#define CPCAP_REG_INTS3 0x0028 /* Interrupt Sense 3 */
+#define CPCAP_REG_INTS4 0x002c /* Interrupt Sense 4 */
+#define CPCAP_REG_ASSIGN1 0x0030 /* Resource Assignment 1 */
+#define CPCAP_REG_ASSIGN2 0x0034 /* Resource Assignment 2 */
+#define CPCAP_REG_ASSIGN3 0x0038 /* Resource Assignment 3 */
+#define CPCAP_REG_ASSIGN4 0x003c /* Resource Assignment 4 */
+#define CPCAP_REG_ASSIGN5 0x0040 /* Resource Assignment 5 */
+#define CPCAP_REG_ASSIGN6 0x0044 /* Resource Assignment 6 */
+#define CPCAP_REG_VERSC1 0x0048 /* Version Control 1 */
+#define CPCAP_REG_VERSC2 0x004c /* Version Control 2 */
+
+#define CPCAP_REG_MI1 0x0200 /* Macro Interrupt 1 */
+#define CPCAP_REG_MIM1 0x0204 /* Macro Interrupt Mask 1 */
+#define CPCAP_REG_MI2 0x0208 /* Macro Interrupt 2 */
+#define CPCAP_REG_MIM2 0x020c /* Macro Interrupt Mask 2 */
+#define CPCAP_REG_UCC1 0x0210 /* UC Control 1 */
+#define CPCAP_REG_UCC2 0x0214 /* UC Control 2 */
+
+#define CPCAP_REG_PC1 0x021c /* Power Cut 1 */
+#define CPCAP_REG_PC2 0x0220 /* Power Cut 2 */
+#define CPCAP_REG_BPEOL 0x0224 /* BP and EOL */
+#define CPCAP_REG_PGC 0x0228 /* Power Gate and Control */
+#define CPCAP_REG_MT1 0x022c /* Memory Transfer 1 */
+#define CPCAP_REG_MT2 0x0230 /* Memory Transfer 2 */
+#define CPCAP_REG_MT3 0x0234 /* Memory Transfer 3 */
+#define CPCAP_REG_PF 0x0238 /* Print Format */
+
+#define CPCAP_REG_SCC 0x0400 /* System Clock Control */
+#define CPCAP_REG_SW1 0x0404 /* Stop Watch 1 */
+#define CPCAP_REG_SW2 0x0408 /* Stop Watch 2 */
+#define CPCAP_REG_UCTM 0x040c /* UC Turbo Mode */
+#define CPCAP_REG_TOD1 0x0410 /* Time of Day 1 */
+#define CPCAP_REG_TOD2 0x0414 /* Time of Day 2 */
+#define CPCAP_REG_TODA1 0x0418 /* Time of Day Alarm 1 */
+#define CPCAP_REG_TODA2 0x041c /* Time of Day Alarm 2 */
+#define CPCAP_REG_DAY 0x0420 /* Day */
+#define CPCAP_REG_DAYA 0x0424 /* Day Alarm */
+#define CPCAP_REG_VAL1 0x0428 /* Validity 1 */
+#define CPCAP_REG_VAL2 0x042c /* Validity 2 */
+
+#define CPCAP_REG_SDVSPLL 0x0600 /* Switcher DVS and PLL */
+#define CPCAP_REG_SI2CC1 0x0604 /* Switcher I2C Control 1 */
+#define CPCAP_REG_Si2CC2 0x0608 /* Switcher I2C Control 2 */
+#define CPCAP_REG_S1C1 0x060c /* Switcher 1 Control 1 */
+#define CPCAP_REG_S1C2 0x0610 /* Switcher 1 Control 2 */
+#define CPCAP_REG_S2C1 0x0614 /* Switcher 2 Control 1 */
+#define CPCAP_REG_S2C2 0x0618 /* Switcher 2 Control 2 */
+#define CPCAP_REG_S3C 0x061c /* Switcher 3 Control */
+#define CPCAP_REG_S4C1 0x0620 /* Switcher 4 Control 1 */
+#define CPCAP_REG_S4C2 0x0624 /* Switcher 4 Control 2 */
+#define CPCAP_REG_S5C 0x0628 /* Switcher 5 Control */
+#define CPCAP_REG_S6C 0x062c /* Switcher 6 Control */
+#define CPCAP_REG_VCAMC 0x0630 /* VCAM Control */
+#define CPCAP_REG_VCSIC 0x0634 /* VCSI Control */
+#define CPCAP_REG_VDACC 0x0638 /* VDAC Control */
+#define CPCAP_REG_VDIGC 0x063c /* VDIG Control */
+#define CPCAP_REG_VFUSEC 0x0640 /* VFUSE Control */
+#define CPCAP_REG_VHVIOC 0x0644 /* VHVIO Control */
+#define CPCAP_REG_VSDIOC 0x0648 /* VSDIO Control */
+#define CPCAP_REG_VPLLC 0x064c /* VPLL Control */
+#define CPCAP_REG_VRF1C 0x0650 /* VRF1 Control */
+#define CPCAP_REG_VRF2C 0x0654 /* VRF2 Control */
+#define CPCAP_REG_VRFREFC 0x0658 /* VRFREF Control */
+#define CPCAP_REG_VWLAN1C 0x065c /* VWLAN1 Control */
+#define CPCAP_REG_VWLAN2C 0x0660 /* VWLAN2 Control */
+#define CPCAP_REG_VSIMC 0x0664 /* VSIM Control */
+#define CPCAP_REG_VVIBC 0x0668 /* VVIB Control */
+#define CPCAP_REG_VUSBC 0x066c /* VUSB Control */
+#define CPCAP_REG_VUSBINT1C 0x0670 /* VUSBINT1 Control */
+#define CPCAP_REG_VUSBINT2C 0x0674 /* VUSBINT2 Control */
+#define CPCAP_REG_URT 0x0678 /* Useroff Regulator Trigger */
+#define CPCAP_REG_URM1 0x067c /* Useroff Regulator Mask 1 */
+#define CPCAP_REG_URM2 0x0680 /* Useroff Regulator Mask 2 */
+
+#define CPCAP_REG_VAUDIOC 0x0800 /* VAUDIO Control */
+#define CPCAP_REG_CC 0x0804 /* Codec Control */
+#define CPCAP_REG_CDI 0x0808 /* Codec Digital Interface */
+#define CPCAP_REG_SDAC 0x080c /* Stereo DAC */
+#define CPCAP_REG_SDACDI 0x0810 /* Stereo DAC Digital Interface */
+#define CPCAP_REG_TXI 0x0814 /* TX Inputs */
+#define CPCAP_REG_TXMP 0x0818 /* TX MIC PGA's */
+#define CPCAP_REG_RXOA 0x081c /* RX Output Amplifiers */
+#define CPCAP_REG_RXVC 0x0820 /* RX Volume Control */
+#define CPCAP_REG_RXCOA 0x0824 /* RX Codec to Output Amps */
+#define CPCAP_REG_RXSDOA 0x0828 /* RX Stereo DAC to Output Amps */
+#define CPCAP_REG_RXEPOA 0x082c /* RX External PGA to Output Amps */
+#define CPCAP_REG_RXLL 0x0830 /* RX Low Latency */
+#define CPCAP_REG_A2LA 0x0834 /* A2 Loudspeaker Amplifier */
+#define CPCAP_REG_MIPIS1 0x0838 /* MIPI Slimbus 1 */
+#define CPCAP_REG_MIPIS2 0x083c /* MIPI Slimbus 2 */
+#define CPCAP_REG_MIPIS3 0x0840 /* MIPI Slimbus 3. */
+#define CPCAP_REG_LVAB 0x0844 /* LMR Volume and A4 Balanced. */
+
+#define CPCAP_REG_CCC1 0x0a00 /* Coulomb Counter Control 1 */
+#define CPCAP_REG_CRM 0x0a04 /* Charger and Reverse Mode */
+#define CPCAP_REG_CCCC2 0x0a08 /* Coincell and Coulomb Ctr Ctrl 2 */
+#define CPCAP_REG_CCS1 0x0a0c /* Coulomb Counter Sample 1 */
+#define CPCAP_REG_CCS2 0x0a10 /* Coulomb Counter Sample 2 */
+#define CPCAP_REG_CCA1 0x0a14 /* Coulomb Counter Accumulator 1 */
+#define CPCAP_REG_CCA2 0x0a18 /* Coulomb Counter Accumulator 2 */
+#define CPCAP_REG_CCM 0x0a1c /* Coulomb Counter Mode */
+#define CPCAP_REG_CCO 0x0a20 /* Coulomb Counter Offset */
+#define CPCAP_REG_CCI 0x0a24 /* Coulomb Counter Integrator */
+
+#define CPCAP_REG_ADCC1 0x0c00 /* A/D Converter Configuration 1 */
+#define CPCAP_REG_ADCC2 0x0c04 /* A/D Converter Configuration 2 */
+#define CPCAP_REG_ADCD0 0x0c08 /* A/D Converter Data 0 */
+#define CPCAP_REG_ADCD1 0x0c0c /* A/D Converter Data 1 */
+#define CPCAP_REG_ADCD2 0x0c10 /* A/D Converter Data 2 */
+#define CPCAP_REG_ADCD3 0x0c14 /* A/D Converter Data 3 */
+#define CPCAP_REG_ADCD4 0x0c18 /* A/D Converter Data 4 */
+#define CPCAP_REG_ADCD5 0x0c1c /* A/D Converter Data 5 */
+#define CPCAP_REG_ADCD6 0x0c20 /* A/D Converter Data 6 */
+#define CPCAP_REG_ADCD7 0x0c24 /* A/D Converter Data 7 */
+#define CPCAP_REG_ADCAL1 0x0c28 /* A/D Converter Calibration 1 */
+#define CPCAP_REG_ADCAL2 0x0c2c /* A/D Converter Calibration 2 */
+
+#define CPCAP_REG_USBC1 0x0e00 /* USB Control 1 */
+#define CPCAP_REG_USBC2 0x0e04 /* USB Control 2 */
+#define CPCAP_REG_USBC3 0x0e08 /* USB Control 3 */
+#define CPCAP_REG_UVIDL 0x0e0c /* ULPI Vendor ID Low */
+#define CPCAP_REG_UVIDH 0x0e10 /* ULPI Vendor ID High */
+#define CPCAP_REG_UPIDL 0x0e14 /* ULPI Product ID Low */
+#define CPCAP_REG_UPIDH 0x0e18 /* ULPI Product ID High */
+#define CPCAP_REG_UFC1 0x0e1c /* ULPI Function Control 1 */
+#define CPCAP_REG_UFC2 0x0e20 /* ULPI Function Control 2 */
+#define CPCAP_REG_UFC3 0x0e24 /* ULPI Function Control 3 */
+#define CPCAP_REG_UIC1 0x0e28 /* ULPI Interface Control 1 */
+#define CPCAP_REG_UIC2 0x0e2c /* ULPI Interface Control 2 */
+#define CPCAP_REG_UIC3 0x0e30 /* ULPI Interface Control 3 */
+#define CPCAP_REG_USBOTG1 0x0e34 /* USB OTG Control 1 */
+#define CPCAP_REG_USBOTG2 0x0e38 /* USB OTG Control 2 */
+#define CPCAP_REG_USBOTG3 0x0e3c /* USB OTG Control 3 */
+#define CPCAP_REG_UIER1 0x0e40 /* USB Interrupt Enable Rising 1 */
+#define CPCAP_REG_UIER2 0x0e44 /* USB Interrupt Enable Rising 2 */
+#define CPCAP_REG_UIER3 0x0e48 /* USB Interrupt Enable Rising 3 */
+#define CPCAP_REG_UIEF1 0x0e4c /* USB Interrupt Enable Falling 1 */
+#define CPCAP_REG_UIEF2 0x0e50 /* USB Interrupt Enable Falling 1 */
+#define CPCAP_REG_UIEF3 0x0e54 /* USB Interrupt Enable Falling 1 */
+#define CPCAP_REG_UIS 0x0e58 /* USB Interrupt Status */
+#define CPCAP_REG_UIL 0x0e5c /* USB Interrupt Latch */
+#define CPCAP_REG_USBD 0x0e60 /* USB Debug */
+#define CPCAP_REG_SCR1 0x0e64 /* Scratch 1 */
+#define CPCAP_REG_SCR2 0x0e68 /* Scratch 2 */
+#define CPCAP_REG_SCR3 0x0e6c /* Scratch 3 */
+
+#define CPCAP_REG_VMC 0x0eac /* Video Mux Control */
+#define CPCAP_REG_OWDC 0x0eb0 /* One Wire Device Control */
+#define CPCAP_REG_GPIO0 0x0eb4 /* GPIO 0 Control */
+
+#define CPCAP_REG_GPIO1 0x0ebc /* GPIO 1 Control */
+
+#define CPCAP_REG_GPIO2 0x0ec4 /* GPIO 2 Control */
+
+#define CPCAP_REG_GPIO3 0x0ecc /* GPIO 3 Control */
+
+#define CPCAP_REG_GPIO4 0x0ed4 /* GPIO 4 Control */
+
+#define CPCAP_REG_GPIO5 0x0edc /* GPIO 5 Control */
+
+#define CPCAP_REG_GPIO6 0x0ee4 /* GPIO 6 Control */
+
+#define CPCAP_REG_MDLC 0x1000 /* Main Display Lighting Control */
+#define CPCAP_REG_KLC 0x1004 /* Keypad Lighting Control */
+#define CPCAP_REG_ADLC 0x1008 /* Aux Display Lighting Control */
+#define CPCAP_REG_REDC 0x100c /* Red Triode Control */
+#define CPCAP_REG_GREENC 0x1010 /* Green Triode Control */
+#define CPCAP_REG_BLUEC 0x1014 /* Blue Triode Control */
+#define CPCAP_REG_CFC 0x1018 /* Camera Flash Control */
+#define CPCAP_REG_ABC 0x101c /* Adaptive Boost Control */
+#define CPCAP_REG_BLEDC 0x1020 /* Bluetooth LED Control */
+#define CPCAP_REG_CLEDC 0x1024 /* Camera Privacy LED Control */
+
+#define CPCAP_REG_OW1C 0x1200 /* One Wire 1 Command */
+#define CPCAP_REG_OW1D 0x1204 /* One Wire 1 Data */
+#define CPCAP_REG_OW1I 0x1208 /* One Wire 1 Interrupt */
+#define CPCAP_REG_OW1IE 0x120c /* One Wire 1 Interrupt Enable */
+
+#define CPCAP_REG_OW1 0x1214 /* One Wire 1 Control */
+
+#define CPCAP_REG_OW2C 0x1220 /* One Wire 2 Command */
+#define CPCAP_REG_OW2D 0x1224 /* One Wire 2 Data */
+#define CPCAP_REG_OW2I 0x1228 /* One Wire 2 Interrupt */
+#define CPCAP_REG_OW2IE 0x122c /* One Wire 2 Interrupt Enable */
+
+#define CPCAP_REG_OW2 0x1234 /* One Wire 2 Control */
+
+#define CPCAP_REG_OW3C 0x1240 /* One Wire 3 Command */
+#define CPCAP_REG_OW3D 0x1244 /* One Wire 3 Data */
+#define CPCAP_REG_OW3I 0x1248 /* One Wire 3 Interrupt */
+#define CPCAP_REG_OW3IE 0x124c /* One Wire 3 Interrupt Enable */
+
+#define CPCAP_REG_OW3 0x1254 /* One Wire 3 Control */
+#define CPCAP_REG_GCAIC 0x1258 /* GCAI Clock Control */
+#define CPCAP_REG_GCAIM 0x125c /* GCAI GPIO Mode */
+#define CPCAP_REG_LGDIR 0x1260 /* LMR GCAI GPIO Direction */
+#define CPCAP_REG_LGPU 0x1264 /* LMR GCAI GPIO Pull-up */
+#define CPCAP_REG_LGPIN 0x1268 /* LMR GCAI GPIO Pin */
+#define CPCAP_REG_LGMASK 0x126c /* LMR GCAI GPIO Mask */
+#define CPCAP_REG_LDEB 0x1270 /* LMR Debounce Settings */
+#define CPCAP_REG_LGDET 0x1274 /* LMR GCAI Detach Detect */
+#define CPCAP_REG_LMISC 0x1278 /* LMR Misc Bits */
+#define CPCAP_REG_LMACE 0x127c /* LMR Mace IC Support */
+
+#define CPCAP_REG_TEST 0x7c00 /* Test */
+
+#define CPCAP_REG_ST_TEST1 0x7d08 /* ST Test1 */
+
+#define CPCAP_REG_ST_TEST2 0x7d18 /* ST Test2 */
+
+/* Drivers name */
+#define CPCAP_LDO_DRIVER "cpcap_ldo"
+#define CPCAP_SW_DRIVER "cpcap_sw"
+
+enum cpcap_regulator_id {
+ CPCAP_SW1,
+ CPCAP_SW2,
+ CPCAP_SW3,
+ CPCAP_SW4,
+ CPCAP_SW5,
+ CPCAP_SW6,
+ CPCAP_VCAM,
+ CPCAP_VCSI,
+ CPCAP_VDAC,
+ CPCAP_VDIG,
+ CPCAP_VFUSE,
+ CPCAP_VHVIO,
+ CPCAP_VSDIO,
+ CPCAP_VPLL,
+ CPCAP_VRF1,
+ CPCAP_VRF2,
+ CPCAP_VRFREF,
+ CPCAP_VWLAN1,
+ CPCAP_VWLAN2,
+ CPCAP_VSIM,
+ CPCAP_VSIMCARD,
+ CPCAP_VVIB,
+ CPCAP_VUSB,
+ CPCAP_VAUDIO,
+ CPCAP_REGULATORS_COUNT,
+};
+
+static const char * const cpcap_regulator_to_name[] = {
+ /* BUCK */
+ [CPCAP_SW1] = "sw1",
+ [CPCAP_SW2] = "sw2",
+ [CPCAP_SW3] = "sw3",
+ [CPCAP_SW4] = "sw4",
+ [CPCAP_SW5] = "sw5",
+ [CPCAP_SW6] = "sw6",
+ /* LDO */
+ [CPCAP_VCAM] = "vcam",
+ [CPCAP_VCSI] = "vcsi",
+ [CPCAP_VDAC] = "vdac",
+ [CPCAP_VDIG] = "vdig",
+ [CPCAP_VFUSE] = "vfuse",
+ [CPCAP_VHVIO] = "vhvio",
+ [CPCAP_VSDIO] = "vsdio",
+ [CPCAP_VPLL] = "vpll",
+ [CPCAP_VRF1] = "vrf1",
+ [CPCAP_VRF2] = "vrf2",
+ [CPCAP_VRFREF] = "vrfref",
+ [CPCAP_VWLAN1] = "vwlan1",
+ [CPCAP_VWLAN2] = "vwlan2",
+ [CPCAP_VSIM] = "vsim",
+ [CPCAP_VSIMCARD] = "vsimcard",
+ [CPCAP_VVIB] = "vvib",
+ [CPCAP_VUSB] = "vusb",
+ [CPCAP_VAUDIO] = "vaudio",
+};
+
+static const u32 unknown_val_tbl[] = { 0, };
+static const u32 sw1_val_tbl[] = { 750000, 762500, 775000, 787500, 800000,
+ 812500, 825000, 837500, 850000, 862500,
+ 875000, 887500, 900000, 912500, 925000,
+ 937500, 950000, 962500, 975000, 987500,
+ 1000000, 1012500, 1025000, 1037500,
+ 1050000, 1062500, 1075000, 1087500,
+ 1100000, 1112500, 1125000, 1137500,
+ 1150000, 1162500, 1175000, 1187500,
+ 1200000, 1212500, 1225000, 1237500,
+ 1250000, 1262500, 1275000, 1287500,
+ 1300000, 1312500, 1325000, 1337500,
+ 1350000, 1362500, 1375000, 1387500,
+ 1400000, 1412500, 1425000, 1437500,
+ 1450000, 1462500, 1475000 };
+static const u32 sw2_sw4_val_tbl[] = { 900000, 912500, 925000, 937500, 950000,
+ 962500, 975000, 987500, 1000000, 1012500,
+ 1025000, 1037500, 1050000, 1062500,
+ 1075000, 1087500, 1100000, 1112500,
+ 1125000, 1137500, 1150000, 1162500,
+ 1175000, 1187500, 1200000, 1212500,
+ 1225000, 1237500, 1250000, 1262500,
+ 1275000, 1287500, 1300000, 1312500,
+ 1325000, 1337500, 1350000, 1362500,
+ 1375000, 1387500, 1400000, 1412500,
+ 1425000, 1437500, 1450000, 1462500,
+ 1475000 };
+static const u32 sw3_val_tbl[] = { 1350000, 1800000, 1850000, 1875000 };
+static const u32 sw5_val_tbl[] = { 0, 5050000 };
+static const u32 vcam_val_tbl[] = { 2600000, 2700000, 2800000, 2900000 };
+static const u32 vcsi_val_tbl[] = { 1200000, 1800000 };
+static const u32 vdac_val_tbl[] = { 1200000, 1500000, 1800000, 2500000 };
+static const u32 vdig_val_tbl[] = { 1200000, 1350000, 1500000, 1875000 };
+static const u32 vfuse_val_tbl[] = { 1500000, 1600000, 1700000, 1800000, 1900000,
+ 2000000, 2100000, 2200000, 2300000, 2400000,
+ 2500000, 2600000, 2700000, 3150000 };
+static const u32 vhvio_val_tbl[] = { 2775000 };
+static const u32 vsdio_val_tbl[] = { 1500000, 1600000, 1800000, 2600000,
+ 2700000, 2800000, 2900000, 3000000 };
+static const u32 vpll_val_tbl[] = { 1200000, 1300000, 1400000, 1800000 };
+static const u32 vrf1_val_tbl[] = { 2775000, 2500000 }; /* Yes, this is correct */
+static const u32 vrf2_val_tbl[] = { 0, 2775000 };
+static const u32 vrfref_val_tbl[] = { 2500000, 2775000 };
+static const u32 vwlan1_val_tbl[] = { 1800000, 1900000 };
+static const u32 vwlan2_val_tbl[] = { 2775000, 3000000, 3300000, 3300000 };
+static const u32 vsim_val_tbl[] = { 1800000, 2900000 };
+static const u32 vsimcard_val_tbl[] = { 1800000, 2900000 };
+static const u32 vvib_val_tbl[] = { 1300000, 1800000, 2000000, 3000000 };
+static const u32 vusb_val_tbl[] = { 0, 3300000 };
+static const u32 vaudio_val_tbl[] = { 0, 2775000 };
+
+struct cpcap_regulator_data {
+ u16 reg;
+ u16 assignment_reg;
+ u16 assignment_mask;
+ u16 mode_mask;
+ u16 volt_mask;
+ u8 volt_shft;
+ u16 mode_val;
+ u16 off_mode_val;
+ u32 val_tbl_sz;
+ const u32 *val_tbl;
+ u32 mode_cntr;
+ u32 volt_trans_time; /* in micro seconds */
+ u32 turn_on_time; /* in micro seconds */
+
+ /*
+ * Bit difference between lowest value in val_tbl and start of voltage
+ * table setting in cpcap. Use this for switchers that have many too
+ * many voltages to list in val_tbl.
+ */
+ u32 bit_offset_from_cpcap_lowest_voltage;
+};
+
+#endif /* _CPCAP_H_ */
diff --git a/include/regmap.h b/include/regmap.h
index 22b0434..8c6f7c1 100644
--- a/include/regmap.h
+++ b/include/regmap.h
@@ -362,6 +362,34 @@
int regmap_update_bits(struct regmap *map, uint offset, uint mask, uint val);
/**
+ * regmap_set_bits() - Set bits to a regmap
+ *
+ * @map: Regmap to write bits to
+ * @offset: Offset in the regmap to write to
+ * @bits: Bits to set to the regmap at the specified offset
+ *
+ * Return: 0 if OK, -ve on error
+ */
+static inline int regmap_set_bits(struct regmap *map, uint offset, uint bits)
+{
+ return regmap_update_bits(map, offset, bits, bits);
+}
+
+/**
+ * regmap_clear_bits() - Clear bits to a regmap
+ *
+ * @map: Regmap to write bits to
+ * @offset: Offset in the regmap to write to
+ * @bits: Bits to clear to the regmap at the specified offset
+ *
+ * Return: 0 if OK, -ve on error
+ */
+static inline int regmap_clear_bits(struct regmap *map, uint offset, uint bits)
+{
+ return regmap_update_bits(map, offset, bits, 0);
+}
+
+/**
* regmap_init_mem() - Set up a new register map that uses memory access
*
* @node: Device node that uses this map
diff --git a/include/scsi.h b/include/scsi.h
index b18ae37..ab53b47 100644
--- a/include/scsi.h
+++ b/include/scsi.h
@@ -9,6 +9,7 @@
#include <asm/cache.h>
#include <bouncebuf.h>
#include <linux/dma-direction.h>
+#include <part.h>
struct udevice;
@@ -181,6 +182,7 @@
#define SCSI_WRT_VERIFY 0x2E /* Write and Verify (O) */
#define SCSI_WRITE_LONG 0x3F /* Write Long (O) */
#define SCSI_WRITE_SAME 0x41 /* Write Same (O) */
+#define SCSI_UNMAP 0x42 /* Write 10-Byte (MANDATORY) */
/**
* enum scsi_cmd_phase - current phase of the SCSI protocol
diff --git a/include/sdhci.h b/include/sdhci.h
index 31a49ca..2372697 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -518,6 +518,7 @@
/* Export the operations to drivers */
int sdhci_probe(struct udevice *dev);
int sdhci_set_clock(struct mmc *mmc, unsigned int clock);
+void sdhci_set_voltage(struct sdhci_host *host);
/**
* sdhci_set_control_reg - Set control registers
diff --git a/include/setjmp.h b/include/setjmp.h
index 37d3a8a..32dd488 100644
--- a/include/setjmp.h
+++ b/include/setjmp.h
@@ -3,12 +3,27 @@
#ifndef _SETJMP_H_
#define _SETJMP_H_ 1
+/**
+ * DOC: Overview
+ *
+ * The long jump API allows to perform nonlocal gotos, that is jump from one
+ * function to another typically further down in the stack, while properly
+ * restoring the stack's state (unwinding). The two functions needed to do this
+ * are setjmp() and longjmp().
+ *
+ * In addition to these two standard POSIX.1-2001/C89 functions, a third one is
+ * present in U-Boot: initjmp(). It is an extension which allows to implement
+ * user-mode threads.
+ */
+
#ifdef CONFIG_HAVE_SETJMP
#include <asm/setjmp.h>
#else
struct jmp_buf_data {
};
#endif
+#include <linux/compiler_attributes.h>
+#include <stddef.h>
/**
* typedef jmp_buf - information needed to restore a calling environment
@@ -37,4 +52,21 @@
*/
void longjmp(jmp_buf env, int val);
+/**
+ * initjmp() - prepare for a long jump to a given function with a given stack
+ *
+ * This function sets up a jump buffer for later use with longjmp(). It allows
+ * to branch to a specific function with a specific stack. Please note that
+ * @func MUST NOT return. It shall typically restore the main stack and resume
+ * execution by doing a long jump to a jump buffer initialized by setjmp()
+ * before the long jump. initjmp() allows to implement multithreading.
+ *
+ * @env: jump buffer
+ * @func: function to be called on longjmp(), MUST NOT RETURN
+ * @stack_base: the stack to be used by @func (lower address)
+ * @stack_sz: the stack size in bytes
+ */
+int initjmp(jmp_buf env, void __noreturn (*func)(void), void *stack_base,
+ size_t stack_sz);
+
#endif /* _SETJMP_H_ */
diff --git a/include/spi.h b/include/spi.h
index 6944773..2783200 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -11,6 +11,8 @@
#include <linux/bitops.h>
+struct spinand_info;
+
/* SPI mode flags */
#define SPI_CPHA BIT(0) /* clock phase (1 = SPI_CLOCK_PHASE_SECOND) */
#define SPI_CPOL BIT(1) /* clock polarity (1 = SPI_POLARITY_HIGH) */
@@ -537,6 +539,16 @@
*/
int (*get_mmap)(struct udevice *dev, ulong *map_basep,
uint *map_sizep, uint *offsetp);
+
+ /**
+ * setup_for_spinand() - Setup the SPI for attached SPI NAND
+ *
+ * @dev: The SPI flash slave device
+ * @spinand_info: The SPI NAND info to configure for
+ * @return 0 if OK, -ve value on error
+ */
+ int (*setup_for_spinand)(struct spi_slave *slave,
+ const struct spinand_info *spinand_info);
};
struct dm_spi_emul_ops {
diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h
index 122987c..12b54c8 100644
--- a/include/sunxi_gpio.h
+++ b/include/sunxi_gpio.h
@@ -82,7 +82,6 @@
SUNXI_GPIO_L_START = 352,
SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),
SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M),
- SUNXI_GPIO_AXP0_START = 1024,
};
/* SUNXI GPIO number definitions */
@@ -99,8 +98,6 @@
#define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr))
#define SUNXI_GPN(_nr) (SUNXI_GPIO_N_START + (_nr))
-#define SUNXI_GPAXP0(_nr) (SUNXI_GPIO_AXP0_START + (_nr))
-
/* GPIO pin function config */
#define SUNXI_GPIO_INPUT 0
#define SUNXI_GPIO_OUTPUT 1
@@ -185,11 +182,6 @@
#define SUNXI_GPIO_PULL_UP 1
#define SUNXI_GPIO_PULL_DOWN 2
-/* Virtual AXP0 GPIOs */
-#define SUNXI_GPIO_AXP0_PREFIX "AXP0-"
-#define SUNXI_GPIO_AXP0_VBUS_ENABLE 5
-#define SUNXI_GPIO_AXP0_GPIO_COUNT 6
-
struct sunxi_gpio_plat {
void *regs;
char bank_name[3];
diff --git a/include/u-boot/schedule.h b/include/u-boot/schedule.h
index 4fd34c4..4605971 100644
--- a/include/u-boot/schedule.h
+++ b/include/u-boot/schedule.h
@@ -3,6 +3,8 @@
#ifndef _U_BOOT_SCHEDULE_H
#define _U_BOOT_SCHEDULE_H
+#include <uthread.h>
+
#if CONFIG_IS_ENABLED(CYCLIC)
/**
* schedule() - Schedule all potentially waiting tasks
@@ -17,6 +19,7 @@
static inline void schedule(void)
{
+ uthread_schedule();
}
#endif
diff --git a/include/uthread.h b/include/uthread.h
new file mode 100644
index 0000000..11a19aa
--- /dev/null
+++ b/include/uthread.h
@@ -0,0 +1,188 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2025 Linaro Limited
+ */
+
+#include <linux/list.h>
+#include <linux/types.h>
+#include <setjmp.h>
+
+#ifndef _UTHREAD_H_
+#define _UTHREAD_H_
+
+/**
+ * DOC: Overview
+ *
+ * The uthread framework is a basic task scheduler that allows to run functions
+ * "in parallel" on a single CPU core. The scheduling is cooperative, not
+ * preemptive -- meaning that context switches from one task to another task is
+ * voluntary, via a call to uthread_schedule(). This characteristic makes thread
+ * synchronization much easier, because a thread cannot be interrupted in the
+ * middle of a critical section (reading from or writing to shared state, for
+ * instance).
+ *
+ * CONFIG_UTHREAD in lib/Kconfig enables the uthread framework. When disabled,
+ * the uthread_create() and uthread_schedule() functions may still be used so
+ * that code differences between uthreads enabled and disabled can be reduced to
+ * a minimum.
+ */
+
+/**
+ * struct uthread - a thread object
+ *
+ * @fn: thread entry point
+ * @arg: argument passed to the entry point when the thread is started
+ * @ctx: context to resume execution of this thread (via longjmp())
+ * @stack: initial stack pointer for the thread
+ * @done: true once @fn has returned, false otherwise
+ * @grp_id: user-supplied identifier for this thread and possibly others. A
+ * thread can belong to zero or one group (not more), and a group may contain
+ * any number of threads.
+ * @list: link in the global scheduler list
+ */
+struct uthread {
+ void (*fn)(void *arg);
+ void *arg;
+ jmp_buf ctx;
+ void *stack;
+ bool done;
+ unsigned int grp_id;
+ struct list_head list;
+};
+
+/**
+ * enum uthread_mutex_state - internal state of a struct uthread_mutex
+ *
+ * @UTHREAD_MUTEX_UNLOCKED: mutex has no owner
+ * @UTHREAD_MUTEX_LOCKED: mutex has one owner
+ */
+enum uthread_mutex_state {
+ UTHREAD_MUTEX_UNLOCKED = 0,
+ UTHREAD_MUTEX_LOCKED = 1
+};
+
+/**
+ * struct uthread_mutex - a mutex object
+ *
+ * @state: the internal state of the mutex
+ */
+struct uthread_mutex {
+ enum uthread_mutex_state state;
+};
+
+#define UTHREAD_MUTEX_INITIALIZER { .state = UTHREAD_MUTEX_UNLOCKED }
+
+#ifdef CONFIG_UTHREAD
+
+/**
+ * uthread_create() - Create a uthread object and make it ready for execution
+ *
+ * Threads are automatically deleted when they return from their entry point.
+ *
+ * @uthr: a pointer to a user-allocated uthread structure to store information
+ * about the new thread, or NULL to let the framework allocate and manage its
+ * own structure.
+ * @fn: the thread's entry point
+ * @arg: argument passed to the thread's entry point
+ * @stack_sz: stack size for the new thread (in bytes). The stack is allocated
+ * on the heap.
+ * @grp_id: an optional thread group ID that the new thread should belong to
+ * (zero for no group)
+ */
+int uthread_create(struct uthread *uthr, void (*fn)(void *), void *arg,
+ size_t stack_sz, unsigned int grp_id);
+/**
+ * uthread_schedule() - yield the CPU to the next runnable thread
+ *
+ * This function is called either by the main thread or any secondary thread
+ * (that is, any thread created via uthread_create()) to switch execution to
+ * the next runnable thread.
+ *
+ * Return: true if a thread was scheduled, false if no runnable thread was found
+ */
+bool uthread_schedule(void);
+/**
+ * uthread_grp_new_id() - return a new ID for a thread group
+ *
+ * Return: the new thread group ID
+ */
+unsigned int uthread_grp_new_id(void);
+/**
+ * uthread_grp_done() - test if all threads in a group are done
+ *
+ * @grp_id: the ID of the thread group that should be considered
+ * Return: false if the group contains at least one runnable thread (i.e., one
+ * thread which entry point has not returned yet), true otherwise
+ */
+bool uthread_grp_done(unsigned int grp_id);
+
+/**
+ * uthread_mutex_lock() - lock a mutex
+ *
+ * If the cwmutexlock is available (i.e., not owned by any other thread), then
+ * it is locked for use by the current thread. Otherwise the current thread
+ * blocks: it enters a wait loop by scheduling other threads until the mutex
+ * becomes unlocked.
+ *
+ * @mutex: pointer to the mutex to lock
+ * Return: 0 on success, in which case the lock is owned by the calling thread.
+ * != 0 otherwise (the lock is not owned by the calling thread).
+ */
+int uthread_mutex_lock(struct uthread_mutex *mutex);
+
+/**
+ * uthread_mutex_trylock() - lock a mutex if not currently locked
+ *
+ * Similar to uthread_mutex_lock() except return immediately if the mutex is
+ * locked already.
+ *
+ * @mutex: pointer to the mutex to lock
+ * Return: 0 on success, in which case the lock is owned by the calling thread.
+ * EBUSY if the mutex is already locked by another thread. Any other non-zero
+ * value on error.
+ */
+int uthread_mutex_trylock(struct uthread_mutex *mutex);
+
+/**
+ * uthread_mutex_unlock() - unlock a mutex
+ *
+ * The mutex is assumed to be owned by the calling thread on entry. On exit, it
+ * is unlocked.
+ *
+ * @mutex: pointer to the mutex to unlock
+ * Return: 0 on success, != 0 on error
+ */
+int uthread_mutex_unlock(struct uthread_mutex *mutex);
+
+#else
+
+static inline int uthread_create(struct uthread *uthr, void (*fn)(void *),
+ void *arg, size_t stack_sz,
+ unsigned int grp_id)
+{
+ fn(arg);
+ return 0;
+}
+
+static inline bool uthread_schedule(void)
+{
+ return false;
+}
+
+static inline unsigned int uthread_grp_new_id(void)
+{
+ return 0;
+}
+
+static inline bool uthread_grp_done(unsigned int grp_id)
+{
+ return true;
+}
+
+/* These are macros for convenience on the caller side */
+#define uthread_mutex_lock(_mutex) ({ 0; })
+#define uthread_mutex_trylock(_mutex) ({ 0 })
+#define uthread_mutex_unlock(_mutex) ({ 0; })
+
+#endif /* CONFIG_UTHREAD */
+#endif /* _UTHREAD_H_ */
diff --git a/include/video.h b/include/video.h
index a1f7fd7..2fe2f73 100644
--- a/include/video.h
+++ b/include/video.h
@@ -85,6 +85,11 @@
* @fb_size: Frame buffer size
* @copy_fb: Copy of the frame buffer to keep up to date; see struct
* video_uc_plat
+ * @damage: A bounding box of framebuffer regions updated since last sync
+ * @damage.xstart: X start position in pixels from the left
+ * @damage.ystart: Y start position in pixels from the top
+ * @damage.xend: X end position in pixels from the left
+ * @damage.xend: Y end position in pixels from the top
* @line_length: Length of each frame buffer line, in bytes. This can be
* set by the driver, but if not, the uclass will set it after
* probing
@@ -113,6 +118,12 @@
void *fb;
int fb_size;
void *copy_fb;
+ struct {
+ int xstart;
+ int ystart;
+ int xend;
+ int yend;
+ } damage;
int line_length;
u32 colour_fg;
u32 colour_bg;
@@ -259,8 +270,9 @@
* @return: 0 on success, error code otherwise
*
* Some frame buffers are cached or have a secondary frame buffer. This
- * function syncs these up so that the current contents of the U-Boot frame
- * buffer are displayed to the user.
+ * function syncs the damaged parts of them up so that the current contents
+ * of the U-Boot frame buffer are displayed to the user. It clears the damage
+ * buffer.
*/
int video_sync(struct udevice *vid, bool force);
@@ -343,42 +355,29 @@
*/
int video_default_font_height(struct udevice *dev);
-#ifdef CONFIG_VIDEO_COPY
+#ifdef CONFIG_VIDEO_DAMAGE
/**
- * vidconsole_sync_copy() - Sync back to the copy framebuffer
+ * video_damage() - Notify the video subsystem about screen updates.
*
- * This ensures that the copy framebuffer has the same data as the framebuffer
- * for a particular region. It should be called after the framebuffer is updated
- *
- * @from and @to can be in either order. The region between them is synced.
- *
- * @dev: Vidconsole device being updated
- * @from: Start/end address within the framebuffer (->fb)
- * @to: Other address within the frame buffer
- * Return: 0 if OK, -EFAULT if the start address is before the start of the
- * frame buffer start
- */
-int video_sync_copy(struct udevice *dev, void *from, void *to);
-
-/**
- * video_sync_copy_all() - Sync the entire framebuffer to the copy
+ * @vid: Device to sync
+ * @x: Upper left X coordinate of the damaged rectangle
+ * @y: Upper left Y coordinate of the damaged rectangle
+ * @width: Width of the damaged rectangle
+ * @height: Height of the damaged rectangle
*
- * @dev: Vidconsole device being updated
- * Return: 0 (always)
+ * Some frame buffers are cached or have a secondary frame buffer. This
+ * function notifies the video subsystem about rectangles that were updated
+ * within the frame buffer. They may only get written to the screen on the
+ * next call to video_sync().
*/
-int video_sync_copy_all(struct udevice *dev);
+void video_damage(struct udevice *vid, int x, int y, int width, int height);
#else
-static inline int video_sync_copy(struct udevice *dev, void *from, void *to)
+static inline void video_damage(struct udevice *vid, int x, int y, int width,
+ int height)
{
- return 0;
+ return;
}
-
-static inline int video_sync_copy_all(struct udevice *dev)
-{
- return 0;
-}
-
-#endif
+#endif /* CONFIG_VIDEO_DAMAGE */
/**
* video_is_active() - Test if one video device it active
diff --git a/include/video_console.h b/include/video_console.h
index 723d231..13197fa 100644
--- a/include/video_console.h
+++ b/include/video_console.h
@@ -537,56 +537,4 @@
*/
int vidconsole_get_font_size(struct udevice *dev, const char **name, uint *sizep);
-#ifdef CONFIG_VIDEO_COPY
-/**
- * vidconsole_sync_copy() - Sync back to the copy framebuffer
- *
- * This ensures that the copy framebuffer has the same data as the framebuffer
- * for a particular region. It should be called after the framebuffer is updated
- *
- * @from and @to can be in either order. The region between them is synced.
- *
- * @dev: Vidconsole device being updated
- * @from: Start/end address within the framebuffer (->fb)
- * @to: Other address within the frame buffer
- * Return: 0 if OK, -EFAULT if the start address is before the start of the
- * frame buffer start
- */
-int vidconsole_sync_copy(struct udevice *dev, void *from, void *to);
-
-/**
- * vidconsole_memmove() - Perform a memmove() within the frame buffer
- *
- * This handles a memmove(), e.g. for scrolling. It also updates the copy
- * framebuffer.
- *
- * @dev: Vidconsole device being updated
- * @dst: Destination address within the framebuffer (->fb)
- * @src: Source address within the framebuffer (->fb)
- * @size: Number of bytes to transfer
- * Return: 0 if OK, -EFAULT if the start address is before the start of the
- * frame buffer start
- */
-int vidconsole_memmove(struct udevice *dev, void *dst, const void *src,
- int size);
-#else
-
-#include <string.h>
-
-static inline int vidconsole_sync_copy(struct udevice *dev, void *from,
- void *to)
-{
- return 0;
-}
-
-static inline int vidconsole_memmove(struct udevice *dev, void *dst,
- const void *src, int size)
-{
- memmove(dst, src, size);
-
- return 0;
-}
-
-#endif
-
#endif
diff --git a/include/xilinx.h b/include/xilinx.h
index e4e2979..c54d6dc 100644
--- a/include/xilinx.h
+++ b/include/xilinx.h
@@ -34,6 +34,8 @@
xilinx_zynq, /* Zynq Family */
xilinx_zynqmp, /* ZynqMP Family */
xilinx_versal, /* Versal Family */
+ xilinx_versal_net, /* Versal NET Family */
+ xilinx_versal2, /* Versal Gen 2 Family */
max_xilinx_type /* insert all new types before this */
} xilinx_family; /* end, typedef xilinx_family */
diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h
index 73198a6..dc06abc 100644
--- a/include/zynqmp_firmware.h
+++ b/include/zynqmp_firmware.h
@@ -457,6 +457,12 @@
int zynqmp_mmio_read(const u32 address, u32 *value);
int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
int zynqmp_pm_feature(const u32 api_id);
+u32 zynqmp_pm_get_bootmode_reg(void);
+int zynqmp_pm_ufs_get_txrx_cfgrdy(u32 *value);
+int zynqmp_pm_ufs_sram_csr_read(u32 *value);
+int zynqmp_pm_ufs_sram_csr_write(u32 *value);
+int zynqmp_pm_ufs_cal_reg(u32 *value);
+u32 zynqmp_pm_get_pmc_multi_boot_reg(void);
/* Type of Config Object */
#define PM_CONFIG_OBJECT_TYPE_BASE 0x1U
@@ -500,4 +506,10 @@
u32 *buf;
};
+#define CRP_BOOT_MODE_REG_NODE 0x30000001
+#define CRP_BOOT_MODE_REG_OFFSET 0x200
+
+#define PM_REG_PMC_GLOBAL_NODE 0x30000004
+#define PMC_MULTI_BOOT_MODE_REG_OFFSET 0x4
+
#endif /* _ZYNQMP_FIRMWARE_H_ */
diff --git a/lib/Kconfig b/lib/Kconfig
index 1795446..b2aecd8 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -317,6 +317,7 @@
config GENERATE_ACPI_TABLE
bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
depends on ACPI
+ select BLOBLIST
select QFW if QEMU
help
The Advanced Configuration and Power Interface (ACPI) specification
@@ -1257,6 +1258,27 @@
enable this config option to distinguish them using
phandles in fdtdec_get_alias_seq() function.
+config UTHREAD
+ bool "Enable thread support"
+ depends on HAVE_INITJMP
+ help
+ Implement a simple form of cooperative multi-tasking based on
+ context-switching via initjmp(), setjmp() and longjmp(). The
+ uthread_ interface enables the main thread of execution to create
+ one or more secondary threads and schedule them until they all have
+ returned. At any point a thread may suspend its execution and
+ schedule another thread, which allows for the efficient multiplexing
+ of leghthy operations.
+
+config UTHREAD_STACK_SIZE
+ int "Default uthread stack size"
+ depends on UTHREAD
+ default 32768
+ help
+ The default stack size for uthreads. Each uthread has its own stack.
+ When the stack_sz argument to uthread_create() is zero then this
+ value is used.
+
endmenu
source "lib/fwu_updates/Kconfig"
diff --git a/lib/Makefile b/lib/Makefile
index 41de267..18ae0cd 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -43,7 +43,6 @@
obj-$(CONFIG_SMBIOS_PARSER) += smbios-parser.o
obj-$(CONFIG_IMAGE_SPARSE) += image-sparse.o
-obj-y += initcall.o
obj-y += ldiv.o
obj-$(CONFIG_XXHASH) += xxhash.o
obj-y += net_utils.o
@@ -71,7 +70,7 @@
obj-$(CONFIG_$(PHASE_)ACPI) += acpi/
obj-$(CONFIG_ECDSA) += ecdsa/
-obj-$(CONFIG_$(XPL_)RSA) += rsa/
+obj-$(CONFIG_$(PHASE_)RSA) += rsa/
obj-$(CONFIG_HASH) += hash-checksum.o
obj-$(CONFIG_BLAKE2) += blake2/blake2b.o
@@ -82,7 +81,7 @@
obj-$(CONFIG_$(PHASE_)SHA512_LEGACY) += sha512.o
obj-$(CONFIG_CRYPT_PW) += crypt/
-obj-$(CONFIG_$(XPL_)ASN1_DECODER_LEGACY) += asn1_decoder.o
+obj-$(CONFIG_$(PHASE_)ASN1_DECODER_LEGACY) += asn1_decoder.o
obj-$(CONFIG_$(PHASE_)ZLIB) += zlib/
obj-$(CONFIG_$(PHASE_)ZSTD) += zstd/
@@ -91,14 +90,14 @@
obj-$(CONFIG_$(PHASE_)LZMA) += lzma/
obj-$(CONFIG_$(PHASE_)LZ4) += lz4_wrapper.o
-obj-$(CONFIG_$(XPL_)LIB_RATIONAL) += rational.o
+obj-$(CONFIG_$(PHASE_)LIB_RATIONAL) += rational.o
obj-$(CONFIG_LIBAVB) += libavb/
obj-$(CONFIG_$(PHASE_)OF_LIBFDT) += libfdt/
obj-$(CONFIG_$(PHASE_)OF_REAL) += fdtdec_common.o fdtdec.o
-obj-$(CONFIG_$(XPL_)MBEDTLS_LIB) += mbedtls/
+obj-$(CONFIG_$(PHASE_)MBEDTLS_LIB) += mbedtls/
obj-$(CONFIG_NET_LWIP) += lwip/
@@ -150,7 +149,7 @@
obj-y += vsprintf.o strto.o
obj-$(CONFIG_SSCANF) += sscanf.o
endif
-obj-$(CONFIG_$(XPL_)OID_REGISTRY) += oid_registry.o
+obj-$(CONFIG_$(PHASE_)OID_REGISTRY) += oid_registry.o
obj-y += abuf.o
obj-y += alist.o
@@ -160,6 +159,8 @@
obj-$(CONFIG_$(PHASE_)SEMIHOSTING) += semihosting.o
+obj-$(CONFIG_UTHREAD) += uthread.o
+
#
# Build a fast OID lookup registry from include/linux/oid_registry.h
#
diff --git a/lib/acpi/Makefile b/lib/acpi/Makefile
index dcca0c6..64f06de 100644
--- a/lib/acpi/Makefile
+++ b/lib/acpi/Makefile
@@ -5,10 +5,10 @@
ifdef CONFIG_$(PHASE_)GENERATE_ACPI_TABLE
-obj-$(CONFIG_$(XPL_)ACPIGEN) += acpigen.o
-obj-$(CONFIG_$(XPL_)ACPIGEN) += acpi_device.o
-obj-$(CONFIG_$(XPL_)ACPIGEN) += acpi_dp.o
-obj-$(CONFIG_$(XPL_)ACPIGEN) += acpi_table.o
+obj-$(CONFIG_$(PHASE_)ACPIGEN) += acpigen.o
+obj-$(CONFIG_$(PHASE_)ACPIGEN) += acpi_device.o
+obj-$(CONFIG_$(PHASE_)ACPIGEN) += acpi_dp.o
+obj-$(CONFIG_$(PHASE_)ACPIGEN) += acpi_table.o
obj-y += acpi_writer.o
# With QEMU the ACPI tables come from there, not from U-Boot
diff --git a/lib/aes/Makefile b/lib/aes/Makefile
index ad6228a..41ebdd0 100644
--- a/lib/aes/Makefile
+++ b/lib/aes/Makefile
@@ -2,4 +2,4 @@
#
# Copyright (c) 2019, Softathome
-obj-$(CONFIG_$(XPL_)FIT_CIPHER) += aes-decrypt.o
+obj-$(CONFIG_$(PHASE_)FIT_CIPHER) += aes-decrypt.o
diff --git a/lib/crypto/Makefile b/lib/crypto/Makefile
index b729824..ac2b9a7 100644
--- a/lib/crypto/Makefile
+++ b/lib/crypto/Makefile
@@ -3,17 +3,17 @@
# Makefile for asymmetric cryptographic keys
#
-obj-$(CONFIG_$(XPL_)ASYMMETRIC_KEY_TYPE) += asymmetric_keys.o
+obj-$(CONFIG_$(PHASE_)ASYMMETRIC_KEY_TYPE) += asymmetric_keys.o
asymmetric_keys-y := asymmetric_type.o
-obj-$(CONFIG_$(XPL_)ASYMMETRIC_PUBLIC_KEY_SUBTYPE) += public_key_helper.o
-obj-$(CONFIG_$(XPL_)ASYMMETRIC_PUBLIC_KEY_LEGACY) += public_key.o
+obj-$(CONFIG_$(PHASE_)ASYMMETRIC_PUBLIC_KEY_SUBTYPE) += public_key_helper.o
+obj-$(CONFIG_$(PHASE_)ASYMMETRIC_PUBLIC_KEY_LEGACY) += public_key.o
#
# RSA public key parser
#
-obj-$(CONFIG_$(XPL_)RSA_PUBLIC_KEY_PARSER_LEGACY) += rsa_public_key.o
+obj-$(CONFIG_$(PHASE_)RSA_PUBLIC_KEY_PARSER_LEGACY) += rsa_public_key.o
rsa_public_key-y := \
rsapubkey.asn1.o \
rsa_helper.o
@@ -31,9 +31,9 @@
#
# X.509 Certificate handling
#
-obj-$(CONFIG_$(XPL_)X509_CERTIFICATE_PARSER) += x509_key_parser.o
+obj-$(CONFIG_$(PHASE_)X509_CERTIFICATE_PARSER) += x509_key_parser.o
x509_key_parser-y := x509_helper.o
-x509_key_parser-$(CONFIG_$(XPL_)X509_CERTIFICATE_PARSER_LEGACY) += \
+x509_key_parser-$(CONFIG_$(PHASE_)X509_CERTIFICATE_PARSER_LEGACY) += \
x509.asn1.o \
x509_akid.asn1.o \
x509_cert_parser.o \
@@ -49,21 +49,21 @@
#
# PKCS#7 message handling
#
-obj-$(CONFIG_$(XPL_)PKCS7_MESSAGE_PARSER) += pkcs7_message.o
+obj-$(CONFIG_$(PHASE_)PKCS7_MESSAGE_PARSER) += pkcs7_message.o
pkcs7_message-y := pkcs7_helper.o
-pkcs7_message-$(CONFIG_$(SPL_)PKCS7_MESSAGE_PARSER_LEGACY) += \
+pkcs7_message-$(CONFIG_$(PHASE_)PKCS7_MESSAGE_PARSER_LEGACY) += \
pkcs7.asn1.o \
pkcs7_parser.o
$(obj)/pkcs7_parser.o: $(obj)/pkcs7.asn1.h
$(obj)/pkcs7.asn1.o: $(obj)/pkcs7.asn1.c $(obj)/pkcs7.asn1.h
-obj-$(CONFIG_$(XPL_)PKCS7_VERIFY) += pkcs7_verify.o
+obj-$(CONFIG_$(PHASE_)PKCS7_VERIFY) += pkcs7_verify.o
#
# Signed PE binary-wrapped key handling
#
-obj-$(CONFIG_$(XPL_)MSCODE_PARSER_LEGACY) += mscode.o
+obj-$(CONFIG_$(PHASE_)MSCODE_PARSER_LEGACY) += mscode.o
mscode-y := \
mscode_parser.o \
diff --git a/lib/ecdsa/Makefile b/lib/ecdsa/Makefile
index 32b6183..9db9f7b 100644
--- a/lib/ecdsa/Makefile
+++ b/lib/ecdsa/Makefile
@@ -1 +1 @@
-obj-$(CONFIG_$(XPL_)ECDSA_VERIFY) += ecdsa-verify.o
+obj-$(CONFIG_$(PHASE_)ECDSA_VERIFY) += ecdsa-verify.o
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 6130af1..7f02a83 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -305,7 +305,6 @@
depends on EFI_CAPSULE_FIRMWARE_MANAGEMENT
select UPDATE_FIT
select DFU
- select SET_DFU_ALT_INFO
select EFI_CAPSULE_FIRMWARE
help
Select this option if you want to enable firmware management protocol
@@ -317,7 +316,6 @@
depends on SANDBOX || (!SANDBOX && !EFI_CAPSULE_FIRMWARE_FIT)
select DFU_WRITE_ALT
select DFU
- select SET_DFU_ALT_INFO
select EFI_CAPSULE_FIRMWARE
help
Select this option if you want to enable firmware management protocol
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index 2a0b417..cf050e5 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -29,6 +29,7 @@
obj-y += efi_helper.o
obj-$(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) += efi_capsule.o
obj-$(CONFIG_EFI_CAPSULE_FIRMWARE) += efi_firmware.o
+obj-$(CONFIG_EFI_CAPSULE_AUTHENTICATE) += efi_capsule_key.o
obj-y += efi_console.o
obj-y += efi_device_path.o
obj-$(CONFIG_EFI_DEVICE_PATH_TO_TEXT) += efi_device_path_to_text.o
@@ -36,7 +37,7 @@
obj-y += efi_dt_fixup.o
obj-y += efi_fdt.o
obj-y += efi_file.o
-obj-$(CONFIG_EFI_LOADER_HII) += efi_hii.o
+obj-$(CONFIG_EFI_LOADER_HII) += efi_hii.o efi_hii_config.o
obj-y += efi_image_loader.o
obj-y += efi_load_options.o
obj-y += efi_memory.o
@@ -73,6 +74,23 @@
EFI_VAR_SEED_FILE := $(subst $\",,$(CONFIG_EFI_VAR_SEED_FILE))
$(obj)/efi_var_seed.o: $(srctree)/$(EFI_VAR_SEED_FILE)
+ifeq ($(CONFIG_EFI_CAPSULE_AUTHENTICATE),y)
+capsule_crt_path=($(subst $(quote),,$(CONFIG_EFI_CAPSULE_CRT_FILE)))
+capsule_crt_full=$(srctree)/$(subst $(quote),,$(CONFIG_EFI_CAPSULE_CRT_FILE))
+quiet_cmd_capsule_esl_gen = CAPSULE_ESL_GEN $@
+cmd_capsule_esl_gen = cert-to-efi-sig-list $(capsule_crt_full) $@
+$(objtree)/capsule_esl_file: FORCE
+ @if [ ! -e "$(capsule_crt_full)" ]; then \
+ echo "ERROR: path $(capsule_crt_full) is invalid." >&2; \
+ echo "EFI CONFIG_EFI_CAPSULE_CRT_FILE must be specified when CONFIG_EFI_CAPSULE_AUTHENTICATE is enabled." >&2; \
+ exit 1; \
+ fi
+ $(call cmd,capsule_esl_gen)
+
+$(obj)/efi_capsule.o: $(objtree)/capsule_esl_file FORCE
+asflags-y += -DCAPSULE_ESL_PATH=\"$(objtree)/capsule_esl_file\"
+endif
+
# Set the C flags to add and remove for each app
$(foreach f,$(apps-y),\
$(eval CFLAGS_$(f).o := $(CFLAGS_EFI) -Os -ffreestanding)\
diff --git a/lib/efi_loader/capsule_esl.dtsi.in b/lib/efi_loader/capsule_esl.dtsi.in
deleted file mode 100644
index bc7db83..0000000
--- a/lib/efi_loader/capsule_esl.dtsi.in
+++ /dev/null
@@ -1,11 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Devicetree file with the public key EFI Signature List(ESL)
- * node. This file is used to generate the dtsi file to be
- * included into the DTB.
- */
-/ {
- signature {
- capsule-key = /incbin/("ESL_BIN_FILE");
- };
-};
diff --git a/lib/efi_loader/efi_acpi.c b/lib/efi_loader/efi_acpi.c
index 4422b31..046986a 100644
--- a/lib/efi_loader/efi_acpi.c
+++ b/lib/efi_loader/efi_acpi.c
@@ -7,6 +7,7 @@
#define LOG_CATEGORY LOGC_EFI
+#include <bloblist.h>
#include <efi_loader.h>
#include <log.h>
#include <mapmem.h>
@@ -34,25 +35,38 @@
* add_u_boot_and_runtime(). At some point that function could create a
* more detailed map.
*/
- if (IS_ENABLED(CONFIG_BLOBLIST_TABLES))
- return EFI_SUCCESS;
+ if (IS_ENABLED(CONFIG_BLOBLIST_TABLES)) {
+ int size;
+ void *tab = bloblist_get_blob(BLOBLISTT_ACPI_TABLES, &size);
- /* Mark space used for tables */
- start = ALIGN_DOWN(gd->arch.table_start, EFI_PAGE_MASK);
- end = ALIGN(gd->arch.table_end, EFI_PAGE_MASK);
- ret = efi_add_memory_map(start, end - start, EFI_ACPI_RECLAIM_MEMORY);
- if (ret != EFI_SUCCESS)
- return ret;
- if (gd->arch.table_start_high) {
- start = ALIGN_DOWN(gd->arch.table_start_high, EFI_PAGE_MASK);
- end = ALIGN(gd->arch.table_end_high, EFI_PAGE_MASK);
+ if (!tab)
+ return EFI_NOT_FOUND;
+ addr = map_to_sysmem(tab);
+
+ ret = efi_add_memory_map(addr, size,
+ EFI_ACPI_RECLAIM_MEMORY);
+ if (ret != EFI_SUCCESS)
+ return ret;
+ } else {
+ /* Mark space used for tables */
+ start = ALIGN_DOWN(gd->arch.table_start, EFI_PAGE_MASK);
+ end = ALIGN(gd->arch.table_end, EFI_PAGE_MASK);
ret = efi_add_memory_map(start, end - start,
EFI_ACPI_RECLAIM_MEMORY);
if (ret != EFI_SUCCESS)
return ret;
- }
+ if (gd->arch.table_start_high) {
+ start = ALIGN_DOWN(gd->arch.table_start_high,
+ EFI_PAGE_MASK);
+ end = ALIGN(gd->arch.table_end_high, EFI_PAGE_MASK);
+ ret = efi_add_memory_map(start, end - start,
+ EFI_ACPI_RECLAIM_MEMORY);
+ if (ret != EFI_SUCCESS)
+ return ret;
+ }
- addr = gd_acpi_start();
+ addr = gd_acpi_start();
+ }
log_debug("EFI using ACPI tables at %lx\n", addr);
/* And expose them to our EFI payload */
diff --git a/lib/efi_loader/efi_bootbin.c b/lib/efi_loader/efi_bootbin.c
index deafb2c..94ba7c5 100644
--- a/lib/efi_loader/efi_bootbin.c
+++ b/lib/efi_loader/efi_bootbin.c
@@ -204,6 +204,8 @@
* @image: memory address of the UEFI image
* @size: size of the UEFI image
* @fdt: device-tree
+ * @initrd: initrd
+ * @initrd_sz: initrd size
* @dp_dev: EFI device-path
* @dp_img: EFI image-path
*
@@ -213,6 +215,7 @@
* Return: status code
*/
static efi_status_t efi_binary_run_dp(void *image, size_t size, void *fdt,
+ void *initrd, size_t initrd_sz,
struct efi_device_path *dp_dev,
struct efi_device_path *dp_img)
{
@@ -230,6 +233,10 @@
if (ret != EFI_SUCCESS)
return ret;
+ ret = efi_install_initrd(initrd, initrd_sz);
+ if (ret != EFI_SUCCESS)
+ return ret;
+
return efi_run_image(image, size, dp_dev, dp_img);
}
@@ -239,13 +246,15 @@
* @image: memory address of the UEFI image
* @size: size of the UEFI image
* @fdt: device-tree
+ * @initrd: initrd
+ * @initrd_sz: initrd size
*
* Execute an EFI binary image loaded at @image.
* @size may be zero if the binary is loaded with U-Boot load command.
*
* Return: status code
*/
-efi_status_t efi_binary_run(void *image, size_t size, void *fdt)
+efi_status_t efi_binary_run(void *image, size_t size, void *fdt, void *initrd, size_t initrd_sz)
{
efi_handle_t mem_handle = NULL;
struct efi_device_path *file_path = NULL;
@@ -269,11 +278,14 @@
file_path, NULL);
if (ret != EFI_SUCCESS)
goto out;
+
+ bootefi_device_path = file_path;
+ bootefi_image_path = NULL;
} else {
log_debug("Loaded from disk\n");
}
- ret = efi_binary_run_dp(image, size, fdt, bootefi_device_path,
+ ret = efi_binary_run_dp(image, size, fdt, initrd, initrd_sz, bootefi_device_path,
bootefi_image_path);
out:
if (mem_handle) {
@@ -355,7 +367,7 @@
log_debug("Booting with external fdt\n");
fdt = map_sysmem(bflow->fdt_addr, 0);
}
- ret = efi_binary_run_dp(bflow->buf, bflow->size, fdt, device, image);
+ ret = efi_binary_run_dp(bflow->buf, bflow->size, fdt, NULL, 0, device, image);
return ret;
}
diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
index f9534ef..c0df5cb 100644
--- a/lib/efi_loader/efi_bootmgr.c
+++ b/lib/efi_loader/efi_bootmgr.c
@@ -685,12 +685,12 @@
/* try to register load file2 for initrd's */
if (IS_ENABLED(CONFIG_EFI_LOAD_FILE2_INITRD)) {
- ret = efi_initrd_register();
+ ret = efi_initrd_register(NULL);
if (ret != EFI_SUCCESS)
goto error;
}
- log_info("Booting: %ls\n", lo.label);
+ log_info("Booting: Label: %ls Device path: %pD\n", lo.label, lo.file_path);
/* Ignore the optional data in auto-generated boot options */
if (size >= sizeof(efi_guid_t) &&
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index f220daa..dbebb37 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -3195,7 +3195,7 @@
struct efi_loaded_image_obj *image_obj =
(struct efi_loaded_image_obj *)image_handle;
efi_status_t ret;
- void *info;
+ struct efi_loaded_image *info;
efi_handle_t parent_image = current_image;
efi_status_t exit_status;
jmp_buf exit_jmp;
@@ -3213,7 +3213,7 @@
return EFI_EXIT(EFI_SECURITY_VIOLATION);
ret = EFI_CALL(efi_open_protocol(image_handle, &efi_guid_loaded_image,
- &info, NULL, NULL,
+ (void **)&info, NULL, NULL,
EFI_OPEN_PROTOCOL_GET_PROTOCOL));
if (ret != EFI_SUCCESS)
return EFI_EXIT(EFI_INVALID_PARAMETER);
@@ -3266,7 +3266,8 @@
current_image = image_handle;
image_obj->header.type = EFI_OBJECT_TYPE_STARTED_IMAGE;
- EFI_PRINT("Jumping into 0x%p\n", image_obj->entry);
+ EFI_PRINT("Starting image loaded at 0x%p, entry point 0x%p\n",
+ info->image_base, image_obj->entry);
ret = EFI_CALL(image_obj->entry(image_handle, &systab));
/*
diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index f8a4a7c..1aa52ac 100644
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -22,6 +22,7 @@
#include <asm/global_data.h>
#include <u-boot/uuid.h>
+#include <asm/sections.h>
#include <crypto/pkcs7.h>
#include <crypto/pkcs7_parser.h>
#include <linux/err.h>
@@ -284,33 +285,12 @@
}
#if defined(CONFIG_EFI_CAPSULE_AUTHENTICATE)
-int efi_get_public_key_data(void **pkey, efi_uintn_t *pkey_len)
+static int efi_get_public_key_data(const void **pkey, efi_uintn_t *pkey_len)
{
- const void *fdt_blob = gd->fdt_blob;
- const void *blob;
- const char *cnode_name = "capsule-key";
- const char *snode_name = "signature";
- int sig_node;
- int len;
+ const void *blob = __efi_capsule_sig_begin;
+ const int len = __efi_capsule_sig_end - __efi_capsule_sig_begin;
- sig_node = fdt_subnode_offset(fdt_blob, 0, snode_name);
- if (sig_node < 0) {
- log_err("Unable to get signature node offset\n");
-
- return -FDT_ERR_NOTFOUND;
- }
-
- blob = fdt_getprop(fdt_blob, sig_node, cnode_name, &len);
-
- if (!blob || len < 0) {
- log_err("Unable to get capsule-key value\n");
- *pkey = NULL;
- *pkey_len = 0;
-
- return -FDT_ERR_NOTFOUND;
- }
-
- *pkey = (void *)blob;
+ *pkey = blob;
*pkey_len = len;
return 0;
@@ -321,7 +301,8 @@
{
u8 *buf;
int ret;
- void *fdt_pkey, *pkey;
+ void *pkey;
+ const void *stored_pkey;
efi_uintn_t pkey_len;
uint64_t monotonic_count;
struct efi_signature_store *truststore;
@@ -373,7 +354,7 @@
goto out;
}
- ret = efi_get_public_key_data(&fdt_pkey, &pkey_len);
+ ret = efi_get_public_key_data(&stored_pkey, &pkey_len);
if (ret < 0)
goto out;
@@ -381,7 +362,7 @@
if (!pkey)
goto out;
- memcpy(pkey, fdt_pkey, pkey_len);
+ memcpy(pkey, stored_pkey, pkey_len);
truststore = efi_build_signature_store(pkey, pkey_len);
if (!truststore)
goto out;
diff --git a/lib/efi_loader/efi_capsule_key.S b/lib/efi_loader/efi_capsule_key.S
new file mode 100644
index 0000000..80cefbe
--- /dev/null
+++ b/lib/efi_loader/efi_capsule_key.S
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * .esl cert for capsule authentication
+ *
+ * Copyright (c) 2021, Ilias Apalodimas <ilias.apalodimas@linaro.org>
+ */
+
+#include <config.h>
+
+.section .rodata.capsule_key.init,"a"
+.balign 16
+.global __efi_capsule_sig_begin
+__efi_capsule_sig_begin:
+.incbin CAPSULE_ESL_PATH
+__efi_capsule_sig_end:
+.global __efi_capsule_sig_end
+.balign 16
diff --git a/lib/efi_loader/efi_dt_fixup.c b/lib/efi_loader/efi_dt_fixup.c
index 26928cf..544e1aa 100644
--- a/lib/efi_loader/efi_dt_fixup.c
+++ b/lib/efi_loader/efi_dt_fixup.c
@@ -168,7 +168,7 @@
/* Check size */
required_size = fdt_off_dt_strings(dtb) +
fdt_size_dt_strings(dtb) +
- 0x3000;
+ CONFIG_SYS_FDT_PAD;
total_size = fdt_totalsize(dtb);
if (required_size < total_size)
required_size = total_size;
diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c
index 5a754c9..d44dc09 100644
--- a/lib/efi_loader/efi_firmware.c
+++ b/lib/efi_loader/efi_firmware.c
@@ -56,11 +56,6 @@
u32 last_attempt_status; /* not used */
};
-__weak void set_dfu_alt_info(char *interface, char *devstr)
-{
- env_set("dfu_alt_info", update_info.dfu_string);
-}
-
/**
* efi_firmware_get_image_type_id - get image_type_id
* @image_index: image index
@@ -649,8 +644,10 @@
efi_status_t (*progress)(efi_uintn_t completion),
u16 **abort_reason)
{
+ int ret;
efi_status_t status;
struct fmp_state state = { 0 };
+ char *orig_dfu_env;
EFI_ENTRY("%p %d %p %zu %p %p %p\n", this, image_index, image,
image_size, vendor_code, progress, abort_reason);
@@ -663,7 +660,28 @@
if (status != EFI_SUCCESS)
return EFI_EXIT(status);
+ orig_dfu_env = env_get("dfu_alt_info");
+ if (orig_dfu_env) {
+ orig_dfu_env = strdup(orig_dfu_env);
+ if (!orig_dfu_env) {
+ log_err("strdup() failed!\n");
+ return EFI_EXIT(EFI_OUT_OF_RESOURCES);
+ }
+ }
+ if (env_set("dfu_alt_info", update_info.dfu_string)) {
+ log_err("Unable to set env variable \"dfu_alt_info\"!\n");
+ free(orig_dfu_env);
+ return EFI_EXIT(EFI_DEVICE_ERROR);
+ }
+
+ ret = fit_update(image);
+
- if (fit_update(image))
+ if (env_set("dfu_alt_info", orig_dfu_env))
+ log_warning("Unable to restore env variable \"dfu_alt_info\". Further DFU operations may fail!\n");
+
+ free(orig_dfu_env);
+
+ if (ret)
return EFI_EXIT(EFI_DEVICE_ERROR);
efi_firmware_set_fmp_state_var(&state, image_index);
@@ -717,6 +735,7 @@
u8 dfu_alt_num;
efi_status_t status;
struct fmp_state state = { 0 };
+ char *orig_dfu_env;
EFI_ENTRY("%p %d %p %zu %p %p %p\n", this, image_index, image,
image_size, vendor_code, progress, abort_reason);
@@ -746,9 +765,30 @@
return EFI_EXIT(EFI_DEVICE_ERROR);
}
}
+
+ orig_dfu_env = env_get("dfu_alt_info");
+ if (orig_dfu_env) {
+ orig_dfu_env = strdup(orig_dfu_env);
+ if (!orig_dfu_env) {
+ log_err("strdup() failed!\n");
+ return EFI_EXIT(EFI_OUT_OF_RESOURCES);
+ }
+ }
+ if (env_set("dfu_alt_info", update_info.dfu_string)) {
+ log_err("Unable to set env variable \"dfu_alt_info\"!\n");
+ free(orig_dfu_env);
+ return EFI_EXIT(EFI_DEVICE_ERROR);
+ }
+
+ ret = dfu_write_by_alt(dfu_alt_num, (void *)image, image_size,
+ NULL, NULL);
+
+ if (env_set("dfu_alt_info", orig_dfu_env))
+ log_warning("Unable to restore env variable \"dfu_alt_info\". Further DFU operations may fail!\n");
+
+ free(orig_dfu_env);
- if (dfu_write_by_alt(dfu_alt_num, (void *)image, image_size,
- NULL, NULL))
+ if (ret)
return EFI_EXIT(EFI_DEVICE_ERROR);
efi_firmware_set_fmp_state_var(&state, image_index);
diff --git a/lib/efi_loader/efi_gop.c b/lib/efi_loader/efi_gop.c
index 4593975..3abb47d 100644
--- a/lib/efi_loader/efi_gop.c
+++ b/lib/efi_loader/efi_gop.c
@@ -26,6 +26,7 @@
* @ops: graphical output protocol interface
* @info: graphical output mode information
* @mode: graphical output mode
+ * @vdev: backing video device
* @bpix: bits per pixel
* @fb: frame buffer
*/
@@ -34,6 +35,7 @@
struct efi_gop ops;
struct efi_gop_mode_info info;
struct efi_gop_mode mode;
+ struct udevice *vdev;
/* Fields we only have access to during init */
u32 bpix;
void *fb;
@@ -122,6 +124,7 @@
u32 *fb32 = gopobj->fb;
u16 *fb16 = gopobj->fb;
struct efi_gop_pixel *buffer = __builtin_assume_aligned(bufferp, 4);
+ bool blt_to_video = (operation != EFI_BLT_VIDEO_TO_BLT_BUFFER);
if (delta) {
/* Check for 4 byte alignment */
@@ -245,6 +248,9 @@
dlineoff += dwidth;
}
+ if (blt_to_video)
+ video_damage(gopobj->vdev, dx, dy, width, height);
+
return EFI_SUCCESS;
}
@@ -551,6 +557,7 @@
gopobj->info.pixels_per_scanline = col;
gopobj->bpix = bpix;
gopobj->fb = map_sysmem(fb_base, fb_size);
+ gopobj->vdev = vdev;
return EFI_SUCCESS;
}
diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c
index 8c32059..19fb5d0 100644
--- a/lib/efi_loader/efi_helper.c
+++ b/lib/efi_loader/efi_helper.c
@@ -485,7 +485,7 @@
* needs to be expanded later.
*/
fdt = *fdtp;
- fdt_pages = efi_size_in_pages(fdt_totalsize(fdt) + 0x3000);
+ fdt_pages = efi_size_in_pages(fdt_totalsize(fdt) + CONFIG_SYS_FDT_PAD);
fdt_size = fdt_pages << EFI_PAGE_SHIFT;
ret = efi_allocate_pages(EFI_ALLOCATE_ANY_PAGES,
@@ -623,6 +623,35 @@
}
/**
+ * efi_install_initrd() - install initrd
+ *
+ * Install the initrd located at @initrd using the EFI_LOAD_FILE2
+ * protocol.
+ *
+ * @initrd: address of initrd or NULL if none is provided
+ * @initrd_sz: size of initrd
+ * Return: status code
+ */
+efi_status_t efi_install_initrd(void *initrd, size_t initd_sz)
+{
+ efi_status_t ret;
+ struct efi_device_path *dp_initrd;
+
+ if (!initrd)
+ return EFI_SUCCESS;
+
+ dp_initrd = efi_dp_from_mem(EFI_LOADER_DATA, (uintptr_t)initrd, initd_sz);
+ if (!dp_initrd)
+ return EFI_OUT_OF_RESOURCES;
+
+ ret = efi_initrd_register(dp_initrd);
+ if (ret != EFI_SUCCESS)
+ efi_free_pool(dp_initrd);
+
+ return ret;
+}
+
+/**
* do_bootefi_exec() - execute EFI binary
*
* The image indicated by @handle is started. When it returns the allocated
diff --git a/lib/efi_loader/efi_hii.c b/lib/efi_loader/efi_hii.c
index 4423597..330d7c5 100644
--- a/lib/efi_loader/efi_hii.c
+++ b/lib/efi_loader/efi_hii.c
@@ -343,6 +343,9 @@
struct efi_hii_packagelist *hii;
hii = malloc(sizeof(*hii));
+ if (!hii)
+ return NULL;
+
list_add_tail(&hii->link, &efi_package_lists);
hii->max_string_id = 0;
INIT_LIST_HEAD(&hii->string_tables);
diff --git a/lib/efi_loader/efi_hii_config.c b/lib/efi_loader/efi_hii_config.c
index 37d8c66..521481a 100644
--- a/lib/efi_loader/efi_hii_config.c
+++ b/lib/efi_loader/efi_hii_config.c
@@ -4,10 +4,6 @@
*
* Copyright (c) 2017 Leif Lindholm
* Copyright (c) 2018 AKASHI Takahiro, Linaro Limited
- *
- * As this is still a non-working stub and the protocol is neither required
- * by the EFI shell nor by the UEFI SCT this module has been removed from
- * the Makefile.
*/
#define LOG_CATEGORY LOGC_EFI
diff --git a/lib/efi_loader/efi_load_initrd.c b/lib/efi_loader/efi_load_initrd.c
index fb8cc7b..b5d5894 100644
--- a/lib/efi_loader/efi_load_initrd.c
+++ b/lib/efi_loader/efi_load_initrd.c
@@ -42,6 +42,7 @@
};
static efi_handle_t efi_initrd_handle;
+static struct efi_device_path *efi_initrd_dp;
/**
* get_initrd_fp() - Get initrd device path from a FilePathList device path
@@ -73,6 +74,41 @@
}
/**
+ * efi_initrd_from_mem() - load initial RAM disk from memory
+ *
+ * This function copies the initrd from the memory mapped device
+ * path pointed to by efi_initrd_dp
+ *
+ * @buffer_size: size of allocated buffer
+ * @buffer: buffer to load the file
+ *
+ * Return: status code
+ */
+static efi_status_t efi_initrd_from_mem(efi_uintn_t *buffer_size, void *buffer)
+{
+ efi_status_t ret = EFI_NOT_FOUND;
+ efi_uintn_t bs;
+ struct efi_device_path_memory *mdp;
+
+ mdp = (struct efi_device_path_memory *)efi_initrd_dp;
+ if (!mdp)
+ return ret;
+
+ bs = mdp->end_address - mdp->start_address;
+
+ if (!buffer || *buffer_size < bs) {
+ ret = EFI_BUFFER_TOO_SMALL;
+ *buffer_size = bs;
+ } else {
+ memcpy(buffer, (void *)(uintptr_t)mdp->start_address, bs);
+ *buffer_size = bs;
+ ret = EFI_SUCCESS;
+ }
+
+ return ret;
+}
+
+/**
* efi_load_file2_initrd() - load initial RAM disk
*
* This function implements the LoadFile service of the EFI_LOAD_FILE2_PROTOCOL
@@ -118,6 +154,9 @@
goto out;
}
+ if (efi_initrd_dp)
+ return EFI_EXIT(efi_initrd_from_mem(buffer_size, buffer));
+
ret = get_initrd_fp(&initrd_fp);
if (ret != EFI_SUCCESS)
goto out;
@@ -209,6 +248,9 @@
NULL);
efi_initrd_handle = NULL;
+ efi_free_pool(efi_initrd_dp);
+ efi_initrd_dp = NULL;
+
return ret;
}
@@ -234,24 +276,31 @@
* This function creates a new handle and installs a Linux specific vendor
* device path and an EFI_LOAD_FILE2_PROTOCOL. Linux uses the device path
* to identify the handle and then calls the LoadFile service of the
- * EFI_LOAD_FILE2_PROTOCOL to read the initial RAM disk.
+ * EFI_LOAD_FILE2_PROTOCOL to read the initial RAM disk. If dp_initrd is
+ * not provided, the initrd will be taken from the BootCurrent variable
+ *
+ * @dp_initrd: optional device path containing an initrd
*
* Return: status code
*/
-efi_status_t efi_initrd_register(void)
+efi_status_t efi_initrd_register(struct efi_device_path *dp_initrd)
{
efi_status_t ret;
struct efi_event *event;
- /*
- * Allow the user to continue if Boot#### file path is not set for
- * an initrd
- */
- ret = check_initrd();
- if (ret == EFI_INVALID_PARAMETER)
- return EFI_SUCCESS;
- if (ret != EFI_SUCCESS)
- return ret;
+ if (dp_initrd) {
+ efi_initrd_dp = dp_initrd;
+ } else {
+ /*
+ * Allow the user to continue if Boot#### file path is not set for
+ * an initrd
+ */
+ ret = check_initrd();
+ if (ret == EFI_INVALID_PARAMETER)
+ return EFI_SUCCESS;
+ if (ret != EFI_SUCCESS)
+ return ret;
+ }
ret = efi_install_multiple_protocol_interfaces(&efi_initrd_handle,
/* initramfs */
diff --git a/lib/efi_loader/efi_root_node.c b/lib/efi_loader/efi_root_node.c
index 74225ed..e5246f6 100644
--- a/lib/efi_loader/efi_root_node.c
+++ b/lib/efi_loader/efi_root_node.c
@@ -80,6 +80,9 @@
/* HII database protocol */
&efi_guid_hii_database_protocol,
&efi_hii_database,
+ /* EFI HII Configuration Routing Protocol */
+ &efi_guid_hii_config_routing_protocol,
+ &efi_hii_config_routing,
#endif
NULL);
efi_root->type = EFI_OBJECT_TYPE_U_BOOT_FIRMWARE;
diff --git a/lib/efi_selftest/Makefile b/lib/efi_selftest/Makefile
index 17fbfad..d78bf7d 100644
--- a/lib/efi_selftest/Makefile
+++ b/lib/efi_selftest/Makefile
@@ -51,6 +51,7 @@
efi_selftest_watchdog.o
obj-$(CONFIG_EFI_ECPT) += efi_selftest_ecpt.o
+obj-$(CONFIG_ARM64) += efi_selftest_el.o
obj-$(CONFIG_NETDEVICES) += efi_selftest_snp.o
obj-$(CONFIG_EFI_HTTP_PROTOCOL) += efi_selftest_http.o
obj-$(CONFIG_EFI_HTTP_PROTOCOL) += efi_selftest_ipconfig.o
diff --git a/lib/efi_selftest/efi_selftest_el.c b/lib/efi_selftest/efi_selftest_el.c
new file mode 100644
index 0000000..f9941ca
--- /dev/null
+++ b/lib/efi_selftest/efi_selftest_el.c
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Check current exception level on ARMv8.
+ */
+#include <efi_loader.h>
+#include <efi_selftest.h>
+
+/**
+ * current_exception_level()
+ *
+ * Return: current exception level, 0 - 3
+ */
+static unsigned int current_exception_level(void)
+{
+ unsigned long el;
+
+ asm volatile (
+ "MRS %0, CurrentEL"
+ : "=r" (el) : : );
+
+ return (el >> 2) & 0x3;
+}
+
+/**
+ * execute() - execute test
+ *
+ * Check that the exception level is not EL3.
+ */
+static int execute(void)
+{
+ unsigned int el = current_exception_level();
+
+ efi_st_printf("Exception level EL%u\n", el);
+ if (el != 1 && el != 2) {
+ efi_st_error("EL1 or EL2 expected");
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(el) = {
+ .name = "exception level",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .execute = execute,
+};
diff --git a/lib/efi_selftest/efi_selftest_hii.c b/lib/efi_selftest/efi_selftest_hii.c
index c363df4..228dc29 100644
--- a/lib/efi_selftest/efi_selftest_hii.c
+++ b/lib/efi_selftest/efi_selftest_hii.c
@@ -609,14 +609,12 @@
result = EFI_ST_SUCCESS;
out:
- if (handle) {
- ret = hii_database_protocol->remove_package_list(
- hii_database_protocol, handle);
- if (ret != EFI_SUCCESS) {
- efi_st_error("remove_package_list returned %u\n",
- (unsigned int)ret);
- return EFI_ST_FAILURE;
- }
+ ret = hii_database_protocol->remove_package_list(
+ hii_database_protocol, handle);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("remove_package_list returned %u\n",
+ (unsigned int)ret);
+ return EFI_ST_FAILURE;
}
return result;
@@ -711,14 +709,12 @@
result = EFI_ST_SUCCESS;
out:
- if (handle) {
- ret = hii_database_protocol->remove_package_list(
- hii_database_protocol, handle);
- if (ret != EFI_SUCCESS) {
- efi_st_error("remove_package_list returned %u\n",
- (unsigned int)ret);
- return EFI_ST_FAILURE;
- }
+ ret = hii_database_protocol->remove_package_list(
+ hii_database_protocol, handle);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("remove_package_list returned %u\n",
+ (unsigned int)ret);
+ return EFI_ST_FAILURE;
}
return result;
@@ -792,14 +788,12 @@
result = EFI_ST_SUCCESS;
out:
- if (handle) {
- ret = hii_database_protocol->remove_package_list(
- hii_database_protocol, handle);
- if (ret != EFI_SUCCESS) {
- efi_st_error("remove_package_list returned %u\n",
- (unsigned int)ret);
- return EFI_ST_FAILURE;
- }
+ ret = hii_database_protocol->remove_package_list(
+ hii_database_protocol, handle);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("remove_package_list returned %u\n",
+ (unsigned int)ret);
+ return EFI_ST_FAILURE;
}
return result;
@@ -851,14 +845,12 @@
result = EFI_ST_SUCCESS;
out:
- if (handle) {
- ret = hii_database_protocol->remove_package_list(
- hii_database_protocol, handle);
- if (ret != EFI_SUCCESS) {
- efi_st_error("remove_package_list returned %u\n",
- (unsigned int)ret);
- return EFI_ST_FAILURE;
- }
+ ret = hii_database_protocol->remove_package_list(
+ hii_database_protocol, handle);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("remove_package_list returned %u\n",
+ (unsigned int)ret);
+ return EFI_ST_FAILURE;
}
return result;
@@ -918,14 +910,12 @@
result = EFI_ST_SUCCESS;
out:
- if (handle) {
- ret = hii_database_protocol->remove_package_list(
- hii_database_protocol, handle);
- if (ret != EFI_SUCCESS) {
- efi_st_error("remove_package_list returned %u\n",
- (unsigned int)ret);
- return EFI_ST_FAILURE;
- }
+ ret = hii_database_protocol->remove_package_list(
+ hii_database_protocol, handle);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("remove_package_list returned %u\n",
+ (unsigned int)ret);
+ return EFI_ST_FAILURE;
}
return result;
@@ -991,14 +981,12 @@
result = EFI_ST_SUCCESS;
out:
- if (handle) {
- ret = hii_database_protocol->remove_package_list(
- hii_database_protocol, handle);
- if (ret != EFI_SUCCESS) {
- efi_st_error("remove_package_list returned %u\n",
- (unsigned int)ret);
- return EFI_ST_FAILURE;
- }
+ ret = hii_database_protocol->remove_package_list(
+ hii_database_protocol, handle);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("remove_package_list returned %u\n",
+ (unsigned int)ret);
+ return EFI_ST_FAILURE;
}
return result;
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index f09c992..c38738b 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1708,7 +1708,7 @@
gd->fdt_src = FDTSRC_BLOBLIST;
log_debug("Devicetree is in bloblist at %p\n",
gd->fdt_blob);
- ret = 0;
+ goto setup_fdt;
} else {
log_debug("No FDT found in bloblist\n");
ret = -ENOENT;
@@ -1752,6 +1752,7 @@
}
}
+setup_fdt:
if (CONFIG_IS_ENABLED(MULTI_DTB_FIT))
setup_multi_dtb_fit();
diff --git a/lib/initcall.c b/lib/initcall.c
deleted file mode 100644
index 2686b9a..0000000
--- a/lib/initcall.c
+++ /dev/null
@@ -1,102 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2013 The Chromium OS Authors.
- */
-
-#include <efi.h>
-#include <initcall.h>
-#include <log.h>
-#include <relocate.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static ulong calc_reloc_ofs(void)
-{
-#ifdef CONFIG_EFI_APP
- return (ulong)image_base;
-#endif
- /*
- * Sandbox is relocated by the OS, so symbols always appear at
- * the relocated address.
- */
- if (IS_ENABLED(CONFIG_SANDBOX) || (gd->flags & GD_FLG_RELOC))
- return gd->reloc_off;
-
- return 0;
-}
-
-/**
- * initcall_is_event() - Get the event number for an initcall
- *
- * func: Function pointer to check
- * Return: Event number, if this is an event, else 0
- */
-static int initcall_is_event(init_fnc_t func)
-{
- ulong val = (ulong)func;
-
- if ((val & INITCALL_IS_EVENT) == INITCALL_IS_EVENT)
- return val & INITCALL_EVENT_TYPE;
-
- return 0;
-}
-
-/*
- * To enable debugging. add #define DEBUG at the top of the including file.
- *
- * To find a symbol, use grep on u-boot.map
- */
-int initcall_run_list(const init_fnc_t init_sequence[])
-{
- ulong reloc_ofs;
- const init_fnc_t *ptr;
- enum event_t type;
- init_fnc_t func;
- int ret = 0;
-
- for (ptr = init_sequence; func = *ptr, func; ptr++) {
- reloc_ofs = calc_reloc_ofs();
- type = initcall_is_event(func);
-
- if (type) {
- if (!CONFIG_IS_ENABLED(EVENT))
- continue;
- debug("initcall: event %d/%s\n", type,
- event_type_name(type));
- } else if (reloc_ofs) {
- debug("initcall: %p (relocated to %p)\n",
- (char *)func - reloc_ofs, (char *)func);
- } else {
- debug("initcall: %p\n", (char *)func - reloc_ofs);
- }
-
- ret = type ? event_notify_null(type) : func();
- if (ret)
- break;
- }
-
- if (ret) {
- if (CONFIG_IS_ENABLED(EVENT)) {
- char buf[60];
-
- /* don't worry about buf size as we are dying here */
- if (type) {
- sprintf(buf, "event %d/%s", type,
- event_type_name(type));
- } else {
- sprintf(buf, "call %p",
- (char *)func - reloc_ofs);
- }
-
- printf("initcall failed at %s (err=%dE)\n", buf, ret);
- } else {
- printf("initcall failed at call %p (err=%d)\n",
- (char *)func - reloc_ofs, ret);
- }
-
- return ret;
- }
-
- return 0;
-}
diff --git a/lib/lwip/Makefile b/lib/lwip/Makefile
index fe2b64c..e9e8cae 100644
--- a/lib/lwip/Makefile
+++ b/lib/lwip/Makefile
@@ -54,5 +54,5 @@
lwip/src/core/udp.o \
lwip/src/netif/ethernet.o
-obj-$(CONFIG_$(XPL_)MBEDTLS_LIB_TLS) += lwip/src/apps/altcp_tls/altcp_tls_mbedtls.o \
+obj-$(CONFIG_$(PHASE_)MBEDTLS_LIB_TLS) += lwip/src/apps/altcp_tls/altcp_tls_mbedtls.o \
lwip/src/apps/altcp_tls/altcp_tls_mbedtls_mem.o
diff --git a/lib/mbedtls/Makefile b/lib/mbedtls/Makefile
index 4bbe7ce..c5b445b 100644
--- a/lib/mbedtls/Makefile
+++ b/lib/mbedtls/Makefile
@@ -6,19 +6,19 @@
MBEDTLS_LIB_DIR = external/mbedtls/library
# shim layer for hash
-obj-$(CONFIG_$(XPL_)MD5_MBEDTLS) += md5.o
-obj-$(CONFIG_$(XPL_)SHA1_MBEDTLS) += sha1.o
-obj-$(CONFIG_$(XPL_)SHA256_MBEDTLS) += sha256.o
-obj-$(CONFIG_$(XPL_)SHA512_MBEDTLS) += sha512.o
+obj-$(CONFIG_$(PHASE_)MD5_MBEDTLS) += md5.o
+obj-$(CONFIG_$(PHASE_)SHA1_MBEDTLS) += sha1.o
+obj-$(CONFIG_$(PHASE_)SHA256_MBEDTLS) += sha256.o
+obj-$(CONFIG_$(PHASE_)SHA512_MBEDTLS) += sha512.o
# x509 libraries
-obj-$(CONFIG_$(XPL_)ASYMMETRIC_PUBLIC_KEY_MBEDTLS) += \
+obj-$(CONFIG_$(PHASE_)ASYMMETRIC_PUBLIC_KEY_MBEDTLS) += \
public_key.o
-obj-$(CONFIG_$(XPL_)X509_CERTIFICATE_PARSER_MBEDTLS) += \
+obj-$(CONFIG_$(PHASE_)X509_CERTIFICATE_PARSER_MBEDTLS) += \
x509_cert_parser.o
-obj-$(CONFIG_$(XPL_)PKCS7_MESSAGE_PARSER_MBEDTLS) += pkcs7_parser.o
-obj-$(CONFIG_$(XPL_)MSCODE_PARSER_MBEDTLS) += mscode_parser.o
-obj-$(CONFIG_$(XPL_)RSA_PUBLIC_KEY_PARSER_MBEDTLS) += rsa_helper.o
+obj-$(CONFIG_$(PHASE_)PKCS7_MESSAGE_PARSER_MBEDTLS) += pkcs7_parser.o
+obj-$(CONFIG_$(PHASE_)MSCODE_PARSER_MBEDTLS) += mscode_parser.o
+obj-$(CONFIG_$(PHASE_)RSA_PUBLIC_KEY_PARSER_MBEDTLS) += rsa_helper.o
# MbedTLS crypto library
obj-$(CONFIG_$(XPL_)MBEDTLS_LIB) += mbedtls_lib_crypto.o
@@ -27,35 +27,35 @@
$(MBEDTLS_LIB_DIR)/constant_time.o \
$(MBEDTLS_LIB_DIR)/md.o
-mbedtls_lib_crypto-$(CONFIG_$(XPL_)MD5_MBEDTLS) += $(MBEDTLS_LIB_DIR)/md5.o
-mbedtls_lib_crypto-$(CONFIG_$(XPL_)SHA1_MBEDTLS) += $(MBEDTLS_LIB_DIR)/sha1.o
-mbedtls_lib_crypto-$(CONFIG_$(XPL_)SHA256_MBEDTLS) += \
+mbedtls_lib_crypto-$(CONFIG_$(PHASE_)MD5_MBEDTLS) += $(MBEDTLS_LIB_DIR)/md5.o
+mbedtls_lib_crypto-$(CONFIG_$(PHASE_)SHA1_MBEDTLS) += $(MBEDTLS_LIB_DIR)/sha1.o
+mbedtls_lib_crypto-$(CONFIG_$(PHASE_)SHA256_MBEDTLS) += \
$(MBEDTLS_LIB_DIR)/sha256.o
-mbedtls_lib_crypto-$(CONFIG_$(XPL_)SHA512_MBEDTLS) += \
+mbedtls_lib_crypto-$(CONFIG_$(PHASE_)SHA512_MBEDTLS) += \
$(MBEDTLS_LIB_DIR)/sha512.o
-mbedtls_lib_crypto-$(CONFIG_$(XPL_)HKDF_MBEDTLS) += \
+mbedtls_lib_crypto-$(CONFIG_$(PHASE_)HKDF_MBEDTLS) += \
$(MBEDTLS_LIB_DIR)/hkdf.o
# MbedTLS X509 library
obj-$(CONFIG_$(XPL_)MBEDTLS_LIB_X509) += mbedtls_lib_x509.o
mbedtls_lib_x509-y := $(MBEDTLS_LIB_DIR)/x509.o
-mbedtls_lib_x509-$(CONFIG_$(XPL_)ASN1_DECODER_MBEDTLS) += \
+mbedtls_lib_x509-$(CONFIG_$(PHASE_)ASN1_DECODER_MBEDTLS) += \
$(MBEDTLS_LIB_DIR)/asn1parse.o \
$(MBEDTLS_LIB_DIR)/asn1write.o \
$(MBEDTLS_LIB_DIR)/oid.o
-mbedtls_lib_x509-$(CONFIG_$(XPL_)RSA_PUBLIC_KEY_PARSER_MBEDTLS) += \
+mbedtls_lib_x509-$(CONFIG_$(PHASE_)RSA_PUBLIC_KEY_PARSER_MBEDTLS) += \
$(MBEDTLS_LIB_DIR)/bignum.o \
$(MBEDTLS_LIB_DIR)/bignum_core.o \
$(MBEDTLS_LIB_DIR)/rsa.o \
$(MBEDTLS_LIB_DIR)/rsa_alt_helpers.o
-mbedtls_lib_x509-$(CONFIG_$(XPL_)ASYMMETRIC_PUBLIC_KEY_MBEDTLS) += \
+mbedtls_lib_x509-$(CONFIG_$(PHASE_)ASYMMETRIC_PUBLIC_KEY_MBEDTLS) += \
$(MBEDTLS_LIB_DIR)/pk.o \
$(MBEDTLS_LIB_DIR)/pk_wrap.o \
$(MBEDTLS_LIB_DIR)/pkparse.o
-mbedtls_lib_x509-$(CONFIG_$(XPL_)X509_CERTIFICATE_PARSER_MBEDTLS) += \
+mbedtls_lib_x509-$(CONFIG_$(PHASE_)X509_CERTIFICATE_PARSER_MBEDTLS) += \
$(MBEDTLS_LIB_DIR)/x509_crl.o \
$(MBEDTLS_LIB_DIR)/x509_crt.o
-mbedtls_lib_x509-$(CONFIG_$(XPL_)PKCS7_MESSAGE_PARSER_MBEDTLS) += \
+mbedtls_lib_x509-$(CONFIG_$(PHASE_)PKCS7_MESSAGE_PARSER_MBEDTLS) += \
$(MBEDTLS_LIB_DIR)/pkcs7.o
#mbedTLS TLS support
diff --git a/lib/smbios.c b/lib/smbios.c
index 7c9701a..b8c2846 100644
--- a/lib/smbios.c
+++ b/lib/smbios.c
@@ -950,7 +950,7 @@
ctx.subnode_name = NULL;
if (method->subnode_name) {
ctx.subnode_name = method->subnode_name;
- if (IS_ENABLED(CONFIG_OF_CONTROL))
+ if (ofnode_valid(parent_node))
ctx.node = ofnode_find_subnode(parent_node,
method->subnode_name);
}
diff --git a/lib/time.c b/lib/time.c
index d88edaf..0e9b079 100644
--- a/lib/time.c
+++ b/lib/time.c
@@ -17,6 +17,7 @@
#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/delay.h>
+#include <uthread.h>
#ifndef CFG_WD_PERIOD
# define CFG_WD_PERIOD (10 * 1000 * 1000) /* 10 seconds default */
@@ -197,7 +198,13 @@
do {
schedule();
kv = usec > CFG_WD_PERIOD ? CFG_WD_PERIOD : usec;
- __udelay(kv);
+ if (CONFIG_IS_ENABLED(UTHREAD)) {
+ ulong t0 = timer_get_us();
+ while (timer_get_us() - t0 < kv)
+ uthread_schedule();
+ } else {
+ __udelay(kv);
+ }
usec -= kv;
} while(usec);
}
diff --git a/lib/uthread.c b/lib/uthread.c
new file mode 100644
index 0000000..062fca7
--- /dev/null
+++ b/lib/uthread.c
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2021 Ahmad Fatoum, Pengutronix
+ * Copyright (C) 2025 Linaro Limited
+ *
+ * An implementation of cooperative multi-tasking inspired from barebox threads
+ * https://github.com/barebox/barebox/blob/master/common/bthread.c
+ */
+
+#include <compiler.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <malloc.h>
+#include <setjmp.h>
+#include <stdint.h>
+#include <uthread.h>
+
+static struct uthread main_thread = {
+ .list = LIST_HEAD_INIT(main_thread.list),
+};
+
+static struct uthread *current = &main_thread;
+
+/**
+ * uthread_trampoline() - Call the current thread's entry point then resume the
+ * main thread.
+ *
+ * This is a helper function which is used as the @func argument to the
+ * initjmp() function, and ultimately invoked via setjmp(). It does not return
+ * but instead longjmp()'s back to the main thread.
+ */
+static void __noreturn uthread_trampoline(void)
+{
+ struct uthread *curr = current;
+
+ curr->fn(curr->arg);
+ curr->done = true;
+ current = &main_thread;
+ longjmp(current->ctx, 1);
+ /* Not reached */
+ while (true)
+ ;
+}
+
+/**
+ * uthread_free() - Free memory used by a uthread object.
+ */
+static void uthread_free(struct uthread *uthread)
+{
+ if (!uthread)
+ return;
+ free(uthread->stack);
+ free(uthread);
+}
+
+int uthread_create(struct uthread *uthr, void (*fn)(void *), void *arg,
+ size_t stack_sz, unsigned int grp_id)
+{
+ bool user_allocated = false;
+
+ if (!stack_sz)
+ stack_sz = CONFIG_UTHREAD_STACK_SIZE;
+
+ if (uthr) {
+ user_allocated = true;
+ } else {
+ uthr = calloc(1, sizeof(*uthr));
+ if (!uthr)
+ return -1;
+ }
+
+ uthr->stack = memalign(16, stack_sz);
+ if (!uthr->stack)
+ goto err;
+
+ uthr->fn = fn;
+ uthr->arg = arg;
+ uthr->grp_id = grp_id;
+
+ list_add_tail(&uthr->list, ¤t->list);
+
+ initjmp(uthr->ctx, uthread_trampoline, uthr->stack, stack_sz);
+
+ return 0;
+err:
+ if (!user_allocated)
+ free(uthr);
+ return -1;
+}
+
+/**
+ * uthread_resume() - switch execution to a given thread
+ *
+ * @uthread: the thread object that should be resumed
+ */
+static void uthread_resume(struct uthread *uthread)
+{
+ if (!setjmp(current->ctx)) {
+ current = uthread;
+ longjmp(uthread->ctx, 1);
+ }
+}
+
+bool uthread_schedule(void)
+{
+ struct uthread *next;
+ struct uthread *tmp;
+
+ list_for_each_entry_safe(next, tmp, ¤t->list, list) {
+ if (!next->done) {
+ uthread_resume(next);
+ return true;
+ }
+ /* Found a 'done' thread, free its resources */
+ list_del(&next->list);
+ uthread_free(next);
+ }
+ return false;
+}
+
+unsigned int uthread_grp_new_id(void)
+{
+ static unsigned int id;
+
+ return ++id;
+}
+
+bool uthread_grp_done(unsigned int grp_id)
+{
+ struct uthread *next;
+
+ list_for_each_entry(next, &main_thread.list, list) {
+ if (next->grp_id == grp_id && !next->done)
+ return false;
+ }
+
+ return true;
+}
+
+int uthread_mutex_lock(struct uthread_mutex *mutex)
+{
+ while (mutex->state == UTHREAD_MUTEX_LOCKED)
+ uthread_schedule();
+
+ mutex->state = UTHREAD_MUTEX_LOCKED;
+ return 0;
+}
+
+int uthread_mutex_trylock(struct uthread_mutex *mutex)
+{
+ if (mutex->state == UTHREAD_MUTEX_UNLOCKED) {
+ mutex->state = UTHREAD_MUTEX_LOCKED;
+ return 0;
+ }
+
+ return -EBUSY;
+}
+
+int uthread_mutex_unlock(struct uthread_mutex *mutex)
+{
+ mutex->state = UTHREAD_MUTEX_UNLOCKED;
+
+ return 0;
+}
diff --git a/lib/uuid.c b/lib/uuid.c
index 7565877..6abbcf2 100644
--- a/lib/uuid.c
+++ b/lib/uuid.c
@@ -67,8 +67,11 @@
efi_guid_t guid;
} list_guid[] = {
#ifndef USE_HOSTCC
+#if defined(CONFIG_PARTITION_TYPE_GUID) || defined(CONFIG_CMD_EFIDEBUG) || \
+ defined(CONFIG_EFI)
+ {"EFI System Partition", PARTITION_SYSTEM_GUID},
+#endif
#ifdef CONFIG_PARTITION_TYPE_GUID
- {"system", PARTITION_SYSTEM_GUID},
{"mbr", LEGACY_MBR_PARTITION_GUID},
{"msft", PARTITION_MSFT_RESERVED_GUID},
{"data", PARTITION_BASIC_DATA_GUID},
@@ -182,10 +185,6 @@
{
"TCG2",
EFI_TCG2_PROTOCOL_GUID,
- },
- {
- "System Partition",
- PARTITION_SYSTEM_GUID
},
{
"Firmware Management",
diff --git a/net/Makefile b/net/Makefile
index 7c917b3..d63f62b 100644
--- a/net/Makefile
+++ b/net/Makefile
@@ -11,10 +11,9 @@
obj-$(CONFIG_CMD_BOOTP) += bootp.o
obj-$(CONFIG_CMD_CDP) += cdp.o
obj-$(CONFIG_CMD_DNS) += dns.o
-obj-$(CONFIG_DM_DSA) += dsa-uclass.o
obj-$(CONFIG_CMD_LINK_LOCAL) += link_local.o
obj-$(CONFIG_IPV6) += ndisc.o
-obj-$(CONFIG_$(XPL_)DM_ETH) += net.o
+obj-$(CONFIG_$(PHASE_)DM_ETH) += net.o
obj-$(CONFIG_IPV6) += net6.o
obj-$(CONFIG_CMD_NFS) += nfs.o
obj-$(CONFIG_CMD_PING) += ping.o
@@ -39,11 +38,12 @@
endif
ifeq ($(filter y,$(CONFIG_NET) $(CONFIG_NET_LWIP)),y)
-obj-$(CONFIG_$(XPL_)DM_ETH) += eth-uclass.o
+obj-$(CONFIG_DM_DSA) += dsa-uclass.o
+obj-$(CONFIG_$(PHASE_)DM_ETH) += eth-uclass.o
obj-$(CONFIG_$(PHASE_)BOOTDEV_ETH) += eth_bootdev.o
obj-$(CONFIG_DM_MDIO) += mdio-uclass.o
obj-$(CONFIG_DM_MDIO_MUX) += mdio-mux-uclass.o
-obj-$(CONFIG_$(XPL_)DM_ETH) += eth_common.o
+obj-$(CONFIG_$(PHASE_)DM_ETH) += eth_common.o
obj-y += net-common.o
endif
diff --git a/net/dhcpv6.c b/net/dhcpv6.c
index 54619ee..0c2de75 100644
--- a/net/dhcpv6.c
+++ b/net/dhcpv6.c
@@ -29,6 +29,10 @@
int updated_sol_max_rt_ms = SOL_MAX_RT_MS;
/* state machine parameters/variables */
struct dhcp6_sm_params sm_params;
+/* DHCPv6 all server IP6 address */
+const struct in6_addr dhcp_mcast_ip6 = DHCP6_MULTICAST_ADDR;
+/* IPv6 multicast ethernet address */
+const u8 net_dhcp6_mcast_ethaddr[6] = IPV6_ALL_NODE_ETH_ADDR(dhcp_mcast_ip6);
static void dhcp6_state_machine(bool timeout, uchar *rx_pkt, unsigned int len);
@@ -171,7 +175,6 @@
*/
static void dhcp6_send_solicit_packet(void)
{
- struct in6_addr dhcp_bcast_ip6;
int len = 0;
uchar *pkt;
uchar *dhcp_pkt_start_ptr;
@@ -200,9 +203,8 @@
len = pkt - dhcp_pkt_start_ptr;
/* send UDP packet to DHCP6 multicast address */
- string_to_ip6(DHCP6_MULTICAST_ADDR, sizeof(DHCP6_MULTICAST_ADDR), &dhcp_bcast_ip6);
net_set_udp_handler(dhcp6_handler);
- net_send_udp_packet6((uchar *)net_bcast_ethaddr, &dhcp_bcast_ip6,
+ net_send_udp_packet6((uchar *)net_dhcp6_mcast_ethaddr, (struct in6_addr *)&dhcp_mcast_ip6,
PORT_DHCP6_S, PORT_DHCP6_C, len);
}
@@ -218,7 +220,6 @@
*/
static void dhcp6_send_request_packet(void)
{
- struct in6_addr dhcp_bcast_ip6;
int len = 0;
uchar *pkt;
uchar *dhcp_pkt_start_ptr;
@@ -252,9 +253,8 @@
len = pkt - dhcp_pkt_start_ptr;
/* send UDP packet to DHCP6 multicast address */
- string_to_ip6(DHCP6_MULTICAST_ADDR, strlen(DHCP6_MULTICAST_ADDR), &dhcp_bcast_ip6);
net_set_udp_handler(dhcp6_handler);
- net_send_udp_packet6((uchar *)net_bcast_ethaddr, &dhcp_bcast_ip6,
+ net_send_udp_packet6((uchar *)net_dhcp6_mcast_ethaddr, (struct in6_addr *)&dhcp_mcast_ip6,
PORT_DHCP6_S, PORT_DHCP6_C, len);
}
@@ -473,8 +473,7 @@
* server UID, save the new server UID and preference
*/
if (!sm_params.server_uid.uid_ptr ||
- (sm_params.server_uid.uid_ptr &&
- sm_params.server_uid.preference < sm_params.rx_status.preference)) {
+ sm_params.server_uid.preference < sm_params.rx_status.preference) {
rx_uid_size = sm_params.rx_status.server_uid_size;
if (sm_params.server_uid.uid_ptr)
free(sm_params.server_uid.uid_ptr);
diff --git a/net/dhcpv6.h b/net/dhcpv6.h
index 65c8e4c..d41a3c3 100644
--- a/net/dhcpv6.h
+++ b/net/dhcpv6.h
@@ -40,7 +40,13 @@
/* vendor-class-data to send in vendor clas option */
#define DHCP6_VCI_STRING "U-Boot"
-#define DHCP6_MULTICAST_ADDR "ff02::1:2" /* DHCP multicast address */
+/*
+ * All-DHCPv6 server multicast address
+ */
+#define DHCP6_MULTICAST_ADDR { { { 0xFF, 0x02, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x01, 0x00, 0x02 } } }
/* DHCP6 States supported */
enum dhcp6_state {
diff --git a/net/lwip/Makefile b/net/lwip/Makefile
index 950c531..5df2225 100644
--- a/net/lwip/Makefile
+++ b/net/lwip/Makefile
@@ -1,6 +1,6 @@
ccflags-y += -I$(srctree)/lib/lwip/lwip/src/include -I$(srctree)/lib/lwip/u-boot
-obj-$(CONFIG_$(SPL_)DM_ETH) += net-lwip.o
+obj-$(CONFIG_$(PHASE_)DM_ETH) += net-lwip.o
obj-$(CONFIG_CMD_DHCP) += dhcp.o
obj-$(CONFIG_CMD_DNS) += dns.o
obj-$(CONFIG_CMD_PING) += ping.o
diff --git a/net/lwip/dhcp.c b/net/lwip/dhcp.c
index 3b7e470..92bd706 100644
--- a/net/lwip/dhcp.c
+++ b/net/lwip/dhcp.c
@@ -115,7 +115,8 @@
int ret;
struct udevice *dev;
- net_lwip_set_current();
+ if (net_lwip_eth_start() < 0)
+ return CMD_RET_FAILURE;
dev = eth_get_dev();
if (!dev) {
diff --git a/net/lwip/dns.c b/net/lwip/dns.c
index 149bdb7..19172ac 100644
--- a/net/lwip/dns.c
+++ b/net/lwip/dns.c
@@ -121,7 +121,8 @@
if (argc == 3)
var = argv[2];
- net_lwip_set_current();
+ if (net_lwip_eth_start() < 0)
+ return CMD_RET_FAILURE;
return dns_loop(eth_get_dev(), name, var);
}
diff --git a/net/lwip/net-lwip.c b/net/lwip/net-lwip.c
index 6b7b696..f05c4cd 100644
--- a/net/lwip/net-lwip.c
+++ b/net/lwip/net-lwip.c
@@ -14,6 +14,7 @@
#include <lwip/init.h>
#include <lwip/prot/etharp.h>
#include <net.h>
+#include <timer.h>
/* xx:xx:xx:xx:xx:xx\0 */
#define MAC_ADDR_STRLEN 18
@@ -21,6 +22,8 @@
#if defined(CONFIG_API) || defined(CONFIG_EFI_LOADER)
void (*push_packet)(void *, int len) = 0;
#endif
+static int net_try_count;
+static int net_restarted;
int net_restart_wrap;
static uchar net_pkt_buf[(PKTBUFSRX) * PKTSIZE_ALIGN + PKTALIGN];
uchar *net_rx_packets[PKTBUFSRX];
@@ -134,18 +137,27 @@
return 0;
}
-/* Initialize the lwIP stack and the ethernet devices and set current device */
-void net_lwip_set_current(void)
+/*
+ * Initialize the network stack if needed and start the current device if valid
+ */
+int net_lwip_eth_start(void)
{
- static bool init_done;
+ int ret;
- if (!init_done) {
- eth_init_rings();
- eth_init();
- lwip_init();
- init_done = true;
+ net_init();
+ if (eth_is_on_demand_init()) {
+ eth_halt();
+ eth_set_current();
+ ret = eth_init();
+ if (ret < 0) {
+ eth_halt();
+ return ret;
+ }
+ } else {
+ eth_init_state_only();
}
- eth_set_current();
+
+ return 0;
}
static struct netif *new_netif(struct udevice *udev, bool with_ip)
@@ -224,11 +236,20 @@
free(netif);
}
+/*
+ * Initialize the network buffers, an ethernet device, and the lwIP stack
+ * (once).
+ */
int net_init(void)
{
- eth_set_current();
+ static bool init_done;
- net_lwip_new_netif(eth_get_dev());
+ if (!init_done) {
+ eth_init_rings();
+ eth_init();
+ lwip_init();
+ init_done = true;
+ }
return 0;
}
@@ -319,5 +340,48 @@
u32_t sys_now(void)
{
+#if CONFIG_IS_ENABLED(SANDBOX_TIMER)
+ return timer_early_get_count();
+#else
return get_timer(0);
+#endif
+}
+
+int net_start_again(void)
+{
+ char *nretry;
+ int retry_forever = 0;
+ unsigned long retrycnt = 0;
+
+ nretry = env_get("netretry");
+ if (nretry) {
+ if (!strcmp(nretry, "yes"))
+ retry_forever = 1;
+ else if (!strcmp(nretry, "no"))
+ retrycnt = 0;
+ else if (!strcmp(nretry, "once"))
+ retrycnt = 1;
+ else
+ retrycnt = simple_strtoul(nretry, NULL, 0);
+ } else {
+ retrycnt = 0;
+ retry_forever = 0;
+ }
+
+ if ((!retry_forever) && (net_try_count > retrycnt)) {
+ eth_halt();
+ /*
+ * We don't provide a way for the protocol to return an error,
+ * but this is almost always the reason.
+ */
+ return -ETIMEDOUT;
+ }
+
+ net_try_count++;
+
+ eth_halt();
+#if !defined(CONFIG_NET_DO_NOT_TRY_ANOTHER)
+ eth_try_another(!net_restarted);
+#endif
+ return eth_init();
}
diff --git a/net/lwip/ping.c b/net/lwip/ping.c
index c586a96..d8042ce 100644
--- a/net/lwip/ping.c
+++ b/net/lwip/ping.c
@@ -168,10 +168,13 @@
if (!ipaddr_aton(argv[1], &addr))
return CMD_RET_USAGE;
- net_lwip_set_current();
-
- if (ping_loop(eth_get_dev(), &addr) < 0)
- return CMD_RET_FAILURE;
+restart:
+ if (net_lwip_eth_start() < 0 || ping_loop(eth_get_dev(), &addr) < 0) {
+ if (net_start_again() == 0)
+ goto restart;
+ else
+ return CMD_RET_FAILURE;
+ }
return CMD_RET_SUCCESS;
}
diff --git a/net/lwip/tftp.c b/net/lwip/tftp.c
index 123d66b..4f9b204 100644
--- a/net/lwip/tftp.c
+++ b/net/lwip/tftp.c
@@ -280,7 +280,10 @@
goto out;
}
- net_lwip_set_current();
+ if (net_lwip_eth_start() < 0) {
+ ret = CMD_RET_FAILURE;
+ goto out;
+ }
if (tftp_loop(eth_get_dev(), laddr, fname, srvip, port) < 0)
ret = CMD_RET_FAILURE;
diff --git a/net/lwip/wget.c b/net/lwip/wget.c
index ec09814..a3b8290 100644
--- a/net/lwip/wget.c
+++ b/net/lwip/wget.c
@@ -471,7 +471,11 @@
int wget_do_request(ulong dst_addr, char *uri)
{
- net_lwip_set_current();
+ int ret;
+
+ ret = net_lwip_eth_start();
+ if (ret < 0)
+ return ret;
if (!wget_info)
wget_info = &default_wget_info;
diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include
index edc91b2..054dd15 100644
--- a/scripts/Kbuild.include
+++ b/scripts/Kbuild.include
@@ -324,18 +324,16 @@
# do not delete intermediate files automatically
.SECONDARY:
-ifdef CONFIG_XPL_BUILD
-XPL_ := SPL_
+ifeq ($(CONFIG_SPL_BUILD),y)
+PHASE_ := SPL_
+else
ifeq ($(CONFIG_VPL_BUILD),y)
PHASE_ := VPL_
else
ifeq ($(CONFIG_TPL_BUILD),y)
PHASE_ := TPL_
else
-PHASE_ := SPL_
+PHASE_ :=
endif
endif
-else
-XPL_ :=
-PHASE_ :=
endif
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 275c308..83fd5ff 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -377,35 +377,8 @@
; \
sed "s:$(pre-tmp):$(<):" $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
-capsule_esl_input_file=$(srctree)/lib/efi_loader/capsule_esl.dtsi.in
-capsule_crt_file=$(subst $(quote),,$(CONFIG_EFI_CAPSULE_CRT_FILE))
-capsule_esl_dtsi=.capsule_esl.dtsi
-
-quiet_cmd_capsule_esl_gen = CAPSULE_ESL_GEN $@
-cmd_capsule_esl_gen = cert-to-efi-sig-list $< $@
-
-$(obj)/capsule_esl_file: $(capsule_crt_file) FORCE
-ifeq ($(CONFIG_EFI_CAPSULE_CRT_FILE),"")
- $(error "CONFIG_EFI_CAPSULE_CRT_FILE is empty, EFI capsule authentication \
- public key must be specified when CONFIG_EFI_CAPSULE_AUTHENTICATE is enabled")
-else
- $(call cmd,capsule_esl_gen)
-endif
-
-quiet_cmd_capsule_dtsi_gen = CAPSULE_DTSI_GEN $@
-cmd_capsule_dtsi_gen = \
- $(shell sed "s:ESL_BIN_FILE:$(abspath $<):" $(capsule_esl_input_file) > $@)
-
-$(obj)/$(capsule_esl_dtsi): $(obj)/capsule_esl_file FORCE
- $(call cmd,capsule_dtsi_gen)
-
dtsi_include_list_deps := $(addprefix $(u_boot_dtsi_loc),$(subst $(quote),,$(dtsi_include_list)))
-ifdef CONFIG_EFI_CAPSULE_AUTHENTICATE
-dtsi_include_list += $(capsule_esl_dtsi)
-dtsi_include_list_deps += $(obj)/$(capsule_esl_dtsi)
-endif
-
ifneq ($(CHECK_DTBS),)
DT_CHECKER ?= dt-validate
DT_CHECKER_FLAGS ?= $(if $(DT_SCHEMA_FILES),-l $(DT_SCHEMA_FILES),-m)
diff --git a/scripts/Makefile.xpl b/scripts/Makefile.xpl
index abc49fb..43f2787 100644
--- a/scripts/Makefile.xpl
+++ b/scripts/Makefile.xpl
@@ -58,20 +58,18 @@
export SPL_NAME
-ifdef CONFIG_XPL_BUILD
-XPL_ := SPL_
+ifeq ($(CONFIG_SPL_BUILD),y)
+PHASE_ := SPL_
+else
ifeq ($(CONFIG_VPL_BUILD),y)
PHASE_ := VPL_
else
ifeq ($(CONFIG_TPL_BUILD),y)
PHASE_ := TPL_
else
-PHASE_ := SPL_
+PHASE_ :=
endif
endif
-else
-XPL_ :=
-PHASE_ :=
endif
ifeq ($(obj)$(CONFIG_SUPPORT_SPL),spl)
diff --git a/scripts/dtc/dtc-lexer.l b/scripts/dtc/dtc-lexer.l
index d3694d6..d34e1b0 100644
--- a/scripts/dtc/dtc-lexer.l
+++ b/scripts/dtc/dtc-lexer.l
@@ -215,7 +215,7 @@
return DT_REF;
}
-<*>"&{/"{PATHCHAR}*\} { /* new-style path reference */
+<*>"&{"{PATHCHAR}*\} { /* new-style path reference */
yytext[yyleng-1] = '\0';
DPRINT("Ref: %s\n", yytext+2);
yylval.labelref = xstrdup(yytext+2);
diff --git a/scripts/dtc/dtc-parser.y b/scripts/dtc/dtc-parser.y
index 011a5b2..b3b9c83 100644
--- a/scripts/dtc/dtc-parser.y
+++ b/scripts/dtc/dtc-parser.y
@@ -34,6 +34,12 @@
extern struct dt_info *parser_output;
extern bool treesource_error;
+
+static bool is_ref_relative(const char *ref)
+{
+ return ref[0] != '/' && strchr(&ref[1], '/');
+}
+
%}
%union {
@@ -176,12 +182,17 @@
*/
if (!($<flags>-1 & DTSF_PLUGIN))
ERROR(&@2, "Label or path %s not found", $1);
+ else if (is_ref_relative($1))
+ ERROR(&@2, "Label-relative reference %s not supported in plugin", $1);
$$ = add_orphan_node(name_node(build_node(NULL, NULL), ""), $2, $1);
}
| devicetree DT_LABEL DT_REF nodedef
{
struct node *target = get_node_by_ref($1, $3);
+ if (($<flags>-1 & DTSF_PLUGIN) && is_ref_relative($3))
+ ERROR(&@2, "Label-relative reference %s not supported in plugin", $3);
+
if (target) {
add_label(&target->labels, $2);
merge_nodes(target, $4);
@@ -197,6 +208,8 @@
* so $-1 is what we want (plugindecl)
*/
if ($<flags>-1 & DTSF_PLUGIN) {
+ if (is_ref_relative($2))
+ ERROR(&@2, "Label-relative reference %s not supported in plugin", $2);
add_orphan_node($1, $3, $2);
} else {
struct node *target = get_node_by_ref($1, $2);
diff --git a/scripts/dtc/livetree.c b/scripts/dtc/livetree.c
index ba06ef3..4cfc2ad 100644
--- a/scripts/dtc/livetree.c
+++ b/scripts/dtc/livetree.c
@@ -583,12 +583,39 @@
struct node *get_node_by_ref(struct node *tree, const char *ref)
{
+ struct node *target = tree;
+ const char *label = NULL, *path = NULL;
+
if (streq(ref, "/"))
return tree;
- else if (ref[0] == '/')
- return get_node_by_path(tree, ref);
+
+ if (ref[0] == '/')
+ path = ref;
else
- return get_node_by_label(tree, ref);
+ label = ref;
+
+ if (label) {
+ const char *slash = strchr(label, '/');
+ char *buf = NULL;
+
+ if (slash) {
+ buf = xstrndup(label, slash - label);
+ label = buf;
+ path = slash + 1;
+ }
+
+ target = get_node_by_label(tree, label);
+
+ free(buf);
+
+ if (!target)
+ return NULL;
+ }
+
+ if (path)
+ target = get_node_by_path(target, path);
+
+ return target;
}
cell_t get_node_phandle(struct node *root, struct node *node)
diff --git a/scripts/dtc/util.c b/scripts/dtc/util.c
index 23334d3..25d4db1 100644
--- a/scripts/dtc/util.c
+++ b/scripts/dtc/util.c
@@ -46,6 +46,17 @@
return d;
}
+char *xstrndup(const char *s, size_t n)
+{
+ size_t len = strnlen(s, n) + 1;
+ char *d = xmalloc(len);
+
+ memcpy(d, s, len - 1);
+ d[len - 1] = '\0';
+
+ return d;
+}
+
/* based in part from (3) vsnprintf */
int xasprintf(char **strp, const char *fmt, ...)
{
diff --git a/scripts/dtc/util.h b/scripts/dtc/util.h
index 211d584..23e3296 100644
--- a/scripts/dtc/util.h
+++ b/scripts/dtc/util.h
@@ -70,6 +70,7 @@
}
extern char *xstrdup(const char *s);
+extern char *xstrndup(const char *s, size_t len);
extern int PRINTF(2, 3) xasprintf(char **strp, const char *fmt, ...);
extern char *join_path(const char *path, const char *name);
diff --git a/scripts/make_pip.sh b/scripts/make_pip.sh
index d2639ff..33ad51a 100755
--- a/scripts/make_pip.sh
+++ b/scripts/make_pip.sh
@@ -106,6 +106,10 @@
mkdir ${dir}/tests
cd ${dir}
+# Use virtual environment
+python3 -m venv .venv
+source .venv/bin/activate
+
# Make sure the tools are up to date
python3 -m pip install --upgrade build
python3 -m pip install --upgrade twine
@@ -122,6 +126,8 @@
echo "Completed upload of ${tool}"
fi
+# Finish using virtual environment
+deactivate
rm -rf "${dir}"
echo -e "done\n\n"
diff --git a/test/Makefile b/test/Makefile
index 99d4797..f7ab9a3 100644
--- a/test/Makefile
+++ b/test/Makefile
@@ -4,15 +4,15 @@
obj-y += test-main.o
-obj-$(CONFIG_$(XPL_)CMDLINE) += cmd/
-obj-$(CONFIG_$(XPL_)CMDLINE) += cmd_ut.o
+obj-$(CONFIG_$(PHASE_)CMDLINE) += cmd/
+obj-$(CONFIG_$(PHASE_)CMDLINE) += cmd_ut.o
obj-y += dm/
obj-$(CONFIG_FUZZ) += fuzz/
ifndef CONFIG_SANDBOX_VPL
obj-$(CONFIG_UNIT_TEST) += lib/
endif
ifneq ($(CONFIG_HUSH_PARSER),)
-obj-$(CONFIG_$(XPL_)CMDLINE) += hush/
+obj-$(CONFIG_$(PHASE_)CMDLINE) += hush/
endif
obj-$(CONFIG_UT_OPTEE) += optee/
obj-y += ut.o
diff --git a/test/boot/Makefile b/test/boot/Makefile
index 63487e8..00223b4 100644
--- a/test/boot/Makefile
+++ b/test/boot/Makefile
@@ -11,7 +11,7 @@
endif
ifdef CONFIG_SANDBOX
-obj-$(CONFIG_$(XPL_)CMDLINE) += bootm.o
+obj-$(CONFIG_$(PHASE_)CMDLINE) += bootm.o
endif
obj-$(CONFIG_MEASURED_BOOT) += measurement.o
diff --git a/test/boot/bootdev.c b/test/boot/bootdev.c
index d549991..9af9478 100644
--- a/test/boot/bootdev.c
+++ b/test/boot/bootdev.c
@@ -392,8 +392,7 @@
ut_assert_console_end();
ut_assertok(bootdev_hunt("usb1", false));
- ut_assert_nextline(
- "Bus usb@1: scanning bus usb@1 for devices... 5 USB Device(s) found");
+ ut_assert_skip_to_line("Bus usb@1: 5 USB Device(s) found");
ut_assert_console_end();
/* USB is 7th in the list, so bit 8 */
@@ -448,8 +447,7 @@
ut_assert_nextline("scanning bus for devices...");
ut_assert_skip_to_line("Hunting with: spi_flash");
ut_assert_nextline("Hunting with: usb");
- ut_assert_nextline(
- "Bus usb@1: scanning bus usb@1 for devices... 5 USB Device(s) found");
+ ut_assert_skip_to_line("Bus usb@1: 5 USB Device(s) found");
ut_assert_nextline("Hunting with: virtio");
ut_assert_console_end();
@@ -551,8 +549,7 @@
ut_assertok(bootdev_hunt_prio(BOOTDEVP_5_SCAN_SLOW, true));
ut_assert_nextline("Hunting with: ide");
ut_assert_nextline("Hunting with: usb");
- ut_assert_nextline(
- "Bus usb@1: scanning bus usb@1 for devices... 5 USB Device(s) found");
+ ut_assert_skip_to_line("Bus usb@1: 5 USB Device(s) found");
ut_assert_console_end();
return 0;
@@ -604,7 +601,7 @@
ut_assertnonnull(dev);
ut_asserteq_str("usb_mass_storage.lun0.bootdev", dev->name);
ut_asserteq(BOOTFLOW_METHF_SINGLE_UCLASS, mflags);
- ut_assert_nextlinen("Bus usb@1: scanning bus usb@1");
+ ut_assert_nextline("Bus usb@1: 5 USB Device(s) found");
ut_assert_console_end();
return 0;
diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c
index 5f9c037..b261bd5 100644
--- a/test/boot/bootflow.c
+++ b/test/boot/bootflow.c
@@ -1290,7 +1290,7 @@
ut_assertok(run_command("bootflow scan", 0));
ut_assert_skip_to_line(
- "Bus usb@1: scanning bus usb@1 for devices... 5 USB Device(s) found");
+ "Bus usb@1: 5 USB Device(s) found");
ut_assertok(run_command("bootflow list", 0));
diff --git a/test/cmd/Makefile b/test/cmd/Makefile
index d8a5e77..595e4cf 100644
--- a/test/cmd/Makefile
+++ b/test/cmd/Makefile
@@ -3,7 +3,7 @@
# Copyright (c) 2013 Google, Inc
# Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
-obj-$(CONFIG_$(XPL_)CMDLINE) += command.o
+obj-$(CONFIG_$(PHASE_)CMDLINE) += command.o
ifdef CONFIG_HUSH_PARSER
obj-$(CONFIG_CONSOLE_RECORD) += test_echo.o
endif
@@ -39,3 +39,4 @@
endif
obj-$(CONFIG_ARM_FFA_TRANSPORT) += armffa.o
endif
+obj-$(CONFIG_CMD_SPAWN) += spawn.o
diff --git a/test/cmd/command.c b/test/cmd/command.c
index 5ec93d4..5b1e5a7 100644
--- a/test/cmd/command.c
+++ b/test/cmd/command.c
@@ -45,31 +45,32 @@
"setenv list ${list}3", strlen("setenv list 1"), 0);
ut_assert(!strcmp("1", env_get("list")));
- ut_asserteq(1, run_command("false", 0));
ut_assertok(run_command("echo", 0));
- ut_asserteq(1, run_command_list("false", -1, 0));
ut_assertok(run_command_list("echo", -1, 0));
-#ifdef CONFIG_HUSH_PARSER
- run_command("setenv foo 'setenv black 1\nsetenv adder 2'", 0);
- run_command("run foo", 0);
- ut_assertnonnull(env_get("black"));
- ut_asserteq(0, strcmp("1", env_get("black")));
- ut_assertnonnull(env_get("adder"));
- ut_asserteq(0, strcmp("2", env_get("adder")));
-#endif
-
- ut_assertok(run_command("", 0));
- ut_assertok(run_command(" ", 0));
+ if (IS_ENABLED(CONFIG_HUSH_PARSER)) {
+ ut_asserteq(1, run_command("false", 0));
+ ut_asserteq(1, run_command_list("false", -1, 0));
+ run_command("setenv foo 'setenv black 1\nsetenv adder 2'", 0);
+ run_command("run foo", 0);
+ ut_assertnonnull(env_get("black"));
+ ut_asserteq(0, strcmp("1", env_get("black")));
+ ut_assertnonnull(env_get("adder"));
+ ut_asserteq(0, strcmp("2", env_get("adder")));
+ ut_assertok(run_command("", 0));
+ ut_assertok(run_command(" ", 0));
+ }
ut_asserteq(1, run_command("'", 0));
/* Variadic function test-cases */
+ if (IS_ENABLED(CONFIG_HUSH_PARSER)) {
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wformat-zero-length"
- ut_assertok(run_commandf(""));
+ ut_assertok(run_commandf(""));
#pragma GCC diagnostic pop
- ut_assertok(run_commandf(" "));
+ ut_assertok(run_commandf(" "));
+ }
ut_asserteq(1, run_commandf("'"));
ut_assertok(run_commandf("env %s %s", "delete -f", "list"));
diff --git a/test/cmd/spawn.c b/test/cmd/spawn.c
new file mode 100644
index 0000000..8f48f5e
--- /dev/null
+++ b/test/cmd/spawn.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Tests for spawn and wait commands
+ *
+ * Copyright 2025, Linaro Ltd.
+ */
+
+#include <command.h>
+#include <test/cmd.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+static int test_cmd_spawn(struct unit_test_state *uts)
+{
+ ut_assertok(run_command("wait; spawn sleep 2; setenv j ${job_id}; "
+ "spawn setenv spawned true; "
+ "setenv jj ${job_id}; wait; "
+ "echo ${j} ${jj} ${spawned}", 0));
+ console_record_readline(uts->actual_str, sizeof(uts->actual_str));
+ ut_asserteq_ptr(uts->actual_str,
+ strstr(uts->actual_str, "1 2 true"));
+
+ ut_assertok(run_command("spawn true; wait; setenv t $?; spawn false; "
+ "wait; setenv f $?; wait; echo $t $f $?", 0));
+ console_record_readline(uts->actual_str, sizeof(uts->actual_str));
+ ut_asserteq_ptr(uts->actual_str,
+ strstr(uts->actual_str, "0 1 0"));
+ ut_assert_console_end();
+
+ return 0;
+}
+CMD_TEST(test_cmd_spawn, UTF_CONSOLE);
diff --git a/test/common/Makefile b/test/common/Makefile
index 1ad6c24..baefc7b 100644
--- a/test/common/Makefile
+++ b/test/common/Makefile
@@ -1,13 +1,13 @@
# SPDX-License-Identifier: GPL-2.0+
obj-$(CONFIG_AUTOBOOT) += test_autoboot.o
-ifneq ($(CONFIG_$(XPL_)BLOBLIST),)
+ifneq ($(CONFIG_$(PHASE_)BLOBLIST),)
ifdef CONFIG_BLOBLIST_FIXED
-obj-$(CONFIG_$(XPL_)CMDLINE) += bloblist.o
+obj-$(CONFIG_$(PHASE_)CMDLINE) += bloblist.o
endif
endif
obj-$(CONFIG_CYCLIC) += cyclic.o
obj-$(CONFIG_EVENT_DYNAMIC) += event.o
obj-y += cread.o
-obj-$(CONFIG_$(XPL_)CMDLINE) += print.o
+obj-$(CONFIG_$(PHASE_)CMDLINE) += print.o
diff --git a/test/common/print.c b/test/common/print.c
index e3711b1..c48efc2 100644
--- a/test/common/print.c
+++ b/test/common/print.c
@@ -45,11 +45,11 @@
sprintf(str, "%pUL", guid);
ut_asserteq_str("04030201-0605-0807-090A-0B0C0D0E0F10", str);
sprintf(str, "%pUs", guid_esp);
- if (IS_ENABLED(CONFIG_PARTITION_TYPE_GUID)) { /* brace needed */
- ut_asserteq_str("system", str);
- } else {
+ if (IS_ENABLED(CONFIG_PARTITION_TYPE_GUID) ||
+ IS_ENABLED(CONFIG_CMD_EFIDEBUG) || IS_ENABLED(CONFIG_EFI))
+ ut_asserteq_str("EFI System Partition", str);
+ else
ut_asserteq_str("c12a7328-f81f-11d2-ba4b-00a0c93ec93b", str);
- }
ret = snprintf(str, 4, "%pUL", guid);
ut_asserteq(0, str[3]);
ut_asserteq(36, ret);
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 3afcc26..917dafe 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -46,9 +46,7 @@
obj-$(CONFIG_DM_DSA) += dsa.o
obj-$(CONFIG_ECDSA_VERIFY) += ecdsa.o
obj-$(CONFIG_EFI_MEDIA_SANDBOX) += efi_media.o
-ifdef CONFIG_NET
obj-$(CONFIG_DM_ETH) += eth.o
-endif
obj-$(CONFIG_EXTCON) += extcon.o
ifneq ($(CONFIG_EFI_PARTITION),)
obj-$(CONFIG_FASTBOOT_FLASH_MMC) += fastboot.o
diff --git a/test/dm/dsa.c b/test/dm/dsa.c
index c6b4e12..9a31ae3 100644
--- a/test/dm/dsa.c
+++ b/test/dm/dsa.c
@@ -63,15 +63,15 @@
*/
static int dm_test_dsa(struct unit_test_state *uts)
{
- net_ping_ip = string_to_ip("1.2.3.5");
+ char *argv[] = { "ping", "1.1.2.2" };
env_set("ethact", "eth2");
- ut_assertok(net_loop(PING));
+ ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv));
env_set("ethact", "lan0");
- ut_assertok(net_loop(PING));
+ ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv));
env_set("ethact", "lan1");
- ut_assertok(net_loop(PING));
+ ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv));
env_set("ethact", "");
diff --git a/test/dm/eth.c b/test/dm/eth.c
index 4674958..1087ae9 100644
--- a/test/dm/eth.c
+++ b/test/dm/eth.c
@@ -171,18 +171,18 @@
static int dm_test_eth(struct unit_test_state *uts)
{
- net_ping_ip = string_to_ip("1.1.2.2");
+ char *argv[] = { "ping", "1.1.2.2" };
env_set("ethact", "eth@10002000");
- ut_assertok(net_loop(PING));
+ ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv));
ut_asserteq_str("eth@10002000", env_get("ethact"));
env_set("ethact", "eth@10003000");
- ut_assertok(net_loop(PING));
+ ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv));
ut_asserteq_str("eth@10003000", env_get("ethact"));
env_set("ethact", "eth@10004000");
- ut_assertok(net_loop(PING));
+ ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv));
ut_asserteq_str("eth@10004000", env_get("ethact"));
return 0;
@@ -191,22 +191,23 @@
static int dm_test_eth_alias(struct unit_test_state *uts)
{
- net_ping_ip = string_to_ip("1.1.2.2");
+ char *argv[] = { "ping", "1.1.2.2" };
+
env_set("ethact", "eth0");
- ut_assertok(net_loop(PING));
+ ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv));
ut_asserteq_str("eth@10002000", env_get("ethact"));
env_set("ethact", "eth6");
- ut_assertok(net_loop(PING));
+ ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv));
ut_asserteq_str("eth@10004000", env_get("ethact"));
/* Expected to fail since eth1 is not defined in the device tree */
env_set("ethact", "eth1");
- ut_assertok(net_loop(PING));
+ ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv));
ut_asserteq_str("eth@10002000", env_get("ethact"));
env_set("ethact", "eth5");
- ut_assertok(net_loop(PING));
+ ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv));
ut_asserteq_str("eth@10003000", env_get("ethact"));
return 0;
@@ -215,18 +216,18 @@
static int dm_test_eth_prime(struct unit_test_state *uts)
{
- net_ping_ip = string_to_ip("1.1.2.2");
+ char *argv[] = { "ping", "1.1.2.2" };
/* Expected to be "eth@10003000" because of ethprime variable */
env_set("ethact", NULL);
env_set("ethprime", "eth5");
- ut_assertok(net_loop(PING));
+ ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv));
ut_asserteq_str("eth@10003000", env_get("ethact"));
/* Expected to be "eth@10002000" because it is first */
env_set("ethact", NULL);
env_set("ethprime", NULL);
- ut_assertok(net_loop(PING));
+ ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv));
ut_asserteq_str("eth@10002000", env_get("ethact"));
return 0;
@@ -249,6 +250,7 @@
*/
static int dm_test_eth_act(struct unit_test_state *uts)
{
+ char *argv[] = { "ping", "1.1.2.2" };
struct udevice *dev[DM_TEST_ETH_NUM];
const char *ethname[DM_TEST_ETH_NUM] = {"eth@10002000", "eth@10003000",
"sbe5", "eth@10004000"};
@@ -258,7 +260,6 @@
int i;
memset(ethaddr, '\0', sizeof(ethaddr));
- net_ping_ip = string_to_ip("1.1.2.2");
/* Prepare the test scenario */
for (i = 0; i < DM_TEST_ETH_NUM; i++) {
@@ -281,7 +282,7 @@
env_set("ethact", ethname[0]);
/* Segment fault might happen if something is wrong */
- ut_asserteq(-ENODEV, net_loop(PING));
+ ut_asserteq(CMD_RET_FAILURE, do_ping(NULL, 0, ARRAY_SIZE(argv), argv));
for (i = 0; i < DM_TEST_ETH_NUM; i++) {
/* Restore the env */
@@ -334,15 +335,17 @@
/* The asserts include a return on fail; cleanup in the caller */
static int _dm_test_eth_rotate1(struct unit_test_state *uts)
{
+ char *argv[] = { "ping", "1.1.2.2" };
+
/* Make sure that the default is to rotate to the next interface */
env_set("ethact", "eth@10004000");
- ut_assertok(net_loop(PING));
+ ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv));
ut_asserteq_str("eth@10002000", env_get("ethact"));
/* If ethrotate is no, then we should fail on a bad MAC */
env_set("ethact", "eth@10004000");
env_set("ethrotate", "no");
- ut_asserteq(-EINVAL, net_loop(PING));
+ ut_asserteq(CMD_RET_FAILURE, do_ping(NULL, 0, ARRAY_SIZE(argv), argv));
ut_asserteq_str("eth@10004000", env_get("ethact"));
return 0;
@@ -350,14 +353,16 @@
static int _dm_test_eth_rotate2(struct unit_test_state *uts)
{
+ char *argv[] = { "ping", "1.1.2.2" };
+
/* Make sure we can skip invalid devices */
env_set("ethact", "eth@10004000");
- ut_assertok(net_loop(PING));
+ ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv));
ut_asserteq_str("eth@10004000", env_get("ethact"));
/* Make sure we can handle device name which is not eth# */
env_set("ethact", "sbe5");
- ut_assertok(net_loop(PING));
+ ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv));
ut_asserteq_str("sbe5", env_get("ethact"));
return 0;
@@ -368,9 +373,6 @@
char ethaddr[18];
int retval;
- /* Set target IP to mock ping */
- net_ping_ip = string_to_ip("1.1.2.2");
-
/* Invalidate eth1's MAC address */
memset(ethaddr, '\0', sizeof(ethaddr));
strncpy(ethaddr, env_get("eth6addr"), 17);
@@ -396,6 +398,7 @@
/* Restore the env */
env_set("ethaddr", ethaddr);
}
+
/* Restore the env */
env_set(".flags", NULL);
@@ -406,26 +409,28 @@
/* The asserts include a return on fail; cleanup in the caller */
static int _dm_test_net_retry(struct unit_test_state *uts)
{
+ char *argv[] = { "ping", "1.1.2.2" };
+
/*
- * eth1 is disabled and netretry is yes, so the ping should succeed and
- * the active device should be eth0
+ * eth0 is disabled and netretry is yes, so the ping should succeed and
+ * the active device should be eth1
*/
- sandbox_eth_disable_response(1, true);
- env_set("ethact", "lan1");
+ sandbox_eth_disable_response(0, true);
+ env_set("ethact", "eth@10002000");
env_set("netretry", "yes");
sandbox_eth_skip_timeout();
- ut_assertok(net_loop(PING));
- ut_asserteq_str("eth@10002000", env_get("ethact"));
+ ut_assertok(do_ping(NULL, 0, ARRAY_SIZE(argv), argv));
+ ut_asserteq_str("eth@10003000", env_get("ethact"));
/*
- * eth1 is disabled and netretry is no, so the ping should fail and the
- * active device should be eth1
+ * eth0 is disabled and netretry is no, so the ping should fail and the
+ * active device should be eth0
*/
- env_set("ethact", "lan1");
+ env_set("ethact", "eth@10002000");
env_set("netretry", "no");
sandbox_eth_skip_timeout();
- ut_asserteq(-ENONET, net_loop(PING));
- ut_asserteq_str("lan1", env_get("ethact"));
+ ut_asserteq(CMD_RET_FAILURE, do_ping(NULL, 0, ARRAY_SIZE(argv), argv));
+ ut_asserteq_str("eth@10002000", env_get("ethact"));
return 0;
}
@@ -434,8 +439,6 @@
{
int retval;
- net_ping_ip = string_to_ip("1.1.2.2");
-
retval = _dm_test_net_retry(uts);
/* Restore the env */
@@ -446,6 +449,7 @@
}
DM_TEST(dm_test_net_retry, UTF_SCAN_FDT);
+#if CONFIG_IS_ENABLED(NET)
static int sb_check_arp_reply(struct udevice *dev, void *packet,
unsigned int len)
{
@@ -511,7 +515,9 @@
return sb_check_arp_reply(dev, packet, len);
}
+#endif
+#if CONFIG_IS_ENABLED(NET)
static int dm_test_eth_async_arp_reply(struct unit_test_state *uts)
{
net_ping_ip = string_to_ip("1.1.2.2");
@@ -529,7 +535,9 @@
return 0;
}
DM_TEST(dm_test_eth_async_arp_reply, UTF_SCAN_FDT);
+#endif
+#if CONFIG_IS_ENABLED(NET)
static int sb_check_ping_reply(struct udevice *dev, void *packet,
unsigned int len)
{
@@ -613,6 +621,7 @@
return 0;
}
DM_TEST(dm_test_eth_async_ping_reply, UTF_SCAN_FDT);
+#endif
#if IS_ENABLED(CONFIG_IPV6_ROUTER_DISCOVERY)
diff --git a/test/dm/power-domain.c b/test/dm/power-domain.c
index 896cf5b..1002d83 100644
--- a/test/dm/power-domain.c
+++ b/test/dm/power-domain.c
@@ -27,7 +27,7 @@
ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "power-domain-test",
&dev_test));
- ut_asserteq(1, sandbox_power_domain_query(dev_power_domain,
+ ut_asserteq(0, sandbox_power_domain_query(dev_power_domain,
TEST_POWER_DOMAIN));
ut_assertok(sandbox_power_domain_test_get(dev_test));
@@ -35,11 +35,20 @@
ut_asserteq(0, sandbox_power_domain_query(dev_power_domain, 0));
ut_asserteq(1, sandbox_power_domain_query(dev_power_domain,
TEST_POWER_DOMAIN));
+ ut_asserteq(-EALREADY, sandbox_power_domain_test_on_ll(dev_test));
+ ut_asserteq(1, sandbox_power_domain_query(dev_power_domain,
+ TEST_POWER_DOMAIN));
+ ut_asserteq(-EBUSY, sandbox_power_domain_test_off_ll(dev_test));
+ ut_asserteq(1, sandbox_power_domain_query(dev_power_domain,
+ TEST_POWER_DOMAIN));
ut_assertok(sandbox_power_domain_test_off(dev_test));
ut_asserteq(0, sandbox_power_domain_query(dev_power_domain, 0));
ut_asserteq(0, sandbox_power_domain_query(dev_power_domain,
TEST_POWER_DOMAIN));
+ ut_asserteq(-EALREADY, sandbox_power_domain_test_off_ll(dev_test));
+ ut_asserteq(0, sandbox_power_domain_query(dev_power_domain,
+ TEST_POWER_DOMAIN));
ut_assertok(sandbox_power_domain_test_free(dev_test));
diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c
index af8cd61..295fdca 100644
--- a/test/dm/test-fdt.c
+++ b/test/dm/test-fdt.c
@@ -792,7 +792,7 @@
/* Test a few uclass phandle functions */
static int dm_test_fdt_phandle(struct unit_test_state *uts)
{
- struct udevice *back, *dev, *dev2;
+ struct udevice *back, *dispc, *panel, *dev, *dev2;
ut_assertok(uclass_find_first_device(UCLASS_PANEL_BACKLIGHT, &back));
ut_assertnonnull(back);
@@ -807,6 +807,24 @@
"power-supply", &dev2));
ut_asserteq_ptr(dev, dev2);
+ /* Test uclass_get_device_by_endpoint() */
+ ut_assertok(uclass_find_device_by_name(UCLASS_VIDEO_BRIDGE, "lvds-encoder", &dispc));
+ ut_assertnonnull(dispc);
+ ut_asserteq(0, device_active(dispc));
+ ut_assertok(uclass_find_device_by_name(UCLASS_PANEL, "panel", &panel));
+ ut_assertnonnull(panel);
+ ut_asserteq(0, device_active(panel));
+
+ ut_asserteq(-ENODEV, uclass_get_device_by_endpoint(UCLASS_PANEL_BACKLIGHT, dispc, 1, -1, &dev));
+ ut_asserteq(-EINVAL, uclass_get_device_by_endpoint(UCLASS_PANEL, dispc, 0, -1, &dev));
+ ut_assertok(uclass_get_device_by_endpoint(UCLASS_PANEL, dispc, 1, -1, &dev));
+ ut_asserteq_ptr(panel, dev);
+
+ ut_asserteq(-ENODEV, uclass_get_device_by_endpoint(UCLASS_PANEL_BACKLIGHT, panel, -1, -1, &dev2));
+ ut_asserteq(-EINVAL, uclass_get_device_by_endpoint(UCLASS_VIDEO_BRIDGE, panel, 1, -1, &dev2));
+ ut_assertok(uclass_get_device_by_endpoint(UCLASS_VIDEO_BRIDGE, panel, -1, -1, &dev2));
+ ut_asserteq_ptr(dispc, dev2);
+
return 0;
}
DM_TEST(dm_test_fdt_phandle, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/video.c b/test/dm/video.c
index e347c14..929fc16 100644
--- a/test/dm/video.c
+++ b/test/dm/video.c
@@ -54,43 +54,64 @@
* size of the compressed data. This provides a pretty good level of
* certainty and the resulting tests need only check a single value.
*
- * If the copy framebuffer is enabled, this compares it to the main framebuffer
- * too.
- *
* @uts: Test state
* @dev: Video device
+ * @use_copy: Use copy frame buffer if available
* Return: compressed size of the frame buffer, or -ve on error
*/
static int compress_frame_buffer(struct unit_test_state *uts,
- struct udevice *dev)
+ struct udevice *dev,
+ bool use_copy)
{
struct video_priv *priv = dev_get_uclass_priv(dev);
- struct video_priv *uc_priv = dev_get_uclass_priv(dev);
uint destlen;
void *dest;
int ret;
+ if (!IS_ENABLED(CONFIG_VIDEO_COPY))
+ use_copy = false;
+
destlen = priv->fb_size;
dest = malloc(priv->fb_size);
if (!dest)
return -ENOMEM;
ret = BZ2_bzBuffToBuffCompress(dest, &destlen,
- priv->fb, priv->fb_size,
+ use_copy ? priv->copy_fb : priv->fb,
+ priv->fb_size,
3, 0, 0);
free(dest);
if (ret)
return ret;
- /* Check here that the copy frame buffer is working correctly */
- if (IS_ENABLED(CONFIG_VIDEO_COPY)) {
- ut_assertf(!memcmp(uc_priv->fb, uc_priv->copy_fb,
- uc_priv->fb_size),
- "Copy framebuffer does not match fb");
- }
-
return destlen;
}
+/**
+ * check_copy_frame_buffer() - Compare main frame buffer to copy
+ *
+ * If the copy frame buffer is enabled, this compares it to the main
+ * frame buffer. Normally they should have the same contents after a
+ * sync.
+ *
+ * @uts: Test state
+ * @dev: Video device
+ * Return: 0, or -ve on error
+ */
+static int check_copy_frame_buffer(struct unit_test_state *uts,
+ struct udevice *dev)
+{
+ struct video_priv *priv = dev_get_uclass_priv(dev);
+
+ if (!IS_ENABLED(CONFIG_VIDEO_COPY))
+ return 0;
+
+ video_sync(dev, false);
+ ut_assertf(!memcmp(priv->fb, priv->copy_fb, priv->fb_size),
+ "Copy framebuffer does not match fb");
+
+ return 0;
+}
+
/*
* Call this function at any point to halt and show the current display. Be
* sure to run the test with the -l flag.
@@ -153,25 +174,31 @@
ut_assertok(video_get_nologo(uts, &dev));
ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
ut_assertok(vidconsole_select_font(con, "8x16", 0));
- ut_asserteq(46, compress_frame_buffer(uts, dev));
+ ut_asserteq(46, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
vidconsole_putc_xy(con, 0, 0, 'a');
- ut_asserteq(79, compress_frame_buffer(uts, dev));
+ ut_asserteq(79, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
vidconsole_putc_xy(con, 0, 0, ' ');
- ut_asserteq(46, compress_frame_buffer(uts, dev));
+ ut_asserteq(46, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
for (i = 0; i < 20; i++)
vidconsole_putc_xy(con, VID_TO_POS(i * 8), 0, ' ' + i);
- ut_asserteq(273, compress_frame_buffer(uts, dev));
+ ut_asserteq(273, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
vidconsole_set_row(con, 0, WHITE);
- ut_asserteq(46, compress_frame_buffer(uts, dev));
+ ut_asserteq(46, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
for (i = 0; i < 20; i++)
vidconsole_putc_xy(con, VID_TO_POS(i * 8), 0, ' ' + i);
- ut_asserteq(273, compress_frame_buffer(uts, dev));
+ ut_asserteq(273, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
return 0;
}
@@ -189,25 +216,31 @@
ut_assertok(video_get_nologo(uts, &dev));
ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
ut_assertok(vidconsole_select_font(con, "12x22", 0));
- ut_asserteq(46, compress_frame_buffer(uts, dev));
+ ut_asserteq(46, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
vidconsole_putc_xy(con, 0, 0, 'a');
- ut_asserteq(89, compress_frame_buffer(uts, dev));
+ ut_asserteq(89, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
vidconsole_putc_xy(con, 0, 0, ' ');
- ut_asserteq(46, compress_frame_buffer(uts, dev));
+ ut_asserteq(46, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
for (i = 0; i < 20; i++)
vidconsole_putc_xy(con, VID_TO_POS(i * 8), 0, ' ' + i);
- ut_asserteq(363, compress_frame_buffer(uts, dev));
+ ut_asserteq(363, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
vidconsole_set_row(con, 0, WHITE);
- ut_asserteq(46, compress_frame_buffer(uts, dev));
+ ut_asserteq(46, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
for (i = 0; i < 20; i++)
vidconsole_putc_xy(con, VID_TO_POS(i * 8), 0, ' ' + i);
- ut_asserteq(363, compress_frame_buffer(uts, dev));
+ ut_asserteq(363, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
return 0;
}
@@ -224,7 +257,8 @@
ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
ut_assertok(vidconsole_select_font(con, "8x16", 0));
vidconsole_put_string(con, test_string);
- ut_asserteq(466, compress_frame_buffer(uts, dev));
+ ut_asserteq(466, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
return 0;
}
@@ -245,20 +279,24 @@
/* reference clear: */
video_clear(con->parent);
video_sync(con->parent, false);
- ut_asserteq(46, compress_frame_buffer(uts, dev));
+ ut_asserteq(46, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
/* test clear escape sequence: [2J */
vidconsole_put_string(con, "A\tB\tC"ANSI_ESC"[2J");
- ut_asserteq(46, compress_frame_buffer(uts, dev));
+ ut_asserteq(46, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
/* test set-cursor: [%d;%df */
vidconsole_put_string(con, "abc"ANSI_ESC"[2;2fab"ANSI_ESC"[4;4fcd");
- ut_asserteq(143, compress_frame_buffer(uts, dev));
+ ut_asserteq(143, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
/* test colors (30-37 fg color, 40-47 bg color) */
vidconsole_put_string(con, ANSI_ESC"[30;41mfoo"); /* black on red */
vidconsole_put_string(con, ANSI_ESC"[33;44mbar"); /* yellow on blue */
- ut_asserteq(272, compress_frame_buffer(uts, dev));
+ ut_asserteq(272, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
return 0;
}
@@ -290,24 +328,28 @@
ut_assertok(video_get_nologo(uts, &dev));
ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
ut_assertok(vidconsole_select_font(con, "8x16", 0));
- ut_asserteq(46, compress_frame_buffer(uts, dev));
+ ut_asserteq(46, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
/* Check display wrap */
for (i = 0; i < 120; i++)
vidconsole_put_char(con, 'A' + i % 50);
- ut_asserteq(wrap_size, compress_frame_buffer(uts, dev));
+ ut_asserteq(wrap_size, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
/* Check display scrolling */
for (i = 0; i < SCROLL_LINES; i++) {
vidconsole_put_char(con, 'A' + i % 50);
vidconsole_put_char(con, '\n');
}
- ut_asserteq(scroll_size, compress_frame_buffer(uts, dev));
+ ut_asserteq(scroll_size, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
/* If we scroll enough, the screen becomes blank again */
for (i = 0; i < SCROLL_LINES; i++)
vidconsole_put_char(con, '\n');
- ut_asserteq(46, compress_frame_buffer(uts, dev));
+ ut_asserteq(46, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
return 0;
}
@@ -381,7 +423,8 @@
ut_assertok(read_file(uts, "tools/logos/denx.bmp", &addr));
ut_assertok(video_bmp_display(dev, addr, 0, 0, false));
- ut_asserteq(1368, compress_frame_buffer(uts, dev));
+ ut_asserteq(1368, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
return 0;
}
@@ -400,7 +443,8 @@
ut_assertok(read_file(uts, "tools/logos/denx.bmp", &addr));
ut_assertok(video_bmp_display(dev, addr, 0, 0, false));
- ut_asserteq(1247, compress_frame_buffer(uts, dev));
+ ut_asserteq(1247, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
return 0;
}
@@ -423,7 +467,8 @@
&src_len));
ut_assertok(video_bmp_display(dev, dst, 0, 0, false));
- ut_asserteq(3700, compress_frame_buffer(uts, dev));
+ ut_asserteq(3700, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
return 0;
}
@@ -446,7 +491,8 @@
&src_len));
ut_assertok(video_bmp_display(dev, dst, 0, 0, false));
- ut_asserteq(3656, compress_frame_buffer(uts, dev));
+ ut_asserteq(3656, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
return 0;
}
@@ -469,7 +515,8 @@
&src_len));
ut_assertok(video_bmp_display(dev, dst, 0, 0, false));
- ut_asserteq(6827, compress_frame_buffer(uts, dev));
+ ut_asserteq(6827, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
return 0;
}
@@ -487,7 +534,8 @@
ut_assertok(read_file(uts, "tools/logos/denx.bmp", &addr));
ut_assertok(video_bmp_display(dev, addr, 0, 0, false));
- ut_asserteq(2024, compress_frame_buffer(uts, dev));
+ ut_asserteq(2024, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
return 0;
}
@@ -503,7 +551,8 @@
ut_assertok(read_file(uts, "tools/logos/denx-comp.bmp", &addr));
ut_assertok(video_bmp_display(dev, addr, 0, 0, false));
- ut_asserteq(1368, compress_frame_buffer(uts, dev));
+ ut_asserteq(1368, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
return 0;
}
@@ -522,7 +571,8 @@
ut_assertok(read_file(uts, "tools/logos/denx.bmp", &addr));
ut_assertok(video_bmp_display(dev, addr, 0, 0, false));
- ut_asserteq(2024, compress_frame_buffer(uts, dev));
+ ut_asserteq(2024, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
return 0;
}
@@ -541,7 +591,8 @@
ut_assertok(read_file(uts, "tools/logos/denx.bmp", &addr));
ut_assertok(video_bmp_display(dev, addr, 0, 0, false));
- ut_asserteq(1247, compress_frame_buffer(uts, dev));
+ ut_asserteq(1247, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
return 0;
}
@@ -556,7 +607,8 @@
ut_assertok(video_get_nologo(uts, &dev));
ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
vidconsole_put_string(con, test_string);
- ut_asserteq(12174, compress_frame_buffer(uts, dev));
+ ut_asserteq(12174, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
return 0;
}
@@ -577,7 +629,8 @@
ut_assertok(video_get_nologo(uts, &dev));
ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
vidconsole_put_string(con, test_string);
- ut_asserteq(34287, compress_frame_buffer(uts, dev));
+ ut_asserteq(34287, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
return 0;
}
@@ -598,8 +651,129 @@
ut_assertok(video_get_nologo(uts, &dev));
ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
vidconsole_put_string(con, test_string);
- ut_asserteq(29471, compress_frame_buffer(uts, dev));
+ ut_asserteq(29471, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
return 0;
}
DM_TEST(dm_test_video_truetype_bs, UTF_SCAN_PDATA | UTF_SCAN_FDT);
+
+/* Test partial rendering onto hardware frame buffer */
+static int dm_test_video_copy(struct unit_test_state *uts)
+{
+ struct sandbox_sdl_plat *plat;
+ struct video_uc_plat *uc_plat;
+ struct udevice *dev, *con;
+ struct video_priv *priv;
+ const char *test_string = "\n\tCriticism may not be agreeable, but it is necessary.\t";
+ ulong addr;
+
+ if (!IS_ENABLED(CONFIG_VIDEO_COPY))
+ return -EAGAIN;
+
+ ut_assertok(uclass_find_first_device(UCLASS_VIDEO, &dev));
+ ut_assertnonnull(dev);
+ uc_plat = dev_get_uclass_plat(dev);
+ uc_plat->hide_logo = true;
+ plat = dev_get_plat(dev);
+ plat->font_size = 32;
+ ut_assert(!device_active(dev));
+ ut_assertok(uclass_first_device_err(UCLASS_VIDEO, &dev));
+ ut_assertnonnull(dev);
+ priv = dev_get_uclass_priv(dev);
+
+ ut_assertok(read_file(uts, "tools/logos/denx.bmp", &addr));
+ ut_assertok(video_bmp_display(dev, addr, 0, 0, false));
+
+ ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
+ vidconsole_put_string(con, "\n\n\n\n\n");
+ vidconsole_put_string(con, test_string);
+ vidconsole_put_string(con, test_string);
+
+ ut_asserteq(6678, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
+
+ /*
+ * Secretly clear the hardware frame buffer, but in a different
+ * color (black) to see which parts will be overwritten.
+ */
+ memset(priv->copy_fb, 0, priv->fb_size);
+
+ /*
+ * We should have the full content on the main buffer, but only
+ * 'damage' should have been copied to the copy buffer. This consists
+ * of a while rectangle with the Denx logo and four lines of text. The
+ * rest of the display is black.
+ *
+ * An easy way to try this is by changing video_sync() to call
+ * sandbox_sdl_sync(priv->copy_fb) instead of priv->fb then running the
+ * unit test:
+ *
+ * ./u-boot -Tl
+ * ut dm dm_test_video_copy
+ */
+ vidconsole_put_string(con, test_string);
+ vidconsole_put_string(con, test_string);
+ video_sync(dev, true);
+ ut_asserteq(7589, compress_frame_buffer(uts, dev, false));
+ ut_asserteq(7704, compress_frame_buffer(uts, dev, true));
+
+ return 0;
+}
+DM_TEST(dm_test_video_copy, UTF_SCAN_PDATA | UTF_SCAN_FDT);
+
+/* Test video damage tracking */
+static int dm_test_video_damage(struct unit_test_state *uts)
+{
+ struct sandbox_sdl_plat *plat;
+ struct udevice *dev, *con;
+ struct video_priv *priv;
+ const char *test_string_1 = "Criticism may not be agreeable, ";
+ const char *test_string_2 = "but it is necessary.";
+ const char *test_string_3 = "It fulfils the same function as pain in the human body.";
+
+ if (!IS_ENABLED(CONFIG_VIDEO_DAMAGE))
+ return -EAGAIN;
+
+ ut_assertok(uclass_find_device(UCLASS_VIDEO, 0, &dev));
+ ut_assert(!device_active(dev));
+ plat = dev_get_plat(dev);
+ plat->font_size = 32;
+
+ ut_assertok(video_get_nologo(uts, &dev));
+ ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
+ priv = dev_get_uclass_priv(dev);
+
+ vidconsole_position_cursor(con, 14, 10);
+ vidconsole_put_string(con, test_string_2);
+ ut_asserteq(449, priv->damage.xstart);
+ ut_asserteq(325, priv->damage.ystart);
+ ut_asserteq(661, priv->damage.xend);
+ ut_asserteq(350, priv->damage.yend);
+
+ vidconsole_position_cursor(con, 7, 5);
+ vidconsole_put_string(con, test_string_1);
+ ut_asserteq(225, priv->damage.xstart);
+ ut_asserteq(164, priv->damage.ystart);
+ ut_asserteq(661, priv->damage.xend);
+ ut_asserteq(350, priv->damage.yend);
+
+ vidconsole_position_cursor(con, 21, 15);
+ vidconsole_put_string(con, test_string_3);
+ ut_asserteq(225, priv->damage.xstart);
+ ut_asserteq(164, priv->damage.ystart);
+ ut_asserteq(1280, priv->damage.xend);
+ ut_asserteq(510, priv->damage.yend);
+
+ video_sync(dev, true);
+ ut_asserteq(priv->xsize, priv->damage.xstart);
+ ut_asserteq(priv->ysize, priv->damage.ystart);
+ ut_asserteq(0, priv->damage.xend);
+ ut_asserteq(0, priv->damage.yend);
+
+ ut_asserteq(7339, compress_frame_buffer(uts, dev, false));
+ ut_assertok(check_copy_frame_buffer(uts, dev));
+
+ return 0;
+}
+DM_TEST(dm_test_video_damage, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/fuzz/Makefile b/test/fuzz/Makefile
index 8a135b6..0a8f3d1 100644
--- a/test/fuzz/Makefile
+++ b/test/fuzz/Makefile
@@ -4,5 +4,5 @@
# Written by Andrew Scull <ascull@google.com>
#
-obj-$(CONFIG_$(XPL_)CMDLINE) += cmd_fuzz.o
+obj-$(CONFIG_$(PHASE_)CMDLINE) += cmd_fuzz.o
obj-$(CONFIG_VIRTIO_SANDBOX) += virtio.o
diff --git a/test/lib/Makefile b/test/lib/Makefile
index aa89923..d620510 100644
--- a/test/lib/Makefile
+++ b/test/lib/Makefile
@@ -3,7 +3,7 @@
# (C) Copyright 2018
# Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
-obj-$(CONFIG_$(XPL_)UT_COMPRESSION) += compression.o
+obj-$(CONFIG_$(PHASE_)UT_COMPRESSION) += compression.o
ifeq ($(CONFIG_XPL_BUILD),)
obj-y += abuf.o
@@ -15,6 +15,7 @@
obj-y += lmb.o
obj-$(CONFIG_HAVE_SETJMP) += longjmp.o
obj-$(CONFIG_SANDBOX) += membuf.o
+obj-$(CONFIG_HAVE_INITJMP) += initjmp.o
obj-$(CONFIG_CONSOLE_RECORD) += test_print.o
obj-$(CONFIG_SSCANF) += sscanf.o
obj-$(CONFIG_$(PHASE_)STRTO) += str.o
@@ -30,7 +31,8 @@
obj-$(CONFIG_CRC8) += test_crc8.o
obj-$(CONFIG_UT_LIB_CRYPT) += test_crypt.o
obj-$(CONFIG_UT_TIME) += time.o
-obj-$(CONFIG_$(XPL_)UT_UNICODE) += unicode.o
+obj-$(CONFIG_$(PHASE_)UT_UNICODE) += unicode.o
+obj-$(CONFIG_UTHREAD) += uthread.o
obj-$(CONFIG_LIB_UUID) += uuid.o
else
obj-$(CONFIG_SANDBOX) += kconfig_spl.o
diff --git a/test/lib/initjmp.c b/test/lib/initjmp.c
new file mode 100644
index 0000000..5b4b50b
--- /dev/null
+++ b/test/lib/initjmp.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2025 Linaro Limited
+ *
+ * Unit test for initjmp()
+ */
+
+#include <compiler.h>
+#include <setjmp.h>
+#include <stdbool.h>
+#include <test/lib.h>
+#include <test/ut.h>
+#include <vsprintf.h>
+
+static bool ep_entered;
+static jmp_buf return_buf;
+
+static void __noreturn entrypoint(void)
+{
+ ep_entered = true;
+
+ /* Jump back to the main routine */
+ longjmp(return_buf, 1);
+
+ /* Not reached */
+ panic("longjmp failed\n");
+}
+
+static int lib_initjmp(struct unit_test_state *uts)
+{
+ int ret;
+ void *stack;
+ jmp_buf buf;
+ /* Arbitrary but smaller values (< page size?) fail on SANDBOX */
+ size_t stack_sz = 8192;
+
+ (void)entrypoint;
+
+ ep_entered = false;
+
+ stack = malloc(stack_sz);
+ ut_assertnonnull(stack);
+
+ /*
+ * Prepare return_buf so that entrypoint may jump back just after the
+ * if()
+ */
+ if (!setjmp(return_buf)) {
+ /* return_buf initialized, entrypoint not yet called */
+
+ /*
+ * Prepare another jump buffer to jump into entrypoint with the
+ * given stack
+ */
+ ret = initjmp(buf, entrypoint, stack, stack_sz);
+ ut_assertok(ret);
+
+ /* Jump into entrypoint */
+ longjmp(buf, 1);
+ /*
+ * Not reached since entrypoint is expected to branch after
+ * the if()
+ */
+ ut_assert(false);
+ }
+
+ ut_assert(ep_entered);
+
+ free(stack);
+
+ return 0;
+}
+LIB_TEST(lib_initjmp, 0);
diff --git a/test/lib/uthread.c b/test/lib/uthread.c
new file mode 100644
index 0000000..10a94d1
--- /dev/null
+++ b/test/lib/uthread.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 Linaro Limited
+ *
+ * Unit test for uthread
+ */
+
+#include <stdbool.h>
+#include <test/lib.h>
+#include <test/ut.h>
+#include <uthread.h>
+
+static int count;
+
+/* A thread entry point */
+static void worker(void *arg)
+{
+ int loops = (int)(unsigned long)arg;
+ int i;
+
+ for (i = 0; i < loops; i++) {
+ count++;
+ uthread_schedule();
+ }
+}
+
+/*
+ * uthread() - testing the uthread API
+ *
+ * This function creates two threads with the same entry point. The first one
+ * receives 5 as an argument, the second one receives 10. The number indicates
+ * the number of time the worker thread should loop on uthread_schedule()
+ * before returning. The workers increment a global counter each time they loop.
+ * As a result the main thread knows how many times it should call
+ * uthread_schedule() to let the two threads proceed, and it also knows which
+ * value the counter should have at any moment.
+ */
+static int uthread(struct unit_test_state *uts)
+{
+ int i;
+ int id1, id2;
+
+ count = 0;
+ id1 = uthread_grp_new_id();
+ ut_assert(id1 != 0);
+ id2 = uthread_grp_new_id();
+ ut_assert(id2 != 0);
+ ut_assert(id1 != id2);
+ ut_assertok(uthread_create(NULL, worker, (void *)5, 0, id1));
+ ut_assertok(uthread_create(NULL, worker, (void *)10, 0, 0));
+ /*
+ * The first call is expected to schedule the first worker, which will
+ * schedule the second one, which will schedule back to the main thread
+ * (here). Therefore count should be 2.
+ */
+ ut_assert(uthread_schedule());
+ ut_asserteq(2, count);
+ ut_assert(!uthread_grp_done(id1));
+ /* Four more calls should bring the count to 10 */
+ for (i = 0; i < 4; i++) {
+ ut_assert(!uthread_grp_done(id1));
+ ut_assert(uthread_schedule());
+ }
+ ut_asserteq(10, count);
+ /* This one allows the first worker to exit */
+ ut_assert(uthread_schedule());
+ /* At this point there should be no runnable thread in group 'id1' */
+ ut_assert(uthread_grp_done(id1));
+ /* Five more calls for the second worker to finish incrementing */
+ for (i = 0; i < 5; i++)
+ ut_assert(uthread_schedule());
+ ut_asserteq(15, count);
+ /* Plus one call to let the second worker return from its entry point */
+ ut_assert(uthread_schedule());
+ /* Now both tasks should be done, schedule should return false */
+ ut_assert(!uthread_schedule());
+
+ return 0;
+}
+LIB_TEST(uthread, 0);
+
+struct mw_args {
+ struct unit_test_state *uts;
+ struct uthread_mutex *m;
+ int flag;
+};
+
+static int mutex_worker_ret;
+
+static int _mutex_worker(struct mw_args *args)
+{
+ struct unit_test_state *uts = args->uts;
+
+ ut_asserteq(-EBUSY, uthread_mutex_trylock(args->m));
+ ut_assertok(uthread_mutex_lock(args->m));
+ args->flag = 1;
+ ut_assertok(uthread_mutex_unlock(args->m));
+
+ return 0;
+}
+
+static void mutex_worker(void *arg)
+{
+ mutex_worker_ret = _mutex_worker((struct mw_args *)arg);
+}
+
+/*
+ * thread_mutex() - testing uthread mutex operations
+ *
+ */
+static int uthread_mutex(struct unit_test_state *uts)
+{
+ struct uthread_mutex m = UTHREAD_MUTEX_INITIALIZER;
+ struct mw_args args = { .uts = uts, .m = &m, .flag = 0 };
+ int id;
+ int i;
+
+ id = uthread_grp_new_id();
+ ut_assert(id != 0);
+ /* Take the mutex */
+ ut_assertok(uthread_mutex_lock(&m));
+ /* Start a thread */
+ ut_assertok(uthread_create(NULL, mutex_worker, (void *)&args, 0,
+ id));
+ /* Let the thread run for a bit */
+ for (i = 0; i < 100; i++)
+ ut_assert(uthread_schedule());
+ /* Thread should not have set the flag due to the mutex */
+ ut_asserteq(0, args.flag);
+ /* Release the mutex */
+ ut_assertok(uthread_mutex_unlock(&m));
+ /* Schedule the thread until it is done */
+ while (uthread_schedule())
+ ;
+ /* Now the flag should be set */
+ ut_asserteq(1, args.flag);
+ /* And the mutex should be available */
+ ut_assertok(uthread_mutex_trylock(&m));
+ ut_assertok(uthread_mutex_unlock(&m));
+
+ /* Of course no error are expected from the thread routine */
+ ut_assertok(mutex_worker_ret);
+
+ return 0;
+}
+LIB_TEST(uthread_mutex, 0);
diff --git a/test/py/tests/test_fs/conftest.py b/test/py/tests/test_fs/conftest.py
index c73fb4a..0205048 100644
--- a/test/py/tests/test_fs/conftest.py
+++ b/test/py/tests/test_fs/conftest.py
@@ -17,7 +17,7 @@
supported_fs_mkdir = ['fat12', 'fat16', 'fat32', 'exfat', 'fs_generic']
supported_fs_unlink = ['fat12', 'fat16', 'fat32', 'exfat', 'fs_generic']
supported_fs_symlink = ['ext4']
-supported_fs_rename = ['fat12', 'fat16', 'fat32']
+supported_fs_rename = ['fat12', 'fat16', 'fat32', 'exfat', 'fs_generic']
#
# Filesystem test specific setup
diff --git a/test/py/tests/test_fs/test_basic.py b/test/py/tests/test_fs/test_basic.py
index 64a3b50..88b163c 100644
--- a/test/py/tests/test_fs/test_basic.py
+++ b/test/py/tests/test_fs/test_basic.py
@@ -35,6 +35,19 @@
'%sls host 0:0 invalid_d' % fs_cmd_prefix)
assert('' == output)
+ with ubman.log.section('Test Case 1c - test -e'):
+ # Test Case 1 - test -e
+ output = ubman.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ 'test -e host 0:0 1MB.file && echo PASS'])
+ assert('PASS' in ''.join(output))
+
+ with ubman.log.section('Test Case 1d - test -e (invalid file)'):
+ # In addition, test with a nonexistent file to see if we crash.
+ output = ubman.run_command(
+ 'test -e host 0:0 2MB.file || echo PASS')
+ assert('PASS' in ''.join(output))
+
def test_fs2(self, ubman, fs_obj_basic):
"""
Test Case 2 - size command for a small file
diff --git a/test/py/tests/test_memtest.py b/test/py/tests/test_memtest.py
index 0340edb..f24f9f0 100644
--- a/test/py/tests/test_memtest.py
+++ b/test/py/tests/test_memtest.py
@@ -29,12 +29,12 @@
if not f:
pytest.skip("memtest is not enabled!")
else:
- start = f.get("start_addr", 0x0)
- size = f.get("size", 0x1000)
- pattern = f.get("pattern", 0x0)
+ start = hex(f.get("start_addr", 0x0))
+ size = hex(f.get("size", 0x1000))
+ pattern = hex(f.get("pattern", 0x0))
iteration = f.get("iteration", 2)
timeout = f.get("timeout", 50000)
- end = hex(int(start) + int(size))
+ end = hex(int(start, 16) + int(size, 16))
return start, end, pattern, iteration, timeout
@pytest.mark.buildconfigspec("cmd_memtest")
diff --git a/test/py/tests/test_spi.py b/test/py/tests/test_spi.py
index dd76752..09174f9 100644
--- a/test/py/tests/test_spi.py
+++ b/test/py/tests/test_spi.py
@@ -703,4 +703,33 @@
ubman, 'read', start, size, res_area, 1, error_msg, EXPECTED_READ
)
+ # Start reading from the reserved area
+ m = re.search(r'reserved\[0\]\s*\[(0x.+)-(0x.+)\]', output)
+ if not m or int(m.group(1), 16) == 0:
+ ubman.log.info('No reserved area is defined or start addr is 0x0!')
+ else:
+ rstart_area = int(m.group(1), 16)
+ rend_area = int(m.group(2), 16)
+
+ # Case 1: Start reading from the middle of the reserved area
+ r_size = rend_area - rstart_area
+ r_area = rstart_area + r_size
+ flash_ops(
+ ubman, 'read', start, size, r_area, 1, error_msg, EXPECTED_READ
+ )
+
+ # Case 2: Start reading from before the reserved area to cross-over
+ # the reserved area
+ rstart_area = rstart_area - int(size/2)
+ flash_ops(
+ ubman, 'read', start, size, rstart_area, 1, error_msg, EXPECTED_READ
+ )
+
+ # Case 3: Start reading till after the reserved area to cross-over
+ # the reserved area
+ rend_area = rend_area - int(size/2)
+ flash_ops(
+ ubman, 'read', start, size, rend_area, 1, error_msg, EXPECTED_READ
+ )
+
i = i + 1
diff --git a/test/py/tests/test_trace.py b/test/py/tests/test_trace.py
index 6ac1b22..fcdcbe2 100644
--- a/test/py/tests/test_trace.py
+++ b/test/py/tests/test_trace.py
@@ -201,7 +201,7 @@
# Then look for this:
# u-boot-1 0..... 282.101375: funcgraph_exit: 0.006 us | }
# Then check for this:
- # u-boot-1 0..... 282.101375: funcgraph_entry: 0.000 us | calc_reloc_ofs();
+ # u-boot-1 0..... 282.101375: funcgraph_entry: 0.000 us | event_init();
expected_indent = None
found_start = False
@@ -224,8 +224,8 @@
found_end = True
# The next function after initf_bootstage() exits should be
- # initcall_is_event()
- assert upto == 'calc_reloc_ofs()'
+ # event_init()
+ assert upto == 'event_init()'
# Now look for initf_dm() and dm_timer_init() so we can check the bootstage
# time
@@ -274,7 +274,7 @@
# We expect dm_timer_init() to be called twice: once before relocation and
# once after
look1 = 'initf_dm;dm_timer_init 1'
- look2 = 'board_init_r;initcall_run_list;initr_dm_devices;dm_timer_init 1'
+ look2 = 'board_init_r;initcall_run_r;initr_dm_devices;dm_timer_init 1'
found = 0
with open(trace_fg, 'r') as fd:
for line in fd:
diff --git a/tools/Makefile b/tools/Makefile
index 53b87d2..97ce1db 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -63,8 +63,7 @@
hostprogs-y += mkenvimage
mkenvimage-objs := mkenvimage.o os_support.o generated/lib/crc32.o
-hostprogs-y += dumpimage mkimage
-hostprogs-$(CONFIG_TOOLS_LIBCRYPTO) += fit_info fit_check_sign
+hostprogs-y += dumpimage mkimage fit_info fit_check_sign
hostprogs-$(CONFIG_TOOLS_LIBCRYPTO) += fdt_add_pubkey
hostprogs-$(CONFIG_TOOLS_LIBCRYPTO) += preload_check_sign
@@ -169,6 +168,8 @@
fdt_add_pubkey-objs := $(dumpimage-mkimage-objs) fdt_add_pubkey.o
file2include-objs := file2include.o
preload_check_sign-objs := $(dumpimage-mkimage-objs) $(PRELOAD_OBJS-y) preload_check_sign.o
+HOSTCFLAGS_preload_check_sign.o += \
+ $(shell pkg-config --cflags libssl libcrypto 2> /dev/null || echo "")
ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_TOOLS_LIBCRYPTO),)
# Add CFG_MXS into host CFLAGS, so we can check whether or not register
@@ -207,6 +208,8 @@
HOSTLDLIBS_fit_check_sign := $(HOSTLDLIBS_mkimage)
HOSTLDLIBS_fdt_add_pubkey := $(HOSTLDLIBS_mkimage)
HOSTLDLIBS_preload_check_sign := $(HOSTLDLIBS_mkimage)
+HOSTLDLIBS_preload_check_sign += \
+ $(shell pkg-config --libs libssl libcrypto 2> /dev/null || echo "-lssl -lcrypto")
hostprogs-$(CONFIG_EXYNOS5250) += mkexynosspl
hostprogs-$(CONFIG_EXYNOS5420) += mkexynosspl
diff --git a/tools/binman/elf.py b/tools/binman/elf.py
index c75f447..6ac960e 100644
--- a/tools/binman/elf.py
+++ b/tools/binman/elf.py
@@ -28,7 +28,7 @@
# BSYM in little endian, keep in sync with include/binman_sym.h
BINMAN_SYM_MAGIC_VALUE = 0x4d595342
-# Information about an EFL symbol:
+# Information about an ELF symbol:
# section (str): Name of the section containing this symbol
# address (int): Address of the symbol (its value)
# size (int): Size of the symbol in bytes
diff --git a/tools/binman/etype/fit.py b/tools/binman/etype/fit.py
index 803fb66..ed3cac4 100644
--- a/tools/binman/etype/fit.py
+++ b/tools/binman/etype/fit.py
@@ -562,8 +562,6 @@
for subnode in node.subnodes:
if (subnode.name.startswith('signature') or
subnode.name.startswith('cipher')):
- if subnode.props.get('key-name-hint') is None:
- continue
hint = subnode.props['key-name-hint'].value
name = tools.get_input_filename(
f"{hint}.key" if subnode.name.startswith('signature')
diff --git a/tools/binman/etype/section.py b/tools/binman/etype/section.py
index 5e11cf5..4c4c8c4 100644
--- a/tools/binman/etype/section.py
+++ b/tools/binman/etype/section.py
@@ -662,23 +662,6 @@
else:
raise ValueError("%s: No such property '%s'" % (msg, prop_name))
- def GetRootSkipAtStart(self):
- """Get the skip-at-start value for the top-level section
-
- This is used to find out the starting offset for root section that
- contains this section. If this is a top-level section then it returns
- the skip-at-start offset for this section.
-
- This is used to get the absolute position of section within the image.
-
- Returns:
- Integer skip-at-start value for the root section containing this
- section
- """
- if self.section:
- return self.section.GetRootSkipAtStart()
- return self._skip_at_start
-
def GetStartOffset(self):
"""Get the start offset for this section
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index 948fcc0..92df2a0 100644
--- a/tools/binman/ftest.py
+++ b/tools/binman/ftest.py
@@ -4613,6 +4613,8 @@
dtb.Scan()
props = self._GetPropTree(dtb, ['offset', 'image-pos', 'size',
'uncomp-size'])
+ data = data[:0x30]
+ data = data.rstrip(b'\xff')
orig = self._decompress(data)
self.assertEqual(COMPRESS_DATA + U_BOOT_DATA, orig)
expected = {
@@ -6218,8 +6220,9 @@
def testCompUtilPadding(self):
"""Test padding of compression algorithms"""
- # Skip zstd because it doesn't support padding
- for bintool in [v for k,v in self.comp_bintools.items() if k != 'zstd']:
+ # Skip zstd and lz4 because they doesn't support padding
+ for bintool in [v for k,v in self.comp_bintools.items()
+ if not k in ['zstd', 'lz4']]:
self._CheckBintool(bintool)
data = bintool.compress(COMPRESS_DATA)
self.assertNotEqual(COMPRESS_DATA, data)
diff --git a/tools/binman/main.py b/tools/binman/main.py
index 619840e..326f5c9 100755
--- a/tools/binman/main.py
+++ b/tools/binman/main.py
@@ -94,10 +94,16 @@
if toolpath:
for path in toolpath:
extra_args += ' --toolpath %s' % path
+
+ # Some files unfortunately don't thave the required test coverage. This will
+ # eventually be fixed, but exclude them for now
test_util.run_test_coverage('tools/binman/binman', None,
['*test*', '*main.py', 'tools/patman/*', 'tools/dtoc/*',
'tools/u_boot_pylib/*'],
- build_dir, all_set, extra_args or None, args=args)
+ build_dir, all_set, extra_args or None, args=args,
+ allow_failures=['tools/binman/btool/cst.py',
+ 'tools/binman/etype/nxp_imx8mcst.py',
+ 'tools/binman/etype/nxp_imx8mimage.py'])
def RunBinman(args):
"""Main entry point to binman once arguments are parsed
diff --git a/tools/binman/requirements.txt b/tools/binman/requirements.txt
index f068ef7..7db72e8 100644
--- a/tools/binman/requirements.txt
+++ b/tools/binman/requirements.txt
@@ -1,3 +1,4 @@
+coverage==7.8.0
importlib_resources==6.5.2
jsonschema==4.23.0
pycryptodomex==3.21.0
diff --git a/tools/binman/state.py b/tools/binman/state.py
index 6772d36..f4d885c 100644
--- a/tools/binman/state.py
+++ b/tools/binman/state.py
@@ -411,8 +411,7 @@
m = hashlib.sha256()
m.update(get_data_func())
data = m.digest()
- if data is None:
- raise ValueError(f"Node '{node.path}': Unknown hash algorithm '{algo}'")
+ assert data
for n in GetUpdateNodes(hash_node):
n.SetData('value', data)
diff --git a/tools/binman/test/184_compress_section_size.dts b/tools/binman/test/184_compress_section_size.dts
index 95ed30a..1c1dbd5 100644
--- a/tools/binman/test/184_compress_section_size.dts
+++ b/tools/binman/test/184_compress_section_size.dts
@@ -6,6 +6,7 @@
section {
size = <0x30>;
compress = "lz4";
+ pad-byte = <0xff>;
blob {
filename = "compress";
};
diff --git a/tools/buildman/buildman.rst b/tools/buildman/buildman.rst
index 924564b..07ecc5c 100644
--- a/tools/buildman/buildman.rst
+++ b/tools/buildman/buildman.rst
@@ -247,7 +247,7 @@
section is ignored. If more than one line is provided, only the last one
is taken.
-#. Make sure you have the require Python pre-requisites
+#. Make sure you have the required Python pre-requisites
Buildman uses multiprocessing, Queue, shutil, StringIO, ConfigParser and
urllib2. These should normally be available, but if you get an error like
diff --git a/tools/buildman/test.py b/tools/buildman/test.py
index c5feb74..e31e6c7 100644
--- a/tools/buildman/test.py
+++ b/tools/buildman/test.py
@@ -987,7 +987,7 @@
diff = self.call_make_environment(tchn, full_path=True)[0]
self.assertEqual({b'LC_ALL': b'C'}, diff)
- # Test that virtualenv is handled correctly
+ # Test that Python sandbox is handled correctly
tchn.override_toolchain = False
sys.prefix = '/some/venv'
env = dict(os.environb)
diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py
index 5d051e0..5e5bb4b 100644
--- a/tools/buildman/toolchain.py
+++ b/tools/buildman/toolchain.py
@@ -217,7 +217,7 @@
elif self.cross:
env[b'CROSS_COMPILE'] = tools.to_bytes(wrapper + self.cross)
- # Detect a Python virtualenv and avoid defeating it
+ # Detect a Python sandbox and avoid defeating it
if sys.prefix != sys.base_prefix:
paths = env[b'PATH'].split(b':')
new_paths = []
@@ -531,7 +531,7 @@
if arch == 'aarch64':
arch = 'arm64'
base = 'https://www.kernel.org/pub/tools/crosstool/files/bin'
- versions = ['13.2.0', '12.2.0']
+ versions = ['14.2.0', '13.2.0']
links = []
for version in versions:
url = '%s/%s/%s/' % (base, arch, version)
diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile
index e14d164..1d7d2a1 100644
--- a/tools/docker/Dockerfile
+++ b/tools/docker/Dockerfile
@@ -2,7 +2,7 @@
# This Dockerfile is used to build an image containing basic stuff to be used
# to build U-Boot and run our test suites.
-FROM ubuntu:jammy-20240911.1
+FROM ubuntu:jammy-20250404
LABEL org.opencontainers.image.authors="Tom Rini <trini@konsulko.com>"
LABEL org.opencontainers.image.description=" This image is for building U-Boot inside a container"
@@ -23,7 +23,7 @@
ENV MIRROR=https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin
# Toolchain version
-ENV TCVER=13.2.0
+ENV TCVER=14.2.0
RUN echo "Building on $BUILDPLATFORM, for target $TARGETPLATFORM"
@@ -32,7 +32,7 @@
--mount=type=cache,target=/var/lib/apt,sharing=locked \
apt-get update && apt-get install -y gnupg2 wget xz-utils
RUN wget -O - https://apt.llvm.org/llvm-snapshot.gpg.key | apt-key add -
-RUN echo deb http://apt.llvm.org/jammy/ llvm-toolchain-jammy-17 main | tee /etc/apt/sources.list.d/llvm.list
+RUN echo deb http://apt.llvm.org/jammy/ llvm-toolchain-jammy-18 main | tee /etc/apt/sources.list.d/llvm.list
# Create a list of URLs to process, then pass them into a 'while read' loop
RUN if [ "$TARGETPLATFORM" = "linux/amd64" ]; then HOSTARCH=x86_64; else HOSTARCH=arm64; fi; ( \
@@ -64,8 +64,9 @@
binutils-dev \
bison \
build-essential \
+ byacc \
cgpt \
- clang-17 \
+ clang-18 \
coreutils \
cpio \
curl \
@@ -77,6 +78,7 @@
exfatprogs \
expect \
fakeroot \
+ fdisk \
flex \
gawk \
gdisk \
@@ -88,6 +90,7 @@
help2man \
iasl \
imagemagick \
+ inetutils-telnet \
iputils-ping \
libconfuse-dev \
libgit2-dev \
@@ -122,7 +125,7 @@
python3-dev \
python3-pip \
python3-sphinx \
- python3-virtualenv \
+ python3-venv \
rpm2cpio \
sbsigntool \
socat \
@@ -134,7 +137,6 @@
texinfo \
util-linux \
uuid-dev \
- virtualenv \
vboot-kernel-utils \
vboot-utils \
xilinx-bootgen \
@@ -177,7 +179,7 @@
search search_fs_file search_fs_uuid search_label serial sleep test \
true && \
make clean && \
- ./configure --target=riscv64 --with-platform=efi \
+ grub_cv_cc_mcmodel=no ./configure --target=riscv64 --with-platform=efi \
CC=gcc \
TARGET_CC=/opt/gcc-${TCVER}-nolibc/riscv64-linux/bin/riscv64-linux-gcc \
TARGET_OBJCOPY=/opt/gcc-${TCVER}-nolibc/riscv64-linux/bin/riscv64-linux-objcopy \
@@ -230,13 +232,24 @@
# Build fiptool
RUN git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git /tmp/tf-a && \
cd /tmp/tf-a/ && \
- git checkout v2.10.0 && \
- cd tools/fiptool && \
- make -j$(nproc) && \
- mkdir -p /usr/local/bin && \
- cp fiptool /usr/local/bin && \
+ git checkout v2.12.0 && \
+ make CROSS_COMPILE=/opt/gcc-${TCVER}-nolibc/aarch64-linux/bin/aarch64-linux- \
+ PLAT=fvp BL33=/dev/null -j$(nproc) all fip && \
+ mkdir -p /usr/local/bin /opt/tf-a/vexpress_fvp && \
+ cp tools/fiptool/fiptool /usr/local/bin && \
+ cp build/fvp/release/fip.bin build/fvp/release/bl1.bin \
+ /opt/tf-a/vexpress_fvp/ && \
+ rm -rf build/fvp && \
+ make CROSS_COMPILE=/opt/gcc-${TCVER}-nolibc/aarch64-linux/bin/aarch64-linux- \
+ PLAT=fvp BL33=/dev/null TRANSFER_LIST=1 -j$(nproc) all fip && \
+ mkdir -p /opt/tf-a/vexpress_fvp_bloblist && \
+ cp build/fvp/release/fip.bin build/fvp/release/bl1.bin \
+ /opt/tf-a/vexpress_fvp_bloblist/ && \
rm -rf /tmp/tf-a
+# Download the Arm Architecture FVP platform. This file is double compressed.
+RUN wget -O - https://developer.arm.com/-/cdn-downloads/permalink/FVPs-Architecture/FM-11.28/FVP_Base_RevC-2xAEMvA_11.28_23_Linux64.tgz | gunzip -dc | tar -C /opt -x
+
# Build genimage (required by some targets to generate disk images)
RUN wget -O - https://github.com/pengutronix/genimage/releases/download/v14/genimage-14.tar.xz | tar -C /tmp -xJ && \
cd /tmp/genimage-14 && \
@@ -308,7 +321,7 @@
RUN wget -O /tmp/buildman-requirements.txt https://source.denx.de/u-boot/u-boot/-/raw/master/tools/buildman/requirements.txt
RUN wget -O /tmp/patman-requirements.txt https://source.denx.de/u-boot/u-boot/-/raw/master/tools/patman/requirements.txt
RUN wget -O /tmp/u_boot_pylib-requirements.txt https://source.denx.de/u-boot/u-boot/-/raw/master/tools/u_boot_pylib/requirements.txt
-RUN virtualenv -p /usr/bin/python3 /tmp/venv && \
+RUN python3 -m venv /tmp/venv && \
. /tmp/venv/bin/activate && \
pip install -r /tmp/pytest-requirements.txt \
-r /tmp/sphinx-requirements.txt \
diff --git a/tools/fit_check_sign.c b/tools/fit_check_sign.c
index 3d1d33f..32d0fdb 100644
--- a/tools/fit_check_sign.c
+++ b/tools/fit_check_sign.c
@@ -45,7 +45,7 @@
char *config_name = NULL;
char cmdname[256];
int ret;
- void *key_blob;
+ void *key_blob = NULL;
int c;
strncpy(cmdname, *argv, sizeof(cmdname) - 1);
@@ -70,18 +70,15 @@
fprintf(stderr, "%s: Missing fdt file\n", *argv);
usage(*argv);
}
- if (!keyfile) {
- fprintf(stderr, "%s: Missing key file\n", *argv);
- usage(*argv);
- }
ffd = mmap_fdt(cmdname, fdtfile, 0, &fit_blob, &fsbuf, false, true);
if (ffd < 0)
return EXIT_FAILURE;
- kfd = mmap_fdt(cmdname, keyfile, 0, &key_blob, &ksbuf, false, true);
- if (kfd < 0)
- return EXIT_FAILURE;
-
+ if (keyfile) {
+ kfd = mmap_fdt(cmdname, keyfile, 0, &key_blob, &ksbuf, false, true);
+ if (kfd < 0)
+ return EXIT_FAILURE;
+ }
image_set_host_blob(key_blob);
ret = fit_check_sign(fit_blob, key_blob, config_name);
if (!ret) {
@@ -93,7 +90,9 @@
}
(void) munmap((void *)fit_blob, fsbuf.st_size);
- (void) munmap((void *)key_blob, ksbuf.st_size);
+
+ if (key_blob)
+ (void)munmap((void *)key_blob, ksbuf.st_size);
close(ffd);
close(kfd);
diff --git a/tools/mkimage.c b/tools/mkimage.c
index ac62ebb..2954626 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -196,6 +196,7 @@
{ "verbose", no_argument, NULL, 'v' },
{ "version", no_argument, NULL, 'V' },
{ "xip", no_argument, NULL, 'x' },
+ { /* sentinel */ },
};
static void process_args(int argc, char **argv)
diff --git a/tools/patman/control.py b/tools/patman/control.py
index fb5a424..b8a4591 100644
--- a/tools/patman/control.py
+++ b/tools/patman/control.py
@@ -63,7 +63,8 @@
branch, start, to_do, ignore_binary, series, signoff)
# Fix up the patch files to our liking, and insert the cover letter
- patchstream.fix_patches(series, patch_files, keep_change_id)
+ patchstream.fix_patches(series, patch_files, keep_change_id,
+ insert_base_commit=not cover_fname)
if cover_fname and series.get('cover'):
patchstream.insert_cover_letter(cover_fname, series, to_do)
return series, cover_fname, patch_files
diff --git a/tools/patman/func_test.py b/tools/patman/func_test.py
index bf333dc..720746e 100644
--- a/tools/patman/func_test.py
+++ b/tools/patman/func_test.py
@@ -216,6 +216,8 @@
text = self._get_text('test01.txt')
series = patchstream.get_metadata_for_test(text)
+ series.base_commit = Commit('1a44532')
+ series.branch = 'mybranch'
cover_fname, args = self._create_patches_for_test(series)
get_maintainer_script = str(pathlib.Path(__file__).parent.parent.parent
/ 'get_maintainer.pl') + ' --norolestats'
@@ -308,6 +310,8 @@
--\x20
2.7.4
+base-commit: 1a44532
+branch: mybranch
'''
lines = open(cover_fname, encoding='utf-8').read().splitlines()
self.assertEqual(
@@ -353,6 +357,31 @@
expected = expected.splitlines()
self.assertEqual(expected, lines[start:(start+len(expected))])
+ def test_base_commit(self):
+ """Test adding a base commit with no cover letter"""
+ orig_text = self._get_text('test01.txt')
+ pos = orig_text.index('commit 5ab48490f03051875ab13d288a4bf32b507d76fd')
+ text = orig_text[:pos]
+ series = patchstream.get_metadata_for_test(text)
+ series.base_commit = Commit('1a44532')
+ series.branch = 'mybranch'
+ cover_fname, args = self._create_patches_for_test(series)
+ self.assertFalse(cover_fname)
+ with capture_sys_output() as out:
+ patchstream.fix_patches(series, args, insert_base_commit=True)
+ self.assertEqual('Cleaned 1 patch\n', out[0].getvalue())
+ lines = tools.read_file(args[0], binary=False).splitlines()
+ pos = lines.index('-- ')
+
+ # We expect these lines at the end:
+ # -- (with trailing space)
+ # 2.7.4
+ # (empty)
+ # base-commit: xxx
+ # branch: xxx
+ self.assertEqual('base-commit: 1a44532', lines[pos + 3])
+ self.assertEqual('branch: mybranch', lines[pos + 4])
+
def make_commit_with_file(self, subject, body, fname, text):
"""Create a file and add it to the git repo with a new commit
@@ -511,12 +540,23 @@
# Check that it can detect a different branch
self.assertEqual(3, gitutil.count_commits_to_branch('second'))
with capture_sys_output() as _:
- _, cover_fname, patch_files = control.prepare_patches(
+ series, cover_fname, patch_files = control.prepare_patches(
col, branch='second', count=-1, start=0, end=0,
ignore_binary=False, signoff=True)
self.assertIsNotNone(cover_fname)
self.assertEqual(3, len(patch_files))
+ cover = tools.read_file(cover_fname, binary=False)
+ lines = cover.splitlines()[-2:]
+ base = repo.lookup_reference('refs/heads/base').target
+ self.assertEqual(f'base-commit: {base}', lines[0])
+ self.assertEqual('branch: second', lines[1])
+
+ # Make sure that the base-commit is not present when it is in the
+ # cover letter
+ for fname in patch_files:
+ self.assertNotIn(b'base-commit:', tools.read_file(fname))
+
# Check that it can skip patches at the end
with capture_sys_output() as _:
_, cover_fname, patch_files = control.prepare_patches(
@@ -524,6 +564,13 @@
ignore_binary=False, signoff=True)
self.assertIsNotNone(cover_fname)
self.assertEqual(2, len(patch_files))
+
+ cover = tools.read_file(cover_fname, binary=False)
+ lines = cover.splitlines()[-2:]
+ base2 = repo.lookup_reference('refs/heads/second')
+ ref = base2.peel(pygit2.GIT_OBJ_COMMIT).parents[0].parents[0].id
+ self.assertEqual(f'base-commit: {ref}', lines[0])
+ self.assertEqual('branch: second', lines[1])
finally:
os.chdir(orig_dir)
diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py
index 490d382..7a695c3 100644
--- a/tools/patman/patchstream.py
+++ b/tools/patman/patchstream.py
@@ -76,8 +76,13 @@
are interested in. We can also process a patch file in order to remove
unwanted tags or inject additional ones. These correspond to the two
phases of processing.
+
+ Args:
+ keep_change_id (bool): Keep the Change-Id tag
+ insert_base_commit (bool): True to add the base commit to the end
"""
- def __init__(self, series, is_log=False, keep_change_id=False):
+ def __init__(self, series, is_log=False, keep_change_id=False,
+ insert_base_commit=False):
self.skip_blank = False # True to skip a single blank line
self.found_test = False # Found a TEST= line
self.lines_after_test = 0 # Number of lines found after TEST=
@@ -103,6 +108,7 @@
self.recent_quoted = collections.deque([], 5)
self.recent_unquoted = queue.Queue()
self.was_quoted = None
+ self.insert_base_commit = insert_base_commit
@staticmethod
def process_text(text, is_comment=False):
@@ -658,6 +664,13 @@
outfd.write(line + '\n')
self.blank_count = 0
self.finalise()
+ if self.insert_base_commit:
+ if self.series.base_commit:
+ print(f'base-commit: {self.series.base_commit.hash}',
+ file=outfd)
+ if self.series.branch:
+ print(f'branch: {self.series.branch}', file=outfd)
+
def insert_tags(msg, tags_to_emit):
"""Add extra tags to a commit message
@@ -755,8 +768,12 @@
Returns:
Series: Object containing information about the commits.
"""
- return get_metadata_for_list(
- '%s~%d' % (branch if branch else 'HEAD', start), None, count)
+ top = f"{branch if branch else 'HEAD'}~{start}"
+ series = get_metadata_for_list(top, None, count)
+ series.base_commit = commit.Commit(gitutil.get_hash(f'{top}~{count}'))
+ series.branch = branch or gitutil.get_branch()
+ series.top = top
+ return series
def get_metadata_for_test(text):
"""Process metadata from a file containing a git log. Used for tests
@@ -774,7 +791,8 @@
pst.finalise()
return series
-def fix_patch(backup_dir, fname, series, cmt, keep_change_id=False):
+def fix_patch(backup_dir, fname, series, cmt, keep_change_id=False,
+ insert_base_commit=False):
"""Fix up a patch file, by adding/removing as required.
We remove our tags from the patch file, insert changes lists, etc.
@@ -788,6 +806,7 @@
series (Series): Series information about this patch set
cmt (Commit): Commit object for this patch file
keep_change_id (bool): Keep the Change-Id tag.
+ insert_base_commit (bool): True to add the base commit to the end
Return:
list: A list of errors, each str, or [] if all ok.
@@ -795,7 +814,8 @@
handle, tmpname = tempfile.mkstemp()
outfd = os.fdopen(handle, 'w', encoding='utf-8')
infd = open(fname, 'r', encoding='utf-8')
- pst = PatchStream(series, keep_change_id=keep_change_id)
+ pst = PatchStream(series, keep_change_id=keep_change_id,
+ insert_base_commit=insert_base_commit)
pst.commit = cmt
pst.process_stream(infd, outfd)
infd.close()
@@ -807,7 +827,7 @@
shutil.move(tmpname, fname)
return cmt.warn
-def fix_patches(series, fnames, keep_change_id=False):
+def fix_patches(series, fnames, keep_change_id=False, insert_base_commit=False):
"""Fix up a list of patches identified by filenames
The patch files are processed in place, and overwritten.
@@ -816,6 +836,7 @@
series (Series): The Series object
fnames (:type: list of str): List of patch files to process
keep_change_id (bool): Keep the Change-Id tag.
+ insert_base_commit (bool): True to add the base commit to the end
"""
# Current workflow creates patches, so we shouldn't need a backup
backup_dir = None #tempfile.mkdtemp('clean-patch')
@@ -825,7 +846,8 @@
cmt.patch = fname
cmt.count = count
result = fix_patch(backup_dir, fname, series, cmt,
- keep_change_id=keep_change_id)
+ keep_change_id=keep_change_id,
+ insert_base_commit=insert_base_commit)
if result:
print('%d warning%s for %s:' %
(len(result), 's' if len(result) > 1 else '', fname))
@@ -868,4 +890,11 @@
out = series.MakeChangeLog(None)
line += '\n' + '\n'.join(out)
fil.write(line)
+
+ # Insert the base commit and branch
+ if series.base_commit:
+ print(f'base-commit: {series.base_commit.hash}', file=fil)
+ if series.branch:
+ print(f'branch: {series.branch}', file=fil)
+
fil.close()
diff --git a/tools/patman/series.py b/tools/patman/series.py
index d7f2f01..b73e9c5 100644
--- a/tools/patman/series.py
+++ b/tools/patman/series.py
@@ -42,6 +42,8 @@
self.notes = []
self.changes = {}
self.allow_overwrite = False
+ self.base_commit = None
+ self.branch = None
# Written in MakeCcFile()
# key: name of patch file
diff --git a/tools/qconfig.py b/tools/qconfig.py
index c96a305..5b85f9d 100755
--- a/tools/qconfig.py
+++ b/tools/qconfig.py
@@ -1175,7 +1175,7 @@
return oper + cfg
-RE_MK_CONFIGS = re.compile(r'CONFIG_(\$\(XPL_\)|\$\(PHASE_\))?([A-Za-z0-9_]*)')
+RE_MK_CONFIGS = re.compile(r'CONFIG_(\$\(PHASE_\))?([A-Za-z0-9_]*)')
RE_IFDEF = re.compile(r'(ifdef|ifndef)')
RE_C_CONFIGS = re.compile(r'CONFIG_([A-Za-z0-9_]*)')
RE_CONFIG_IS = re.compile(r'CONFIG_IS_ENABLED\(([A-Za-z0-9_]*)\)')
@@ -1220,8 +1220,6 @@
>>> RE_MK_CONFIGS.search('CONFIG_FRED').groups()
(None, 'FRED')
- >>> RE_MK_CONFIGS.search('CONFIG_$(XPL_)MARY').groups()
- ('$(XPL_)', 'MARY')
>>> RE_MK_CONFIGS.search('CONFIG_$(PHASE_)MARY').groups()
('$(PHASE_)', 'MARY')
"""
@@ -1321,8 +1319,8 @@
spl_mode (int): If MODE_SPL, look at source code which implies
an xPL_ option, but for which there is none;
for MOD_PROPER, look at source code which implies a Proper
- option (i.e. use of CONFIG_IS_ENABLED() or $(XPL_) or
- $(PHASE_) but for which there none;
+ option (i.e. use of CONFIG_IS_ENABLED() or $(PHASE_) but for
+ which there none;
if MODE_NORMAL, ignore SPL
Returns:
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 3e52236..a0caa02 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -134,7 +134,9 @@
{ "rk3399", "RK33", 0x30000 - 0x2000, false, RK_HEADER_V1 },
{ "rv1108", "RK11", 0x1800, false, RK_HEADER_V1 },
{ "rv1126", "110B", 0x10000 - 0x1000, false, RK_HEADER_V1 },
+ { "rk3528", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 },
{ "rk3568", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 },
+ { "rk3576", "RK35", 0x80000 - 0x1000, false, RK_HEADER_V2 },
{ "rk3588", "RK35", 0x100000 - 0x1000, false, RK_HEADER_V2 },
};
diff --git a/tools/u_boot_pylib/gitutil.py b/tools/u_boot_pylib/gitutil.py
index 5e3e98a..0376bec 100644
--- a/tools/u_boot_pylib/gitutil.py
+++ b/tools/u_boot_pylib/gitutil.py
@@ -701,13 +701,38 @@
.return_code == 0)
+def get_hash(spec):
+ """Get the hash of a commit
+
+ Args:
+ spec (str): Git commit to show, e.g. 'my-branch~12'
+
+ Returns:
+ str: Hash of commit
+ """
+ return command.output_one_line('git', 'show', '-s', '--pretty=format:%H',
+ spec)
+
+
def get_head():
"""Get the hash of the current HEAD
Returns:
Hash of HEAD
"""
+ return get_hash('HEAD')
+
+
+def get_branch():
+ """Get the branch we are currently on
+
+ Return:
+ str: branch name, or None if none
+ """
- return command.output_one_line('git', 'show', '-s', '--pretty=format:%H')
+ out = command.output_one_line('git', 'rev-parse', '--abbrev-ref', 'HEAD')
+ if out == 'HEAD':
+ return None
+ return out
if __name__ == "__main__":
diff --git a/tools/u_boot_pylib/test_util.py b/tools/u_boot_pylib/test_util.py
index dd67196..637403f 100644
--- a/tools/u_boot_pylib/test_util.py
+++ b/tools/u_boot_pylib/test_util.py
@@ -8,6 +8,7 @@
import glob
import multiprocessing
import os
+import re
import sys
import unittest
@@ -25,7 +26,7 @@
def run_test_coverage(prog, filter_fname, exclude_list, build_dir,
required=None, extra_args=None, single_thread='-P1',
- args=None):
+ args=None, allow_failures=None):
"""Run tests and check that we get 100% coverage
Args:
@@ -56,14 +57,14 @@
else:
glob_list = []
glob_list += exclude_list
- glob_list += ['*libfdt.py', '*site-packages*', '*dist-packages*']
+ glob_list += ['*libfdt.py', '*/site-packages/*', '*/dist-packages/*']
glob_list += ['*concurrencytest*']
test_cmd = 'test' if 'binman' in prog or 'patman' in prog else '-t'
prefix = ''
if build_dir:
prefix = 'PYTHONPATH=$PYTHONPATH:%s/sandbox_spl/tools ' % build_dir
- # Detect a Python virtualenv and use 'coverage' instead
+ # Detect a Python sandbox and use 'coverage' instead
covtool = ('python3-coverage' if sys.prefix == sys.base_prefix else
'coverage')
@@ -96,6 +97,19 @@
print('Coverage error: %s, but should be 100%%' % coverage)
ok = False
if not ok:
+ if allow_failures:
+ # for line in lines:
+ # print('.', line, re.match(r'^(tools/.*py) *\d+ *(\d+) *(\d+)%$', line))
+ lines = [re.match(r'^(tools/.*py) *\d+ *(\d+) *\d+%$', line)
+ for line in stdout.splitlines()]
+ bad = []
+ for mat in lines:
+ if mat and mat.group(2) != '0':
+ fname = mat.group(1)
+ if fname not in allow_failures:
+ bad.append(fname)
+ if not bad:
+ return
raise ValueError('Test coverage failure')