| commit | c86cb4a88ba9eb83ce7f7759a00051df5fd5741b | [log] [tgz] |
|---|---|---|
| author | Kautuk Consul <kconsul@ventanamicro.com> | Wed Dec 07 17:12:35 2022 +0530 |
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | Thu Dec 08 15:15:58 2022 +0800 |
| tree | fa08dd5ee80ff563cb71240bafd1ad0b23ff22cd | |
| parent | a51bb74979842e2a7a21ad162c009cd173a70ed4 [diff] [blame] |
arch/riscv: add semihosting support for RISC-V We add RISC-V semihosting based serial console for JTAG based early debugging. The RISC-V semihosting specification is available at: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
diff --git a/arch/riscv/include/asm/spl.h b/arch/riscv/include/asm/spl.h index e8a94fc..2898a77 100644 --- a/arch/riscv/include/asm/spl.h +++ b/arch/riscv/include/asm/spl.h
@@ -25,6 +25,7 @@ BOOT_DEVICE_DFU, BOOT_DEVICE_XIP, BOOT_DEVICE_BOOTROM, + BOOT_DEVICE_SMH, BOOT_DEVICE_NONE };