Cleanup
diff --git a/board/integratorcp/integratorcp.c b/board/integratorcp/integratorcp.c
index db833f0..216876b 100644
--- a/board/integratorcp/integratorcp.c
+++ b/board/integratorcp/integratorcp.c
@@ -24,7 +24,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -108,33 +108,33 @@
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
#ifdef CONFIG_CM_SPD_DETECT
- {
+ {
extern void dram_query(void);
unsigned long cm_reg_sdram;
unsigned long sdram_shift;
dram_query(); /* Assembler accesses to CM registers */
- /* Queries the SPD values */
+ /* Queries the SPD values */
/* Obtain the SDRAM size from the CM SDRAM register */
cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM);
- /* Register SDRAM size
- *
- * 0xXXXXXXbbb000bb 16 MB
- * 0xXXXXXXbbb001bb 32 MB
- * 0xXXXXXXbbb010bb 64 MB
- * 0xXXXXXXbbb011bb 128 MB
- * 0xXXXXXXbbb100bb 256 MB
- *
+ /* Register SDRAM size
+ *
+ * 0xXXXXXXbbb000bb 16 MB
+ * 0xXXXXXXbbb001bb 32 MB
+ * 0xXXXXXXbbb010bb 64 MB
+ * 0xXXXXXXbbb011bb 128 MB
+ * 0xXXXXXXbbb100bb 256 MB
+ *
*/
- sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
- gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift;
+ sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
+ gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift;
- }
+ }
#endif /* CM_SPD_DETECT */
return 0;
@@ -147,13 +147,13 @@
/* U-Boot expects a 32 bit timer, running at CFG_HZ */
/* Keep total timer count to avoid losing decrements < div_timer */
static unsigned long long total_count = 0;
-static unsigned long long lastdec; /* Timer reading at last call */
+static unsigned long long lastdec; /* Timer reading at last call */
static unsigned long long div_clock = 1; /* Divisor applied to timer clock */
static unsigned long long div_timer = 1; /* Divisor to convert timer reading
* change to U-Boot ticks
*/
/* CFG_HZ = CFG_HZ_CLOCK/(div_clock * div_timer) */
-static ulong timestamp; /* U-Boot ticks since startup */
+static ulong timestamp; /* U-Boot ticks since startup */
#define TIMER_LOAD_VAL ((ulong)0xFFFFFFFF)
#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+4))
@@ -169,13 +169,13 @@
/* Load timer with initial value */
*(volatile ulong *)(CFG_TIMERBASE + 0) = TIMER_LOAD_VAL;
/* Set timer to be
- * enabled 1
- * periodic 1
- * no interrupts 0
- * X 0
- * divider 1 00 == less rounding error
- * 32 bit 1
- * wrapping 0
+ * enabled 1
+ * periodic 1
+ * no interrupts 0
+ * X 0
+ * divider 1 00 == less rounding error
+ * 32 bit 1
+ * wrapping 0
*/
*(volatile ulong *)(CFG_TIMERBASE + 8) = 0x000000C2;
/* init the timestamp */
@@ -219,8 +219,7 @@
tmp = get_timer_masked(); /* get current timestamp */
tmo += tmp; /* form target timestamp */
- while (get_timer_masked () < tmo)/* loop till event */
- {
+ while (get_timer_masked () < tmo) {/* loop till event */
/*NOP*/;
}
}
@@ -228,26 +227,25 @@
void reset_timer_masked (void)
{
/* capure current decrementer value */
- lastdec = (unsigned long long)READ_TIMER;
+ lastdec = (unsigned long long)READ_TIMER;
/* start "advancing" time stamp from 0 */
- timestamp = 0L;
+ timestamp = 0L;
}
-/* converts the timer reading to U-Boot ticks */
+/* converts the timer reading to U-Boot ticks */
/* the timestamp is the number of ticks since reset */
ulong get_timer_masked (void)
{
/* get current count */
unsigned long long now = (unsigned long long)READ_TIMER;
- if(now > lastdec)
- {
+ if(now > lastdec) {
/* Must have wrapped */
- total_count += lastdec + TIMER_LOAD_VAL + 1 - now;
+ total_count += lastdec + TIMER_LOAD_VAL + 1 - now;
} else {
total_count += lastdec - now;
}
- lastdec = now;
+ lastdec = now;
timestamp = (ulong)(total_count/div_timer);
return timestamp;
diff --git a/board/integratorcp/memsetup.S b/board/integratorcp/memsetup.S
index bdf6af9..dfdc784 100644
--- a/board/integratorcp/memsetup.S
+++ b/board/integratorcp/memsetup.S
@@ -1,5 +1,5 @@
/*
- * Memory setup for integratorAP
+ * Memory setup for integratorAP
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -27,4 +27,3 @@
.globl memsetup
memsetup:
mov pc,lr
-
diff --git a/board/integratorcp/platform.S b/board/integratorcp/platform.S
index 73d6922..9bda771 100644
--- a/board/integratorcp/platform.S
+++ b/board/integratorcp/platform.S
@@ -14,7 +14,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -52,8 +52,8 @@
#ifdef CONFIG_CM_INIT
/* CM has an initialization register
* - bits in it are wired into test-chip pins to force
- * reset defaults
- * - may need to change its contents for U-Boot
+ * reset defaults
+ * - may need to change its contents for U-Boot
*/
/* set the desired CM specific value */
@@ -65,39 +65,39 @@
#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
!defined (CONFIG_CM940T)
-
-#ifdef CONFIG_CM_MULTIPLE_SSRAM
- /* set simple mapping */
+
+#ifdef CONFIG_CM_MULTIPLE_SSRAM
+ /* set simple mapping */
and r2,r2,#CMMASK_MAP_SIMPLE
#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */
-#ifdef CONFIG_CM_TCRAM
- /* disable TCRAM */
+#ifdef CONFIG_CM_TCRAM
+ /* disable TCRAM */
and r2,r2,#CMMASK_TCRAM_DISABLE
-#endif /* #ifdef CONFIG_CM_TCRAM */
+#endif /* #ifdef CONFIG_CM_TCRAM */
#if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \
defined (CONFIG_CM1136JF_S)
and r2,r2,#CMMASK_LE
-
+
#endif /* cpu with little endian initialization */
orr r2,r2,#CMMASK_CMxx6_COMMON
#endif /* CMxx6 code */
-
+
#endif /* ARM102xxE value */
-
- /* read CM_INIT */
+
+ /* read CM_INIT */
mov r0, #CM_BASE
ldr r1, [r0, #OS_INIT]
/* check against desired bit setting */
and r3,r1,r2
cmp r3,r2
beq init_reg_OK
-
- /* lock for change */
+
+ /* lock for change */
mov r3, #CMVAL_LOCK
and r3,r3,#CMMASK_LOCK
str r3, [r0, #OS_LOCK]
@@ -112,39 +112,39 @@
b reset_cpu
init_reg_OK:
-
-#endif /* CONFIG_CM_INIT */
+
+#endif /* CONFIG_CM_INIT */
mov pc, lr
-#ifdef CONFIG_CM_SPD_DETECT
+#ifdef CONFIG_CM_SPD_DETECT
/* Fast memory is available for the DRAM data
- * - ensure it has been transferred, then summarize the data
+ * - ensure it has been transferred, then summarize the data
* into a CM register
*/
.globl dram_query
dram_query:
stmfd r13!,{r4-r6,lr}
- /* set up SDRAM info */
+ /* set up SDRAM info */
/* - based on example code from the CM User Guide */
mov r0, #CM_BASE
-
+
readspdbit:
- ldr r1, [r0, #OS_SDRAM] /* read the SDRAM register */
- and r1, r1, #0x20 /* mask SPD bit (5) */
- cmp r1, #0x20 /* test if set */
+ ldr r1, [r0, #OS_SDRAM] /* read the SDRAM register */
+ and r1, r1, #0x20 /* mask SPD bit (5) */
+ cmp r1, #0x20 /* test if set */
bne readspdbit
setupsdram:
add r0, r0, #OS_SPD /* address the copy of the SDP data */
- ldrb r1, [r0, #3] /* number of row address lines */
+ ldrb r1, [r0, #3] /* number of row address lines */
ldrb r2, [r0, #4] /* number of column address lines */
- ldrb r3, [r0, #5] /* number of banks */
- ldrb r4, [r0, #31] /* module bank density */
+ ldrb r3, [r0, #5] /* number of banks */
+ ldrb r4, [r0, #31] /* module bank density */
mul r5, r4, r3 /* size of SDRAM (MB divided by 4) */
- mov r5, r5, ASL#2 /* size in MB */
- mov r0, #CM_BASE /* reload for later code */
- cmp r5, #0x10 /* is it 16MB? */
+ mov r5, r5, ASL#2 /* size in MB */
+ mov r0, #CM_BASE /* reload for later code */
+ cmp r5, #0x10 /* is it 16MB? */
bne not16
mov r6, #0x2 /* store size and CAS latency of 2 */
b writesize
@@ -175,21 +175,21 @@
writesize:
mov r1, r1, ASL#8 /* row addr lines from SDRAM reg */
- orr r2, r1, r2, ASL#12 /* OR in column address lines */
- orr r3, r2, r3, ASL#16 /* OR in number of banks */
- orr r6, r6, r3 /* OR in size and CAS latency */
- str r6, [r0, #OS_SDRAM] /* store SDRAM parameters */
+ orr r2, r1, r2, ASL#12 /* OR in column address lines */
+ orr r3, r2, r3, ASL#16 /* OR in number of banks */
+ orr r6, r6, r3 /* OR in size and CAS latency */
+ str r6, [r0, #OS_SDRAM] /* store SDRAM parameters */
#endif /* #ifdef CONFIG_CM_SPD_DETECT */
ldmfd r13!,{r4-r6,pc} /* back to caller */
-#ifdef CONFIG_CM_REMAP
- /* CM remap bit is operational
+#ifdef CONFIG_CM_REMAP
+ /* CM remap bit is operational
* - use it to map writeable memory at 0x00000000, in place of flash
*/
.globl cm_remap
-cm_remap:
+cm_remap:
stmfd r13!,{r4-r10,lr}
mov r0, #CM_BASE
@@ -198,9 +198,9 @@
str r1, [r0, #OS_CTRL]
/* Now 0x00000000 is writeable, replace the vectors */
- ldr r0, =_start /* r0 <- start of vectors */
- ldr r2, =_armboot_start /* r2 <- past vectors */
- sub r1,r1,r1 /* destination 0x00000000 */
+ ldr r0, =_start /* r0 <- start of vectors */
+ ldr r2, =_armboot_start /* r2 <- past vectors */
+ sub r1,r1,r1 /* destination 0x00000000 */
copy_vec:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
@@ -208,7 +208,6 @@
cmp r0, r2 /* until source end address [r2] */
ble copy_vec
- ldmfd r13!,{r4-r10,pc} /* back to caller */
+ ldmfd r13!,{r4-r10,pc} /* back to caller */
#endif /* #ifdef CONFIG_CM_REMAP */
-