Migrate esd 405EP boards to new NAND subsystem
Migrate esd 405EP boards to new NAND subsystem
-cleanup
-use correct io accessors (in/out_be32())
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
diff --git a/include/configs/HH405.h b/include/configs/HH405.h
index dc40ebc..f36777a 100644
--- a/include/configs/HH405.h
+++ b/include/configs/HH405.h
@@ -130,8 +130,6 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
-#define CFG_NAND_LEGACY
-
#undef CONFIG_BZIP2 /* include support for bzip2 compressed images */
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -198,34 +196,15 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US 25
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */