Merge patch series "fs: ext4: implement opendir, readdir, closedir"
Heinrich Schuchardt <heinrich.schuchardt@canonical.com> says:
With this series opendir, readdir, closedir are implemented for ext4.
These functions are needed for the UEFI sub-system to interact with
the ext4 file system.
To reduce code growth the functions are reused to implement the ls
command for ext4.
A memory leak in ext4fs_exists is resolved.
ext4fs_iterate_dir is simplified by removing a redundant pointer copy.
Link: https://lore.kernel.org/r/20241026064048.370062-1-heinrich.schuchardt@canonical.com
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index 3ff1b44..4ecf76e 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -255,6 +255,11 @@
wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
fi
+ if [[ "\${TEST_PY_BD}" == "qemu-arm-sbsa" ]]; then
+ wget -O /tmp/bl1.bin https://artifacts.codelinaro.org/artifactory/linaro-419-sbsa-ref/latest/tf-a/bl1.bin;
+ wget -O /tmp/fip.bin https://artifacts.codelinaro.org/artifactory/linaro-419-sbsa-ref/latest/tf-a/fip.bin;
+ export BINMAN_INDIRS=/tmp
+ fi
# the below corresponds to .gitlab-ci.yml "script"
cd \${WORK_DIR}
export UBOOT_TRAVIS_BUILD_DIR=/tmp/\${TEST_PY_BD}
@@ -426,6 +431,9 @@
qemu_arm64_lwip:
TEST_PY_BD: "qemu_arm64_lwip"
TEST_PY_TEST_SPEC: "test_net_dhcp or test_net_ping or test_net_tftpboot"
+ qemu_arm_sbsa_ref:
+ TEST_PY_BD: "qemu-arm-sbsa"
+ TEST_PY_TEST_SPEC: "not sleep"
qemu_m68k:
TEST_PY_BD: "M5208EVBE"
TEST_PY_ID: "--id qemu"
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index d89657e..0aeda53 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -42,6 +42,11 @@
wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
fi
+ - if [[ "${TEST_PY_BD}" == "qemu-arm-sbsa" ]]; then
+ wget -O /tmp/bl1.bin https://artifacts.codelinaro.org/artifactory/linaro-419-sbsa-ref/latest/tf-a/bl1.bin;
+ wget -O /tmp/fip.bin https://artifacts.codelinaro.org/artifactory/linaro-419-sbsa-ref/latest/tf-a/fip.bin;
+ export BINMAN_INDIRS=/tmp;
+ fi
after_script:
- cp -v /tmp/${TEST_PY_BD}/*.{html,css,xml} .
@@ -357,6 +362,12 @@
TEST_PY_TEST_SPEC: "test_net_dhcp or test_net_ping or test_net_tftpboot"
<<: *buildman_and_testpy_dfn
+qemu_arm_sbsa test.py:
+ variables:
+ TEST_PY_BD: "qemu-arm-sbsa"
+ TEST_PY_TEST_SPEC: "not sleep"
+ <<: *buildman_and_testpy_dfn
+
qemu_m68k test.py:
variables:
TEST_PY_BD: "M5208EVBE"
diff --git a/Kconfig b/Kconfig
index a7b2b6d..eb55f25 100644
--- a/Kconfig
+++ b/Kconfig
@@ -599,7 +599,6 @@
bool
default y if TARGET_PIC32MZDASK
default y if TARGET_DEVKIT8000
- default y if TARGET_TRICORDER
help
Enable this to allow support for the on board SRAM.
SRAM base address is controlled by CONFIG_SYS_SRAM_BASE.
@@ -609,14 +608,12 @@
hex
default 0x80000000 if TARGET_PIC32MZDASK
default 0x40200000 if TARGET_DEVKIT8000
- default 0x40200000 if TARGET_TRICORDER
default 0x0
config SYS_SRAM_SIZE
hex
default 0x00080000 if TARGET_PIC32MZDASK
default 0x10000 if TARGET_DEVKIT8000
- default 0x10000 if TARGET_TRICORDER
default 0x0
config SYS_MONITOR_LEN
diff --git a/MAINTAINERS b/MAINTAINERS
index 8e375e7..df04619 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -355,7 +355,7 @@
T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git
F: arch/arm/mach-kirkwood/
F: arch/arm/mach-mvebu/
-F: drivers/ata/ahci_mvebu.c
+F: drivers/ata/ahci_generic.c
F: drivers/clk/mvebu/
F: drivers/ddr/marvell/
F: drivers/gpio/mvebu_gpio.c
@@ -1604,6 +1604,7 @@
SPI-NOR
M: Jagan Teki <jagan@amarulasolutions.com>
M: Vignesh R <vigneshr@ti.com>
+R: Tudor Ambarus <tudor.ambarus@linaro.org>
S: Maintained
F: drivers/mtd/spi/
F: include/spi_flash.h
diff --git a/Makefile b/Makefile
index 6b9c00b..7275a02 100644
--- a/Makefile
+++ b/Makefile
@@ -1,9 +1,9 @@
# SPDX-License-Identifier: GPL-2.0+
-VERSION = 2024
-PATCHLEVEL = 10
+VERSION = 2025
+PATCHLEVEL = 01
SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
NAME =
# *DOCUMENTATION*
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 060636e..787f983 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -113,6 +113,13 @@
config GICV3
bool
+config DRIVER_GICV2
+ bool "ARM GICV2 driver"
+ select IRQ
+ help
+ ARM GICV2 driver.
+ Basic support for parsing the GICV2 node and generate ACPI tables.
+
config GIC_V3_ITS
bool "ARM GICV3 ITS"
select IRQ
@@ -644,6 +651,7 @@
config ARCH_BCM283X
bool "Broadcom BCM283X family"
+ select CPU
select DM
select DM_GPIO
select DM_SERIAL
@@ -1047,7 +1055,7 @@
imply DM_RNG
imply DM_RTC
imply RTC_PL031
- imply OF_HAS_PRIOR_STAGE
+ imply OF_HAS_PRIOR_STAGE if !TARGET_QEMU_ARM_SBSA
imply VIDEO
imply VIDEO_BOCHS
imply SYS_WHITE_ON_BLACK
@@ -2374,6 +2382,7 @@
source "board/cavium/thunderx/Kconfig"
source "board/eets/pdu001/Kconfig"
source "board/emulation/qemu-arm/Kconfig"
+source "board/emulation/qemu-sbsa/Kconfig"
source "board/freescale/ls2080aqds/Kconfig"
source "board/freescale/ls2080ardb/Kconfig"
source "board/freescale/ls1088a/Kconfig"
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index 8747d2e..2e71ff2 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -29,6 +29,7 @@
ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_ARMV8_SPIN_TABLE) += spin_table.o spin_table_v8.o
+obj-$(CONFIG_ACPI_PARKING_PROTOCOL) += acpi_park_v8.o
else
obj-$(CONFIG_ARCH_SUNXI) += fel_utils.o
endif
diff --git a/arch/arm/cpu/armv8/acpi_park_v8.S b/arch/arm/cpu/armv8/acpi_park_v8.S
new file mode 100644
index 0000000..0bc605d
--- /dev/null
+++ b/arch/arm/cpu/armv8/acpi_park_v8.S
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2024 9elements GmbH
+ * Author: Patrick Rudolph <patrick.rudolph@9elements.com>
+ *
+ * This file provides ARMv8 specific code for the generic part of the
+ * ACPI parking protocol implementation. It contains the spinning code
+ * that will be installed into the parking protocol and it points the
+ * secondary CPUs to their own parking protocol page once it has been
+ * set up by the generic part.
+ */
+
+#include <asm/acpi_table.h>
+#include <linux/linkage.h>
+
+/* Filled by C code */
+.global acpi_pp_tables
+acpi_pp_tables:
+ .quad 0
+
+.global acpi_pp_etables
+acpi_pp_etables:
+ .quad 0
+
+/* Read by C code */
+.global acpi_pp_code_size
+acpi_pp_code_size:
+ .word __secondary_pp_code_end - __secondary_pp_code_start
+
+.global acpi_pp_secondary_jump
+ENTRY(acpi_pp_secondary_jump)
+0:
+ /*
+ * Cannot use atomic operations since the MMU and D-cache
+ * might be off. Use the MPIDR instead to find the spintable.
+ */
+
+ /* Check if parking protocol table is ready */
+ ldr x1, =acpi_pp_tables
+ ldr x0, [x1]
+ cbnz x0, 0f
+ wfe
+ b 0b
+
+0: /* Get end of page tables in x3 */
+ ldr x1, =acpi_pp_etables
+ ldr x3, [x1]
+
+ /* Get own CPU ID in w2 */
+ mrs x2, mpidr_el1
+ lsr x9, x2, #32
+ bfi x2, x9, #24, #8 /* w2 is aff3:aff2:aff1:aff0 */
+
+0: /* Loop over all parking protocol pages */
+ cmp x0, x3
+ b.ge hlt
+
+ /* Fetch CPU_ID from current page */
+ ldr x1, [x0, #ACPI_PP_CPU_ID_OFFSET]
+ lsr x9, x1, #32
+ bfi x1, x9, #24, #8 /* w1 is aff3:aff2:aff1:aff0 */
+
+ /* Compare CPU_IDs */
+ cmp w1, w2
+ b.eq 0f
+
+ add x0, x0, #ACPI_PP_PAGE_SIZE
+ b 0b
+
+hlt: wfi
+ b hlt /* Should never happen. */
+
+0: /* x0 points to the 4K-aligned, parking protocol page */
+ add x2, x0, #ACPI_PP_CPU_CODE_OFFSET
+
+ /* Jump to spin code in own parking protocol page */
+ br x2
+ENDPROC(acpi_pp_secondary_jump)
+
+.align 8
+__secondary_pp_code_start:
+.global acpi_pp_code_start
+ENTRY(acpi_pp_code_start)
+ /* x0 points to the 4K-aligned, parking protocol page */
+
+ /* Prepare defines for spinning code */
+ mov w3, #ACPI_PP_CPU_ID_INVALID
+ mov x2, #ACPI_PP_JMP_ADR_INVALID
+
+ /* Mark parking protocol page as ready */
+ str w3, [x0, #ACPI_PP_CPU_ID_OFFSET]
+ dsb sy
+
+0: wfe
+ ldr w1, [x0, #ACPI_PP_CPU_ID_OFFSET]
+
+ /* Check CPU ID is valid */
+ cmp w1, w3
+ b.eq 0b
+
+ /* Check jump address valid */
+ ldr x1, [x0, #ACPI_PP_CPU_JMP_OFFSET]
+ cmp x1, x2
+ b.eq 0b
+
+ /* Clear jump address before jump */
+ str x2, [x0, #ACPI_PP_CPU_JMP_OFFSET]
+ dsb sy
+
+ br x1
+ENDPROC(acpi_pp_code_start)
+ /* Secondary Boot Code ends here */
+__secondary_pp_code_end:
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 4a3b9f6..d3a8a7c 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -178,6 +178,18 @@
branch_if_master x0, master_cpu
b spin_table_secondary_jump
/* never return */
+#elif defined(CONFIG_ACPI_PARKING_PROTOCOL) && !defined(CONFIG_SPL_BUILD)
+ branch_if_master x0, master_cpu
+ /*
+ * Waits for ACPI parking protocol memory to be allocated and the spin-table
+ * code to be written. Once ready the secondary CPUs will jump and spin in
+ * their own 4KiB memory region, which is also used as mailbox, until released
+ * by the OS.
+ * The mechanism is similar to the DT enable-method = "spin-table", but works
+ * with ACPI enabled platforms.
+ */
+ b acpi_pp_secondary_jump
+ /* never return */
#elif defined(CONFIG_ARMV8_MULTIENTRY)
branch_if_master x0, master_cpu
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 03ed3cb..aeccfa9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1165,14 +1165,6 @@
dtb-$(CONFIG_SOC_K3_AM654) += \
k3-am654-base-board.dtb \
k3-am654-r5-base-board.dtb \
- k3-am65-iot2050-spl.dtb \
- k3-am6528-iot2050-basic.dtb \
- k3-am6528-iot2050-basic-pg2.dtb \
- k3-am6548-iot2050-advanced.dtb \
- k3-am6548-iot2050-advanced-pg2.dtb \
- k3-am6548-iot2050-advanced-m2.dtb \
- k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtbo \
- k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtbo \
k3-am654-icssg2.dtbo
dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-r5-common-proc-board.dtb \
diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts
index d481ead..9a5037d 100644
--- a/arch/arm/dts/ast2500-evb.dts
+++ b/arch/arm/dts/ast2500-evb.dts
@@ -129,3 +129,8 @@
reg = <0x4d>;
};
};
+
+&sgpio {
+ status = "okay";
+ ngpios = <80>;
+};
diff --git a/arch/arm/dts/ast2500.dtsi b/arch/arm/dts/ast2500.dtsi
index 320d2e5..d677705 100644
--- a/arch/arm/dts/ast2500.dtsi
+++ b/arch/arm/dts/ast2500.dtsi
@@ -255,6 +255,21 @@
interrupt-controller;
};
+ sgpio: sgpio@1e780200 {
+ compatible = "aspeed,ast2500-sgpio";
+ reg = <0x1e780200 0x100>;
+ interrupts = <40>;
+ clocks = <&scu ASPEED_CLK_APB>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ bus-frequency = <1000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sgpm_default>;
+ status = "disabled";
+ };
+
timer: timer@1e782000 {
/* This timer is a Faraday FTTMR010 derivative */
compatible = "aspeed,ast2400-timer";
@@ -1445,4 +1460,9 @@
function = "WDTRST2";
groups = "WDTRST2";
};
+
+ pinctrl_sgpm_default: sgpm_default {
+ function = "SGPM";
+ groups = "SGPM";
+ };
};
diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts
index 9aac0e2..570ba61 100644
--- a/arch/arm/dts/ast2600-evb.dts
+++ b/arch/arm/dts/ast2600-evb.dts
@@ -266,3 +266,13 @@
bootph-all;
status = "okay";
};
+
+&sgpiom0 {
+ status = "okay";
+ ngpios = <128>;
+};
+
+&sgpiom1 {
+ status = "okay";
+ ngpios = <80>;
+};
diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi
index 43db80e..cb8ce8b 100644
--- a/arch/arm/dts/ast2600.dtsi
+++ b/arch/arm/dts/ast2600.dtsi
@@ -501,6 +501,36 @@
ngpios = <208>;
};
+ sgpiom0: sgpiom@1e780500 {
+ compatible = "aspeed,ast2600-sgpiom";
+ reg = <0x1e780500 0x100>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scu ASPEED_CLK_APB2>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ bus-frequency = <1000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sgpm1_default>;
+ status = "disabled";
+ };
+
+ sgpiom1: sgpiom@1e780600 {
+ compatible = "aspeed,ast2600-sgpiom";
+ reg = <0x1e780600 0x100>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scu ASPEED_CLK_APB2>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ bus-frequency = <12000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sgpm2_default>;
+ status = "disabled";
+ };
+
gpio1: gpio@1e780800 {
compatible = "aspeed,ast2600-gpio";
reg = <0x1e780800 0x800>;
@@ -2167,4 +2197,14 @@
function = "PCIE1RC";
groups = "PCIE1RC";
};
+
+ pinctrl_sgpm1_default: sgpm1_default {
+ function = "SGPM1";
+ groups = "SGPM1";
+ };
+
+ pinctrl_sgpm2_default: sgpm2_default {
+ function = "SGPM2";
+ groups = "SGPM2";
+ };
};
diff --git a/arch/arm/dts/imx8mp-navqp-u-boot.dtsi b/arch/arm/dts/imx8mp-navqp-u-boot.dtsi
new file mode 100644
index 0000000..fe41d81
--- /dev/null
+++ b/arch/arm/dts/imx8mp-navqp-u-boot.dtsi
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019, 2021 NXP
+ * Copyright 2024 Gilles Talis <gilles.talis@gmail.com>
+ */
+
+#include "imx8mp-u-boot.dtsi"
+
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ bootph-pre-ram;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
+ bootph-all;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
+ bootph-all;
+};
+
+&gpio1 {
+ bootph-pre-ram;
+};
+
+&gpio2 {
+ bootph-pre-ram;
+};
+
+&gpio3 {
+ bootph-pre-ram;
+};
+
+&gpio4 {
+ bootph-pre-ram;
+};
+
+&gpio5 {
+ bootph-pre-ram;
+};
+
+&i2c1 {
+ bootph-all;
+};
+
+&pinctrl_i2c1 {
+ bootph-pre-ram;
+};
+
+&pinctrl_pmic {
+ bootph-pre-ram;
+};
+
+&pinctrl_uart2 {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_gpio {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc2 {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc3 {
+ bootph-pre-ram;
+};
+
+&pinctrl_wdog {
+ bootph-pre-ram;
+};
+
+®_usdhc2_vmmc {
+ u-boot,off-on-delay-us = <20000>;
+};
+
+®_usdhc2_vmmc {
+ bootph-pre-ram;
+};
+
+&uart2 {
+ bootph-pre-ram;
+};
+
+&usdhc1 {
+ bootph-pre-ram;
+};
+
+&usdhc2 {
+ bootph-pre-ram;
+};
+
+&usdhc3 {
+ bootph-pre-ram;
+};
+
+&wdog1 {
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi
index 3a6db91..f49d6f2 100644
--- a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi
+++ b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi
@@ -84,12 +84,12 @@
};
fdt-0 {
- description = "k3-am65-iot2050-spl.dtb";
+ description = "ti/k3-am6528-iot2050-basic.dtb";
type = "flat_dt";
arch = "arm";
compression = "none";
blob-ext {
- filename = "spl/dts/k3-am65-iot2050-spl.dtb";
+ filename = "spl/dts/ti/k3-am6528-iot2050-basic.dtb";
};
};
};
@@ -205,10 +205,10 @@
};
fit@380000 {
- fit,fdt-list-val = "k3-am6528-iot2050-basic", "k3-am6548-iot2050-advanced";
+ fit,fdt-list-val = "ti/k3-am6528-iot2050-basic", "ti/k3-am6548-iot2050-advanced";
configurations {
- default = "k3-am6528-iot2050-basic";
+ default = "ti/k3-am6528-iot2050-basic";
@config-SEQ {
loadables =
#ifdef CONFIG_WDT_K3_RTI_FW_FILE
@@ -229,7 +229,10 @@
};
fit@380000 {
- fit,fdt-list-val = "k3-am6528-iot2050-basic-pg2", "k3-am6548-iot2050-advanced-pg2", "k3-am6548-iot2050-advanced-m2";
+ fit,fdt-list-val = "ti/k3-am6528-iot2050-basic-pg2",
+ "ti/k3-am6548-iot2050-advanced-pg2",
+ "ti/k3-am6548-iot2050-advanced-m2",
+ "ti/k3-am6548-iot2050-advanced-sm";
images {
bkey-usb3-overlay {
@@ -239,7 +242,7 @@
arch = "arm64";
compression = "none";
blob-ext {
- filename = "k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtbo";
+ filename = "ti/k3-am6548-iot2050-advanced-m2-bkey-usb3.dtbo";
};
hash {
algo = "sha256";
@@ -253,7 +256,7 @@
arch = "arm64";
compression = "none";
blob-ext {
- filename = "k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtbo";
+ filename = "ti/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie.dtbo";
};
hash {
algo = "sha256";
@@ -262,7 +265,7 @@
};
configurations {
- default = "k3-am6528-iot2050-basic-pg2";
+ default = "ti/k3-am6528-iot2050-basic-pg2";
@config-SEQ {
loadables =
#ifdef CONFIG_WDT_K3_RTI_FW_FILE
diff --git a/arch/arm/dts/k3-am65-iot2050-common-pg1.dtsi b/arch/arm/dts/k3-am65-iot2050-common-pg1.dtsi
deleted file mode 100644
index 51f902f..0000000
--- a/arch/arm/dts/k3-am65-iot2050-common-pg1.dtsi
+++ /dev/null
@@ -1,46 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) Siemens AG, 2021
- *
- * Authors:
- * Jan Kiszka <jan.kiszka@siemens.com>
- *
- * Common bits of the IOT2050 Basic and Advanced variants, PG1
- */
-
-&dss {
- assigned-clocks = <&k3_clks 67 2>;
- assigned-clock-parents = <&k3_clks 67 5>;
-};
-
-&serdes0 {
- status = "disabled";
-};
-
-&sdhci1 {
- no-1-8-v;
-};
-
-&tx_pru0_0 {
- status = "disabled";
-};
-
-&tx_pru0_1 {
- status = "disabled";
-};
-
-&tx_pru1_0 {
- status = "disabled";
-};
-
-&tx_pru1_1 {
- status = "disabled";
-};
-
-&tx_pru2_0 {
- status = "disabled";
-};
-
-&tx_pru2_1 {
- status = "disabled";
-};
diff --git a/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi b/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi
deleted file mode 100644
index e9419c4..0000000
--- a/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi
+++ /dev/null
@@ -1,51 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) Siemens AG, 2021
- *
- * Authors:
- * Chao Zeng <chao.zeng@siemens.com>
- * Jan Kiszka <jan.kiszka@siemens.com>
- *
- * Common bits of the IOT2050 Basic and Advanced variants, PG2
- */
-
-&main_pmx0 {
- cp2102n_reset_pin_default: cp2102n-reset-default-pins {
- pinctrl-single,pins = <
- /* (AF12) GPIO1_24, used as cp2102 reset */
- AM65X_IOPAD(0x01e0, PIN_OUTPUT, 7)
- >;
- };
-};
-
-&main_gpio1 {
- pinctrl-names = "default";
- pinctrl-0 = <&cp2102n_reset_pin_default>;
- gpio-line-names =
- "", "", "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "", "", "",
- "", "", "", "", "CP2102N-RESET";
-};
-
-&dss {
- /* Workaround needed to get DP clock of 154Mhz */
- assigned-clocks = <&k3_clks 67 0>;
-};
-
-&serdes0 {
- assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
- assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;
-};
-
-&dwc3_0 {
- assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
- <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */
- phys = <&serdes0 PHY_TYPE_USB3 0>;
- phy-names = "usb3-phy";
-};
-
-&usb0 {
- maximum-speed = "super-speed";
- snps,dis-u1-entry-quirk;
- snps,dis-u2-entry-quirk;
-};
diff --git a/arch/arm/dts/k3-am65-iot2050-common.dtsi b/arch/arm/dts/k3-am65-iot2050-common.dtsi
deleted file mode 100644
index fa71781..0000000
--- a/arch/arm/dts/k3-am65-iot2050-common.dtsi
+++ /dev/null
@@ -1,738 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) Siemens AG, 2018-2021
- *
- * Authors:
- * Le Jin <le.jin@siemens.com>
- * Jan Kiszka <jan.kiszka@siemens.com>
- *
- * Common bits of the IOT2050 Basic and Advanced variants, PG1 and PG2
- */
-
-#include "k3-am654.dtsi"
-#include <dt-bindings/phy/phy.h>
-
-/ {
- aliases {
- serial0 = &wkup_uart0;
- serial1 = &mcu_uart0;
- serial2 = &main_uart0;
- serial3 = &main_uart1;
- i2c0 = &wkup_i2c0;
- i2c1 = &mcu_i2c0;
- i2c2 = &main_i2c0;
- i2c3 = &main_i2c1;
- i2c4 = &main_i2c2;
- i2c5 = &main_i2c3;
- spi0 = &mcu_spi0;
- mmc0 = &sdhci1;
- mmc1 = &sdhci0;
- };
-
- chosen {
- stdout-path = "serial3:115200n8";
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- secure_ddr: secure-ddr@9e800000 {
- reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
- alignment = <0x1000>;
- no-map;
- };
-
- mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
- compatible = "shared-dma-pool";
- reg = <0 0xa0000000 0 0x100000>;
- no-map;
- };
-
- mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
- compatible = "shared-dma-pool";
- reg = <0 0xa0100000 0 0xf00000>;
- no-map;
- };
-
- mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
- compatible = "shared-dma-pool";
- reg = <0 0xa1000000 0 0x100000>;
- no-map;
- };
-
- mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
- compatible = "shared-dma-pool";
- reg = <0 0xa1100000 0 0xf00000>;
- no-map;
- };
-
- rtos_ipc_memory_region: ipc-memories@a2000000 {
- reg = <0x00 0xa2000000 0x00 0x00200000>;
- alignment = <0x1000>;
- no-map;
- };
-
- /* To reserve the power-on(PON) reason for watchdog reset */
- wdt_reset_memory_region: wdt-memory@a2200000 {
- reg = <0x00 0xa2200000 0x00 0x00001000>;
- no-map;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&leds_pins_default>;
-
- status-led-red {
- gpios = <&wkup_gpio0 32 GPIO_ACTIVE_HIGH>;
- panic-indicator;
- };
-
- status-led-green {
- gpios = <&wkup_gpio0 24 GPIO_ACTIVE_HIGH>;
- };
-
- user-led1-red {
- gpios = <&pcal9535_3 14 GPIO_ACTIVE_HIGH>;
- };
-
- user-led1-green {
- gpios = <&pcal9535_2 15 GPIO_ACTIVE_HIGH>;
- };
-
- user-led2-red {
- gpios = <&wkup_gpio0 17 GPIO_ACTIVE_HIGH>;
- };
-
- user-led2-green {
- gpios = <&wkup_gpio0 22 GPIO_ACTIVE_HIGH>;
- };
- };
-
- dp_refclk: clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <19200000>;
- };
-};
-
-&wkup_pmx0 {
- wkup_i2c0_pins_default: wkup-i2c0-default-pins {
- pinctrl-single,pins = <
- /* (AC7) WKUP_I2C0_SCL */
- AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0)
- /* (AD6) WKUP_I2C0_SDA */
- AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0)
- >;
- };
-
- mcu_i2c0_pins_default: mcu-i2c0-default-pins {
- pinctrl-single,pins = <
- /* (AD8) MCU_I2C0_SCL */
- AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0)
- /* (AD7) MCU_I2C0_SDA */
- AM65X_WKUP_IOPAD(0x00ec, PIN_INPUT, 0)
- >;
- };
-
- arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-default-pins {
- pinctrl-single,pins = <
- /* (R2) WKUP_GPIO0_21 */
- AM65X_WKUP_IOPAD(0x0024, PIN_OUTPUT, 7)
- >;
- };
-
- push_button_pins_default: push-button-default-pins {
- pinctrl-single,pins = <
- /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
- AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7)
- >;
- };
-
- arduino_uart_pins_default: arduino-uart-default-pins {
- pinctrl-single,pins = <
- /* (P4) MCU_UART0_RXD */
- AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4)
- /* (P5) MCU_UART0_TXD */
- AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4)
- >;
- };
-
- arduino_io_d2_to_d3_pins_default: arduino-io-d2-to-d3-default-pins {
- pinctrl-single,pins = <
- /* (P1) WKUP_GPIO0_31 */
- AM65X_WKUP_IOPAD(0x004C, PIN_OUTPUT, 7)
- /* (N3) WKUP_GPIO0_33 */
- AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 7)
- >;
- };
-
- arduino_io_oe_pins_default: arduino-io-oe-default-pins {
- pinctrl-single,pins = <
- /* (N4) WKUP_GPIO0_34 */
- AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 7)
- /* (M2) WKUP_GPIO0_36 */
- AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 7)
- /* (M3) WKUP_GPIO0_37 */
- AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 7)
- /* (M4) WKUP_GPIO0_38 */
- AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 7)
- /* (M1) WKUP_GPIO0_41 */
- AM65X_WKUP_IOPAD(0x0074, PIN_OUTPUT, 7)
- >;
- };
-
- mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
- pinctrl-single,pins = <
- /* (V1) MCU_OSPI0_CLK */
- AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0)
- /* (U2) MCU_OSPI0_DQS */
- AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0)
- /* (U4) MCU_OSPI0_D0 */
- AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0)
- /* (U5) MCU_OSPI0_D1 */
- AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0)
- /* (R4) MCU_OSPI0_CSn0 */
- AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0)
- >;
- };
-
- db9_com_mode_pins_default: db9-com-mode-default-pins {
- pinctrl-single,pins = <
- /* (AD3) WKUP_GPIO0_5, used as uart0 mode 0 */
- AM65X_WKUP_IOPAD(0x00c4, PIN_OUTPUT, 7)
- /* (AC3) WKUP_GPIO0_4, used as uart0 mode 1 */
- AM65X_WKUP_IOPAD(0x00c0, PIN_OUTPUT, 7)
- /* (AC1) WKUP_GPIO0_7, used as uart0 term */
- AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 7)
- /* (AC2) WKUP_GPIO0_6, used as uart0 en */
- AM65X_WKUP_IOPAD(0x00c8, PIN_OUTPUT, 7)
- >;
- };
-
- leds_pins_default: leds-default-pins {
- pinctrl-single,pins = <
- /* (T2) WKUP_GPIO0_17, used as user led1 red */
- AM65X_WKUP_IOPAD(0x0014, PIN_OUTPUT, 7)
- /* (R3) WKUP_GPIO0_22, used as user led1 green */
- AM65X_WKUP_IOPAD(0x0028, PIN_OUTPUT, 7)
- /* (R5) WKUP_GPIO0_24, used as status led red */
- AM65X_WKUP_IOPAD(0x0030, PIN_OUTPUT, 7)
- /* (N2) WKUP_GPIO0_32, used as status led green */
- AM65X_WKUP_IOPAD(0x0050, PIN_OUTPUT, 7)
- >;
- };
-
- mcu_spi0_pins_default: mcu-spi0-default-pins {
- pinctrl-single,pins = <
- /* (Y1) MCU_SPI0_CLK */
- AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 0)
- /* (Y3) MCU_SPI0_D0 */
- AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 0)
- /* (Y2) MCU_SPI0_D1 */
- AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 0)
- /* (Y4) MCU_SPI0_CS0 */
- AM65X_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0)
- >;
- };
-
- minipcie_pins_default: minipcie-default-pins {
- pinctrl-single,pins = <
- /* (P2) MCU_OSPI1_DQS.WKUP_GPIO0_27 */
- AM65X_WKUP_IOPAD(0x003C, PIN_OUTPUT, 7)
- >;
- };
-};
-
-&main_pmx0 {
- main_uart1_pins_default: main-uart1-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x0174, PIN_INPUT, 6) /* (AE23) UART1_RXD */
- AM65X_IOPAD(0x014c, PIN_OUTPUT, 6) /* (AD23) UART1_TXD */
- AM65X_IOPAD(0x0178, PIN_INPUT, 6) /* (AD22) UART1_CTSn */
- AM65X_IOPAD(0x017c, PIN_OUTPUT, 6) /* (AC21) UART1_RTSn */
- >;
- };
-
- main_i2c3_pins_default: main-i2c3-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x01c0, PIN_INPUT, 2) /* (AF13) I2C3_SCL */
- AM65X_IOPAD(0x01d4, PIN_INPUT, 2) /* (AG12) I2C3_SDA */
- >;
- };
-
- main_mmc1_pins_default: main-mmc1-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
- AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
- AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
- AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
- AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
- AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
- AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
- AM65X_IOPAD(0x02e0, PIN_INPUT_PULLUP, 0) /* (C24) MMC1_SDWP */
- >;
- };
-
- usb0_pins_default: usb0-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
- >;
- };
-
- usb1_pins_default: usb1-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
- >;
- };
-
- arduino_io_d4_to_d9_pins_default: arduino-io-d4-to-d9-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x0084, PIN_OUTPUT, 7) /* (AG18) GPIO0_33 */
- AM65X_IOPAD(0x008C, PIN_OUTPUT, 7) /* (AF17) GPIO0_35 */
- AM65X_IOPAD(0x0098, PIN_OUTPUT, 7) /* (AH16) GPIO0_38 */
- AM65X_IOPAD(0x00AC, PIN_OUTPUT, 7) /* (AH15) GPIO0_43 */
- AM65X_IOPAD(0x00C0, PIN_OUTPUT, 7) /* (AG15) GPIO0_48 */
- AM65X_IOPAD(0x00CC, PIN_OUTPUT, 7) /* (AD15) GPIO0_51 */
- >;
- };
-
- dss_vout1_pins_default: dss-vout1-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x0000, PIN_OUTPUT, 1) /* VOUT1_DATA0 */
- AM65X_IOPAD(0x0004, PIN_OUTPUT, 1) /* VOUT1_DATA1 */
- AM65X_IOPAD(0x0008, PIN_OUTPUT, 1) /* VOUT1_DATA2 */
- AM65X_IOPAD(0x000c, PIN_OUTPUT, 1) /* VOUT1_DATA3 */
- AM65X_IOPAD(0x0010, PIN_OUTPUT, 1) /* VOUT1_DATA4 */
- AM65X_IOPAD(0x0014, PIN_OUTPUT, 1) /* VOUT1_DATA5 */
- AM65X_IOPAD(0x0018, PIN_OUTPUT, 1) /* VOUT1_DATA6 */
- AM65X_IOPAD(0x001c, PIN_OUTPUT, 1) /* VOUT1_DATA7 */
- AM65X_IOPAD(0x0020, PIN_OUTPUT, 1) /* VOUT1_DATA8 */
- AM65X_IOPAD(0x0024, PIN_OUTPUT, 1) /* VOUT1_DATA9 */
- AM65X_IOPAD(0x0028, PIN_OUTPUT, 1) /* VOUT1_DATA10 */
- AM65X_IOPAD(0x002c, PIN_OUTPUT, 1) /* VOUT1_DATA11 */
- AM65X_IOPAD(0x0030, PIN_OUTPUT, 1) /* VOUT1_DATA12 */
- AM65X_IOPAD(0x0034, PIN_OUTPUT, 1) /* VOUT1_DATA13 */
- AM65X_IOPAD(0x0038, PIN_OUTPUT, 1) /* VOUT1_DATA14 */
- AM65X_IOPAD(0x003c, PIN_OUTPUT, 1) /* VOUT1_DATA15 */
- AM65X_IOPAD(0x0040, PIN_OUTPUT, 1) /* VOUT1_DATA16 */
- AM65X_IOPAD(0x0044, PIN_OUTPUT, 1) /* VOUT1_DATA17 */
- AM65X_IOPAD(0x0048, PIN_OUTPUT, 1) /* VOUT1_DATA18 */
- AM65X_IOPAD(0x004c, PIN_OUTPUT, 1) /* VOUT1_DATA19 */
- AM65X_IOPAD(0x0050, PIN_OUTPUT, 1) /* VOUT1_DATA20 */
- AM65X_IOPAD(0x0054, PIN_OUTPUT, 1) /* VOUT1_DATA21 */
- AM65X_IOPAD(0x0058, PIN_OUTPUT, 1) /* VOUT1_DATA22 */
- AM65X_IOPAD(0x005c, PIN_OUTPUT, 1) /* VOUT1_DATA23 */
- AM65X_IOPAD(0x0060, PIN_OUTPUT, 1) /* VOUT1_VSYNC */
- AM65X_IOPAD(0x0064, PIN_OUTPUT, 1) /* VOUT1_HSYNC */
- AM65X_IOPAD(0x0068, PIN_OUTPUT, 1) /* VOUT1_PCLK */
- AM65X_IOPAD(0x006c, PIN_OUTPUT, 1) /* VOUT1_DE */
- >;
- };
-
- dp_pins_default: dp-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AF18) DP rst_n */
- >;
- };
-
- main_i2c2_pins_default: main-i2c2-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) I2C2_SCL */
- AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) I2C2_SDA */
- >;
- };
-};
-
-&main_pmx1 {
- main_i2c0_pins_default: main-i2c0-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */
- AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */
- >;
- };
-
- main_i2c1_pins_default: main-i2c1-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */
- AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
- >;
- };
-
- ecap0_pins_default: ecap0-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
- >;
- };
-};
-
-&wkup_uart0 {
- /* Wakeup UART is used by System firmware */
- status = "reserved";
-};
-
-&main_uart1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart1_pins_default>;
-};
-
-&mcu_uart0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&arduino_uart_pins_default>;
-};
-
-&main_gpio0 {
- pinctrl-names = "default";
- pinctrl-0 = <&arduino_io_d4_to_d9_pins_default>;
- gpio-line-names =
- "main_gpio0-base", "", "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "", "", "",
- "", "", "", "IO4", "", "IO5", "", "", "IO6", "",
- "", "", "", "IO7", "", "", "", "", "IO8", "",
- "", "IO9";
-};
-
-&wkup_gpio0 {
- pinctrl-names = "default";
- pinctrl-0 =
- <&arduino_io_d2_to_d3_pins_default>,
- <&arduino_i2c_aio_switch_pins_default>,
- <&arduino_io_oe_pins_default>,
- <&push_button_pins_default>,
- <&db9_com_mode_pins_default>;
- gpio-line-names =
- /* 0..9 */
- "wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0",
- "UART0-enable", "UART0-terminate", "", "WIFI-disable",
- /* 10..19 */
- "", "", "", "", "", "", "", "", "", "",
- /* 20..29 */
- "", "A4A5-I2C-mux", "", "", "", "USER-button", "", "", "","IO0",
- /* 30..39 */
- "IO1", "IO2", "", "IO3", "IO17-direction", "A5",
- "IO16-direction", "IO15-direction", "IO14-direction", "A3",
- /* 40..49 */
- "", "IO18-direction", "A4", "A2", "A1", "A0", "", "", "IO13",
- "IO11",
- /* 50..51 */
- "IO12", "IO10";
-};
-
-&wkup_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_i2c0_pins_default>;
- clock-frequency = <400000>;
-};
-
-&mcu_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_i2c0_pins_default>;
- clock-frequency = <400000>;
-
- psu: regulator@60 {
- compatible = "ti,tps62363";
- reg = <0x60>;
- regulator-name = "tps62363-vout";
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1500000>;
- regulator-boot-on;
- ti,vsel0-state-high;
- ti,vsel1-state-high;
- ti,enable-vout-discharge;
- };
-
- /* D4200 */
- pcal9535_1: gpio@20 {
- compatible = "nxp,pcal9535";
- reg = <0x20>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-line-names =
- "A0-pull", "A1-pull", "A2-pull", "A3-pull", "A4-pull",
- "A5-pull", "", "",
- "IO14-enable", "IO15-enable", "IO16-enable",
- "IO17-enable", "IO18-enable", "IO19-enable";
- };
-
- /* D4201 */
- pcal9535_2: gpio@21 {
- compatible = "nxp,pcal9535";
- reg = <0x21>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-line-names =
- "IO0-direction", "IO1-direction", "IO2-direction",
- "IO3-direction", "IO4-direction", "IO5-direction",
- "IO6-direction", "IO7-direction",
- "IO8-direction", "IO9-direction", "IO10-direction",
- "IO11-direction", "IO12-direction", "IO13-direction",
- "IO19-direction";
- };
-
- /* D4202 */
- pcal9535_3: gpio@25 {
- compatible = "nxp,pcal9535";
- reg = <0x25>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-line-names =
- "IO0-pull", "IO1-pull", "IO2-pull", "IO3-pull",
- "IO4-pull", "IO5-pull", "IO6-pull", "IO7-pull",
- "IO8-pull", "IO9-pull", "IO10-pull", "IO11-pull",
- "IO12-pull", "IO13-pull";
- };
-};
-
-&main_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c0_pins_default>;
- clock-frequency = <400000>;
-
- rtc: rtc@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- };
-
- eeprom: eeprom@54 {
- compatible = "atmel,24c08";
- reg = <0x54>;
- pagesize = <16>;
- };
-};
-
-&main_i2c1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c1_pins_default>;
- clock-frequency = <400000>;
-};
-
-&main_i2c2 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c2_pins_default>;
- clock-frequency = <400000>;
-};
-
-&main_i2c3 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c3_pins_default>;
- clock-frequency = <400000>;
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- edp-bridge@f {
- compatible = "toshiba,tc358767";
- reg = <0x0f>;
- pinctrl-names = "default";
- pinctrl-0 = <&dp_pins_default>;
- reset-gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>;
-
- clock-names = "ref";
- clocks = <&dp_refclk>;
-
- toshiba,hpd-pin = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
-
- bridge_in: endpoint {
- remote-endpoint = <&dpi_out>;
- };
- };
- };
- };
-};
-
-&mcu_cpsw {
- status = "disabled";
-};
-
-&ecap0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&ecap0_pins_default>;
-};
-
-&sdhci1 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_mmc1_pins_default>;
- ti,driver-strength-ohm = <50>;
- disable-wp;
-};
-
-&usb0 {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_pins_default>;
- dr_mode = "host";
-};
-
-&usb1 {
- pinctrl-names = "default";
- pinctrl-0 = <&usb1_pins_default>;
- dr_mode = "host";
-};
-
-&mcu_spi0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_spi0_pins_default>;
-
- #address-cells = <1>;
- #size-cells = <0>;
- ti,pindir-d0-out-d1-in;
-};
-
-&tscadc1 {
- status = "okay";
- adc {
- ti,adc-channels = <0 1 2 3 4 5>;
- };
-};
-
-&ospi0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <1>;
- spi-max-frequency = <50000000>;
- cdns,tshsl-ns = <60>;
- cdns,tsd2d-ns = <60>;
- cdns,tchsh-ns = <60>;
- cdns,tslch-ns = <60>;
- cdns,read-delay = <2>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- seboot@0 {
- label = "seboot";
- reg = <0x0 0x180000>; /* 1.5M */
- };
-
- tispl@180000 {
- label = "tispl";
- reg = <0x180000 0x200000>; /* 2M */
- };
-
- u-boot@380000 {
- label = "u-boot";
- reg = <0x380000 0x300000>; /* 3M */
- };
-
- env@680000 {
- label = "env";
- reg = <0x680000 0x20000>; /* 128K */
- };
-
- env-backup@6a0000 {
- label = "env.backup";
- reg = <0x6a0000 0x20000>; /* 128K */
- };
-
- otpcmd@6c0000 {
- label = "otpcmd";
- reg = <0x6c0000 0x10000>; /* 64K */
- };
-
- unused@6d0000 {
- label = "unused";
- reg = <0x6d0000 0x7b0000>; /* 7872K */
- };
-
- seboot-backup@e80000 {
- label = "seboot.backup";
- reg = <0xe80000 0x180000>; /* 1.5M */
- };
- };
- };
-};
-
-&dss {
- pinctrl-names = "default";
- pinctrl-0 = <&dss_vout1_pins_default>;
-
- assigned-clocks = <&k3_clks 67 2>;
- assigned-clock-parents = <&k3_clks 67 5>;
-};
-
-&dss_ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@1 {
- reg = <1>;
-
- dpi_out: endpoint {
- remote-endpoint = <&bridge_in>;
- };
- };
-};
-
-&pcie1_rc {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&minipcie_pins_default>;
-
- num-lanes = <1>;
- phys = <&serdes1 PHY_TYPE_PCIE 0>;
- phy-names = "pcie-phy0";
- reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>;
-};
-
-&mailbox0_cluster0 {
- status = "okay";
- interrupts = <436>;
-
- mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
- ti,mbox-tx = <1 0 0>;
- ti,mbox-rx = <0 0 0>;
- };
-};
-
-&mailbox0_cluster1 {
- status = "okay";
- interrupts = <432>;
-
- mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
- ti,mbox-tx = <1 0 0>;
- ti,mbox-rx = <0 0 0>;
- };
-};
-
-&mcu_r5fss0_core0 {
- memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
- <&mcu_r5fss0_core0_memory_region>;
- mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
-};
-
-&mcu_r5fss0_core1 {
- memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
- <&mcu_r5fss0_core1_memory_region>;
- mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>;
-};
-
-&mcu_rti1 {
- memory-region = <&wdt_reset_memory_region>;
-};
diff --git a/arch/arm/dts/k3-am65-iot2050-spl.dts b/arch/arm/dts/k3-am65-iot2050-spl.dts
deleted file mode 100644
index 4e668fa..0000000
--- a/arch/arm/dts/k3-am65-iot2050-spl.dts
+++ /dev/null
@@ -1,17 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) Siemens AG, 2018-2021
- *
- * Authors:
- * Jan Kiszka <jan.kiszka@siemens.com>
- */
-
-/dts-v1/;
-
-#include "k3-am65-iot2050-common.dtsi"
-#include "k3-am65-iot2050-common-u-boot.dtsi"
-
-/ {
- compatible = "siemens,iot2050", "ti,am654";
- model = "Siemens IOT2050";
-};
diff --git a/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi b/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi
deleted file mode 100644
index 5ab434c..0000000
--- a/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi
+++ /dev/null
@@ -1,61 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) Siemens AG, 2018-2021
- *
- * Authors:
- * Le Jin <le.jin@siemens.com>
- * Jan Kiszka <jan.kiszka@siemens.com>
- *
- * Common bits of the IOT2050 Basic variant, PG1 and PG2
- */
-
-#include "k3-am65-iot2050-common.dtsi"
-
-/ {
- memory@80000000 {
- device_type = "memory";
- /* 1G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
- };
-
- cpus {
- cpu-map {
- /delete-node/ cluster1;
- };
- /delete-node/ cpu@100;
- /delete-node/ cpu@101;
- };
-
- /delete-node/ l2-cache1;
-};
-
-/* eMMC */
-&sdhci0 {
- status = "disabled";
-};
-
-&main_pmx0 {
- main_uart0_pins_default: main-uart0-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
- AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
- AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
- AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
- AM65X_IOPAD(0x0188, PIN_INPUT, 1) /* (D25) UART0_DCDn */
- AM65X_IOPAD(0x018c, PIN_INPUT, 1) /* (B26) UART0_DSRn */
- AM65X_IOPAD(0x0190, PIN_OUTPUT, 1) /* (A24) UART0_DTRn */
- AM65X_IOPAD(0x0194, PIN_INPUT, 1) /* (E24) UART0_RIN */
- >;
- };
-};
-
-&main_uart0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
-};
-
-&mcu_r5fss0 {
- /* lock-step mode not supported on Basic boards */
- ti,cluster-mode = <0>;
-};
diff --git a/arch/arm/dts/k3-am6528-iot2050-basic-pg2.dts b/arch/arm/dts/k3-am6528-iot2050-basic-pg2.dts
deleted file mode 100644
index c62549a..0000000
--- a/arch/arm/dts/k3-am6528-iot2050-basic-pg2.dts
+++ /dev/null
@@ -1,24 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) Siemens AG, 2018-2021
- *
- * Authors:
- * Le Jin <le.jin@siemens.com>
- * Jan Kiszka <jan.kiszka@siemens.com>
- *
- * AM6528-based (dual-core) IOT2050 Basic variant, Product Generation 2
- * 1 GB RAM, no eMMC, main_uart0 on connector X30
- *
- * Product homepage:
- * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
- */
-
-/dts-v1/;
-
-#include "k3-am6528-iot2050-basic-common.dtsi"
-#include "k3-am65-iot2050-common-pg2.dtsi"
-
-/ {
- compatible = "siemens,iot2050-basic-pg2", "ti,am654";
- model = "SIMATIC IOT2050 Basic PG2";
-};
diff --git a/arch/arm/dts/k3-am6528-iot2050-basic.dts b/arch/arm/dts/k3-am6528-iot2050-basic.dts
deleted file mode 100644
index 87928ff..0000000
--- a/arch/arm/dts/k3-am6528-iot2050-basic.dts
+++ /dev/null
@@ -1,24 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) Siemens AG, 2018-2021
- *
- * Authors:
- * Le Jin <le.jin@siemens.com>
- * Jan Kiszka <jan.kiszka@siemens.com>
- *
- * AM6528-based (dual-core) IOT2050 Basic variant, Product Generation 1
- * 1 GB RAM, no eMMC, main_uart0 on connector X30
- *
- * Product homepage:
- * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
- */
-
-/dts-v1/;
-
-#include "k3-am6528-iot2050-basic-common.dtsi"
-#include "k3-am65-iot2050-common-pg1.dtsi"
-
-/ {
- compatible = "siemens,iot2050-basic", "ti,am654";
- model = "SIMATIC IOT2050 Basic";
-};
diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi b/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi
deleted file mode 100644
index be55494..0000000
--- a/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi
+++ /dev/null
@@ -1,52 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) Siemens AG, 2018-2021
- *
- * Authors:
- * Le Jin <le.jin@siemens.com>
- * Jan Kiszka <jan.kiszka@siemens.com>
- *
- * Common bits of the IOT2050 Advanced variant, PG1 and PG2
- */
-
-/dts-v1/;
-
-#include "k3-am65-iot2050-common.dtsi"
-
-/ {
- memory@80000000 {
- device_type = "memory";
- /* 2G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
- };
-};
-
-&main_pmx0 {
- main_mmc0_pins_default: main-mmc0-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
- AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
- AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
- AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
- AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
- AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
- AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
- AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
- AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
- AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
- AM65X_IOPAD(0x01b8, PIN_OUTPUT_PULLUP, 7) /* (B23) MMC0_SDWP */
- AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
- AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
- >;
- };
-};
-
-/* eMMC */
-&sdhci0 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_mmc0_pins_default>;
- bus-width = <8>;
- non-removable;
- ti,driver-strength-ohm = <50>;
- disable-wp;
-};
diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-m2.dts b/arch/arm/dts/k3-am6548-iot2050-advanced-m2.dts
deleted file mode 100644
index 774eb14..0000000
--- a/arch/arm/dts/k3-am6548-iot2050-advanced-m2.dts
+++ /dev/null
@@ -1,119 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) Siemens AG, 2018-2023
- *
- * Authors:
- * Chao Zeng <chao.zeng@siemens.com>
- * Jan Kiszka <jan.kiszka@siemens.com>
- *
- * AM6548-based (quad-core) IOT2050 M.2 variant (based on Advanced Product
- * Generation 2), 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30
- *
- * Product homepage:
- * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
- */
-
-#include "k3-am6548-iot2050-advanced-common.dtsi"
-#include "k3-am65-iot2050-common-pg2.dtsi"
-
-/ {
- compatible = "siemens,iot2050-advanced-m2", "ti,am654";
- model = "SIMATIC IOT2050 Advanced M2";
-};
-
-&mcu_r5fss0 {
- /* lock-step mode not supported on this board */
- ti,cluster-mode = <0>;
-};
-
-&main_pmx0 {
- main_m2_enable_pins_default: main-m2-enable-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */
- >;
- };
-
- main_bkey_pcie_reset: main-bkey-pcie-reset-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x01bc, PIN_OUTPUT_PULLUP, 7) /* (AG13) GPIO1_15 */
- >;
- };
-
- main_pmx0_m2_config_pins_default: main-pmx0-m2-config-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x01c8, PIN_INPUT_PULLUP, 7) /* (AE13) GPIO1_18 */
- AM65X_IOPAD(0x01cc, PIN_INPUT_PULLUP, 7) /* (AD13) GPIO1_19 */
- >;
- };
-
- main_m2_pcie_mux_control: main-m2-pcie-mux-control-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x0148, PIN_INPUT_PULLUP, 7) /* (AG22) GPIO0_82 */
- AM65X_IOPAD(0x0160, PIN_INPUT_PULLUP, 7) /* (AE20) GPIO0_88 */
- AM65X_IOPAD(0x0164, PIN_INPUT_PULLUP, 7) /* (AF19) GPIO0_89 */
- >;
- };
-};
-
-&main_pmx1 {
- main_pmx1_m2_config_pins_default: main-pmx1-m2-config-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x0018, PIN_INPUT_PULLUP, 7) /* (B22) GPIO1_88 */
- AM65X_IOPAD(0x001c, PIN_INPUT_PULLUP, 7) /* (C23) GPIO1_89 */
- >;
- };
-};
-
-&main_gpio0 {
- pinctrl-names = "default";
- pinctrl-0 =
- <&main_m2_pcie_mux_control>,
- <&arduino_io_d4_to_d9_pins_default>;
-};
-
-&main_gpio1 {
- pinctrl-names = "default";
- pinctrl-0 =
- <&main_m2_enable_pins_default>,
- <&main_pmx0_m2_config_pins_default>,
- <&main_pmx1_m2_config_pins_default>,
- <&cp2102n_reset_pin_default>;
-};
-
-/*
- * Base configuration for B-key slot with PCIe x2, E-key with USB 2.0 only.
- * Firmware switches to other modes via device tree overlays.
- */
-
-&serdes0 {
- assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
- assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
-};
-
-&pcie0_rc {
- pinctrl-names = "default";
- pinctrl-0 = <&main_bkey_pcie_reset>;
-
- num-lanes = <2>;
- phys = <&serdes0 PHY_TYPE_PCIE 1>, <&serdes1 PHY_TYPE_PCIE 1>;
- phy-names = "pcie-phy0","pcie-phy1";
- reset-gpios = <&main_gpio1 15 GPIO_ACTIVE_HIGH>;
- status = "okay";
-};
-
-&pcie1_rc {
- status = "disabled";
-};
-
-&dwc3_0 {
- assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
- <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
- /delete-property/ phys;
- /delete-property/ phy-names;
-};
-
-&usb0 {
- maximum-speed = "high-speed";
- /delete-property/ snps,dis-u1-entry-quirk;
- /delete-property/ snps,dis-u2-entry-quirk;
-};
diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-pg2.dts b/arch/arm/dts/k3-am6548-iot2050-advanced-pg2.dts
deleted file mode 100644
index f00dc86..0000000
--- a/arch/arm/dts/k3-am6548-iot2050-advanced-pg2.dts
+++ /dev/null
@@ -1,29 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) Siemens AG, 2018-2021
- *
- * Authors:
- * Le Jin <le.jin@siemens.com>
- * Jan Kiszka <jan.kiszka@siemens.com>
- *
- * AM6548-based (quad-core) IOT2050 Advanced variant, Product Generation 2
- * 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30
- *
- * Product homepage:
- * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
- */
-
-/dts-v1/;
-
-#include "k3-am6548-iot2050-advanced-common.dtsi"
-#include "k3-am65-iot2050-common-pg2.dtsi"
-
-/ {
- compatible = "siemens,iot2050-advanced-pg2", "ti,am654";
- model = "SIMATIC IOT2050 Advanced PG2";
-};
-
-&mcu_r5fss0 {
- /* lock-step mode not supported on this board */
- ti,cluster-mode = <0>;
-};
diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-sm-u-boot.dtsi b/arch/arm/dts/k3-am6548-iot2050-advanced-sm-u-boot.dtsi
new file mode 120000
index 0000000..859776d
--- /dev/null
+++ b/arch/arm/dts/k3-am6548-iot2050-advanced-sm-u-boot.dtsi
@@ -0,0 +1 @@
+k3-am6528-iot2050-basic-pg2-u-boot.dtsi
\ No newline at end of file
diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced.dts b/arch/arm/dts/k3-am6548-iot2050-advanced.dts
deleted file mode 100644
index 077f165..0000000
--- a/arch/arm/dts/k3-am6548-iot2050-advanced.dts
+++ /dev/null
@@ -1,24 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) Siemens AG, 2018-2021
- *
- * Authors:
- * Le Jin <le.jin@siemens.com>
- * Jan Kiszka <jan.kiszka@siemens.com>
- *
- * AM6548-based (quad-core) IOT2050 Advanced variant, Product Generation 1
- * 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30
- *
- * Product homepage:
- * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
- */
-
-/dts-v1/;
-
-#include "k3-am6548-iot2050-advanced-common.dtsi"
-#include "k3-am65-iot2050-common-pg1.dtsi"
-
-/ {
- compatible = "siemens,iot2050-advanced", "ti,am654";
- model = "SIMATIC IOT2050 Advanced";
-};
diff --git a/arch/arm/dts/k3-am69-r5-sk.dts b/arch/arm/dts/k3-am69-r5-sk.dts
index 13809f8..9c6e324 100644
--- a/arch/arm/dts/k3-am69-r5-sk.dts
+++ b/arch/arm/dts/k3-am69-r5-sk.dts
@@ -9,105 +9,4 @@
#include "k3-j784s4-ddr-evm-lp4-4266.dtsi"
#include "k3-j784s4-ddr.dtsi"
#include "k3-am69-sk-u-boot.dtsi"
-
-/ {
- chosen {
- tick-timer = &mcu_timer0;
- };
-
- aliases {
- remoteproc0 = &sysctrler;
- remoteproc1 = &a72_0;
- };
-
- a72_0: a72@0 {
- compatible = "ti,am654-rproc";
- reg = <0x0 0x00a90000 0x0 0x10>;
- power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
- <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
- resets = <&k3_reset 202 0>;
- clocks = <&k3_clks 61 0>, <&k3_clks 202 0>;
- clock-names = "gtc", "core";
- assigned-clocks = <&k3_clks 61 0>, <&k3_clks 202 0>;
- assigned-clock-parents = <&k3_clks 61 2>;
- assigned-clock-rates = <200000000>, <2000000000>;
- ti,sci = <&sms>;
- ti,sci-proc-id = <32>;
- ti,sci-host-id = <10>;
- bootph-pre-ram;
- };
-
- dm_tifs: dm-tifs {
- compatible = "ti,j721e-dm-sci";
- ti,host-id = <3>;
- ti,secure-host;
- mbox-names = "rx", "tx";
- mboxes= <&secure_proxy_mcu 21>, <&secure_proxy_mcu 23>;
- bootph-pre-ram;
- };
-};
-
-&mcu_timer0 {
- status = "okay";
- clock-frequency = <250000000>;
- bootph-pre-ram;
-};
-
-&secure_proxy_sa3 {
- status = "okay";
- bootph-pre-ram;
-};
-
-&secure_proxy_mcu {
- status = "okay";
- bootph-pre-ram;
-};
-
-&cbass_mcu_wakeup {
- sysctrler: sysctrler {
- compatible = "ti,am654-system-controller";
- mboxes= <&secure_proxy_mcu 4>,
- <&secure_proxy_mcu 5>,
- <&secure_proxy_sa3 5>;
- mbox-names = "tx", "rx", "boot_notify";
- bootph-pre-ram;
- };
-};
-
-&sms {
- mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
- mbox-names = "tx", "rx", "notify";
- ti,host-id = <4>;
- ti,secure-host;
- bootph-pre-ram;
-};
-
-/* WKUP UART0 is used for DM firmware logs */
-&wkup_uart0 {
- bootph-pre-ram;
- status = "okay";
-};
-
-&ospi0 {
- reg = <0x0 0x47040000 0x0 0x100>,
- <0x0 0x50000000 0x0 0x8000000>;
-};
-
-&ospi1 {
- reg = <0x0 0x47050000 0x0 0x100>,
- <0x0 0x58000000 0x0 0x8000000>;
-};
-
-&fss {
- /* enable ranges missing from the FSS node */
- ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>,
- <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>;
-};
-
-&mcu_ringacc {
- ti,sci = <&dm_tifs>;
-};
-
-&mcu_udmap {
- ti,sci = <&dm_tifs>;
-};
+#include "k3-j784s4-r5.dtsi"
diff --git a/arch/arm/dts/k3-j784s4-r5-evm.dts b/arch/arm/dts/k3-j784s4-r5-evm.dts
index 8b8b0e7..0eeffa7 100644
--- a/arch/arm/dts/k3-j784s4-r5-evm.dts
+++ b/arch/arm/dts/k3-j784s4-r5-evm.dts
@@ -9,105 +9,4 @@
#include "k3-j784s4-ddr-evm-lp4-4266.dtsi"
#include "k3-j784s4-ddr.dtsi"
#include "k3-j784s4-evm-u-boot.dtsi"
-
-/ {
- chosen {
- tick-timer = &mcu_timer0;
- };
-
- aliases {
- remoteproc0 = &sysctrler;
- remoteproc1 = &a72_0;
- };
-
- a72_0: a72@0 {
- compatible = "ti,am654-rproc";
- reg = <0x0 0x00a90000 0x0 0x10>;
- power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
- <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
- resets = <&k3_reset 202 0>;
- clocks = <&k3_clks 61 0>, <&k3_clks 202 0>;
- clock-names = "gtc", "core";
- assigned-clocks = <&k3_clks 61 0>, <&k3_clks 202 0>;
- assigned-clock-parents = <&k3_clks 61 2>;
- assigned-clock-rates = <200000000>, <2000000000>;
- ti,sci = <&sms>;
- ti,sci-proc-id = <32>;
- ti,sci-host-id = <10>;
- bootph-pre-ram;
- };
-
- dm_tifs: dm-tifs {
- compatible = "ti,j721e-dm-sci";
- ti,host-id = <3>;
- ti,secure-host;
- mbox-names = "rx", "tx";
- mboxes= <&secure_proxy_mcu 21>, <&secure_proxy_mcu 23>;
- bootph-pre-ram;
- };
-};
-
-&mcu_timer0 {
- status = "okay";
- clock-frequency = <250000000>;
- bootph-pre-ram;
-};
-
-&secure_proxy_sa3 {
- status = "okay";
- bootph-pre-ram;
-};
-
-&secure_proxy_mcu {
- status = "okay";
- bootph-pre-ram;
-};
-
-&cbass_mcu_wakeup {
- sysctrler: sysctrler {
- compatible = "ti,am654-system-controller";
- mboxes= <&secure_proxy_mcu 4>,
- <&secure_proxy_mcu 5>,
- <&secure_proxy_sa3 5>;
- mbox-names = "tx", "rx", "boot_notify";
- bootph-pre-ram;
- };
-};
-
-&sms {
- mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
- mbox-names = "tx", "rx", "notify";
- ti,host-id = <4>;
- ti,secure-host;
- bootph-pre-ram;
-};
-
-/* WKUP UART0 is used for DM firmware logs */
-&wkup_uart0 {
- bootph-pre-ram;
- status = "okay";
-};
-
-&ospi0 {
- reg = <0x0 0x47040000 0x0 0x100>,
- <0x0 0x50000000 0x0 0x8000000>;
-};
-
-&ospi1 {
- reg = <0x0 0x47050000 0x0 0x100>,
- <0x0 0x58000000 0x0 0x8000000>;
-};
-
-&fss {
- /* enable ranges missing from the FSS node */
- ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>,
- <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>;
-};
-
-&mcu_ringacc {
- ti,sci = <&dm_tifs>;
-};
-
-&mcu_udmap {
- ti,sci = <&dm_tifs>;
-};
+#include "k3-j784s4-r5.dtsi"
diff --git a/arch/arm/dts/k3-j784s4-r5.dtsi b/arch/arm/dts/k3-j784s4-r5.dtsi
new file mode 100644
index 0000000..0cd0ccc
--- /dev/null
+++ b/arch/arm/dts/k3-j784s4-r5.dtsi
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+ chosen {
+ tick-timer = &mcu_timer0;
+ };
+
+ aliases {
+ remoteproc0 = &sysctrler;
+ remoteproc1 = &a72_0;
+ };
+
+ a72_0: a72@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x0 0x00a90000 0x0 0x10>;
+ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
+ resets = <&k3_reset 202 0>;
+ clocks = <&k3_clks 61 0>, <&k3_clks 202 0>;
+ clock-names = "gtc", "core";
+ assigned-clocks = <&k3_clks 61 0>, <&k3_clks 202 0>;
+ assigned-clock-parents = <&k3_clks 61 2>;
+ assigned-clock-rates = <200000000>, <2000000000>;
+ ti,sci = <&sms>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ bootph-pre-ram;
+ };
+
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <3>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes= <&secure_proxy_mcu 21>, <&secure_proxy_mcu 23>;
+ bootph-pre-ram;
+ };
+};
+
+&mcu_timer0 {
+ status = "okay";
+ clock-frequency = <250000000>;
+ bootph-pre-ram;
+};
+
+&secure_proxy_sa3 {
+ status = "okay";
+ bootph-pre-ram;
+};
+
+&secure_proxy_mcu {
+ status = "okay";
+ bootph-pre-ram;
+};
+
+&cbass_mcu_wakeup {
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <&secure_proxy_mcu 4>,
+ <&secure_proxy_mcu 5>,
+ <&secure_proxy_sa3 5>;
+ mbox-names = "tx", "rx", "boot_notify";
+ bootph-pre-ram;
+ };
+};
+
+&sms {
+ mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
+ mbox-names = "tx", "rx", "notify";
+ ti,host-id = <4>;
+ ti,secure-host;
+ bootph-pre-ram;
+};
+
+/* WKUP UART0 is used for DM firmware logs */
+&wkup_uart0 {
+ bootph-pre-ram;
+ status = "okay";
+};
+
+&ospi0 {
+ reg = <0x0 0x47040000 0x0 0x100>,
+ <0x0 0x50000000 0x0 0x8000000>;
+};
+
+&ospi1 {
+ reg = <0x0 0x47050000 0x0 0x100>,
+ <0x0 0x58000000 0x0 0x8000000>;
+};
+
+&fss {
+ /* enable ranges missing from the FSS node */
+ ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>,
+ <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>;
+};
+
+&mcu_ringacc {
+ ti,sci = <&dm_tifs>;
+};
+
+&mcu_udmap {
+ ti,sci = <&dm_tifs>;
+};
diff --git a/arch/arm/dts/qemu-sbsa.dts b/arch/arm/dts/qemu-sbsa.dts
new file mode 100644
index 0000000..ed00e50
--- /dev/null
+++ b/arch/arm/dts/qemu-sbsa.dts
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Devicetree with onboard devices for qemu_sbsa-ref for internal use only!
+ * DO NOT PASS TO THE OS!
+ *
+ * As QEMU provides only a minimal devicetree this one is merged with
+ * it and then fixed at runtime.
+ *
+ * Copyright 2024 9elements GmbH
+ */
+#include "configs/qemu-sbsa.h"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/dts-v1/;
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&intc>;
+ compatible = "linux,sbsa-ref";
+
+ binman: binman {
+ multiple-images;
+ };
+
+ cpus {
+ /* Filled by fdtdec_board_setup() */
+ };
+
+ memory {
+ /* Filled by fdtdec_board_setup() */
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cfi_flash {
+ compatible = "cfi-flash";
+ reg = /bits/ 64 <SBSA_FLASH_BASE_ADDR
+ SBSA_FLASH_LENGTH>;
+ status = "okay";
+ };
+
+ uart0 {
+ compatible = "arm,pl011";
+ status = "okay";
+ reg = /bits/ 64 <SBSA_UART_BASE_ADDR
+ SBSA_UART_LENGTH>;
+ };
+
+ ahci {
+ compatible = "generic-ahci";
+ status = "okay";
+ reg = /bits/ 64 <0x60100000 0x00010000>;
+ };
+
+ xhci {
+ compatible = "generic-xhci";
+ status = "okay";
+ reg = /bits/ 64 <0x60110000 0x00010000>;
+ };
+
+ pci {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ compatible = "pci-host-ecam-generic";
+ device_type = "pci";
+ status = "okay";
+ reg = /bits/ 64 <0xf0000000 0x10000000>;
+ bus-range = <0 0xff>;
+ ranges = /bits/ 32 <0x01000000>,
+ /bits/ 64 <0
+ SBSA_PIO_BASE_ADDR
+ SBSA_PIO_LENGTH>,
+ /bits/ 32 <0x02000000>,
+ /bits/ 64 <SBSA_PCIE_MMIO_BASE_ADDR
+ SBSA_PCIE_MMIO_BASE_ADDR
+ SBSA_PCIE_MMIO_LENGTH>,
+ /bits/ 32 <0x43000000>,
+ /bits/ 64 <SBSA_PCIE_MMIO_HIGH_BASE_ADDR
+ SBSA_PCIE_MMIO_HIGH_BASE_ADDR
+ SBSA_PCIE_MMIO_HIGH_LENGTH>;
+ };
+ };
+
+ intc: interrupt-controller {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ status = "okay";
+ interrupt-controller;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = /bits/ 64 <SBSA_GIC_DIST_BASE_ADDR SBSA_GIC_DIST_LENGTH>,
+ /bits/ 64 <SBSA_GIC_REDIST_BASE_ADDR SBSA_GIC_REDIST_LENGTH>,
+ /bits/ 64 <0 0>,
+ /bits/ 64 <SBSA_GIC_HBASE_ADDR SBSA_GIC_HBASE_LENGTH>,
+ /bits/ 64 <SBSA_GIC_VBASE_ADDR SBSA_GIC_VBASE_LENGTH>;
+ };
+
+ its {
+ compatible = "arm,gic-v3-its";
+ status = "disabled";
+ };
+};
+
+&binman {
+ secure-world {
+ filename = "secure-world.rom";
+ size = <SBSA_SECURE_FLASH_LENGTH>;
+
+ bl1 {
+ offset = <0x0>;
+ description = "ARM Trusted Firmware BL1";
+ filename = "bl1.bin";
+ type = "blob-ext";
+ };
+
+ fip {
+ offset = <0x12000>;
+ description = "ARM Trusted Firmware FIP";
+ filename = "fip.bin";
+ type = "blob-ext";
+ };
+ };
+
+ unsecure-world {
+ filename = "unsecure-world.rom";
+ size = <SBSA_FLASH_LENGTH>;
+
+ u-boot {
+ };
+ u-boot-dtb {
+ compress = "lz4";
+ };
+ };
+};
diff --git a/arch/arm/include/asm/acpi_table.h b/arch/arm/include/asm/acpi_table.h
index e69de29..7386f55 100644
--- a/arch/arm/include/asm/acpi_table.h
+++ b/arch/arm/include/asm/acpi_table.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __ASM_ACPI_TABLE_H__
+#define __ASM_ACPI_TABLE_H__
+
+#ifndef __ACPI__
+#ifndef __ASSEMBLY__
+
+#include <acpi/acpi_table.h>
+
+/**
+ * acpi_write_madt_gicc() - Write out a MADT GICC sub-table
+ *
+ * Write out the GIC CPU Interface sub-table.
+ *
+ * @gicc: Pointer to place to put the sub-table
+ * @cpu_num: GIC's CPU Interface Number
+ * @perf_gsiv: The GSIV used for Performance Monitoring Interrupts
+ * @phys_base: Address at which the processor can access this
+ * GIC CPU Interface
+ * @gicv: Address of the GIC virtual CPU interface registers
+ * @gich: Address of the GIC virtual interface control block
+ * registers
+ * @vgic_maint_irq: GSIV for Virtual GIC maintenance interrupt
+ * @gicr_base: Physical address of the associated Redistributor
+ * @mpidr: MPIDR as defined by ARM architecture
+ * @efficiency: Describes the relative power efficiency
+ */
+void acpi_write_madt_gicc(struct acpi_madt_gicc *gicc, uint cpu_num,
+ uint perf_gsiv, ulong phys_base, ulong gicv,
+ ulong gich, uint vgic_maint_irq, u64 gicr_base,
+ ulong mpidr, uint efficiency);
+
+/**
+ * acpi_write_madt_gicd() - Write out a MADT GICD sub-table
+ *
+ * Write out the GIC Distributor sub-table.
+ *
+ * @gicd: Pointer to place to put the sub-table
+ * @gic_id: This GIC Distributor's hardware ID
+ * @phys_base: The 64-bit physical address for this Distributor
+ * @gic_version: GIC version
+ */
+void acpi_write_madt_gicd(struct acpi_madt_gicd *gicd, uint gic_id,
+ ulong phys_base, uint gic_version);
+
+/**
+ * acpi_write_madt_gicr() - Write out a MADT GICR sub-table
+ *
+ * Write out the GIC Redistributor sub-table.
+ *
+ * @gicr: Pointer to place to put the sub-table
+ * @discovery_range_base_address: Physical address of a page range
+ * containing all GIC Redistributors
+ * @discovery_range_length: Length of the GIC Redistributor
+ * Discovery page range
+ */
+void acpi_write_madt_gicr(struct acpi_madt_gicr *gicr,
+ u64 discovery_range_base_address,
+ u32 discovery_range_length);
+
+/**
+ * acpi_write_madt_its() - Write out a MADT ITS sub-table
+ *
+ * Write out the GIC Interrupt Translation Service sub-table.
+ *
+ * @its: Pointer to place to put the sub-table
+ * @its_id: Uniqueue GIC ITS ID
+ * @physical_base_address: Physical address for the Interrupt
+ * Translation Service
+ */
+void acpi_write_madt_its(struct acpi_madt_its *its,
+ u32 its_id,
+ u64 physical_base_address);
+
+/**
+ * acpi_pptt_add_proc() - Write out a PPTT processor sub-table
+ *
+ * Write out the Processor Properties Topology Table processor sub-table.
+ *
+ * @ctx: ACPI context pointer
+ * @flags: Processor Structure Flags
+ * @parent: Reference to parent processor
+ * @proc_id: ACPI processor ID as defined in MADT
+ * @num_resources: Number of resource structure references
+ * @resource_list: References to other PPTT structures
+ * Return: offset from start of PPTT in bytes
+ */
+int acpi_pptt_add_proc(struct acpi_ctx *ctx, const u32 flags, const u32 parent,
+ const u32 proc_id, const u32 num_resources,
+ const u32 *resource_list);
+
+/**
+ * acpi_pptt_add_cache() - Write out a PPTT cache sub-table
+ *
+ * Write out the Processor Properties Topology Table cache sub-table.
+ *
+ * @ctx: ACPI context pointer
+ * @flags: Cache Structure Flags
+ * @next_cache_level: Reference to next level of cache
+ * @size: Size of the cache in bytes
+ * @sets: Number of sets in the cache
+ * @assoc: Integer number of ways
+ * @attributes: Allocation type, Cache type, policy
+ * @line_size: Line size in bytes
+ * Return: offset from start of PPTT in bytes
+ */
+int acpi_pptt_add_cache(struct acpi_ctx *ctx, const u32 flags,
+ const u32 next_cache_level, const u32 size,
+ const u32 sets, const u8 assoc, const u8 attributes,
+ const u16 line_size);
+
+/* Multi-processor Startup for ARM Platforms */
+/**
+ * struct acpi_pp_page - MP startup handshake mailbox
+ *
+ * Defines a 4096 byte memory region that is used for starting secondary CPUs on
+ * an Arm system that follows the "Multi-processor Startup for ARM Platforms" spec.
+ *
+ * @cpu_id: MPIDR as returned by the Multiprocessor Affinity Register.
+ * On 32bit Arm systems the upper bits are unused.
+ * @jumping_address: On 32bit Arm systems the address must be below 4 GiB
+ * @os_reserved: Reserved for OS use. Firmware must not access this memory.
+ * @spinning_code: Reserved for firmware use. OS must not access this memory.
+ * The spinning code will be installed by firmware and the secondary
+ * CPUs will enter it before the control is handed over to the OS.
+ */
+struct acpi_pp_page {
+ u64 cpu_id;
+ u64 jumping_address;
+ u8 os_reserved[2032];
+ u8 spinning_code[2048];
+} __packed;
+
+#endif /* !__ASSEMBLY__ */
+#endif /* !__ACPI__ */
+
+/* Multi-processor Startup for ARM Platforms defines */
+#define ACPI_PP_CPU_ID_INVALID 0xffffffff
+#define ACPI_PP_JMP_ADR_INVALID 0
+#define ACPI_PP_PAGE_SIZE 4096
+#define ACPI_PP_CPU_ID_OFFSET 0
+#define ACPI_PP_CPU_JMP_OFFSET 8
+#define ACPI_PP_CPU_CODE_OFFSET 2048
+#define ACPI_PP_VERSION 1
+
+#endif /* __ASM_ACPI_TABLE_H__ */
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index f1b7526..95a8cc1 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -15,7 +15,7 @@
#define MCU_BOOTROM_BASE_ADDR 0x007E0000
-#define GPIO1_BASE_ADDR 0X30200000
+#define GPIO1_BASE_ADDR 0x30200000
#define GPIO2_BASE_ADDR 0x30210000
#define GPIO3_BASE_ADDR 0x30220000
#define GPIO4_BASE_ADDR 0x30230000
diff --git a/arch/arm/include/asm/arch-qemu-sbsa/boot0.h b/arch/arm/include/asm/arch-qemu-sbsa/boot0.h
new file mode 100644
index 0000000..4a1a254
--- /dev/null
+++ b/arch/arm/include/asm/arch-qemu-sbsa/boot0.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * sbsa-ref starts U-Boot in XIP memory. Need to relocate U-Boot
+ * to DRAM which is already up. Instead of using SPL this simple loader
+ * is being used.
+ */
+relocate_check:
+ /* x0 contains the pointer to FDT provided by ATF */
+ adr x1, _start /* x1 <- Runtime value of _start */
+ ldr x2, _TEXT_BASE /* x2 <- Linked value of _start */
+ subs x9, x1, x2 /* x9 <- Run-vs-link offset */
+ beq reset
+
+ adrp x1, __image_copy_start /* x2 <- address bits [31:12] */
+ add x1, x1, :lo12:__image_copy_start/* x2 <- address bits [11:00] */
+ adrp x3, __image_copy_end /* x3 <- address bits [31:12] */
+ add x3, x3, :lo12:__image_copy_end /* x3 <- address bits [11:00] */
+ add x3, x3, #0x100000 /* 1 MiB for the DTB found at _end */
+
+copy_loop:
+ ldp x10, x11, [x1], #16 /* copy from source address [x1] */
+ stp x10, x11, [x2], #16 /* copy to target address [x2] */
+ cmp x1, x3 /* until source end address [x3] */
+ b.lo copy_loop
+
+ isb
+ ldr x2, _TEXT_BASE /* x2 <- Linked value of _start */
+ br x2 /* Jump to linked address */
+ /* Never reaches this point */
+1:
+ wfi
+ b 1b
+
+relocate_done:
\ No newline at end of file
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 2237d7d..52f6c9b 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -394,6 +394,15 @@
#define wfi()
#endif
+static inline unsigned long read_mpidr(void)
+{
+ unsigned long val;
+
+ asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (val));
+
+ return val;
+}
+
static inline unsigned long get_cpsr(void)
{
unsigned long cpsr;
@@ -656,22 +665,6 @@
void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
enum dcache_option option);
-#ifdef CONFIG_SYS_NONCACHED_MEMORY
-/**
- * noncached_init() - Initialize non-cached memory region
- *
- * Initialize non-cached memory area. This memory region will be typically
- * located right below the malloc() area and mapped uncached in the MMU.
- *
- * It is called during the generic post-relocation init sequence.
- *
- * Return: 0 if OK
- */
-int noncached_init(void);
-
-phys_addr_t noncached_alloc(size_t size, size_t align);
-#endif /* CONFIG_SYS_NONCACHED_MEMORY */
-
#endif /* __ASSEMBLY__ */
#endif
diff --git a/arch/arm/include/asm/ti-common/ti-aemif.h b/arch/arm/include/asm/ti-common/ti-aemif.h
index a775386..11a7384 100644
--- a/arch/arm/include/asm/ti-common/ti-aemif.h
+++ b/arch/arm/include/asm/ti-common/ti-aemif.h
@@ -16,6 +16,7 @@
#define AEMIF_PRESERVE -1
struct aemif_config {
+ void *base;
unsigned mode;
unsigned select_strobe;
unsigned extend_wait;
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index f254186..1c95dd6 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -68,6 +68,7 @@
ifneq ($(CONFIG_GICV2)$(CONFIG_GICV3),)
obj-y += gic_64.o
endif
+obj-$(CONFIG_DRIVER_GICV2) += gic-v2.o
obj-$(CONFIG_GIC_V3_ITS) += gic-v3-its.o
obj-y += interrupts_64.o
else
@@ -86,6 +87,7 @@
obj-$(CONFIG_DEBUG_LL) += debug.o
obj-$(CONFIG_BLOBLIST) += xferlist.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o
# For EABI conformant tool chains, provide eabi_compat()
ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
diff --git a/arch/arm/lib/acpi_table.c b/arch/arm/lib/acpi_table.c
new file mode 100644
index 0000000..f760b7f
--- /dev/null
+++ b/arch/arm/lib/acpi_table.c
@@ -0,0 +1,276 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Based on acpi.c from coreboot
+ *
+ * Copyright (C) 2024 9elements GmbH
+ */
+
+#define LOG_CATEGORY LOGC_ACPI
+
+#include <bloblist.h>
+#include <cpu_func.h>
+#include <efi_loader.h>
+#include <malloc.h>
+#include <string.h>
+#include <tables_csum.h>
+#include <acpi/acpigen.h>
+#include <acpi/acpi_device.h>
+#include <acpi/acpi_table.h>
+#include <asm-generic/io.h>
+#include <dm/acpi.h>
+#include <dm/uclass.h>
+#include <linux/log2.h>
+#include <linux/sizes.h>
+
+/* defined in assembly file */
+/**
+ * acpi_pp_code_size - Spinloop code size *
+ */
+extern u16 acpi_pp_code_size;
+
+/**
+ * acpi_pp_tables - Start of ACPI PP tables.
+ */
+extern ulong acpi_pp_tables;
+
+/**
+ * acpi_pp_etables - End of ACPI PP tables.
+ */
+extern ulong acpi_pp_etables;
+
+/**
+ * acpi_pp_code_start() - Spinloop code
+ *
+ * Architectural spinloop code to be installed in each parking protocol
+ * page. The spinloop code must be less than 2048 bytes.
+ *
+ * The spinloop code will be entered after calling
+ * acpi_parking_protocol_install().
+ *
+ */
+void acpi_pp_code_start(void);
+
+void acpi_write_madt_gicc(struct acpi_madt_gicc *gicc, uint cpu_num,
+ uint perf_gsiv, ulong phys_base, ulong gicv,
+ ulong gich, uint vgic_maint_irq, u64 gicr_base,
+ ulong mpidr, uint efficiency)
+{
+ memset(gicc, '\0', sizeof(struct acpi_madt_gicc));
+ gicc->type = ACPI_APIC_GICC;
+ gicc->length = sizeof(struct acpi_madt_gicc);
+ gicc->cpu_if_num = cpu_num;
+ gicc->processor_id = cpu_num;
+ gicc->flags = ACPI_MADTF_ENABLED;
+ gicc->perf_gsiv = perf_gsiv;
+ gicc->phys_base = phys_base;
+ gicc->gicv = gicv;
+ gicc->gich = gich;
+ gicc->vgic_maint_irq = vgic_maint_irq;
+ gicc->gicr_base = gicr_base;
+ gicc->mpidr = mpidr;
+ gicc->efficiency = efficiency;
+}
+
+void acpi_write_madt_gicd(struct acpi_madt_gicd *gicd, uint gic_id,
+ ulong phys_base, uint gic_version)
+{
+ memset(gicd, '\0', sizeof(struct acpi_madt_gicd));
+ gicd->type = ACPI_APIC_GICD;
+ gicd->length = sizeof(struct acpi_madt_gicd);
+ gicd->gic_id = gic_id;
+ gicd->phys_base = phys_base;
+ gicd->gic_version = gic_version;
+}
+
+void acpi_write_madt_gicr(struct acpi_madt_gicr *gicr,
+ u64 discovery_range_base_address,
+ u32 discovery_range_length)
+{
+ memset(gicr, '\0', sizeof(struct acpi_madt_gicr));
+ gicr->type = ACPI_APIC_GICR;
+ gicr->length = sizeof(struct acpi_madt_gicr);
+ gicr->discovery_range_base_address = discovery_range_base_address;
+ gicr->discovery_range_length = discovery_range_length;
+}
+
+void acpi_write_madt_its(struct acpi_madt_its *its,
+ u32 its_id,
+ u64 physical_base_address)
+{
+ memset(its, '\0', sizeof(struct acpi_madt_its));
+ its->type = ACPI_APIC_ITS;
+ its->length = sizeof(struct acpi_madt_its);
+ its->gic_its_id = its_id;
+ its->physical_base_address = physical_base_address;
+}
+
+int acpi_pptt_add_proc(struct acpi_ctx *ctx, const u32 flags, const u32 parent,
+ const u32 proc_id, const u32 num_resources,
+ const u32 *resource_list)
+{
+ struct acpi_pptt_proc *proc = ctx->current;
+ int offset;
+
+ offset = ctx->current - ctx->tab_start;
+ proc->hdr.type = ACPI_PPTT_TYPE_PROC;
+ proc->flags = flags;
+ proc->parent = parent;
+ proc->proc_id = proc_id;
+ proc->num_resources = num_resources;
+ proc->hdr.length = sizeof(struct acpi_pptt_proc) +
+ sizeof(u32) * num_resources;
+
+ if (resource_list)
+ memcpy(proc + 1, resource_list, sizeof(u32) * num_resources);
+
+ acpi_inc(ctx, proc->hdr.length);
+
+ return offset;
+}
+
+int acpi_pptt_add_cache(struct acpi_ctx *ctx, const u32 flags,
+ const u32 next_cache_level, const u32 size,
+ const u32 sets, const u8 assoc, const u8 attributes,
+ const u16 line_size)
+{
+ struct acpi_pptt_cache *cache = ctx->current;
+ int offset;
+
+ offset = ctx->current - ctx->tab_start;
+ cache->hdr.type = ACPI_PPTT_TYPE_CACHE;
+ cache->hdr.length = sizeof(struct acpi_pptt_cache);
+ cache->flags = flags;
+ cache->next_cache_level = next_cache_level;
+ cache->size = size;
+ cache->sets = sets;
+ cache->assoc = assoc;
+ cache->attributes = attributes;
+ cache->line_size = line_size;
+ acpi_inc(ctx, cache->hdr.length);
+
+ return offset;
+}
+
+void *acpi_fill_madt(struct acpi_madt *madt, struct acpi_ctx *ctx)
+{
+ uclass_probe_all(UCLASS_CPU);
+ uclass_probe_all(UCLASS_IRQ);
+
+ /* All SoCs must use the driver model */
+ acpi_fill_madt_subtbl(ctx);
+
+ return ctx->current;
+}
+
+/**
+ * acpi_write_pp_setup_one_page() - Fill out one page used by the PP
+ *
+ * Fill out the struct acpi_pp_page to contain the spin-loop
+ * code and the mailbox area. After this function the page is ready for
+ * the secondary core's to enter the spin-loop code.
+ *
+ * @page: Pointer to current parking protocol page
+ * @gicc: Pointer to corresponding GICC sub-table
+ */
+static void acpi_write_pp_setup_one_page(struct acpi_pp_page *page,
+ struct acpi_madt_gicc *gicc)
+{
+ void *reloc;
+
+ /* Update GICC. Mark parking protocol as available. */
+ gicc->parking_proto = ACPI_PP_VERSION;
+ gicc->parked_addr = virt_to_phys(page);
+
+ /* Prepare parking protocol page */
+ memset(page, '\0', sizeof(struct acpi_pp_page));
+
+ /* Init mailbox. Set MPIDR so core's will find their page. */
+ page->cpu_id = gicc->mpidr;
+ page->jumping_address = ACPI_PP_JMP_ADR_INVALID;
+
+ /* Relocate spinning code */
+ reloc = &page->spinning_code[0];
+
+ log_debug("Relocating spin table from %lx to %lx (size %x)\n",
+ (ulong)&acpi_pp_code_start, (ulong)reloc, acpi_pp_code_size);
+ memcpy(reloc, &acpi_pp_code_start, acpi_pp_code_size);
+
+ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ flush_dcache_range((unsigned long)page,
+ (unsigned long)(page + 1));
+}
+
+void acpi_write_park(struct acpi_madt *madt)
+{
+ struct acpi_pp_page *start, *page;
+ struct acpi_madt_gicc *gicc;
+ int ret, i, ncpus = 0;
+
+ /*
+ * According to the "Multi-processor Startup for ARM Platforms":
+ * - Every CPU as specified by MADT GICC has it's own 4K page
+ * - Every page is divided into two sections: OS and FW reserved
+ * - Memory occupied by "Parking Protocol" must be marked 'Reserved'
+ * - Spinloop code should reside in FW reserved 2048 bytes
+ * - Spinloop code will check the mailbox in OS reserved area
+ */
+
+ if (acpi_pp_code_size > sizeof(page->spinning_code)) {
+ log_err("Spinning code too big to fit: %d\n",
+ acpi_pp_code_size);
+ return;
+ }
+
+ /* Count all MADT GICCs including BSP */
+ for (i = sizeof(struct acpi_madt); i < madt->header.length;
+ i += gicc->length) {
+ gicc = (struct acpi_madt_gicc *)((void *)madt + i);
+ if (gicc->type != ACPI_APIC_GICC)
+ continue;
+ ncpus++;
+ }
+ log_debug("Found %#x GICCs in MADT\n", ncpus);
+
+ /* Allocate pages linearly due to assembly code requirements */
+ start = bloblist_add(BLOBLISTT_ACPI_PP, ACPI_PP_PAGE_SIZE * ncpus,
+ ilog2(SZ_4K));
+ if (!start) {
+ log_err("Failed to allocate memory for ACPI-parking-protocol pages\n");
+ return;
+ }
+ log_debug("Allocated parking protocol at %p\n", start);
+ page = start;
+
+ if (IS_ENABLED(CONFIG_EFI_LOADER)) {
+ /* Default mapping is 'BOOT CODE'. Mark as reserved instead. */
+ ret = efi_add_memory_map((u64)(uintptr_t)start,
+ ncpus * ACPI_PP_PAGE_SIZE,
+ EFI_RESERVED_MEMORY_TYPE);
+
+ if (ret)
+ log_err("Reserved memory mapping failed addr %p size %x\n",
+ start, ncpus * ACPI_PP_PAGE_SIZE);
+ }
+
+ /* Prepare the parking protocol pages */
+ for (i = sizeof(struct acpi_madt); i < madt->header.length;
+ i += gicc->length) {
+ gicc = (struct acpi_madt_gicc *)((void *)madt + i);
+ if (gicc->type != ACPI_APIC_GICC)
+ continue;
+
+ acpi_write_pp_setup_one_page(page++, gicc);
+ }
+
+ acpi_pp_etables = virt_to_phys(start) +
+ ACPI_PP_PAGE_SIZE * ncpus;
+ acpi_pp_tables = virt_to_phys(start);
+
+ /* Make sure other cores see written value in memory */
+ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ flush_dcache_all();
+
+ /* Send an event to wake up the secondary CPU. */
+ asm("dsb ishst\n"
+ "sev");
+}
diff --git a/arch/arm/lib/gic-v2.c b/arch/arm/lib/gic-v2.c
new file mode 100644
index 0000000..b70434a
--- /dev/null
+++ b/arch/arm/lib/gic-v2.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Broadcom.
+ */
+#include <dm.h>
+#include <irq.h>
+#include <asm/gic.h>
+#include <asm/acpi_table.h>
+#include <cpu_func.h>
+#include <dm/acpi.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#ifdef CONFIG_ACPIGEN
+/**
+ * acpi_gicv2_fill_madt() - Fill out the body of the MADT
+ *
+ * Write GICD and GICR tables based on collected devicetree data.
+ *
+ * @dev: Device to write ACPI tables for
+ * @ctx: ACPI context to write MADT sub-tables to
+ * Return: 0 if OK
+ */
+static int acpi_gicv2_fill_madt(const struct udevice *dev, struct acpi_ctx *ctx)
+{
+ struct acpi_madt_gicd *gicd;
+ fdt_addr_t addr;
+
+ addr = dev_read_addr_index(dev, 0);
+ if (addr == FDT_ADDR_T_NONE) {
+ pr_err("%s: failed to get GICD address\n", __func__);
+ return -EINVAL;
+ }
+
+ gicd = ctx->current;
+ acpi_write_madt_gicd(gicd, dev_seq(dev), addr, 2);
+ acpi_inc(ctx, gicd->length);
+
+ return 0;
+}
+
+static struct acpi_ops gic_v2_acpi_ops = {
+ .fill_madt = acpi_gicv2_fill_madt,
+};
+#endif
+
+static const struct udevice_id gic_v2_ids[] = {
+ { .compatible = "arm,arm11mp-gic" },
+ { .compatible = "arm,cortex-a15-gic" },
+ { .compatible = "arm,cortex-a7-gic" },
+ { .compatible = "arm,cortex-a5-gic" },
+ { .compatible = "arm,cortex-a9-gic" },
+ { .compatible = "arm,eb11mp-gic" },
+ { .compatible = "arm,gic-400" },
+ { .compatible = "arm,pl390" },
+ { .compatible = "arm,tc11mp-gic" },
+ { .compatible = "qcom,msm-8660-qgic" },
+ { .compatible = "qcom,msm-qgic2" },
+ {}
+};
+
+static int arm_gic_v2_of_xlate(struct irq *irq, struct ofnode_phandle_args *args)
+{
+ if (args->args_count != 3) {
+ log_debug("Invalid args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ /* ARM Generic Interrupt Controller v1 and v2 */
+ if (args->args[0] == GIC_SPI)
+ irq->id = args->args[1] + 32;
+ else
+ irq->id = args->args[1] + 16;
+
+ irq->flags = args->args[2];
+
+ return 0;
+}
+
+static const struct irq_ops arm_gic_v2_ops = {
+ .of_xlate = arm_gic_v2_of_xlate,
+};
+
+U_BOOT_DRIVER(arm_gic_v2) = {
+ .name = "gic-v2",
+ .id = UCLASS_IRQ,
+ .of_match = gic_v2_ids,
+ .ops = &arm_gic_v2_ops,
+ ACPI_OPS_PTR(&gic_v2_acpi_ops)
+};
diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c
index 2cc0a32..51cc239 100644
--- a/arch/arm/lib/gic-v3-its.c
+++ b/arch/arm/lib/gic-v3-its.c
@@ -4,9 +4,13 @@
*/
#include <cpu_func.h>
#include <dm.h>
+#include <irq.h>
+#include <asm/acpi_table.h>
#include <asm/gic.h>
#include <asm/gic-v3.h>
#include <asm/io.h>
+#include <dm/acpi.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <linux/bitops.h>
#include <linux/printk.h>
#include <linux/sizes.h>
@@ -26,19 +30,21 @@
struct gic_v3_its_priv {
ulong gicd_base;
ulong gicr_base;
+ ulong gicr_length;
};
static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv *priv)
{
struct udevice *dev;
fdt_addr_t addr;
+ fdt_size_t size;
int ret;
ret = uclass_get_device_by_driver(UCLASS_IRQ,
- DM_DRIVER_GET(arm_gic_v3_its), &dev);
+ DM_DRIVER_GET(arm_gic_v3), &dev);
if (ret) {
pr_err("%s: failed to get %s irq device\n", __func__,
- DM_DRIVER_GET(arm_gic_v3_its)->name);
+ DM_DRIVER_GET(arm_gic_v3)->name);
return ret;
}
@@ -49,12 +55,13 @@
}
priv->gicd_base = addr;
- addr = dev_read_addr_index(dev, 1);
+ addr = dev_read_addr_size_index(dev, 1, &size);
if (addr == FDT_ADDR_T_NONE) {
pr_err("%s: failed to get GICR address\n", __func__);
return -EINVAL;
}
priv->gicr_base = addr;
+ priv->gicr_length = size;
return 0;
}
@@ -158,13 +165,117 @@
return 0;
}
-static const struct udevice_id gic_v3_its_ids[] = {
+#ifdef CONFIG_ACPIGEN
+/**
+ * acpi_gicv3_fill_madt() - Fill out the body of the MADT
+ *
+ * Write GICD and GICR tables based on collected devicetree data.
+ *
+ * @dev: Device to write ACPI tables for
+ * @ctx: ACPI context to write MADT sub-tables to
+ * Return: 0 if OK
+ */
+static int acpi_gicv3_fill_madt(const struct udevice *dev, struct acpi_ctx *ctx)
+{
+ struct acpi_madt_gicd *gicd;
+ struct acpi_madt_gicr *gicr;
+
+ struct gic_v3_its_priv priv;
+
+ if (gic_v3_its_get_gic_addr(&priv))
+ return -EINVAL;
+
+ gicd = ctx->current;
+ acpi_write_madt_gicd(gicd, dev_seq(dev), priv.gicd_base, 3);
+ acpi_inc(ctx, gicd->length);
+
+ gicr = ctx->current;
+ acpi_write_madt_gicr(gicr, priv.gicr_base, priv.gicr_length);
+ acpi_inc(ctx, gicr->length);
+
+ return 0;
+}
+
+struct acpi_ops gic_v3_acpi_ops = {
+ .fill_madt = acpi_gicv3_fill_madt,
+};
+#endif
+
+static const struct udevice_id gic_v3_ids[] = {
{ .compatible = "arm,gic-v3" },
{}
};
-U_BOOT_DRIVER(arm_gic_v3_its) = {
+static int arm_gic_v3_of_xlate(struct irq *irq, struct ofnode_phandle_args *args)
+{
+ if (args->args_count < 3) {
+ log_debug("Invalid args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ if (args->args[0] == GIC_SPI)
+ irq->id = args->args[1] + 32;
+ else
+ irq->id = args->args[1] + 16;
+
+ irq->flags = args->args[2];
+
+ return 0;
+}
+
+static const struct irq_ops arm_gic_v3_ops = {
+ .of_xlate = arm_gic_v3_of_xlate,
+};
+
+U_BOOT_DRIVER(arm_gic_v3) = {
.name = "gic-v3",
.id = UCLASS_IRQ,
+ .of_match = gic_v3_ids,
+ .ops = &arm_gic_v3_ops,
+ ACPI_OPS_PTR(&gic_v3_acpi_ops)
+};
+
+#ifdef CONFIG_ACPIGEN
+/**
+ * acpi_gic_its_fill_madt() - Fill out the body of the MADT
+ *
+ * Write ITS tables based on collected devicetree data.
+ *
+ * @dev: Device to write ACPI tables for
+ * @ctx: ACPI context to write MADT sub-tables to
+ * Return: 0 if OK
+ */
+static int acpi_gic_its_fill_madt(const struct udevice *dev, struct acpi_ctx *ctx)
+{
+ struct acpi_madt_its *its;
+ fdt_addr_t addr;
+
+ addr = dev_read_addr_index(dev, 0);
+ if (addr == FDT_ADDR_T_NONE) {
+ pr_err("%s: failed to get GIC ITS address\n", __func__);
+ return -EINVAL;
+ }
+
+ its = ctx->current;
+ acpi_write_madt_its(its, dev_seq(dev), addr);
+ acpi_inc(ctx, its->length);
+
+ return 0;
+}
+
+struct acpi_ops gic_v3_its_acpi_ops = {
+ .fill_madt = acpi_gic_its_fill_madt,
+};
+#endif
+
+static const struct udevice_id gic_v3_its_ids[] = {
+ { .compatible = "arm,gic-v3-its" },
+ {}
+};
+
+U_BOOT_DRIVER(arm_gic_v3_its) = {
+ .name = "gic-v3-its",
+ .id = UCLASS_IRQ,
.of_match = gic_v3_its_ids,
+ ACPI_OPS_PTR(&gic_v3_its_acpi_ops)
};
diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
index b3287ce..d9303e8 100644
--- a/arch/arm/mach-bcm283x/Kconfig
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -24,7 +24,13 @@
bool "Broadcom BCM2837 SoC 64-bit support"
depends on ARCH_BCM283X
select BCM2837
+ select DRIVER_GICV2
select ARM64
+ select CPU_ARMV8
+ select ARMV8_MULTIENTRY if GENERATE_ACPI_TABLE
+ select BLOBLIST if GENERATE_ACPI_TABLE
+ select BLOBLIST_ALLOC if GENERATE_ACPI_TABLE
+ select BLOBLIST_TABLES if GENERATE_ACPI_TABLE
config BCM2711
bool "Broadcom BCM2711 SoC support"
@@ -42,11 +48,16 @@
bool "Broadcom BCM2711 SoC 64-bit support"
depends on ARCH_BCM283X
select BCM2711
+ select DRIVER_GICV2
select ARM64
+ select CPU_ARMV8
+ select ARMV8_MULTIENTRY if GENERATE_ACPI_TABLE
+ select BLOBLIST if GENERATE_ACPI_TABLE
+ select BLOBLIST_ALLOC if GENERATE_ACPI_TABLE
+ select BLOBLIST_TABLES if GENERATE_ACPI_TABLE
menu "Broadcom BCM283X family"
depends on ARCH_BCM283X
-
choice
prompt "Broadcom BCM283X board select"
optional
@@ -210,6 +221,9 @@
config SYS_CONFIG_NAME
default "rpi"
+config BLOBLIST_SIZE_RELOC
+ default 0x20000
+
source "board/raspberrypi/rpi/Kconfig"
endmenu
diff --git a/arch/arm/mach-bcm283x/Makefile b/arch/arm/mach-bcm283x/Makefile
index 7cd0688..38e3203 100644
--- a/arch/arm/mach-bcm283x/Makefile
+++ b/arch/arm/mach-bcm283x/Makefile
@@ -4,3 +4,7 @@
obj-$(CONFIG_BCM2835) += lowlevel_init.o
obj-y += init.o reset.o mbox.o msg.o phys2bus.o
+
+ifeq ($(CONFIG_GENERATE_ACPI_TABLE),y)
+obj-$(CONFIG_BCM2711) += bcm2711_acpi.o
+endif
\ No newline at end of file
diff --git a/arch/arm/mach-bcm283x/bcm2711_acpi.c b/arch/arm/mach-bcm283x/bcm2711_acpi.c
new file mode 100644
index 0000000..79b2833
--- /dev/null
+++ b/arch/arm/mach-bcm283x/bcm2711_acpi.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2024 9elements GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ */
+
+#include <string.h>
+#include <tables_csum.h>
+#include <acpi/acpi_table.h>
+#include <asm/acpi_table.h>
+#include <asm/armv8/sec_firmware.h>
+#include <asm/arch/acpi/bcm2711.h>
+#include <dm/uclass.h>
+
+void acpi_fill_fadt(struct acpi_fadt *fadt)
+{
+ fadt->flags = ACPI_FADT_HW_REDUCED_ACPI | ACPI_FADT_LOW_PWR_IDLE_S0;
+
+ if (CONFIG_IS_ENABLED(SEC_FIRMWARE_ARMV8_PSCI) &&
+ sec_firmware_support_psci_version() != PSCI_INVALID_VER)
+ fadt->arm_boot_arch = ACPI_ARM_PSCI_COMPLIANT;
+}
+
+#define L3_ATTRIBUTES (ACPI_PPTT_READ_ALLOC | ACPI_PPTT_WRITE_ALLOC | \
+ (ACPI_PPTT_CACHE_TYPE_UNIFIED << \
+ ACPI_PPTT_CACHE_TYPE_SHIFT))
+#define L3_SIZE 0x100000
+#define L3_SETS 0x400
+#define L3_WAYS 0x10
+
+#define L1D_ATTRIBUTES (ACPI_PPTT_READ_ALLOC | ACPI_PPTT_WRITE_ALLOC | \
+ (ACPI_PPTT_CACHE_TYPE_DATA << \
+ ACPI_PPTT_CACHE_TYPE_SHIFT))
+#define L1D_SIZE 0x8000
+#define L1D_SETS 0x100
+#define L1D_WAYS 2
+
+#define L1I_ATTRIBUTES (ACPI_PPTT_READ_ALLOC | \
+ (ACPI_PPTT_CACHE_TYPE_INSTR << \
+ ACPI_PPTT_CACHE_TYPE_SHIFT))
+#define L1I_SIZE 0xc000
+#define L1I_SETS 0x100
+#define L1I_WAYS 3
+
+static int acpi_write_pptt(struct acpi_ctx *ctx, const struct acpi_writer *entry)
+{
+ struct acpi_table_header *header;
+ int cluster_offset, l3_offset;
+ u32 offsets[2];
+
+ header = ctx->current;
+ ctx->tab_start = ctx->current;
+
+ memset(header, '\0', sizeof(struct acpi_table_header));
+
+ acpi_fill_header(header, "PPTT");
+ header->revision = acpi_get_table_revision(ACPITAB_PPTT);
+ acpi_inc(ctx, sizeof(*header));
+
+ l3_offset = acpi_pptt_add_cache(ctx, ACPI_PPTT_ALL_VALID, 0, L3_SIZE,
+ L3_SETS, L3_WAYS, L3_ATTRIBUTES, 64);
+
+ cluster_offset = acpi_pptt_add_proc(ctx, ACPI_PPTT_PHYSICAL_PACKAGE |
+ ACPI_PPTT_CHILDREN_IDENTICAL,
+ 0, 0, 1, &l3_offset);
+
+ offsets[0] = acpi_pptt_add_cache(ctx, ACPI_PPTT_ALL_VALID, 0, L1D_SIZE,
+ L1D_SETS, L1D_WAYS, L1D_ATTRIBUTES, 64);
+
+ offsets[1] = acpi_pptt_add_cache(ctx, ACPI_PPTT_ALL_BUT_WRITE_POL, 0,
+ L1I_SIZE, L1I_SETS, L1I_WAYS,
+ L1I_ATTRIBUTES, 64);
+
+ for (int i = 0; i < uclass_id_count(UCLASS_CPU); i++) {
+ acpi_pptt_add_proc(ctx, ACPI_PPTT_CHILDREN_IDENTICAL |
+ ACPI_PPTT_NODE_IS_LEAF |
+ ACPI_PPTT_PROC_ID_VALID,
+ cluster_offset, i, 2, offsets);
+ }
+
+ header->length = ctx->current - ctx->tab_start;
+ header->checksum = table_compute_checksum(header, header->length);
+
+ acpi_inc(ctx, header->length);
+ acpi_add_table(ctx, header);
+
+ return 0;
+};
+
+ACPI_WRITER(5pptt, "PPTT", acpi_write_pptt, 0);
+
+static int rpi_write_gtdt(struct acpi_ctx *ctx, const struct acpi_writer *entry)
+{
+ struct acpi_table_header *header;
+ struct acpi_gtdt *gtdt;
+
+ gtdt = ctx->current;
+ header = >dt->header;
+
+ memset(gtdt, '\0', sizeof(struct acpi_gtdt));
+
+ acpi_fill_header(header, "GTDT");
+ header->length = sizeof(struct acpi_gtdt);
+ header->revision = acpi_get_table_revision(ACPITAB_GTDT);
+
+ gtdt->cnt_ctrl_base = BCM2711_ARM_LOCAL_BASE_ADDRESS + 0x1c;
+ gtdt->sec_el1_gsiv = 29;
+ gtdt->sec_el1_flags = GTDT_FLAG_INT_ACTIVE_LOW;
+ gtdt->el1_gsiv = 30;
+ gtdt->el1_flags = GTDT_FLAG_INT_ACTIVE_LOW;
+ gtdt->virt_el1_gsiv = 27;
+ gtdt->virt_el1_flags = GTDT_FLAG_INT_ACTIVE_LOW;
+ gtdt->el2_gsiv = 26;
+ gtdt->el2_flags = GTDT_FLAG_INT_ACTIVE_LOW;
+ gtdt->cnt_read_base = 0xffffffffffffffff;
+
+ header->checksum = table_compute_checksum(header, header->length);
+
+ acpi_add_table(ctx, gtdt);
+
+ acpi_inc(ctx, sizeof(struct acpi_gtdt));
+
+ return 0;
+};
+
+ACPI_WRITER(5gtdt, "GTDT", rpi_write_gtdt, 0);
diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h
new file mode 100644
index 0000000..a86875b
--- /dev/null
+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: BSD-2-Clause-Patent */
+/**
+ *
+ * Copyright (c) 2019, Jeremy Linton
+ * Copyright (c) 2019, Pete Batard <pete@akeo.ie>.
+ *
+ **/
+
+#ifndef BCM2711_H__
+#define BCM2711_H__
+
+#define BCM2711_SOC_REGISTERS 0xfc000000
+#define BCM2711_SOC_REGISTER_LENGTH 0x02000000
+
+#define BCM2711_ARM_LOCAL_REGISTERS 0xfe000000
+#define BCM2711_ARM_LOCAL_REGISTER_LENGTH 0x02000000
+
+/* arm local addresses */
+#define BCM2711_ARMC_OFFSET 0x0000b000
+#define BCM2711_ARMC_BASE_ADDRESS (BCM2711_ARM_LOCAL_REGISTERS + BCM2711_ARMC_OFFSET)
+#define BCM2711_ARMC_LENGTH 0x00000400
+
+#define BCM2711_ARM_LOCAL_OFFSET 0x01800000
+#define BCM2711_ARM_LOCAL_BASE_ADDRESS (BCM2711_ARM_LOCAL_REGISTERS + BCM2711_ARM_LOCAL_OFFSET)
+#define BCM2711_ARM_LOCAL_LENGTH 0x00000080
+
+#define BCM2711_GIC400_OFFSET 0x01840000
+#define BCM2711_GIC400_BASE_ADDRESS (BCM2711_ARM_LOCAL_REGISTERS + BCM2711_GIC400_OFFSET)
+#define BCM2711_GIC400_LENGTH 0x00008000
+
+/* Generic PCI addresses */
+#define PCIE_TOP_OF_MEM_WIN 0xf8000000
+#define PCIE_CPU_MMIO_WINDOW 0x600000000
+#define PCIE_BRIDGE_MMIO_LEN 0x3ffffff
+
+/* PCI root bridge control registers location */
+#define PCIE_REG_BASE 0xfd500000
+#define PCIE_REG_LIMIT 0x9310
+
+/* PCI root bridge control registers */
+#define BRCM_PCIE_CAP_REGS 0x00ac
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
+#define VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN 0x0
+#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
+#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
+#define LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
+
+#define PCIE_RC_DL_MDIO_ADDR 0x1100
+#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
+#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
+
+#define PCIE_MISC_MISC_CTRL 0x4008
+#define MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
+#define MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
+#define MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
+#define MISC_CTRL_MAX_BURST_SIZE_128 0x0
+#define MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
+
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
+#define PCIE_MEM_WIN0_LO(win) \
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)
+
+#define PCIE_MEM_WIN0_HI(win) \
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4)
+#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
+#define RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
+#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
+#define RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
+#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
+#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
+#define RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
+#define PCIE_MISC_PCIE_STATUS 0x4068
+#define STATUS_PCIE_PORT_MASK 0x80
+#define STATUS_PCIE_PORT_SHIFT 7
+#define STATUS_PCIE_DL_ACTIVE_MASK 0x20
+#define STATUS_PCIE_DL_ACTIVE_SHIFT 5
+#define STATUS_PCIE_PHYLINKUP_MASK 0x10
+#define STATUS_PCIE_PHYLINKUP_SHIFT 4
+#define PCIE_MISC_REVISION 0x406c
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
+#define MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
+#define MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
+#define MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT 12
+#define PCIE_MEM_WIN0_BASE_LIMIT(win) \
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4)
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
+#define MEM_WIN0_BASE_HI_BASE_MASK 0xff
+#define PCIE_MEM_WIN0_BASE_HI(win) \
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8)
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
+#define PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
+#define PCIE_MEM_WIN0_LIMIT_HI(win) \
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
+
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
+#define PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
+
+#define PCIE_INTR2_CPU_STATUS 0x4300
+#define PCIE_INTR2_CPU_SET 0x4304
+#define PCIE_INTR2_CPU_CLR 0x4308
+#define PCIE_INTR2_CPU_MASK_STATUS 0x430c
+#define PCIE_INTR2_CPU_MASK_SET 0x4310
+#define PCIE_INTR2_CPU_MASK_CLR 0x4314
+
+#define PCIE_MSI_INTR2_CLR 0x4508
+#define PCIE_MSI_INTR2_MASK_SET 0x4510
+
+#define PCIE_RGR1_SW_INIT_1 0x9210
+#define PCIE_EXT_CFG_INDEX 0x9000
+/* A small window pointing at the ECAM of the device selected by CFG_INDEX */
+#define PCIE_EXT_CFG_DATA 0x8000
+
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
+#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
+
+#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
+#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
+#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
+#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
+#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x7c00000
+#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x1f
+#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
+
+#define PCIE_RGR1_SW_INIT_1_INIT_MASK 0x2
+#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
+
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
+
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
+
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_MASK_BITS 0xc
+
+#define PCIE_MISC_REVISION_MAJMIN_MASK 0xffff
+
+#define BURST_SIZE_128 0
+#define BURST_SIZE_256 1
+#define BURST_SIZE_512 2
+
+#define BCM2711_THERM_SENSOR_OFFSET 0x015d2200
+#define BCM2711_THERM_SENSOR_BASE_ADDRESS (BCM2711_SOC_REGISTERS + BCM2711_THERM_SENSOR_OFFSET)
+#define BCM2711_THERM_SENSOR_LENGTH 0x00000008
+
+#define BCM2711_GENET_BASE_OFFSET 0x01580000
+#define BCM2711_GENET_BASE_ADDRESS (BCM2711_SOC_REGISTERS + BCM2711_GENET_BASE_OFFSET)
+#define BCM2711_GENET_LENGTH 0x10000
+
+#endif /* BCM2711_H__ */
diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836.h
new file mode 100644
index 0000000..64cec36
--- /dev/null
+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836.h
@@ -0,0 +1,127 @@
+/* SPDX-License-Identifier: BSD-2-Clause-Patent */
+/**
+ *
+ * Copyright (c) 2019, ARM Limited. All rights reserved.
+ * Copyright (c) 2017, Andrei Warkentin <andrey.warkentin@gmail.com>
+ * Copyright (c) 2016, Linaro Limited. All rights reserved.
+ *
+ **/
+
+#ifndef __BCM2836_H__
+#define __BCM2836_H__
+
+/*
+ * Both "core" and SoC perpherals (1M each).
+ */
+#define BCM2836_SOC_REGISTERS 0xfe000000
+#define BCM2836_SOC_REGISTER_LENGTH 0x02000000
+
+/*
+ * Offset between the CPU's view and the VC's view of system memory.
+ */
+#define BCM2836_DMA_DEVICE_OFFSET 0xc0000000
+
+/* watchdog constants */
+#define BCM2836_WDOG_OFFSET 0x00100000
+#define BCM2836_WDOG_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_WDOG_OFFSET)
+#define BCM2836_WDOG_PASSWORD 0x5a000000
+#define BCM2836_WDOG_RSTC_OFFSET 0x0000001c
+#define BCM2836_WDOG_WDOG_OFFSET 0x00000024
+#define BCM2836_WDOG_RSTC_WRCFG_MASK 0x00000030
+#define BCM2836_WDOG_RSTC_WRCFG_FULL_RESET 0x00000020
+
+/* clock manager constants */
+#define BCM2836_CM_OFFSET 0x00101000
+#define BCM2836_CM_BASE (BCM2836_SOC_REGISTERS + BCM2836_CM_OFFSET)
+#define BCM2836_CM_GEN_CLOCK_CONTROL 0x0000
+#define BCM2836_CM_GEN_CLOCK_DIVISOR 0x0004
+#define BCM2836_CM_VPU_CLOCK_CONTROL 0x0008
+#define BCM2836_CM_VPU_CLOCK_DIVISOR 0x000c
+#define BCM2836_CM_SYSTEM_CLOCK_CONTROL 0x0010
+#define BCM2836_CM_SYSTEM_CLOCK_DIVISOR 0x0014
+#define BCM2836_CM_H264_CLOCK_CONTROL 0x0028
+#define BCM2836_CM_H264_CLOCK_DIVISOR 0x002c
+#define BCM2836_CM_PWM_CLOCK_CONTROL 0x00a0
+#define BCM2836_CM_PWM_CLOCK_DIVISOR 0x00a4
+#define BCM2836_CM_UART_CLOCK_CONTROL 0x00f0
+#define BCM2836_CM_UART_CLOCK_DIVISOR 0x00f4
+#define BCM2836_CM_SDC_CLOCK_CONTROL 0x01a8
+#define BCM2836_CM_SDC_CLOCK_DIVISOR 0x01ac
+#define BCM2836_CM_ARM_CLOCK_CONTROL 0x01b0
+#define BCM2836_CM_ARM_CLOCK_DIVISOR 0x01b4
+#define BCM2836_CM_EMMC_CLOCK_CONTROL 0x01c0
+#define BCM2836_CM_EMMC_CLOCK_DIVISOR 0x01c4
+
+/* mailbox interface constants */
+#define BCM2836_MBOX_OFFSET 0x0000b880
+#define BCM2836_MBOX_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_MBOX_OFFSET)
+#define BCM2836_MBOX_LENGTH 0x00000024
+#define BCM2836_MBOX_READ_OFFSET 0x00000000
+#define BCM2836_MBOX_STATUS_OFFSET 0x00000018
+#define BCM2836_MBOX_CONFIG_OFFSET 0x0000001c
+#define BCM2836_MBOX_WRITE_OFFSET 0x00000020
+
+#define BCM2836_MBOX_STATUS_FULL 0x1f
+#define BCM2836_MBOX_STATUS_EMPTY 0x1e
+
+#define BCM2836_MBOX_NUM_CHANNELS 16
+
+/* interrupt controller constants */
+#define BCM2836_INTC_TIMER_CONTROL_OFFSET 0x00000040
+#define BCM2836_INTC_TIMER_PENDING_OFFSET 0x00000060
+
+/* usb constants */
+#define BCM2836_USB_OFFSET 0x00980000
+#define BCM2836_USB_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_USB_OFFSET)
+#define BCM2836_USB_LENGTH 0x00010000
+
+/* serial based protocol constants */
+#define BCM2836_PL011_UART_OFFSET 0x00201000
+#define BCM2836_PL011_UART_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PL011_UART_OFFSET)
+#define BCM2836_PL011_UART_LENGTH 0x00001000
+
+#define BCM2836_MINI_UART_OFFSET 0x00215000
+#define BCM2836_MINI_UART_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_MINI_UART_OFFSET)
+#define BCM2836_MINI_UART_LENGTH 0x00000070
+
+#define BCM2836_I2C0_OFFSET 0x00205000
+#define BCM2836_I2C0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_I2C0_OFFSET)
+#define BCM2836_I2C0_LENGTH 0x00000020
+
+#define BCM2836_I2C1_OFFSET 0x00804000
+#define BCM2836_I2C1_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_I2C1_OFFSET)
+#define BCM2836_I2C1_LENGTH 0x00000020
+
+#define BCM2836_I2C2_OFFSET 0x00805000
+#define BCM2836_I2C2_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_I2C2_OFFSET)
+#define BCM2836_I2C2_LENGTH 0x00000020
+
+#define BCM2836_SPI0_OFFSET 0x00204000
+#define BCM2836_SPI0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SPI0_OFFSET)
+#define BCM2836_SPI0_LENGTH 0x00000020
+
+#define BCM2836_SPI1_OFFSET 0x00215080
+#define BCM2836_SPI1_LENGTH 0x00000040
+#define BCM2836_SPI1_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SPI1_OFFSET)
+
+#define BCM2836_SPI2_OFFSET 0x002150C0
+#define BCM2836_SPI2_LENGTH 0x00000040
+#define BCM2836_SPI2_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SPI2_OFFSET)
+
+#define BCM2836_SYSTEM_TIMER_OFFSET 0x00003000
+#define BCM2836_SYSTEM_TIMER_LENGTH 0x00000020
+#define BCM2836_SYSTEM_TIMER_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SYSTEM_TIMER_OFFSET)
+
+/* dma constants */
+#define BCM2836_DMA0_OFFSET 0x00007000
+#define BCM2836_DMA0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_DMA0_OFFSET)
+
+#define BCM2836_DMA15_OFFSET 0x00E05000
+#define BCM2836_DMA15_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_DMA15_OFFSET)
+
+#define BCM2836_DMA_CTRL_OFFSET 0x00007FE0
+#define BCM2836_DMA_CTRL_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_DMA_CTRL_OFFSET)
+
+#define BCM2836_DMA_CHANNEL_LENGTH 0x00000100
+
+#endif /*__BCM2836_H__ */
diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpio.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpio.h
new file mode 100644
index 0000000..c5b858b
--- /dev/null
+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpio.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: BSD-2-Clause-Patent */
+/**
+ *
+ * Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ * Copyright (c) 2018, Andrei Warkentin <andrey.warkentin@gmail.com>
+ * Copyright (c) Microsoft Corporation. All rights reserved.
+ *
+ **/
+
+#include <asm/arch/acpi/bcm2836.h>
+
+#ifndef __BCM2836_GPIO_H__
+#define __BCM2836_GPIO_H__
+
+#define GPIO_OFFSET 0x00200000
+#define GPIO_BASE_ADDRESS (BCM2836_SOC_REGISTERS + GPIO_OFFSET)
+#define GPIO_LENGTH 0x000000B4
+
+#endif /* __BCM2836_GPIO_H__ */
diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpu.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpu.h
new file mode 100644
index 0000000..5857d75
--- /dev/null
+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpu.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: BSD-2-Clause-Patent */
+/**
+ *
+ * Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ *
+ **/
+
+#include <asm/arch/acpi/bcm2836.h>
+
+#ifndef __BCM2836_GPU_H__
+#define __BCM2836_GPU_H__
+
+/* VideoCore constants */
+
+#define BCM2836_VCHIQ_OFFSET 0x0000B840
+#define BCM2836_VCHIQ_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_VCHIQ_OFFSET)
+#define BCM2836_VCHIQ_LENGTH 0x00000010
+
+#define BCM2836_V3D_BUS_OFFSET 0x00C00000
+#define BCM2836_V3D_BUS_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_V3D_BUS_OFFSET)
+#define BCM2836_V3D_BUS_LENGTH 0x00001000
+
+#define BCM2836_HVS_OFFSET 0x00400000
+#define BCM2836_HVS_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_HVS_OFFSET)
+#define BCM2836_HVS_LENGTH 0x00006000
+
+#define BCM2836_PV0_OFFSET 0x00206000
+#define BCM2836_PV0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PV0_OFFSET)
+#define BCM2836_PV0_LENGTH 0x00000100
+
+#define BCM2836_PV1_OFFSET 0x00207000
+#define BCM2836_PV1_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PV1_OFFSET)
+#define BCM2836_PV1_LENGTH 0x00000100
+
+#define BCM2836_PV2_OFFSET 0x00807000
+#define BCM2836_PV2_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PV2_OFFSET)
+#define BCM2836_PV2_LENGTH 0x00000100
+
+#define BCM2836_HDMI0_OFFSET 0x00902000
+#define BCM2836_HDMI0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_HDMI0_OFFSET)
+#define BCM2836_HDMI0_LENGTH 0x00000600
+
+#define BCM2836_HDMI1_OFFSET 0x00808000
+#define BCM2836_HDMI1_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_HDMI1_OFFSET)
+#define BCM2836_HDMI1_LENGTH 0x00000100
+
+#endif /* __BCM2836_MISC_H__ */
diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_pwm.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_pwm.h
new file mode 100644
index 0000000..78a8486
--- /dev/null
+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_pwm.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: BSD-2-Clause-Patent */
+/**
+ *
+ * Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ *
+ **/
+
+#include <asm/arch/acpi/bcm2836.h>
+
+#ifndef __BCM2836_PWM_H__
+#define __BCM2836_PWM_H__
+
+/* PWM controller constants */
+
+#define BCM2836_PWM_DMA_OFFSET 0x00007B00
+#define BCM2836_PWM_DMA_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PWM_DMA_OFFSET)
+#define BCM2836_PWM_DMA_LENGTH 0x00000100
+
+#define BCM2836_PWM_CLK_OFFSET 0x001010A0
+#define BCM2836_PWM_CLK_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PWM_CLK_OFFSET)
+#define BCM2836_PWM_CLK_LENGTH 0x00000008
+
+#define BCM2836_PWM_CTRL_OFFSET 0x0020C000
+#define BCM2836_PWM_CTRL_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PWM_CTRL_OFFSET)
+#define BCM2836_PWM_CTRL_LENGTH 0x00000028
+
+#define BCM2836_PWM_BUS_BASE_ADDRESS 0x7E20C000
+#define BCM2836_PWM_BUS_LENGTH 0x00000028
+
+#define BCM2836_PWM_CTRL_UNCACHED_BASE_ADDRESS 0xFF20C000
+#define BCM2836_PWM_CTRL_UNCACHED_LENGTH 0x00000028
+
+#endif /* __BCM2836_PWM_H__ */
diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdhost.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdhost.h
new file mode 100644
index 0000000..9b1afe8
--- /dev/null
+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdhost.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: BSD-2-Clause-Patent */
+/**
+ *
+ * Copyright (c) 2017, Andrei Warkentin <andrey.warkentin@gmail.com>
+ * Copyright (c) Microsoft Corporation. All rights reserved.
+ *
+ **/
+
+#include <asm/arch/acpi/bcm2836.h>
+
+#ifndef __BCM2836_SDHOST_H__
+#define __BCM2836_SDHOST_H__
+
+#define SDHOST_OFFSET 0x00202000
+#define SDHOST_BASE_ADDRESS (BCM2836_SOC_REGISTERS + SDHOST_OFFSET)
+#define SDHOST_LENGTH 0x00000100
+
+#endif /*__BCM2836_SDHOST_H__ */
diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdio.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdio.h
new file mode 100644
index 0000000..48d073d
--- /dev/null
+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdio.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: BSD-2-Clause-Patent */
+/**
+ *
+ * Copyright (c) Microsoft Corporation. All rights reserved.
+ *
+ **/
+
+#include <asm/arch/acpi/bcm2836.h>
+
+#ifndef __BCM2836_SDIO_H__
+#define __BCM2836_SDIO_H__
+
+// MMC/SD/SDIO1 register definitions.
+#define MMCHS1_OFFSET 0x00300000
+#define MMCHS2_OFFSET 0x00340000
+#define MMCHS1_BASE (BCM2836_SOC_REGISTERS + MMCHS1_OFFSET)
+#define MMCHS2_BASE (BCM2836_SOC_REGISTERS + MMCHS2_OFFSET)
+#define MMCHS1_LENGTH 0x00000100
+#define MMCHS2_LENGTH 0x00000100
+
+#endif /* __BCM2836_SDIO_H__ */
diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index 1b45970..7a1de22 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -50,7 +50,7 @@
}, {
.virt = 0xfc000000UL,
.phys = 0xfc000000UL,
- .size = 0x03800000UL,
+ .size = 0x04000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 9d1fabe..b254a50 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -228,6 +228,13 @@
select SPL_CRYPTO if SPL
imply OF_UPSTREAM
+config TARGET_IMX8MP_NAVQP
+ bool "Emcraft Systems i.MX8M Plus NavQ+ board"
+ select IMX8MP
+ select IMX8M_LPDDR4
+ select SUPPORT_SPL
+ imply OF_UPSTREAM
+
config TARGET_IMX8MP_VENICE
bool "Support Gateworks Venice iMX8M Plus module"
select IMX8MP
@@ -358,6 +365,7 @@
source "board/data_modul/imx8mm_edm_sbc/Kconfig"
source "board/data_modul/imx8mp_edm_sbc/Kconfig"
source "board/dhelectronics/dh_imx8mp/Kconfig"
+source "board/emcraft/imx8mp_navqp/Kconfig"
source "board/engicam/imx8mm/Kconfig"
source "board/engicam/imx8mp/Kconfig"
source "board/freescale/imx8mq_evk/Kconfig"
diff --git a/arch/arm/mach-qemu/Kconfig b/arch/arm/mach-qemu/Kconfig
index 186c358..9c06c6a 100644
--- a/arch/arm/mach-qemu/Kconfig
+++ b/arch/arm/mach-qemu/Kconfig
@@ -3,12 +3,6 @@
config SYS_VENDOR
default "emulation"
-config SYS_BOARD
- default "qemu-arm"
-
-config SYS_CONFIG_NAME
- default "qemu-arm"
-
choice
prompt "QEMU ARM architecture"
default TARGET_QEMU_ARM_64BIT
@@ -25,6 +19,36 @@
select ARM64
select BOARD_LATE_INIT
+config TARGET_QEMU_ARM_SBSA
+ bool "SBSA Reference"
+ select ARM64
+ select BINMAN
+ select BOARD_LATE_INIT
+ select ENABLE_ARM_SOC_BOOT0_HOOK
+ select MISC_INIT_R
endchoice
+if TARGET_QEMU_ARM_32BIT || TARGET_QEMU_ARM_64BIT
+
+config SYS_BOARD
+ default "qemu-arm"
+
+config SYS_CONFIG_NAME
+ default "qemu-arm"
+
+endif
+
+if TARGET_QEMU_ARM_SBSA
+
+config SYS_BOARD
+ default "qemu-sbsa"
+
+config SYS_CONFIG_NAME
+ default "qemu-sbsa"
+
+config SYS_SOC
+ default "qemu-sbsa"
+
+endif
+
endif
diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h
index 89a2ac2..00699c4 100644
--- a/arch/mips/include/asm/system.h
+++ b/arch/mips/include/asm/system.h
@@ -286,20 +286,6 @@
/* 1MB granularity */
#define MMU_SECTION_SHIFT 20
#define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT)
-
-/**
- * noncached_init() - Initialize non-cached memory region
- *
- * Initialize non-cached memory area. This memory region will be typically
- * located right below the malloc() area and be accessed from KSEG1.
- *
- * It is called during the generic post-relocation init sequence.
- *
- * Return: 0 if OK
- */
-int noncached_init(void);
-
-phys_addr_t noncached_alloc(size_t size, size_t align);
#endif /* CONFIG_SYS_NONCACHED_MEMORY */
#endif /* _ASM_SYSTEM_H */
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index fa37102..043d963 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -21,7 +21,7 @@
bool "Support RISC-V cores on OpenPiton SoC"
config TARGET_QEMU_VIRT
- bool "Support QEMU Virt Board"
+ bool "Support QEMU Virt & RVVM Boards"
select BOARD_LATE_INIT
config TARGET_SIFIVE_UNLEASHED
@@ -319,6 +319,10 @@
help
Adds "A" to the ISA string passed to the compiler.
+config RISCV_ISA_ZICBOM
+ bool "Zicbom support"
+ depends on !SYS_DISABLE_DCACHE_OPS
+
config DMA_ADDR_T_64BIT
bool
default y if 64BIT
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index f3dfd75..bf32ead 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -1,7 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb
-dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb
dtb-$(CONFIG_TARGET_MILKV_DUO) += cv1800b-milkv-duo.dtb
dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
diff --git a/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi
deleted file mode 100644
index 1069134..0000000
--- a/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi
+++ /dev/null
@@ -1,71 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright (c) 2020-2021 Microchip Technology Inc */
-
-/ {
- compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
- "microchip,mpfs";
-
- core_pwm0: pwm@40000000 {
- compatible = "microchip,corepwm-rtl-v4";
- reg = <0x0 0x40000000 0x0 0xF0>;
- microchip,sync-update-mask = /bits/ 32 <0>;
- #pwm-cells = <3>;
- clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>;
- status = "disabled";
- };
-
- i2c2: i2c@40000200 {
- compatible = "microchip,corei2c-rtl-v7";
- reg = <0x0 0x40000200 0x0 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>;
- interrupt-parent = <&plic>;
- interrupts = <122>;
- clock-frequency = <100000>;
- status = "disabled";
- };
-
- pcie: pcie@3000000000 {
- compatible = "microchip,pcie-host-1.0";
- #address-cells = <0x3>;
- #interrupt-cells = <0x1>;
- #size-cells = <0x2>;
- device_type = "pci";
- reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
- reg-names = "cfg", "apb";
- bus-range = <0x0 0x7f>;
- interrupt-parent = <&plic>;
- interrupts = <119>;
- interrupt-map = <0 0 0 1 &pcie_intc 0>,
- <0 0 0 2 &pcie_intc 1>,
- <0 0 0 3 &pcie_intc 2>,
- <0 0 0 4 &pcie_intc 3>;
- interrupt-map-mask = <0 0 0 7>;
- clocks = <&ccc_nw CLK_CCC_PLL0_OUT1>, <&ccc_nw CLK_CCC_PLL0_OUT3>;
- clock-names = "fic1", "fic3";
- ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>;
- dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>;
- msi-parent = <&pcie>;
- msi-controller;
- status = "disabled";
- pcie_intc: interrupt-controller {
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-controller;
- };
- };
-
- refclk_ccc: cccrefclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- };
-};
-
-&ccc_nw {
- clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
- <&refclk_ccc>, <&refclk_ccc>;
- clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
- "dll0_ref", "dll1_ref";
- status = "okay";
-};
diff --git a/arch/riscv/dts/mpfs-icicle-kit-u-boot.dtsi b/arch/riscv/dts/mpfs-icicle-kit-u-boot.dtsi
deleted file mode 100644
index f60283f..0000000
--- a/arch/riscv/dts/mpfs-icicle-kit-u-boot.dtsi
+++ /dev/null
@@ -1,14 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2020 Microchip Technology Inc.
- * Padmarao Begari <padmarao.begari@microchip.com>
- */
-
-/ {
- aliases {
- cpu1 = &cpu1;
- cpu2 = &cpu2;
- cpu3 = &cpu3;
- cpu4 = &cpu4;
- };
-};
diff --git a/arch/riscv/dts/mpfs-icicle-kit.dts b/arch/riscv/dts/mpfs-icicle-kit.dts
deleted file mode 100644
index 8aa5fb1..0000000
--- a/arch/riscv/dts/mpfs-icicle-kit.dts
+++ /dev/null
@@ -1,208 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2021-2022 Microchip Technology Inc.
- * Padmarao Begari <padmarao.begari@microchip.com>
- */
-
-/dts-v1/;
-
-#include "mpfs.dtsi"
-#include "mpfs-icicle-kit-fabric.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-
-/* Clock frequency (in Hz) of the rtcclk */
-#define RTCCLK_FREQ 1000000
-
-/ {
- model = "Microchip PolarFire-SoC Icicle Kit";
- compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
- "microchip,mpfs";
-
- aliases {
- ethernet0 = &mac1;
- serial0 = &mmuart0;
- serial1 = &mmuart1;
- serial2 = &mmuart2;
- serial3 = &mmuart3;
- serial4 = &mmuart4;
- };
-
- chosen {
- stdout-path = "serial1:115200n8";
- };
-
- cpus {
- timebase-frequency = <RTCCLK_FREQ>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-1 {
- gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_RED>;
- label = "led1";
- };
-
- led-2 {
- gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_RED>;
- label = "led2";
- };
-
- led-3 {
- gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_AMBER>;
- label = "led3";
- };
-
- led-4 {
- gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_AMBER>;
- label = "led4";
- };
- };
-
- ddrc_cache_lo: memory@80000000 {
- device_type = "memory";
- reg = <0x0 0x80000000 0x0 0x40000000>;
- status = "okay";
- };
-
- ddrc_cache_hi: memory@1040000000 {
- device_type = "memory";
- reg = <0x10 0x40000000 0x0 0x40000000>;
- status = "okay";
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- hss_payload: region@BFC00000 {
- reg = <0x0 0xBFC00000 0x0 0x400000>;
- no-map;
- };
- };
-};
-
-&core_pwm0 {
- status = "okay";
-};
-
-&gpio2 {
- interrupts = <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>;
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-};
-
-&i2c1 {
- status = "okay";
-};
-
-&i2c2 {
- status = "okay";
-};
-
-&mac0 {
- phy-mode = "sgmii";
- phy-handle = <&phy0>;
- status = "enabled";
-};
-
-&mac1 {
- phy-mode = "sgmii";
- phy-handle = <&phy1>;
- status = "okay";
-
- phy1: ethernet-phy@9 {
- reg = <9>;
- };
-
- phy0: ethernet-phy@8 {
- reg = <8>;
- };
-};
-
-&mbox {
- status = "okay";
-};
-
-&mmc {
- bus-width = <4>;
- disable-wp;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- status = "okay";
-};
-
-&mmuart1 {
- status = "okay";
-};
-
-&mmuart2 {
- status = "okay";
-};
-
-&mmuart3 {
- status = "okay";
-};
-
-&mmuart4 {
- status = "okay";
-};
-
-&pcie {
- status = "okay";
-};
-
-&qspi {
- status = "okay";
-};
-
-&refclk {
- clock-frequency = <125000000>;
-};
-
-&refclk_ccc {
- clock-frequency = <50000000>;
-};
-
-&rtc {
- status = "okay";
-};
-
-&spi0 {
- status = "okay";
-};
-
-&spi1 {
- status = "okay";
-};
-
-&syscontroller {
- status = "okay";
-};
-
-&usb {
- status = "okay";
- dr_mode = "host";
-};
diff --git a/arch/riscv/dts/mpfs.dtsi b/arch/riscv/dts/mpfs.dtsi
deleted file mode 100644
index 6012a28..0000000
--- a/arch/riscv/dts/mpfs.dtsi
+++ /dev/null
@@ -1,511 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/* Copyright (c) 2020-2021 Microchip Technology Inc */
-
-#include "dt-bindings/clock/microchip-mpfs-clock.h"
-
-/ {
- #address-cells = <2>;
- #size-cells = <2>;
- model = "Microchip PolarFire SoC";
- compatible = "microchip,mpfs";
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- compatible = "sifive,e51", "sifive,rocket0", "riscv";
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <128>;
- i-cache-size = <16384>;
- reg = <0>;
- riscv,isa = "rv64imac";
- clocks = <&clkcfg CLK_CPU>;
- status = "disabled";
-
- cpu0_intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
-
- cpu1: cpu@1 {
- compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <32>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <64>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <32>;
- mmu-type = "riscv,sv39";
- reg = <1>;
- riscv,isa = "rv64imafdc";
- clocks = <&clkcfg CLK_CPU>;
- tlb-split;
- next-level-cache = <&cctrllr>;
- status = "okay";
-
- cpu1_intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
-
- cpu2: cpu@2 {
- compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <32>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <64>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <32>;
- mmu-type = "riscv,sv39";
- reg = <2>;
- riscv,isa = "rv64imafdc";
- clocks = <&clkcfg CLK_CPU>;
- tlb-split;
- next-level-cache = <&cctrllr>;
- status = "okay";
-
- cpu2_intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
-
- cpu3: cpu@3 {
- compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <32>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <64>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <32>;
- mmu-type = "riscv,sv39";
- reg = <3>;
- riscv,isa = "rv64imafdc";
- clocks = <&clkcfg CLK_CPU>;
- tlb-split;
- next-level-cache = <&cctrllr>;
- status = "okay";
-
- cpu3_intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
-
- cpu4: cpu@4 {
- compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <32>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <64>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <32>;
- mmu-type = "riscv,sv39";
- reg = <4>;
- riscv,isa = "rv64imafdc";
- clocks = <&clkcfg CLK_CPU>;
- tlb-split;
- next-level-cache = <&cctrllr>;
- status = "okay";
- cpu4_intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
-
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&cpu0>;
- };
-
- core1 {
- cpu = <&cpu1>;
- };
-
- core2 {
- cpu = <&cpu2>;
- };
-
- core3 {
- cpu = <&cpu3>;
- };
-
- core4 {
- cpu = <&cpu4>;
- };
- };
- };
- };
-
- refclk: mssrefclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- };
-
- syscontroller: syscontroller {
- compatible = "microchip,mpfs-sys-controller";
- mboxes = <&mbox 0>;
- };
-
- soc {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "simple-bus";
- ranges;
-
- cctrllr: cache-controller@2010000 {
- compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache";
- reg = <0x0 0x2010000 0x0 0x1000>;
- cache-block-size = <64>;
- cache-level = <2>;
- cache-sets = <1024>;
- cache-size = <2097152>;
- cache-unified;
- interrupt-parent = <&plic>;
- interrupts = <1>, <3>, <4>, <2>;
- };
-
- clint: clint@2000000 {
- compatible = "sifive,fu540-c000-clint", "sifive,clint0";
- reg = <0x0 0x2000000 0x0 0xC000>;
- interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
- <&cpu1_intc 3>, <&cpu1_intc 7>,
- <&cpu2_intc 3>, <&cpu2_intc 7>,
- <&cpu3_intc 3>, <&cpu3_intc 7>,
- <&cpu4_intc 3>, <&cpu4_intc 7>;
- };
-
- plic: interrupt-controller@c000000 {
- compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
- reg = <0x0 0xc000000 0x0 0x4000000>;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-controller;
- interrupts-extended = <&cpu0_intc 11>,
- <&cpu1_intc 11>, <&cpu1_intc 9>,
- <&cpu2_intc 11>, <&cpu2_intc 9>,
- <&cpu3_intc 11>, <&cpu3_intc 9>,
- <&cpu4_intc 11>, <&cpu4_intc 9>;
- riscv,ndev = <186>;
- };
-
- pdma: dma-controller@3000000 {
- compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
- reg = <0x0 0x3000000 0x0 0x8000>;
- interrupt-parent = <&plic>;
- interrupts = <5 6>, <7 8>, <9 10>, <11 12>;
- dma-channels = <4>;
- #dma-cells = <1>;
- };
-
- clkcfg: clkcfg@20002000 {
- compatible = "microchip,mpfs-clkcfg";
- reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
- clocks = <&refclk>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- ccc_se: clock-controller@38010000 {
- compatible = "microchip,mpfs-ccc";
- reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>,
- <0x0 0x39010000 0x0 0x1000>, <0x0 0x39020000 0x0 0x1000>;
- #clock-cells = <1>;
- status = "disabled";
- };
-
- ccc_ne: clock-controller@38040000 {
- compatible = "microchip,mpfs-ccc";
- reg = <0x0 0x38040000 0x0 0x1000>, <0x0 0x38080000 0x0 0x1000>,
- <0x0 0x39040000 0x0 0x1000>, <0x0 0x39080000 0x0 0x1000>;
- #clock-cells = <1>;
- status = "disabled";
- };
-
- ccc_nw: clock-controller@38100000 {
- compatible = "microchip,mpfs-ccc";
- reg = <0x0 0x38100000 0x0 0x1000>, <0x0 0x38200000 0x0 0x1000>,
- <0x0 0x39100000 0x0 0x1000>, <0x0 0x39200000 0x0 0x1000>;
- #clock-cells = <1>;
- status = "disabled";
- };
-
- ccc_sw: clock-controller@38400000 {
- compatible = "microchip,mpfs-ccc";
- reg = <0x0 0x38400000 0x0 0x1000>, <0x0 0x38800000 0x0 0x1000>,
- <0x0 0x39400000 0x0 0x1000>, <0x0 0x39800000 0x0 0x1000>;
- #clock-cells = <1>;
- status = "disabled";
- };
-
- mmuart0: serial@20000000 {
- compatible = "ns16550a";
- reg = <0x0 0x20000000 0x0 0x400>;
- reg-io-width = <4>;
- reg-shift = <2>;
- interrupt-parent = <&plic>;
- interrupts = <90>;
- current-speed = <115200>;
- clocks = <&clkcfg CLK_MMUART0>;
- status = "disabled"; /* Reserved for the HSS */
- };
-
- mmuart1: serial@20100000 {
- compatible = "ns16550a";
- reg = <0x0 0x20100000 0x0 0x400>;
- reg-io-width = <4>;
- reg-shift = <2>;
- interrupt-parent = <&plic>;
- interrupts = <91>;
- current-speed = <115200>;
- clocks = <&clkcfg CLK_MMUART1>;
- status = "disabled";
- };
-
- mmuart2: serial@20102000 {
- compatible = "ns16550a";
- reg = <0x0 0x20102000 0x0 0x400>;
- reg-io-width = <4>;
- reg-shift = <2>;
- interrupt-parent = <&plic>;
- interrupts = <92>;
- current-speed = <115200>;
- clocks = <&clkcfg CLK_MMUART2>;
- status = "disabled";
- };
-
- mmuart3: serial@20104000 {
- compatible = "ns16550a";
- reg = <0x0 0x20104000 0x0 0x400>;
- reg-io-width = <4>;
- reg-shift = <2>;
- interrupt-parent = <&plic>;
- interrupts = <93>;
- current-speed = <115200>;
- clocks = <&clkcfg CLK_MMUART3>;
- status = "disabled";
- };
-
- mmuart4: serial@20106000 {
- compatible = "ns16550a";
- reg = <0x0 0x20106000 0x0 0x400>;
- reg-io-width = <4>;
- reg-shift = <2>;
- interrupt-parent = <&plic>;
- interrupts = <94>;
- clocks = <&clkcfg CLK_MMUART4>;
- current-speed = <115200>;
- status = "disabled";
- };
-
- /* Common node entry for emmc/sd */
- mmc: mmc@20008000 {
- compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
- reg = <0x0 0x20008000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- interrupts = <88>;
- clocks = <&clkcfg CLK_MMC>;
- max-frequency = <200000000>;
- status = "disabled";
- };
-
- spi0: spi@20108000 {
- compatible = "microchip,mpfs-spi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x20108000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- interrupts = <54>;
- clocks = <&clkcfg CLK_SPI0>;
- status = "disabled";
- };
-
- spi1: spi@20109000 {
- compatible = "microchip,mpfs-spi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x20109000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- interrupts = <55>;
- clocks = <&clkcfg CLK_SPI1>;
- status = "disabled";
- };
-
- qspi: spi@21000000 {
- compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x21000000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- interrupts = <85>;
- clocks = <&clkcfg CLK_QSPI>;
- status = "disabled";
- };
-
- i2c0: i2c@2010a000 {
- compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
- reg = <0x0 0x2010a000 0x0 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&plic>;
- interrupts = <58>;
- clocks = <&clkcfg CLK_I2C0>;
- clock-frequency = <100000>;
- status = "disabled";
- };
-
- i2c1: i2c@2010b000 {
- compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
- reg = <0x0 0x2010b000 0x0 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&plic>;
- interrupts = <61>;
- clocks = <&clkcfg CLK_I2C1>;
- clock-frequency = <100000>;
- status = "disabled";
- };
-
- can0: can@2010c000 {
- compatible = "microchip,mpfs-can";
- reg = <0x0 0x2010c000 0x0 0x1000>;
- clocks = <&clkcfg CLK_CAN0>;
- interrupt-parent = <&plic>;
- interrupts = <56>;
- status = "disabled";
- };
-
- can1: can@2010d000 {
- compatible = "microchip,mpfs-can";
- reg = <0x0 0x2010d000 0x0 0x1000>;
- clocks = <&clkcfg CLK_CAN1>;
- interrupt-parent = <&plic>;
- interrupts = <57>;
- status = "disabled";
- };
-
- mac0: ethernet@20110000 {
- compatible = "microchip,mpfs-macb", "cdns,macb";
- reg = <0x0 0x20110000 0x0 0x2000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&plic>;
- interrupts = <64>, <65>, <66>, <67>, <68>, <69>;
- local-mac-address = [00 00 00 00 00 00];
- clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
- clock-names = "pclk", "hclk";
- resets = <&clkcfg CLK_MAC0>;
- status = "disabled";
- };
-
- mac1: ethernet@20112000 {
- compatible = "microchip,mpfs-macb", "cdns,macb";
- reg = <0x0 0x20112000 0x0 0x2000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&plic>;
- interrupts = <70>, <71>, <72>, <73>, <74>, <75>;
- local-mac-address = [00 00 00 00 00 00];
- clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
- clock-names = "pclk", "hclk";
- resets = <&clkcfg CLK_MAC1>;
- status = "disabled";
- };
-
- gpio0: gpio@20120000 {
- compatible = "microchip,mpfs-gpio";
- reg = <0x0 0x20120000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- interrupt-controller;
- #interrupt-cells = <1>;
- clocks = <&clkcfg CLK_GPIO0>;
- gpio-controller;
- #gpio-cells = <2>;
- status = "disabled";
- };
-
- gpio1: gpio@20121000 {
- compatible = "microchip,mpfs-gpio";
- reg = <0x0 0x20121000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- interrupt-controller;
- #interrupt-cells = <1>;
- clocks = <&clkcfg CLK_GPIO1>;
- gpio-controller;
- #gpio-cells = <2>;
- status = "disabled";
- };
-
- gpio2: gpio@20122000 {
- compatible = "microchip,mpfs-gpio";
- reg = <0x0 0x20122000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- interrupt-controller;
- #interrupt-cells = <1>;
- clocks = <&clkcfg CLK_GPIO2>;
- gpio-controller;
- #gpio-cells = <2>;
- status = "disabled";
- };
-
- rtc: rtc@20124000 {
- compatible = "microchip,mpfs-rtc";
- reg = <0x0 0x20124000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- interrupts = <80>, <81>;
- clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>;
- clock-names = "rtc", "rtcref";
- status = "disabled";
- };
-
- usb: usb@20201000 {
- compatible = "microchip,mpfs-musb";
- reg = <0x0 0x20201000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- interrupts = <86>, <87>;
- clocks = <&clkcfg CLK_USB>;
- interrupt-names = "dma","mc";
- status = "disabled";
- };
-
- mbox: mailbox@37020000 {
- compatible = "microchip,mpfs-mailbox";
- reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>,
- <0x0 0x37020800 0x0 0x100>;
- interrupt-parent = <&plic>;
- interrupts = <96>;
- #mbox-cells = <1>;
- status = "disabled";
- };
- };
-};
diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-mbv32.dts
index 48ee115..4050ce2 100644
--- a/arch/riscv/dts/xilinx-mbv32.dts
+++ b/arch/riscv/dts/xilinx-mbv32.dts
@@ -20,7 +20,7 @@
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
- timebase-frequency = <102000000>;
+ timebase-frequency = <100000000>;
cpu_0: cpu@0 {
compatible = "amd,mbv32", "riscv";
device_type = "cpu";
@@ -28,7 +28,7 @@
riscv,isa = "rv32imafdc";
i-cache-size = <32768>;
d-cache-size = <32768>;
- clock-frequency = <102000000>;
+ clock-frequency = <100000000>;
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
@@ -46,15 +46,15 @@
stdout-path = "serial0:115200n8";
};
- memory@20000000 {
+ memory@80000000 {
device_type = "memory";
- reg = <0x20000000 0x20000000>;
+ reg = <0x80000000 0x40000000>;
};
- clk102: clock {
+ clk100: clock {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <102000000>;
+ clock-frequency = <100000000>;
};
axi: axi {
@@ -77,30 +77,20 @@
compatible = "xlnx,xps-timer-1.00.a";
reg = <0x41c00000 0x1000>;
interrupt-parent = <&axi_intc>;
- interrupts = <1 2>;
- bootph-all;
- xlnx,one-timer-only = <0>;
- clock-names = "s_axi_aclk";
- clocks = <&clk102>;
- };
-
- xlnx_timer1: timer@41c20000 {
- compatible = "xlnx,xps-timer-1.00.a";
- reg = <0x41c20000 0x1000>;
- interrupt-parent = <&axi_intc>;
interrupts = <0 2>;
+ bootph-all;
xlnx,one-timer-only = <0>;
clock-names = "s_axi_aclk";
- clocks = <&clk102>;
+ clocks = <&clk100>;
};
uart0: serial@40600000 {
compatible = "xlnx,xps-uartlite-1.00.a";
reg = <0x40600000 0x1000>;
interrupt-parent = <&axi_intc>;
- interrupts = <2 2>;
+ interrupts = <1 2>;
bootph-all;
- clocks = <&clk102>;
+ clocks = <&clk100>;
current-speed = <115200>;
xlnx,data-bits = <8>;
xlnx,use-parity = <0>;
diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
index 593d927..d356752 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -42,6 +42,7 @@
#ifdef CONFIG_SMBIOS
ulong smbios_start; /* Start address of SMBIOS table */
#endif
+ struct resume_data *resume;
};
#include <asm-generic/global_data.h>
diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h
new file mode 100644
index 0000000..19a10ca
--- /dev/null
+++ b/arch/riscv/include/asm/insn-def.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2024 Ventana Micro Systems Ltd.
+ *
+ * Ported from linux insn-def.h.
+ */
+
+#ifndef _ASM_RISCV_BARRIER_H
+#define _ASM_RISCV_BARRIER_H
+
+#define INSN_I_SIMM12_SHIFT 20
+#define INSN_I_RS1_SHIFT 15
+#define INSN_I_FUNC3_SHIFT 12
+#define INSN_I_RD_SHIFT 7
+#define INSN_I_OPCODE_SHIFT 0
+
+#define RV_OPCODE(v) __ASM_STR(v)
+#define RV_FUNC3(v) __ASM_STR(v)
+#define RV_FUNC7(v) __ASM_STR(v)
+#define RV_SIMM12(v) __ASM_STR(v)
+#define RV_RD(v) __ASM_STR(v)
+#define RV_RS1(v) __ASM_STR(v)
+#define RV_RS2(v) __ASM_STR(v)
+#define __RV_REG(v) __ASM_STR(x ## v)
+#define RV___RD(v) __RV_REG(v)
+#define RV___RS1(v) __RV_REG(v)
+#define RV___RS2(v) __RV_REG(v)
+
+#define RV_OPCODE_MISC_MEM RV_OPCODE(15)
+#define RV_OPCODE_SYSTEM RV_OPCODE(115)
+
+#define __INSN_I(opcode, func3, rd, rs1, simm12) \
+ ".insn i " opcode ", " func3 ", " rd ", " rs1 ", " simm12 "\n"
+
+#define INSN_I(opcode, func3, rd, rs1, simm12) \
+ __INSN_I(RV_##opcode, RV_##func3, RV_##rd, \
+ RV_##rs1, RV_##simm12)
+
+#endif /* _ASM_RISCV_BARRIER_H */
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index ad32ded..47124db 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -33,8 +33,10 @@
SBI_EXT_CPPC = 0x43505043,
SBI_EXT_NACL = 0x4E41434C,
SBI_EXT_STA = 0x535441,
- SBI_EXT_DBTR = 0x44425452,
SBI_EXT_SSE = 0x535345,
+ SBI_EXT_FWFT = 0x46574654,
+ SBI_EXT_DBTR = 0x44425452,
+ SBI_EXT_MPXY = 0x4D505859,
};
enum sbi_ext_base_fid {
diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c
index afad7e1..e184d5e 100644
--- a/arch/riscv/lib/cache.c
+++ b/arch/riscv/lib/cache.c
@@ -5,6 +5,98 @@
*/
#include <cpu_func.h>
+#include <dm.h>
+#include <asm/insn-def.h>
+#include <linux/const.h>
+
+#define CBO_INVAL(base) \
+ INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \
+ RS1(base), SIMM12(0))
+#define CBO_CLEAN(base) \
+ INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \
+ RS1(base), SIMM12(1))
+#define CBO_FLUSH(base) \
+ INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \
+ RS1(base), SIMM12(2))
+enum {
+ CBO_CLEAN,
+ CBO_FLUSH,
+ CBO_INVAL
+} riscv_cbo_ops;
+static int zicbom_block_size;
+
+static inline void do_cbo_clean(unsigned long base)
+{
+ asm volatile ("add a0, %0, zero\n" CBO_CLEAN(%0) ::
+ "r"(base) : "memory");
+}
+
+static inline void do_cbo_flush(unsigned long base)
+{
+ asm volatile ("add a0, %0, zero\n" CBO_FLUSH(%0) ::
+ "r"(base) : "memory");
+}
+
+static inline void do_cbo_inval(unsigned long base)
+{
+ asm volatile ("add a0, %0, zero\n" CBO_INVAL(%0) ::
+ "r"(base) : "memory");
+}
+
+static void cbo_op(int op_type, unsigned long start,
+ unsigned long end)
+{
+ unsigned long op_size = end - start, size = 0;
+ void (*fn)(unsigned long base);
+
+ switch (op_type) {
+ case CBO_CLEAN:
+ fn = do_cbo_clean;
+ break;
+ case CBO_FLUSH:
+ fn = do_cbo_flush;
+ break;
+ case CBO_INVAL:
+ fn = do_cbo_inval;
+ break;
+ }
+ start &= ~(UL(zicbom_block_size - 1));
+ while (size < op_size) {
+ fn(start + size);
+ size += zicbom_block_size;
+ }
+}
+
+void cbo_flush(unsigned long start, unsigned long end)
+{
+ if (zicbom_block_size)
+ cbo_op(CBO_FLUSH, start, end);
+}
+
+void cbo_inval(unsigned long start, unsigned long end)
+{
+ if (zicbom_block_size)
+ cbo_op(CBO_INVAL, start, end);
+}
+
+static int riscv_zicbom_init(void)
+{
+ struct udevice *dev;
+
+ if (!CONFIG_IS_ENABLED(RISCV_ISA_ZICBOM) || zicbom_block_size)
+ return 1;
+
+ uclass_first_device(UCLASS_CPU, &dev);
+ if (!dev) {
+ log_debug("Failed to get cpu device!\n");
+ return 0;
+ }
+
+ if (dev_read_u32(dev, "riscv,cbom-block-size", &zicbom_block_size))
+ log_debug("riscv,cbom-block-size DT property not present\n");
+
+ return zicbom_block_size;
+}
void invalidate_icache_all(void)
{
@@ -17,6 +109,7 @@
__weak void flush_dcache_range(unsigned long start, unsigned long end)
{
+ cbo_flush(start, end);
}
__weak void invalidate_icache_range(unsigned long start, unsigned long end)
@@ -30,6 +123,7 @@
__weak void invalidate_dcache_range(unsigned long start, unsigned long end)
{
+ cbo_inval(start, end);
}
void cache_flush(void)
@@ -72,4 +166,6 @@
__weak void enable_caches(void)
{
+ if (!riscv_zicbom_init())
+ log_info("Zicbom not initialized.\n");
}
diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c
index c658e72..6dfd1a2 100644
--- a/arch/riscv/lib/fdt_fixup.c
+++ b/arch/riscv/lib/fdt_fixup.c
@@ -142,7 +142,7 @@
size = fdt_totalsize(blob);
err = fdt_open_into(blob, blob, size + 32);
if (err < 0) {
- log_err("Device Tree can't be expanded to accommodate new node");
+ log_err("Device-tree can't be expanded to accommodate new node\n");
return err;
}
chosen_offset = fdt_path_offset(blob, "/chosen");
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index 714cc92..ef1056e 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -22,11 +22,9 @@
DECLARE_GLOBAL_DATA_PTR;
-static struct resume_data *resume;
-
void set_resume(struct resume_data *data)
{
- resume = data;
+ gd->arch.resume = data;
}
static void show_efi_loaded_images(uintptr_t epc)
@@ -138,9 +136,9 @@
"Store/AMO page fault",
};
- if (resume) {
- resume->code = code;
- longjmp(resume->jump, 1);
+ if (gd->arch.resume) {
+ gd->arch.resume->code = code;
+ longjmp(gd->arch.resume->jump, 1);
}
if (code < ARRAY_SIZE(exception_code))
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 9bf44ae..3017b33 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -527,6 +527,9 @@
};
f-test {
+ #interrupt-cells = <2>;
+ interrupt-parent = <&irq>;
+ interrupts = <4 0>;
compatible = "denx,u-boot-fdt-test";
};
diff --git a/arch/sandbox/lib/Makefile b/arch/sandbox/lib/Makefile
index d7d15a5..5d7beb2 100644
--- a/arch/sandbox/lib/Makefile
+++ b/arch/sandbox/lib/Makefile
@@ -5,7 +5,8 @@
# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-obj-y += fdt_fixup.o interrupts.o
-obj-$(CONFIG_PCI) += pci_io.o
-obj-$(CONFIG_CMD_BOOTM) += bootm.o
-obj-$(CONFIG_CMD_BOOTZ) += bootm.o
+obj-y += fdt_fixup.o interrupts.o
+obj-$(CONFIG_PCI) += pci_io.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_CMD_BOOTZ) += bootm.o
+obj-$(CONFIG_$(SPL_)ACPIGEN) += acpi_table.o
diff --git a/arch/sandbox/lib/acpi_table.c b/arch/sandbox/lib/acpi_table.c
new file mode 100644
index 0000000..90bb96d
--- /dev/null
+++ b/arch/sandbox/lib/acpi_table.c
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <acpi/acpi_table.h>
+
+void acpi_fill_fadt(struct acpi_fadt *fadt)
+{
+}
+
+void *acpi_fill_madt(struct acpi_madt *madt, struct acpi_ctx *ctx)
+{
+ return ctx->current;
+}
diff --git a/arch/x86/cpu/apollolake/acpi.c b/arch/x86/cpu/apollolake/acpi.c
index 76230ae..93040e7 100644
--- a/arch/x86/cpu/apollolake/acpi.c
+++ b/arch/x86/cpu/apollolake/acpi.c
@@ -128,8 +128,10 @@
return MP_IRQ_POLARITY_LOW;
}
-void fill_fadt(struct acpi_fadt *fadt)
+void acpi_fill_fadt(struct acpi_fadt *fadt)
{
+ intel_acpi_fill_fadt(fadt);
+
fadt->pm_tmr_blk = IOMAP_ACPI_BASE + PM1_TMR;
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
@@ -143,23 +145,9 @@
fadt->x_pm_tmr_blk.space_id = 1;
fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
fadt->x_pm_tmr_blk.addrl = IOMAP_ACPI_BASE + PM1_TMR;
-}
-
-static int apl_write_fadt(struct acpi_ctx *ctx, const struct acpi_writer *entry)
-{
- struct acpi_table_header *header;
- struct acpi_fadt *fadt;
-
- fadt = ctx->current;
- acpi_fadt_common(fadt, ctx->facs, ctx->dsdt);
- intel_acpi_fill_fadt(fadt);
- fill_fadt(fadt);
- header = &fadt->header;
- header->checksum = table_compute_checksum(fadt, header->length);
- return acpi_add_fadt(ctx, fadt);
+ fadt->preferred_pm_profile = ACPI_PM_MOBILE;
}
-ACPI_WRITER(5fadt, "FADT", apl_write_fadt, 0);
int apl_acpi_fill_dmar(struct acpi_ctx *ctx)
{
diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c
index 7821964..7e1c2de 100644
--- a/arch/x86/cpu/baytrail/acpi.c
+++ b/arch/x86/cpu/baytrail/acpi.c
@@ -15,20 +15,13 @@
#include <asm/arch/iomap.h>
#include <dm/uclass-internal.h>
-static int baytrail_write_fadt(struct acpi_ctx *ctx,
- const struct acpi_writer *entry)
+void acpi_fill_fadt(struct acpi_fadt *fadt)
{
struct acpi_table_header *header;
- struct acpi_fadt *fadt;
- fadt = ctx->current;
header = &fadt->header;
u16 pmbase = ACPI_BASE_ADDRESS;
- memset(fadt, '\0', sizeof(struct acpi_fadt));
-
- acpi_fill_header(header, "FACP");
- header->length = sizeof(struct acpi_fadt);
header->revision = 4;
fadt->preferred_pm_profile = ACPI_PM_MOBILE;
@@ -77,9 +70,6 @@
fadt->reset_reg.addrh = 0;
fadt->reset_value = SYS_RST | RST_CPU | FULL_RST;
- fadt->x_firmware_ctrl = map_to_sysmem(ctx->facs);
- fadt->x_dsdt = map_to_sysmem(ctx->dsdt);
-
fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
fadt->x_pm1a_evt_blk.bit_offset = 0;
@@ -135,12 +125,7 @@
fadt->x_gpe1_blk.access_size = 0;
fadt->x_gpe1_blk.addrl = 0x0;
fadt->x_gpe1_blk.addrh = 0x0;
-
- header->checksum = table_compute_checksum(fadt, header->length);
-
- return acpi_add_fadt(ctx, fadt);
}
-ACPI_WRITER(5fadt, "FADT", baytrail_write_fadt, 0);
int acpi_create_gnvs(struct acpi_global_nvs *gnvs)
{
diff --git a/arch/x86/cpu/intel_common/acpi.c b/arch/x86/cpu/intel_common/acpi.c
index 29676b4..982149b 100644
--- a/arch/x86/cpu/intel_common/acpi.c
+++ b/arch/x86/cpu/intel_common/acpi.c
@@ -19,6 +19,7 @@
#include <asm/global_data.h>
#include <asm/intel_acpi.h>
#include <asm/ioapic.h>
+#include <asm/lapic.h>
#include <asm/mpspec.h>
#include <asm/smm.h>
#include <asm/turbo.h>
@@ -80,33 +81,40 @@
return sci_irq;
}
-static unsigned long acpi_madt_irq_overrides(unsigned long current)
+static void *acpi_madt_irq_overrides(void *current)
{
int sci = acpi_sci_irq();
u16 flags = MP_IRQ_TRIGGER_LEVEL;
- if (sci < 0)
- return log_msg_ret("sci irq", sci);
+ if (sci < 0) {
+ log_err("sci irq %d", sci);
+ return current;
+ }
/* INT_SRC_OVR */
- current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride(current, 0, 0, 2, 0);
flags |= arch_madt_sci_irq_polarity(sci);
/* SCI */
current +=
- acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags);
+ acpi_create_madt_irqoverride(current, 0, sci, sci, flags);
return current;
}
-u32 acpi_fill_madt(u32 current)
+void *acpi_fill_madt(struct acpi_madt *madt, struct acpi_ctx *ctx)
{
+ void *current = ctx->current;
+
+ madt->lapic_addr = LAPIC_DEFAULT_BASE;
+ madt->flags = ACPI_MADT_PCAT_COMPAT;
+
/* Local APICs */
current += acpi_create_madt_lapics(current);
/* IOAPIC */
- current += acpi_create_madt_ioapic((void *)current, 2, IO_APIC_ADDR, 0);
+ current += acpi_create_madt_ioapic(current, 2, IO_APIC_ADDR, 0);
return acpi_madt_irq_overrides(current);
}
diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c
index 80e9460..0fe5f2b 100644
--- a/arch/x86/cpu/quark/acpi.c
+++ b/arch/x86/cpu/quark/acpi.c
@@ -11,23 +11,14 @@
#include <asm/arch/iomap.h>
#include <linux/string.h>
-static int quark_write_fadt(struct acpi_ctx *ctx,
- const struct acpi_writer *entry)
+void acpi_fill_fadt(struct acpi_fadt *fadt)
{
u16 pmbase = ACPI_PM1_BASE_ADDRESS;
struct acpi_table_header *header;
- struct acpi_fadt *fadt;
- fadt = ctx->current;
header = &fadt->header;
-
- memset(fadt, '\0', sizeof(struct acpi_fadt));
-
- acpi_fill_header(header, "FACP");
- header->length = sizeof(struct acpi_fadt);
header->revision = 4;
- fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED;
fadt->sci_int = 9;
fadt->smi_cmd = 0;
fadt->acpi_enable = 0;
@@ -73,9 +64,6 @@
fadt->reset_reg.addrh = 0;
fadt->reset_value = SYS_RST | RST_CPU | FULL_RST;
- fadt->x_firmware_ctrl = map_to_sysmem(ctx->facs);
- fadt->x_dsdt = map_to_sysmem(ctx->dsdt);
-
fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
fadt->x_pm1a_evt_blk.bit_offset = 0;
@@ -131,12 +119,7 @@
fadt->x_gpe1_blk.access_size = 0;
fadt->x_gpe1_blk.addrl = 0x0;
fadt->x_gpe1_blk.addrh = 0x0;
-
- header->checksum = table_compute_checksum(fadt, header->length);
-
- return acpi_add_fadt(ctx, fadt);
}
-ACPI_WRITER(5fadt, "FADT", quark_write_fadt, 0);
int acpi_create_gnvs(struct acpi_global_nvs *gnvs)
{
diff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c
index d4d0ef6..8ea764f 100644
--- a/arch/x86/cpu/tangier/acpi.c
+++ b/arch/x86/cpu/tangier/acpi.c
@@ -10,27 +10,15 @@
#include <mapmem.h>
#include <acpi/acpi_table.h>
#include <asm/ioapic.h>
+#include <asm/lapic.h>
#include <asm/mpspec.h>
#include <asm/tables.h>
#include <asm/arch/global_nvs.h>
#include <asm/arch/iomap.h>
#include <dm/uclass-internal.h>
-static int tangier_write_fadt(struct acpi_ctx *ctx,
- const struct acpi_writer *entry)
+void acpi_fill_fadt(struct acpi_fadt *fadt)
{
- struct acpi_table_header *header;
- struct acpi_fadt *fadt;
-
- fadt = ctx->current;
- header = &fadt->header;
-
- memset(fadt, '\0', sizeof(struct acpi_fadt));
-
- acpi_fill_header(header, "FACP");
- header->length = sizeof(struct acpi_fadt);
- header->revision = 6;
-
fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED;
fadt->iapc_boot_arch = ACPI_FADT_VGA_NOT_PRESENT |
@@ -40,20 +28,15 @@
ACPI_FADT_POWER_BUTTON | ACPI_FADT_SLEEP_BUTTON |
ACPI_FADT_SEALED_CASE | ACPI_FADT_HEADLESS |
ACPI_FADT_HW_REDUCED_ACPI;
-
- fadt->minor_revision = 2;
-
- fadt->x_firmware_ctrl = map_to_sysmem(ctx->facs);
- fadt->x_dsdt = map_to_sysmem(ctx->dsdt);
-
- header->checksum = table_compute_checksum(fadt, header->length);
-
- return acpi_add_fadt(ctx, fadt);
}
-ACPI_WRITER(5fadt, "FADT", tangier_write_fadt, 0);
-u32 acpi_fill_madt(u32 current)
+void *acpi_fill_madt(struct acpi_madt *madt, struct acpi_ctx *ctx)
{
+ void *current = ctx->current;
+
+ madt->lapic_addr = LAPIC_DEFAULT_BASE;
+ madt->flags = ACPI_MADT_PCAT_COMPAT;
+
current += acpi_create_madt_lapics(current);
current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h
index 57e4165..ff60384 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -24,16 +24,13 @@
/* These can be used by the target port */
-int acpi_create_madt_lapics(u32 current);
+int acpi_create_madt_lapics(void *current);
int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
u32 addr, u32 gsi_base);
int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
u8 bus, u8 source, u32 gsirq, u16 flags);
int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
u8 cpu, u16 flags, u8 lint);
-u32 acpi_fill_madt(u32 current);
-int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 base,
- u16 seg_nr, u8 start, u8 end);
/**
* acpi_write_hpet() - Write out a HPET table
@@ -46,17 +43,6 @@
int acpi_write_hpet(struct acpi_ctx *ctx);
/**
- * acpi_write_dbg2_pci_uart() - Write out a DBG2 table
- *
- * @ctx: Current ACPI context
- * @dev: Debug UART device to describe
- * @access_size: Access size for UART (e.g. ACPI_ACCESS_SIZE_DWORD_ACCESS)
- * Return: 0 if OK, -ve on error
- */
-int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,
- uint access_size);
-
-/**
* acpi_create_gnvs() - Create a GNVS (Global Non Volatile Storage) table
*
* @gnvs: Table to fill in
@@ -180,18 +166,6 @@
pci_dev_t bdf);
/**
- * acpi_fadt_common() - Handle common parts of filling out an FADT
- *
- * This sets up the Fixed ACPI Description Table
- *
- * @fadt: Pointer to place to put FADT
- * @facs: Pointer to the FACS
- * @dsdt: Pointer to the DSDT
- */
-void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs,
- void *dsdt);
-
-/**
* intel_acpi_fill_fadt() - Set up the contents of the FADT
*
* This sets up parts of the Fixed ACPI Description Table that are common to
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 7677c0c..43e6a1d 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -97,7 +97,7 @@
else
ifndef CONFIG_XPL_BUILD
-ifneq ($(CONFIG_CMD_BOOTEFI_SELFTEST)$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE),)
+ifneq ($(CONFIG_CMD_BOOTEFI_SELFTEST)$(CONFIG_BOOTEFI_HELLO_COMPILE),)
extra-y += $(EFI_CRT0) $(EFI_RELOC)
endif
endif
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index e38ce19..3186e48 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -40,7 +40,7 @@
return lapic->length;
}
-int acpi_create_madt_lapics(u32 current)
+int acpi_create_madt_lapics(void *current)
{
struct udevice *dev;
int total_length = 0;
@@ -100,23 +100,28 @@
return lapic_nmi->length;
}
-static int acpi_create_madt_irq_overrides(u32 current)
+static int acpi_create_madt_irq_overrides(void *current)
{
struct acpi_madt_irqoverride *irqovr;
u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
int length = 0;
- irqovr = (void *)current;
+ irqovr = current;
length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
- irqovr = (void *)(current + length);
+ irqovr = current + length;
length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags);
return length;
}
-__weak u32 acpi_fill_madt(u32 current)
+__weak void *acpi_fill_madt(struct acpi_madt *madt, struct acpi_ctx *ctx)
{
+ void *current = ctx->current;
+
+ madt->lapic_addr = LAPIC_DEFAULT_BASE;
+ madt->flags = ACPI_MADT_PCAT_COMPAT;
+
current += acpi_create_madt_lapics(current);
current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
@@ -127,39 +132,6 @@
return current;
}
-int acpi_write_madt(struct acpi_ctx *ctx, const struct acpi_writer *entry)
-{
- struct acpi_table_header *header;
- struct acpi_madt *madt;
- u32 current;
-
- madt = ctx->current;
-
- memset(madt, '\0', sizeof(struct acpi_madt));
- header = &madt->header;
-
- /* Fill out header fields */
- acpi_fill_header(header, "APIC");
- header->length = sizeof(struct acpi_madt);
- header->revision = ACPI_MADT_REV_ACPI_3_0;
-
- madt->lapic_addr = LAPIC_DEFAULT_BASE;
- madt->flags = ACPI_MADT_PCAT_COMPAT;
-
- current = (u32)madt + sizeof(struct acpi_madt);
- current = acpi_fill_madt(current);
-
- /* (Re)calculate length and checksum */
- header->length = current - (u32)madt;
-
- header->checksum = table_compute_checksum((void *)madt, header->length);
- acpi_add_table(ctx, madt);
- acpi_inc(ctx, madt->header.length);
-
- return 0;
-}
-ACPI_WRITER(5x86, NULL, acpi_write_madt, 0);
-
/**
* acpi_create_tcpa() - Create a TCPA table
*
@@ -279,140 +251,6 @@
}
ACPI_WRITER(5tpm2, "TPM2", acpi_write_tpm2, 0);
-int acpi_write_spcr(struct acpi_ctx *ctx, const struct acpi_writer *entry)
-{
- struct serial_device_info serial_info = {0};
- ulong serial_address, serial_offset;
- struct acpi_table_header *header;
- struct acpi_spcr *spcr;
- struct udevice *dev;
- uint serial_config;
- uint serial_width;
- int access_size;
- int space_id;
- int ret = -ENODEV;
-
- spcr = ctx->current;
- header = &spcr->header;
-
- memset(spcr, '\0', sizeof(struct acpi_spcr));
-
- /* Fill out header fields */
- acpi_fill_header(header, "SPCR");
- header->length = sizeof(struct acpi_spcr);
- header->revision = 2;
-
- /* Read the device once, here. It is reused below */
- dev = gd->cur_serial_dev;
- if (dev)
- ret = serial_getinfo(dev, &serial_info);
- if (ret)
- serial_info.type = SERIAL_CHIP_UNKNOWN;
-
- /* Encode chip type */
- switch (serial_info.type) {
- case SERIAL_CHIP_16550_COMPATIBLE:
- spcr->interface_type = ACPI_DBG2_16550_COMPATIBLE;
- break;
- case SERIAL_CHIP_UNKNOWN:
- default:
- spcr->interface_type = ACPI_DBG2_UNKNOWN;
- break;
- }
-
- /* Encode address space */
- switch (serial_info.addr_space) {
- case SERIAL_ADDRESS_SPACE_MEMORY:
- space_id = ACPI_ADDRESS_SPACE_MEMORY;
- break;
- case SERIAL_ADDRESS_SPACE_IO:
- default:
- space_id = ACPI_ADDRESS_SPACE_IO;
- break;
- }
-
- serial_width = serial_info.reg_width * 8;
- serial_offset = serial_info.reg_offset << serial_info.reg_shift;
- serial_address = serial_info.addr + serial_offset;
-
- /* Encode register access size */
- switch (serial_info.reg_shift) {
- case 0:
- access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- break;
- case 1:
- access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
- break;
- case 2:
- access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- break;
- case 3:
- access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS;
- break;
- default:
- access_size = ACPI_ACCESS_SIZE_UNDEFINED;
- break;
- }
-
- debug("UART type %u @ %lx\n", spcr->interface_type, serial_address);
-
- /* Fill GAS */
- spcr->serial_port.space_id = space_id;
- spcr->serial_port.bit_width = serial_width;
- spcr->serial_port.bit_offset = 0;
- spcr->serial_port.access_size = access_size;
- spcr->serial_port.addrl = lower_32_bits(serial_address);
- spcr->serial_port.addrh = upper_32_bits(serial_address);
-
- /* Encode baud rate */
- switch (serial_info.baudrate) {
- case 9600:
- spcr->baud_rate = 3;
- break;
- case 19200:
- spcr->baud_rate = 4;
- break;
- case 57600:
- spcr->baud_rate = 6;
- break;
- case 115200:
- spcr->baud_rate = 7;
- break;
- default:
- spcr->baud_rate = 0;
- break;
- }
-
- serial_config = SERIAL_DEFAULT_CONFIG;
- if (dev)
- ret = serial_getconfig(dev, &serial_config);
-
- spcr->parity = SERIAL_GET_PARITY(serial_config);
- spcr->stop_bits = SERIAL_GET_STOP(serial_config);
-
- /* No PCI devices for now */
- spcr->pci_device_id = 0xffff;
- spcr->pci_vendor_id = 0xffff;
-
- /*
- * SPCR has no clue if the UART base clock speed is different
- * to the default one. However, the SPCR 1.04 defines baud rate
- * 0 as a preconfigured state of UART and OS is supposed not
- * to touch the configuration of the serial device.
- */
- if (serial_info.clock != SERIAL_DEFAULT_CLOCK)
- spcr->baud_rate = 0;
-
- /* Fix checksum */
- header->checksum = table_compute_checksum((void *)spcr, header->length);
-
- acpi_add_table(ctx, spcr);
- acpi_inc(ctx, spcr->header.length);
-
- return 0;
-}
-ACPI_WRITER(5spcr, "SPCR", acpi_write_spcr, 0);
-
int acpi_write_gnvs(struct acpi_ctx *ctx, const struct acpi_writer *entry)
{
ulong addr;
@@ -515,69 +353,6 @@
return 0;
}
-int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,
- uint access_size)
-{
- struct acpi_dbg2_header *dbg2 = ctx->current;
- char path[ACPI_PATH_MAX];
- struct acpi_gen_regaddr address;
- phys_addr_t addr;
- int ret;
-
- if (!device_active(dev)) {
- log_info("Device not enabled\n");
- return -EACCES;
- }
- /*
- * PCI devices don't remember their resource allocation information in
- * U-Boot at present. We assume that MMIO is used for the UART and that
- * the address space is 32 bytes: ns16550 uses 8 registers of up to
- * 32-bits each. This is only for debugging so it is not a big deal.
- */
- addr = dm_pci_read_bar32(dev, 0);
- log_debug("UART addr %lx\n", (ulong)addr);
-
- memset(&address, '\0', sizeof(address));
- address.space_id = ACPI_ADDRESS_SPACE_MEMORY;
- address.addrl = (uint32_t)addr;
- address.addrh = (uint32_t)((addr >> 32) & 0xffffffff);
- address.access_size = access_size;
-
- ret = acpi_device_path(dev, path, sizeof(path));
- if (ret)
- return log_msg_ret("path", ret);
- acpi_create_dbg2(dbg2, ACPI_DBG2_SERIAL_PORT,
- ACPI_DBG2_16550_COMPATIBLE, &address, 0x1000, path);
-
- acpi_inc_align(ctx, dbg2->header.length);
- acpi_add_table(ctx, dbg2);
-
- return 0;
-}
-
-void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs,
- void *dsdt)
-{
- struct acpi_table_header *header = &fadt->header;
-
- memset((void *)fadt, '\0', sizeof(struct acpi_fadt));
-
- acpi_fill_header(header, "FACP");
- header->length = sizeof(struct acpi_fadt);
- header->revision = 4;
- memcpy(header->oem_id, OEM_ID, 6);
- memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
- memcpy(header->creator_id, ASLC_ID, 4);
-
- fadt->x_firmware_ctrl = map_to_sysmem(facs);
- fadt->x_dsdt = map_to_sysmem(dsdt);
-
- fadt->preferred_pm_profile = ACPI_PM_MOBILE;
-
- /* Use ACPI 3.0 revision */
- fadt->header.revision = 4;
-}
-
void acpi_create_dmar_drhd(struct acpi_ctx *ctx, uint flags, uint segment,
u64 bar)
{
diff --git a/board/emcraft/imx8mp_navqp/Kconfig b/board/emcraft/imx8mp_navqp/Kconfig
new file mode 100644
index 0000000..20b09b6
--- /dev/null
+++ b/board/emcraft/imx8mp_navqp/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_IMX8MP_NAVQP
+
+config SYS_BOARD
+ default "imx8mp_navqp"
+
+config SYS_VENDOR
+ default "emcraft"
+
+config SYS_CONFIG_NAME
+ default "imx8mp_navqp"
+
+config IMX_CONFIG
+ default "board/emcraft/imx8mp_navqp/imximage-8mp-lpddr4.cfg"
+
+endif
diff --git a/board/emcraft/imx8mp_navqp/MAINTAINERS b/board/emcraft/imx8mp_navqp/MAINTAINERS
new file mode 100644
index 0000000..d91605e
--- /dev/null
+++ b/board/emcraft/imx8mp_navqp/MAINTAINERS
@@ -0,0 +1,8 @@
+Emcraft Systems NavQ+ board (i.MX8M Plus)
+M: Gilles Talis <gilles.talis@gmail.com>
+S: Maintained
+F: arch/arm/dts/imx8mp-navqp-u-boot.dtsi
+F: board/emcraft/imx8mp_navqp/
+F: configs/imx8mp_navqp_defconfig
+F: doc/board/emcraft/
+F: include/configs/imx8mp_navqp.h
diff --git a/board/emcraft/imx8mp_navqp/Makefile b/board/emcraft/imx8mp_navqp/Makefile
new file mode 100644
index 0000000..a5890b0
--- /dev/null
+++ b/board/emcraft/imx8mp_navqp/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright 2019 NXP
+# Copyright 2024 Gilles Talis <gilles.talis@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += imx8mp_navqp.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
diff --git a/board/emcraft/imx8mp_navqp/imx8mp_navqp.c b/board/emcraft/imx8mp_navqp/imx8mp_navqp.c
new file mode 100644
index 0000000..219efdd
--- /dev/null
+++ b/board/emcraft/imx8mp_navqp/imx8mp_navqp.c
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Copyright 2024 Gilles Talis <gilles.talis@gmail.com>
+ */
+
+int board_init(void)
+{
+ return 0;
+}
diff --git a/board/emcraft/imx8mp_navqp/imx8mp_navqp.env b/board/emcraft/imx8mp_navqp/imx8mp_navqp.env
new file mode 100644
index 0000000..c19fe08
--- /dev/null
+++ b/board/emcraft/imx8mp_navqp/imx8mp_navqp.env
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 Gilles Talis <gilles.talis@gmail.com>
+ */
+
+#include <config_distro_bootcmd.h>
+
+scriptaddr=CONFIG_SYS_LOAD_ADDR
+kernel_addr_r=CONFIG_SYS_LOAD_ADDR
+image=Image
+console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200
+fdt_addr_r=0x43000000
+boot_fdt=try
+fdtfile=CONFIG_DEFAULT_FDT_FILE
+initrd_addr=0x43800000
+bootm_size=0x10000000
+mmcpart=1
+mmcroot=/dev/mmcblk1p2 rootwait rw
diff --git a/board/emcraft/imx8mp_navqp/imximage-8mp-lpddr4.cfg b/board/emcraft/imx8mp_navqp/imximage-8mp-lpddr4.cfg
new file mode 100644
index 0000000..0a23408
--- /dev/null
+++ b/board/emcraft/imx8mp_navqp/imximage-8mp-lpddr4.cfg
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021, 2024 NXP
+ */
+
+ROM_VERSION v2
+BOOT_FROM sd
+LOADER u-boot-spl-ddr.bin 0x920000
diff --git a/board/emcraft/imx8mp_navqp/lpddr4_timing.c b/board/emcraft/imx8mp_navqp/lpddr4_timing.c
new file mode 100644
index 0000000..039ea3e
--- /dev/null
+++ b/board/emcraft/imx8mp_navqp/lpddr4_timing.c
@@ -0,0 +1,1842 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019, 2024 NXP
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa3080020 },
+ { 0x3d400020, 0x1223 },
+ { 0x3d400024, 0x16e3600 },
+ { 0x3d400064, 0x5b011d },
+ { 0x3d400070, 0x7027f90 },
+ { 0x3d400074, 0x790 },
+ { 0x3d4000d0, 0xc00305ba },
+ { 0x3d4000d4, 0x940000 },
+ { 0x3d4000dc, 0xd4002d },
+ { 0x3d4000e0, 0x310000 },
+ { 0x3d4000e8, 0x660048 },
+ { 0x3d4000ec, 0x160048 },
+ { 0x3d400100, 0x191e1920 },
+ { 0x3d400104, 0x60630 },
+ { 0x3d40010c, 0xb0b000 },
+ { 0x3d400110, 0xe04080e },
+ { 0x3d400114, 0x2040c0c },
+ { 0x3d400118, 0x1010007 },
+ { 0x3d40011c, 0x401 },
+ { 0x3d400130, 0x20600 },
+ { 0x3d400134, 0xc100002 },
+ { 0x3d400138, 0x123 },
+ { 0x3d400144, 0x96004b },
+ { 0x3d400180, 0x2ee0017 },
+ { 0x3d400184, 0x2605b8e },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x497820a },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x170a },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0xc99 },
+ { 0x3d400108, 0x70e1617 },
+ { 0x3d400200, 0x18 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d40021c, 0xf07 },
+ { 0x3d400250, 0x1705 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400404, 0x72ff },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x1021 },
+ { 0x3d402024, 0x30d400 },
+ { 0x3d402050, 0x20d000 },
+ { 0x3d402064, 0xc0026 },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x330000 },
+ { 0x3d4020e8, 0x660048 },
+ { 0x3d4020ec, 0x160048 },
+ { 0x3d402100, 0xa040305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x301 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x27 },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0xc99 },
+ { 0x3d403020, 0x1021 },
+ { 0x3d403024, 0xc3500 },
+ { 0x3d403050, 0x20d000 },
+ { 0x3d403064, 0x3000a },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x330000 },
+ { 0x3d4030e8, 0x660048 },
+ { 0x3d4030ec, 0x160048 },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x301 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0xa },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d4030f4, 0xc99 },
+ { 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x1 },
+ { 0x100a2, 0x2 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x4 },
+ { 0x100a5, 0x5 },
+ { 0x100a6, 0x6 },
+ { 0x100a7, 0x7 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x4 },
+ { 0x110a4, 0x5 },
+ { 0x110a5, 0x2 },
+ { 0x110a6, 0x7 },
+ { 0x110a7, 0x6 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x1 },
+ { 0x120a2, 0x3 },
+ { 0x120a3, 0x2 },
+ { 0x120a4, 0x5 },
+ { 0x120a5, 0x4 },
+ { 0x120a6, 0x7 },
+ { 0x120a7, 0x6 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x1 },
+ { 0x130a2, 0x2 },
+ { 0x130a3, 0x3 },
+ { 0x130a4, 0x4 },
+ { 0x130a5, 0x5 },
+ { 0x130a6, 0x6 },
+ { 0x130a7, 0x7 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x1205f, 0x1ff },
+ { 0x1215f, 0x1ff },
+ { 0x1305f, 0x1ff },
+ { 0x1315f, 0x1ff },
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x11205f, 0x1ff },
+ { 0x11215f, 0x1ff },
+ { 0x11305f, 0x1ff },
+ { 0x11315f, 0x1ff },
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x21205f, 0x1ff },
+ { 0x21215f, 0x1ff },
+ { 0x21305f, 0x1ff },
+ { 0x21315f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0x19 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x20024, 0x1a3 },
+ { 0x2003a, 0x2 },
+ { 0x120024, 0x1a3 },
+ { 0x2003a, 0x2 },
+ { 0x220024, 0x1a3 },
+ { 0x2003a, 0x2 },
+ { 0x20056, 0x3 },
+ { 0x120056, 0x3 },
+ { 0x220056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x1204d, 0xe00 },
+ { 0x1214d, 0xe00 },
+ { 0x1304d, 0xe00 },
+ { 0x1314d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x11204d, 0xe00 },
+ { 0x11214d, 0xe00 },
+ { 0x11304d, 0xe00 },
+ { 0x11314d, 0xe00 },
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x21204d, 0xe00 },
+ { 0x21214d, 0xe00 },
+ { 0x21304d, 0xe00 },
+ { 0x21314d, 0xe00 },
+ { 0x10049, 0xeba },
+ { 0x10149, 0xeba },
+ { 0x11049, 0xeba },
+ { 0x11149, 0xeba },
+ { 0x12049, 0xeba },
+ { 0x12149, 0xeba },
+ { 0x13049, 0xeba },
+ { 0x13149, 0xeba },
+ { 0x110049, 0xeba },
+ { 0x110149, 0xeba },
+ { 0x111049, 0xeba },
+ { 0x111149, 0xeba },
+ { 0x112049, 0xeba },
+ { 0x112149, 0xeba },
+ { 0x113049, 0xeba },
+ { 0x113149, 0xeba },
+ { 0x210049, 0xeba },
+ { 0x210149, 0xeba },
+ { 0x211049, 0xeba },
+ { 0x211149, 0xeba },
+ { 0x212049, 0xeba },
+ { 0x212149, 0xeba },
+ { 0x213049, 0xeba },
+ { 0x213149, 0xeba },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x3 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x2ee },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0x104 },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x12043, 0x5a1 },
+ { 0x12143, 0x5a1 },
+ { 0x13043, 0x5a1 },
+ { 0x13143, 0x5a1 },
+ { 0x1200b2, 0x104 },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x112043, 0x5a1 },
+ { 0x112143, 0x5a1 },
+ { 0x113043, 0x5a1 },
+ { 0x113143, 0x5a1 },
+ { 0x2200b2, 0x104 },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x212043, 0x5a1 },
+ { 0x212143, 0x5a1 },
+ { 0x213043, 0x5a1 },
+ { 0x213143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
+ { 0x2007d, 0x212 },
+ { 0x12007d, 0x212 },
+ { 0x22007d, 0x212 },
+ { 0x2007c, 0x61 },
+ { 0x12007c, 0x61 },
+ { 0x22007c, 0x61 },
+ { 0x1004a, 0x500 },
+ { 0x1104a, 0x500 },
+ { 0x1204a, 0x500 },
+ { 0x1304a, 0x500 },
+ { 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
+ { 0x8080, 0x0 },
+ { 0x108080, 0x0 },
+ { 0x208080, 0x0 },
+ { 0x9080, 0x0 },
+ { 0x109080, 0x0 },
+ { 0x209080, 0x0 },
+ { 0x10080, 0x0 },
+ { 0x110080, 0x0 },
+ { 0x210080, 0x0 },
+ { 0x10180, 0x0 },
+ { 0x110180, 0x0 },
+ { 0x210180, 0x0 },
+ { 0x11080, 0x0 },
+ { 0x111080, 0x0 },
+ { 0x211080, 0x0 },
+ { 0x11180, 0x0 },
+ { 0x111180, 0x0 },
+ { 0x211180, 0x0 },
+ { 0x12080, 0x0 },
+ { 0x112080, 0x0 },
+ { 0x212080, 0x0 },
+ { 0x12180, 0x0 },
+ { 0x112180, 0x0 },
+ { 0x212180, 0x0 },
+ { 0x13080, 0x0 },
+ { 0x113080, 0x0 },
+ { 0x213080, 0x0 },
+ { 0x13180, 0x0 },
+ { 0x113180, 0x0 },
+ { 0x213180, 0x0 },
+ { 0x10081, 0x0 },
+ { 0x110081, 0x0 },
+ { 0x210081, 0x0 },
+ { 0x10181, 0x0 },
+ { 0x110181, 0x0 },
+ { 0x210181, 0x0 },
+ { 0x11081, 0x0 },
+ { 0x111081, 0x0 },
+ { 0x211081, 0x0 },
+ { 0x11181, 0x0 },
+ { 0x111181, 0x0 },
+ { 0x211181, 0x0 },
+ { 0x12081, 0x0 },
+ { 0x112081, 0x0 },
+ { 0x212081, 0x0 },
+ { 0x12181, 0x0 },
+ { 0x112181, 0x0 },
+ { 0x212181, 0x0 },
+ { 0x13081, 0x0 },
+ { 0x113081, 0x0 },
+ { 0x213081, 0x0 },
+ { 0x13181, 0x0 },
+ { 0x113181, 0x0 },
+ { 0x213181, 0x0 },
+ { 0x100d0, 0x0 },
+ { 0x1100d0, 0x0 },
+ { 0x2100d0, 0x0 },
+ { 0x101d0, 0x0 },
+ { 0x1101d0, 0x0 },
+ { 0x2101d0, 0x0 },
+ { 0x110d0, 0x0 },
+ { 0x1110d0, 0x0 },
+ { 0x2110d0, 0x0 },
+ { 0x111d0, 0x0 },
+ { 0x1111d0, 0x0 },
+ { 0x2111d0, 0x0 },
+ { 0x120d0, 0x0 },
+ { 0x1120d0, 0x0 },
+ { 0x2120d0, 0x0 },
+ { 0x121d0, 0x0 },
+ { 0x1121d0, 0x0 },
+ { 0x2121d0, 0x0 },
+ { 0x130d0, 0x0 },
+ { 0x1130d0, 0x0 },
+ { 0x2130d0, 0x0 },
+ { 0x131d0, 0x0 },
+ { 0x1131d0, 0x0 },
+ { 0x2131d0, 0x0 },
+ { 0x100d1, 0x0 },
+ { 0x1100d1, 0x0 },
+ { 0x2100d1, 0x0 },
+ { 0x101d1, 0x0 },
+ { 0x1101d1, 0x0 },
+ { 0x2101d1, 0x0 },
+ { 0x110d1, 0x0 },
+ { 0x1110d1, 0x0 },
+ { 0x2110d1, 0x0 },
+ { 0x111d1, 0x0 },
+ { 0x1111d1, 0x0 },
+ { 0x2111d1, 0x0 },
+ { 0x120d1, 0x0 },
+ { 0x1120d1, 0x0 },
+ { 0x2120d1, 0x0 },
+ { 0x121d1, 0x0 },
+ { 0x1121d1, 0x0 },
+ { 0x2121d1, 0x0 },
+ { 0x130d1, 0x0 },
+ { 0x1130d1, 0x0 },
+ { 0x2130d1, 0x0 },
+ { 0x131d1, 0x0 },
+ { 0x1131d1, 0x0 },
+ { 0x2131d1, 0x0 },
+ { 0x10068, 0x0 },
+ { 0x10168, 0x0 },
+ { 0x10268, 0x0 },
+ { 0x10368, 0x0 },
+ { 0x10468, 0x0 },
+ { 0x10568, 0x0 },
+ { 0x10668, 0x0 },
+ { 0x10768, 0x0 },
+ { 0x10868, 0x0 },
+ { 0x11068, 0x0 },
+ { 0x11168, 0x0 },
+ { 0x11268, 0x0 },
+ { 0x11368, 0x0 },
+ { 0x11468, 0x0 },
+ { 0x11568, 0x0 },
+ { 0x11668, 0x0 },
+ { 0x11768, 0x0 },
+ { 0x11868, 0x0 },
+ { 0x12068, 0x0 },
+ { 0x12168, 0x0 },
+ { 0x12268, 0x0 },
+ { 0x12368, 0x0 },
+ { 0x12468, 0x0 },
+ { 0x12568, 0x0 },
+ { 0x12668, 0x0 },
+ { 0x12768, 0x0 },
+ { 0x12868, 0x0 },
+ { 0x13068, 0x0 },
+ { 0x13168, 0x0 },
+ { 0x13268, 0x0 },
+ { 0x13368, 0x0 },
+ { 0x13468, 0x0 },
+ { 0x13568, 0x0 },
+ { 0x13668, 0x0 },
+ { 0x13768, 0x0 },
+ { 0x13868, 0x0 },
+ { 0x10069, 0x0 },
+ { 0x10169, 0x0 },
+ { 0x10269, 0x0 },
+ { 0x10369, 0x0 },
+ { 0x10469, 0x0 },
+ { 0x10569, 0x0 },
+ { 0x10669, 0x0 },
+ { 0x10769, 0x0 },
+ { 0x10869, 0x0 },
+ { 0x11069, 0x0 },
+ { 0x11169, 0x0 },
+ { 0x11269, 0x0 },
+ { 0x11369, 0x0 },
+ { 0x11469, 0x0 },
+ { 0x11569, 0x0 },
+ { 0x11669, 0x0 },
+ { 0x11769, 0x0 },
+ { 0x11869, 0x0 },
+ { 0x12069, 0x0 },
+ { 0x12169, 0x0 },
+ { 0x12269, 0x0 },
+ { 0x12369, 0x0 },
+ { 0x12469, 0x0 },
+ { 0x12569, 0x0 },
+ { 0x12669, 0x0 },
+ { 0x12769, 0x0 },
+ { 0x12869, 0x0 },
+ { 0x13069, 0x0 },
+ { 0x13169, 0x0 },
+ { 0x13269, 0x0 },
+ { 0x13369, 0x0 },
+ { 0x13469, 0x0 },
+ { 0x13569, 0x0 },
+ { 0x13669, 0x0 },
+ { 0x13769, 0x0 },
+ { 0x13869, 0x0 },
+ { 0x1008c, 0x0 },
+ { 0x11008c, 0x0 },
+ { 0x21008c, 0x0 },
+ { 0x1018c, 0x0 },
+ { 0x11018c, 0x0 },
+ { 0x21018c, 0x0 },
+ { 0x1108c, 0x0 },
+ { 0x11108c, 0x0 },
+ { 0x21108c, 0x0 },
+ { 0x1118c, 0x0 },
+ { 0x11118c, 0x0 },
+ { 0x21118c, 0x0 },
+ { 0x1208c, 0x0 },
+ { 0x11208c, 0x0 },
+ { 0x21208c, 0x0 },
+ { 0x1218c, 0x0 },
+ { 0x11218c, 0x0 },
+ { 0x21218c, 0x0 },
+ { 0x1308c, 0x0 },
+ { 0x11308c, 0x0 },
+ { 0x21308c, 0x0 },
+ { 0x1318c, 0x0 },
+ { 0x11318c, 0x0 },
+ { 0x21318c, 0x0 },
+ { 0x1008d, 0x0 },
+ { 0x11008d, 0x0 },
+ { 0x21008d, 0x0 },
+ { 0x1018d, 0x0 },
+ { 0x11018d, 0x0 },
+ { 0x21018d, 0x0 },
+ { 0x1108d, 0x0 },
+ { 0x11108d, 0x0 },
+ { 0x21108d, 0x0 },
+ { 0x1118d, 0x0 },
+ { 0x11118d, 0x0 },
+ { 0x21118d, 0x0 },
+ { 0x1208d, 0x0 },
+ { 0x11208d, 0x0 },
+ { 0x21208d, 0x0 },
+ { 0x1218d, 0x0 },
+ { 0x11218d, 0x0 },
+ { 0x21218d, 0x0 },
+ { 0x1308d, 0x0 },
+ { 0x11308d, 0x0 },
+ { 0x21308d, 0x0 },
+ { 0x1318d, 0x0 },
+ { 0x11318d, 0x0 },
+ { 0x21318d, 0x0 },
+ { 0x100c0, 0x0 },
+ { 0x1100c0, 0x0 },
+ { 0x2100c0, 0x0 },
+ { 0x101c0, 0x0 },
+ { 0x1101c0, 0x0 },
+ { 0x2101c0, 0x0 },
+ { 0x102c0, 0x0 },
+ { 0x1102c0, 0x0 },
+ { 0x2102c0, 0x0 },
+ { 0x103c0, 0x0 },
+ { 0x1103c0, 0x0 },
+ { 0x2103c0, 0x0 },
+ { 0x104c0, 0x0 },
+ { 0x1104c0, 0x0 },
+ { 0x2104c0, 0x0 },
+ { 0x105c0, 0x0 },
+ { 0x1105c0, 0x0 },
+ { 0x2105c0, 0x0 },
+ { 0x106c0, 0x0 },
+ { 0x1106c0, 0x0 },
+ { 0x2106c0, 0x0 },
+ { 0x107c0, 0x0 },
+ { 0x1107c0, 0x0 },
+ { 0x2107c0, 0x0 },
+ { 0x108c0, 0x0 },
+ { 0x1108c0, 0x0 },
+ { 0x2108c0, 0x0 },
+ { 0x110c0, 0x0 },
+ { 0x1110c0, 0x0 },
+ { 0x2110c0, 0x0 },
+ { 0x111c0, 0x0 },
+ { 0x1111c0, 0x0 },
+ { 0x2111c0, 0x0 },
+ { 0x112c0, 0x0 },
+ { 0x1112c0, 0x0 },
+ { 0x2112c0, 0x0 },
+ { 0x113c0, 0x0 },
+ { 0x1113c0, 0x0 },
+ { 0x2113c0, 0x0 },
+ { 0x114c0, 0x0 },
+ { 0x1114c0, 0x0 },
+ { 0x2114c0, 0x0 },
+ { 0x115c0, 0x0 },
+ { 0x1115c0, 0x0 },
+ { 0x2115c0, 0x0 },
+ { 0x116c0, 0x0 },
+ { 0x1116c0, 0x0 },
+ { 0x2116c0, 0x0 },
+ { 0x117c0, 0x0 },
+ { 0x1117c0, 0x0 },
+ { 0x2117c0, 0x0 },
+ { 0x118c0, 0x0 },
+ { 0x1118c0, 0x0 },
+ { 0x2118c0, 0x0 },
+ { 0x120c0, 0x0 },
+ { 0x1120c0, 0x0 },
+ { 0x2120c0, 0x0 },
+ { 0x121c0, 0x0 },
+ { 0x1121c0, 0x0 },
+ { 0x2121c0, 0x0 },
+ { 0x122c0, 0x0 },
+ { 0x1122c0, 0x0 },
+ { 0x2122c0, 0x0 },
+ { 0x123c0, 0x0 },
+ { 0x1123c0, 0x0 },
+ { 0x2123c0, 0x0 },
+ { 0x124c0, 0x0 },
+ { 0x1124c0, 0x0 },
+ { 0x2124c0, 0x0 },
+ { 0x125c0, 0x0 },
+ { 0x1125c0, 0x0 },
+ { 0x2125c0, 0x0 },
+ { 0x126c0, 0x0 },
+ { 0x1126c0, 0x0 },
+ { 0x2126c0, 0x0 },
+ { 0x127c0, 0x0 },
+ { 0x1127c0, 0x0 },
+ { 0x2127c0, 0x0 },
+ { 0x128c0, 0x0 },
+ { 0x1128c0, 0x0 },
+ { 0x2128c0, 0x0 },
+ { 0x130c0, 0x0 },
+ { 0x1130c0, 0x0 },
+ { 0x2130c0, 0x0 },
+ { 0x131c0, 0x0 },
+ { 0x1131c0, 0x0 },
+ { 0x2131c0, 0x0 },
+ { 0x132c0, 0x0 },
+ { 0x1132c0, 0x0 },
+ { 0x2132c0, 0x0 },
+ { 0x133c0, 0x0 },
+ { 0x1133c0, 0x0 },
+ { 0x2133c0, 0x0 },
+ { 0x134c0, 0x0 },
+ { 0x1134c0, 0x0 },
+ { 0x2134c0, 0x0 },
+ { 0x135c0, 0x0 },
+ { 0x1135c0, 0x0 },
+ { 0x2135c0, 0x0 },
+ { 0x136c0, 0x0 },
+ { 0x1136c0, 0x0 },
+ { 0x2136c0, 0x0 },
+ { 0x137c0, 0x0 },
+ { 0x1137c0, 0x0 },
+ { 0x2137c0, 0x0 },
+ { 0x138c0, 0x0 },
+ { 0x1138c0, 0x0 },
+ { 0x2138c0, 0x0 },
+ { 0x100c1, 0x0 },
+ { 0x1100c1, 0x0 },
+ { 0x2100c1, 0x0 },
+ { 0x101c1, 0x0 },
+ { 0x1101c1, 0x0 },
+ { 0x2101c1, 0x0 },
+ { 0x102c1, 0x0 },
+ { 0x1102c1, 0x0 },
+ { 0x2102c1, 0x0 },
+ { 0x103c1, 0x0 },
+ { 0x1103c1, 0x0 },
+ { 0x2103c1, 0x0 },
+ { 0x104c1, 0x0 },
+ { 0x1104c1, 0x0 },
+ { 0x2104c1, 0x0 },
+ { 0x105c1, 0x0 },
+ { 0x1105c1, 0x0 },
+ { 0x2105c1, 0x0 },
+ { 0x106c1, 0x0 },
+ { 0x1106c1, 0x0 },
+ { 0x2106c1, 0x0 },
+ { 0x107c1, 0x0 },
+ { 0x1107c1, 0x0 },
+ { 0x2107c1, 0x0 },
+ { 0x108c1, 0x0 },
+ { 0x1108c1, 0x0 },
+ { 0x2108c1, 0x0 },
+ { 0x110c1, 0x0 },
+ { 0x1110c1, 0x0 },
+ { 0x2110c1, 0x0 },
+ { 0x111c1, 0x0 },
+ { 0x1111c1, 0x0 },
+ { 0x2111c1, 0x0 },
+ { 0x112c1, 0x0 },
+ { 0x1112c1, 0x0 },
+ { 0x2112c1, 0x0 },
+ { 0x113c1, 0x0 },
+ { 0x1113c1, 0x0 },
+ { 0x2113c1, 0x0 },
+ { 0x114c1, 0x0 },
+ { 0x1114c1, 0x0 },
+ { 0x2114c1, 0x0 },
+ { 0x115c1, 0x0 },
+ { 0x1115c1, 0x0 },
+ { 0x2115c1, 0x0 },
+ { 0x116c1, 0x0 },
+ { 0x1116c1, 0x0 },
+ { 0x2116c1, 0x0 },
+ { 0x117c1, 0x0 },
+ { 0x1117c1, 0x0 },
+ { 0x2117c1, 0x0 },
+ { 0x118c1, 0x0 },
+ { 0x1118c1, 0x0 },
+ { 0x2118c1, 0x0 },
+ { 0x120c1, 0x0 },
+ { 0x1120c1, 0x0 },
+ { 0x2120c1, 0x0 },
+ { 0x121c1, 0x0 },
+ { 0x1121c1, 0x0 },
+ { 0x2121c1, 0x0 },
+ { 0x122c1, 0x0 },
+ { 0x1122c1, 0x0 },
+ { 0x2122c1, 0x0 },
+ { 0x123c1, 0x0 },
+ { 0x1123c1, 0x0 },
+ { 0x2123c1, 0x0 },
+ { 0x124c1, 0x0 },
+ { 0x1124c1, 0x0 },
+ { 0x2124c1, 0x0 },
+ { 0x125c1, 0x0 },
+ { 0x1125c1, 0x0 },
+ { 0x2125c1, 0x0 },
+ { 0x126c1, 0x0 },
+ { 0x1126c1, 0x0 },
+ { 0x2126c1, 0x0 },
+ { 0x127c1, 0x0 },
+ { 0x1127c1, 0x0 },
+ { 0x2127c1, 0x0 },
+ { 0x128c1, 0x0 },
+ { 0x1128c1, 0x0 },
+ { 0x2128c1, 0x0 },
+ { 0x130c1, 0x0 },
+ { 0x1130c1, 0x0 },
+ { 0x2130c1, 0x0 },
+ { 0x131c1, 0x0 },
+ { 0x1131c1, 0x0 },
+ { 0x2131c1, 0x0 },
+ { 0x132c1, 0x0 },
+ { 0x1132c1, 0x0 },
+ { 0x2132c1, 0x0 },
+ { 0x133c1, 0x0 },
+ { 0x1133c1, 0x0 },
+ { 0x2133c1, 0x0 },
+ { 0x134c1, 0x0 },
+ { 0x1134c1, 0x0 },
+ { 0x2134c1, 0x0 },
+ { 0x135c1, 0x0 },
+ { 0x1135c1, 0x0 },
+ { 0x2135c1, 0x0 },
+ { 0x136c1, 0x0 },
+ { 0x1136c1, 0x0 },
+ { 0x2136c1, 0x0 },
+ { 0x137c1, 0x0 },
+ { 0x1137c1, 0x0 },
+ { 0x2137c1, 0x0 },
+ { 0x138c1, 0x0 },
+ { 0x1138c1, 0x0 },
+ { 0x2138c1, 0x0 },
+ { 0x10020, 0x0 },
+ { 0x110020, 0x0 },
+ { 0x210020, 0x0 },
+ { 0x11020, 0x0 },
+ { 0x111020, 0x0 },
+ { 0x211020, 0x0 },
+ { 0x12020, 0x0 },
+ { 0x112020, 0x0 },
+ { 0x212020, 0x0 },
+ { 0x13020, 0x0 },
+ { 0x113020, 0x0 },
+ { 0x213020, 0x0 },
+ { 0x20072, 0x0 },
+ { 0x20073, 0x0 },
+ { 0x20074, 0x0 },
+ { 0x100aa, 0x0 },
+ { 0x110aa, 0x0 },
+ { 0x120aa, 0x0 },
+ { 0x130aa, 0x0 },
+ { 0x20010, 0x0 },
+ { 0x120010, 0x0 },
+ { 0x220010, 0x0 },
+ { 0x20011, 0x0 },
+ { 0x120011, 0x0 },
+ { 0x220011, 0x0 },
+ { 0x100ae, 0x0 },
+ { 0x1100ae, 0x0 },
+ { 0x2100ae, 0x0 },
+ { 0x100af, 0x0 },
+ { 0x1100af, 0x0 },
+ { 0x2100af, 0x0 },
+ { 0x110ae, 0x0 },
+ { 0x1110ae, 0x0 },
+ { 0x2110ae, 0x0 },
+ { 0x110af, 0x0 },
+ { 0x1110af, 0x0 },
+ { 0x2110af, 0x0 },
+ { 0x120ae, 0x0 },
+ { 0x1120ae, 0x0 },
+ { 0x2120ae, 0x0 },
+ { 0x120af, 0x0 },
+ { 0x1120af, 0x0 },
+ { 0x2120af, 0x0 },
+ { 0x130ae, 0x0 },
+ { 0x1130ae, 0x0 },
+ { 0x2130ae, 0x0 },
+ { 0x130af, 0x0 },
+ { 0x1130af, 0x0 },
+ { 0x2130af, 0x0 },
+ { 0x20020, 0x0 },
+ { 0x120020, 0x0 },
+ { 0x220020, 0x0 },
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x0 },
+ { 0x100a2, 0x0 },
+ { 0x100a3, 0x0 },
+ { 0x100a4, 0x0 },
+ { 0x100a5, 0x0 },
+ { 0x100a6, 0x0 },
+ { 0x100a7, 0x0 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x0 },
+ { 0x110a2, 0x0 },
+ { 0x110a3, 0x0 },
+ { 0x110a4, 0x0 },
+ { 0x110a5, 0x0 },
+ { 0x110a6, 0x0 },
+ { 0x110a7, 0x0 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x0 },
+ { 0x120a2, 0x0 },
+ { 0x120a3, 0x0 },
+ { 0x120a4, 0x0 },
+ { 0x120a5, 0x0 },
+ { 0x120a6, 0x0 },
+ { 0x120a7, 0x0 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x0 },
+ { 0x130a2, 0x0 },
+ { 0x130a3, 0x0 },
+ { 0x130a4, 0x0 },
+ { 0x130a5, 0x0 },
+ { 0x130a6, 0x0 },
+ { 0x130a7, 0x0 },
+ { 0x2007c, 0x0 },
+ { 0x12007c, 0x0 },
+ { 0x22007c, 0x0 },
+ { 0x2007d, 0x0 },
+ { 0x12007d, 0x0 },
+ { 0x22007d, 0x0 },
+ { 0x400fd, 0x0 },
+ { 0x400c0, 0x0 },
+ { 0x90201, 0x0 },
+ { 0x190201, 0x0 },
+ { 0x290201, 0x0 },
+ { 0x90202, 0x0 },
+ { 0x190202, 0x0 },
+ { 0x290202, 0x0 },
+ { 0x90203, 0x0 },
+ { 0x190203, 0x0 },
+ { 0x290203, 0x0 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x90205, 0x0 },
+ { 0x190205, 0x0 },
+ { 0x290205, 0x0 },
+ { 0x90206, 0x0 },
+ { 0x190206, 0x0 },
+ { 0x290206, 0x0 },
+ { 0x90207, 0x0 },
+ { 0x190207, 0x0 },
+ { 0x290207, 0x0 },
+ { 0x90208, 0x0 },
+ { 0x190208, 0x0 },
+ { 0x290208, 0x0 },
+ { 0x10062, 0x0 },
+ { 0x10162, 0x0 },
+ { 0x10262, 0x0 },
+ { 0x10362, 0x0 },
+ { 0x10462, 0x0 },
+ { 0x10562, 0x0 },
+ { 0x10662, 0x0 },
+ { 0x10762, 0x0 },
+ { 0x10862, 0x0 },
+ { 0x11062, 0x0 },
+ { 0x11162, 0x0 },
+ { 0x11262, 0x0 },
+ { 0x11362, 0x0 },
+ { 0x11462, 0x0 },
+ { 0x11562, 0x0 },
+ { 0x11662, 0x0 },
+ { 0x11762, 0x0 },
+ { 0x11862, 0x0 },
+ { 0x12062, 0x0 },
+ { 0x12162, 0x0 },
+ { 0x12262, 0x0 },
+ { 0x12362, 0x0 },
+ { 0x12462, 0x0 },
+ { 0x12562, 0x0 },
+ { 0x12662, 0x0 },
+ { 0x12762, 0x0 },
+ { 0x12862, 0x0 },
+ { 0x13062, 0x0 },
+ { 0x13162, 0x0 },
+ { 0x13262, 0x0 },
+ { 0x13362, 0x0 },
+ { 0x13462, 0x0 },
+ { 0x13562, 0x0 },
+ { 0x13662, 0x0 },
+ { 0x13762, 0x0 },
+ { 0x13862, 0x0 },
+ { 0x20077, 0x0 },
+ { 0x10001, 0x0 },
+ { 0x11001, 0x0 },
+ { 0x12001, 0x0 },
+ { 0x13001, 0x0 },
+ { 0x10040, 0x0 },
+ { 0x10140, 0x0 },
+ { 0x10240, 0x0 },
+ { 0x10340, 0x0 },
+ { 0x10440, 0x0 },
+ { 0x10540, 0x0 },
+ { 0x10640, 0x0 },
+ { 0x10740, 0x0 },
+ { 0x10840, 0x0 },
+ { 0x10030, 0x0 },
+ { 0x10130, 0x0 },
+ { 0x10230, 0x0 },
+ { 0x10330, 0x0 },
+ { 0x10430, 0x0 },
+ { 0x10530, 0x0 },
+ { 0x10630, 0x0 },
+ { 0x10730, 0x0 },
+ { 0x10830, 0x0 },
+ { 0x11040, 0x0 },
+ { 0x11140, 0x0 },
+ { 0x11240, 0x0 },
+ { 0x11340, 0x0 },
+ { 0x11440, 0x0 },
+ { 0x11540, 0x0 },
+ { 0x11640, 0x0 },
+ { 0x11740, 0x0 },
+ { 0x11840, 0x0 },
+ { 0x11030, 0x0 },
+ { 0x11130, 0x0 },
+ { 0x11230, 0x0 },
+ { 0x11330, 0x0 },
+ { 0x11430, 0x0 },
+ { 0x11530, 0x0 },
+ { 0x11630, 0x0 },
+ { 0x11730, 0x0 },
+ { 0x11830, 0x0 },
+ { 0x12040, 0x0 },
+ { 0x12140, 0x0 },
+ { 0x12240, 0x0 },
+ { 0x12340, 0x0 },
+ { 0x12440, 0x0 },
+ { 0x12540, 0x0 },
+ { 0x12640, 0x0 },
+ { 0x12740, 0x0 },
+ { 0x12840, 0x0 },
+ { 0x12030, 0x0 },
+ { 0x12130, 0x0 },
+ { 0x12230, 0x0 },
+ { 0x12330, 0x0 },
+ { 0x12430, 0x0 },
+ { 0x12530, 0x0 },
+ { 0x12630, 0x0 },
+ { 0x12730, 0x0 },
+ { 0x12830, 0x0 },
+ { 0x13040, 0x0 },
+ { 0x13140, 0x0 },
+ { 0x13240, 0x0 },
+ { 0x13340, 0x0 },
+ { 0x13440, 0x0 },
+ { 0x13540, 0x0 },
+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3300 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3300 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3300 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3300 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x0 },
+ { 0x90033, 0xe8 },
+ { 0x90034, 0x109 },
+ { 0x90035, 0x2 },
+ { 0x90036, 0x10 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0xb },
+ { 0x90039, 0x7c0 },
+ { 0x9003a, 0x139 },
+ { 0x9003b, 0x44 },
+ { 0x9003c, 0x633 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x14f },
+ { 0x9003f, 0x630 },
+ { 0x90040, 0x159 },
+ { 0x90041, 0x47 },
+ { 0x90042, 0x633 },
+ { 0x90043, 0x149 },
+ { 0x90044, 0x4f },
+ { 0x90045, 0x633 },
+ { 0x90046, 0x179 },
+ { 0x90047, 0x8 },
+ { 0x90048, 0xe0 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x7c8 },
+ { 0x9004c, 0x109 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x1 },
+ { 0x9004f, 0x8 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x45a },
+ { 0x90052, 0x9 },
+ { 0x90053, 0x0 },
+ { 0x90054, 0x448 },
+ { 0x90055, 0x109 },
+ { 0x90056, 0x40 },
+ { 0x90057, 0x633 },
+ { 0x90058, 0x179 },
+ { 0x90059, 0x1 },
+ { 0x9005a, 0x618 },
+ { 0x9005b, 0x109 },
+ { 0x9005c, 0x40c0 },
+ { 0x9005d, 0x633 },
+ { 0x9005e, 0x149 },
+ { 0x9005f, 0x8 },
+ { 0x90060, 0x4 },
+ { 0x90061, 0x48 },
+ { 0x90062, 0x4040 },
+ { 0x90063, 0x633 },
+ { 0x90064, 0x149 },
+ { 0x90065, 0x0 },
+ { 0x90066, 0x4 },
+ { 0x90067, 0x48 },
+ { 0x90068, 0x40 },
+ { 0x90069, 0x633 },
+ { 0x9006a, 0x149 },
+ { 0x9006b, 0x10 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x18 },
+ { 0x9006e, 0x0 },
+ { 0x9006f, 0x4 },
+ { 0x90070, 0x78 },
+ { 0x90071, 0x549 },
+ { 0x90072, 0x633 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0xd49 },
+ { 0x90075, 0x633 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x94a },
+ { 0x90078, 0x633 },
+ { 0x90079, 0x159 },
+ { 0x9007a, 0x441 },
+ { 0x9007b, 0x633 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x42 },
+ { 0x9007e, 0x633 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x1 },
+ { 0x90081, 0x633 },
+ { 0x90082, 0x149 },
+ { 0x90083, 0x0 },
+ { 0x90084, 0xe0 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0xa },
+ { 0x90087, 0x10 },
+ { 0x90088, 0x109 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x149 },
+ { 0x9008c, 0x9 },
+ { 0x9008d, 0x3c0 },
+ { 0x9008e, 0x159 },
+ { 0x9008f, 0x18 },
+ { 0x90090, 0x10 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x0 },
+ { 0x90093, 0x3c0 },
+ { 0x90094, 0x109 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x48 },
+ { 0x90098, 0x18 },
+ { 0x90099, 0x4 },
+ { 0x9009a, 0x58 },
+ { 0x9009b, 0xb },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x1 },
+ { 0x9009f, 0x10 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x5 },
+ { 0x900a2, 0x7c0 },
+ { 0x900a3, 0x109 },
+ { 0x40000, 0x811 },
+ { 0x40020, 0x880 },
+ { 0x40040, 0x0 },
+ { 0x40060, 0x0 },
+ { 0x40001, 0x4008 },
+ { 0x40021, 0x83 },
+ { 0x40041, 0x4f },
+ { 0x40061, 0x0 },
+ { 0x40002, 0x4040 },
+ { 0x40022, 0x83 },
+ { 0x40042, 0x51 },
+ { 0x40062, 0x0 },
+ { 0x40003, 0x811 },
+ { 0x40023, 0x880 },
+ { 0x40043, 0x0 },
+ { 0x40063, 0x0 },
+ { 0x40004, 0x720 },
+ { 0x40024, 0xf },
+ { 0x40044, 0x1740 },
+ { 0x40064, 0x0 },
+ { 0x40005, 0x16 },
+ { 0x40025, 0x83 },
+ { 0x40045, 0x4b },
+ { 0x40065, 0x0 },
+ { 0x40006, 0x716 },
+ { 0x40026, 0xf },
+ { 0x40046, 0x2001 },
+ { 0x40066, 0x0 },
+ { 0x40007, 0x716 },
+ { 0x40027, 0xf },
+ { 0x40047, 0x2800 },
+ { 0x40067, 0x0 },
+ { 0x40008, 0x716 },
+ { 0x40028, 0xf },
+ { 0x40048, 0xf00 },
+ { 0x40068, 0x0 },
+ { 0x40009, 0x720 },
+ { 0x40029, 0xf },
+ { 0x40049, 0x1400 },
+ { 0x40069, 0x0 },
+ { 0x4000a, 0xe08 },
+ { 0x4002a, 0xc15 },
+ { 0x4004a, 0x0 },
+ { 0x4006a, 0x0 },
+ { 0x4000b, 0x625 },
+ { 0x4002b, 0x15 },
+ { 0x4004b, 0x0 },
+ { 0x4006b, 0x0 },
+ { 0x4000c, 0x4028 },
+ { 0x4002c, 0x80 },
+ { 0x4004c, 0x0 },
+ { 0x4006c, 0x0 },
+ { 0x4000d, 0xe08 },
+ { 0x4002d, 0xc1a },
+ { 0x4004d, 0x0 },
+ { 0x4006d, 0x0 },
+ { 0x4000e, 0x625 },
+ { 0x4002e, 0x1a },
+ { 0x4004e, 0x0 },
+ { 0x4006e, 0x0 },
+ { 0x4000f, 0x4040 },
+ { 0x4002f, 0x80 },
+ { 0x4004f, 0x0 },
+ { 0x4006f, 0x0 },
+ { 0x40010, 0x2604 },
+ { 0x40030, 0x15 },
+ { 0x40050, 0x0 },
+ { 0x40070, 0x0 },
+ { 0x40011, 0x708 },
+ { 0x40031, 0x5 },
+ { 0x40051, 0x0 },
+ { 0x40071, 0x2002 },
+ { 0x40012, 0x8 },
+ { 0x40032, 0x80 },
+ { 0x40052, 0x0 },
+ { 0x40072, 0x0 },
+ { 0x40013, 0x2604 },
+ { 0x40033, 0x1a },
+ { 0x40053, 0x0 },
+ { 0x40073, 0x0 },
+ { 0x40014, 0x708 },
+ { 0x40034, 0xa },
+ { 0x40054, 0x0 },
+ { 0x40074, 0x2002 },
+ { 0x40015, 0x4040 },
+ { 0x40035, 0x80 },
+ { 0x40055, 0x0 },
+ { 0x40075, 0x0 },
+ { 0x40016, 0x60a },
+ { 0x40036, 0x15 },
+ { 0x40056, 0x1200 },
+ { 0x40076, 0x0 },
+ { 0x40017, 0x61a },
+ { 0x40037, 0x15 },
+ { 0x40057, 0x1300 },
+ { 0x40077, 0x0 },
+ { 0x40018, 0x60a },
+ { 0x40038, 0x1a },
+ { 0x40058, 0x1200 },
+ { 0x40078, 0x0 },
+ { 0x40019, 0x642 },
+ { 0x40039, 0x1a },
+ { 0x40059, 0x1300 },
+ { 0x40079, 0x0 },
+ { 0x4001a, 0x4808 },
+ { 0x4003a, 0x880 },
+ { 0x4005a, 0x0 },
+ { 0x4007a, 0x0 },
+ { 0x900a4, 0x0 },
+ { 0x900a5, 0x790 },
+ { 0x900a6, 0x11a },
+ { 0x900a7, 0x8 },
+ { 0x900a8, 0x7aa },
+ { 0x900a9, 0x2a },
+ { 0x900aa, 0x10 },
+ { 0x900ab, 0x7b2 },
+ { 0x900ac, 0x2a },
+ { 0x900ad, 0x0 },
+ { 0x900ae, 0x7c8 },
+ { 0x900af, 0x109 },
+ { 0x900b0, 0x10 },
+ { 0x900b1, 0x10 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x10 },
+ { 0x900b4, 0x2a8 },
+ { 0x900b5, 0x129 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0x370 },
+ { 0x900b8, 0x129 },
+ { 0x900b9, 0xa },
+ { 0x900ba, 0x3c8 },
+ { 0x900bb, 0x1a9 },
+ { 0x900bc, 0xc },
+ { 0x900bd, 0x408 },
+ { 0x900be, 0x199 },
+ { 0x900bf, 0x14 },
+ { 0x900c0, 0x790 },
+ { 0x900c1, 0x11a },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x18 },
+ { 0x900c5, 0xe },
+ { 0x900c6, 0x408 },
+ { 0x900c7, 0x199 },
+ { 0x900c8, 0x8 },
+ { 0x900c9, 0x8568 },
+ { 0x900ca, 0x108 },
+ { 0x900cb, 0x18 },
+ { 0x900cc, 0x790 },
+ { 0x900cd, 0x16a },
+ { 0x900ce, 0x8 },
+ { 0x900cf, 0x1d8 },
+ { 0x900d0, 0x169 },
+ { 0x900d1, 0x10 },
+ { 0x900d2, 0x8558 },
+ { 0x900d3, 0x168 },
+ { 0x900d4, 0x70 },
+ { 0x900d5, 0x788 },
+ { 0x900d6, 0x16a },
+ { 0x900d7, 0x1ff8 },
+ { 0x900d8, 0x85a8 },
+ { 0x900d9, 0x1e8 },
+ { 0x900da, 0x50 },
+ { 0x900db, 0x798 },
+ { 0x900dc, 0x16a },
+ { 0x900dd, 0x60 },
+ { 0x900de, 0x7a0 },
+ { 0x900df, 0x16a },
+ { 0x900e0, 0x8 },
+ { 0x900e1, 0x8310 },
+ { 0x900e2, 0x168 },
+ { 0x900e3, 0x8 },
+ { 0x900e4, 0xa310 },
+ { 0x900e5, 0x168 },
+ { 0x900e6, 0xa },
+ { 0x900e7, 0x408 },
+ { 0x900e8, 0x169 },
+ { 0x900e9, 0x6e },
+ { 0x900ea, 0x0 },
+ { 0x900eb, 0x68 },
+ { 0x900ec, 0x0 },
+ { 0x900ed, 0x408 },
+ { 0x900ee, 0x169 },
+ { 0x900ef, 0x0 },
+ { 0x900f0, 0x8310 },
+ { 0x900f1, 0x168 },
+ { 0x900f2, 0x0 },
+ { 0x900f3, 0xa310 },
+ { 0x900f4, 0x168 },
+ { 0x900f5, 0x1ff8 },
+ { 0x900f6, 0x85a8 },
+ { 0x900f7, 0x1e8 },
+ { 0x900f8, 0x68 },
+ { 0x900f9, 0x798 },
+ { 0x900fa, 0x16a },
+ { 0x900fb, 0x78 },
+ { 0x900fc, 0x7a0 },
+ { 0x900fd, 0x16a },
+ { 0x900fe, 0x68 },
+ { 0x900ff, 0x790 },
+ { 0x90100, 0x16a },
+ { 0x90101, 0x8 },
+ { 0x90102, 0x8b10 },
+ { 0x90103, 0x168 },
+ { 0x90104, 0x8 },
+ { 0x90105, 0xab10 },
+ { 0x90106, 0x168 },
+ { 0x90107, 0xa },
+ { 0x90108, 0x408 },
+ { 0x90109, 0x169 },
+ { 0x9010a, 0x58 },
+ { 0x9010b, 0x0 },
+ { 0x9010c, 0x68 },
+ { 0x9010d, 0x0 },
+ { 0x9010e, 0x408 },
+ { 0x9010f, 0x169 },
+ { 0x90110, 0x0 },
+ { 0x90111, 0x8b10 },
+ { 0x90112, 0x168 },
+ { 0x90113, 0x1 },
+ { 0x90114, 0xab10 },
+ { 0x90115, 0x168 },
+ { 0x90116, 0x0 },
+ { 0x90117, 0x1d8 },
+ { 0x90118, 0x169 },
+ { 0x90119, 0x80 },
+ { 0x9011a, 0x790 },
+ { 0x9011b, 0x16a },
+ { 0x9011c, 0x18 },
+ { 0x9011d, 0x7aa },
+ { 0x9011e, 0x6a },
+ { 0x9011f, 0xa },
+ { 0x90120, 0x0 },
+ { 0x90121, 0x1e9 },
+ { 0x90122, 0x8 },
+ { 0x90123, 0x8080 },
+ { 0x90124, 0x108 },
+ { 0x90125, 0xf },
+ { 0x90126, 0x408 },
+ { 0x90127, 0x169 },
+ { 0x90128, 0xc },
+ { 0x90129, 0x0 },
+ { 0x9012a, 0x68 },
+ { 0x9012b, 0x9 },
+ { 0x9012c, 0x0 },
+ { 0x9012d, 0x1a9 },
+ { 0x9012e, 0x0 },
+ { 0x9012f, 0x408 },
+ { 0x90130, 0x169 },
+ { 0x90131, 0x0 },
+ { 0x90132, 0x8080 },
+ { 0x90133, 0x108 },
+ { 0x90134, 0x8 },
+ { 0x90135, 0x7aa },
+ { 0x90136, 0x6a },
+ { 0x90137, 0x0 },
+ { 0x90138, 0x8568 },
+ { 0x90139, 0x108 },
+ { 0x9013a, 0xb7 },
+ { 0x9013b, 0x790 },
+ { 0x9013c, 0x16a },
+ { 0x9013d, 0x1f },
+ { 0x9013e, 0x0 },
+ { 0x9013f, 0x68 },
+ { 0x90140, 0x8 },
+ { 0x90141, 0x8558 },
+ { 0x90142, 0x168 },
+ { 0x90143, 0xf },
+ { 0x90144, 0x408 },
+ { 0x90145, 0x169 },
+ { 0x90146, 0xd },
+ { 0x90147, 0x0 },
+ { 0x90148, 0x68 },
+ { 0x90149, 0x0 },
+ { 0x9014a, 0x408 },
+ { 0x9014b, 0x169 },
+ { 0x9014c, 0x0 },
+ { 0x9014d, 0x8558 },
+ { 0x9014e, 0x168 },
+ { 0x9014f, 0x8 },
+ { 0x90150, 0x3c8 },
+ { 0x90151, 0x1a9 },
+ { 0x90152, 0x3 },
+ { 0x90153, 0x370 },
+ { 0x90154, 0x129 },
+ { 0x90155, 0x20 },
+ { 0x90156, 0x2aa },
+ { 0x90157, 0x9 },
+ { 0x90158, 0x8 },
+ { 0x90159, 0xe8 },
+ { 0x9015a, 0x109 },
+ { 0x9015b, 0x0 },
+ { 0x9015c, 0x8140 },
+ { 0x9015d, 0x10c },
+ { 0x9015e, 0x10 },
+ { 0x9015f, 0x8138 },
+ { 0x90160, 0x104 },
+ { 0x90161, 0x8 },
+ { 0x90162, 0x448 },
+ { 0x90163, 0x109 },
+ { 0x90164, 0xf },
+ { 0x90165, 0x7c0 },
+ { 0x90166, 0x109 },
+ { 0x90167, 0x0 },
+ { 0x90168, 0xe8 },
+ { 0x90169, 0x109 },
+ { 0x9016a, 0x47 },
+ { 0x9016b, 0x630 },
+ { 0x9016c, 0x109 },
+ { 0x9016d, 0x8 },
+ { 0x9016e, 0x618 },
+ { 0x9016f, 0x109 },
+ { 0x90170, 0x8 },
+ { 0x90171, 0xe0 },
+ { 0x90172, 0x109 },
+ { 0x90173, 0x0 },
+ { 0x90174, 0x7c8 },
+ { 0x90175, 0x109 },
+ { 0x90176, 0x8 },
+ { 0x90177, 0x8140 },
+ { 0x90178, 0x10c },
+ { 0x90179, 0x0 },
+ { 0x9017a, 0x478 },
+ { 0x9017b, 0x109 },
+ { 0x9017c, 0x0 },
+ { 0x9017d, 0x1 },
+ { 0x9017e, 0x8 },
+ { 0x9017f, 0x8 },
+ { 0x90180, 0x4 },
+ { 0x90181, 0x0 },
+ { 0x90006, 0x8 },
+ { 0x90007, 0x7c8 },
+ { 0x90008, 0x109 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x400 },
+ { 0x9000b, 0x106 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x9001f, 0x29 },
+ { 0x90026, 0x68 },
+ { 0x400d0, 0x0 },
+ { 0x400d1, 0x101 },
+ { 0x400d2, 0x105 },
+ { 0x400d3, 0x107 },
+ { 0x400d4, 0x10f },
+ { 0x400d5, 0x202 },
+ { 0x400d6, 0x20a },
+ { 0x400d7, 0x20b },
+ { 0x2003a, 0x2 },
+ { 0x200be, 0x3 },
+ { 0x2000b, 0x34b },
+ { 0x2000c, 0xbb },
+ { 0x2000d, 0x753 },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0x70 },
+ { 0x12000c, 0x19 },
+ { 0x12000d, 0xfa },
+ { 0x12000e, 0x10 },
+ { 0x22000b, 0x1c },
+ { 0x22000c, 0x6 },
+ { 0x22000d, 0x3e },
+ { 0x22000e, 0x10 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0x2060 },
+ { 0x90013, 0x6152 },
+ { 0x20010, 0x5a },
+ { 0x20011, 0x3 },
+ { 0x40080, 0xe0 },
+ { 0x40081, 0x12 },
+ { 0x40082, 0xe0 },
+ { 0x40083, 0x12 },
+ { 0x40084, 0xe0 },
+ { 0x40085, 0x12 },
+ { 0x140080, 0xe0 },
+ { 0x140081, 0x12 },
+ { 0x140082, 0xe0 },
+ { 0x140083, 0x12 },
+ { 0x140084, 0xe0 },
+ { 0x140085, 0x12 },
+ { 0x240080, 0xe0 },
+ { 0x240081, 0x12 },
+ { 0x240082, 0xe0 },
+ { 0x240083, 0x12 },
+ { 0x240084, 0xe0 },
+ { 0x240085, 0x12 },
+ { 0x400fd, 0xf },
+ { 0x10011, 0x1 },
+ { 0x10012, 0x1 },
+ { 0x10013, 0x180 },
+ { 0x10018, 0x1 },
+ { 0x10002, 0x6209 },
+ { 0x100b2, 0x1 },
+ { 0x101b4, 0x1 },
+ { 0x102b4, 0x1 },
+ { 0x103b4, 0x1 },
+ { 0x104b4, 0x1 },
+ { 0x105b4, 0x1 },
+ { 0x106b4, 0x1 },
+ { 0x107b4, 0x1 },
+ { 0x108b4, 0x1 },
+ { 0x11011, 0x1 },
+ { 0x11012, 0x1 },
+ { 0x11013, 0x180 },
+ { 0x11018, 0x1 },
+ { 0x11002, 0x6209 },
+ { 0x110b2, 0x1 },
+ { 0x111b4, 0x1 },
+ { 0x112b4, 0x1 },
+ { 0x113b4, 0x1 },
+ { 0x114b4, 0x1 },
+ { 0x115b4, 0x1 },
+ { 0x116b4, 0x1 },
+ { 0x117b4, 0x1 },
+ { 0x118b4, 0x1 },
+ { 0x12011, 0x1 },
+ { 0x12012, 0x1 },
+ { 0x12013, 0x180 },
+ { 0x12018, 0x1 },
+ { 0x12002, 0x6209 },
+ { 0x120b2, 0x1 },
+ { 0x121b4, 0x1 },
+ { 0x122b4, 0x1 },
+ { 0x123b4, 0x1 },
+ { 0x124b4, 0x1 },
+ { 0x125b4, 0x1 },
+ { 0x126b4, 0x1 },
+ { 0x127b4, 0x1 },
+ { 0x128b4, 0x1 },
+ { 0x13011, 0x1 },
+ { 0x13012, 0x1 },
+ { 0x13013, 0x180 },
+ { 0x13018, 0x1 },
+ { 0x13002, 0x6209 },
+ { 0x130b2, 0x1 },
+ { 0x131b4, 0x1 },
+ { 0x132b4, 0x1 },
+ { 0x133b4, 0x1 },
+ { 0x134b4, 0x1 },
+ { 0x135b4, 0x1 },
+ { 0x136b4, 0x1 },
+ { 0x137b4, 0x1 },
+ { 0x138b4, 0x1 },
+ { 0x20089, 0x1 },
+ { 0x20088, 0x19 },
+ { 0xc0080, 0x2 },
+ { 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 3000mts 1D */
+ .drate = 3000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 3000mts 2D */
+ .drate = 3000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 3000, 400, 100, },
+};
diff --git a/board/emcraft/imx8mp_navqp/spl.c b/board/emcraft/imx8mp_navqp/spl.c
new file mode 100644
index 0000000..7f30f3a
--- /dev/null
+++ b/board/emcraft/imx8mp_navqp/spl.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2018-2019, 2021 NXP
+ * Copyright 2024 Gilles Talis <gilles.talis@gmail.com>
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mp_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/sections.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <power/pca9450.h>
+#include <power/pmic.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+ return BOOT_DEVICE_BOOTROM;
+}
+
+void spl_dram_init(void)
+{
+ ddr_init(&dram_timing);
+}
+
+void spl_board_init(void)
+{
+ /*
+ * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
+ * not allow to change it. Should set the clock after PMIC
+ * setting done. Default is 400Mhz (system_pll1_800m with div = 2)
+ * set by ROM for ND VDD_SOC
+ */
+ clock_enable(CCGR_GIC, 0);
+ clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
+ clock_enable(CCGR_GIC, 1);
+
+ puts("Normal Boot\n");
+}
+
+int power_init_board(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = pmic_get("pmic@25", &dev);
+ if (ret == -ENODEV) {
+ puts("Failed to get PMIC\n");
+ return 0;
+ }
+ if (ret != 0)
+ return ret;
+
+ /* BUCKxOUT_DVS0/1 control BUCK123 output */
+ pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
+
+ /*
+ * Increase VDD_SOC to typical value 0.95V before first
+ * DRAM access, set DVS1 to 0.85V for suspend.
+ * Enable DVS control through PMIC_STBY_REQ and
+ * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
+ */
+ if (CONFIG_IS_ENABLED(IMX8M_VDD_SOC_850MV))
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
+ else
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
+
+ /* Set DVS1 to 0.85v for suspend. */
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
+
+ /*
+ * Enable DVS control through PMIC_STBY_REQ and
+ * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H).
+ */
+ pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
+
+ /*
+ * Kernel uses OD/OD freq for SOC.
+ * To avoid timing risk from SOC to ARM,increase VDD_ARM to OD
+ * voltage 0.95V.
+ */
+ pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C);
+
+ return 0;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+ if (is_imx8mp() &&
+ !strcmp(name, "imx8mp-navqp"))
+ return 0;
+
+ return -EINVAL;
+}
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ arch_cpu_init();
+
+ init_uart_clk(1);
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ ret = spl_init();
+ if (ret) {
+ debug("spl_init() failed: %d\n", ret);
+ hang();
+ }
+
+ preloader_console_init();
+
+ enable_tzc380();
+
+ power_init_board();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ board_init_r(NULL, 0);
+}
diff --git a/board/emulation/qemu-arm/MAINTAINERS b/board/emulation/qemu-arm/MAINTAINERS
index 5154262..7bc0ee6 100644
--- a/board/emulation/qemu-arm/MAINTAINERS
+++ b/board/emulation/qemu-arm/MAINTAINERS
@@ -4,5 +4,7 @@
F: board/emulation/qemu-arm/
F: board/emulation/common/
F: include/configs/qemu-arm.h
+F: include/configs/qemu-sbsa.h
F: configs/qemu_arm_defconfig
F: configs/qemu_arm64_defconfig
+F: configs/qemu-arm-sbsa_defconfig
diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig
index 9538c66..012ac14 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -58,6 +58,8 @@
imply E1000
imply PCI
imply NVME_PCI
+ imply VIDEO
+ imply VIDEO_SIMPLE
imply PCIE_ECAM_GENERIC
imply DM_RNG
imply DM_RTC
diff --git a/board/emulation/qemu-sbsa/Kconfig b/board/emulation/qemu-sbsa/Kconfig
new file mode 100644
index 0000000..72c76b3
--- /dev/null
+++ b/board/emulation/qemu-sbsa/Kconfig
@@ -0,0 +1,59 @@
+if TARGET_QEMU_ARM_SBSA
+
+config SYS_SOC
+ default "qemu-sbsa"
+
+config TEXT_BASE
+ default 0x10000100000
+
+config SYS_LOAD_ADDR
+ default 0x10000100000
+
+config PRE_CON_BUF_ADDR
+ default 0x100000FF000
+
+config DEFAULT_DEVICE_TREE
+ default "qemu-sbsa"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select AHCI
+ select ACPIGEN
+ select ACPI
+ select BLOBLIST
+ select CPU
+ select CPU_ARMV8
+ select DM
+ select DM_USB
+ select DM_MTD
+ select GENERATE_ACPI_TABLE
+ select HAS_ROM
+ select MTD
+ select OF_LIBFDT_OVERLAY
+ select OF_SEPARATE
+ select PCI
+ select PCIE_ECAM_GENERIC
+ select USB
+ select GIC_V3
+ select GIC_V3_ITS
+ select SYS_FLASH_CFI_WIDTH_16BIT
+ imply AHCI_GENERIC
+ imply USB_XHCI_HCD
+ imply USB_XHCI_GENERIC
+ imply USB_STORAGE
+ imply E1000
+ imply E1000_NO_NVM
+ imply NET_RANDOM_ETHADDR
+ imply VIDEO_BOCHS
+ imply CFI_FLASH
+ imply SYS_MTDPARTS_RUNTIME
+ imply SET_DFU_ALT_INFO
+
+if DEBUG_UART
+
+config DEBUG_UART_BASE
+ default 0x60000000
+endif
+
+source "board/emulation/common/Kconfig"
+endif
diff --git a/board/emulation/qemu-sbsa/Makefile b/board/emulation/qemu-sbsa/Makefile
new file mode 100644
index 0000000..bacae32
--- /dev/null
+++ b/board/emulation/qemu-sbsa/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += qemu-sbsa.o
+obj-y += lowlevel_init.o
+obj-y += smc.o
+
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt_generated.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o
diff --git a/board/emulation/qemu-sbsa/acpi.c b/board/emulation/qemu-sbsa/acpi.c
new file mode 100644
index 0000000..ba85e08
--- /dev/null
+++ b/board/emulation/qemu-sbsa/acpi.c
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024 9elements GmbH
+ */
+
+#include <cpu.h>
+#include <tables_csum.h>
+#include <string.h>
+#include <acpi/acpi_table.h>
+#include <asm/acpi_table.h>
+#include <asm/armv8/sec_firmware.h>
+#include <configs/qemu-sbsa.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include "qemu-sbsa.h"
+
+#define SBSAQEMU_MADT_GIC_VBASE 0x2c020000
+#define SBSAQEMU_MADT_GIC_HBASE 0x2c010000
+#define SBSAQEMU_MADT_GIC_PMU_IRQ 23
+
+#define SBSA_PLATFORM_WATCHDOG_COUNT 1
+#define SBSA_PLATFORM_TIMER_COUNT (SBSA_PLATFORM_WATCHDOG_COUNT)
+
+#define L2_ATTRIBUTES (ACPI_PPTT_READ_ALLOC | ACPI_PPTT_WRITE_ALLOC | \
+ (ACPI_PPTT_CACHE_TYPE_UNIFIED << \
+ ACPI_PPTT_CACHE_TYPE_SHIFT))
+#define L2_SIZE 0x80000
+#define L2_SETS 0x400
+#define L2_WAYS 8
+
+#define L1D_ATTRIBUTES (ACPI_PPTT_READ_ALLOC | ACPI_PPTT_WRITE_ALLOC | \
+ (ACPI_PPTT_CACHE_TYPE_DATA << \
+ ACPI_PPTT_CACHE_TYPE_SHIFT))
+#define L1D_SIZE 0x8000
+#define L1D_SETS 0x100
+#define L1D_WAYS 2
+
+#define L1I_ATTRIBUTES (ACPI_PPTT_READ_ALLOC | \
+ (ACPI_PPTT_CACHE_TYPE_INSTR << \
+ ACPI_PPTT_CACHE_TYPE_SHIFT))
+#define L1I_SIZE 0x8000
+#define L1I_SETS 0x100
+#define L1I_WAYS 2
+
+int acpi_fill_iort(struct acpi_ctx *ctx)
+{
+ u32 its_offset, smmu_offset;
+ u64 gic_its_base = 0;
+
+ smc_get_gic_its_base(&gic_its_base);
+ if (gic_its_base == 0)
+ return 0;
+
+ u32 identifiers[] = { 0 };
+
+ its_offset = acpi_iort_add_its_group(ctx, ARRAY_SIZE(identifiers),
+ identifiers);
+
+ struct acpi_iort_id_mapping map_smmu[] = {{
+ 0, 0xffff, 0, its_offset, 0
+ }};
+
+ smmu_offset = acpi_iort_add_smmu_v3(ctx,
+ SBSA_SMMU_BASE_ADDR, // Base address
+ ACPI_IORT_SMMU_V3_COHACC_OVERRIDE, // Flags
+ 0, // VATOS address
+ 0, // SMMUv3 Model
+ 74, // Event
+ 75, // Pri
+ 77, // Gerror
+ 76, // Sync
+ 0, // Proximity domain
+ 1, // DevIDMappingIndex
+ ARRAY_SIZE(map_smmu),
+ map_smmu);
+
+ struct acpi_iort_id_mapping map_rc[] = {{
+ 0, 0xffff, 0, smmu_offset, 0
+ }};
+
+ acpi_iort_add_rc(ctx,
+ BIT(0) | BIT(56), // CacheCoherent + CPM
+ 0, // AtsAttribute
+ 0, // PciSegmentNumber
+ 64, // MemoryAddressSizeLimit
+ ARRAY_SIZE(map_rc),
+ map_rc);
+ return 0;
+}
+
+void acpi_fill_fadt(struct acpi_fadt *fadt)
+{
+ fadt->flags = ACPI_FADT_HW_REDUCED_ACPI | ACPI_FADT_LOW_PWR_IDLE_S0;
+ fadt->preferred_pm_profile = ACPI_PM_PERFORMANCE_SERVER;
+ fadt->arm_boot_arch = ACPI_ARM_PSCI_COMPLIANT;
+}
+
+int acpi_fill_mcfg(struct acpi_ctx *ctx)
+{
+ size_t size;
+
+ /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */
+ size = acpi_create_mcfg_mmconfig((void *)ctx->current,
+ SBSA_PCIE_ECAM_BASE_ADDR, 0, 0, 255);
+ acpi_inc(ctx, size);
+
+ return 0;
+}
+
+static int sbsa_write_gtdt(struct acpi_ctx *ctx, const struct acpi_writer *entry)
+{
+ struct acpi_table_header *header;
+ struct acpi_gtdt *gtdt;
+
+ gtdt = ctx->current;
+ header = >dt->header;
+
+ memset(gtdt, '\0', sizeof(struct acpi_gtdt));
+
+ acpi_fill_header(header, "GTDT");
+ header->length = sizeof(struct acpi_gtdt);
+ header->revision = acpi_get_table_revision(ACPITAB_GTDT);
+
+ gtdt->cnt_ctrl_base = 0xFFFFFFFFFFFFFFFF;
+ gtdt->sec_el1_gsiv = 29;
+ gtdt->sec_el1_flags = GTDT_FLAG_INT_ACTIVE_LOW;
+ gtdt->el1_gsiv = 30;
+ gtdt->el1_flags = GTDT_FLAG_INT_ACTIVE_LOW;
+ gtdt->virt_el1_gsiv = 27;
+ gtdt->virt_el1_flags = GTDT_FLAG_INT_ACTIVE_LOW;
+ gtdt->el2_gsiv = 26;
+ gtdt->el2_flags = GTDT_FLAG_INT_ACTIVE_LOW;
+ gtdt->cnt_read_base = 0xffffffffffffffff;
+
+ // FIXME: VirtualPL2Timer
+ header->checksum = table_compute_checksum(header, header->length);
+
+ acpi_add_table(ctx, gtdt);
+
+ acpi_inc(ctx, sizeof(struct acpi_gtdt));
+
+ return 0;
+};
+
+ACPI_WRITER(5gtdt, "GTDT", sbsa_write_gtdt, 0);
+
+static int acpi_write_pptt(struct acpi_ctx *ctx, const struct acpi_writer *entry)
+{
+ struct acpi_table_header *header;
+ int cluster_offset, l2_offset;
+ u32 offsets[2];
+
+ header = ctx->current;
+ ctx->tab_start = ctx->current;
+
+ memset(header, '\0', sizeof(struct acpi_table_header));
+
+ acpi_fill_header(header, "PPTT");
+ header->revision = acpi_get_table_revision(ACPITAB_PPTT);
+ acpi_inc(ctx, sizeof(*header));
+
+ cluster_offset = acpi_pptt_add_proc(ctx, ACPI_PPTT_PHYSICAL_PACKAGE |
+ ACPI_PPTT_CHILDREN_IDENTICAL,
+ 0, 0, 0, NULL);
+
+ l2_offset = acpi_pptt_add_cache(ctx, ACPI_PPTT_ALL_VALID, 0, L2_SIZE,
+ L2_SETS, L2_WAYS, L2_ATTRIBUTES, 64);
+
+ offsets[0] = acpi_pptt_add_cache(ctx, ACPI_PPTT_ALL_VALID, l2_offset,
+ L1D_SIZE, L1D_SETS, L1D_WAYS,
+ L1D_ATTRIBUTES, 64);
+
+ offsets[1] = acpi_pptt_add_cache(ctx, ACPI_PPTT_ALL_BUT_WRITE_POL,
+ l2_offset, L1I_SIZE, L1I_SETS,
+ L1I_WAYS, L1I_ATTRIBUTES, 64);
+
+ for (int i = 0; i < uclass_id_count(UCLASS_CPU); i++) {
+ acpi_pptt_add_proc(ctx, ACPI_PPTT_CHILDREN_IDENTICAL |
+ ACPI_PPTT_NODE_IS_LEAF | ACPI_PPTT_PROC_ID_VALID,
+ cluster_offset, i, 2, offsets);
+ }
+
+ header->length = ctx->current - ctx->tab_start;
+ header->checksum = table_compute_checksum(header, header->length);
+
+ acpi_inc(ctx, header->length);
+ acpi_add_table(ctx, header);
+
+ return 0;
+};
+
+ACPI_WRITER(5pptt, "PPTT", acpi_write_pptt, 0);
diff --git a/board/emulation/qemu-sbsa/dsdt.asl b/board/emulation/qemu-sbsa/dsdt.asl
new file mode 100644
index 0000000..f12cca0
--- /dev/null
+++ b/board/emulation/qemu-sbsa/dsdt.asl
@@ -0,0 +1,483 @@
+/** @file
+* Differentiated System Description Table Fields (DSDT).
+*
+* Copyright (c) 2020, Linaro Ltd. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <configs/qemu-sbsa.h>
+
+#define LINK_DEVICE(Uid, LinkName, Irq) \
+ Device (LinkName) { \
+ Name (_HID, EISAID("PNP0C0F")) \
+ Name (_UID, Uid) \
+ Name (_PRS, ResourceTemplate() { \
+ Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive) { Irq } \
+ }) \
+ Method (_STA) { \
+ Return (0xF) \
+ } \
+ Method (_CRS, 0) { Return (_PRS) } \
+ Method (_SRS, 1) { } \
+ Method (_DIS) { } \
+ }
+
+#define PRT_ENTRY(Address, Pin, Link) \
+ Package (4) { \
+ Address, Pin, Link, Zero \
+ }
+
+DefinitionBlock ("Dsdt.aml", "DSDT", 2, "U-Boot", "SBSAQEMU", 2) {
+ Scope (_SB) {
+ // UART PL011
+ Device (COM0) {
+ Name (_HID, "ARMH0011")
+ Name (_UID, Zero)
+ Name (_CRS, ResourceTemplate () {
+ Memory32Fixed (ReadWrite,
+ SBSA_UART_BASE_ADDR,
+ SBSA_UART_LENGTH)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 33 }
+ })
+ Method (_STA) {
+ Return (0xF)
+ }
+ }
+
+ // AHCI Host Controller
+ Device (AHC0) {
+ Name (_HID, "LNRO001E")
+ Name (_CLS, Package (3) {
+ 0x01,
+ 0x06,
+ 0x01,
+ })
+ Name (_CCA, 1)
+ Name (_CRS, ResourceTemplate() {
+ Memory32Fixed (ReadWrite,
+ SBSA_AHCI_BASE_ADDR,
+ SBSA_AHCI_LENGTH)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 42 }
+ })
+ Method (_STA) {
+ Return (0xF)
+ }
+ }
+
+
+ // USB XHCI Host Controller
+ Device (USB0) {
+ Name (_HID, "PNP0D10") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (XHCI, 0xF) // will be set using AcpiLib
+ Method (_STA) {
+ Return (XHCI)
+ }
+ Name (_CRS, ResourceTemplate() {
+ Memory32Fixed (ReadWrite,
+ SBSA_XHCI_BASE_ADDR,
+ SBSA_XHCI_LENGTH)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 43 }
+ })
+
+ // Root Hub
+ Device (RHUB) {
+ Name (_ADR, 0x00000000) // Address of Root Hub should be 0 as per ACPI 5.0 spec
+ Method (_STA) {
+ Return (0xF)
+ }
+
+ // Ports connected to Root Hub
+ Device (HUB1) {
+ Name (_ADR, 0x00000001)
+ Name (_UPC, Package() {
+ 0x00, // Port is NOT connectable
+ 0xFF, // Don't care
+ 0x00000000, // Reserved 0 must be zero
+ 0x00000000 // Reserved 1 must be zero
+ })
+ Method (_STA) {
+ Return (0xF)
+ }
+
+ Device (PRT1) {
+ Name (_ADR, 0x00000001)
+ Name (_UPC, Package() {
+ 0xFF, // Port is connectable
+ 0x00, // Port connector is A
+ 0x00000000,
+ 0x00000000
+ })
+ Name (_PLD, Package() {
+ Buffer(0x10) {
+ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }
+ })
+ Method (_STA) {
+ Return (0xF)
+ }
+ } // USB0_RHUB_HUB1_PRT1
+ Device (PRT2) {
+ Name (_ADR, 0x00000002)
+ Name (_UPC, Package() {
+ 0xFF, // Port is connectable
+ 0x00, // Port connector is A
+ 0x00000000,
+ 0x00000000
+ })
+ Name (_PLD, Package() {
+ Buffer(0x10) {
+ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }
+ })
+ Method (_STA) {
+ Return (0xF)
+ }
+ } // USB0_RHUB_HUB1_PRT2
+
+ Device (PRT3) {
+ Name (_ADR, 0x00000003)
+ Name (_UPC, Package() {
+ 0xFF, // Port is connectable
+ 0x09, // Type C connector - USB2 and SS with Switch
+ 0x00000000,
+ 0x00000000
+ })
+ Name (_PLD, Package() {
+ Buffer (0x10) {
+ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }
+ })
+ Method (_STA) {
+ Return (0xF)
+ }
+ } // USB0_RHUB_HUB1_PRT3
+
+ Device (PRT4) {
+ Name (_ADR, 0x00000004)
+ Name (_UPC, Package() {
+ 0xFF, // Port is connectable
+ 0x09, // Type C connector - USB2 and SS with Switch
+ 0x00000000,
+ 0x00000000
+ })
+ Name (_PLD, Package() {
+ Buffer (0x10){
+ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }
+ })
+ Method (_STA) {
+ Return (0xF)
+ }
+ } // USB0_RHUB_HUB1_PRT4
+ } // USB0_RHUB_HUB1
+ } // USB0_RHUB
+ } // USB0
+
+ Device (PCI0)
+ {
+ Name (_HID, EISAID ("PNP0A08")) // PCI Express Root Bridge
+ Name (_CID, EISAID ("PNP0A03")) // Compatible PCI Root Bridge
+ Name (_SEG, Zero) // PCI Segment Group number
+ Name (_BBN, Zero) // PCI Base Bus Number
+ Name (_UID, "PCI0")
+ Name (_CCA, One) // Initially mark the PCI coherent (for JunoR1)
+
+ Method (_STA) {
+ Return (0xF)
+ }
+
+ Method (_CBA, 0, NotSerialized) {
+ return (SBSA_PCIE_ECAM_BASE_ADDR)
+ }
+
+ LINK_DEVICE(0, GSI0, 0x23)
+ LINK_DEVICE(1, GSI1, 0x24)
+ LINK_DEVICE(2, GSI2, 0x25)
+ LINK_DEVICE(3, GSI3, 0x26)
+
+ Name (_PRT, Package () // _PRT: PCI Routing Table
+ {
+ PRT_ENTRY(0x0000FFFF, 0, GSI0),
+ PRT_ENTRY(0x0000FFFF, 0, GSI1),
+ PRT_ENTRY(0x0000FFFF, 0, GSI2),
+ PRT_ENTRY(0x0000FFFF, 0, GSI3),
+
+ PRT_ENTRY(0x0001FFFF, 0, GSI1),
+ PRT_ENTRY(0x0001FFFF, 1, GSI2),
+ PRT_ENTRY(0x0001FFFF, 2, GSI3),
+ PRT_ENTRY(0x0001FFFF, 3, GSI0),
+
+ PRT_ENTRY(0x0002FFFF, 0, GSI2),
+ PRT_ENTRY(0x0002FFFF, 1, GSI3),
+ PRT_ENTRY(0x0002FFFF, 2, GSI0),
+ PRT_ENTRY(0x0002FFFF, 3, GSI1),
+
+ PRT_ENTRY(0x0003FFFF, 0, GSI3),
+ PRT_ENTRY(0x0003FFFF, 1, GSI0),
+ PRT_ENTRY(0x0003FFFF, 2, GSI1),
+ PRT_ENTRY(0x0003FFFF, 3, GSI2),
+
+ PRT_ENTRY(0x0004FFFF, 0, GSI0),
+ PRT_ENTRY(0x0004FFFF, 1, GSI1),
+ PRT_ENTRY(0x0004FFFF, 2, GSI2),
+ PRT_ENTRY(0x0004FFFF, 3, GSI3),
+
+ PRT_ENTRY(0x0005FFFF, 0, GSI1),
+ PRT_ENTRY(0x0005FFFF, 1, GSI2),
+ PRT_ENTRY(0x0005FFFF, 2, GSI3),
+ PRT_ENTRY(0x0005FFFF, 3, GSI0),
+
+ PRT_ENTRY(0x0006FFFF, 0, GSI2),
+ PRT_ENTRY(0x0006FFFF, 1, GSI3),
+ PRT_ENTRY(0x0006FFFF, 2, GSI0),
+ PRT_ENTRY(0x0006FFFF, 3, GSI1),
+
+ PRT_ENTRY(0x0007FFFF, 0, GSI3),
+ PRT_ENTRY(0x0007FFFF, 1, GSI0),
+ PRT_ENTRY(0x0007FFFF, 2, GSI1),
+ PRT_ENTRY(0x0007FFFF, 3, GSI2),
+
+ PRT_ENTRY(0x0008FFFF, 0, GSI0),
+ PRT_ENTRY(0x0008FFFF, 1, GSI1),
+ PRT_ENTRY(0x0008FFFF, 2, GSI2),
+ PRT_ENTRY(0x0008FFFF, 3, GSI3),
+
+ PRT_ENTRY(0x0009FFFF, 0, GSI1),
+ PRT_ENTRY(0x0009FFFF, 1, GSI2),
+ PRT_ENTRY(0x0009FFFF, 2, GSI3),
+ PRT_ENTRY(0x0009FFFF, 3, GSI0),
+
+ PRT_ENTRY(0x000AFFFF, 0, GSI2),
+ PRT_ENTRY(0x000AFFFF, 1, GSI3),
+ PRT_ENTRY(0x000AFFFF, 2, GSI0),
+ PRT_ENTRY(0x000AFFFF, 3, GSI1),
+
+ PRT_ENTRY(0x000BFFFF, 0, GSI3),
+ PRT_ENTRY(0x000BFFFF, 1, GSI0),
+ PRT_ENTRY(0x000BFFFF, 2, GSI1),
+ PRT_ENTRY(0x000BFFFF, 3, GSI2),
+
+ PRT_ENTRY(0x000CFFFF, 0, GSI0),
+ PRT_ENTRY(0x000CFFFF, 1, GSI1),
+ PRT_ENTRY(0x000CFFFF, 2, GSI2),
+ PRT_ENTRY(0x000CFFFF, 3, GSI3),
+
+ PRT_ENTRY(0x000DFFFF, 0, GSI1),
+ PRT_ENTRY(0x000DFFFF, 1, GSI2),
+ PRT_ENTRY(0x000DFFFF, 2, GSI3),
+ PRT_ENTRY(0x000DFFFF, 3, GSI0),
+
+ PRT_ENTRY(0x000EFFFF, 0, GSI2),
+ PRT_ENTRY(0x000EFFFF, 1, GSI3),
+ PRT_ENTRY(0x000EFFFF, 2, GSI0),
+ PRT_ENTRY(0x000EFFFF, 3, GSI1),
+
+ PRT_ENTRY(0x000FFFFF, 0, GSI3),
+ PRT_ENTRY(0x000FFFFF, 1, GSI0),
+ PRT_ENTRY(0x000FFFFF, 2, GSI1),
+ PRT_ENTRY(0x000FFFFF, 3, GSI2),
+
+ PRT_ENTRY(0x0010FFFF, 0, GSI0),
+ PRT_ENTRY(0x0010FFFF, 1, GSI1),
+ PRT_ENTRY(0x0010FFFF, 2, GSI2),
+ PRT_ENTRY(0x0010FFFF, 3, GSI3),
+
+ PRT_ENTRY(0x0011FFFF, 0, GSI1),
+ PRT_ENTRY(0x0011FFFF, 1, GSI2),
+ PRT_ENTRY(0x0011FFFF, 2, GSI3),
+ PRT_ENTRY(0x0011FFFF, 3, GSI0),
+
+ PRT_ENTRY(0x0012FFFF, 0, GSI2),
+ PRT_ENTRY(0x0012FFFF, 1, GSI3),
+ PRT_ENTRY(0x0012FFFF, 2, GSI0),
+ PRT_ENTRY(0x0012FFFF, 3, GSI1),
+
+ PRT_ENTRY(0x0013FFFF, 0, GSI3),
+ PRT_ENTRY(0x0013FFFF, 1, GSI0),
+ PRT_ENTRY(0x0013FFFF, 2, GSI1),
+ PRT_ENTRY(0x0013FFFF, 3, GSI2),
+
+ PRT_ENTRY(0x0014FFFF, 0, GSI0),
+ PRT_ENTRY(0x0014FFFF, 1, GSI1),
+ PRT_ENTRY(0x0014FFFF, 2, GSI2),
+ PRT_ENTRY(0x0014FFFF, 3, GSI3),
+
+ PRT_ENTRY(0x0015FFFF, 0, GSI1),
+ PRT_ENTRY(0x0015FFFF, 1, GSI2),
+ PRT_ENTRY(0x0015FFFF, 2, GSI3),
+ PRT_ENTRY(0x0015FFFF, 3, GSI0),
+
+ PRT_ENTRY(0x0016FFFF, 0, GSI2),
+ PRT_ENTRY(0x0016FFFF, 1, GSI3),
+ PRT_ENTRY(0x0016FFFF, 2, GSI0),
+ PRT_ENTRY(0x0016FFFF, 3, GSI1),
+
+ PRT_ENTRY(0x0017FFFF, 0, GSI3),
+ PRT_ENTRY(0x0017FFFF, 1, GSI0),
+ PRT_ENTRY(0x0017FFFF, 2, GSI1),
+ PRT_ENTRY(0x0017FFFF, 3, GSI2),
+
+ PRT_ENTRY(0x0018FFFF, 0, GSI0),
+ PRT_ENTRY(0x0018FFFF, 1, GSI1),
+ PRT_ENTRY(0x0018FFFF, 2, GSI2),
+ PRT_ENTRY(0x0018FFFF, 3, GSI3),
+
+ PRT_ENTRY(0x0019FFFF, 0, GSI1),
+ PRT_ENTRY(0x0019FFFF, 1, GSI2),
+ PRT_ENTRY(0x0019FFFF, 2, GSI3),
+ PRT_ENTRY(0x0019FFFF, 3, GSI0),
+
+ PRT_ENTRY(0x001AFFFF, 0, GSI2),
+ PRT_ENTRY(0x001AFFFF, 1, GSI3),
+ PRT_ENTRY(0x001AFFFF, 2, GSI0),
+ PRT_ENTRY(0x001AFFFF, 3, GSI1),
+
+ PRT_ENTRY(0x001BFFFF, 0, GSI3),
+ PRT_ENTRY(0x001BFFFF, 1, GSI0),
+ PRT_ENTRY(0x001BFFFF, 2, GSI1),
+ PRT_ENTRY(0x001BFFFF, 3, GSI2),
+
+ PRT_ENTRY(0x001CFFFF, 0, GSI0),
+ PRT_ENTRY(0x001CFFFF, 1, GSI1),
+ PRT_ENTRY(0x001CFFFF, 2, GSI2),
+ PRT_ENTRY(0x001CFFFF, 3, GSI3),
+
+ PRT_ENTRY(0x001DFFFF, 0, GSI1),
+ PRT_ENTRY(0x001DFFFF, 1, GSI2),
+ PRT_ENTRY(0x001DFFFF, 2, GSI3),
+ PRT_ENTRY(0x001DFFFF, 3, GSI0),
+
+ PRT_ENTRY(0x001EFFFF, 0, GSI2),
+ PRT_ENTRY(0x001EFFFF, 1, GSI3),
+ PRT_ENTRY(0x001EFFFF, 2, GSI0),
+ PRT_ENTRY(0x001EFFFF, 3, GSI1),
+
+ PRT_ENTRY(0x001FFFFF, 0, GSI3),
+ PRT_ENTRY(0x001FFFFF, 1, GSI0),
+ PRT_ENTRY(0x001FFFFF, 2, GSI1),
+ PRT_ENTRY(0x001FFFFF, 3, GSI2),
+ })
+
+ // Root complex resources
+ Name (_CRS, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer,
+ MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 0, // AddressMinimum - Minimum Bus Number
+ 0xff,// AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 256 // RangeLength - Number of Busses
+ )
+
+ // IO to mmio window
+ QWordIO (
+ ResourceProducer, MinFixed,
+ MaxFixed, PosDecode,
+ EntireRange,
+ 0x00000000, // Granularity
+ 0x0000, // Min Base Address
+ 0xffff, // Max Base Address
+ SBSA_PIO_BASE_ADDR, // Translate
+ SBSA_PIO_LENGTH // Length
+ )
+
+ DWordMemory ( // 32-bit BAR Windows
+ ResourceProducer, PosDecode,
+ MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ SBSA_PCIE_MMIO_BASE_ADDR, // Min Base Address
+ SBSA_PCIE_MMIO_END, // Max Base Address
+ 0, // Translate
+ SBSA_PCIE_MMIO_LENGTH // Length
+ )
+
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer, PosDecode,
+ MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ SBSA_PCIE_MMIO_HIGH_BASE_ADDR, // Min Base Address
+ SBSA_PCIE_MMIO_HIGH_END, // Max Base Address
+ 0, // Translate
+ SBSA_PCIE_MMIO_HIGH_LENGTH // Length
+ )
+ }) // Name(_CRS)
+
+ Device (RES0)
+ {
+ Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ SBSA_PCIE_ECAM_BASE_ADDR, // Range Minimum
+ SBSA_PCIE_ECAM_END, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ SBSA_PCIE_ECAM_LENGTH, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+ Method (_STA) {
+ Return (0xF)
+ }
+ }
+
+ // OS Control Handoff
+ Name (SUPP, Zero) // PCI _OSC Support Field value
+ Name (CTRL, Zero) // PCI _OSC Control Field value
+
+ /*
+ * See [1] 6.2.10, [2] 4.5
+ */
+ Method (_OSC,4) {
+ // Check for proper UUID
+ If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) {
+ // Create DWord-adressable fields from the Capabilities Buffer
+ CreateDWordField (Arg3,0,CDW1)
+ CreateDWordField (Arg3,4,CDW2)
+ CreateDWordField (Arg3,8,CDW3)
+
+ // Save Capabilities DWord2 & 3
+ Store (CDW2,SUPP)
+ Store (CDW3,CTRL)
+
+ // Only allow native hot plug control if OS supports:
+ // * ASPM
+ // * Clock PM
+ // * MSI/MSI-X
+ If ((SUPP & 0x16) != 0x16) {
+ CTRL &= 0x1E // Mask bit 0 (and undefined bits)
+ }
+
+ // Always allow native PME, AER (no dependencies)
+
+ // Never allow SHPC (no SHPC controller in this system)
+ CTRL &= 0x1D
+
+ If (Arg1 != One) { // Unknown revision
+ CDW1 |= 0x08
+ }
+
+ If (CDW3 != CTRL) { // Capabilities bits were masked
+ CDW1 |= 0x10
+ }
+
+ // Update DWORD3 in the buffer
+ Store (CTRL,CDW3)
+ Return (Arg3)
+ } Else {
+ CDW1 |= 4 // Unrecognized UUID
+ Return (Arg3)
+ }
+ } // End _OSC
+ }
+ } // Scope (_SB)
+}
diff --git a/board/emulation/qemu-sbsa/lowlevel_init.S b/board/emulation/qemu-sbsa/lowlevel_init.S
new file mode 100644
index 0000000..c997721
--- /dev/null
+++ b/board/emulation/qemu-sbsa/lowlevel_init.S
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016
+ * Cédric Schieli <cschieli@gmail.com>
+ */
+
+#include <config.h>
+
+/*
+ * Routine: save_boot_params (called after reset from start.S)
+ * Description: save ATAG/FDT address provided by the firmware at boot time
+ */
+
+.global save_boot_params
+save_boot_params:
+ /* The firmware provided ATAG/FDT address can be found in r2/x0 */
+ adr x8, fw_dtb_pointer
+ str x0, [x8]
+
+
+ /* Returns */
+ b save_boot_params_ret
diff --git a/board/emulation/qemu-sbsa/qemu-sbsa.c b/board/emulation/qemu-sbsa/qemu-sbsa.c
new file mode 100644
index 0000000..3943c92
--- /dev/null
+++ b/board/emulation/qemu-sbsa/qemu-sbsa.c
@@ -0,0 +1,273 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Tuomas Tynkkynen
+ */
+
+#include <cpu_func.h>
+#include <dm.h>
+#include <env.h>
+#include <fdtdec.h>
+#include <fdt_support.h>
+#include <init.h>
+#include <log.h>
+#include <usb.h>
+#include <asm/armv8/mmu.h>
+
+#include "qemu-sbsa.h"
+
+/* Assigned in lowlevel_init.S
+ * Push the variable into the .data section so that it
+ * does not get cleared later.
+ */
+unsigned long __section(".data") fw_dtb_pointer;
+
+static struct mm_region qemu_sbsa_mem_map[] = {
+ {
+ /* Secure flash */
+ .virt = SBSA_SECURE_FLASH_BASE_ADDR,
+ .phys = SBSA_SECURE_FLASH_BASE_ADDR,
+ .size = SBSA_SECURE_FLASH_LENGTH,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_INNER_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* Flash */
+ .virt = SBSA_FLASH_BASE_ADDR,
+ .phys = SBSA_FLASH_BASE_ADDR,
+ .size = SBSA_FLASH_LENGTH,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* Lowmem peripherals */
+ .virt = SBSA_PERIPH_BASE_ADDR,
+ .phys = SBSA_PERIPH_BASE_ADDR,
+ .size = SBSA_PCIE_MMIO_BASE_ADDR - SBSA_PERIPH_BASE_ADDR,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* 32-bit address PCIE MMIO space */
+ .virt = SBSA_PCIE_MMIO_BASE_ADDR,
+ .phys = SBSA_PCIE_MMIO_BASE_ADDR,
+ .size = SBSA_PCIE_MMIO_LENGTH,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* PCI-E ECAM memory area */
+ .virt = SBSA_PCIE_ECAM_BASE_ADDR,
+ .phys = SBSA_PCIE_ECAM_BASE_ADDR,
+ .size = SBSA_PCIE_ECAM_LENGTH,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* Highmem PCI-E MMIO memory area */
+ .virt = SBSA_PCIE_MMIO_HIGH_BASE_ADDR,
+ .phys = SBSA_PCIE_MMIO_HIGH_BASE_ADDR,
+ .size = SBSA_PCIE_MMIO_HIGH_LENGTH,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* DRAM */
+ .virt = SBSA_MEM_BASE_ADDR,
+ .phys = SBSA_MEM_BASE_ADDR,
+ .size = 0x800000000000ULL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = qemu_sbsa_mem_map;
+
+int board_late_init(void)
+{
+ /* start usb so that usb keyboard can be used as input device */
+ if (CONFIG_IS_ENABLED(USB_KEYBOARD))
+ usb_init();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+/**
+ * dtb_dt_qemu - Return the address of the QEMU provided FDT.
+ *
+ * @return: Pointer to FDT or NULL on failure
+ */
+static void *dtb_dt_qemu(void)
+{
+ /* FDT might be at start of DRAM */
+ if (fdt_magic(SBSA_MEM_BASE_ADDR) == FDT_MAGIC)
+ return (void *)(u64)SBSA_MEM_BASE_ADDR;
+
+ /* When ARM_LINUX_KERNEL_AS_BL33 is enabled in ATF, it's passed in x0 */
+ if (fw_dtb_pointer >= SBSA_MEM_BASE_ADDR &&
+ fdt_magic(fw_dtb_pointer) == FDT_MAGIC) {
+ return (void *)fw_dtb_pointer;
+ }
+
+ return NULL;
+}
+
+/*
+ * QEMU doesn't set compatible on cpus.
+ * Add them to make sure the U-Boot driver properly bind.
+ */
+static int fdtdec_fix_cpus(void *fdt_blob)
+{
+ int cpus_offset, off, ret;
+ u64 mpidr, i = 0;
+
+ cpus_offset = fdt_path_offset(fdt_blob, "/cpus");
+ if (cpus_offset < 0) {
+ puts("couldn't find /cpus node\n");
+ return cpus_offset;
+ }
+
+ fdt_for_each_subnode(off, fdt_blob, cpus_offset) {
+ if (strncmp(fdt_get_name(fdt_blob, off, NULL), "cpu@", 4))
+ continue;
+
+ mpidr = 0;
+ ret = smc_get_mpidr(i, &mpidr);
+ if (ret) {
+ log_warning("Failed to get MPIDR for processor %lld from SMC: %d\n",
+ i, ret);
+ mpidr = i;
+ }
+
+ ret = fdt_setprop_string(fdt_blob, off, "compatible", "arm,armv8");
+ if (ret < 0)
+ return ret;
+
+ ret = fdt_setprop_string(fdt_blob, off, "device_type", "cpu");
+ if (ret < 0)
+ return ret;
+
+ ret = fdt_setprop_u64(fdt_blob, off, "reg", mpidr);
+ if (ret < 0)
+ return ret;
+ i++;
+ }
+ return 0;
+}
+
+/*
+ * Update the GIC node when necessary and add optional ITS when it has a
+ * non zero base-address.
+ */
+static int fdtdec_fix_gic(void *fdt)
+{
+ u64 gic_dist_base = SBSA_GIC_DIST_BASE_ADDR;
+ u64 gic_redist_base = SBSA_GIC_REDIST_BASE_ADDR;
+ u64 gic_its_base = 0;
+ int offs, ret;
+ u64 reg[10];
+
+ /* Invoke SMC to get real base-address */
+ smc_get_gic_dist_base(&gic_dist_base);
+ smc_get_gic_redist_base(&gic_redist_base);
+
+ if ((gic_dist_base != SBSA_GIC_DIST_BASE_ADDR) ||
+ (gic_redist_base != SBSA_GIC_REDIST_BASE_ADDR)) {
+ offs = fdt_path_offset(fdt, "/interrupt-controller");
+ if (offs < 0) {
+ puts("couldn't find /interrupt-controller node\n");
+ return offs;
+ }
+
+ reg[0] = cpu_to_fdt64(gic_dist_base);
+ reg[1] = cpu_to_fdt64((u64)SBSA_GIC_DIST_LENGTH);
+ reg[2] = cpu_to_fdt64(gic_redist_base);
+ reg[3] = cpu_to_fdt64((u64)SBSA_GIC_REDIST_LENGTH);
+ reg[4] = cpu_to_fdt64(0);
+ reg[5] = cpu_to_fdt64(0);
+ reg[6] = cpu_to_fdt64(SBSA_GIC_HBASE_ADDR);
+ reg[7] = cpu_to_fdt64((u64)SBSA_GIC_HBASE_LENGTH);
+ reg[8] = cpu_to_fdt64(SBSA_GIC_VBASE_ADDR);
+ reg[9] = cpu_to_fdt64((u64)SBSA_GIC_VBASE_LENGTH);
+
+ ret = fdt_setprop_inplace(fdt, offs, "reg", reg, sizeof(reg));
+ }
+
+ smc_get_gic_its_base(&gic_its_base);
+
+ if (gic_its_base != 0) {
+ offs = fdt_path_offset(fdt, "/its");
+ if (offs < 0)
+ return offs;
+
+ ret = fdt_setprop_string(fdt, offs, "status", "okay");
+ if (ret < 0)
+ return ret;
+
+ reg[0] = cpu_to_fdt64(gic_its_base);
+ reg[1] = 0;
+
+ ret = fdt_setprop(fdt, offs, "reg", reg, sizeof(u64) * 2);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+int fdtdec_board_setup(const void *fdt_blob)
+{
+ void *qemu_fdt;
+ int ret;
+
+ /*
+ * Locate the QEMU provided DTB that contains the CPUs and amount of DRAM.
+ */
+ qemu_fdt = dtb_dt_qemu();
+ if (!qemu_fdt) {
+ log_err("QEMU FDT not found\n");
+ return -ENODEV;
+ }
+
+ ret = fdt_increase_size((void *)fdt_blob, 1024 + fdt_totalsize(qemu_fdt));
+ if (ret)
+ return -ENOMEM;
+
+ /*
+ * Merge the QEMU DTB as overlay into the U-Boot provided DTB.
+ */
+ ret = fdt_overlay_apply_node((void *)fdt_blob, 0, qemu_fdt, 0);
+ if (ret < 0)
+ log_err("Failed to apply overlay: %d\n", ret);
+
+ /* Fix QEMU nodes to make sure U-Boot drivers are properly working */
+ ret = fdtdec_fix_cpus((void *)fdt_blob);
+ if (ret < 0)
+ log_err("Failed to fix CPUs in FDT: %d\n", ret);
+
+ ret = fdtdec_fix_gic((void *)fdt_blob);
+ if (ret < 0)
+ log_err("Failed to fix INTC in FDT: %d\n", ret);
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ return env_set_hex("fdt_addr", (uintptr_t)gd->fdt_blob);
+}
+
+void reset_cpu(void)
+{
+}
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
\ No newline at end of file
diff --git a/board/emulation/qemu-sbsa/qemu-sbsa.env b/board/emulation/qemu-sbsa/qemu-sbsa.env
new file mode 100644
index 0000000..88fdb0e
--- /dev/null
+++ b/board/emulation/qemu-sbsa/qemu-sbsa.env
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+/* environment for qemu-arm and qemu-arm64 */
+
+stdin=serial,usbkbd
+stdout=serial,vidconsole
+stderr=serial,vidconsole
+fdt_high=0xffffffffffffffff
+initrd_high=0xffffffffffffffff
+scriptaddr=0x100000300000
+pxefile_addr_r=0x10000400000
+kernel_addr_r=0x10000200000
+ramdisk_addr_r=0x10001000000
+boot_targets=qfw usb scsi virtio nvme dhcp
diff --git a/board/emulation/qemu-sbsa/qemu-sbsa.h b/board/emulation/qemu-sbsa/qemu-sbsa.h
new file mode 100644
index 0000000..391a70b
--- /dev/null
+++ b/board/emulation/qemu-sbsa/qemu-sbsa.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2024 9elements GmbH
+ */
+
+/**
+ * smc_get_mpidr() - Call into SMC and get the MPIDR for given CPU
+ *
+ * @id: CPU index
+ * @mpidr: Pointer where to place the MPIDR
+ * @return 0 if OK, other -ve on error
+ */
+int smc_get_mpidr(unsigned long id, u64 *mpidr);
+
+/**
+ * smc_get_gic_dist_base() - Call into SMC and get GIC dist base address
+ *
+ * @mpidr: Pointer where to place the base address
+ * @return 0 if OK, other -ve on error
+ */
+int smc_get_gic_dist_base(u64 *base);
+
+/**
+ * smc_get_gic_redist_base() - Call into SMC and get the GIC redistributor
+ * base address
+ *
+ * @mpidr: Pointer where to place the base address
+ * @return 0 if OK, other -ve on error
+ */
+int smc_get_gic_redist_base(u64 *base);
+
+/**
+ * smc_get_gic_its_base() - Call into SMC and get the ITS base address
+ *
+ * @mpidr: Pointer where to place the base address
+ * @return 0 if OK, other -ve on error
+ */
+int smc_get_gic_its_base(u64 *base);
diff --git a/board/emulation/qemu-sbsa/smc.c b/board/emulation/qemu-sbsa/smc.c
new file mode 100644
index 0000000..9a2d091
--- /dev/null
+++ b/board/emulation/qemu-sbsa/smc.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024 9elements GmbH
+ */
+
+#include <cpu.h>
+#include <init.h>
+#include <log.h>
+#include <linux/arm-smccc.h>
+
+#define SMC_SIP_FUNCTION_ID(n) (0xC2000000 | (n))
+
+#define SIP_SVC_VERSION SMC_SIP_FUNCTION_ID(1)
+#define SIP_SVC_GET_GIC SMC_SIP_FUNCTION_ID(100)
+#define SIP_SVC_GET_GIC_ITS SMC_SIP_FUNCTION_ID(101)
+#define SIP_SVC_GET_CPU_COUNT SMC_SIP_FUNCTION_ID(200)
+#define SIP_SVC_GET_CPU_NODE SMC_SIP_FUNCTION_ID(201)
+#define SIP_SVC_GET_MEMORY_NODE_COUNT SMC_SIP_FUNCTION_ID(300)
+#define SIP_SVC_GET_MEMORY_NODE SMC_SIP_FUNCTION_ID(301)
+
+int smc_get_mpidr(unsigned long id, u64 *mpidr)
+{
+ struct arm_smccc_res res;
+
+ res.a0 = ~0;
+ arm_smccc_smc(SIP_SVC_GET_CPU_NODE, id, 0, 0, 0, 0, 0, 0, &res);
+
+ if (!res.a0)
+ *mpidr = res.a2;
+
+ return res.a0;
+}
+
+int smc_get_gic_dist_base(u64 *base)
+{
+ struct arm_smccc_res res;
+
+ res.a0 = ~0;
+ arm_smccc_smc(SIP_SVC_GET_GIC, 0, 0, 0, 0, 0, 0, 0, &res);
+
+ if (!res.a0)
+ *base = res.a1;
+
+ return res.a0;
+}
+
+int smc_get_gic_redist_base(u64 *base)
+{
+ struct arm_smccc_res res;
+
+ res.a0 = ~0;
+ arm_smccc_smc(SIP_SVC_GET_GIC, 0, 0, 0, 0, 0, 0, 0, &res);
+
+ if (!res.a0)
+ *base = res.a2;
+
+ return res.a0;
+}
+
+int smc_get_gic_its_base(u64 *base)
+{
+ struct arm_smccc_res res;
+
+ res.a0 = ~0;
+ arm_smccc_smc(SIP_SVC_GET_GIC_ITS, 0, 0, 0, 0, 0, 0, 0, &res);
+
+ if (!res.a0)
+ *base = res.a1;
+
+ return res.a0;
+}
diff --git a/board/microchip/mpfs_icicle/Kconfig b/board/microchip/mpfs_icicle/Kconfig
index 4309f75..6e8c479 100644
--- a/board/microchip/mpfs_icicle/Kconfig
+++ b/board/microchip/mpfs_icicle/Kconfig
@@ -24,6 +24,8 @@
imply SMP
imply CLK_CCF
imply CLK_MPFS
+ imply REGMAP
+ imply SYSCON
imply SYS_NS16550
imply CMD_DHCP
imply CMD_EXT2
diff --git a/board/raspberrypi/rpi/.gitignore b/board/raspberrypi/rpi/.gitignore
new file mode 100644
index 0000000..39e46ba
--- /dev/null
+++ b/board/raspberrypi/rpi/.gitignore
@@ -0,0 +1,3 @@
+dsdt_generated.aml
+dsdt_generated.asl.tmp
+dsdt_generated.c
diff --git a/board/raspberrypi/rpi/Makefile b/board/raspberrypi/rpi/Makefile
index b1186cd..bb1b7cc 100644
--- a/board/raspberrypi/rpi/Makefile
+++ b/board/raspberrypi/rpi/Makefile
@@ -4,3 +4,5 @@
obj-y := rpi.o
obj-y += lowlevel_init.o
+
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt_generated.o
diff --git a/board/raspberrypi/rpi/acpitables.h b/board/raspberrypi/rpi/acpitables.h
new file mode 100644
index 0000000..3ba8f19
--- /dev/null
+++ b/board/raspberrypi/rpi/acpitables.h
@@ -0,0 +1,90 @@
+/** @file
+ *
+ * RPi defines for constructing ACPI tables
+ *
+ * Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ * Copyright (c) 2019, ARM Ltd. All rights reserved.
+ * Copyright (c) 2018, Andrei Warkentin <andrey.warkentin@gmail.com>
+ * Copyright (c) Microsoft Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#ifndef __RPI_ACPITABLES_H__
+#define __RPI_ACPITABLES_H__
+
+#include <acpi/acpi_table.h>
+
+// The ASL compiler can't perform arithmetic on MEMORY32FIXED ()
+// parameters so you can't pass a constant like BASE + OFFSET.
+// We therefore define a macro that can perform arithmetic base
+// address update with an offset.
+#define MEMORY32SETBASE(BufName, MemName, VarName, Offset) \
+ CreateDwordField (^BufName, ^MemName._BAS, VarName) \
+ Add (BCM2836_SOC_REGISTERS, Offset, VarName)
+
+//------------------------------------------------------------------------
+// Interrupts. These are specific to each platform
+//------------------------------------------------------------------------
+#if defined(CONFIG_TARGET_RPI_3)
+#define BCM2836_V3D_BUS_INTERRUPT 0x2A
+#define BCM2836_DMA_INTERRUPT 0x3B
+#define BCM2836_SPI1_INTERRUPT 0x3D
+#define BCM2836_SPI2_INTERRUPT 0x3D
+#define BCM2836_HVS_INTERRUPT 0x41
+#define BCM2836_HDMI0_INTERRUPT 0x48
+#define BCM2836_HDMI1_INTERRUPT 0x49
+#define BCM2836_PV2_INTERRUPT 0x4A
+#define BCM2836_PV0_INTERRUPT 0x4D
+#define BCM2836_PV1_INTERRUPT 0x4E
+#define BCM2836_MBOX_INTERRUPT 0x61
+#define BCM2836_VCHIQ_INTERRUPT 0x62
+#define BCM2386_GPIO_INTERRUPT0 0x51
+#define BCM2386_GPIO_INTERRUPT1 0x52
+#define BCM2386_GPIO_INTERRUPT2 0x53
+#define BCM2386_GPIO_INTERRUPT3 0x54
+#define BCM2836_I2C1_INTERRUPT 0x55
+#define BCM2836_I2C2_INTERRUPT 0x55
+#define BCM2836_SPI0_INTERRUPT 0x56
+#define BCM2836_USB_INTERRUPT 0x29
+#define BCM2836_SDHOST_INTERRUPT 0x58
+#define BCM2836_MMCHS1_INTERRUPT 0x5E
+#define BCM2836_MINI_UART_INTERRUPT 0x3D
+#define BCM2836_PL011_UART_INTERRUPT 0x59
+#elif defined(CONFIG_TARGET_RPI_4)
+#define BCM2836_V3D_BUS_INTERRUPT 0x2A
+#define BCM2836_DMA_INTERRUPT 0x3B
+#define BCM2836_SPI1_INTERRUPT 0x7D
+#define BCM2836_SPI2_INTERRUPT 0x7D
+#define BCM2836_HVS_INTERRUPT 0x41
+#define BCM2836_HDMI0_INTERRUPT 0x48
+#define BCM2836_HDMI1_INTERRUPT 0x49
+#define BCM2836_PV2_INTERRUPT 0x4A
+#define BCM2836_PV0_INTERRUPT 0x4D
+#define BCM2836_PV1_INTERRUPT 0x4E
+#define BCM2836_MBOX_INTERRUPT 0x41
+#define BCM2836_VCHIQ_INTERRUPT 0x42
+#define BCM2386_GPIO_INTERRUPT0 0x91
+#define BCM2386_GPIO_INTERRUPT1 0x92
+#define BCM2386_GPIO_INTERRUPT2 0x93
+#define BCM2386_GPIO_INTERRUPT3 0x94
+#define BCM2836_I2C1_INTERRUPT 0x95
+#define BCM2836_I2C2_INTERRUPT 0x95
+#define BCM2836_SPI0_INTERRUPT 0x96
+#define BCM2836_USB_INTERRUPT 0x69
+#define BCM2836_SDHOST_INTERRUPT 0x98
+#define BCM2836_MMCHS1_INTERRUPT 0x9E
+#define BCM2836_MINI_UART_INTERRUPT 0x7D
+#define BCM2836_PL011_UART_INTERRUPT 0x99
+#define GENET_INTERRUPT0 0xBD
+#define GENET_INTERRUPT1 0xBE
+#define GENET_BASE_ADDRESS 0xFD580000
+#define GENET_LENGTH 0x10000
+#define THERM_SENSOR_BASE_ADDRESS 0xFD5d2200
+#define THERM_SENSOR_LENGTH 0x8
+#else
+#error "Unsupported rpi module for ACPI tables"
+#endif
+
+#endif // __ACPITABLES_H__
diff --git a/board/raspberrypi/rpi/dsdt.asl b/board/raspberrypi/rpi/dsdt.asl
new file mode 100644
index 0000000..c89b08d
--- /dev/null
+++ b/board/raspberrypi/rpi/dsdt.asl
@@ -0,0 +1,254 @@
+/** @file
+ *
+ * Differentiated System Definition Table (DSDT)
+ *
+ * Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ * Copyright (c) 2018-2020, Andrey Warkentin <andrey.warkentin@gmail.com>
+ * Copyright (c) Microsoft Corporation. All rights reserved.
+ * Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <asm/arch/acpi/bcm2711.h>
+#include <asm/arch/acpi/bcm2836.h>
+#include <asm/arch/acpi/bcm2836_gpio.h>
+#include <asm/arch/acpi/bcm2836_gpu.h>
+#include <asm/arch/acpi/bcm2836_pwm.h>
+#include <asm/arch/acpi/bcm2836_sdio.h>
+#include <asm/arch/acpi/bcm2836_sdhost.h>
+
+#include "acpitables.h"
+
+#define BCM_ALT0 0x4
+#define BCM_ALT1 0x5
+#define BCM_ALT2 0x6
+#define BCM_ALT3 0x7
+#define BCM_ALT4 0x3
+#define BCM_ALT5 0x2
+
+//
+// The ASL compiler does not support argument arithmetic in functions
+// like QWordMemory (). So we need to instantiate dummy qword regions
+// that we can then update the Min, Max and Length attributes of.
+// The three macros below help accomplish this.
+//
+// QWORDMEMORYSET specifies a CPU memory range (whose base address is
+// BCM2836_SOC_REGISTERS + Offset), and QWORDBUSMEMORYSET specifies
+// a VPU memory range (whose base address is provided directly).
+//
+#define QWORDMEMORYBUF(Index) \
+ QWordMemory (ResourceProducer,, \
+ MinFixed, MaxFixed, NonCacheable, ReadWrite, \
+ 0x0, 0x0, 0x0, 0x0, 0x1,,, RB ## Index)
+
+#define QWORDMEMORYSET(Index, Offset, Length) \
+ CreateQwordField (RBUF, RB ## Index._MIN, MI ## Index) \
+ CreateQwordField (RBUF, RB ## Index._MAX, MA ## Index) \
+ CreateQwordField (RBUF, RB ## Index._LEN, LE ## Index) \
+ Store (Length, LE ## Index) \
+ Add (BCM2836_SOC_REGISTERS, Offset, MI ## Index) \
+ Add (MI ## Index, LE ## Index - 1, MA ## Index)
+
+#define QWORDBUSMEMORYSET(Index, Base, Length) \
+ CreateQwordField (RBUF, RB ## Index._MIN, MI ## Index) \
+ CreateQwordField (RBUF, RB ## Index._MAX, MA ## Index) \
+ CreateQwordField (RBUF, RB ## Index._LEN, LE ## Index) \
+ Store (Base, MI ## Index) \
+ Store (Length, LE ## Index) \
+ Add (MI ## Index, LE ## Index - 1, MA ## Index)
+
+DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
+{
+ External (\_PR.CP00, DeviceObj)
+ External (\_PR.CP01, DeviceObj)
+ External (\_PR.CP02, DeviceObj)
+ External (\_PR.CP03, DeviceObj)
+ Scope (\_SB_)
+ {
+ include ("pep.asl")
+
+ //
+ // GPU device container describes the DMA translation required
+ // when a device behind the GPU wants to access Arm memory.
+ // Only the first GB can be addressed.
+ //
+ Device (GDV0)
+ {
+ Name (_HID, "ACPI0004")
+ Name (_UID, 0x1)
+ Name (_CCA, 0x0)
+
+ Method (_CRS, 0, Serialized) {
+ //
+ // Container devices with _DMA must have _CRS, meaning GDV0
+ // to provide all resources that GpuDevs.asl consume (except
+ // interrupts).
+ //
+ Name (RBUF, ResourceTemplate () {
+ QWORDMEMORYBUF(01)
+ QWORDMEMORYBUF(02)
+ QWORDMEMORYBUF(03)
+ // QWORDMEMORYBUF(04)
+ // QWORDMEMORYBUF(05)
+ QWORDMEMORYBUF(06)
+ QWORDMEMORYBUF(07)
+ QWORDMEMORYBUF(08)
+ QWORDMEMORYBUF(09)
+ QWORDMEMORYBUF(10)
+ QWORDMEMORYBUF(11)
+ QWORDMEMORYBUF(12)
+ QWORDMEMORYBUF(13)
+ QWORDMEMORYBUF(14)
+ QWORDMEMORYBUF(15)
+ // QWORDMEMORYBUF(16)
+ QWORDMEMORYBUF(17)
+ QWORDMEMORYBUF(18)
+ QWORDMEMORYBUF(19)
+ QWORDMEMORYBUF(20)
+ QWORDMEMORYBUF(21)
+ QWORDMEMORYBUF(22)
+ QWORDMEMORYBUF(23)
+ QWORDMEMORYBUF(24)
+ QWORDMEMORYBUF(25)
+ })
+
+ // USB
+ QWORDMEMORYSET(01, BCM2836_USB_OFFSET, BCM2836_USB_LENGTH)
+
+ // GPU
+ QWORDMEMORYSET(02, BCM2836_V3D_BUS_OFFSET, BCM2836_V3D_BUS_LENGTH)
+ QWORDMEMORYSET(03, BCM2836_HVS_OFFSET, BCM2836_HVS_LENGTH)
+ // QWORDMEMORYSET(04, BCM2836_PV0_OFFSET, BCM2836_PV0_LENGTH)
+ // QWORDMEMORYSET(05, BCM2836_PV1_OFFSET, BCM2836_PV1_LENGTH)
+ QWORDMEMORYSET(06, BCM2836_PV2_OFFSET, BCM2836_PV2_LENGTH)
+ QWORDMEMORYSET(07, BCM2836_HDMI0_OFFSET, BCM2836_HDMI0_LENGTH)
+ QWORDMEMORYSET(08, BCM2836_HDMI1_OFFSET, BCM2836_HDMI1_LENGTH)
+
+ // Mailbox
+ QWORDMEMORYSET(09, BCM2836_MBOX_OFFSET, BCM2836_MBOX_LENGTH)
+
+ // VCHIQ
+ QWORDMEMORYSET(10, BCM2836_VCHIQ_OFFSET, BCM2836_VCHIQ_LENGTH)
+
+ // GPIO
+ QWORDMEMORYSET(11, GPIO_OFFSET, GPIO_LENGTH)
+
+ // I2C
+ QWORDMEMORYSET(12, BCM2836_I2C1_OFFSET, BCM2836_I2C1_LENGTH)
+ QWORDMEMORYSET(13, BCM2836_I2C2_OFFSET, BCM2836_I2C2_LENGTH)
+
+ // SPI
+ QWORDMEMORYSET(14, BCM2836_SPI0_OFFSET, BCM2836_SPI0_LENGTH)
+ QWORDMEMORYSET(15, BCM2836_SPI1_OFFSET, BCM2836_SPI1_LENGTH)
+ // QWORDMEMORYSET(16, BCM2836_SPI2_OFFSET, BCM2836_SPI2_LENGTH)
+
+ // PWM
+ QWORDMEMORYSET(17, BCM2836_PWM_DMA_OFFSET, BCM2836_PWM_DMA_LENGTH)
+ QWORDMEMORYSET(18, BCM2836_PWM_CTRL_OFFSET, BCM2836_PWM_CTRL_LENGTH)
+ QWORDBUSMEMORYSET(19, BCM2836_PWM_BUS_BASE_ADDRESS, BCM2836_PWM_BUS_LENGTH)
+ QWORDBUSMEMORYSET(20, BCM2836_PWM_CTRL_UNCACHED_BASE_ADDRESS, BCM2836_PWM_CTRL_UNCACHED_LENGTH)
+ QWORDMEMORYSET(21, BCM2836_PWM_CLK_OFFSET, BCM2836_PWM_CLK_LENGTH)
+
+ // UART
+ QWORDMEMORYSET(22, BCM2836_PL011_UART_OFFSET, BCM2836_PL011_UART_LENGTH)
+ QWORDMEMORYSET(23, BCM2836_MINI_UART_OFFSET, BCM2836_MINI_UART_LENGTH)
+
+ // SDC
+ QWORDMEMORYSET(24, MMCHS1_OFFSET, MMCHS1_LENGTH)
+ QWORDMEMORYSET(25, SDHOST_OFFSET, SDHOST_LENGTH)
+
+ Return (RBUF)
+ }
+
+ Name (_DMA, ResourceTemplate() {
+ //
+ // Only the first GB is available.
+ // Bus 0xC0000000 -> CPU 0x00000000.
+ //
+ QWordMemory (ResourceProducer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x00000000C0000000, // MIN
+ 0x00000000FFFFFFFF, // MAX
+ 0xFFFFFFFF40000000, // TRA
+ 0x0000000040000000, // LEN
+ ,
+ ,
+ )
+ })
+#include "gpudevs.asl"
+ }
+
+#if defined(CONFIG_TARGET_RPI_4)
+ Device (ETH0)
+ {
+ Name (_HID, "BCM6E4E")
+ Name (_CID, "BCM6E4E")
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
+
+ Method (_CRS, 0x0, Serialized)
+ {
+ Return (ResourceTemplate ()
+ {
+ // No need for MEMORY32SETBASE on Genet as we have a straight base address constant
+ MEMORY32FIXED (ReadWrite, GENET_BASE_ADDRESS, GENET_LENGTH, )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { GENET_INTERRUPT0, GENET_INTERRUPT1 }
+ })
+ }
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "brcm,max-dma-burst-size", 0x08 },
+ Package () { "phy-mode", "rgmii-rxid" },
+ }
+ })
+ }
+
+ // Define a simple thermal zone. The idea here is we compute the SOC temp
+ // via a register we can read, and give it to the OS. This enables basic
+ // reports from the "sensors" utility, and the OS can then poll and take
+ // actions if that temp exceeds any of the given thresholds.
+ Device (EC00)
+ {
+ Name (_HID, EISAID ("PNP0C06"))
+ Name (_CCA, 0x0)
+
+ // all temps in are tenths of K (aka 2732 is the min temps in Linux (aka 0C))
+ ThermalZone (TZ00) {
+ OperationRegion (TEMS, SystemMemory, THERM_SENSOR_BASE_ADDRESS, THERM_SENSOR_LENGTH)
+ Field (TEMS, DWordAcc, NoLock, Preserve) {
+ TMPS, 32
+ }
+ Method (_TMP, 0, Serialized) {
+ return (((410040 - ((TMPS & 0x3ff) * 487)) / 100) + 2732);
+ }
+
+ Method (_SCP, 3) { } // receive cooling policy from OS
+
+ Method (_CRT) { Return (3632) } // (90C) Critical temp point (immediate power-off)
+ Method (_HOT) { Return (3582) } // (85C) HOT state where OS should hibernate
+ Method (_PSV) { Return (3532) } // (80C) Passive cooling (CPU throttling) trip point
+
+ // SSDT inserts _AC0/_AL0 @60C here, if a FAN is configured
+
+ Name (_TZP, 10) //The OSPM must poll this device every 1 seconds
+ Name (_PSL, Package () { \_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03 })
+ }
+ }
+#endif
+
+
+#include "uart.asl"
+#include "rhpx.asl"
+#include "sdhc.asl"
+#include "emmc.asl"
+#include "pci.asl"
+ }
+}
diff --git a/board/raspberrypi/rpi/emmc.asl b/board/raspberrypi/rpi/emmc.asl
new file mode 100644
index 0000000..63f0136
--- /dev/null
+++ b/board/raspberrypi/rpi/emmc.asl
@@ -0,0 +1,136 @@
+/** @file
+ *
+ * Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <asm/arch/acpi/bcm2836_sdhost.h>
+#include <asm/arch/acpi/bcm2836_sdio.h>
+#include <asm/arch/acpi/bcm2711.h>
+
+Device (GDV1) {
+ Name (_HID, "ACPI0004")
+ Name (_UID, 0x2)
+ Name (_CCA, 0x0)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, MMCHS2_LENGTH, RMEM)
+ })
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, MMCHS2_OFFSET)
+ Return (^RBUF)
+ }
+
+ // Translated DMA region for BCM2711 silicon revisions older than C0
+ Name (DMTR, ResourceTemplate() {
+ QWordMemory (ResourceProducer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x00000000C0000000, // MIN
+ 0x00000000FFFFFFFF, // MAX
+ 0xFFFFFFFF40000000, // TRA
+ 0x0000000040000000, // LEN
+ ,
+ ,
+ )
+ })
+
+ // Non translated DMA region for BCM2711 revisions C0 and newer
+ Name (DMNT, ResourceTemplate() {
+ QWordMemory (ResourceProducer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x0000000000000000, // MIN
+ 0x000000FFFFFFFFFF, // MAX
+ 0x0000000000000000, // TRA
+ 0x0000010000000000, // LEN
+ ,
+ ,
+ )
+ })
+
+ // emmc2 Host Controller. (brcm,bcm2711-emmc2)
+ Device (SDC3)
+ {
+ Name (_HID, "BRCME88C")
+ Name (_UID, 0x1)
+ Name (_CCA, 0x0)
+ Name (_S1D, 0x1)
+ Name (_S2D, 0x1)
+ Name (_S3D, 0x1)
+ Name (_S4D, 0x1)
+ Name (SDMA, 0x2)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, MMCHS2_LENGTH, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) { BCM2836_MMCHS1_INTERRUPT }
+ })
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, MMCHS2_OFFSET)
+ Return (^RBUF)
+ }
+
+ // Unfortunately this controller doesn't honor the
+ // standard SDHCI voltage control registers
+ // (or at least Linux's standard code can't
+ // lower the voltage) So, UHS mode is disabled with caps
+ Name (DSD1, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "sdhci-caps-mask", 0x0000000500080000 },
+ }
+ })
+ // Along with disabling UHS, here both SDMA and ADMA2
+ // are also disabled until the linux _DMA() mask/translate
+ // works properly.
+ Name (DSD2, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "sdhci-caps-mask", 0x0000000504480000 },
+ }
+ })
+ Method (_DSD, 0x0, Serialized)
+ {
+ // Select one of the sdhci-caps-mask definitions
+ // depending on whether we also want to disable DMA
+ if (SDMA == 0)
+ {
+ return (^DSD2)
+ }
+ else
+ {
+ return (^DSD1)
+ }
+ }
+
+ //
+ // A child device that represents the
+ // sd card, which is marked as non-removable.
+ //
+ Device (SDMM)
+ {
+ Method (_ADR)
+ {
+ Return (0)
+ }
+ Method (_RMV) // Is removable
+ {
+ Return (0) // 0 - fixed
+ }
+ }
+ } //SDC3
+} //GDV1
diff --git a/board/raspberrypi/rpi/gpudevs.asl b/board/raspberrypi/rpi/gpudevs.asl
new file mode 100644
index 0000000..a3077a9
--- /dev/null
+++ b/board/raspberrypi/rpi/gpudevs.asl
@@ -0,0 +1,372 @@
+/** @file
+ *
+ * [DSDT] Devices behind the GPU.
+ *
+ * Copyright (c) 2018-2020, Andrey Warkentin <andrey.warkentin@gmail.com>
+ * Copyright (c) Microsoft Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+// DWC OTG Controller
+Device (USB0)
+{
+ Name (_HID, "BCM2848")
+#if defined(CONFIG_TARGET_RPI_3)
+ Name (_CID, "DWC_OTG")
+#elif defined(CONFIG_TARGET_RPI_4)
+ Name (_CID, "BCM2848")
+#endif
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
+ Method (_STA)
+ {
+ Return (0xf)
+ }
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_USB_LENGTH, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_USB_INTERRUPT }
+ })
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_USB_OFFSET)
+ Return (^RBUF)
+ }
+}
+
+// Video Core 4 GPU
+Device (GPU0)
+{
+ Name (_HID, "BCM2850")
+ Name (_CID, "BCM2850")
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
+ Method (_STA)
+ {
+ Return (0xf)
+ }
+ Name (RBUF, ResourceTemplate ()
+ {
+ // Memory and interrupt for the GPU
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_V3D_BUS_LENGTH, RM01)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_V3D_BUS_INTERRUPT }
+
+ // HVS - Hardware Video Scalar
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_HVS_LENGTH, RM02)
+ // The HVS interrupt is reserved by the VPU
+ // Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_HVS_INTERRUPT }
+
+ // PixelValve0 - DSI0 or DPI
+ // MEMORY32FIXED (ReadWrite, BCM2836_PV0_BASE_ADDRESS, BCM2836_PV0_LENGTH, RM03)
+ // Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_PV0_INTERRUPT }
+
+ // PixelValve1 - DS1 or SMI
+ // MEMORY32FIXED (ReadWrite, BCM2836_PV1_BASE_ADDRESS, BCM2836_PV1_LENGTH, RM04)
+ // Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_PV1_INTERRUPT }
+
+ // PixelValve2 - HDMI output - connected to HVS display FIFO 1
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_PV2_LENGTH, RM05)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_PV2_INTERRUPT }
+
+ // HDMI registers
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_HDMI0_LENGTH, RM06)
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_HDMI1_LENGTH, RM07)
+ // hdmi_int[0]
+ // Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_HDMI0_INTERRUPT }
+ // hdmi_int[1]
+ // Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_HDMI1_INTERRUPT }
+
+ // HDMI DDC connection
+ I2CSerialBus (0x50,, 100000,, "\\_SB.GDV0.I2C2",,,,) // EDID
+ I2CSerialBus (0x30,, 100000,, "\\_SB.GDV0.I2C2",,,,) // E-DDC Segment Pointer
+ })
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RM01, RB01, BCM2836_V3D_BUS_OFFSET)
+ MEMORY32SETBASE (RBUF, RM02, RB02, BCM2836_HVS_OFFSET)
+ MEMORY32SETBASE (RBUF, RM05, RB05, BCM2836_PV2_OFFSET)
+ MEMORY32SETBASE (RBUF, RM06, RB06, BCM2836_HDMI0_OFFSET)
+ MEMORY32SETBASE (RBUF, RM07, RB07, BCM2836_HDMI1_OFFSET)
+ Return (^RBUF)
+ }
+
+ // GPU Power Management Component Data
+ // Reference : https://github.com/Microsoft/graphics-driver-samples/wiki/Install-Driver-in-a-Windows-VM
+ Method (PMCD, 0, Serialized)
+ {
+ Name (RBUF, Package ()
+ {
+ 1, // Version
+ 1, // Number of graphics power components
+ Package () // Power components package
+ {
+ Package () // GPU component package
+ {
+ 0, // Component Index
+ 0, // DXGK_POWER_COMPONENT_MAPPING.ComponentType (0 = DXGK_POWER_COMPONENT_ENGINE)
+ 0, // DXGK_POWER_COMPONENT_MAPPING.NodeIndex
+
+ Buffer () // DXGK_POWER_RUNTIME_COMPONENT.ComponentGuid
+ { // 9B2D1E26-1575-4747-8FC0-B9EB4BAA2D2B
+ 0x26, 0x1E, 0x2D, 0x9B, 0x75, 0x15, 0x47, 0x47,
+ 0x8f, 0xc0, 0xb9, 0xeb, 0x4b, 0xaa, 0x2d, 0x2b
+ },
+
+ "VC4_Engine_00",// DXGK_POWER_RUNTIME_COMPONENT.ComponentName
+ 2, // DXGK_POWER_RUNTIME_COMPONENT.StateCount
+
+ Package () // DXGK_POWER_RUNTIME_COMPONENT.States[] package
+ {
+ Package () // F0
+ {
+ 0, // DXGK_POWER_RUNTIME_STATE.TransitionLatency
+ 0, // DXGK_POWER_RUNTIME_STATE.ResidencyRequirement
+ 1210000, // DXGK_POWER_RUNTIME_STATE.NominalPower (microwatt)
+ },
+
+ Package () // F1 - Placeholder
+ {
+ 10000, // DXGK_POWER_RUNTIME_STATE.TransitionLatency
+ 10000, // DXGK_POWER_RUNTIME_STATE.ResidencyRequirement
+ 4, // DXGK_POWER_RUNTIME_STATE.NominalPower
+ },
+ }
+ }
+ }
+ })
+ Return (RBUF)
+ }
+}
+
+// PiQ Mailbox Driver
+Device (RPIQ)
+{
+ Name (_HID, "BCM2849")
+ Name (_CID, "BCM2849")
+ Name (_UID, 0)
+ Name (_CCA, 0x0)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_MBOX_LENGTH, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_MBOX_INTERRUPT }
+ })
+
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_MBOX_OFFSET)
+ Return (^RBUF)
+ }
+}
+
+// VCHIQ Driver
+Device (VCIQ)
+{
+ Name (_HID, "BCM2835")
+ Name (_CID, "BCM2835")
+ Name (_UID, 0)
+ Name (_CCA, 0x0)
+ Name (_DEP, Package() { \_SB.GDV0.RPIQ })
+ Method (_STA)
+ {
+ Return (0xf)
+ }
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_VCHIQ_LENGTH, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_VCHIQ_INTERRUPT }
+ })
+
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_VCHIQ_OFFSET)
+ Return (^RBUF)
+ }
+}
+
+// VC Shared Memory Driver
+Device (VCSM)
+{
+ Name (_HID, "BCM2856")
+ Name (_CID, "BCM2856")
+ Name (_UID, 0)
+ Name (_CCA, 0x0)
+ Name (_DEP, Package() { \_SB.GDV0.VCIQ })
+ Method (_STA)
+ {
+ Return (0xf)
+ }
+}
+
+// Description: GPIO
+Device (GPI0)
+{
+ Name (_HID, "BCM2845")
+ Name (_CID, "BCM2845")
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, GPIO_LENGTH, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared)
+ {
+ BCM2386_GPIO_INTERRUPT0, BCM2386_GPIO_INTERRUPT1,
+ BCM2386_GPIO_INTERRUPT2, BCM2386_GPIO_INTERRUPT3
+ }
+ })
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, GPIO_OFFSET)
+ Return (^RBUF)
+ }
+}
+
+// Description: I2C
+Device (I2C1)
+{
+ Name (_HID, "BCM2841")
+ Name (_CID, "BCM2841")
+ Name (_UID, 0x1)
+ Name (_CCA, 0x0)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_I2C1_LENGTH, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) { BCM2836_I2C1_INTERRUPT }
+ PinFunction (Exclusive, PullUp, BCM_ALT0, "\\_SB.GDV0.GPI0", 0, ResourceConsumer, , ) { 2, 3 }
+ })
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_I2C1_OFFSET)
+ Return (^RBUF)
+ }
+}
+
+// I2C2 is the HDMI DDC connection
+Device (I2C2)
+{
+ Name (_HID, "BCM2841")
+ Name (_CID, "BCM2841")
+ Name (_UID, 0x2)
+ Name (_CCA, 0x0)
+
+ Name (RBUF, ResourceTemplate()
+ {
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_I2C2_LENGTH, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) { BCM2836_I2C2_INTERRUPT }
+ })
+
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_I2C2_OFFSET)
+ Return (^RBUF)
+ }
+}
+
+// SPI
+Device (SPI0)
+{
+ Name (_HID, "BCM2838")
+ Name (_CID, "BCM2838")
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_SPI0_LENGTH, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) { BCM2836_SPI0_INTERRUPT }
+ PinFunction (Exclusive, PullDown, BCM_ALT0, "\\_SB.GDV0.GPI0", 0, ResourceConsumer, , ) { 9, 10, 11 } // MISO, MOSI, SCLK
+ PinFunction (Exclusive, PullUp, BCM_ALT0, "\\_SB.GDV0.GPI0", 0, ResourceConsumer, , ) { 8 } // CE0
+ PinFunction (Exclusive, PullUp, BCM_ALT0, "\\_SB.GDV0.GPI0", 0, ResourceConsumer, , ) { 7 } // CE1
+ })
+
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_SPI0_OFFSET)
+ Return (^RBUF)
+ }
+}
+
+Device (SPI1)
+{
+ Name (_HID, "BCM2839")
+ Name (_CID, "BCM2839")
+ Name (_UID, 0x1)
+ Name (_CCA, 0x0)
+ Name (_DEP, Package() { \_SB.GDV0.RPIQ })
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_SPI1_LENGTH, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared,) { BCM2836_SPI1_INTERRUPT }
+ PinFunction (Exclusive, PullDown, BCM_ALT4, "\\_SB.GDV0.GPI0", 0, ResourceConsumer, , ) { 19, 20, 21 } // MISO, MOSI, SCLK
+ PinFunction (Exclusive, PullDown, BCM_ALT4, "\\_SB.GDV0.GPI0", 0, ResourceConsumer, , ) { 16 } // CE2
+ })
+
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_SPI1_OFFSET)
+ Return (^RBUF)
+ }
+}
+
+// SPI2 has no pins on GPIO header
+// Device (SPI2)
+// {
+// Name (_HID, "BCM2839")
+// Name (_CID, "BCM2839")
+// Name (_UID, 0x2)
+// Name (_CCA, 0x0)
+// Name (_DEP, Package() { \_SB.GDV0.RPIQ })
+// Method (_STA)
+// {
+// Return (0xf) // Disabled
+// }
+// Method (_CRS, 0x0, Serialized)
+// {
+// Name (RBUF, ResourceTemplate ()
+// {
+// MEMORY32FIXED (ReadWrite, BCM2836_SPI2_BASE_ADDRESS, BCM2836_SPI2_LENGTH, RMEM)
+// Interrupt (ResourceConsumer, Level, ActiveHigh, Shared,) { BCM2836_SPI2_INTERRUPT }
+// })
+// Return (RBUF)
+// }
+// }
+
+// PWM Driver
+Device (PWM0)
+{
+ Name (_HID, "BCM2844")
+ Name (_CID, "BCM2844")
+ Name (_UID, 0)
+ Name (_CCA, 0x0)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ // DMA channel 11 control
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_PWM_DMA_LENGTH, RM01)
+ // PWM control
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_PWM_CTRL_LENGTH, RM02)
+ // PWM control bus
+ MEMORY32FIXED (ReadWrite, BCM2836_PWM_BUS_BASE_ADDRESS, BCM2836_PWM_BUS_LENGTH, )
+ // PWM control uncached
+ MEMORY32FIXED (ReadWrite, BCM2836_PWM_CTRL_UNCACHED_BASE_ADDRESS, BCM2836_PWM_CTRL_UNCACHED_LENGTH, )
+ // PWM clock control
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_PWM_CLK_LENGTH, RM03)
+ // Interrupt DMA channel 11
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_DMA_INTERRUPT }
+ // DMA channel 11, DREQ 5 for PWM
+ FixedDMA (5, 11, Width32Bit, )
+ })
+
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RM01, RB01, BCM2836_PWM_DMA_OFFSET)
+ MEMORY32SETBASE (RBUF, RM02, RB02, BCM2836_PWM_CTRL_OFFSET)
+ MEMORY32SETBASE (RBUF, RM03, RB03, BCM2836_PWM_CLK_OFFSET)
+ Return (^RBUF)
+ }
+}
\ No newline at end of file
diff --git a/board/raspberrypi/rpi/pci.asl b/board/raspberrypi/rpi/pci.asl
new file mode 100644
index 0000000..a7a09df
--- /dev/null
+++ b/board/raspberrypi/rpi/pci.asl
@@ -0,0 +1,177 @@
+/** @file
+ *
+ * Copyright (c) 2019 Linaro, Limited. All rights reserved.
+ * Copyright (c) 2021 Arm
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+Device(PCI0)
+{
+ Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
+ Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
+ Name(_SEG, Zero) // PCI Segment Group number
+ Name(_BBN, Zero) // PCI Base Bus Number
+ Name(_CCA, 0) // Mark the PCI noncoherent
+
+ // PCIe can only DMA to first 3GB with early SOC's
+ // But we keep the restriction on the later ones
+ // To avoid DMA translation problems.
+ Name (_DMA, ResourceTemplate() {
+ QWordMemory (ResourceProducer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x0, // MIN
+ 0xbfffffff, // MAX
+ 0x0, // TRA
+ 0xc0000000, // LEN
+ ,
+ ,
+ )
+ })
+
+ // PCI Routing Table
+ Name(_PRT, Package() {
+ Package (4) { 0x0000FFFF, 0, zero, 175 },
+ Package (4) { 0x0000FFFF, 1, zero, 176 },
+ Package (4) { 0x0000FFFF, 2, zero, 177 },
+ Package (4) { 0x0000FFFF, 3, zero, 178 }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "linux-ecam-quirk-id", "bcm2711" },
+ }
+ })
+
+ // Root complex resources
+ Method (_CRS, 0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+
+ // bus numbers assigned to this root
+ WordBusNumber (
+ ResourceProducer,
+ MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 0, // AddressMinimum - Minimum Bus Number
+ 255, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 256 // RangeLength - Number of Busses
+ )
+
+ // 32-bit mmio window in 64-bit addr
+ QWordMemory (
+ ResourceProducer, PosDecode,
+ MinFixed, MaxFixed,
+ NonCacheable, ReadWrite, // cacheable
+ 0x00000000, // Granularity
+ 0, // PCIE_PCI_MMIO_BEGIN
+ 1, // PCIE_MMIO_LEN + PCIE_PCI_MMIO_BEGIN
+ PCIE_CPU_MMIO_WINDOW, // PCIE_PCI_MMIO_BEGIN - PCIE_CPU_MMIO_WINDOW
+ 2 // PCIE_MMIO_LEN + 1
+ ,,,MMI1
+ )
+
+ // root port registers, not to be used if SMCCC is utilized
+ QWordMemory (
+ ResourceConsumer, ,
+ MinFixed, MaxFixed,
+ NonCacheable, ReadWrite, // cacheable
+ 0x00000000, // Granularity
+ 0xFD500000, // Root port begin
+ 0xFD509FFF, // Root port end
+ 0x00000000, // no translation
+ 0x0000A000, // size
+ ,,
+ )
+ }) // end Name(RBUF)
+
+ // Work around ASL's inability to add in a resource definition
+ // or for that matter compute the min,max,len properly
+ CreateQwordField (RBUF, MMI1._MIN, MMIB)
+ CreateQwordField (RBUF, MMI1._MAX, MMIE)
+ CreateQwordField (RBUF, MMI1._TRA, MMIT)
+ CreateQwordField (RBUF, MMI1._LEN, MMIL)
+ Add (MMIB, PCIE_TOP_OF_MEM_WIN, MMIB)
+ Add (PCIE_BRIDGE_MMIO_LEN, PCIE_TOP_OF_MEM_WIN, MMIE)
+ Subtract (MMIT, PCIE_TOP_OF_MEM_WIN, MMIT)
+ Add (PCIE_BRIDGE_MMIO_LEN, 1 , MMIL)
+
+ Return (RBUF)
+ } // end Method(_CRS)
+
+ // OS Control Handoff
+ Name(SUPP, Zero) // PCI _OSC Support Field value
+ Name(CTRL, Zero) // PCI _OSC Control Field value
+
+ // See [1] 6.2.10, [2] 4.5
+ Method(_OSC,4) {
+ // Note, This code is very similar to the code in the PCIe firmware
+ // specification which can be used as a reference
+ // Check for proper UUID
+ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ // Create DWord-adressable fields from the Capabilities Buffer
+ CreateDWordField(Arg3,0,CDW1)
+ CreateDWordField(Arg3,4,CDW2)
+ CreateDWordField(Arg3,8,CDW3)
+ // Save Capabilities DWord2 & 3
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+ // Mask out Native HotPlug
+ And(CTRL,0x1E,CTRL)
+ // Always allow native PME, AER (no dependencies)
+ // Never allow SHPC (no SHPC controller in this system)
+ And(CTRL,0x1D,CTRL)
+
+ If(LNotEqual(Arg1,One)) { // Unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ // Update DWORD3 in the buffer
+ Store(CTRL,CDW3)
+ Return(Arg3)
+ } Else {
+ Or(CDW1,4,CDW1) // Unrecognized UUID
+ Return(Arg3)
+ }
+ } // End _OSC
+
+ Device (XHC0)
+ {
+ Name (_ADR, 0x00010000)
+ Name (_CID, "PNP0D10")
+ Name (_UID, 0x0) // _UID: Unique ID
+ Name (_CCA, 0x0) // _CCA: Cache Coherency Attribute
+
+ /*
+ * Microsoft's USB Device-Specific Methods. See:
+ * https://docs.microsoft.com/en-us/windows-hardware/drivers/bringup/usb-device-specific-method---dsm-
+ */
+ Name (DSMU, ToUUID ("ce2ee385-00e6-48cb-9f05-2edb927c4899"))
+
+ Method (_DSM, 4, Serialized) {
+ If (LEqual (Arg0, DSMU)) { // USB capabilities UUID
+ Switch (ToInteger (Arg2)) {
+ Case (0) { // Function 0: List of supported functions
+ Return (Buffer () { 0x41 }) // 0x41 - Functions 0 and 6 supported
+ }
+ Case (6) { // Function 6: RegisterAccessType
+ Return (Buffer () { 0x01 }) // 0x01 - Must use 32bit register access
+ }
+ Default { } // Unsupported
+ }
+ }
+ return (Buffer () { 0x00 }) // Return 0x00 for anything unsupported
+ }
+ } // end XHC0
+
+} // PCI0
\ No newline at end of file
diff --git a/board/raspberrypi/rpi/pep.asl b/board/raspberrypi/rpi/pep.asl
new file mode 100644
index 0000000..87469e2
--- /dev/null
+++ b/board/raspberrypi/rpi/pep.asl
@@ -0,0 +1,90 @@
+/** @file
+ *
+ * Platform Extension Plugin (PEP).
+ *
+ * Copyright (c) 2019, ARM Ltd. All rights reserved.
+ * Copyright (c) 2018, Andrey Warkentin <andrey.warkentin@gmail.com>
+ * Copyright (c) Microsoft Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+Device(PEPD)
+{
+ //
+ // PEP virtual device.
+ //
+ Name (_HID, "BCM2854") // Note: Since PEP on RPi is a virtual device,
+ Name (_CID, "BCM2854") // its device id needs to be generated by Microsoft
+ Name (_UID, 0x0)
+ Name (_CRS, ResourceTemplate ()
+ {
+ // No hardware resources for PEP driver are needed.
+ })
+
+ //
+ // Processor info. PEP proprietary method to return
+ // PEP_PROCESSOR_TABLE_PLAT structure.
+ //
+ // See Pep.h and Pep.c.
+ //
+ Name (_GPI, Buffer()
+ {
+ 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x5F, 0x00, 0x53,
+ 0x00, 0x42, 0x00, 0x2E, 0x00, 0x43, 0x00, 0x50, 0x00, 0x55, 0x00, 0x30,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ })
+
+ //
+ // Coordinated state info. PEP proprietary method to return
+ // PEP_COORDINATED_STATE_TABLE_PLAT structure.
+ //
+ // See Pep.h and Pep.c.
+ //
+ Name (_GCI, Buffer()
+ {
+ 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00
+ })
+
+ //
+ // Device info. PEP proprietary method to return
+ // PEP_DEVICE_TABLE_PLAT structure.
+ //
+ // See Pep.h and Pep.c.
+ //
+ Name (_GDI, Buffer()
+ {
+ 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x5F, 0x00, 0x53,
+ 0x00, 0x42, 0x00, 0x2E, 0x00, 0x49, 0x00, 0x32, 0x00, 0x43, 0x00, 0x30,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09,
+ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ })
+}
diff --git a/board/raspberrypi/rpi/rhpx.asl b/board/raspberrypi/rpi/rhpx.asl
new file mode 100644
index 0000000..214b55c
--- /dev/null
+++ b/board/raspberrypi/rpi/rhpx.asl
@@ -0,0 +1,195 @@
+/** @file
+ *
+ * [DSDT] RHProxy device to enable WinRT API (RHPX)
+ *
+ * Copyright (c) 2018, Andrey Warkentin <andrey.warkentin@gmail.com>
+ * Copyright (c) Microsoft Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+Device (RHPX)
+{
+ Name (_HID, "MSFT8000")
+ Name (_CID, "MSFT8000")
+ Name (_UID, 1)
+
+ Name(_CRS, ResourceTemplate ()
+ {
+ // Index 0
+ SPISerialBus ( // SCKL - GPIO 11 - Pin 23
+ // MOSI - GPIO 10 - Pin 19
+ // MISO - GPIO 9 - Pin 21
+ // CE0 - GPIO 8 - Pin 24
+ 0, // Device selection (CE0)
+ PolarityLow, // Device selection polarity
+ FourWireMode, // WireMode
+ 8, // DataBit len
+ ControllerInitiated, // Slave mode
+ 4000000, // Connection speed
+ ClockPolarityLow, // Clock polarity
+ ClockPhaseFirst, // Clock phase
+ "\\_SB.GDV0.SPI0", // ResourceSource: SPI bus controller name
+ 0, // ResourceSourceIndex
+ // Resource usage
+ // DescriptorName: creates name for offset of resource descriptor
+ ) // Vendor Data
+
+ // Index 1
+ SPISerialBus ( // SCKL - GPIO 11 - Pin 23
+ // MOSI - GPIO 10 - Pin 19
+ // MISO - GPIO 9 - Pin 21
+ // CE1 - GPIO 7 - Pin 26
+ 1, // Device selection (CE1)
+ PolarityLow, // Device selection polarity
+ FourWireMode, // WireMode
+ 8, // DataBit len
+ ControllerInitiated, // Slave mode
+ 4000000, // Connection speed
+ ClockPolarityLow, // Clock polarity
+ ClockPhaseFirst, // Clock phase
+ "\\_SB.GDV0.SPI0", // ResourceSource: SPI bus controller name
+ 0, // ResourceSourceIndex
+ // Resource usage
+ // DescriptorName: creates name for offset of resource descriptor
+ ) // Vendor Data
+
+ // Index 2
+ I2CSerialBus ( // Pin 3 (GPIO2, SDA1), 5 (GPIO3, SCL1)
+ 0xFFFF, // SlaveAddress: placeholder
+ , // SlaveMode: default to ControllerInitiated
+ 0, // ConnectionSpeed: placeholder
+ , // Addressing Mode: default to 7 bit
+ "\\_SB.GDV0.I2C1", // ResourceSource: I2C bus controller name
+ ,
+ ,
+ , // Descriptor Name: creates name for offset of resource descriptor
+ ) // Vendor Data
+
+ // Index 3
+ SPISerialBus ( // SPI1_SCLK - GPIO21
+ // SPI1_MOSI - GPIO20
+ // SPI1_MISO - GPIO19
+ // SPI1_CE2_N - GPIO16
+ 2, // Device selection (CE2)
+ PolarityLow, // Device selection polarity
+ FourWireMode, // WireMode
+ 8, // DataBit len
+ ControllerInitiated, // Slave mode
+ 4000000, // Connection speed
+ ClockPolarityLow, // Clock polarity
+ ClockPhaseFirst, // Clock phase
+ "\\_SB.GDV0.SPI1", // ResourceSource: SPI bus controller name
+ 0, // ResourceSourceIndex
+ // Resource usage
+ // DescriptorName: creates name for offset of resource descriptor
+ ) // Vendor Data
+
+ // GPIO 2
+ GpioIO (Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 2 }
+ GpioInt (Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GDV0.GPI0",) { 2 }
+ // GPIO 3
+ GpioIO (Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 3 }
+ GpioInt (Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GDV0.GPI0",) { 3 }
+ // GPIO 4
+ GpioIO (Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 4 }
+ GpioInt (Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GDV0.GPI0",) { 4 }
+ // GPIO 5
+ GpioIO (Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 5 }
+ GpioInt (Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GDV0.GPI0",) { 5 }
+ // GPIO 6
+ GpioIO (Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 6 }
+ GpioInt (Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GDV0.GPI0",) { 6 }
+ // GPIO 7
+ GpioIO (Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 7 }
+ GpioInt (Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GDV0.GPI0",) { 7 }
+ // GPIO 8
+ GpioIO (Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 8 }
+ GpioInt (Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GDV0.GPI0",) { 8 }
+ // GPIO 9
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 9 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 9 }
+ // GPIO 10
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 10 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 10 }
+ // GPIO 11
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 11 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 11 }
+ // GPIO 12
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 12 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 12 }
+ // GPIO 13
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 13 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 13 }
+ // NTRAID#MSFT-7141401-2016/04/7-jordanrh - disable UART muxing
+ // until a proper solution can be created for the dmap conflict
+ // GPIO 14 - UART TX
+ // GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 14 }
+ // GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 14 }
+ // GPIO 15 - UART RX
+ // GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 15 }
+ // GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 15 }
+ // GPIO 16
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 16 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 16 }
+ // GPIO 17
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 17 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 17 }
+ // GPIO 18
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 18 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 18 }
+ // GPIO 19
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 19 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 19 }
+ // GPIO 20
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 20 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 20 }
+ // GPIO 21
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 21 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 21 }
+ // GPIO 22
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 22 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 22 }
+ // GPIO 23
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 23 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 23 }
+ // GPIO 24
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 24 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 24 }
+ // GPIO 25
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 25 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 25 }
+ // GPIO 26
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 26 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 26 }
+ // GPIO 27
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 27 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 27 }
+ })
+
+ Name (_DSD, Package()
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ // Reference http://www.raspberrypi.org/documentation/hardware/raspberrypi/spi/README.md
+ // SPI 0
+ Package (2) { "bus-SPI-SPI0", Package() { 0, 1 } }, // Index 0 & 1
+ Package (2) { "SPI0-MinClockInHz", 7629 }, // 7629 Hz
+ Package (2) { "SPI0-MaxClockInHz", 125000000 }, // 125 MHz
+ Package (2) { "SPI0-SupportedDataBitLengths", Package() { 8 } }, // Data Bit Length
+ // I2C1
+ Package (2) { "bus-I2C-I2C1", Package() { 2 } },
+ // GPIO Pin Count and supported drive modes
+ Package (2) { "GPIO-PinCount", 54 },
+ Package (2) { "GPIO-UseDescriptorPinNumbers", 1 },
+ Package (2) { "GPIO-SupportedDriveModes", 0xf }, // InputHighImpedance, InputPullUp, InputPullDown, OutputCmos
+ // SPI 1
+ Package (2) { "bus-SPI-SPI1", Package() { 3 }}, // Index 3
+ Package (2) { "SPI1-MinClockInHz", 30511 }, // 30.5 kHz
+ Package (2) { "SPI1-MaxClockInHz", 20000000 }, // 20 MHz
+ Package (2) { "SPI1-SupportedDataBitLengths", Package() { 8 } }, // Data Bit Length
+ }
+ })
+}
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index ab5ea85..9122f33 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -23,6 +23,11 @@
#endif
#include <watchdog.h>
#include <dm/pinctrl.h>
+#include <dm/ofnode.h>
+#include <acpi/acpi_table.h>
+#include <acpi/acpigen.h>
+#include <dm/lists.h>
+#include <tables_csum.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -583,3 +588,181 @@
return 0;
}
+
+#if CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE)
+static bool is_rpi4(void)
+{
+ return of_machine_is_compatible("brcm,bcm2711") ||
+ of_machine_is_compatible("brcm,bcm2712");
+}
+
+static bool is_rpi3(void)
+{
+ return of_machine_is_compatible("brcm,bcm2837");
+}
+
+static int acpi_rpi_board_fill_ssdt(struct acpi_ctx *ctx)
+{
+ int node, ret, uart_in_use, mini_clock_rate;
+ bool enabled;
+ struct udevice *dev;
+ struct {
+ const char *fdt_compatible;
+ const char *acpi_scope;
+ bool on_rpi4;
+ bool on_rpi3;
+ u32 mmio_address;
+ } map[] = {
+ {"brcm,bcm2711-pcie", "\\_SB.PCI0", true, false},
+ {"brcm,bcm2711-emmc2", "\\_SB.GDV1.SDC3", true, false},
+ {"brcm,bcm2835-pwm", "\\_SB.GDV0.PWM0", true, true},
+ {"brcm,bcm2711-genet-v5", "\\_SB.ETH0", true, false},
+ {"brcm,bcm2711-thermal", "\\_SB.EC00", true, true},
+ {"brcm,bcm2835-sdhci", "\\_SB.SDC1", true, true},
+ {"brcm,bcm2835-sdhost", "\\_SB.SDC2", false, true},
+ {"brcm,bcm2835-mbox", "\\_SB.GDV0.RPIQ", true, true},
+ {"brcm,bcm2835-i2c", "\\_SB.GDV0.I2C1", true, true, 0xfe205000},
+ {"brcm,bcm2835-i2c", "\\_SB.GDV0.I2C2", true, true, 0xfe804000},
+ {"brcm,bcm2835-spi", "\\_SB.GDV0.SPI0", true, true},
+ {"brcm,bcm2835-aux-spi", "\\_SB.GDV0.SPI1", true, true, 0xfe215080},
+ {"arm,pl011", "\\_SB.URT0", true, true},
+ {"brcm,bcm2835-aux-uart", "\\_SB.URTM", true, true},
+ { /* Sentinel */ }
+ };
+
+ /* Device enable */
+ for (int i = 0; map[i].fdt_compatible; i++) {
+ if ((is_rpi4() && !map[i].on_rpi4) ||
+ (is_rpi3() && !map[i].on_rpi3)) {
+ enabled = false;
+ } else {
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
+ map[i].fdt_compatible);
+ while (node != -FDT_ERR_NOTFOUND && map[i].mmio_address) {
+ struct fdt_resource r;
+
+ ret = fdt_get_resource(gd->fdt_blob, node, "reg", 0, &r);
+ if (ret) {
+ node = -FDT_ERR_NOTFOUND;
+ break;
+ }
+
+ if (r.start == map[i].mmio_address)
+ break;
+
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, node,
+ map[i].fdt_compatible);
+ }
+
+ enabled = (node > 0) ? fdtdec_get_is_enabled(gd->fdt_blob, node) : 0;
+ }
+ acpigen_write_scope(ctx, map[i].acpi_scope);
+ acpigen_write_name_integer(ctx, "_STA", enabled ? 0xf : 0);
+ acpigen_pop_len(ctx);
+ }
+
+ /* GPIO quirks */
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "brcm,bcm2835-gpio");
+ if (node <= 0)
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "brcm,bcm2711-gpio");
+
+ acpigen_write_scope(ctx, "\\_SB.GDV0.GPI0");
+ enabled = (node > 0) ? fdtdec_get_is_enabled(gd->fdt_blob, node) : 0;
+ acpigen_write_name_integer(ctx, "_STA", enabled ? 0xf : 0);
+ acpigen_pop_len(ctx);
+
+ if (is_rpi4()) {
+ /* eMMC quirks */
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "brcm,bcm2711-emmc2");
+ if (node) {
+ phys_addr_t cpu;
+ dma_addr_t bus;
+ u64 size;
+
+ ret = fdt_get_dma_range(gd->fdt_blob, node, &cpu, &bus, &size);
+
+ acpigen_write_scope(ctx, "\\_SB.GDV1");
+ acpigen_write_method_serialized(ctx, "_DMA", 0);
+ acpigen_emit_byte(ctx, RETURN_OP);
+
+ if (!ret && bus != cpu) /* Translated DMA range */
+ acpigen_emit_namestring(ctx, "\\_SB.GDV1.DMTR");
+ else if (!ret && bus == cpu) /* Non translated DMA */
+ acpigen_emit_namestring(ctx, "\\_SB.GDV1.DMNT");
+ else /* Silicon revisions older than C0: Translated DMA range */
+ acpigen_emit_namestring(ctx, "\\_SB.GDV1.DMTR");
+ acpigen_pop_len(ctx);
+ }
+ }
+
+ /* Serial */
+ uart_in_use = ~0;
+ mini_clock_rate = 0x1000000;
+
+ ret = uclass_get_device_by_driver(UCLASS_SERIAL,
+ DM_DRIVER_GET(bcm283x_pl011_uart),
+ &dev);
+ if (!ret)
+ uart_in_use = 0;
+
+ ret = uclass_get_device_by_driver(UCLASS_SERIAL,
+ DM_DRIVER_GET(serial_bcm283x_mu),
+ &dev);
+ if (!ret) {
+ if (uart_in_use == 0)
+ log_err("Invalid config: PL011 and MiniUART are both enabled.");
+ else
+ uart_in_use = 1;
+
+ mini_clock_rate = dev_read_u32_default(dev, "clock", 0x1000000);
+ }
+ if (uart_in_use > 1)
+ log_err("No working serial: PL011 and MiniUART are both disabled.");
+
+ acpigen_write_scope(ctx, "\\_SB.BTH0");
+ acpigen_write_name_integer(ctx, "URIU", uart_in_use);
+ acpigen_pop_len(ctx);
+
+ acpigen_write_scope(ctx, "\\_SB.URTM");
+ acpigen_write_name_integer(ctx, "MUCR", mini_clock_rate);
+ acpigen_pop_len(ctx);
+
+ return 0;
+}
+
+static int rpi_acpi_write_ssdt(struct acpi_ctx *ctx, const struct acpi_writer *entry)
+{
+ struct acpi_table_header *ssdt;
+ int ret;
+
+ ssdt = ctx->current;
+ memset(ssdt, '\0', sizeof(struct acpi_table_header));
+
+ acpi_fill_header(ssdt, "SSDT");
+ ssdt->revision = acpi_get_table_revision(ACPITAB_SSDT);
+ ssdt->creator_revision = 1;
+ ssdt->length = sizeof(struct acpi_table_header);
+
+ acpi_inc(ctx, sizeof(struct acpi_table_header));
+
+ ret = acpi_rpi_board_fill_ssdt(ctx);
+ if (ret) {
+ ctx->current = ssdt;
+ return log_msg_ret("fill", ret);
+ }
+
+ /* (Re)calculate length and checksum */
+ ssdt->length = ctx->current - (void *)ssdt;
+ ssdt->checksum = table_compute_checksum((void *)ssdt, ssdt->length);
+ log_debug("SSDT at %p, length %x\n", ssdt, ssdt->length);
+
+ /* Drop the table if it is empty */
+ if (ssdt->length == sizeof(struct acpi_table_header))
+ return log_msg_ret("fill", -ENOENT);
+ acpi_add_table(ctx, ssdt);
+
+ return 0;
+}
+
+ACPI_WRITER(5ssdt, "SSDT", rpi_acpi_write_ssdt, 0);
+#endif
diff --git a/board/raspberrypi/rpi/sdhc.asl b/board/raspberrypi/rpi/sdhc.asl
new file mode 100644
index 0000000..3feac14
--- /dev/null
+++ b/board/raspberrypi/rpi/sdhc.asl
@@ -0,0 +1,111 @@
+/** @file
+ *
+ * [DSDT] SD controller/card definition (SDHC)
+ *
+ * Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ * Copyright (c) 2018, Andrey Warkentin <andrey.warkentin@gmail.com>
+ * Copyright (c) Microsoft Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <asm/arch/acpi/bcm2836_sdhost.h>
+#include <asm/arch/acpi/bcm2836_sdio.h>
+
+#include "acpitables.h"
+
+//
+// Note: UEFI can use either SDHost or Arasan. We expose both to the OS.
+//
+
+// ArasanSD 3.0 SD Host Controller. (brcm,bcm2835-sdhci)
+Device (SDC1)
+{
+ Name (_HID, "BCM2847")
+ Name (_CID, "BCM2847")
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
+ Name (_S1D, 0x1)
+ Name (_S2D, 0x1)
+ Name (_S3D, 0x1)
+ Name (_S4D, 0x1)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, MMCHS1_LENGTH, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) { BCM2836_MMCHS1_INTERRUPT }
+ })
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, MMCHS1_OFFSET)
+ Return (^RBUF)
+ }
+
+ // The standard CAPs registers on this controller
+ // appear to be 0, lets set some minimal defaults
+ // Since this cap doesn't indicate DMA capability
+ // we don't need a _DMA()
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "sdhci-caps", 0x0120fa81 },
+ }
+ })
+
+ //
+ // A child device that represents the
+ // sd card, which is marked as non-removable.
+ //
+ Device (SDMM)
+ {
+ Method (_ADR)
+ {
+ Return (0)
+ }
+ Method (_RMV) // Is removable
+ {
+ Return (0) // 0 - fixed
+ }
+ }
+}
+
+// Broadcom SDHost 2.0 SD Host Controller
+Device (SDC2)
+{
+ Name (_HID, "BCM2855")
+ Name (_CID, "BCM2855")
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
+ Name (_S1D, 0x1)
+ Name (_S2D, 0x1)
+ Name (_S3D, 0x1)
+ Name (_S4D, 0x1)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, SDHOST_LENGTH, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_SDHOST_INTERRUPT }
+ })
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, SDHOST_OFFSET)
+ Return (^RBUF)
+ }
+
+ //
+ // A child device that represents the
+ // sd card, which is marked as non-removable.
+ //
+ Device (SDMM)
+ {
+ Method (_ADR)
+ {
+ Return (0)
+ }
+ Method (_RMV) // Is removable
+ {
+ Return (0) // 0 - fixed
+ }
+ }
+}
\ No newline at end of file
diff --git a/board/raspberrypi/rpi/uart.asl b/board/raspberrypi/rpi/uart.asl
new file mode 100644
index 0000000..78dc9a7
--- /dev/null
+++ b/board/raspberrypi/rpi/uart.asl
@@ -0,0 +1,208 @@
+/** @file
+ *
+ * [DSDT] Serial devices (UART).
+ *
+ * Copyright (c) 2021, ARM Limited. All rights reserved.
+ * Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ * Copyright (c) 2018, Andrey Warkentin <andrey.warkentin@gmail.com>
+ * Copyright (c) Microsoft Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <asm/arch/acpi/bcm2836.h>
+
+#include "acpitables.h"
+
+// PL011 based UART.
+Device (URT0)
+{
+ Name (_HID, "BCM2837")
+ Name (_CID, "ARMH0011")
+ Name (_UID, 0x4)
+ Name (_CCA, 0x0)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_PL011_UART_LENGTH, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_PL011_UART_INTERRUPT }
+ })
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_PL011_UART_OFFSET)
+ Return (^RBUF)
+ }
+
+ Name (CLCK, 48000000)
+
+ Name (_DSD, Package ()
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package ()
+ {
+ Package (2) { "clock-frequency", CLCK },
+ }
+ })
+}
+
+//
+// UART Mini.
+//
+// This device is referenced in the DBG2 table, which will cause the system to
+// not start the driver when the debugger is enabled and to mark the device
+// with problem code 53 (CM_PROB_USED_BY_DEBUGGER).
+//
+
+Device (URTM)
+{
+ Name (_HID, "BCM2836")
+ Name (_CID, "BCM2836")
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_MINI_UART_LENGTH, RMEM)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Shared) { BCM2836_MINI_UART_INTERRUPT }
+
+ })
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_MINI_UART_OFFSET)
+ Return (^RBUF)
+ }
+
+ //
+ // Mini Uart Clock Rate will be dynamically updated during boot
+ //
+ External (\_SB.URTM.MUCR, IntObj)
+
+ Name (_DSD, Package ()
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package ()
+ {
+ Package (2) { "clock-frequency", MUCR },
+ }
+ })
+}
+
+//
+// Multifunction serial bus device to support Bluetooth function.
+//
+Device(BTH0)
+{
+ Name (_HID, "BCM2EA6")
+ Name (_CID, "BCM2EA6")
+
+ //
+ // UART In Use will be dynamically updated during boot
+ //
+ External (\_SB.BTH0.URIU, IntObj)
+
+ Method (_STA)
+ {
+ Return (0xf)
+ }
+
+ //
+ // Resource for URT0 (PL011)
+ //
+ Name (BTPL, ResourceTemplate ()
+ {
+ UARTSerialBus(
+ 115200, // InitialBaudRate: in BPS
+ , // BitsPerByte: default to 8 bits
+ , // StopBits: Defaults to one bit
+ 0x00, // LinesInUse: 8 1-bit flags to
+ // declare enabled control lines.
+ // Raspberry Pi does not exposed
+ // HW control signals -> not supported.
+ // Optional bits:
+ // - Bit 7 (0x80) Request To Send (RTS)
+ // - Bit 6 (0x40) Clear To Send (CTS)
+ // - Bit 5 (0x20) Data Terminal Ready (DTR)
+ // - Bit 4 (0x10) Data Set Ready (DSR)
+ // - Bit 3 (0x08) Ring Indicator (RI)
+ // - Bit 2 (0x04) Data Carrier Detect (DTD)
+ // - Bit 1 (0x02) Reserved. Must be 0.
+ // - Bit 0 (0x01) Reserved. Must be 0.
+ , // IsBigEndian:
+ // default to LittleEndian.
+ , // Parity: Defaults to no parity
+ , // FlowControl: Defaults to
+ // no flow control.
+ 16, // ReceiveBufferSize
+ 16, // TransmitBufferSize
+ "\\_SB.GDV0.URT0", // ResourceSource:
+ // UART bus controller name
+ , // ResourceSourceIndex: assumed to be 0
+ , // ResourceUsage: assumed to be
+ // ResourceConsumer
+ UAR0, // DescriptorName: creates name
+ // for offset of resource descriptor
+ ) // Vendor data
+ })
+
+ //
+ // Resource for URTM (miniUART)
+ //
+ Name (BTMN, ResourceTemplate ()
+ {
+ //
+ // BT UART: ResourceSource will be dynamically updated to
+ // either URT0 (PL011) or URTM (miniUART) during boot
+ //
+ UARTSerialBus(
+ 115200, // InitialBaudRate: in BPS
+ , // BitsPerByte: default to 8 bits
+ , // StopBits: Defaults to one bit
+ 0x00, // LinesInUse: 8 1-bit flags to
+ // declare enabled control lines.
+ // Raspberry Pi does not exposed
+ // HW control signals -> not supported.
+ // Optional bits:
+ // - Bit 7 (0x80) Request To Send (RTS)
+ // - Bit 6 (0x40) Clear To Send (CTS)
+ // - Bit 5 (0x20) Data Terminal Ready (DTR)
+ // - Bit 4 (0x10) Data Set Ready (DSR)
+ // - Bit 3 (0x08) Ring Indicator (RI)
+ // - Bit 2 (0x04) Data Carrier Detect (DTD)
+ // - Bit 1 (0x02) Reserved. Must be 0.
+ // - Bit 0 (0x01) Reserved. Must be 0.
+ , // IsBigEndian:
+ // default to LittleEndian.
+ , // Parity: Defaults to no parity
+ , // FlowControl: Defaults to
+ // no flow control.
+ 16, // ReceiveBufferSize
+ 16, // TransmitBufferSize
+ "\\_SB.GDV0.URTM", // ResourceSource:
+ // UART bus controller name
+ , // ResourceSourceIndex: assumed to be 0
+ , // ResourceUsage: assumed to be
+ // ResourceConsumer
+ UARM, // DescriptorName: creates name
+ // for offset of resource descriptor
+ ) // Vendor data
+ })
+
+ Method (_CRS, 0x0, Serialized)
+ {
+ if (URIU == 0)
+ {
+ //
+ // PL011 UART is configured for console output
+ // Return Mini UART for Bluetooth
+ //
+ return (^BTMN)
+ }
+ else
+ {
+ //
+ // Mini UART is configured for console output
+ // Return PL011 UART for Bluetooth
+ //
+ return (^BTPL)
+ }
+ }
+}
diff --git a/board/renesas/MAINTAINERS b/board/renesas/MAINTAINERS
new file mode 100644
index 0000000..13551cd
--- /dev/null
+++ b/board/renesas/MAINTAINERS
@@ -0,0 +1,17 @@
+RENESAS BOARDS
+M: Marek Vasut <marek.vasut+renesas@mailbox.org>
+M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+S: Maintained
+N: grpeach
+N: r2dplus
+N: r7s72100
+N: r8a66597
+N: r8a77
+N: r9a0[0-9]g
+N: rcar
+N: renesas
+N: rza1
+N: rzg2l
+N: serial_sh
+N: sh77
+N: sh_eth
diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c
index ed292c3..e6bedc3 100644
--- a/board/siemens/iot2050/board.c
+++ b/board/siemens/iot2050/board.c
@@ -38,6 +38,8 @@
u8 mac_addr_cnt;
u8 mac_addr[8][ARP_HLEN];
char seboot_version[40 + 1];
+ u8 padding[3];
+ u32 ddr_size_mb;
} __packed;
/*
@@ -172,6 +174,14 @@
strcmp((char *)info->name, "IOT2050-ADVANCED-M2") == 0;
}
+static bool board_is_sm(void)
+{
+ struct iot2050_info *info = IOT2050_INFO_DATA;
+
+ return info->magic == IOT2050_INFO_MAGIC &&
+ strcmp((char *)info->name, "IOT2050-ADVANCED-SM") == 0;
+}
+
static void remove_mmc1_target(void)
{
char *boot_targets = strdup(env_get("boot_targets"));
@@ -185,6 +195,15 @@
free(boot_targets);
}
+static void enable_pcie_connector_power(void)
+{
+ if (board_is_sm())
+ set_pinvalue("gpio@601000_22", "P3V3_PCIE_CON_EN", 1);
+ else
+ set_pinvalue("gpio@601000_17", "P3V3_PCIE_CON_EN", 1);
+ udelay(4 * 100);
+}
+
void set_board_info_env(void)
{
struct iot2050_info *info = IOT2050_INFO_DATA;
@@ -220,8 +239,10 @@
if (board_is_advanced()) {
if (board_is_pg1())
fdtfile = "ti/k3-am6548-iot2050-advanced.dtb";
- else if(board_is_m2())
+ else if (board_is_m2())
fdtfile = "ti/k3-am6548-iot2050-advanced-m2.dtb";
+ else if (board_is_sm())
+ fdtfile = "ti/k3-am6548-iot2050-advanced-sm.dtb";
else
fdtfile = "ti/k3-am6548-iot2050-advanced-pg2.dtb";
} else {
@@ -237,23 +258,14 @@
env_save();
}
-static void m2_overlay_prepare(void)
+static void do_overlay_prepare(const char *overlay_path)
{
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
- const char *overlay_path;
void *overlay;
u64 loadaddr;
ofnode node;
int ret;
- if (connector_mode == BKEY_PCIEX2)
- return;
-
- if (connector_mode == BKEY_PCIE_EKEY_PCIE)
- overlay_path = "/fit-images/bkey-ekey-pcie-overlay";
- else
- overlay_path = "/fit-images/bkey-usb3-overlay";
-
node = ofnode_path(overlay_path);
if (!ofnode_valid(node))
goto fit_error;
@@ -280,6 +292,21 @@
#endif
}
+static void m2_overlay_prepare(void)
+{
+ const char *overlay_path;
+
+ if (connector_mode == BKEY_PCIEX2)
+ return;
+
+ if (connector_mode == BKEY_PCIE_EKEY_PCIE)
+ overlay_path = "/fit-images/bkey-ekey-pcie-overlay";
+ else
+ overlay_path = "/fit-images/bkey-usb3-overlay";
+
+ do_overlay_prepare(overlay_path);
+}
+
static void m2_connector_setup(void)
{
ulong m2_manual_config = env_get_ulong("m2_manual_config", 10,
@@ -288,10 +315,6 @@
struct m2_config_pins config_pins;
unsigned int n;
- /* enable M.2 connector power */
- set_pinvalue("gpio@601000_17", "P3V3_M2_EN", 1);
- udelay(4 * 100);
-
if (m2_manual_config < CONNECTOR_MODE_INVALID) {
mode_info = " [manual mode]";
connector_mode = m2_manual_config;
@@ -339,25 +362,42 @@
int dram_init(void)
{
- if (board_is_advanced())
- gd->ram_size = SZ_2G;
- else
- gd->ram_size = SZ_1G;
+ struct iot2050_info *info = IOT2050_INFO_DATA;
+ gd->ram_size = ((phys_size_t)(info->ddr_size_mb)) << 20;
return 0;
}
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ /* Limit RAM used by U-Boot to the DDR low region */
+ if (gd->ram_top > 0x100000000)
+ return 0x100000000;
+
+ return gd->ram_top;
+}
+
int dram_init_banksize(void)
{
dram_init();
- /* Bank 0 declares the memory available in the DDR low region */
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = gd->ram_size;
+ if (gd->ram_size > SZ_2G) {
+ /* Bank 0 declares the memory available in the DDR low region */
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = SZ_2G;
- /* Bank 1 declares the memory available in the DDR high region */
- gd->bd->bi_dram[1].start = 0;
- gd->bd->bi_dram[1].size = 0;
+ /* Bank 1 declares the memory available in the DDR high region */
+ gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
+ gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
+ } else {
+ /* Bank 0 declares the memory available in the DDR low region */
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+
+ /* Bank 1 declares the memory available in the DDR high region */
+ gd->bd->bi_dram[1].start = 0;
+ gd->bd->bi_dram[1].size = 0;
+ }
return 0;
}
@@ -368,8 +408,8 @@
struct iot2050_info *info = IOT2050_INFO_DATA;
char upper_name[32];
- /* skip the prefix "k3-am65x8-" */
- name += 10;
+ /* skip the prefix "ti/k3-am65x8-" */
+ name += 13;
if (info->magic != IOT2050_INFO_MAGIC ||
strlen(name) >= sizeof(upper_name))
@@ -429,6 +469,8 @@
/* change CTRL_MMR register to let serdes0 not output USB3.0 signals. */
writel(0x3, SERDES0_LANE_SELECT);
+ enable_pcie_connector_power();
+
if (board_is_m2())
m2_connector_setup();
@@ -443,7 +485,7 @@
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-static void m2_fdt_fixup(void *blob)
+static void variants_fdt_fixup(void *blob)
{
void *overlay_copy = NULL;
void *fdt_copy = NULL;
@@ -483,14 +525,14 @@
return;
fixup_error:
- pr_err("Could not apply M.2 device tree overlay\n");
+ pr_err("Could not apply device tree overlay\n");
goto cleanup;
}
int ft_board_setup(void *blob, struct bd_info *bd)
{
if (board_is_m2())
- m2_fdt_fixup(blob);
+ variants_fdt_fixup(blob);
return 0;
}
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index f55c6b5..3fd535e 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -41,7 +41,7 @@
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
"motorcomm,rx-data-drv-microamp", "2910"},
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
- "rx-internal-delay-ps", "1900"},
+ "rx-internal-delay-ps", "1500"},
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
"tx-internal-delay-ps", "1500"},
};
@@ -68,9 +68,7 @@
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
"motorcomm,rx-data-drv-microamp", "2910"},
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
- "rx-internal-delay-ps", "1900"},
- {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
- "tx-internal-delay-ps", "1500"},
+ "rx-internal-delay-ps", "1500"},
{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
"motorcomm,tx-clk-adj-enabled", NULL},
diff --git a/board/ti/j784s4/MAINTAINERS b/board/ti/j784s4/MAINTAINERS
index b7605ff3..e92e8d0 100644
--- a/board/ti/j784s4/MAINTAINERS
+++ b/board/ti/j784s4/MAINTAINERS
@@ -8,6 +8,7 @@
F: configs/j784s4_evm_a72_defconfig
F: arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
F: arch/arm/dts/k3-j784s4-r5-evm.dts
+F: arch/arm/dts/k3-j784s4-r5.dtsi
F: arch/arm/dts/k3-j784s4-ddr.dtsi
F: arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi
F: doc/board/ti/j784s4_evm.rst
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index 4854771..a92aa5c 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -49,8 +49,10 @@
gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
CFG_MAX_RAM_BANK_SIZE);
#if defined(CONFIG_TI_AEMIF)
- if (!(board_is_k2g_ice() || board_is_k2g_i1()))
+ if (!(board_is_k2g_ice() || board_is_k2g_i1())) {
+ aemif_configs->base = (void *)KS2_AEMIF_CNTRL_BASE;
aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
+ }
#endif
if (!(board_is_k2g_ice() || board_is_k2g_i1())) {
diff --git a/board/xilinx/mbv/Kconfig b/board/xilinx/mbv/Kconfig
index a3a6f21..c52ba18 100644
--- a/board/xilinx/mbv/Kconfig
+++ b/board/xilinx/mbv/Kconfig
@@ -10,14 +10,14 @@
default "generic"
config TEXT_BASE
- default 0x21200000
+ default 0x81200000
config SPL_TEXT_BASE
- default 0x20000000
+ default 0x80000000
config SPL_OPENSBI_LOAD_ADDR
hex
- default 0x20200000
+ default 0x80200000
config BOARD_SPECIFIC_OPTIONS
def_bool y
diff --git a/boot/Kconfig b/boot/Kconfig
index b9287c6..7dd30a0 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig
@@ -1699,7 +1699,7 @@
memory
config ARCH_FIXUP_FDT_MEMORY
- bool "Enable arch_fixup_memory_banks() call"
+ bool "Enable fdt_fixup_memory_banks() call"
default y
help
Enable FDT memory map syncup before OS boot. This feature can be
diff --git a/boot/bootflow.c b/boot/bootflow.c
index 59d77d2..d8807eb 100644
--- a/boot/bootflow.c
+++ b/boot/bootflow.c
@@ -936,11 +936,15 @@
return ret;
*buf = '\0';
- if (!strcmp("earlycon", arg)) {
+ if (!strcmp("earlycon", arg) && info.type == SERIAL_CHIP_16550_COMPATIBLE) {
snprintf(buf, sizeof(buf),
"uart8250,mmio32,%#lx,%dn8", info.addr,
info.baudrate);
- } else if (!strcmp("console", arg)) {
+ } else if (!strcmp("earlycon", arg) && info.type == SERIAL_CHIP_PL01X) {
+ snprintf(buf, sizeof(buf),
+ "pl011,mmio32,%#lx,%dn8", info.addr,
+ info.baudrate);
+ } else if (!strcmp("console", arg) && info.type == SERIAL_CHIP_16550_COMPATIBLE) {
snprintf(buf, sizeof(buf),
"ttyS0,%dn8", info.baudrate);
}
diff --git a/boot/image-fdt.c b/boot/image-fdt.c
index 8eda521..3d5b6f9 100644
--- a/boot/image-fdt.c
+++ b/boot/image-fdt.c
@@ -73,7 +73,7 @@
long ret;
ret = lmb_reserve_flags(addr, size, flags);
- if (ret >= 0) {
+ if (!ret) {
debug(" reserving fdt memory region: addr=%llx size=%llx flags=%x\n",
(unsigned long long)addr,
(unsigned long long)size, flags);
@@ -110,7 +110,7 @@
for (i = 0; i < total; i++) {
if (fdt_get_mem_rsv(fdt_blob, i, &addr, &size) != 0)
continue;
- boot_fdt_reserve_region(addr, size, LMB_NONE);
+ boot_fdt_reserve_region(addr, size, LMB_NOOVERWRITE);
}
/* process reserved-memory */
@@ -122,7 +122,7 @@
ret = fdt_get_resource(fdt_blob, subnode, "reg", 0,
&res);
if (!ret && fdtdec_get_is_enabled(fdt_blob, subnode)) {
- flags = LMB_NONE;
+ flags = LMB_NOOVERWRITE;
if (fdtdec_get_bool(fdt_blob, subnode,
"no-map"))
flags = LMB_NOMAP;
diff --git a/cmd/Makefile b/cmd/Makefile
index b4668eb..d1f369d 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -127,13 +127,10 @@
endif
obj-$(CONFIG_CMD_MUX) += mux.o
obj-$(CONFIG_CMD_NAND) += nand.o
-ifdef CONFIG_CMD_NET
-obj-$(CONFIG_NET) += net.o
-obj-$(CONFIG_NET_LWIP) += net-lwip.o
-obj-$(filter y,$(CONFIG_CMD_NET) $(CONFIG_CMD_NET_LWIP)) += net-common.o
-lwip-includes := -I$(srctree)/lib/lwip/lwip/src/include -I$(srctree)/lib/lwip/u-boot
-CFLAGS_net-lwip.o := $(lwip-includes)
-CFLAGS_net-common.o := $(lwip-includes)
+ifdef CONFIG_NET
+obj-$(CONFIG_CMD_NET) += net.o net-common.o
+else ifdef CONFIG_NET_LWIP
+obj-$(CONFIG_CMD_NET) += net-lwip.o net-common.o
endif
obj-$(CONFIG_ENV_SUPPORT) += nvedit.o
obj-$(CONFIG_CMD_NVEDIT_EFI) += nvedit_efi.o
diff --git a/cmd/eficonfig.c b/cmd/eficonfig.c
index bea09e4..0291802 100644
--- a/cmd/eficonfig.c
+++ b/cmd/eficonfig.c
@@ -963,7 +963,7 @@
return handle_user_input(bo->description, EFICONFIG_DESCRIPTION_MAX, 22,
"\n ** Edit Description **\n"
"\n"
- " enter description: ");
+ " Enter description: ");
}
/**
diff --git a/cmd/fat.c b/cmd/fat.c
index 1655e80..5b7484d 100644
--- a/cmd/fat.c
+++ b/cmd/fat.c
@@ -14,7 +14,7 @@
#include <part.h>
#include <asm/cache.h>
-int do_fat_size(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+static int do_fat_size(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
return do_size(cmdtp, flag, argc, argv, FS_TYPE_FAT);
}
diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c
index a231604..5ecf567 100644
--- a/cmd/riscv/sbi.c
+++ b/cmd/riscv/sbi.c
@@ -54,8 +54,10 @@
{ SBI_EXT_CPPC, "Collaborative Processor Performance Control Extension" },
{ SBI_EXT_NACL, "Nested Acceleration Extension" },
{ SBI_EXT_STA, "Steal-time Accounting Extension" },
- { SBI_EXT_DBTR, "Debug Trigger Extension" },
{ SBI_EXT_SSE, "Supervisor Software Events" },
+ { SBI_EXT_FWFT, "Firmware Features Extension" },
+ { SBI_EXT_DBTR, "Debug Triggers Extension" },
+ { SBI_EXT_MPXY, "Message Proxy Extension" },
};
static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc,
diff --git a/common/Kconfig b/common/Kconfig
index 14a6c44..e8d89bf 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -1081,6 +1081,7 @@
hex "Size of bloblist after relocation"
default BLOBLIST_SIZE if BLOBLIST_FIXED || BLOBLIST_ALLOC
default 0x0 if BLOBLIST_PASSAGE
+ default 0x20000 if (ARM && EFI_LOADER && GENERATE_ACPI_TABLE)
help
Sets the size of the bloblist in bytes after relocation. Since U-Boot
has a lot more memory available then, it is possible to use a larger
diff --git a/common/bloblist.c b/common/bloblist.c
index 6640ad1..ec6ff7a 100644
--- a/common/bloblist.c
+++ b/common/bloblist.c
@@ -499,7 +499,7 @@
{
bool fixed = IS_ENABLED(CONFIG_BLOBLIST_FIXED);
int ret = -ENOENT;
- ulong addr, size;
+ ulong addr = 0, size;
/*
* If U-Boot is not in the first phase, an existing bloblist must be
* at a fixed address.
diff --git a/common/board_r.c b/common/board_r.c
index 8a19817..62228a7 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -32,6 +32,7 @@
#include <command.h>
#include <console.h>
#include <dm.h>
+#include <efi_loader.h>
#include <env.h>
#include <env_internal.h>
#include <fdtdec.h>
@@ -63,10 +64,8 @@
#include <dm/ofnode.h>
#include <linux/compiler.h>
#include <linux/err.h>
-#include <efi_loader.h>
#include <wdt.h>
#include <asm-generic/gpio.h>
-#include <efi_loader.h>
#include <relocate.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig
index f251d69..bba25e0 100644
--- a/configs/clearfog_defconfig
+++ b/configs/clearfog_defconfig
@@ -53,7 +53,7 @@
CONFIG_NET_RETRY_COUNT=50
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/clearfog_gt_8k_defconfig b/configs/clearfog_gt_8k_defconfig
index cabd222..eaa8a33 100644
--- a/configs/clearfog_gt_8k_defconfig
+++ b/configs/clearfog_gt_8k_defconfig
@@ -46,7 +46,7 @@
CONFIG_ARP_TIMEOUT=200
CONFIG_NET_RETRY_COUNT=50
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_LBA48=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_DM_I2C=y
diff --git a/configs/clearfog_sata_defconfig b/configs/clearfog_sata_defconfig
index 8d4b54c..b82d604 100644
--- a/configs/clearfog_sata_defconfig
+++ b/configs/clearfog_sata_defconfig
@@ -53,7 +53,7 @@
CONFIG_NET_RETRY_COUNT=50
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/clearfog_spi_defconfig b/configs/clearfog_spi_defconfig
index 2f58e94..cef80d6 100644
--- a/configs/clearfog_spi_defconfig
+++ b/configs/clearfog_spi_defconfig
@@ -53,7 +53,7 @@
CONFIG_NET_RETRY_COUNT=50
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig
index b327149..5b69a20 100644
--- a/configs/db-88f6820-gp_defconfig
+++ b/configs/db-88f6820-gp_defconfig
@@ -58,7 +58,7 @@
CONFIG_ARP_TIMEOUT=200
CONFIG_NET_RETRY_COUNT=50
CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/ds116_defconfig b/configs/ds116_defconfig
index 0bb7e30..c321e6f 100644
--- a/configs/ds116_defconfig
+++ b/configs/ds116_defconfig
@@ -65,7 +65,7 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_LBA48=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_DM_I2C=y
diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig
index 61d110e..e45446c 100644
--- a/configs/helios4_defconfig
+++ b/configs/helios4_defconfig
@@ -53,7 +53,7 @@
CONFIG_NET_RETRY_COUNT=50
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/imx8mp_navqp_defconfig b/configs/imx8mp_navqp_defconfig
new file mode 100644
index 0000000..d4c10fe
--- /dev/null
+++ b/configs/imx8mp_navqp_defconfig
@@ -0,0 +1,104 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-navqp"
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_TARGET_IMX8MP_NAVQP=y
+CONFIG_SYS_MONITOR_LEN=524288
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK=0x960000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x98fc00
+CONFIG_SPL_BSS_MAX_SIZE=0x400
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="imx8mp-navqp.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
+CONFIG_SPL_MAX_SIZE=0x26000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="eth1"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PCA9450=y
+CONFIG_SPL_DM_REGULATOR_PCA9450=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_IMX_WATCHDOG=y
diff --git a/configs/iot2050_defconfig b/configs/iot2050_defconfig
index 401e57a..2624f0c 100644
--- a/configs/iot2050_defconfig
+++ b/configs/iot2050_defconfig
@@ -17,7 +17,7 @@
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-am6528-iot2050-basic"
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am6528-iot2050-basic"
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
@@ -79,8 +79,11 @@
# CONFIG_ISO_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
+CONFIG_OF_LIST="ti/k3-am6528-iot2050-basic ti/k3-am6528-iot2050-basic-pg2 ti/k3-am6548-iot2050-advanced ti/k3-am6548-iot2050-advanced-pg2 ti/k3-am6548-iot2050-advanced-m2 ti/k3-am6548-iot2050-advanced-sm"
+CONFIG_OF_OVERLAY_LIST="ti/k3-am6548-iot2050-advanced-m2-bkey-usb3 ti/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie"
CONFIG_SPL_MULTI_DTB_FIT=y
-CONFIG_SPL_OF_LIST="k3-am65-iot2050-spl"
+CONFIG_SPL_OF_LIST="ti/k3-am6528-iot2050-basic"
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig
index 94952a9..a35721a 100644
--- a/configs/microchip_mpfs_icicle_defconfig
+++ b/configs/microchip_mpfs_icicle_defconfig
@@ -4,8 +4,8 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_ENV_SIZE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="mpfs-icicle-kit"
-CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_DEFAULT_DEVICE_TREE="microchip/mpfs-icicle-kit"
+CONFIG_OF_UPSTREAM=y
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_SYS_MEM_TOP_HIDE=0x400000
CONFIG_TARGET_MICROCHIP_ICICLE=y
diff --git a/configs/mvebu_crb_cn9130_defconfig b/configs/mvebu_crb_cn9130_defconfig
index 505f063..e8984b6 100644
--- a/configs/mvebu_crb_cn9130_defconfig
+++ b/configs/mvebu_crb_cn9130_defconfig
@@ -46,7 +46,7 @@
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_ARP_TIMEOUT=200
CONFIG_NET_RETRY_COUNT=50
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_LBA48=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_DM_I2C=y
diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig
index 962edb7..e5de34c 100644
--- a/configs/mvebu_db-88f3720_defconfig
+++ b/configs/mvebu_db-88f3720_defconfig
@@ -43,7 +43,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ARP_TIMEOUT=200
CONFIG_NET_RETRY_COUNT=50
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_LBA48=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_CLK=y
diff --git a/configs/mvebu_db_armada8k_defconfig b/configs/mvebu_db_armada8k_defconfig
index 7c6b53e..f9b03a7 100644
--- a/configs/mvebu_db_armada8k_defconfig
+++ b/configs/mvebu_db_armada8k_defconfig
@@ -42,7 +42,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ARP_TIMEOUT=200
CONFIG_NET_RETRY_COUNT=50
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_LBA48=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_DM_I2C=y
diff --git a/configs/mvebu_db_cn9130_defconfig b/configs/mvebu_db_cn9130_defconfig
index f80812c..6dd6be7 100644
--- a/configs/mvebu_db_cn9130_defconfig
+++ b/configs/mvebu_db_cn9130_defconfig
@@ -47,7 +47,7 @@
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_ARP_TIMEOUT=200
CONFIG_NET_RETRY_COUNT=50
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_LBA48=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_DM_GPIO_LOOKUP_LABEL=y
diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig
index 375705c..e9ee885 100644
--- a/configs/mvebu_espressobin-88f3720_defconfig
+++ b/configs/mvebu_espressobin-88f3720_defconfig
@@ -54,7 +54,7 @@
CONFIG_NET_RETRY_COUNT=50
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_AHCI_PCI=y
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_LBA48=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_CLK=y
diff --git a/configs/mvebu_espressobin_ultra-88f3720_defconfig b/configs/mvebu_espressobin_ultra-88f3720_defconfig
index fe3def1..aa9026a 100644
--- a/configs/mvebu_espressobin_ultra-88f3720_defconfig
+++ b/configs/mvebu_espressobin_ultra-88f3720_defconfig
@@ -53,7 +53,7 @@
CONFIG_NET_RETRY_COUNT=50
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_AHCI_PCI=y
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_LBA48=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_CLK=y
diff --git a/configs/mvebu_mcbin-88f8040_defconfig b/configs/mvebu_mcbin-88f8040_defconfig
index c1b470c..90d341e 100644
--- a/configs/mvebu_mcbin-88f8040_defconfig
+++ b/configs/mvebu_mcbin-88f8040_defconfig
@@ -46,7 +46,7 @@
CONFIG_ARP_TIMEOUT=200
CONFIG_NET_RETRY_COUNT=50
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_LBA48=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_DM_I2C=y
diff --git a/configs/mvebu_puzzle-m801-88f8040_defconfig b/configs/mvebu_puzzle-m801-88f8040_defconfig
index 1d86e26..21ab217 100644
--- a/configs/mvebu_puzzle-m801-88f8040_defconfig
+++ b/configs/mvebu_puzzle-m801-88f8040_defconfig
@@ -50,7 +50,7 @@
CONFIG_ARP_TIMEOUT=200
CONFIG_NET_RETRY_COUNT=50
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_LBA48=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_DM_PCA953X=y
diff --git a/configs/n2350_defconfig b/configs/n2350_defconfig
index 8d54882..7851bc4 100644
--- a/configs/n2350_defconfig
+++ b/configs/n2350_defconfig
@@ -65,7 +65,7 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_LBA48=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_DM_I2C=y
diff --git a/configs/octeon_nic23_defconfig b/configs/octeon_nic23_defconfig
index 0febe80..76adbf2 100644
--- a/configs/octeon_nic23_defconfig
+++ b/configs/octeon_nic23_defconfig
@@ -46,7 +46,7 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_TFTP_TSIZE=y
CONFIG_SATA=y
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_LBA48=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_CLK=y
diff --git a/configs/qemu-arm-sbsa_defconfig b/configs/qemu-arm-sbsa_defconfig
new file mode 100644
index 0000000..69195af
--- /dev/null
+++ b/configs/qemu-arm-sbsa_defconfig
@@ -0,0 +1,12 @@
+CONFIG_ARM=y
+CONFIG_ARCH_QEMU=y
+CONFIG_TARGET_QEMU_ARM_SBSA=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="bootflow scan"
+CONFIG_EFI_PARTITION=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_EFI_MEDIA=y
+CONFIG_FS_FAT=y
+CONFIG_EFI_VARIABLE_NO_STORE=y
+CONFIG_BLOBLIST_ALLOC=y
+CONFIG_BLOBLIST_SIZE_RELOC=0x20000
diff --git a/configs/rpi_4_acpi_defconfig b/configs/rpi_4_acpi_defconfig
new file mode 100644
index 0000000..b32dfc1
--- /dev/null
+++ b/configs/rpi_4_acpi_defconfig
@@ -0,0 +1,10 @@
+#include <configs/rpi_4_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_BCM283X=y
+CONFIG_TARGET_RPI_4=y
+CONFIG_BLOBLIST_ALLOC=y
+CONFIG_OF_BOARD=y
+CONFIG_ACPI=y
+CONFIG_GENERATE_ACPI_TABLE=y
+
diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index 511645c..c350892 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -62,6 +62,7 @@
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_PROMPT="StarFive # "
+CONFIG_CMD_ERASEENV=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_EEPROM_SIZE=512
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
diff --git a/configs/th1520_lpi4a_defconfig b/configs/th1520_lpi4a_defconfig
index a57cedb..3b6ff62 100644
--- a/configs/th1520_lpi4a_defconfig
+++ b/configs/th1520_lpi4a_defconfig
@@ -4,6 +4,7 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
+CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="th1520-lichee-pi-4a"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x80200000
@@ -50,6 +51,7 @@
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNLZ4 is not set
# CONFIG_CMD_UNZIP is not set
+CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_ITEST is not set
@@ -61,7 +63,7 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_NO_NET=y
# CONFIG_BLOCK_CACHE is not set
-# CONFIG_GPIO is not set
+CONFIG_DWAPB_GPIO=y
# CONFIG_I2C is not set
# CONFIG_INPUT is not set
# CONFIG_DM_MMC is not set
diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig
index 3bb8559..dd1a45b 100644
--- a/configs/turris_omnia_defconfig
+++ b/configs/turris_omnia_defconfig
@@ -90,7 +90,7 @@
CONFIG_NETCONSOLE=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_AHCI_PCI=y
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_DM_PCA953X=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_MV=y
diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig
index 3983b20..7333413 100644
--- a/configs/xilinx_mbv32_defconfig
+++ b/configs/xilinx_mbv32_defconfig
@@ -2,17 +2,17 @@
CONFIG_SYS_MALLOC_LEN=0xe00000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x21200000
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81200000
CONFIG_ENV_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32"
-CONFIG_SPL_STACK=0x20200000
-CONFIG_SPL_BSS_START_ADDR=0x24000000
+CONFIG_SPL_STACK=0x80200000
+CONFIG_SPL_BSS_START_ADDR=0x84000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
-CONFIG_SYS_LOAD_ADDR=0x20200000
+CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_SPL_SIZE_LIMIT=0x40000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0x40600000
-CONFIG_DEBUG_UART_CLOCK=1000000
+CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_SYS_CLK_FREQ=100000000
CONFIG_BOOT_SCRIPT_OFFSET=0x0
CONFIG_DEBUG_UART=y
@@ -20,7 +20,7 @@
# CONFIG_SPL_SMP is not set
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x20200000
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
diff --git a/disk/part_efi.c b/disk/part_efi.c
index 7f04c6e..bdcfcba 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -216,7 +216,7 @@
return 0;
}
-void part_print_efi(struct blk_desc *desc)
+static void __maybe_unused part_print_efi(struct blk_desc *desc)
{
ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, desc->blksz);
gpt_entry *gpt_pte = NULL;
@@ -258,8 +258,8 @@
return;
}
-int part_get_info_efi(struct blk_desc *desc, int part,
- struct disk_partition *info)
+static int __maybe_unused part_get_info_efi(struct blk_desc *desc, int part,
+ struct disk_partition *info)
{
ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, desc->blksz);
gpt_entry *gpt_pte = NULL;
diff --git a/doc/api/fs.rst b/doc/api/fs.rst
new file mode 100644
index 0000000..38c8b0d
--- /dev/null
+++ b/doc/api/fs.rst
@@ -0,0 +1,7 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+File system API
+===============
+
+.. kernel-doc:: include/fs.h
+ :internal:
diff --git a/doc/api/index.rst b/doc/api/index.rst
index 9f7f23f..a108718 100644
--- a/doc/api/index.rst
+++ b/doc/api/index.rst
@@ -12,6 +12,7 @@
dm
efi
event
+ fs
getopt
interrupt
led
diff --git a/doc/board/emcraft/imx8mp-navqp.rst b/doc/board/emcraft/imx8mp-navqp.rst
new file mode 100644
index 0000000..89d8f95
--- /dev/null
+++ b/doc/board/emcraft/imx8mp-navqp.rst
@@ -0,0 +1,65 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+.. sectionauthor:: Gilles Talis <gilles.talis@gmail.com>
+
+i.MX8M Plus NavQ+ Board
+=======================
+
+U-Boot for the EmCraft Systems i.MX8M Plus NavQ+ board
+
+Quick Start
+-----------
+
+- Build the ARM trusted firmware binary
+- Get the DDR firmware
+- Build U-Boot
+- Flash to eMMC
+- Boot
+
+Get and Build the ARM Trusted Firmware (Trusted Firmware A)
+-----------------------------------------------------------
+
+.. code-block:: bash
+
+ $ echo "Downloading and building TF-A..."
+ $ git clone -b lts-v2.10 https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
+ $ cd trusted-firmware-a
+
+Then build ATF (TF-A):
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-linux-gnu-
+ $ make PLAT=imx8mp bl31
+ $ cp build/imx8mp/release/bl31.bin ../
+
+Get the DDR Firmware
+--------------------
+
+.. code-block:: bash
+
+ $ cd ..
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.23.bin
+ $ chmod +x firmware-imx-8.23.bin
+ $ ./firmware-imx-8.23.bin
+ $ cp firmware-imx-8.23/firmware/ddr/synopsys/lpddr4*_202006.bin ./
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-linux-gnu-
+ $ make imx8mp_navqp_defconfig
+ $ make
+
+Burn the flash.bin to the MicroSD card at offset 32KB:
+
+.. code-block:: bash
+
+ $ sudo dd if=flash.bin of=/dev/sd[x] bs=1K seek=32 conv=notrunc; sync
+
+Boot
+----
+
+Set Boot switch to SD boot
+Use /dev/ttyUSB0 for U-Boot console
diff --git a/doc/board/emcraft/index.rst b/doc/board/emcraft/index.rst
new file mode 100644
index 0000000..564552c
--- /dev/null
+++ b/doc/board/emcraft/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Emcraft
+=======
+
+.. toctree::
+ :maxdepth: 2
+
+ imx8mp-navqp
diff --git a/doc/board/emulation/index.rst b/doc/board/emulation/index.rst
index 98a0b26..f890816 100644
--- a/doc/board/emulation/index.rst
+++ b/doc/board/emulation/index.rst
@@ -8,10 +8,14 @@
acpi
blkdev
- ../../usage/semihosting
qemu-arm
qemu-mips
qemu-ppce500
qemu-riscv
+ qemu-sbsa
qemu-x86
qemu-xtensa
+
+Also see
+
+* :doc:`../../usage/semihosting`
diff --git a/doc/board/emulation/qemu-sbsa.rst b/doc/board/emulation/qemu-sbsa.rst
new file mode 100644
index 0000000..fe1dc32
--- /dev/null
+++ b/doc/board/emulation/qemu-sbsa.rst
@@ -0,0 +1,98 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2024, Patrick Rudolph <patrick.rudolph@9elements.com>
+
+QEMU ARM SBSA
+=============
+
+QEMU for ARM supports Arm Server Base System Architecture Reference board,
+short 'sbsa-ref' that utilizes ACPI over FDT. This document describes how to run
+U-Boot under it. Only AArch64 is supported.
+
+The 'sbsa' platform provides the following as the basic functionality:
+
+ - A freely configurable amount of CPU cores
+ - U-Boot loaded and executing in the emulated flash at address 0x10000000
+ - No device tree blob
+ - A freely configurable amount of RAM
+ - A PL011 serial port
+ - An ARMv7/ARMv8 architected timer
+ - PSCI for rebooting the system
+ - A generic ECAM-based PCI host controller
+
+Additionally, a number of optional peripherals can be added to the PCI bus.
+
+Compile ARM Trusted Firmware (ATF)
+----------------------------------
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+Get ATF from: https://github.com/ARM-software/arm-trusted-firmware
+
+.. code-block:: bash
+
+ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git tfa
+ cd tfa
+ make CROSS_COMPILE=aarch64-linux-gnu- all fip \
+ ARM_LINUX_KERNEL_AS_BL33=1 DEBUG=1 PLAT=qemu_sbsa
+
+Copy the resulting FIP and BL1 binary
+
+.. code-block:: bash
+
+ cp build/qemu_sbsa/debug/fip.bin ../
+ cp build/qemu_sbsa/debug/bl1.bin ../
+
+Building U-Boot
+---------------
+Set the CROSS_COMPILE environment variable as usual, and run:
+
+.. code-block:: bash
+
+ make qemu-arm-sbsa_defconfig
+ make
+
+Running U-Boot
+--------------
+The minimal QEMU command line to get U-Boot up and running is:
+
+.. code-block:: bash
+
+ qemu-system-aarch64 -machine sbsa-ref -nographic -cpu cortex-a57 \
+ -pflash secure-world.rom \
+ -pflash unsecure-world.rom
+
+Note that for some odd reason qemu-system-aarch64 needs to be explicitly
+told to use a 64-bit CPU or it will boot in 32-bit mode. The -nographic argument
+ensures that output appears on the terminal. Use Ctrl-A X to quit.
+
+Booting distros
+---------------
+
+It is possible to install and boot a standard Linux distribution using
+sbsa by setting up a root disk::
+
+.. code-block:: bash
+
+ qemu-img create root.img 20G
+
+then using the installer to install. For example, with Debian 12::
+
+.. code-block:: bash
+
+ qemu-system-aarch64 \
+ -machine sbsa-ref -cpu cortex-a57 -m 4G -smp 4 \
+ -pflash secure-world.rom \
+ -pflash unsecure-world.rom \
+ -device virtio-rng-pci \
+ -device usb-kbd -device usb-tablet \
+ -cdrom debian-12.0.0-arm64-netinst.iso \
+ -hda root.img
+
+Debug UART
+----------
+
+The debug UART on the ARM sbsa board uses these settings::
+
+ CONFIG_DEBUG_UART=y
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 3fb7c84..ca5246e 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -24,6 +24,7 @@
cloos/index
congatec/index
coreboot/index
+ emcraft/index
emulation/index
gateworks/index
google/index
diff --git a/doc/board/siemens/iot2050.rst b/doc/board/siemens/iot2050.rst
index ee3c5c9..37b23f6 100644
--- a/doc/board/siemens/iot2050.rst
+++ b/doc/board/siemens/iot2050.rst
@@ -8,7 +8,9 @@
AM6528 GP (Basic variant) or the AM6548 HS (Advanced variant). The Advanced
variant is prepared for secure boot. M.2 Variant also uses the AM6548 HS.
Instead of a MiniPCI connector, it comes with two M.2 connectors and can
-support 5G/WIFI/BT applications or connect an SSD.
+support 5G/WIFI/BT applications or connect an SSD. Compared with the AM6548
+Advanced variant, SM variant removes the Arduino interface, and adds a new
+ASIC for communicating with the PLC 1200 signal modules.
The IOT2050 starts only from OSPI. It loads a Siemens-provided bootloader
called SE-Boot for the MCU domain (R5F cores), then hands over to ATF and
@@ -29,6 +31,9 @@
- seboot_pg1.bin
- seboot_pg2.bin
+Note that SE-Boot D/V01.04.01.02 or greater is required, otherwise the DDR size
+will not be picked up correctly by U-Boot.
+
When using the watchdog, a related firmware for the R5 core(s) is needed, e.g.
https://github.com/siemens/k3-rti-wdt. The name and location of the image is
configured via CONFIG_WDT_K3_RTI_FW_FILE.
diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst
index c3513f0..5d01f48 100644
--- a/doc/board/ti/k3.rst
+++ b/doc/board/ti/k3.rst
@@ -32,19 +32,22 @@
am62ax_sk
am62x_sk
- ../beagle/am62x_beagleplay
- ../phytec/phycore-am62x
- ../toradex/verdin-am62
am62px_sk
am64x_evm
am65x_evm
j7200_evm
- ../beagle/j721e_beagleboneai64
j721e_evm
j721s2_evm
j722s_evm
j784s4_evm
+K3 SoC based boards in other sections
+
+* :doc:`../beagle/am62x_beagleplay`
+* :doc:`../beagle/j721e_beagleboneai64`
+* :doc:`../phytec/phycore-am62x`
+* :doc:`../toradex/verdin-am62`
+
Boot Flow Overview
------------------
diff --git a/doc/develop/driver-model/virtio.rst b/doc/develop/driver-model/virtio.rst
index 8ac9c94..31b94d0 100644
--- a/doc/develop/driver-model/virtio.rst
+++ b/doc/develop/driver-model/virtio.rst
@@ -34,6 +34,7 @@
- qemu_arm_defconfig
- qemu_arm64_defconfig
+ - qemu-arm-sbsa_defconfig
- qemu-riscv32_defconfig
- qemu-riscv64_defconfig
- qemu-x86_defconfig
diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst
index 9340e9c..faec644 100644
--- a/doc/develop/release_cycle.rst
+++ b/doc/develop/release_cycle.rst
@@ -51,10 +51,9 @@
Current Status
--------------
-* U-Boot v2024.10 was released on Mon 07 October 2024.
+* U-Boot v2025.01-rc1 was released on Mon 28 October 2024.
-* The Merge Window for the next release (v2025.01) is **open** until the -rc1
- release on Mon 28 October 2024.
+* The Merge Window for the next release (v2025.01) is **closed**.
* The next branch is now **closed**.
@@ -66,9 +65,9 @@
.. The following commented out dates are for when release candidates are
planned to be tagged.
-.. For the next scheduled release, release candidates were made on::
+For the next scheduled release, release candidates were made on::
-.. * U-Boot v2025.01-rc1 was released on Mon 28 October 2024.
+* U-Boot v2025.01-rc1 was released on Mon 28 October 2024.
.. * U-Boot v2025.01-rc2 was released on Mon 11 November 2024.
diff --git a/doc/sphinx/requirements.txt b/doc/sphinx/requirements.txt
index 40dde59..13e0327 100644
--- a/doc/sphinx/requirements.txt
+++ b/doc/sphinx/requirements.txt
@@ -1,25 +1,26 @@
-alabaster==0.7.16
-Babel==2.15.0
-certifi==2024.7.4
-charset-normalizer==3.3.2
-docutils==0.20.1
-idna==3.7
+alabaster==1.0.0
+babel==2.16.0
+certifi==2024.8.30
+charset-normalizer==3.4.0
+docutils==0.21.2
+idna==3.10
imagesize==1.4.1
Jinja2==3.1.4
-MarkupSafe==2.1.5
+MarkupSafe==3.0.2
packaging==24.1
+pip==24.2
Pygments==2.18.0
requests==2.32.3
six==1.16.0
snowballstemmer==2.2.0
-Sphinx==7.3.7
-sphinx-prompt==1.8.0
-sphinx-rtd-theme==2.0.0
-sphinxcontrib-applehelp==1.0.8
-sphinxcontrib-devhelp==1.0.6
-sphinxcontrib-htmlhelp==2.0.5
+Sphinx==8.1.3
+sphinx-prompt==1.9.0
+sphinx-rtd-theme==3.0.1
+sphinxcontrib-applehelp==2.0.0
+sphinxcontrib-devhelp==2.0.0
+sphinxcontrib-htmlhelp==2.1.0
sphinxcontrib-jquery==4.1
sphinxcontrib-jsmath==1.0.1
-sphinxcontrib-qthelp==1.0.7
-sphinxcontrib-serializinghtml==1.1.10
-urllib3==2.2.2
+sphinxcontrib-qthelp==2.0.0
+sphinxcontrib-serializinghtml==2.0.0
+urllib3==2.2.3
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 6cca561..4fbb63a 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -78,14 +78,16 @@
Enable this driver to support Sata devices through
Mediatek AHCI controller (e.g. MT7622).
-config AHCI_MVEBU
- bool "Marvell EBU AHCI SATA support"
- depends on ARCH_MVEBU || ARCH_OCTEON
+config AHCI_GENERIC
+ bool "Generic AHCI SATA support"
+ depends on OF_CONTROL
select SCSI_AHCI
select SCSI
help
- This option enables support for the Marvell EBU SoC's
- onboard AHCI SATA.
+ This option enables support for generic onboard AHCI SATA controller
+ that do not need platform specific quirks, like emulated devices,
+ Marvell EBU SoC's onboard AHCI SATA controllers or Cavium's Octeon
+ 7130 AHCI controllers.
If unsure, say N.
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index ee10c44..69fa9b7 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -14,6 +14,6 @@
obj-$(CONFIG_SATA_CEVA) += sata_ceva.o
obj-$(CONFIG_SATA_MV) += sata_mv.o
obj-$(CONFIG_SATA_SIL) += sata_sil.o
-obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o
+obj-$(CONFIG_AHCI_GENERIC) += ahci_generic.o
obj-$(CONFIG_SUNXI_AHCI) += ahci_sunxi.o
obj-$(CONFIG_MTK_AHCI) += mtk_ahci.o
diff --git a/drivers/ata/ahci_mvebu.c b/drivers/ata/ahci_generic.c
similarity index 71%
rename from drivers/ata/ahci_mvebu.c
rename to drivers/ata/ahci_generic.c
index f6e2d6b..6e5a6cb 100644
--- a/drivers/ata/ahci_mvebu.c
+++ b/drivers/ata/ahci_generic.c
@@ -16,7 +16,7 @@
return 0;
}
-static int mvebu_ahci_bind(struct udevice *dev)
+static int generic_ahci_bind(struct udevice *dev)
{
struct udevice *scsi_dev;
int ret;
@@ -30,7 +30,7 @@
return 0;
}
-static int mvebu_ahci_probe(struct udevice *dev)
+static int generic_ahci_probe(struct udevice *dev)
{
/*
* Board specific SATA / AHCI enable code, e.g. enable the
@@ -43,18 +43,19 @@
return 0;
}
-static const struct udevice_id mvebu_ahci_ids[] = {
+static const struct udevice_id generic_ahci_ids[] = {
{ .compatible = "marvell,armada-380-ahci" },
{ .compatible = "marvell,armada-3700-ahci" },
{ .compatible = "marvell,armada-8k-ahci" },
{ .compatible = "cavium,octeon-7130-ahci" },
+ { .compatible = "generic-ahci" },
{ }
};
-U_BOOT_DRIVER(ahci_mvebu_drv) = {
- .name = "ahci_mvebu",
+U_BOOT_DRIVER(ahci_generic_drv) = {
+ .name = "ahci_generic",
.id = UCLASS_AHCI,
- .of_match = mvebu_ahci_ids,
- .bind = mvebu_ahci_bind,
- .probe = mvebu_ahci_probe,
+ .of_match = generic_ahci_ids,
+ .bind = generic_ahci_bind,
+ .probe = generic_ahci_probe,
};
diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig
index b702415..62072e10 100644
--- a/drivers/clk/microchip/Kconfig
+++ b/drivers/clk/microchip/Kconfig
@@ -1,5 +1,7 @@
config CLK_MPFS
bool "Clock support for Microchip PolarFire SoC"
depends on CLK && CLK_CCF
+ depends on SYSCON
+ depends on REGMAP
help
This enables support clock driver for Microchip PolarFire SoC platform.
diff --git a/drivers/clk/microchip/mpfs_clk.c b/drivers/clk/microchip/mpfs_clk.c
index 0a82777..2c6694f 100644
--- a/drivers/clk/microchip/mpfs_clk.c
+++ b/drivers/clk/microchip/mpfs_clk.c
@@ -9,25 +9,39 @@
#include <log.h>
#include <dm/device.h>
#include <dm/devres.h>
+#include <dm/ofnode.h>
#include <dm/uclass.h>
+#include <regmap.h>
+#include <syscon.h>
#include <dt-bindings/clock/microchip-mpfs-clock.h>
#include <linux/err.h>
#include "mpfs_clk.h"
-static int mpfs_clk_probe(struct udevice *dev)
+static int mpfs_clk_syscon_probe(struct udevice *dev, void __iomem **msspll_base,
+ struct regmap **regmap)
{
- struct clk *parent_clk = dev_get_priv(dev);
- struct clk clk_msspll = { .id = CLK_MSSPLL };
- void __iomem *base;
- void __iomem *msspll_base;
- int ret;
+ ofnode node;
- base = dev_read_addr_index_ptr(dev, 0);
- if (!base)
- return -EINVAL;
+ node = ofnode_by_compatible(ofnode_null(), "microchip,mpfs-mss-top-sysreg");
+ if (!ofnode_valid(node))
+ return -ENODEV;
- ret = clk_get_by_index(dev, 0, parent_clk);
+ *regmap = syscon_node_to_regmap(node);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ *msspll_base = dev_read_addr_index_ptr(dev, 0);
+
+ return 0;
+}
+
+static int mpfs_clk_old_format_probe(struct udevice *dev, void __iomem **msspll_base,
+ struct regmap **regmap)
+{
+ int ret;
+
+ ret = regmap_init_mem_index(dev_ofnode(dev), regmap, 0);
if (ret)
return ret;
@@ -40,7 +54,30 @@
* Otherwise, skip registering it & pass the reference clock directly
* to the cfg clock registration function.
*/
- msspll_base = dev_read_addr_index_ptr(dev, 1);
+ *msspll_base = dev_read_addr_index_ptr(dev, 1);
+
+ return 0;
+}
+
+static int mpfs_clk_probe(struct udevice *dev)
+{
+ struct clk *parent_clk = dev_get_priv(dev);
+ struct clk clk_msspll = { .id = CLK_MSSPLL };
+ struct regmap *regmap;
+ void __iomem *msspll_base;
+ int ret;
+
+ ret = clk_get_by_index(dev, 0, parent_clk);
+ if (ret)
+ return ret;
+
+ ret = mpfs_clk_syscon_probe(dev, &msspll_base, ®map);
+ if (ret) {
+ ret = mpfs_clk_old_format_probe(dev, &msspll_base, ®map);
+ if (ret)
+ return ret;
+ }
+
if (msspll_base) {
ret = mpfs_clk_register_msspll(msspll_base, parent_clk);
if (ret)
@@ -50,11 +87,11 @@
parent_clk = &clk_msspll;
}
- ret = mpfs_clk_register_cfgs(base, parent_clk);
+ ret = mpfs_clk_register_cfgs(parent_clk, regmap);
if (ret)
return ret;
- ret = mpfs_clk_register_periphs(base, dev);
+ ret = mpfs_clk_register_periphs(dev, regmap);
return ret;
}
diff --git a/drivers/clk/microchip/mpfs_clk.h b/drivers/clk/microchip/mpfs_clk.h
index 72288cc..b8ad3ea 100644
--- a/drivers/clk/microchip/mpfs_clk.h
+++ b/drivers/clk/microchip/mpfs_clk.h
@@ -7,6 +7,7 @@
#define __MICROCHIP_MPFS_CLK_H
#include <linux/clk-provider.h>
+#include <regmap.h>
/**
* mpfs_clk_register_cfgs() - register configuration clocks
*
@@ -14,7 +15,7 @@
* @parent: a pointer to parent clock.
* Return: zero on success, or a negative error code.
*/
-int mpfs_clk_register_cfgs(void __iomem *base, struct clk *parent);
+int mpfs_clk_register_cfgs(struct clk *parent, struct regmap *regmap);
/**
* mpfs_clk_register_msspll() - register the mss pll
*
@@ -30,7 +31,7 @@
* @dev: udevice representing the clock controller.
* Return: zero on success, or a negative error code.
*/
-int mpfs_clk_register_periphs(void __iomem *base, struct udevice *dev);
+int mpfs_clk_register_periphs(struct udevice *dev, struct regmap *regmap);
/**
* divider_get_val() - get the clock divider value
*
diff --git a/drivers/clk/microchip/mpfs_clk_cfg.c b/drivers/clk/microchip/mpfs_clk_cfg.c
index 5e8fb99..7da1fc7 100644
--- a/drivers/clk/microchip/mpfs_clk_cfg.c
+++ b/drivers/clk/microchip/mpfs_clk_cfg.c
@@ -9,6 +9,7 @@
#include <dm/device.h>
#include <dm/devres.h>
#include <dm/uclass.h>
+#include <regmap.h>
#include <dt-bindings/clock/microchip-mpfs-clock.h>
#include <linux/err.h>
@@ -57,7 +58,7 @@
*/
struct mpfs_cfg_hw_clock {
struct mpfs_cfg_clock cfg;
- void __iomem *sys_base;
+ struct regmap *regmap;
u32 prate;
struct clk hw;
};
@@ -68,11 +69,11 @@
{
struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
- void __iomem *base_addr = cfg_hw->sys_base;
unsigned long rate;
u32 val;
- val = readl(base_addr + REG_CLOCK_CONFIG_CR) >> cfg->shift;
+ regmap_read(cfg_hw->regmap, REG_CLOCK_CONFIG_CR, &val);
+ val >>= cfg->shift;
val &= clk_div_mask(cfg->width);
rate = cfg_hw->prate / (1u << val);
hw->rate = rate;
@@ -84,7 +85,6 @@
{
struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
- void __iomem *base_addr = cfg_hw->sys_base;
u32 val;
int divider_setting;
@@ -93,10 +93,10 @@
if (divider_setting < 0)
return divider_setting;
- val = readl(base_addr + REG_CLOCK_CONFIG_CR);
+ regmap_read(cfg_hw->regmap, REG_CLOCK_CONFIG_CR, &val);
val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift);
val |= divider_setting << cfg->shift;
- writel(val, base_addr + REG_CLOCK_CONFIG_CR);
+ regmap_write(cfg_hw->regmap, REG_CLOCK_CONFIG_CR, val);
return clk_get_rate(hw);
}
@@ -116,7 +116,7 @@
CLK_CFG(CLK_AHB, "clk_ahb", 4, 2, mpfs_div_ahb_table, 0),
};
-int mpfs_clk_register_cfgs(void __iomem *base, struct clk *parent)
+int mpfs_clk_register_cfgs(struct clk *parent, struct regmap *regmap)
{
int ret;
int i, id, num_clks;
@@ -126,7 +126,7 @@
num_clks = ARRAY_SIZE(mpfs_cfg_clks);
for (i = 0; i < num_clks; i++) {
hw = &mpfs_cfg_clks[i].hw;
- mpfs_cfg_clks[i].sys_base = base;
+ mpfs_cfg_clks[i].regmap = regmap;
mpfs_cfg_clks[i].prate = clk_get_rate(parent);
name = mpfs_cfg_clks[i].cfg.name;
ret = clk_register(hw, MPFS_CFG_CLOCK, name, parent->dev->name);
diff --git a/drivers/clk/microchip/mpfs_clk_periph.c b/drivers/clk/microchip/mpfs_clk_periph.c
index 41c6df4..b734f49 100644
--- a/drivers/clk/microchip/mpfs_clk_periph.c
+++ b/drivers/clk/microchip/mpfs_clk_periph.c
@@ -9,6 +9,7 @@
#include <dm/device.h>
#include <dm/devres.h>
#include <dm/uclass.h>
+#include <regmap.h>
#include <dt-bindings/clock/microchip-mpfs-clock.h>
#include <linux/err.h>
@@ -50,7 +51,7 @@
*/
struct mpfs_periph_hw_clock {
struct mpfs_periph_clock periph;
- void __iomem *sys_base;
+ struct regmap *regmap;
u32 prate;
struct clk hw;
};
@@ -61,17 +62,16 @@
{
struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
struct mpfs_periph_clock *periph = &periph_hw->periph;
- void __iomem *base_addr = periph_hw->sys_base;
- u32 reg, val;
+ u32 reg;
if (periph->flags != CLK_IS_CRITICAL) {
- reg = readl(base_addr + REG_SUBBLK_RESET_CR);
- val = reg & ~(1u << periph->shift);
- writel(val, base_addr + REG_SUBBLK_RESET_CR);
+ regmap_read(periph_hw->regmap, REG_SUBBLK_RESET_CR, ®);
+ reg &= ~(1u << periph->shift);
+ regmap_write(periph_hw->regmap, REG_SUBBLK_RESET_CR, reg);
- reg = readl(base_addr + REG_SUBBLK_CLOCK_CR);
- val = reg | (1u << periph->shift);
- writel(val, base_addr + REG_SUBBLK_CLOCK_CR);
+ regmap_read(periph_hw->regmap, REG_SUBBLK_CLOCK_CR, ®);
+ reg |= (1u << periph->shift);
+ regmap_write(periph_hw->regmap, REG_SUBBLK_CLOCK_CR, reg);
}
return 0;
@@ -81,17 +81,16 @@
{
struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
struct mpfs_periph_clock *periph = &periph_hw->periph;
- void __iomem *base_addr = periph_hw->sys_base;
- u32 reg, val;
+ u32 reg;
if (periph->flags != CLK_IS_CRITICAL) {
- reg = readl(base_addr + REG_SUBBLK_RESET_CR);
- val = reg | (1u << periph->shift);
- writel(val, base_addr + REG_SUBBLK_RESET_CR);
+ regmap_read(periph_hw->regmap, REG_SUBBLK_RESET_CR, ®);
+ reg |= (1u << periph->shift);
+ regmap_write(periph_hw->regmap, REG_SUBBLK_RESET_CR, reg);
- reg = readl(base_addr + REG_SUBBLK_CLOCK_CR);
- val = reg & ~(1u << periph->shift);
- writel(val, base_addr + REG_SUBBLK_CLOCK_CR);
+ regmap_read(periph_hw->regmap, REG_SUBBLK_CLOCK_CR, ®);
+ reg &= ~(1u << periph->shift);
+ regmap_write(periph_hw->regmap, REG_SUBBLK_CLOCK_CR, reg);
}
return 0;
@@ -159,7 +158,7 @@
CLK_PERIPH(CLK_CFM, "clk_periph_cfm", CLK_AHB, 29, 0),
};
-int mpfs_clk_register_periphs(void __iomem *base, struct udevice *dev)
+int mpfs_clk_register_periphs(struct udevice *dev, struct regmap *regmap)
{
int ret;
int i, id, num_clks;
@@ -172,7 +171,7 @@
clk_request(dev, &parent);
hw = &mpfs_periph_clks[i].hw;
- mpfs_periph_clks[i].sys_base = base;
+ mpfs_periph_clks[i].regmap = regmap;
mpfs_periph_clks[i].prate = clk_get_rate(&parent);
name = mpfs_periph_clks[i].periph.name;
ret = clk_register(hw, MPFS_PERIPH_CLOCK, name, parent.dev->name);
diff --git a/drivers/core/acpi.c b/drivers/core/acpi.c
index 9f78422..4763963 100644
--- a/drivers/core/acpi.c
+++ b/drivers/core/acpi.c
@@ -48,6 +48,7 @@
METHOD_FILL_SSDT,
METHOD_INJECT_DSDT,
METHOD_SETUP_NHLT,
+ METHOD_FILL_MADT,
};
/* Prototype for all methods */
@@ -282,6 +283,8 @@
switch (method) {
case METHOD_WRITE_TABLES:
return aops->write_tables;
+ case METHOD_FILL_MADT:
+ return aops->fill_madt;
case METHOD_FILL_SSDT:
return aops->fill_ssdt;
case METHOD_INJECT_DSDT:
@@ -328,6 +331,19 @@
return 0;
}
+int acpi_fill_madt_subtbl(struct acpi_ctx *ctx)
+{
+ int ret;
+
+ log_debug("Writing MADT table\n");
+ ret = acpi_recurse_method(ctx, dm_root(), METHOD_FILL_MADT, TYPE_NONE);
+ log_debug("Writing MADT finished, err=%d\n", ret);
+ if (ret)
+ return log_msg_ret("build", ret);
+
+ return ret;
+}
+
int acpi_fill_ssdt(struct acpi_ctx *ctx)
{
void *start = ctx->current;
diff --git a/drivers/core/of_access.c b/drivers/core/of_access.c
index d05be27..77acd76 100644
--- a/drivers/core/of_access.c
+++ b/drivers/core/of_access.c
@@ -490,17 +490,17 @@
{
const u8 *val;
- dm_warn("%s: %s: ", __func__, propname);
+ log_debug("%s: %s: ", __func__, propname);
if (!np)
return -EINVAL;
val = of_find_property_value_of_size(np, propname, sizeof(*outp));
if (IS_ERR(val)) {
- dm_warn("(not found)\n");
+ log_debug("(not found)\n");
return PTR_ERR(val);
}
*outp = *val;
- dm_warn("%#x (%d)\n", *outp, *outp);
+ log_debug("%#x (%d)\n", *outp, *outp);
return 0;
}
@@ -509,17 +509,17 @@
{
const __be16 *val;
- dm_warn("%s: %s: ", __func__, propname);
+ log_debug("%s: %s: ", __func__, propname);
if (!np)
return -EINVAL;
val = of_find_property_value_of_size(np, propname, sizeof(*outp));
if (IS_ERR(val)) {
- dm_warn("(not found)\n");
+ log_debug("(not found)\n");
return PTR_ERR(val);
}
*outp = be16_to_cpup(val);
- dm_warn("%#x (%d)\n", *outp, *outp);
+ log_debug("%#x (%d)\n", *outp, *outp);
return 0;
}
@@ -534,14 +534,14 @@
{
const __be32 *val;
- dm_warn("%s: %s: ", __func__, propname);
+ log_debug("%s: %s: ", __func__, propname);
val = of_find_property_value_of_size(np, propname,
sz * sizeof(*out_values));
if (IS_ERR(val))
return PTR_ERR(val);
- dm_warn("size %zd\n", sz);
+ log_debug("size %zd\n", sz);
while (sz--)
*out_values++ = be32_to_cpup(val++);
@@ -553,19 +553,19 @@
{
const __be32 *val;
- dm_warn("%s: %s: ", __func__, propname);
+ log_debug("%s: %s: ", __func__, propname);
if (!np)
return -EINVAL;
val = of_find_property_value_of_size(np, propname,
sizeof(*outp) * (index + 1));
if (IS_ERR(val)) {
- dm_warn("(not found)\n");
+ log_debug("(not found)\n");
return PTR_ERR(val);
}
*outp = be32_to_cpup(val + index);
- dm_warn("%#x (%d)\n", *outp, *outp);
+ log_debug("%#x (%d)\n", *outp, *outp);
return 0;
}
@@ -575,20 +575,20 @@
{
const __be64 *val;
- dm_warn("%s: %s: ", __func__, propname);
+ log_debug("%s: %s: ", __func__, propname);
if (!np)
return -EINVAL;
val = of_find_property_value_of_size(np, propname,
sizeof(*outp) * (index + 1));
if (IS_ERR(val)) {
- dm_warn("(not found)\n");
+ log_debug("(not found)\n");
return PTR_ERR(val);
}
*outp = be64_to_cpup(val + index);
- dm_warn("%#llx (%lld)\n", (unsigned long long)*outp,
- (unsigned long long)*outp);
+ log_debug("%#llx (%lld)\n", (unsigned long long)*outp,
+ (unsigned long long)*outp);
return 0;
}
@@ -621,7 +621,7 @@
l = strnlen(p, end - p) + 1;
if (p + l > end)
return -EILSEQ;
- dm_warn("comparing %s with %s\n", string, p);
+ log_debug("comparing %s with %s\n", string, p);
if (strcmp(string, p) == 0)
return i; /* Found it; return index */
}
@@ -826,8 +826,8 @@
strncpy(ap->stem, stem, stem_len);
ap->stem[stem_len] = 0;
list_add_tail(&ap->link, &aliases_lookup);
- dm_warn("adding DT alias:%s: stem=%s id=%i node=%s\n",
- ap->alias, ap->stem, ap->id, of_node_full_name(np));
+ log_debug("adding DT alias:%s: stem=%s id=%i node=%s\n",
+ ap->alias, ap->stem, ap->id, of_node_full_name(np));
}
int of_alias_scan(void)
diff --git a/drivers/core/of_addr.c b/drivers/core/of_addr.c
index 6c7b4c9..250dd17 100644
--- a/drivers/core/of_addr.c
+++ b/drivers/core/of_addr.c
@@ -27,7 +27,7 @@
#ifdef DEBUG
static void of_dump_addr(const char *s, const __be32 *addr, int na)
{
- dm_warn("%s", s);
+ pr_debug("%s", s);
while (na--)
pr_cont(" %08x", be32_to_cpu(*(addr++)));
pr_cont("\n");
@@ -66,9 +66,9 @@
s = of_read_number(range + na + pna, ns);
da = of_read_number(addr, na);
- dm_warn("default map, cp=%llx, s=%llx, da=%llx\n",
- (unsigned long long)cp, (unsigned long long)s,
- (unsigned long long)da);
+ log_debug("default map, cp=%llx, s=%llx, da=%llx\n",
+ (unsigned long long)cp, (unsigned long long)s,
+ (unsigned long long)da);
if (da < cp || da >= (cp + s))
return OF_BAD_ADDR;
@@ -200,11 +200,11 @@
if (ranges == NULL || rlen == 0) {
offset = of_read_number(addr, na);
memset(addr, 0, pna * 4);
- dm_warn("empty ranges; 1:1 translation\n");
+ log_debug("empty ranges; 1:1 translation\n");
goto finish;
}
- dm_warn("walking ranges...\n");
+ log_debug("walking ranges...\n");
/* Now walk through the ranges */
rlen /= 4;
@@ -222,7 +222,7 @@
finish:
of_dump_addr("parent translation for:", addr, pna);
- dm_warn("with offset: %llx\n", (unsigned long long)offset);
+ log_debug("with offset: %llx\n", (unsigned long long)offset);
/* Translate it into parent bus space */
return pbus->translate(addr, offset, pna);
@@ -247,7 +247,7 @@
int na, ns, pna, pns;
u64 result = OF_BAD_ADDR;
- dm_warn("** translation for device %s **\n", of_node_full_name(dev));
+ log_debug("** translation for device %s **\n", of_node_full_name(dev));
/* Increase refcount at current level */
(void)of_node_get(dev);
@@ -266,8 +266,8 @@
}
memcpy(addr, in_addr, na * 4);
- dm_warn("bus is %s (na=%d, ns=%d) on %s\n", bus->name, na, ns,
- of_node_full_name(parent));
+ log_debug("bus is %s (na=%d, ns=%d) on %s\n", bus->name, na, ns,
+ of_node_full_name(parent));
of_dump_addr("translating address:", addr, na);
/* Translate */
@@ -279,7 +279,7 @@
/* If root, we have finished */
if (parent == NULL) {
- dm_warn("reached root node\n");
+ log_debug("reached root node\n");
result = of_read_number(addr, na);
break;
}
@@ -293,8 +293,8 @@
break;
}
- dm_warn("parent bus is %s (na=%d, ns=%d) on %s\n", pbus->name,
- pna, pns, of_node_full_name(parent));
+ log_debug("parent bus is %s (na=%d, ns=%d) on %s\n", pbus->name,
+ pna, pns, of_node_full_name(parent));
/* Apply bus translation */
if (of_translate_one(dev, bus, pbus, addr, na, ns, pna, rprop))
diff --git a/drivers/core/of_extra.c b/drivers/core/of_extra.c
index bfc1e34..f49187d 100644
--- a/drivers/core/of_extra.c
+++ b/drivers/core/of_extra.c
@@ -58,7 +58,7 @@
const fdt_addr_t *cell;
int len;
- dm_warn("%s: %s: %s\n", __func__, ofnode_get_name(node), prop_name);
+ log_debug("%s: %s: %s\n", __func__, ofnode_get_name(node), prop_name);
cell = ofnode_get_property(node, prop_name, &len);
if (!cell || (len < sizeof(fdt_addr_t) * 2)) {
dm_warn("cell=%p, len=%d\n", cell, len);
@@ -67,8 +67,8 @@
*basep = fdt_addr_to_cpu(*cell);
*sizep = fdt_size_to_cpu(cell[1]);
- dm_warn("%s: base=%08lx, size=%lx\n", __func__, (ulong)*basep,
- (ulong)*sizep);
+ log_debug("%s: base=%08lx, size=%lx\n", __func__, (ulong)*basep,
+ (ulong)*sizep);
return 0;
}
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index 48ae8ce..950895e 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -315,7 +315,7 @@
int len;
assert(ofnode_valid(node));
- dm_warn("%s: %s: ", __func__, propname);
+ log_debug("%s: %s: ", __func__, propname);
if (ofnode_is_np(node))
return of_read_u8(ofnode_to_np(node), propname, outp);
@@ -323,11 +323,11 @@
cell = fdt_getprop(gd->fdt_blob, ofnode_to_offset(node), propname,
&len);
if (!cell || len < sizeof(*cell)) {
- dm_warn("(not found)\n");
+ log_debug("(not found)\n");
return -EINVAL;
}
*outp = *cell;
- dm_warn("%#x (%u)\n", *outp, *outp);
+ log_debug("%#x (%u)\n", *outp, *outp);
return 0;
}
@@ -346,7 +346,7 @@
int len;
assert(ofnode_valid(node));
- dm_warn("%s: %s: ", __func__, propname);
+ log_debug("%s: %s: ", __func__, propname);
if (ofnode_is_np(node))
return of_read_u16(ofnode_to_np(node), propname, outp);
@@ -354,11 +354,11 @@
cell = fdt_getprop(gd->fdt_blob, ofnode_to_offset(node), propname,
&len);
if (!cell || len < sizeof(*cell)) {
- dm_warn("(not found)\n");
+ log_debug("(not found)\n");
return -EINVAL;
}
*outp = be16_to_cpup(cell);
- dm_warn("%#x (%u)\n", *outp, *outp);
+ log_debug("%#x (%u)\n", *outp, *outp);
return 0;
}
@@ -391,7 +391,7 @@
int len;
assert(ofnode_valid(node));
- dm_warn("%s: %s: ", __func__, propname);
+ log_debug("%s: %s: ", __func__, propname);
if (ofnode_is_np(node))
return of_read_u32_index(ofnode_to_np(node), propname, index,
@@ -400,17 +400,17 @@
cell = fdt_getprop(ofnode_to_fdt(node), ofnode_to_offset(node),
propname, &len);
if (!cell) {
- dm_warn("(not found)\n");
+ log_debug("(not found)\n");
return -EINVAL;
}
if (len < (sizeof(int) * (index + 1))) {
- dm_warn("(not large enough)\n");
+ log_debug("(not large enough)\n");
return -EOVERFLOW;
}
*outp = fdt32_to_cpu(cell[index]);
- dm_warn("%#x (%u)\n", *outp, *outp);
+ log_debug("%#x (%u)\n", *outp, *outp);
return 0;
}
@@ -430,17 +430,17 @@
cell = fdt_getprop(ofnode_to_fdt(node), ofnode_to_offset(node),
propname, &len);
if (!cell) {
- dm_warn("(not found)\n");
+ log_debug("(not found)\n");
return -EINVAL;
}
if (len < (sizeof(u64) * (index + 1))) {
- dm_warn("(not large enough)\n");
+ log_debug("(not large enough)\n");
return -EOVERFLOW;
}
*outp = fdt64_to_cpu(cell[index]);
- dm_warn("%#llx (%llu)\n", *outp, *outp);
+ log_debug("%#llx (%llu)\n", *outp, *outp);
return 0;
}
@@ -468,7 +468,7 @@
int len;
assert(ofnode_valid(node));
- dm_warn("%s: %s: ", __func__, propname);
+ log_debug("%s: %s: ", __func__, propname);
if (ofnode_is_np(node))
return of_read_u64(ofnode_to_np(node), propname, outp);
@@ -476,12 +476,12 @@
cell = fdt_getprop(ofnode_to_fdt(node), ofnode_to_offset(node),
propname, &len);
if (!cell || len < sizeof(*cell)) {
- dm_warn("(not found)\n");
+ log_debug("(not found)\n");
return -EINVAL;
}
*outp = fdt64_to_cpu(cell[0]);
- dm_warn("%#llx (%llu)\n", (unsigned long long)*outp,
- (unsigned long long)*outp);
+ log_debug("%#llx (%llu)\n", (unsigned long long)*outp,
+ (unsigned long long)*outp);
return 0;
}
@@ -499,11 +499,11 @@
bool prop;
assert(ofnode_valid(node));
- dm_warn("%s: %s: ", __func__, propname);
+ log_debug("%s: %s: ", __func__, propname);
prop = ofnode_has_property(node, propname);
- dm_warn("%s\n", prop ? "true" : "false");
+ log_debug("%s\n", prop ? "true" : "false");
return prop ? true : false;
}
@@ -514,7 +514,7 @@
int len;
assert(ofnode_valid(node));
- dm_warn("%s: %s: ", __func__, propname);
+ log_debug("%s: %s: ", __func__, propname);
if (ofnode_is_np(node)) {
struct property *prop = of_find_property(
@@ -529,7 +529,7 @@
propname, &len);
}
if (!val) {
- dm_warn("<not found>\n");
+ log_debug("<not found>\n");
if (sizep)
*sizep = -FDT_ERR_NOTFOUND;
return NULL;
@@ -553,7 +553,7 @@
dm_warn("<invalid>\n");
return NULL;
}
- dm_warn("%s\n", str);
+ log_debug("%s\n", str);
return str;
}
@@ -573,7 +573,7 @@
ofnode subnode;
assert(ofnode_valid(node));
- dm_warn("%s: %s: ", __func__, subnode_name);
+ log_debug("%s: %s: ", __func__, subnode_name);
if (ofnode_is_np(node)) {
struct device_node *np = ofnode_to_np(node);
@@ -588,8 +588,8 @@
ofnode_to_offset(node), subnode_name);
subnode = noffset_to_ofnode(node, ooffset);
}
- dm_warn("%s\n", ofnode_valid(subnode) ?
- ofnode_get_name(subnode) : "<none>");
+ log_debug("%s\n", ofnode_valid(subnode) ?
+ ofnode_get_name(subnode) : "<none>");
return subnode;
}
@@ -598,7 +598,7 @@
u32 *out_values, size_t sz)
{
assert(ofnode_valid(node));
- dm_warn("%s: %s: ", __func__, propname);
+ log_debug("%s: %s: ", __func__, propname);
if (ofnode_is_np(node)) {
return of_read_u32_array(ofnode_to_np(node), propname,
@@ -1032,7 +1032,7 @@
if (!prop)
return ofnode_null();
- dm_warn("%s: node_path: %s\n", __func__, prop);
+ log_debug("%s: node_path: %s\n", __func__, prop);
return ofnode_path(prop);
}
@@ -1301,7 +1301,7 @@
int len;
int ret = -ENOENT;
- dm_warn("%s: %s: ", __func__, propname);
+ log_debug("%s: %s: ", __func__, propname);
/*
* If we follow the pci bus bindings strictly, we should check
@@ -1318,10 +1318,10 @@
int i;
for (i = 0; i < num; i++) {
- dm_warn("pci address #%d: %08lx %08lx %08lx\n", i,
- (ulong)fdt32_to_cpu(cell[0]),
- (ulong)fdt32_to_cpu(cell[1]),
- (ulong)fdt32_to_cpu(cell[2]));
+ log_debug("pci address #%d: %08lx %08lx %08lx\n", i,
+ (ulong)fdt32_to_cpu(cell[0]),
+ (ulong)fdt32_to_cpu(cell[1]),
+ (ulong)fdt32_to_cpu(cell[2]));
if ((fdt32_to_cpu(*cell) & type) == type) {
const unaligned_fdt64_t *ptr;
@@ -1348,7 +1348,7 @@
ret = -EINVAL;
fail:
- dm_warn("(not found)\n");
+ log_debug("(not found)\n");
return ret;
}
@@ -1632,7 +1632,7 @@
{
assert(ofnode_valid(node));
- dm_warn("%s: %s = %s", __func__, propname, value);
+ log_debug("%s: %s = %s", __func__, propname, value);
return ofnode_write_prop(node, propname, value, strlen(value) + 1,
false);
diff --git a/drivers/cpu/Kconfig b/drivers/cpu/Kconfig
index 5c06cd9..4cc3679 100644
--- a/drivers/cpu/Kconfig
+++ b/drivers/cpu/Kconfig
@@ -26,6 +26,13 @@
help
Support CPU cores for RISC-V architecture.
+config CPU_ARMV8
+ bool "Enable generic ARMv8 CPU driver"
+ depends on CPU && ARM64
+ select IRQ
+ help
+ Support CPU cores for armv8 architecture.
+
config CPU_MICROBLAZE
bool "Enable Microblaze CPU driver"
depends on CPU && MICROBLAZE
diff --git a/drivers/cpu/Makefile b/drivers/cpu/Makefile
index bc75d9b..eaf4947 100644
--- a/drivers/cpu/Makefile
+++ b/drivers/cpu/Makefile
@@ -6,10 +6,12 @@
obj-$(CONFIG_CPU) += cpu-uclass.o
+obj-$(CONFIG_ARCH_BCM283X) += bcm283x_cpu.o
obj-$(CONFIG_ARCH_BMIPS) += bmips_cpu.o
obj-$(CONFIG_ARCH_IMX8) += imx8_cpu.o
obj-$(CONFIG_ARCH_AT91) += at91_cpu.o
obj-$(CONFIG_ARCH_MEDIATEK) += mtk_cpu.o
+obj-$(CONFIG_CPU_ARMV8) += armv8_cpu.o
obj-$(CONFIG_CPU_IMX) += imx8_cpu.o
obj-$(CONFIG_CPU_MPC83XX) += mpc83xx_cpu.o
obj-$(CONFIG_CPU_RISCV) += riscv_cpu.o
diff --git a/drivers/cpu/armv8_cpu.c b/drivers/cpu/armv8_cpu.c
new file mode 100644
index 0000000..4eedfe5
--- /dev/null
+++ b/drivers/cpu/armv8_cpu.c
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 9elements GmbH
+ */
+#include <cpu.h>
+#include <dm.h>
+#include <irq.h>
+#include <acpi/acpigen.h>
+#include <asm/armv8/cpu.h>
+#include <asm/io.h>
+#include <dm/acpi.h>
+#include <linux/bitops.h>
+#include <linux/printk.h>
+#include <linux/sizes.h>
+
+static int armv8_cpu_get_desc(const struct udevice *dev, char *buf, int size)
+{
+ int cpuid;
+
+ cpuid = (read_midr() & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT;
+
+ snprintf(buf, size, "CPU MIDR %04x", cpuid);
+
+ return 0;
+}
+
+static int armv8_cpu_get_info(const struct udevice *dev,
+ struct cpu_info *info)
+{
+ info->cpu_freq = 0;
+ info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
+
+ return 0;
+}
+
+static int armv8_cpu_get_count(const struct udevice *dev)
+{
+ return uclass_id_count(UCLASS_CPU);
+}
+
+#ifdef CONFIG_ACPIGEN
+int armv8_cpu_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx)
+{
+ uint core_id = dev_seq(dev);
+
+ acpigen_write_processor_device(ctx, core_id);
+
+ return 0;
+}
+
+int armv8_cpu_fill_madt(const struct udevice *dev, struct acpi_ctx *ctx)
+{
+ struct acpi_madt_gicc *gicc;
+ struct cpu_plat *cpu_plat;
+ struct udevice *gic;
+ u64 gicc_gicv = 0;
+ u64 gicc_gich = 0;
+ u64 gicc_gicr_base = 0;
+ u64 gicc_phys_base = 0;
+ u32 gicc_perf_gsiv = 0;
+ u64 gicc_mpidr;
+ u32 gicc_vgic_maint_irq = 0;
+ int addr_index;
+ fdt_addr_t addr;
+ int ret;
+ struct irq req_irq;
+
+ cpu_plat = dev_get_parent_plat(dev);
+ if (!cpu_plat)
+ return 0;
+
+ ret = irq_get_interrupt_parent(dev, &gic);
+ if (ret) {
+ log_err("%s: Failed to find interrupt parent for %s\n",
+ __func__, dev->name);
+ return -ENODEV;
+ }
+
+ addr_index = 1;
+
+ if (device_is_compatible(gic, "arm,gic-v3")) {
+ addr = dev_read_addr_index(gic, addr_index++);
+ if (addr != FDT_ADDR_T_NONE)
+ gicc_gicr_base = addr;
+ }
+
+ addr = dev_read_addr_index(gic, addr_index++);
+ if (addr != FDT_ADDR_T_NONE)
+ gicc_phys_base = addr;
+
+ addr = dev_read_addr_index(gic, addr_index++);
+ if (addr != FDT_ADDR_T_NONE)
+ gicc_gich = addr;
+
+ addr = dev_read_addr_index(gic, addr_index++);
+ if (addr != FDT_ADDR_T_NONE)
+ gicc_gicv = addr;
+
+ ret = irq_get_by_index(gic, 0, &req_irq);
+ if (!ret)
+ gicc_vgic_maint_irq = req_irq.id;
+
+ gicc_mpidr = dev_read_u64_default(dev, "reg", 0);
+ if (!gicc_mpidr)
+ gicc_mpidr = dev_read_u32_default(dev, "reg", 0);
+
+ /*
+ * gicc_vgic_maint_irq and gicc_gicv are the same for every CPU
+ */
+ gicc = ctx->current;
+ acpi_write_madt_gicc(gicc,
+ dev_seq(dev),
+ gicc_perf_gsiv, /* FIXME: needs a PMU driver */
+ gicc_phys_base,
+ gicc_gicv,
+ gicc_gich,
+ gicc_vgic_maint_irq,
+ gicc_gicr_base,
+ gicc_mpidr,
+ 0); /* FIXME: Not defined in DT */
+
+ acpi_inc(ctx, gicc->length);
+
+ return 0;
+}
+
+struct acpi_ops armv8_cpu_acpi_ops = {
+ .fill_ssdt = armv8_cpu_fill_ssdt,
+ .fill_madt = armv8_cpu_fill_madt,
+};
+#endif
+
+static const struct cpu_ops cpu_ops = {
+ .get_count = armv8_cpu_get_count,
+ .get_desc = armv8_cpu_get_desc,
+ .get_info = armv8_cpu_get_info,
+};
+
+static const struct udevice_id cpu_ids[] = {
+ { .compatible = "arm,armv8" },
+ {}
+};
+
+U_BOOT_DRIVER(arm_cpu) = {
+ .name = "arm-cpu",
+ .id = UCLASS_CPU,
+ .of_match = cpu_ids,
+ .ops = &cpu_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+ ACPI_OPS_PTR(&armv8_cpu_acpi_ops)
+};
diff --git a/drivers/cpu/armv8_cpu.h b/drivers/cpu/armv8_cpu.h
new file mode 100644
index 0000000..48c705e
--- /dev/null
+++ b/drivers/cpu/armv8_cpu.h
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 9elements GmbH
+ */
+#include <dm/acpi.h>
+#include <dm/device.h>
+
+#ifndef _ARMV8_CPU_H_
+#define _ARMV8_CPU_H_
+
+/**
+ * armv8_cpu_fill_ssdt() - Fill the SSDT
+ * Parses the FDT and writes the SSDT nodes.
+ *
+ * @dev: cpu device to generate ACPI tables for
+ * @ctx: ACPI context pointer
+ * @return: 0 if OK, or a negative error code.
+ */
+int armv8_cpu_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx);
+
+/**
+ * armv8_cpu_fill_madt() - Fill the MADT
+ * Parses the FDT and writes the MADT subtables.
+ *
+ * @dev: cpu device to generate ACPI tables for
+ * @ctx: ACPI context pointer
+ * @return: 0 if OK, or a negative error code.
+ */
+int armv8_cpu_fill_madt(const struct udevice *dev, struct acpi_ctx *ctx);
+
+#endif
\ No newline at end of file
diff --git a/drivers/cpu/bcm283x_cpu.c b/drivers/cpu/bcm283x_cpu.c
new file mode 100644
index 0000000..59a7b14
--- /dev/null
+++ b/drivers/cpu/bcm283x_cpu.c
@@ -0,0 +1,214 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 9elements GmbH
+ */
+
+#include <cpu.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <fdt_support.h>
+#include <acpi/acpigen.h>
+#include <asm/armv8/cpu.h>
+#include <asm/cache.h>
+#include <asm/io.h>
+#include <asm/global_data.h>
+#include <asm/system.h>
+#include <asm-generic/sections.h>
+#include <linux/bitops.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include "armv8_cpu.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct bcm_plat {
+ u64 release_addr;
+};
+
+static int cpu_bcm_get_desc(const struct udevice *dev, char *buf, int size)
+{
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
+ const char *name;
+
+ if (size < 32)
+ return -ENOSPC;
+
+ if (device_is_compatible(dev, "arm,cortex-a53"))
+ name = "A53";
+ else if (device_is_compatible(dev, "arm,cortex-a72"))
+ name = "A72";
+ else
+ name = "?";
+
+ snprintf(buf, size, "Broadcom Cortex-%s at %u MHz\n",
+ name, plat->timebase_freq);
+
+ return 0;
+}
+
+static int cpu_bcm_get_info(const struct udevice *dev, struct cpu_info *info)
+{
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
+
+ info->cpu_freq = plat->timebase_freq * 1000;
+ info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
+
+ return 0;
+}
+
+static int cpu_bcm_get_count(const struct udevice *dev)
+{
+ return uclass_id_count(UCLASS_CPU);
+}
+
+static int cpu_bcm_get_vendor(const struct udevice *dev, char *buf, int size)
+{
+ snprintf(buf, size, "Broadcom");
+
+ return 0;
+}
+
+static int cpu_bcm_is_current(struct udevice *dev)
+{
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
+
+ if (plat->cpu_id == (read_mpidr() & 0xffff))
+ return 1;
+
+ return 0;
+}
+
+/**
+ * bcm_cpu_on - Releases the secondary CPU from it's spintable
+ *
+ * Write the CPU's spintable mailbox and let the CPU enter U-Boot.
+ *
+ * @dev: Device to start
+ * @return: zero on success or error code on failure.
+ */
+static int bcm_cpu_on(struct udevice *dev)
+{
+ struct bcm_plat *plat = dev_get_plat(dev);
+ ulong *start_address;
+
+ if (plat->release_addr == ~0ULL)
+ return -ENODATA;
+
+ start_address = map_physmem(plat->release_addr, sizeof(uintptr_t), MAP_NOCACHE);
+
+ /* Point secondary CPU to U-Boot entry */
+ *start_address = (uintptr_t)_start;
+
+ /* Make sure the other CPUs see the written start address */
+ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ flush_dcache_all();
+
+ /* Send an event to wake up the secondary CPU. */
+ asm("dsb ishst\n"
+ "sev");
+
+ unmap_physmem(start_address, MAP_NOCACHE);
+
+ return 0;
+}
+
+static const struct cpu_ops cpu_bcm_ops = {
+ .get_desc = cpu_bcm_get_desc,
+ .get_info = cpu_bcm_get_info,
+ .get_count = cpu_bcm_get_count,
+ .get_vendor = cpu_bcm_get_vendor,
+ .is_current = cpu_bcm_is_current,
+};
+
+static const struct udevice_id cpu_bcm_ids[] = {
+ { .compatible = "arm,cortex-a53" }, /* RPi 3 */
+ { .compatible = "arm,cortex-a72" }, /* RPi 4 */
+ { }
+};
+
+static int bcm_cpu_bind(struct udevice *dev)
+{
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
+
+ plat->cpu_id = dev_read_addr(dev);
+
+ return 0;
+}
+
+/**
+ * bcm_cpu_of_to_plat - Gather spin-table release address
+ *
+ * Read the spin-table release address to allow all seconary CPUs to enter
+ * U-Boot when necessary.
+ *
+ * @dev: Device to start
+ */
+static int bcm_cpu_of_to_plat(struct udevice *dev)
+{
+ struct bcm_plat *plat = dev_get_plat(dev);
+ const char *prop;
+
+ if (CONFIG_IS_ENABLED(ARMV8_MULTIENTRY)) {
+ plat->release_addr = ~0ULL;
+
+ prop = dev_read_string(dev, "enable-method");
+ if (!prop || strcmp(prop, "spin-table"))
+ return -ENODEV;
+
+ plat->release_addr = dev_read_u64_default(dev, "cpu-release-addr", ~0ULL);
+
+ if (plat->release_addr == ~0ULL)
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int bcm_cpu_probe(struct udevice *dev)
+{
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
+ struct clk clk;
+ int ret;
+
+ /* Get a clock if it exists */
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (!ret) {
+ ret = clk_enable(&clk);
+ if (ret && (ret != -ENOSYS || ret != -EOPNOTSUPP))
+ return ret;
+ ret = clk_get_rate(&clk);
+ if (IS_ERR_VALUE(ret))
+ return ret;
+ plat->timebase_freq = ret;
+ }
+
+ /*
+ * The armstub holds the secondary CPUs in a spinloop. When
+ * ARMV8_MULTIENTRY is enabled release the secondary CPUs and
+ * let them enter U-Boot as well.
+ */
+ if (CONFIG_IS_ENABLED(ARMV8_MULTIENTRY)) {
+ ret = bcm_cpu_on(dev);
+ if (ret)
+ return ret;
+ }
+
+ return ret;
+}
+
+struct acpi_ops bcm283x_cpu_acpi_ops = {
+ .fill_ssdt = armv8_cpu_fill_ssdt,
+ .fill_madt = armv8_cpu_fill_madt,
+};
+
+U_BOOT_DRIVER(cpu_bcm_drv) = {
+ .name = "bcm283x_cpu",
+ .id = UCLASS_CPU,
+ .of_match = cpu_bcm_ids,
+ .ops = &cpu_bcm_ops,
+ .probe = bcm_cpu_probe,
+ .bind = bcm_cpu_bind,
+ .of_to_plat = bcm_cpu_of_to_plat,
+ .plat_auto = sizeof(struct bcm_plat),
+ ACPI_OPS_PTR(&bcm283x_cpu_acpi_ops)
+};
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 1e57116..92a8597 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -157,6 +157,13 @@
is found in the AST2400, AST2500 and AST2600 BMC SoCs and
provides access to over 200 GPIOs on each chip.
+config ASPEED_SGPIO
+ bool "Aspeed SGPIO Driver"
+ help
+ Say yes here to support the Aspeed serial GPIO driver. The controller
+ is found in the AST2400, AST2500 and AST2600 BMC SoCs and
+ provides access to generate serial GPIO signal.
+
config ASPEED_G7_GPIO
bool "Aspeed G7 GPIO Driver"
help
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index fe81b6b..3f882c0 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -14,6 +14,7 @@
obj-$(CONFIG_ASPEED_GPIO) += gpio-aspeed.o
obj-$(CONFIG_ASPEED_G7_GPIO) += gpio-aspeed-g7.o
+obj-$(CONFIG_ASPEED_SGPIO) += gpio-aspeed-sgpio.o
obj-$(CONFIG_AT91_GPIO) += at91_gpio.o
obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o
obj-$(CONFIG_BCM6345_GPIO) += bcm6345_gpio.o
diff --git a/drivers/gpio/dwapb_gpio.c b/drivers/gpio/dwapb_gpio.c
index 7a6eae9..04639a4 100644
--- a/drivers/gpio/dwapb_gpio.c
+++ b/drivers/gpio/dwapb_gpio.c
@@ -177,7 +177,9 @@
plat->base = (void *)base;
plat->bank = bank;
- plat->pins = ofnode_read_u32_default(node, "snps,nr-gpios", 0);
+
+ if (ofnode_read_u32(node, "ngpios", &plat->pins))
+ plat->pins = ofnode_read_u32_default(node, "snps,nr-gpios", 0);
if (ofnode_read_string_index(node, "bank-name", 0,
&plat->name)) {
diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
new file mode 100644
index 0000000..4bbdec7
--- /dev/null
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -0,0 +1,310 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) ASPEED Technology Inc.
+ * Billy Tsai <billy_tsai@aspeedtech.com>
+ */
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#include <config.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <asm/io.h>
+#include <linux/bug.h>
+#include <linux/sizes.h>
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+
+#define ASPEED_SGPIO_CTRL 0x54
+
+#define ASPEED_SGPIO_CLK_DIV_MASK GENMASK(31, 16)
+#define ASPEED_SGPIO_ENABLE BIT(0)
+#define ASPEED_SGPIO_PINS_SHIFT 6
+
+struct aspeed_sgpio_priv {
+ void *base;
+ struct clk pclk;
+ const struct aspeed_sgpio_pdata *pdata;
+};
+
+struct aspeed_sgpio_pdata {
+ const u32 pin_mask;
+ const struct aspeed_sgpio_llops *llops;
+};
+
+struct aspeed_sgpio_bank {
+ u16 val_regs;
+ u16 rdata_reg;
+ u16 tolerance_regs;
+ const char names[4][3];
+};
+
+/*
+ * Note: The "value" register returns the input value when the GPIO is
+ * configured as an input.
+ *
+ * The "rdata" register returns the output value when the GPIO is
+ * configured as an output.
+ */
+static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = {
+ {
+ .val_regs = 0x0000,
+ .rdata_reg = 0x0070,
+ .tolerance_regs = 0x0018,
+ .names = { "A", "B", "C", "D" },
+ },
+ {
+ .val_regs = 0x001C,
+ .rdata_reg = 0x0074,
+ .tolerance_regs = 0x0034,
+ .names = { "E", "F", "G", "H" },
+ },
+ {
+ .val_regs = 0x0038,
+ .rdata_reg = 0x0078,
+ .tolerance_regs = 0x0050,
+ .names = { "I", "J", "K", "L" },
+ },
+ {
+ .val_regs = 0x0090,
+ .rdata_reg = 0x007C,
+ .tolerance_regs = 0x00A8,
+ .names = { "M", "N", "O", "P" },
+ },
+};
+
+enum aspeed_sgpio_reg {
+ reg_val,
+ reg_rdata,
+ reg_tolerance,
+};
+
+struct aspeed_sgpio_llops {
+ void (*reg_bit_set)(struct aspeed_sgpio_priv *gpio, unsigned int offset,
+ const enum aspeed_sgpio_reg reg, bool val);
+ bool (*reg_bit_get)(struct aspeed_sgpio_priv *gpio, unsigned int offset,
+ const enum aspeed_sgpio_reg reg);
+};
+
+#define GPIO_VAL_VALUE 0x00
+
+static void __iomem *bank_reg(struct aspeed_sgpio_priv *gpio,
+ const struct aspeed_sgpio_bank *bank,
+ const enum aspeed_sgpio_reg reg)
+{
+ switch (reg) {
+ case reg_val:
+ return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
+ case reg_rdata:
+ return gpio->base + bank->rdata_reg;
+ case reg_tolerance:
+ return gpio->base + bank->tolerance_regs;
+ default:
+ /* acturally if code runs to here, it's an error case */
+ BUG();
+ }
+}
+
+#define GPIO_BANK(x) ((x) >> 6)
+#define GPIO_OFFSET(x) ((x) & GENMASK(5, 0))
+#define GPIO_BIT(x) BIT(GPIO_OFFSET(x) >> 1)
+
+static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
+{
+ unsigned int bank;
+
+ bank = GPIO_BANK(offset);
+
+ WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
+ return &aspeed_sgpio_banks[bank];
+}
+
+static bool aspeed_sgpio_is_input(unsigned int offset)
+{
+ return !(offset % 2);
+}
+
+static int aspeed_sgpio_get_value(struct udevice *dev, unsigned int offset)
+{
+ struct aspeed_sgpio_priv *gpio = dev_get_priv(dev);
+ enum aspeed_sgpio_reg reg;
+
+ reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;
+
+ return gpio->pdata->llops->reg_bit_get(gpio, offset, reg);
+}
+
+static int aspeed_sgpio_set_value(struct udevice *dev, unsigned int offset,
+ int value)
+{
+ struct aspeed_sgpio_priv *gpio = dev_get_priv(dev);
+
+ if (aspeed_sgpio_is_input(offset))
+ return -EINVAL;
+
+ gpio->pdata->llops->reg_bit_set(gpio, offset, reg_val, value);
+
+ return 0;
+}
+
+static int aspeed_sgpio_direction_input(struct udevice *dev,
+ unsigned int offset)
+{
+ return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL;
+}
+
+static int aspeed_sgpio_set_flags(struct udevice *dev, unsigned int offset, ulong flags)
+{
+ int ret = -EOPNOTSUPP;
+
+ if (flags & GPIOD_IS_OUT) {
+ bool value = flags & GPIOD_IS_OUT_ACTIVE;
+
+ ret = aspeed_sgpio_set_value(dev, offset, value);
+ } else if (flags & GPIOD_IS_IN) {
+ ret = aspeed_sgpio_direction_input(dev, offset);
+ }
+ return ret;
+}
+
+static int aspeed_sgpio_get_function(struct udevice *dev, unsigned int offset)
+{
+ return aspeed_sgpio_is_input(offset) ? GPIOF_INPUT : GPIOF_OUTPUT;
+}
+
+static void aspeed_g4_reg_bit_set(struct aspeed_sgpio_priv *gpio, unsigned int offset,
+ const enum aspeed_sgpio_reg reg, bool val)
+{
+ const struct aspeed_sgpio_bank *bank = to_bank(offset);
+ void __iomem *addr = bank_reg(gpio, bank, reg);
+ u32 temp;
+
+ if (reg == reg_val)
+ /* Since this is an output, read the cached value from rdata, then update val. */
+ temp = readl(bank_reg(gpio, bank, reg_rdata));
+ else
+ temp = readl(addr);
+
+ if (val)
+ temp |= GPIO_BIT(offset);
+ else
+ temp &= ~GPIO_BIT(offset);
+
+ writel(temp, addr);
+}
+
+static bool aspeed_g4_reg_bit_get(struct aspeed_sgpio_priv *gpio, unsigned int offset,
+ const enum aspeed_sgpio_reg reg)
+{
+ const struct aspeed_sgpio_bank *bank = to_bank(offset);
+ void __iomem *addr = bank_reg(gpio, bank, reg);
+
+ return !!(readl(addr) & GPIO_BIT(offset));
+}
+
+static const struct aspeed_sgpio_llops aspeed_g4_llops = {
+ .reg_bit_set = aspeed_g4_reg_bit_set,
+ .reg_bit_get = aspeed_g4_reg_bit_get,
+};
+
+static const struct dm_gpio_ops aspeed_sgpio_ops = {
+ .get_value = aspeed_sgpio_get_value,
+ .set_value = aspeed_sgpio_set_value,
+ .get_function = aspeed_sgpio_get_function,
+ .set_flags = aspeed_sgpio_set_flags,
+};
+
+static int aspeed_sgpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct aspeed_sgpio_priv *priv = dev_get_priv(dev);
+ u32 sgpio_freq, sgpio_clk_div, nr_gpios, gpio_cnt_regval, pin_mask;
+ ulong apb_freq;
+ int ret;
+
+ priv->base = devfdt_get_addr_ptr(dev);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ priv->pdata = (const struct aspeed_sgpio_pdata *)dev_get_driver_data(dev);
+ if (!priv->pdata)
+ return -EINVAL;
+
+ pin_mask = priv->pdata->pin_mask;
+
+ ret = ofnode_read_u32(dev_ofnode(dev), "ngpios", &nr_gpios);
+ if (ret < 0) {
+ dev_err(dev, "Could not read ngpios property\n");
+ return -EINVAL;
+ } else if (nr_gpios % 8) {
+ dev_err(dev, "Number of GPIOs not multiple of 8: %d\n",
+ nr_gpios);
+ return -EINVAL;
+ }
+
+ ret = ofnode_read_u32(dev_ofnode(dev), "bus-frequency", &sgpio_freq);
+ if (ret < 0) {
+ dev_err(dev, "Could not read bus-frequency property\n");
+ return -EINVAL;
+ }
+
+ ret = clk_get_by_index(dev, 0, &priv->pclk);
+ if (ret < 0) {
+ dev_err(dev, "get clock failed\n");
+ return ret;
+ }
+
+ apb_freq = clk_get_rate(&priv->pclk);
+
+ /*
+ * From the datasheet,
+ * SGPIO period = 1/PCLK * 2 * (GPIO254[31:16] + 1)
+ * period = 2 * (GPIO254[31:16] + 1) / PCLK
+ * frequency = 1 / (2 * (GPIO254[31:16] + 1) / PCLK)
+ * frequency = PCLK / (2 * (GPIO254[31:16] + 1))
+ * frequency * 2 * (GPIO254[31:16] + 1) = PCLK
+ * GPIO254[31:16] = PCLK / (frequency * 2) - 1
+ */
+ if (sgpio_freq == 0)
+ return -EINVAL;
+
+ sgpio_clk_div = (apb_freq / (sgpio_freq * 2)) - 1;
+
+ if (sgpio_clk_div > (1 << 16) - 1)
+ return -EINVAL;
+
+ gpio_cnt_regval = ((nr_gpios / 8) << ASPEED_SGPIO_PINS_SHIFT) & pin_mask;
+ writel(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) | gpio_cnt_regval |
+ ASPEED_SGPIO_ENABLE, priv->base + ASPEED_SGPIO_CTRL);
+
+ uc_priv->bank_name = dev->name;
+ uc_priv->gpio_count = nr_gpios * 2;
+
+ return 0;
+}
+
+static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = {
+ .pin_mask = GENMASK(9, 6),
+ .llops = &aspeed_g4_llops,
+};
+
+static const struct aspeed_sgpio_pdata ast2600_sgpiom_pdata = {
+ .pin_mask = GENMASK(10, 6),
+ .llops = &aspeed_g4_llops,
+};
+
+static const struct udevice_id aspeed_sgpio_ids[] = {
+ { .compatible = "aspeed,ast2400-sgpio", .data = (ulong)&ast2400_sgpio_pdata, },
+ { .compatible = "aspeed,ast2500-sgpio", .data = (ulong)&ast2400_sgpio_pdata, },
+ { .compatible = "aspeed,ast2600-sgpiom", .data = (ulong)&ast2600_sgpiom_pdata, },
+};
+
+U_BOOT_DRIVER(sgpio_aspeed) = {
+ .name = "sgpio-aspeed",
+ .id = UCLASS_GPIO,
+ .of_match = aspeed_sgpio_ids,
+ .ops = &aspeed_sgpio_ops,
+ .probe = aspeed_sgpio_probe,
+ .priv_auto = sizeof(struct aspeed_sgpio_priv),
+};
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index d10edd2..7c40f17 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -39,7 +39,7 @@
config TI_AEMIF
tristate "Texas Instruments AEMIF driver"
- depends on ARCH_KEYSTONE
+ depends on ARCH_KEYSTONE || ARCH_DAVINCI
help
This driver is for the AEMIF module available in Texas Instruments
SoCs. AEMIF stands for Asynchronous External Memory Interface and
diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
index 1cabf8a..fdc83e4 100644
--- a/drivers/memory/Makefile
+++ b/drivers/memory/Makefile
@@ -3,5 +3,5 @@
obj-$(CONFIG_SANDBOX_MEMORY) += memory-sandbox.o
obj-$(CONFIG_STM32_FMC2_EBI) += stm32-fmc2-ebi.o
obj-$(CONFIG_ATMEL_EBI) += atmel_ebi.o
-obj-$(CONFIG_TI_AEMIF) += ti-aemif.o
+obj-$(CONFIG_TI_AEMIF) += ti-aemif.o ti-aemif-cs.o
obj-$(CONFIG_TI_GPMC) += ti-gpmc.o
diff --git a/drivers/memory/ti-aemif-cs.c b/drivers/memory/ti-aemif-cs.c
new file mode 100644
index 0000000..0fcfee6
--- /dev/null
+++ b/drivers/memory/ti-aemif-cs.c
@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * DaVinci / Keystone2 : AEMIF's chip select configuration
+ *
+ */
+#include <asm/io.h>
+#include <clk.h>
+#include <div64.h>
+#include <dm.h>
+#include "ti-aemif-cs.h"
+
+#define AEMIF_CONFIG(cs) (0x10 + ((cs) * 4))
+
+#define AEMIF_CFG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0)
+#define AEMIF_CFG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0)
+#define AEMIF_CFG_WR_SETUP(v) (((v) & 0x0f) << 26)
+#define AEMIF_CFG_WR_STROBE(v) (((v) & 0x3f) << 20)
+#define AEMIF_CFG_WR_HOLD(v) (((v) & 0x07) << 17)
+#define AEMIF_CFG_RD_SETUP(v) (((v) & 0x0f) << 13)
+#define AEMIF_CFG_RD_STROBE(v) (((v) & 0x3f) << 7)
+#define AEMIF_CFG_RD_HOLD(v) (((v) & 0x07) << 4)
+#define AEMIF_CFG_TURN_AROUND(v) (((v) & 0x03) << 2)
+#define AEMIF_CFG_WIDTH(v) (((v) & 0x03) << 0)
+
+#define SSTROBE_EN 0x1
+#define EW_EN 0x1
+
+#define WSETUP_MAX 0xf
+#define WSTROBE_MAX 0x3f
+#define WHOLD_MAX 0x7
+#define RSETUP_MAX 0xf
+#define RSTROBE_MAX 0x3f
+#define RHOLD_MAX 0x7
+#define TA_MAX 0x3
+
+#define WIDTH_8BITS 0x0
+#define WIDTH_16BITS 0x1
+
+#define set_config_field(reg, field, val) \
+ do { \
+ if ((val) != -1) { \
+ (reg) &= ~AEMIF_CFG_##field(0xffffffff); \
+ (reg) |= AEMIF_CFG_##field((val)); \
+ } \
+ } while (0)
+
+void aemif_cs_configure(int cs, struct aemif_config *cfg)
+{
+ unsigned long tmp;
+
+ tmp = __raw_readl(cfg->base + AEMIF_CONFIG(cs));
+
+ set_config_field(tmp, SELECT_STROBE, cfg->select_strobe);
+ set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait);
+ set_config_field(tmp, WR_SETUP, cfg->wr_setup);
+ set_config_field(tmp, WR_STROBE, cfg->wr_strobe);
+ set_config_field(tmp, WR_HOLD, cfg->wr_hold);
+ set_config_field(tmp, RD_SETUP, cfg->rd_setup);
+ set_config_field(tmp, RD_STROBE, cfg->rd_strobe);
+ set_config_field(tmp, RD_HOLD, cfg->rd_hold);
+ set_config_field(tmp, TURN_AROUND, cfg->turn_around);
+ set_config_field(tmp, WIDTH, cfg->width);
+
+ __raw_writel(tmp, cfg->base + AEMIF_CONFIG(cs));
+}
+
+struct ti_aemif_cs {
+ void __iomem *base;
+ struct clk *clk;
+};
+
+static unsigned int aemif_calc_cfg(ulong rate, u64 timing_ns, u32 max_cfg)
+{
+ u64 result;
+
+ if (!timing_ns)
+ return 0;
+
+ result = DIV_ROUND_UP_ULL(timing_ns * rate, 1000000000ULL);
+
+ if (result - 1 > max_cfg)
+ return max_cfg;
+
+ return result - 1;
+}
+
+static int aemif_cs_set_timings(struct udevice *dev)
+{
+ struct ti_aemif_cs *priv = dev_get_priv(dev);
+ ulong rate = clk_get_rate(priv->clk);
+ struct aemif_config cfg = {};
+ u32 val;
+ u32 cs;
+
+ if (dev_read_u32(dev, "ti,cs-chipselect", &cs))
+ return -EINVAL;
+
+/*
+ * On DaVinci SoCs, chipselect is in range [2-5]
+ * On Keystone SoCs, chipselect is in range [0-3]
+ * The logic to access the configuration registers expects the CS to be in the
+ * Keystone range so a -2 offset is applied on DaVinci SoCs
+ */
+ if (IS_ENABLED(CONFIG_ARCH_DAVINCI)) {
+ if (cs < 2 || cs > 5)
+ return -EINVAL;
+ cs -= 2;
+ } else if (IS_ENABLED(CONFIG_ARCH_KEYSTONE)) {
+ if (cs > 3)
+ return -EINVAL;
+ }
+
+ if (dev_read_bool(dev, "ti,cs-select-strobe-mode"))
+ cfg.select_strobe = SSTROBE_EN;
+
+ if (dev_read_bool(dev, "ti,cs-extended-wait-mode"))
+ cfg.extend_wait = EW_EN;
+
+ val = dev_read_u32_default(dev, "ti,cs-write-setup-ns", U32_MAX);
+ cfg.wr_setup = aemif_calc_cfg(rate, val, WSETUP_MAX);
+
+ val = dev_read_u32_default(dev, "ti,cs-write-strobe-ns", U32_MAX);
+ cfg.wr_strobe = aemif_calc_cfg(rate, val, WSTROBE_MAX);
+
+ val = dev_read_u32_default(dev, "ti,cs-write-hold-ns", U32_MAX);
+ cfg.wr_hold = aemif_calc_cfg(rate, val, WHOLD_MAX);
+
+ val = dev_read_u32_default(dev, "ti,cs-read-setup-ns", U32_MAX);
+ cfg.rd_setup = aemif_calc_cfg(rate, val, RSETUP_MAX);
+
+ val = dev_read_u32_default(dev, "ti,cs-read-strobe-ns", U32_MAX);
+ cfg.rd_strobe = aemif_calc_cfg(rate, val, RSTROBE_MAX);
+
+ val = dev_read_u32_default(dev, "ti,cs-read-hold-ns", U32_MAX);
+ cfg.rd_hold = aemif_calc_cfg(rate, val, RHOLD_MAX);
+
+ val = dev_read_u32_default(dev, "ti,cs-min-turnaround-ns", U32_MAX);
+ cfg.turn_around = aemif_calc_cfg(rate, val, TA_MAX);
+
+ val = dev_read_u32_default(dev, "ti,cs-bus-width", 8);
+ if (val == 16)
+ cfg.width = WIDTH_16BITS;
+ else
+ cfg.width = WIDTH_8BITS;
+
+ cfg.base = priv->base;
+ aemif_cs_configure(cs, &cfg);
+
+ return 0;
+}
+
+static int aemif_cs_probe(struct udevice *dev)
+{
+ struct ti_aemif_cs *priv = dev_get_priv(dev);
+ struct udevice *aemif;
+
+ aemif = dev_get_parent(dev);
+ if (!aemif)
+ return -ENODEV;
+
+ priv->base = dev_read_addr_ptr(aemif);
+ if (!priv->base)
+ return -EINVAL;
+
+ priv->clk = devm_clk_get(aemif, "aemif");
+ if (IS_ERR(priv->clk))
+ return -EINVAL;
+
+ return aemif_cs_set_timings(dev);
+}
+
+static const struct udevice_id aemif_cs_ids[] = {
+ { .compatible = "ti,da850-aemif-cs", },
+ {},
+};
+
+U_BOOT_DRIVER(ti_aemif_cs) = {
+ .name = "ti_aemif_cs",
+ .id = UCLASS_MEMORY,
+ .of_match = aemif_cs_ids,
+ .probe = aemif_cs_probe,
+ .priv_auto = sizeof(struct ti_aemif_cs),
+};
diff --git a/drivers/memory/ti-aemif-cs.h b/drivers/memory/ti-aemif-cs.h
new file mode 100644
index 0000000..62e6c6e
--- /dev/null
+++ b/drivers/memory/ti-aemif-cs.h
@@ -0,0 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+#include <asm/ti-common/ti-aemif.h>
+
+void aemif_cs_configure(int cs, struct aemif_config *cfg);
diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c
index 29131f5..b26423c 100644
--- a/drivers/memory/ti-aemif.c
+++ b/drivers/memory/ti-aemif.c
@@ -7,61 +7,31 @@
*/
#include <asm/arch/hardware.h>
+#include <asm/io.h>
#include <asm/ti-common/ti-aemif.h>
+#include <dm.h>
+#include "ti-aemif-cs.h"
-#define AEMIF_WAITCYCLE_CONFIG (KS2_AEMIF_CNTRL_BASE + 0x4)
-#define AEMIF_NAND_CONTROL (KS2_AEMIF_CNTRL_BASE + 0x60)
-#define AEMIF_ONENAND_CONTROL (KS2_AEMIF_CNTRL_BASE + 0x5c)
-#define AEMIF_CONFIG(cs) (KS2_AEMIF_CNTRL_BASE + 0x10 + (cs * 4))
-
-#define AEMIF_CFG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0)
-#define AEMIF_CFG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0)
-#define AEMIF_CFG_WR_SETUP(v) (((v) & 0x0f) << 26)
-#define AEMIF_CFG_WR_STROBE(v) (((v) & 0x3f) << 20)
-#define AEMIF_CFG_WR_HOLD(v) (((v) & 0x07) << 17)
-#define AEMIF_CFG_RD_SETUP(v) (((v) & 0x0f) << 13)
-#define AEMIF_CFG_RD_STROBE(v) (((v) & 0x3f) << 7)
-#define AEMIF_CFG_RD_HOLD(v) (((v) & 0x07) << 4)
-#define AEMIF_CFG_TURN_AROUND(v) (((v) & 0x03) << 2)
-#define AEMIF_CFG_WIDTH(v) (((v) & 0x03) << 0)
-
-#define set_config_field(reg, field, val) \
- do { \
- if (val != -1) { \
- reg &= ~AEMIF_CFG_##field(0xffffffff); \
- reg |= AEMIF_CFG_##field(val); \
- } \
- } while (0)
+#define AEMIF_WAITCYCLE_CONFIG (0x4)
+#define AEMIF_NAND_CONTROL (0x60)
+#define AEMIF_ONENAND_CONTROL (0x5c)
static void aemif_configure(int cs, struct aemif_config *cfg)
{
unsigned long tmp;
if (cfg->mode == AEMIF_MODE_NAND) {
- tmp = __raw_readl(AEMIF_NAND_CONTROL);
+ tmp = __raw_readl(cfg->base + AEMIF_NAND_CONTROL);
tmp |= (1 << cs);
- __raw_writel(tmp, AEMIF_NAND_CONTROL);
+ __raw_writel(tmp, cfg->base + AEMIF_NAND_CONTROL);
} else if (cfg->mode == AEMIF_MODE_ONENAND) {
- tmp = __raw_readl(AEMIF_ONENAND_CONTROL);
+ tmp = __raw_readl(cfg->base + AEMIF_ONENAND_CONTROL);
tmp |= (1 << cs);
- __raw_writel(tmp, AEMIF_ONENAND_CONTROL);
+ __raw_writel(tmp, cfg->base + AEMIF_ONENAND_CONTROL);
}
- tmp = __raw_readl(AEMIF_CONFIG(cs));
-
- set_config_field(tmp, SELECT_STROBE, cfg->select_strobe);
- set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait);
- set_config_field(tmp, WR_SETUP, cfg->wr_setup);
- set_config_field(tmp, WR_STROBE, cfg->wr_strobe);
- set_config_field(tmp, WR_HOLD, cfg->wr_hold);
- set_config_field(tmp, RD_SETUP, cfg->rd_setup);
- set_config_field(tmp, RD_STROBE, cfg->rd_strobe);
- set_config_field(tmp, RD_HOLD, cfg->rd_hold);
- set_config_field(tmp, TURN_AROUND, cfg->turn_around);
- set_config_field(tmp, WIDTH, cfg->width);
-
- __raw_writel(tmp, AEMIF_CONFIG(cs));
+ aemif_cs_configure(cs, cfg);
}
void aemif_init(int num_cs, struct aemif_config *config)
@@ -76,3 +46,14 @@
for (cs = 0; cs < num_cs; cs++)
aemif_configure(cs, config + cs);
}
+
+static const struct udevice_id aemif_ids[] = {
+ { .compatible = "ti,da850-aemif", },
+ {},
+};
+
+U_BOOT_DRIVER(ti_aemif) = {
+ .name = "ti_aemif",
+ .id = UCLASS_MEMORY,
+ .of_match = aemif_ids,
+};
diff --git a/drivers/misc/irq-uclass.c b/drivers/misc/irq-uclass.c
index 79eb7c2..ac77859 100644
--- a/drivers/misc/irq-uclass.c
+++ b/drivers/misc/irq-uclass.c
@@ -62,6 +62,40 @@
return ops->read_and_clear(irq);
}
+int irq_get_interrupt_parent(const struct udevice *dev,
+ struct udevice **interrupt_parent)
+{
+ struct ofnode_phandle_args phandle_args;
+ struct udevice *irq = NULL;
+ ofnode node;
+ int ret;
+
+ if (!dev || !interrupt_parent)
+ return -EINVAL;
+
+ *interrupt_parent = NULL;
+
+ node = dev_ofnode(dev);
+ if (!ofnode_valid(node))
+ return -EINVAL;
+
+ while (ofnode_valid(node)) {
+ ret = ofnode_parse_phandle_with_args(node, "interrupt-parent",
+ NULL, 0, 0, &phandle_args);
+ if (!ret && !device_get_global_by_ofnode(phandle_args.node, &irq))
+ break;
+ node = ofnode_get_parent(node);
+ }
+
+ if (!irq) {
+ log_err("Cannot find an interrupt parent for device %s\n", dev->name);
+ return -ENODEV;
+ }
+ *interrupt_parent = irq;
+
+ return 0;
+}
+
#if CONFIG_IS_ENABLED(OF_PLATDATA)
int irq_get_by_phandle(struct udevice *dev, const struct phandle_2_arg *cells,
struct irq *irq)
@@ -142,10 +176,40 @@
int irq_get_by_index(struct udevice *dev, int index, struct irq *irq)
{
struct ofnode_phandle_args args;
- int ret;
+ struct udevice *interrupt_parent;
+ int ret, size, i;
+ const __be32 *list;
+ u32 count;
ret = dev_read_phandle_with_args(dev, "interrupts-extended",
"#interrupt-cells", 0, index, &args);
+ if (ret) {
+ list = dev_read_prop(dev, "interrupts", &size);
+ if (!list)
+ return -ENOENT;
+
+ ret = irq_get_interrupt_parent(dev, &interrupt_parent);
+ if (ret)
+ return -ENODEV;
+ args.node = dev_ofnode(interrupt_parent);
+
+ if (dev_read_u32(interrupt_parent, "#interrupt-cells", &count)) {
+ log_err("%s: could not get #interrupt-cells for %s\n",
+ __func__, dev->name);
+ return -ENOENT;
+ }
+
+ if (index * count >= size / sizeof(*list))
+ return -ENOENT;
+ if (count > OF_MAX_PHANDLE_ARGS)
+ count = OF_MAX_PHANDLE_ARGS;
+ args.args_count = count;
+ for (i = 0; i < count; i++)
+ args.args[i] = be32_to_cpup(&list[index * count + i]);
+
+ return irq_get_by_index_tail(ret, dev_ofnode(dev), &args,
+ "interrupts", index, irq);
+ }
return irq_get_by_index_tail(ret, dev_ofnode(dev), &args,
"interrupts-extended", index > 0, irq);
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 23db2a7..92afa6a 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -864,6 +864,7 @@
{ .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
{ .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
{ .compatible = "renesas,rcar-gen4-sdhi", .data = RENESAS_GEN3_QUIRKS },
+ { .compatible = "renesas,rzg2l-sdhi", .data = RENESAS_GEN3_QUIRKS },
{ /* sentinel */ }
};
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index f5c9868..ec841fb 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -1134,12 +1134,10 @@
offset /= 2;
if (nor->flags & SNOR_F_HAS_STACKED) {
- if (offset >= (mtd->size / 2)) {
- offset = offset - (mtd->size / 2);
+ if (offset >= (mtd->size / 2))
nor->spi->flags |= SPI_XFER_U_PAGE;
- } else {
+ else
nor->spi->flags &= ~SPI_XFER_U_PAGE;
- }
}
#ifdef CONFIG_SPI_FLASH_BAR
ret = write_bar(nor, addr);
@@ -1588,23 +1586,22 @@
dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
if ((nor->flags & SNOR_F_HAS_PARALLEL) && (offset & 1)) {
- /* We can hit this case when we use file system like ubifs */
+ /* We can hit this case when we use file system like ubifs */
from--;
len++;
is_ofst_odd = true;
}
while (len) {
- if (nor->addr_width == 3) {
- if (nor->flags & SNOR_F_HAS_PARALLEL) {
- bank = (u32)from / (SZ_16M << 0x01);
- rem_bank_len = ((SZ_16M << 0x01) *
- (bank + 1)) - from;
- } else {
- bank = (u32)from / SZ_16M;
- rem_bank_len = (SZ_16M * (bank + 1)) - from;
- }
- }
+ bank = (u32)from / SZ_16M;
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ bank /= 2;
+
+ rem_bank_len = SZ_16M * (bank + 1);
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ rem_bank_len *= 2;
+ rem_bank_len -= from;
+
offset = from;
if (nor->flags & SNOR_F_HAS_STACKED) {
@@ -1619,13 +1616,11 @@
if (nor->flags & SNOR_F_HAS_PARALLEL)
offset /= 2;
- if (nor->addr_width == 3) {
#ifdef CONFIG_SPI_FLASH_BAR
- ret = write_bar(nor, offset);
- if (ret < 0)
- return log_ret(ret);
+ ret = write_bar(nor, offset);
+ if (ret < 0)
+ return log_ret(ret);
#endif
- }
if (len < rem_bank_len)
read_len = len;
@@ -1635,10 +1630,6 @@
if (read_len == 0)
return -EIO;
- ret = spi_nor_wait_till_ready(nor);
- if (ret)
- goto read_err;
-
ret = nor->read(nor, offset, read_len, buf);
if (ret == 0) {
/* We shouldn't see 0-length reads */
@@ -1977,9 +1968,9 @@
return ret;
*retlen += 1; /* We've written only one actual byte */
- ++buf;
- --len;
- ++to;
+ buf++;
+ len--;
+ to++;
}
for (i = 0; i < len; ) {
@@ -1999,7 +1990,7 @@
page_offset = do_div(aux, nor->page_size);
}
- offset = (to + i);
+ offset = to + i;
if (nor->flags & SNOR_F_HAS_PARALLEL)
offset /= 2;
@@ -2012,21 +2003,16 @@
}
}
- if (nor->addr_width == 3) {
#ifdef CONFIG_SPI_FLASH_BAR
- ret = write_bar(nor, offset);
- if (ret < 0)
- return ret;
+ ret = write_bar(nor, offset);
+ if (ret < 0)
+ return ret;
#endif
- }
+
/* the size of data remaining on the first page */
page_remain = min_t(size_t,
nor->page_size - page_offset, len - i);
- ret = spi_nor_wait_till_ready(nor);
- if (ret)
- goto write_err;
-
write_enable(nor);
/*
* On DTR capable flashes like Micron Xcella the writes cannot
@@ -2086,10 +2072,6 @@
if (ret)
goto write_err;
- ret = write_disable(nor);
- if (ret)
- goto write_err;
-
*retlen += written;
i += written;
}
@@ -2130,10 +2112,6 @@
if (ret)
return ret;
- ret = write_disable(nor);
- if (ret)
- return ret;
-
ret = read_sr(nor);
if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
dev_err(nor->dev, "Macronix Quad bit not set\n");
@@ -2195,7 +2173,7 @@
return -EINVAL;
}
- return write_disable(nor);
+ return 0;
}
#endif
@@ -3069,13 +3047,6 @@
const struct flash_info *info,
struct spi_nor_flash_parameter *params)
{
-#if CONFIG_IS_ENABLED(DM_SPI) && CONFIG_IS_ENABLED(SPI_ADVANCE)
- struct udevice *dev = nor->spi->dev;
- u64 flash_size[SNOR_FLASH_CNT_MAX] = {0};
- u32 idx = 0, i = 0;
- int rc;
-#endif
-
/* Set legacy flash parameters as default. */
memset(params, 0, sizeof(*params));
@@ -3194,62 +3165,71 @@
spi_nor_post_sfdp_fixups(nor, params);
}
-#if CONFIG_IS_ENABLED(DM_SPI) && CONFIG_IS_ENABLED(SPI_ADVANCE)
- /*
- * The flashes that are connected in stacked mode should be of same make.
- * Except the flash size all other properties are identical for all the
- * flashes connected in stacked mode.
- * The flashes that are connected in parallel mode should be identical.
- */
- while (i < SNOR_FLASH_CNT_MAX) {
- rc = ofnode_read_u64_index(dev_ofnode(dev), "stacked-memories",
- idx, &flash_size[i]);
- if (rc == -EINVAL) {
- break;
- } else if (rc == -EOVERFLOW) {
- idx++;
- } else {
- idx++;
- i++;
- if (!(nor->flags & SNOR_F_HAS_STACKED))
- nor->flags |= SNOR_F_HAS_STACKED;
- if (!(nor->spi->flags & SPI_XFER_STACKED))
- nor->spi->flags |= SPI_XFER_STACKED;
+
+#if CONFIG_IS_ENABLED(DM_SPI)
+ if (CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL)) {
+ u64 flash_size[SNOR_FLASH_CNT_MAX] = { 0 };
+ struct udevice *dev = nor->spi->dev;
+ u32 idx = 0, i = 0;
+ int rc;
+
+ /*
+ * The flashes that are connected in stacked mode should be of same make.
+ * Except the flash size all other properties are identical for all the
+ * flashes connected in stacked mode.
+ * The flashes that are connected in parallel mode should be identical.
+ */
+ while (i < SNOR_FLASH_CNT_MAX) {
+ rc = ofnode_read_u64_index(dev_ofnode(dev), "stacked-memories",
+ idx, &flash_size[i]);
+ if (rc == -EINVAL) {
+ break;
+ } else if (rc == -EOVERFLOW) {
+ idx++;
+ } else {
+ idx++;
+ i++;
+ if (!(nor->flags & SNOR_F_HAS_STACKED))
+ nor->flags |= SNOR_F_HAS_STACKED;
+ if (!(nor->spi->flags & SPI_XFER_STACKED))
+ nor->spi->flags |= SPI_XFER_STACKED;
+ }
}
- }
- i = 0;
- idx = 0;
- while (i < SNOR_FLASH_CNT_MAX) {
- rc = ofnode_read_u64_index(dev_ofnode(dev), "parallel-memories",
- idx, &flash_size[i]);
- if (rc == -EINVAL) {
- break;
- } else if (rc == -EOVERFLOW) {
- idx++;
- } else {
- idx++;
- i++;
- if (!(nor->flags & SNOR_F_HAS_PARALLEL))
- nor->flags |= SNOR_F_HAS_PARALLEL;
+ i = 0;
+ idx = 0;
+ while (i < SNOR_FLASH_CNT_MAX) {
+ rc = ofnode_read_u64_index(dev_ofnode(dev), "parallel-memories",
+ idx, &flash_size[i]);
+ if (rc == -EINVAL) {
+ break;
+ } else if (rc == -EOVERFLOW) {
+ idx++;
+ } else {
+ idx++;
+ i++;
+ if (!(nor->flags & SNOR_F_HAS_PARALLEL))
+ nor->flags |= SNOR_F_HAS_PARALLEL;
+ }
}
- }
- if (nor->flags & (SNOR_F_HAS_STACKED | SNOR_F_HAS_PARALLEL)) {
- params->size = 0;
- for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++)
- params->size += flash_size[idx];
- }
- /*
- * In parallel-memories the erase operation is
- * performed on both the flashes simultaneously
- * so, double the erasesize.
- */
- if (nor->flags & SNOR_F_HAS_PARALLEL) {
- nor->mtd.erasesize <<= 1;
- params->page_size <<= 1;
+ if (nor->flags & (SNOR_F_HAS_STACKED | SNOR_F_HAS_PARALLEL)) {
+ params->size = 0;
+ for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++)
+ params->size += flash_size[idx];
+ }
+ /*
+ * In parallel-memories the erase operation is
+ * performed on both the flashes simultaneously
+ * so, double the erasesize.
+ */
+ if (nor->flags & SNOR_F_HAS_PARALLEL) {
+ nor->mtd.erasesize <<= 1;
+ params->page_size <<= 1;
+ }
}
#endif
+
spi_nor_late_init_fixups(nor, params);
return 0;
@@ -3599,19 +3579,6 @@
mtd->erasesize = info->sector_size;
}
- if ((JEDEC_MFR(info) == SNOR_MFR_SST) && info->flags & SECT_4K) {
- nor->erase_opcode = SPINOR_OP_BE_4K;
- /*
- * In parallel-memories the erase operation is
- * performed on both the flashes simultaneously
- * so, double the erasesize.
- */
- if (nor->flags & SNOR_F_HAS_PARALLEL)
- mtd->erasesize = 4096 * 2;
- else
- mtd->erasesize = 4096;
- }
-
return 0;
}
@@ -4606,7 +4573,6 @@
#else
/* Configure the BAR - discover bank cmds and read current bank */
nor->addr_width = 3;
- set_4byte(nor, info, 0);
ret = read_bar(nor, info);
if (ret < 0)
return ret;
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 89f7411..576cd2d 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -525,11 +525,11 @@
The Microchip KS8851 parallel bus external ethernet interface chip.
config KSZ9477
- bool "Microchip KSZ9477 I2C controller driver"
- depends on DM_DSA && DM_I2C
+ bool "Microchip KSZ9477 controller driver"
+ depends on DM_DSA && (DM_I2C || DM_SPI)
help
This driver implements a DSA switch driver for the KSZ9477 family
- of GbE switches using the I2C interface.
+ of GbE switches using the I2C or SPI interface.
config LITEETH
bool "LiteX LiteEth Ethernet MAC"
@@ -762,6 +762,38 @@
help
This driver supports DEC DC2114x Fast ethernet chips.
+config TULIP_SUPPORT_NON_PCI
+ bool "No PCI controller"
+ depends on TULIP
+ default n
+ help
+ Say Y to this and you can run this driver on platforms that do not
+ have PCI controllers.
+
+config TULIP_IGNORE_TX_NO_CARRIER
+ bool "Ignore tx no carrier error"
+ depends on TULIP
+ default n
+ help
+ Some IP cores of dc2114x or its variants do not comply so well with
+ the behaviors described by the official document. A packet could be
+ sent successfully but reported with No Carrier error. Latest drivers
+ of this IP core do not detect this error anymore. Say Y to this could
+ disable handling of this error.
+
+config TULIP_MULTIPLE_TX_DESC
+ bool "Use multiple tx descriptors"
+ depends on TULIP
+ default n
+ help
+ Some IP cores of dc2114x or its variants do not comply so well with
+ the behaviors described by the official document. Originally this
+ driver uses only one tx descriptor and organizes it as a ring buffer,
+ which would lead to a problem that one packet would be sent twice.
+ Say Y to this could prevent this bug if you are using IP cores with
+ this issue, by using multiple tx descriptors and organizing them as
+ a real well-defined ring buffer.
+
config XILINX_AXIEMAC
select PHYLIB
select MII
diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c
index ce028f4..7c0665f 100644
--- a/drivers/net/dc2114x.c
+++ b/drivers/net/dc2114x.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
#include <asm/io.h>
+#include <cpu_func.h>
#include <dm.h>
#include <malloc.h>
#include <net.h>
@@ -72,10 +73,20 @@
#define POLL_DEMAND 1
+#if CONFIG_IS_ENABLED(TULIP_SUPPORT_NON_PCI)
+#define phys_to_bus(dev, a) virt_to_phys((volatile const void *)(a))
+#else
#define phys_to_bus(dev, a) dm_pci_phys_to_mem((dev), (a))
+#endif
+
+/* Number of TX descriptors */
+#if CONFIG_IS_ENABLED(TULIP_MULTIPLE_TX_DESC)
+#define NUM_TX_DESC 4
+#else
+#define NUM_TX_DESC 1
+#endif
#define NUM_RX_DESC PKTBUFSRX
-#define NUM_TX_DESC 1 /* Number of TX descriptors */
#define RX_BUFF_SZ PKTSIZE_ALIGN
#define TOUT_LOOP 1000000
@@ -89,9 +100,17 @@
u32 next;
};
+/* Assigned for network card's ring buffer:
+ * Some CPU might treat these memories as cached, and changes to these memories
+ * won't immediately be visible to each other. It is necessary to ensure that
+ * these memories between the CPU and the network card are marked as uncached.
+ */
+static struct de4x5_desc rx_ring[NUM_RX_DESC] __aligned(32);
+static struct de4x5_desc tx_ring[NUM_TX_DESC] __aligned(32);
+
struct dc2114x_priv {
- struct de4x5_desc rx_ring[NUM_RX_DESC] __aligned(32);
- struct de4x5_desc tx_ring[NUM_TX_DESC] __aligned(32);
+ struct de4x5_desc *rx_ring; /* Must be uncached to CPU */
+ struct de4x5_desc *tx_ring; /* Must be uncached to CPU */
int rx_new; /* RX descriptor ring pointer */
int tx_new; /* TX descriptor ring pointer */
char rx_ring_size;
@@ -271,7 +290,12 @@
static void send_setup_frame(struct dc2114x_priv *priv)
{
- char setup_frame[SETUP_FRAME_LEN];
+ /* We are writing setup frame and these changes should be visible to the
+ * network card immediately. So let's directly read/write through the
+ * uncached window.
+ */
+ char __setup_frame[SETUP_FRAME_LEN] __aligned(32);
+ char *setup_frame = (char *)map_physmem((phys_addr_t)virt_to_phys(__setup_frame), 0, MAP_NOCACHE);
char *pa = &setup_frame[0];
int i;
@@ -292,8 +316,13 @@
}
priv->tx_ring[priv->tx_new].buf = cpu_to_le32(phys_to_bus(priv->devno,
- (u32)&setup_frame[0]));
+ (phys_addr_t)&setup_frame[0]));
+#if CONFIG_IS_ENABLED(TULIP_MULTIPLE_TX_DESC)
+ priv->tx_ring[priv->tx_new].des1 = cpu_to_le32(TD_SET | SETUP_FRAME_LEN);
+ priv->tx_ring[priv->tx_ring_size - 1].des1 |= cpu_to_le32(TD_TER);
+#else
priv->tx_ring[priv->tx_new].des1 = cpu_to_le32(TD_TER | TD_SET | SETUP_FRAME_LEN);
+#endif
priv->tx_ring[priv->tx_new].status = cpu_to_le32(T_OWN);
dc2114x_outl(priv, POLL_DEMAND, DE4X5_TPD);
@@ -307,7 +336,7 @@
}
if (le32_to_cpu(priv->tx_ring[priv->tx_new].status) != 0x7FFFFFFF) {
- printf("TX error status2 = 0x%08X\n",
+ debug("TX error status2 = 0x%08X\n",
le32_to_cpu(priv->tx_ring[priv->tx_new].status));
}
@@ -332,9 +361,17 @@
goto done;
}
+ /* Packet should be visible to the network card */
+ flush_dcache_range((phys_addr_t)packet, (phys_addr_t)(packet + RX_BUFF_SZ));
+
priv->tx_ring[priv->tx_new].buf = cpu_to_le32(phys_to_bus(priv->devno,
- (u32)packet));
+ (phys_addr_t)packet));
+#if CONFIG_IS_ENABLED(TULIP_MULTIPLE_TX_DESC)
+ priv->tx_ring[priv->tx_new].des1 = cpu_to_le32(TD_LS | TD_FS | length);
+ priv->tx_ring[priv->tx_ring_size - 1].des1 |= cpu_to_le32(TD_TER);
+#else
priv->tx_ring[priv->tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
+#endif
priv->tx_ring[priv->tx_new].status = cpu_to_le32(T_OWN);
dc2114x_outl(priv, POLL_DEMAND, DE4X5_TPD);
@@ -349,7 +386,9 @@
if (le32_to_cpu(priv->tx_ring[priv->tx_new].status) & TD_ES) {
priv->tx_ring[priv->tx_new].status = 0x0;
+#if !CONFIG_IS_ENABLED(TULIP_IGNORE_TX_NO_CARRIER)
goto done;
+#endif
}
status = length;
@@ -398,13 +437,22 @@
return -1;
}
- dc2114x_outl(priv, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
+ /* 2024-07:
+ * Remove the OMR_PM flag and choose 16 perfect filtering mode since in
+ * modern networks there're plenty of multicasts and set ORM_PM flag will
+ * increase the dc2114x's workload and ask the U-Boot to handle packets
+ * not related to itself. And most of the time, U-Boot does not need this
+ * feature.
+ *
+ * A better way: let user to decide whether to have this flag.
+ */
+ dc2114x_outl(priv, OMR_SDP | OMR_PS, DE4X5_OMR);
for (i = 0; i < NUM_RX_DESC; i++) {
priv->rx_ring[i].status = cpu_to_le32(R_OWN);
priv->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
priv->rx_ring[i].buf = cpu_to_le32(phys_to_bus(priv->devno,
- (u32)net_rx_packets[i]));
+ (phys_addr_t)net_rx_packets[i]));
priv->rx_ring[i].next = 0;
}
@@ -423,9 +471,9 @@
priv->tx_ring[priv->tx_ring_size - 1].des1 |= cpu_to_le32(TD_TER);
/* Tell the adapter where the TX/RX rings are located. */
- dc2114x_outl(priv, phys_to_bus(priv->devno, (u32)&priv->rx_ring),
+ dc2114x_outl(priv, phys_to_bus(priv->devno, (phys_addr_t)priv->rx_ring),
DE4X5_RRBA);
- dc2114x_outl(priv, phys_to_bus(priv->devno, (u32)&priv->tx_ring),
+ dc2114x_outl(priv, phys_to_bus(priv->devno, (phys_addr_t)priv->tx_ring),
DE4X5_TRBA);
start_de4x5(priv);
@@ -461,21 +509,32 @@
}
}
+#if !CONFIG_IS_ENABLED(TULIP_SUPPORT_NON_PCI)
static struct pci_device_id supported[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST) },
{ PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142) },
{ }
};
+#endif
static int dc2114x_start(struct udevice *dev)
{
- struct eth_pdata *plat = dev_get_plat(dev);
struct dc2114x_priv *priv = dev_get_priv(dev);
+ int rval;
- memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
+ if (!priv->enetaddr) {
+ rval = eth_env_get_enetaddr("ethaddr", priv->enetaddr);
+ if (!rval) {
+ printf("dc2114x: Err: please set a valid MAC address\n");
+ return -EINVAL;
+ }
+ }
+
+#if !CONFIG_IS_ENABLED(TULIP_SUPPORT_NON_PCI)
/* Ensure we're not sleeping. */
dm_pci_write_config8(dev, PCI_CFDA_PSM, WAKEUP);
+#endif
return dc21x4x_init_common(priv);
}
@@ -485,8 +544,9 @@
struct dc2114x_priv *priv = dev_get_priv(dev);
dc21x4x_halt_common(priv);
-
+#if !CONFIG_IS_ENABLED(TULIP_SUPPORT_NON_PCI)
dm_pci_write_config8(dev, PCI_CFDA_PSM, SLEEP);
+#endif
}
static int dc2114x_send(struct udevice *dev, void *packet, int length)
@@ -515,7 +575,8 @@
if (!ret)
return 0;
- *packetp = net_rx_packets[priv->rx_new];
+ invalidate_dcache_range((phys_addr_t)net_rx_packets[priv->rx_new], (phys_addr_t)(net_rx_packets[priv->rx_new] + RX_BUFF_SZ));
+ *packetp = (uchar *)net_rx_packets[priv->rx_new];
return ret - 4;
}
@@ -543,7 +604,7 @@
static int dc2114x_bind(struct udevice *dev)
{
- static int card_number;
+ static int card_number = 0;
char name[16];
sprintf(name, "dc2114x#%u", card_number++);
@@ -555,6 +616,8 @@
{
struct eth_pdata *plat = dev_get_plat(dev);
struct dc2114x_priv *priv = dev_get_priv(dev);
+
+#if !CONFIG_IS_ENABLED(TULIP_SUPPORT_NON_PCI)
u16 command, status;
u32 iobase;
@@ -562,9 +625,6 @@
iobase &= ~0xf;
debug("dc2114x: DEC 2114x PCI Device @0x%x\n", iobase);
-
- priv->devno = dev;
- priv->enetaddr = plat->enetaddr;
priv->iobase = (void __iomem *)dm_pci_mem_to_phys(dev, iobase);
command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
@@ -576,10 +636,29 @@
}
dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x60);
+#endif
+
+ priv->devno = dev;
+ priv->enetaddr = plat->enetaddr;
+ priv->rx_ring = (struct de4x5_desc *)map_physmem((phys_addr_t)virt_to_phys(rx_ring), 0, MAP_NOCACHE);
+ priv->tx_ring = (struct de4x5_desc *)map_physmem((phys_addr_t)virt_to_phys(tx_ring), 0, MAP_NOCACHE);
return 0;
}
+#if CONFIG_IS_ENABLED(TULIP_SUPPORT_NON_PCI)
+static int dc2114x_of_to_plat(struct udevice *dev)
+{
+ struct eth_pdata *plat = dev_get_plat(dev);
+ struct dc2114x_priv *priv = dev_get_priv(dev);
+
+ plat->iobase = (phys_addr_t)map_physmem((phys_addr_t)devfdt_get_addr(dev), 0, MAP_NOCACHE);
+ priv->iobase = (void *)plat->iobase;
+
+ return 0;
+}
+#endif
+
static const struct eth_ops dc2114x_ops = {
.start = dc2114x_start,
.send = dc2114x_send,
@@ -589,9 +668,23 @@
.read_rom_hwaddr = dc2114x_read_rom_hwaddr,
};
+#if CONFIG_IS_ENABLED(TULIP_SUPPORT_NON_PCI)
+static const struct udevice_id dc2114x_eth_ids[] = {
+ { .compatible = "dec,dmfe" },
+ { .compatible = "tulip,dmfe" },
+ { .compatible = "dec,dc2114x" },
+ { .compatible = "tulip,dc2114x" },
+ { }
+};
+#endif
+
U_BOOT_DRIVER(eth_dc2114x) = {
.name = "eth_dc2114x",
.id = UCLASS_ETH,
+#if CONFIG_IS_ENABLED(TULIP_SUPPORT_NON_PCI)
+ .of_match = dc2114x_eth_ids,
+ .of_to_plat = dc2114x_of_to_plat,
+#endif
.bind = dc2114x_bind,
.probe = dc2114x_probe,
.ops = &dc2114x_ops,
@@ -599,4 +692,6 @@
.plat_auto = sizeof(struct eth_pdata),
};
+#if !CONFIG_IS_ENABLED(TULIP_SUPPORT_NON_PCI)
U_BOOT_PCI_DEVICE(eth_dc2114x, supported);
+#endif
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 3415c41..2279481 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -47,10 +47,6 @@
#include <asm/cache.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#ifdef CONFIG_ARCH_IMX8M
-#include <asm/arch/clock.h>
-#include <asm/mach-imx/sys_proto.h>
-#endif
#include <linux/bitfield.h>
#include <linux/delay.h>
#include <linux/printk.h>
@@ -712,6 +708,9 @@
*/
setbits_le32(&eqos->dma_regs->mode, EQOS_DMA_MODE_SWR);
+ if (eqos->config->ops->eqos_fix_soc_reset)
+ eqos->config->ops->eqos_fix_soc_reset(dev);
+
ret = wait_for_bit_le32(&eqos->dma_regs->mode,
EQOS_DMA_MODE_SWR, false,
eqos->config->swr_wait, false);
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index ce57e22..123f98d 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -248,6 +248,7 @@
int (*eqos_set_tx_clk_speed)(struct udevice *dev);
int (*eqos_get_enetaddr)(struct udevice *dev);
ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
+ void (*eqos_fix_soc_reset)(struct udevice *dev);
};
struct eqos_priv {
diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c
index 6424328..af42f74 100644
--- a/drivers/net/dwc_eth_qos_imx.c
+++ b/drivers/net/dwc_eth_qos_imx.c
@@ -216,6 +216,27 @@
return 0;
}
+static void eqos_fix_soc_reset_imx(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+
+ if (IS_ENABLED(CONFIG_IMX93)) {
+ /*
+ * Workaround for ERR051683 in i.MX93
+ * The i.MX93 requires speed configuration bits to be set to
+ * complete the reset procedure in RMII mode.
+ * See b536f32b5b03 ("net: stmmac: dwmac-imx: use platform
+ * specific reset for imx93 SoCs") in linux
+ */
+ if (eqos->config->interface(dev) == PHY_INTERFACE_MODE_RMII) {
+ udelay(200);
+ setbits_le32(&eqos->mac_regs->configuration,
+ EQOS_MAC_CONFIGURATION_PS |
+ EQOS_MAC_CONFIGURATION_FES);
+ }
+ }
+}
+
static struct eqos_ops eqos_imx_ops = {
.eqos_inval_desc = eqos_inval_desc_generic,
.eqos_flush_desc = eqos_flush_desc_generic,
@@ -232,6 +253,7 @@
.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx,
.eqos_get_enetaddr = eqos_get_enetaddr_imx,
.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx,
+ .eqos_fix_soc_reset = eqos_fix_soc_reset_imx,
};
struct eqos_config __maybe_unused eqos_imx_config = {
diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c
index d18a8d5..f64dbb7 100644
--- a/drivers/net/eepro100.c
+++ b/drivers/net/eepro100.c
@@ -678,7 +678,7 @@
status = le16_to_cpu(desc->status);
if (!(status & RFD_STATUS_C))
- return 0;
+ return -EAGAIN;
/* Valid frame status. */
if (status & RFD_STATUS_OK) {
diff --git a/drivers/net/ksz9477.c b/drivers/net/ksz9477.c
index 43baa69..7ebbe19 100644
--- a/drivers/net/ksz9477.c
+++ b/drivers/net/ksz9477.c
@@ -11,7 +11,12 @@
#include <eth_phy.h>
#include <linux/delay.h>
#include <miiphy.h>
-#include <i2c.h>
+#if CONFIG_IS_ENABLED(DM_I2C)
+# include <i2c.h>
+#endif
+#if CONFIG_IS_ENABLED(DM_SPI)
+# include <spi.h>
+#endif
#include <net/dsa.h>
#include <asm-generic/gpio.h>
@@ -71,15 +76,157 @@
#define MMD_SETUP(mode, dev) (((u16)(mode) << PORT_MMD_OP_MODE_S) | (dev))
#define REG_PORT_PHY_MMD_INDEX_DATA 0x011C
+/* SPI specific define (opcodes) */
+#define KSZ_SPI_OP_RD 3
+#define KSZ_SPI_OP_WR 2
+
+#define KSZ9477_SPI_ADDR_SHIFT 24
+#define KSZ9477_SPI_ADDR_ALIGN 3
+#define KSZ9477_SPI_TURNAROUND_SHIFT 5
+
+/**
+ * struct ksz_phy_ops - low-level KSZ bus operations
+ */
+struct ksz_phy_ops {
+ /* read() - Read bytes from the device
+ *
+ * @udev: bus device
+ * @reg: register offset
+ * @val: data read
+ * @len: Number of bytes to read
+ *
+ * @return: 0 on success, negative on failure
+ */
+ int (*read)(struct udevice *udev, u32 reg, u8 *val, int len);
+
+ /* write() - Write bytes to the device
+ *
+ * @udev: bus device
+ * @reg: register offset
+ * @val: data to write
+ * @len: Number of bytes to write
+ *
+ * @return: 0 on success, negative on failure
+ */
+ int (*write)(struct udevice *udev, u32 reg, u8 *val, int len);
+};
+
struct ksz_dsa_priv {
struct udevice *dev;
+ struct ksz_phy_ops *phy_ops;
u32 features; /* chip specific features */
};
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+static inline int ksz_i2c_read(struct udevice *dev, u32 reg, u8 *val, int len)
+{
+ return dm_i2c_read(dev, reg, val, len);
+}
+
+static inline int ksz_i2c_write(struct udevice *dev, u32 reg, u8 *val, int len)
+{
+ return dm_i2c_write(dev, reg, val, len);
+}
+
+static struct ksz_phy_ops phy_i2c_ops = {
+ .read = ksz_i2c_read,
+ .write = ksz_i2c_write,
+};
+#endif
+
+#if CONFIG_IS_ENABLED(DM_SPI)
+/**
+ * ksz_spi_xfer() - only used for 8/16/32 bits bus access
+ *
+ * @dev: The SPI slave device which will be sending/receiving the data.
+ * @reg: register address.
+ * @out: Pointer to a string of bits to send out. The bits are
+ * held in a byte array and are sent MSB first.
+ * @in: Pointer to a string of bits that will be filled in.
+ * @len: number of bytes to read.
+ *
+ * Return: 0 on success, not 0 on failure
+ */
+static int ksz_spi_xfer(struct udevice *dev, u32 reg, const u8 *out,
+ u8 *in, u16 len)
+{
+ int ret;
+ u32 addr = 0;
+ u8 opcode;
+
+ if (in && out) {
+ printf("%s: can't do full duplex\n", __func__);
+ return -EINVAL;
+ }
+
+ if (len > 4 || len == 0) {
+ printf("%s: only 8/16/32 bits bus access supported\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ ret = dm_spi_claim_bus(dev);
+ if (ret < 0) {
+ printf("%s: could not claim bus\n", __func__);
+ return ret;
+ }
+
+ opcode = (in ? KSZ_SPI_OP_RD : KSZ_SPI_OP_WR);
+
+ /* The actual device address space is 16 bits (A15 - A0),
+ * so the values of address bits A23 - A16 in the SPI
+ * command/address phase are “don't care”.
+ */
+ addr |= opcode << (KSZ9477_SPI_ADDR_SHIFT + KSZ9477_SPI_TURNAROUND_SHIFT);
+ addr |= reg << KSZ9477_SPI_TURNAROUND_SHIFT;
+
+ addr = __swab32(addr);
+
+ ret = dm_spi_xfer(dev, 32, &addr, NULL, SPI_XFER_BEGIN);
+ if (ret) {
+ printf("%s ERROR: dm_spi_xfer addr (%u)\n", __func__, ret);
+ goto release_bus;
+ }
+
+ ret = dm_spi_xfer(dev, len * 8, out, in, SPI_XFER_END);
+ if (ret) {
+ printf("%s ERROR: dm_spi_xfer data (%u)\n", __func__, ret);
+ goto release_bus;
+ }
+
+release_bus:
+ /* If an error occurred, release the chip by deasserting the CS */
+ if (ret < 0)
+ dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_END);
+
+ dm_spi_release_bus(dev);
+
+ return ret;
+}
+
+static inline int ksz_spi_read(struct udevice *dev, u32 reg, u8 *val, int len)
+{
+ return ksz_spi_xfer(dev, reg, NULL, val, len);
+}
+
+static inline int ksz_spi_write(struct udevice *dev, u32 reg, u8 *val, int len)
+{
+ return ksz_spi_xfer(dev, reg, val, NULL, len);
+}
+
+static struct ksz_phy_ops phy_spi_ops = {
+ .read = ksz_spi_read,
+ .write = ksz_spi_write,
+};
+#endif
static inline int ksz_read8(struct udevice *dev, u32 reg, u8 *val)
{
- int ret = dm_i2c_read(dev, reg, val, 1);
+ struct ksz_dsa_priv *priv = dev_get_priv(dev);
+ struct ksz_phy_ops *phy_ops = priv->phy_ops;
+
+ int ret = phy_ops->read(dev, reg, val, 1);
dev_dbg(dev, "%s 0x%04x<<0x%02x\n", __func__, reg, *val);
@@ -93,8 +240,11 @@
static inline int ksz_write8(struct udevice *dev, u32 reg, u8 val)
{
+ struct ksz_dsa_priv *priv = dev_get_priv(dev);
+ struct ksz_phy_ops *phy_ops = priv->phy_ops;
+
dev_dbg(dev, "%s 0x%04x>>0x%02x\n", __func__, reg, val);
- return dm_i2c_write(dev, reg, &val, 1);
+ return phy_ops->write(dev, reg, &val, 1);
}
static inline int ksz_pwrite8(struct udevice *dev, int port, int reg, u8 val)
@@ -104,13 +254,15 @@
static inline int ksz_write16(struct udevice *dev, u32 reg, u16 val)
{
+ struct ksz_dsa_priv *priv = dev_get_priv(dev);
+ struct ksz_phy_ops *phy_ops = priv->phy_ops;
u8 buf[2];
buf[1] = val & 0xff;
buf[0] = val >> 8;
dev_dbg(dev, "%s 0x%04x>>0x%04x\n", __func__, reg, val);
- return dm_i2c_write(dev, reg, buf, 2);
+ return phy_ops->write(dev, reg, buf, 2);
}
static inline int ksz_pwrite16(struct udevice *dev, int port, int reg, u16 val)
@@ -120,10 +272,12 @@
static inline int ksz_read16(struct udevice *dev, u32 reg, u16 *val)
{
+ struct ksz_dsa_priv *priv = dev_get_priv(dev);
+ struct ksz_phy_ops *phy_ops = priv->phy_ops;
u8 buf[2];
int ret;
- ret = dm_i2c_read(dev, reg, buf, 2);
+ ret = phy_ops->read(dev, reg, buf, 2);
*val = (buf[0] << 8) | buf[1];
dev_dbg(dev, "%s 0x%04x<<0x%04x\n", __func__, reg, *val);
@@ -137,7 +291,10 @@
static inline int ksz_read32(struct udevice *dev, u32 reg, u32 *val)
{
- return dm_i2c_read(dev, reg, (u8 *)val, 4);
+ struct ksz_dsa_priv *priv = dev_get_priv(dev);
+ struct ksz_phy_ops *phy_ops = priv->phy_ops;
+
+ return phy_ops->read(dev, reg, (u8 *)val, 4);
}
static inline int ksz_pread32(struct udevice *dev, int port, int reg, u32 *val)
@@ -147,6 +304,8 @@
static inline int ksz_write32(struct udevice *dev, u32 reg, u32 val)
{
+ struct ksz_dsa_priv *priv = dev_get_priv(dev);
+ struct ksz_phy_ops *phy_ops = priv->phy_ops;
u8 buf[4];
buf[3] = val & 0xff;
@@ -155,7 +314,7 @@
buf[0] = (val >> 8) & 0xff;
dev_dbg(dev, "%s 0x%04x>>0x%04x\n", __func__, reg, val);
- return dm_i2c_write(dev, reg, buf, 4);
+ return phy_ops->write(dev, reg, buf, 4);
}
static inline int ksz_pwrite32(struct udevice *dev, int port, int reg, u32 val)
@@ -276,7 +435,7 @@
struct ksz_mdio_priv *priv = dev_get_priv(dev);
dev_dbg(dev, "%s\n", __func__);
- priv->ksz = dev_get_parent_priv(dev->parent);
+ priv->ksz = dev_get_priv(dev->parent);
return 0;
}
@@ -355,12 +514,12 @@
phy_interface_t interface)
{
struct dsa_pdata *pdata = dev_get_uclass_plat(dev);
+ struct ksz_dsa_priv *priv = dev_get_priv(dev);
u8 data8;
dev_dbg(dev, "%s P%d %s\n", __func__, port + 1,
(port == pdata->cpu_port) ? "cpu" : "");
- struct ksz_dsa_priv *priv = dev_get_priv(dev);
if (port != pdata->cpu_port) {
if (priv->features & NEW_XMII)
/* phy port: config errata and leds */
@@ -503,25 +662,61 @@
return 0;
}
-/*
- * I2C driver
- */
-static int ksz_i2c_probe(struct udevice *dev)
+static void ksz_ops_register(struct udevice *dev, struct ksz_phy_ops *ops)
+{
+ struct ksz_dsa_priv *priv = dev_get_priv(dev);
+
+ priv->phy_ops = ops;
+}
+
+static bool dsa_ksz_check_ops(struct ksz_phy_ops *phy_ops)
+{
+ if (!phy_ops || !phy_ops->read || !phy_ops->write)
+ return false;
+
+ return true;
+}
+
+static int ksz_probe(struct udevice *dev)
{
struct dsa_pdata *pdata = dev_get_uclass_plat(dev);
struct ksz_dsa_priv *priv = dev_get_priv(dev);
+ enum uclass_id parent_id = UCLASS_INVALID;
int i, ret;
u8 data8;
u32 id;
- dev_set_parent_priv(dev, priv);
+ parent_id = device_get_uclass_id(dev_get_parent(dev));
+ switch (parent_id) {
+#if CONFIG_IS_ENABLED(DM_I2C)
+ case UCLASS_I2C: {
+ ksz_ops_register(dev, &phy_i2c_ops);
- ret = i2c_set_chip_offset_len(dev, 2);
- if (ret) {
- printf("i2c_set_chip_offset_len failed: %d\n", ret);
- return ret;
+ ret = i2c_set_chip_offset_len(dev, 2);
+ if (ret) {
+ printf("i2c_set_chip_offset_len failed: %d\n", ret);
+ return ret;
+ }
+ break;
+ }
+#endif
+#if CONFIG_IS_ENABLED(DM_SPI)
+ case UCLASS_SPI: {
+ ksz_ops_register(dev, &phy_spi_ops);
+ break;
+ }
+#endif
+ default:
+ dev_err(dev, "invalid parent bus (%s)\n",
+ uclass_get_name(parent_id));
+ return -EINVAL;
}
+ if (!dsa_ksz_check_ops(priv->phy_ops)) {
+ printf("Driver bug. No bus ops defined\n");
+ return -EINVAL;
+ }
+
/* default config */
priv->dev = dev;
@@ -543,6 +738,9 @@
case 0x00956700:
puts("KSZ9567R: ");
break;
+ case 0x00989600:
+ puts("KSZ9896C: ");
+ break;
case 0x00989700:
puts("KSZ9897S: ");
break;
@@ -573,19 +771,20 @@
return 0;
};
-static const struct udevice_id ksz_i2c_ids[] = {
+static const struct udevice_id ksz_ids[] = {
{ .compatible = "microchip,ksz9897" },
{ .compatible = "microchip,ksz9477" },
{ .compatible = "microchip,ksz9567" },
{ .compatible = "microchip,ksz9893" },
+ { .compatible = "microchip,ksz9896" },
{ }
};
U_BOOT_DRIVER(ksz) = {
.name = "ksz-switch",
.id = UCLASS_DSA,
- .of_match = ksz_i2c_ids,
- .probe = ksz_i2c_probe,
+ .of_match = ksz_ids,
+ .probe = ksz_probe,
.ops = &ksz_dsa_ops,
.priv_auto = sizeof(struct ksz_dsa_priv),
};
diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
index a96430c..4d67203 100644
--- a/drivers/net/phy/motorcomm.c
+++ b/drivers/net/phy/motorcomm.c
@@ -12,6 +12,7 @@
#define PHY_ID_YT8511 0x0000010a
#define PHY_ID_YT8531 0x4f51e91b
+#define PHY_ID_YT8821 0x4f51ea19
#define PHY_ID_MASK GENMASK(31, 0)
/* Extended Register's Address Offset Register */
@@ -102,8 +103,12 @@
#define YTPHY_SPECIFIC_STATUS_REG 0x11
#define YTPHY_DUPLEX_MASK BIT(13)
#define YTPHY_DUPLEX_SHIFT 13
-#define YTPHY_SPEED_MODE_MASK GENMASK(15, 14)
-#define YTPHY_SPEED_MODE_SHIFT 14
+#define YTPHY_SPEED_MASK ((0x3 << 14) | BIT(9))
+#define YTPHY_SPEED_10M ((0x0 << 14))
+#define YTPHY_SPEED_100M ((0x1 << 14))
+#define YTPHY_SPEED_1000M ((0x2 << 14))
+#define YTPHY_SPEED_10G ((0x3 << 14))
+#define YTPHY_SPEED_2500M ((0x0 << 14) | BIT(9))
#define YT8531_EXTREG_SLEEP_CONTROL1_REG 0x27
#define YT8531_ESC1R_SLEEP_SW BIT(15)
@@ -131,6 +136,91 @@
#define TX_CLK_100_INVERTED BIT(4)
#define TX_CLK_1000_INVERTED BIT(5)
+#define YT8821_SDS_EXT_CSR_CTRL_REG 0x23
+#define YT8821_SDS_EXT_CSR_VCO_LDO_EN BIT(15)
+#define YT8821_SDS_EXT_CSR_VCO_BIAS_LPF_EN BIT(8)
+
+#define YT8821_UTP_EXT_PI_CTRL_REG 0x56
+#define YT8821_UTP_EXT_PI_RST_N_FIFO BIT(5)
+#define YT8821_UTP_EXT_PI_TX_CLK_SEL_AFE BIT(4)
+#define YT8821_UTP_EXT_PI_RX_CLK_3_SEL_AFE BIT(3)
+#define YT8821_UTP_EXT_PI_RX_CLK_2_SEL_AFE BIT(2)
+#define YT8821_UTP_EXT_PI_RX_CLK_1_SEL_AFE BIT(1)
+#define YT8821_UTP_EXT_PI_RX_CLK_0_SEL_AFE BIT(0)
+
+#define YT8821_UTP_EXT_VCT_CFG6_CTRL_REG 0x97
+#define YT8821_UTP_EXT_FECHO_AMP_TH_HUGE GENMASK(15, 8)
+
+#define YT8821_UTP_EXT_ECHO_CTRL_REG 0x336
+#define YT8821_UTP_EXT_TRACE_LNG_GAIN_THR_1000 GENMASK(14, 8)
+
+#define YT8821_UTP_EXT_GAIN_CTRL_REG 0x340
+#define YT8821_UTP_EXT_TRACE_MED_GAIN_THR_1000 GENMASK(6, 0)
+
+#define YT8821_UTP_EXT_RPDN_CTRL_REG 0x34E
+#define YT8821_UTP_EXT_RPDN_BP_FFE_LNG_2500 BIT(15)
+#define YT8821_UTP_EXT_RPDN_BP_FFE_SHT_2500 BIT(7)
+#define YT8821_UTP_EXT_RPDN_IPR_SHT_2500 GENMASK(6, 0)
+
+#define YT8821_UTP_EXT_TH_20DB_2500_CTRL_REG 0x36A
+#define YT8821_UTP_EXT_TH_20DB_2500 GENMASK(15, 0)
+
+#define YT8821_UTP_EXT_TRACE_CTRL_REG 0x372
+#define YT8821_UTP_EXT_TRACE_LNG_GAIN_THE_2500 GENMASK(14, 8)
+#define YT8821_UTP_EXT_TRACE_MED_GAIN_THE_2500 GENMASK(6, 0)
+
+#define YT8821_UTP_EXT_ALPHA_IPR_CTRL_REG 0x374
+#define YT8821_UTP_EXT_ALPHA_SHT_2500 GENMASK(14, 8)
+#define YT8821_UTP_EXT_IPR_LNG_2500 GENMASK(6, 0)
+
+#define YT8821_UTP_EXT_PLL_CTRL_REG 0x450
+#define YT8821_UTP_EXT_PLL_SPARE_CFG GENMASK(7, 0)
+
+#define YT8821_UTP_EXT_DAC_IMID_CH_2_3_CTRL_REG 0x466
+#define YT8821_UTP_EXT_DAC_IMID_CH_3_10_ORG GENMASK(14, 8)
+#define YT8821_UTP_EXT_DAC_IMID_CH_2_10_ORG GENMASK(6, 0)
+
+#define YT8821_UTP_EXT_DAC_IMID_CH_0_1_CTRL_REG 0x467
+#define YT8821_UTP_EXT_DAC_IMID_CH_1_10_ORG GENMASK(14, 8)
+#define YT8821_UTP_EXT_DAC_IMID_CH_0_10_ORG GENMASK(6, 0)
+
+#define YT8821_UTP_EXT_DAC_IMSB_CH_2_3_CTRL_REG 0x468
+#define YT8821_UTP_EXT_DAC_IMSB_CH_3_10_ORG GENMASK(14, 8)
+#define YT8821_UTP_EXT_DAC_IMSB_CH_2_10_ORG GENMASK(6, 0)
+
+#define YT8821_UTP_EXT_DAC_IMSB_CH_0_1_CTRL_REG 0x469
+#define YT8821_UTP_EXT_DAC_IMSB_CH_1_10_ORG GENMASK(14, 8)
+#define YT8821_UTP_EXT_DAC_IMSB_CH_0_10_ORG GENMASK(6, 0)
+
+#define YT8821_UTP_EXT_MU_COARSE_FR_CTRL_REG 0x4B3
+#define YT8821_UTP_EXT_MU_COARSE_FR_F_FFE GENMASK(14, 12)
+#define YT8821_UTP_EXT_MU_COARSE_FR_F_FBE GENMASK(10, 8)
+
+#define YT8821_UTP_EXT_MU_FINE_FR_CTRL_REG 0x4B5
+#define YT8821_UTP_EXT_MU_FINE_FR_F_FFE GENMASK(14, 12)
+#define YT8821_UTP_EXT_MU_FINE_FR_F_FBE GENMASK(10, 8)
+
+#define YT8821_UTP_EXT_VGA_LPF1_CAP_CTRL_REG 0x4D2
+#define YT8821_UTP_EXT_VGA_LPF1_CAP_OTHER GENMASK(7, 4)
+#define YT8821_UTP_EXT_VGA_LPF1_CAP_2500 GENMASK(3, 0)
+
+#define YT8821_UTP_EXT_VGA_LPF2_CAP_CTRL_REG 0x4D3
+#define YT8821_UTP_EXT_VGA_LPF2_CAP_OTHER GENMASK(7, 4)
+#define YT8821_UTP_EXT_VGA_LPF2_CAP_2500 GENMASK(3, 0)
+
+#define YT8821_UTP_EXT_TXGE_NFR_FR_THP_CTRL_REG 0x660
+#define YT8821_UTP_EXT_NFR_TX_ABILITY BIT(3)
+
+#define YT8821_CHIP_MODE_FORCE_BX2500 1
+
+/* chip config register */
+#define YTPHY_CCR_MODE_SEL_MASK GENMASK(2, 0)
+
+#define YTPHY_REG_SPACE_SELECT_REG 0xA000
+#define YTPHY_RSSR_SPACE_MASK BIT(1)
+#define YTPHY_RSSR_FIBER_SPACE (0x1 << 1)
+#define YTPHY_RSSR_UTP_SPACE (0x0 << 1)
+
struct ytphy_plat_priv {
u32 rx_delay_ps;
u32 tx_delay_ps;
@@ -295,15 +385,15 @@
if (val < 0)
return val;
- speed_mode = (val & YTPHY_SPEED_MODE_MASK) >> YTPHY_SPEED_MODE_SHIFT;
+ speed_mode = (val & YTPHY_SPEED_MASK);
switch (speed_mode) {
- case 2:
+ case YTPHY_SPEED_1000M:
speed = SPEED_1000;
break;
- case 1:
+ case YTPHY_SPEED_100M:
speed = SPEED_100;
break;
- default:
+ case YTPHY_SPEED_10M:
speed = SPEED_10;
break;
}
@@ -632,6 +722,398 @@
return 0;
}
+static int ytphy_save_page(struct phy_device *phydev)
+{
+ int old_page;
+
+ old_page = ytphy_read_ext(phydev, YTPHY_REG_SPACE_SELECT_REG);
+ if (old_page < 0)
+ return old_page;
+
+ if ((old_page & YTPHY_RSSR_SPACE_MASK) == YTPHY_RSSR_FIBER_SPACE)
+ return YTPHY_RSSR_FIBER_SPACE;
+
+ return YTPHY_RSSR_UTP_SPACE;
+};
+
+static int ytphy_restore_page(struct phy_device *phydev, int page,
+ int ret)
+{
+ int mask = YTPHY_RSSR_SPACE_MASK;
+ int set;
+ int r;
+
+ if ((page & YTPHY_RSSR_SPACE_MASK) == YTPHY_RSSR_FIBER_SPACE)
+ set = YTPHY_RSSR_FIBER_SPACE;
+ else
+ set = YTPHY_RSSR_UTP_SPACE;
+
+ r = ytphy_modify_ext(phydev, YTPHY_REG_SPACE_SELECT_REG, mask,
+ set);
+ if (ret >= 0 && r < 0)
+ ret = r;
+
+ return ret;
+};
+
+static int ytphy_write_ext(struct phy_device *phydev, u16 regnum,
+ u16 val)
+{
+ int ret;
+
+ ret = phy_write(phydev, MDIO_DEVAD_NONE,
+ YTPHY_PAGE_SELECT, regnum);
+ if (ret < 0)
+ return ret;
+
+ return phy_write(phydev, MDIO_DEVAD_NONE, YTPHY_PAGE_DATA, val);
+}
+
+static int yt8821_probe(struct phy_device *phydev)
+{
+ phydev->advertising = PHY_GBIT_FEATURES |
+ SUPPORTED_2500baseX_Full |
+ SUPPORTED_Pause |
+ SUPPORTED_Asym_Pause;
+ phydev->supported = phydev->advertising;
+
+ return 0;
+}
+
+static int yt8821_serdes_init(struct phy_device *phydev)
+{
+ int old_page;
+ u16 mask;
+ u16 set;
+ int ret;
+
+ old_page = ytphy_save_page(phydev);
+ if (old_page < 0)
+ return old_page;
+
+ ret = ytphy_modify_ext(phydev, YTPHY_REG_SPACE_SELECT_REG,
+ YTPHY_RSSR_SPACE_MASK,
+ YTPHY_RSSR_FIBER_SPACE);
+ if (ret < 0)
+ goto err_restore_page;
+
+ ret = phy_modify(phydev, MDIO_DEVAD_NONE, MII_BMCR,
+ BMCR_ANENABLE, 0);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_SDS_EXT_CSR_VCO_LDO_EN |
+ YT8821_SDS_EXT_CSR_VCO_BIAS_LPF_EN;
+ set = YT8821_SDS_EXT_CSR_VCO_LDO_EN;
+ ret = ytphy_modify_ext(phydev, YT8821_SDS_EXT_CSR_CTRL_REG, mask,
+ set);
+
+err_restore_page:
+ return ytphy_restore_page(phydev, old_page, ret);
+}
+
+static int yt8821_utp_init(struct phy_device *phydev)
+{
+ int old_page;
+ u16 mask;
+ u16 save;
+ u16 set;
+ int ret;
+
+ old_page = ytphy_save_page(phydev);
+ if (old_page < 0)
+ return old_page;
+
+ ret = ytphy_modify_ext(phydev, YTPHY_REG_SPACE_SELECT_REG,
+ YTPHY_RSSR_SPACE_MASK,
+ YTPHY_RSSR_UTP_SPACE);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_RPDN_BP_FFE_LNG_2500 |
+ YT8821_UTP_EXT_RPDN_BP_FFE_SHT_2500 |
+ YT8821_UTP_EXT_RPDN_IPR_SHT_2500;
+ set = YT8821_UTP_EXT_RPDN_BP_FFE_LNG_2500 |
+ YT8821_UTP_EXT_RPDN_BP_FFE_SHT_2500;
+ ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_RPDN_CTRL_REG,
+ mask, set);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_VGA_LPF1_CAP_OTHER |
+ YT8821_UTP_EXT_VGA_LPF1_CAP_2500;
+ ret = ytphy_modify_ext(phydev,
+ YT8821_UTP_EXT_VGA_LPF1_CAP_CTRL_REG,
+ mask, 0);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_VGA_LPF2_CAP_OTHER |
+ YT8821_UTP_EXT_VGA_LPF2_CAP_2500;
+ ret = ytphy_modify_ext(phydev,
+ YT8821_UTP_EXT_VGA_LPF2_CAP_CTRL_REG,
+ mask, 0);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_TRACE_LNG_GAIN_THE_2500 |
+ YT8821_UTP_EXT_TRACE_MED_GAIN_THE_2500;
+ set = FIELD_PREP(YT8821_UTP_EXT_TRACE_LNG_GAIN_THE_2500, 0x5a) |
+ FIELD_PREP(YT8821_UTP_EXT_TRACE_MED_GAIN_THE_2500, 0x3c);
+ ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_TRACE_CTRL_REG,
+ mask, set);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_IPR_LNG_2500;
+ set = FIELD_PREP(YT8821_UTP_EXT_IPR_LNG_2500, 0x6c);
+ ret = ytphy_modify_ext(phydev,
+ YT8821_UTP_EXT_ALPHA_IPR_CTRL_REG,
+ mask, set);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_TRACE_LNG_GAIN_THR_1000;
+ set = FIELD_PREP(YT8821_UTP_EXT_TRACE_LNG_GAIN_THR_1000, 0x2a);
+ ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_ECHO_CTRL_REG,
+ mask, set);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_TRACE_MED_GAIN_THR_1000;
+ set = FIELD_PREP(YT8821_UTP_EXT_TRACE_MED_GAIN_THR_1000, 0x22);
+ ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_GAIN_CTRL_REG,
+ mask, set);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_TH_20DB_2500;
+ set = FIELD_PREP(YT8821_UTP_EXT_TH_20DB_2500, 0x8000);
+ ret = ytphy_modify_ext(phydev,
+ YT8821_UTP_EXT_TH_20DB_2500_CTRL_REG,
+ mask, set);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_MU_COARSE_FR_F_FFE |
+ YT8821_UTP_EXT_MU_COARSE_FR_F_FBE;
+ set = FIELD_PREP(YT8821_UTP_EXT_MU_COARSE_FR_F_FFE, 0x7) |
+ FIELD_PREP(YT8821_UTP_EXT_MU_COARSE_FR_F_FBE, 0x7);
+ ret = ytphy_modify_ext(phydev,
+ YT8821_UTP_EXT_MU_COARSE_FR_CTRL_REG,
+ mask, set);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_MU_FINE_FR_F_FFE |
+ YT8821_UTP_EXT_MU_FINE_FR_F_FBE;
+ set = FIELD_PREP(YT8821_UTP_EXT_MU_FINE_FR_F_FFE, 0x2) |
+ FIELD_PREP(YT8821_UTP_EXT_MU_FINE_FR_F_FBE, 0x2);
+ ret = ytphy_modify_ext(phydev,
+ YT8821_UTP_EXT_MU_FINE_FR_CTRL_REG,
+ mask, set);
+ if (ret < 0)
+ goto err_restore_page;
+
+ /* save YT8821_UTP_EXT_PI_CTRL_REG's val for use later */
+ ret = ytphy_read_ext(phydev, YT8821_UTP_EXT_PI_CTRL_REG);
+ if (ret < 0)
+ goto err_restore_page;
+
+ save = ret;
+
+ mask = YT8821_UTP_EXT_PI_TX_CLK_SEL_AFE |
+ YT8821_UTP_EXT_PI_RX_CLK_3_SEL_AFE |
+ YT8821_UTP_EXT_PI_RX_CLK_2_SEL_AFE |
+ YT8821_UTP_EXT_PI_RX_CLK_1_SEL_AFE |
+ YT8821_UTP_EXT_PI_RX_CLK_0_SEL_AFE;
+ ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_PI_CTRL_REG,
+ mask, 0);
+ if (ret < 0)
+ goto err_restore_page;
+
+ /* restore YT8821_UTP_EXT_PI_CTRL_REG's val */
+ ret = ytphy_write_ext(phydev, YT8821_UTP_EXT_PI_CTRL_REG, save);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_FECHO_AMP_TH_HUGE;
+ set = FIELD_PREP(YT8821_UTP_EXT_FECHO_AMP_TH_HUGE, 0x38);
+ ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_VCT_CFG6_CTRL_REG,
+ mask, set);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_NFR_TX_ABILITY;
+ set = YT8821_UTP_EXT_NFR_TX_ABILITY;
+ ret = ytphy_modify_ext(phydev,
+ YT8821_UTP_EXT_TXGE_NFR_FR_THP_CTRL_REG,
+ mask, set);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_PLL_SPARE_CFG;
+ set = FIELD_PREP(YT8821_UTP_EXT_PLL_SPARE_CFG, 0xe9);
+ ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_PLL_CTRL_REG,
+ mask, set);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_DAC_IMID_CH_3_10_ORG |
+ YT8821_UTP_EXT_DAC_IMID_CH_2_10_ORG;
+ set = FIELD_PREP(YT8821_UTP_EXT_DAC_IMID_CH_3_10_ORG, 0x64) |
+ FIELD_PREP(YT8821_UTP_EXT_DAC_IMID_CH_2_10_ORG, 0x64);
+ ret = ytphy_modify_ext(phydev,
+ YT8821_UTP_EXT_DAC_IMID_CH_2_3_CTRL_REG,
+ mask, set);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_DAC_IMID_CH_1_10_ORG |
+ YT8821_UTP_EXT_DAC_IMID_CH_0_10_ORG;
+ set = FIELD_PREP(YT8821_UTP_EXT_DAC_IMID_CH_1_10_ORG, 0x64) |
+ FIELD_PREP(YT8821_UTP_EXT_DAC_IMID_CH_0_10_ORG, 0x64);
+ ret = ytphy_modify_ext(phydev,
+ YT8821_UTP_EXT_DAC_IMID_CH_0_1_CTRL_REG,
+ mask, set);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_DAC_IMSB_CH_3_10_ORG |
+ YT8821_UTP_EXT_DAC_IMSB_CH_2_10_ORG;
+ set = FIELD_PREP(YT8821_UTP_EXT_DAC_IMSB_CH_3_10_ORG, 0x64) |
+ FIELD_PREP(YT8821_UTP_EXT_DAC_IMSB_CH_2_10_ORG, 0x64);
+ ret = ytphy_modify_ext(phydev,
+ YT8821_UTP_EXT_DAC_IMSB_CH_2_3_CTRL_REG,
+ mask, set);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_DAC_IMSB_CH_1_10_ORG |
+ YT8821_UTP_EXT_DAC_IMSB_CH_0_10_ORG;
+ set = FIELD_PREP(YT8821_UTP_EXT_DAC_IMSB_CH_1_10_ORG, 0x64) |
+ FIELD_PREP(YT8821_UTP_EXT_DAC_IMSB_CH_0_10_ORG, 0x64);
+ ret = ytphy_modify_ext(phydev,
+ YT8821_UTP_EXT_DAC_IMSB_CH_0_1_CTRL_REG,
+ mask, set);
+
+err_restore_page:
+ return ytphy_restore_page(phydev, old_page, ret);
+}
+
+static int yt8821_auto_sleep_config(struct phy_device *phydev,
+ bool enable)
+{
+ int old_page;
+ int ret;
+
+ old_page = ytphy_save_page(phydev);
+ if (old_page < 0)
+ return old_page;
+
+ ret = ytphy_modify_ext(phydev, YTPHY_REG_SPACE_SELECT_REG,
+ YTPHY_RSSR_SPACE_MASK,
+ YTPHY_RSSR_UTP_SPACE);
+ if (ret < 0)
+ goto err_restore_page;
+
+ ret = ytphy_modify_ext(phydev,
+ YT8531_EXTREG_SLEEP_CONTROL1_REG,
+ YT8531_ESC1R_SLEEP_SW,
+ enable ? 1 : 0);
+
+err_restore_page:
+ return ytphy_restore_page(phydev, old_page, ret);
+}
+
+static int yt8821_soft_reset(struct phy_device *phydev)
+{
+ return ytphy_modify_ext(phydev, YT8531_CHIP_CONFIG_REG,
+ YT8531_CCR_SW_RST, 0);
+}
+
+static int yt8821_config(struct phy_device *phydev)
+{
+ u8 mode = YT8821_CHIP_MODE_FORCE_BX2500;
+ int ret;
+ u16 set;
+
+ set = FIELD_PREP(YTPHY_CCR_MODE_SEL_MASK, mode);
+ ret = ytphy_modify_ext(phydev,
+ YT8531_CHIP_CONFIG_REG,
+ YTPHY_CCR_MODE_SEL_MASK,
+ set);
+ if (ret < 0)
+ return ret;
+
+ ret = yt8821_serdes_init(phydev);
+ if (ret < 0)
+ return ret;
+
+ ret = yt8821_utp_init(phydev);
+ if (ret < 0)
+ return ret;
+
+ ret = yt8821_auto_sleep_config(phydev, false);
+ if (ret < 0)
+ return ret;
+
+ return yt8821_soft_reset(phydev);
+}
+
+static void yt8821_parse_status(struct phy_device *phydev, int val)
+{
+ int speed_mode;
+ int speed;
+
+ speed_mode = val & YTPHY_SPEED_MASK;
+ switch (speed_mode) {
+ case YTPHY_SPEED_2500M:
+ speed = SPEED_2500;
+ break;
+ case YTPHY_SPEED_1000M:
+ speed = SPEED_1000;
+ break;
+ case YTPHY_SPEED_100M:
+ speed = SPEED_100;
+ break;
+ case YTPHY_SPEED_10M:
+ speed = SPEED_10;
+ break;
+ }
+
+ phydev->speed = speed;
+ phydev->duplex = FIELD_GET(YTPHY_DUPLEX_MASK, val);
+}
+
+static int yt8821_startup(struct phy_device *phydev)
+{
+ u16 val;
+ int ret;
+
+ ret = ytphy_modify_ext(phydev, YTPHY_REG_SPACE_SELECT_REG,
+ YTPHY_RSSR_SPACE_MASK,
+ YTPHY_RSSR_UTP_SPACE);
+ if (ret)
+ return ret;
+
+ ret = genphy_update_link(phydev);
+ if (ret)
+ return ret;
+
+ ret = phy_read(phydev, MDIO_DEVAD_NONE,
+ YTPHY_SPECIFIC_STATUS_REG);
+ if (ret < 0)
+ return ret;
+
+ val = ret;
+
+ if (phydev->link)
+ yt8821_parse_status(phydev, val);
+
+ return 0;
+}
+
U_BOOT_PHY_DRIVER(motorcomm8511) = {
.name = "YT8511 Gigabit Ethernet",
.uid = PHY_ID_YT8511,
@@ -652,3 +1134,14 @@
.startup = &yt8531_startup,
.shutdown = &genphy_shutdown,
};
+
+U_BOOT_PHY_DRIVER(motorcomm8821) = {
+ .name = "YT8821 2.5G Ethernet",
+ .uid = PHY_ID_YT8821,
+ .mask = PHY_ID_MASK,
+ .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS | MDIO_MMD_AN),
+ .probe = &yt8821_probe,
+ .config = &yt8821_config,
+ .startup = &yt8821_startup,
+ .shutdown = &genphy_shutdown,
+};
diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c
index 2e0afad..5f4b1e2 100644
--- a/drivers/net/rtl8139.c
+++ b/drivers/net/rtl8139.c
@@ -433,7 +433,7 @@
int length = 0;
if (inb(priv->ioaddr + RTL_REG_CHIPCMD) & RTL_REG_CHIPCMD_RXBUFEMPTY)
- return 0;
+ return -EAGAIN;
priv->rxstatus = inw(priv->ioaddr + RTL_REG_INTRSTATUS);
/* See below for the rest of the interrupt acknowledges. */
diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c
index f978c64..f089c48 100644
--- a/drivers/pci/pcie_brcmstb.c
+++ b/drivers/pci/pcie_brcmstb.c
@@ -12,6 +12,7 @@
* Copyright (C) 2020 Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
*/
+#include <asm/arch/acpi/bcm2711.h>
#include <errno.h>
#include <dm.h>
#include <dm/ofnode.h>
@@ -21,88 +22,6 @@
#include <linux/log2.h>
#include <linux/iopoll.h>
-/* Offset of the mandatory PCIe capability config registers */
-#define BRCM_PCIE_CAP_REGS 0x00ac
-
-/* The PCIe controller register offsets */
-#define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1 0x0188
-#define VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
-#define VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN 0x0
-
-#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
-#define CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
-
-#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
-#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
-
-#define PCIE_RC_DL_MDIO_ADDR 0x1100
-#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
-#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
-
-#define PCIE_MISC_MISC_CTRL 0x4008
-#define MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
-#define MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
-#define MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
-#define MISC_CTRL_MAX_BURST_SIZE_128 0x0
-#define MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
-
-#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
-#define PCIE_MEM_WIN0_LO(win) \
- PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)
-
-#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
-#define PCIE_MEM_WIN0_HI(win) \
- PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4)
-
-#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
-#define RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
-
-#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
-#define RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
-#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
-
-#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
-#define RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
-
-#define PCIE_MISC_PCIE_STATUS 0x4068
-#define STATUS_PCIE_PORT_MASK 0x80
-#define STATUS_PCIE_PORT_SHIFT 7
-#define STATUS_PCIE_DL_ACTIVE_MASK 0x20
-#define STATUS_PCIE_DL_ACTIVE_SHIFT 5
-#define STATUS_PCIE_PHYLINKUP_MASK 0x10
-#define STATUS_PCIE_PHYLINKUP_SHIFT 4
-
-#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
-#define MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
-#define MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
-#define MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT 12
-#define PCIE_MEM_WIN0_BASE_LIMIT(win) \
- PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4)
-
-#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
-#define MEM_WIN0_BASE_HI_BASE_MASK 0xff
-#define PCIE_MEM_WIN0_BASE_HI(win) \
- PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8)
-
-#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
-#define PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
-#define PCIE_MEM_WIN0_LIMIT_HI(win) \
- PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
-
-#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
-#define PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
-
-#define PCIE_MSI_INTR2_CLR 0x4508
-#define PCIE_MSI_INTR2_MASK_SET 0x4510
-
-#define PCIE_EXT_CFG_DATA 0x8000
-
-#define PCIE_EXT_CFG_INDEX 0x9000
-
-#define PCIE_RGR1_SW_INIT_1 0x9210
-#define RGR1_SW_INIT_1_PERST_MASK 0x1
-#define RGR1_SW_INIT_1_INIT_MASK 0x2
-
/* PCIe parameters */
#define BRCM_NUM_PCIE_OUT_WINS 4
@@ -447,7 +366,7 @@
* This will need to be changed when support for other SoCs is added.
*/
setbits_le32(base + PCIE_RGR1_SW_INIT_1,
- RGR1_SW_INIT_1_INIT_MASK | RGR1_SW_INIT_1_PERST_MASK);
+ PCIE_RGR1_SW_INIT_1_INIT_MASK | PCIE_RGR1_SW_INIT_1_PERST_MASK);
/*
* The delay is a safety precaution to preclude the reset signal
* from looking like a glitch.
@@ -455,7 +374,7 @@
udelay(100);
/* Take the bridge out of reset */
- clrbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_INIT_MASK);
+ clrbits_le32(base + PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_INIT_MASK);
clrbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
@@ -508,7 +427,7 @@
/* Unassert the fundamental reset */
clrbits_le32(pcie->base + PCIE_RGR1_SW_INIT_1,
- RGR1_SW_INIT_1_PERST_MASK);
+ PCIE_RGR1_SW_INIT_1_PERST_MASK);
/*
* Wait for 100ms after PERST# deassertion; see PCIe CEM specification
@@ -552,7 +471,7 @@
* a PCIe-PCIe bridge (the default setting is to be EP mode).
*/
clrsetbits_le32(base + PCIE_RC_CFG_PRIV1_ID_VAL3,
- CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK, 0x060400);
+ PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK, 0x060400);
if (pcie->ssc) {
ret = brcm_pcie_set_ssc(pcie->base);
@@ -570,8 +489,8 @@
nlw, ssc_good ? "(SSC)" : "(!SSC)");
/* PCIe->SCB endian mode for BAR */
- clrsetbits_le32(base + PCIE_RC_CFG_VENDOR_SPECIFIC_REG1,
- VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK,
+ clrsetbits_le32(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1,
+ PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK,
VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN);
/*
@@ -584,7 +503,7 @@
* let's instead just unadvertise ASPM support.
*/
clrbits_le32(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY,
- PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
+ LINK_CAPABILITY_ASPM_SUPPORT_MASK);
return 0;
}
@@ -595,14 +514,14 @@
void __iomem *base = pcie->base;
/* Assert fundamental reset */
- setbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_PERST_MASK);
+ setbits_le32(base + PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_PERST_MASK);
/* Turn off SerDes */
setbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
/* Shutdown bridge */
- setbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_INIT_MASK);
+ setbits_le32(base + PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_INIT_MASK);
return 0;
}
diff --git a/drivers/pinctrl/aspeed/pinctrl_ast2500.c b/drivers/pinctrl/aspeed/pinctrl_ast2500.c
index 9e7c347..5ecd3f2 100644
--- a/drivers/pinctrl/aspeed/pinctrl_ast2500.c
+++ b/drivers/pinctrl/aspeed/pinctrl_ast2500.c
@@ -62,6 +62,7 @@
{ "SD2", 5, (1 << 1) },
{ "FWSPICS1", 3, (1 << 24) },
{ "SPI1CS1", 1, (1 << 15) },
+ { "SGPM", 2, (1 << 11) | (1 << 10) | (1 << 9) | (1 << 8) },
};
static int ast2500_pinctrl_get_groups_count(struct udevice *dev)
diff --git a/drivers/pinctrl/aspeed/pinctrl_ast2600.c b/drivers/pinctrl/aspeed/pinctrl_ast2600.c
index bc12590..f4bec6f 100644
--- a/drivers/pinctrl/aspeed/pinctrl_ast2600.c
+++ b/drivers/pinctrl/aspeed/pinctrl_ast2600.c
@@ -454,6 +454,14 @@
{0x41c, BIT(31), 0},
};
+static struct aspeed_sig_desc sgpm1[] = {
+ {0x414, GENMASK(27, 24), 0},
+};
+
+static struct aspeed_sig_desc sgpm2[] = {
+ {0x6d0, GENMASK(7, 4), 0},
+};
+
static const struct aspeed_group_config ast2600_groups[] = {
{ "MAC1LINK", ARRAY_SIZE(mac1_link), mac1_link },
{ "MAC2LINK", ARRAY_SIZE(mac2_link), mac2_link },
@@ -543,6 +551,8 @@
{ "PWM14G1", ARRAY_SIZE(pwm14g1), pwm14g1 },
{ "PWM15G0", ARRAY_SIZE(pwm15g0), pwm15g0 },
{ "PWM15G1", ARRAY_SIZE(pwm15g1), pwm15g1 },
+ { "SGPM1", ARRAY_SIZE(sgpm1), sgpm1 },
+ { "SGPM2", ARRAY_SIZE(sgpm2), sgpm2 },
};
static int ast2600_pinctrl_get_groups_count(struct udevice *dev)
diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c
index 51cacf3..bcdeda9 100644
--- a/drivers/scsi/scsi.c
+++ b/drivers/scsi/scsi.c
@@ -309,6 +309,7 @@
((unsigned long)pccb->pdata[5] << 16) |
((unsigned long)pccb->pdata[6] << 8) |
((unsigned long)pccb->pdata[7]);
+ *capacity += 1;
return 0;
}
@@ -332,6 +333,7 @@
((uint64_t)pccb->pdata[5] << 16) |
((uint64_t)pccb->pdata[6] << 8) |
((uint64_t)pccb->pdata[7]);
+ *capacity += 1;
*blksz = ((uint64_t)pccb->pdata[8] << 56) |
((uint64_t)pccb->pdata[9] << 48) |
diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index 80c3596..e6bf0c2 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -19,6 +19,7 @@
#include <watchdog.h>
#include <asm/io.h>
#include <serial.h>
+#include <spl.h>
#include <dm/device_compat.h>
#include <dm/platform_data/serial_pl01x.h>
#include <linux/compiler.h>
@@ -272,6 +273,28 @@
return &pl01x_serial_drv;
}
#else
+
+static int pl01x_serial_getinfo(struct udevice *dev,
+ struct serial_device_info *info)
+{
+ struct pl01x_serial_plat *plat = dev_get_plat(dev);
+
+ /* save code size */
+ if (!not_xpl())
+ return -ENOSYS;
+
+ info->type = SERIAL_CHIP_PL01X;
+ info->addr_space = SERIAL_ADDRESS_SPACE_MEMORY;
+ info->addr = plat->base;
+ info->size = 0x1000;
+ info->reg_width = 4;
+ info->reg_shift = 2;
+ info->reg_offset = 0;
+ info->clock = plat->clock;
+
+ return 0;
+}
+
int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
{
struct pl01x_serial_plat *plat = dev_get_plat(dev);
@@ -341,6 +364,7 @@
.pending = pl01x_serial_pending,
.getc = pl01x_serial_getc,
.setbrg = pl01x_serial_setbrg,
+ .getinfo = pl01x_serial_getinfo,
};
#if CONFIG_IS_ENABLED(OF_REAL)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index fa817ec..fd5cb36 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -20,12 +20,6 @@
if SPI
-config SPI_ADVANCE
- bool "Enable the advance feature"
- help
- Enable the SPI advance feature support. By default this is disabled.
- If you intend to use the advance feature support you should enable.
-
config DM_SPI
bool "Enable Driver Model for SPI drivers"
depends on DM
@@ -615,6 +609,12 @@
This option is used to enable ZynqMP QSPI controller driver which
is used to communicate with qspi flash devices.
+config SPI_STACKED_PARALLEL
+ bool "Enable support for stacked or parallel memories"
+ help
+ Enable support for stacked/or parallel memories. This functionality
+ may appear on Xilinx hardware. By default this is disabled.
+
endif # if DM_SPI
config FSL_ESPI
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 6e10b62..bb5893d 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -68,6 +68,14 @@
SoCs, which includes Armada8K, Armada3700 and other Armada
family SoCs.
+config USB_XHCI_GENERIC
+ bool "Generic SoC USB 3.0 support"
+ depends on OF_CONTROL
+ default n
+ help
+ Choose this option to add support for USB 3.0 driver for SoCs
+ that do not need platform specific code, like on emulated targets.
+
config USB_XHCI_OCTEON
bool "Support for Marvell Octeon family on-chip xHCI USB controller"
depends on ARCH_OCTEON
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 792956e..301bb9f 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -50,6 +50,7 @@
obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
obj-$(CONFIG_USB_XHCI_MTK) += xhci-mtk.o
obj-$(CONFIG_USB_XHCI_MVEBU) += xhci-mvebu.o
+obj-$(CONFIG_USB_XHCI_GENERIC) += xhci-generic.o
obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
obj-$(CONFIG_USB_XHCI_RCAR) += xhci-rcar.o
diff --git a/drivers/usb/host/xhci-generic.c b/drivers/usb/host/xhci-generic.c
new file mode 100644
index 0000000..355d488
--- /dev/null
+++ b/drivers/usb/host/xhci-generic.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 9elements GmbH
+ *
+ * GENERIC USB HOST xHCI Controller
+ */
+#include <dm.h>
+#include <fdtdec.h>
+#include <log.h>
+#include <usb.h>
+#include <asm/io.h>
+#include <dm/device_compat.h>
+#include <usb/xhci.h>
+
+struct generic_xhci_plat {
+ fdt_addr_t hcd_base;
+};
+
+/**
+ * Contains pointers to register base addresses
+ * for the usb controller.
+ */
+struct generic_xhci {
+ struct xhci_ctrl ctrl; /* Needs to come first in this struct! */
+ struct usb_plat usb_plat;
+ struct xhci_hccr *hcd;
+};
+
+static int xhci_usb_probe(struct udevice *dev)
+{
+ struct generic_xhci_plat *plat = dev_get_plat(dev);
+ struct generic_xhci *ctx = dev_get_priv(dev);
+ struct xhci_hcor *hcor;
+ int len;
+
+ ctx->hcd = (struct xhci_hccr *)phys_to_virt(plat->hcd_base);
+ len = HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase));
+ hcor = (struct xhci_hcor *)((uintptr_t)ctx->hcd + len);
+
+ return xhci_register(dev, ctx->hcd, hcor);
+}
+
+static int xhci_usb_of_to_plat(struct udevice *dev)
+{
+ struct generic_xhci_plat *plat = dev_get_plat(dev);
+
+ /*
+ * Get the base address for XHCI controller from the device node
+ */
+ plat->hcd_base = dev_read_addr(dev);
+ if (plat->hcd_base == FDT_ADDR_T_NONE) {
+ dev_dbg(dev, "Can't get the XHCI register base address\n");
+ return -ENXIO;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id xhci_usb_ids[] = {
+ { .compatible = "generic-xhci" },
+ { }
+};
+
+U_BOOT_DRIVER(usb_xhci) = {
+ .name = "xhci_generic",
+ .id = UCLASS_USB,
+ .of_match = xhci_usb_ids,
+ .of_to_plat = xhci_usb_of_to_plat,
+ .probe = xhci_usb_probe,
+ .remove = xhci_deregister,
+ .ops = &xhci_usb_ops,
+ .plat_auto = sizeof(struct generic_xhci_plat),
+ .priv_auto = sizeof(struct generic_xhci),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi b/dts/upstream/src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi
index e2584a5..b3c4c0e 100644
--- a/dts/upstream/src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi
@@ -9,11 +9,6 @@
* Common bits of the IOT2050 Basic and Advanced variants, PG2
*/
-&mcu_r5fss0 {
- /* lock-step mode not supported on PG2 boards */
- ti,cluster-mode = <0>;
-};
-
&main_pmx0 {
cp2102n_reset_pin_default: cp2102n-reset-default-pins {
pinctrl-single,pins = <
diff --git a/dts/upstream/src/arm64/ti/k3-am65-iot2050-common.dtsi b/dts/upstream/src/arm64/ti/k3-am65-iot2050-common.dtsi
index ef34b85..e76828c 100644
--- a/dts/upstream/src/arm64/ti/k3-am65-iot2050-common.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am65-iot2050-common.dtsi
@@ -635,3 +635,8 @@
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
+
+&mcu_r5fss0 {
+ /* lock-step mode not supported on iot2050 boards */
+ ti,cluster-mode = <0>;
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am6528-iot2050-basic.dts b/dts/upstream/src/arm64/ti/k3-am6528-iot2050-basic.dts
index 29a3189..4968a47 100644
--- a/dts/upstream/src/arm64/ti/k3-am6528-iot2050-basic.dts
+++ b/dts/upstream/src/arm64/ti/k3-am6528-iot2050-basic.dts
@@ -22,8 +22,3 @@
compatible = "siemens,iot2050-basic", "ti,am654";
model = "SIMATIC IOT2050 Basic";
};
-
-&mcu_r5fss0 {
- /* lock-step mode not supported on this board */
- ti,cluster-mode = <0>;
-};
diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtso b/dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie.dtso
similarity index 91%
rename from arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtso
rename to dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie.dtso
index c9e7360..666237f 100644
--- a/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtso
+++ b/dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie.dtso
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* IOT2050 M.2 variant, overlay for B-key PCIE0_LANE0 + E-key PCIE1_LANE0
- * Copyright (c) Siemens AG, 2022
+ * Copyright (c) Siemens AG, 2022-2024
*
* Authors:
* Chao Zeng <chao.zeng@siemens.com>
diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtso b/dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-m2-bkey-usb3.dtso
similarity index 95%
rename from arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtso
rename to dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-m2-bkey-usb3.dtso
index 72fc011..0f86235 100644
--- a/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtso
+++ b/dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-m2-bkey-usb3.dtso
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* IOT2050 M.2 variant, overlay for B-key USB3.0 + E-key PCIE1_LANE0
- * Copyright (c) Siemens AG, 2022
+ * Copyright (c) Siemens AG, 2022-2024
*
* Authors:
* Chao Zeng <chao.zeng@siemens.com>
diff --git a/dts/upstream/src/riscv/Makefile b/dts/upstream/src/riscv/Makefile
new file mode 100644
index 0000000..980617e
--- /dev/null
+++ b/dts/upstream/src/riscv/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+include $(srctree)/scripts/Makefile.dts
+
+DTC_FLAGS += -R 4 -p 0x1000
+
diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h
index 15fd61a..b8b1f133 100644
--- a/include/acpi/acpi_table.h
+++ b/include/acpi/acpi_table.h
@@ -290,7 +290,8 @@
#define ACPI_MADT_REV_ACPI_3_0 2
#define ACPI_MADT_REV_ACPI_4_0 3
#define ACPI_MADT_REV_ACPI_5_0 3
-#define ACPI_MADT_REV_ACPI_6_0 5
+#define ACPI_MADT_REV_ACPI_6_2 4
+#define ACPI_MADT_REV_ACPI_6_3 5
#define ACPI_MCFG_REV_ACPI_3_0 1
@@ -342,7 +343,10 @@
ACPI_APIC_LX2APIC, /* Processor local x2APIC */
ACPI_APIC_LX2APIC_NMI, /* Local x2APIC NMI */
ACPI_APIC_GICC, /* Generic Interrupt Ctlr CPU i/f */
- ACPI_APIC_GICD /* Generic Interrupt Ctlr Distributor */
+ ACPI_APIC_GICD, /* Generic Interrupt Ctlr Distributor */
+ ACPI_APIC_MSI_FRAME, /* Generic Interrupt MSI Frame */
+ ACPI_APIC_GICR, /* Generic Interrupt Ctlr Redistributor */
+ ACPI_APIC_ITS, /* Interrupt Translation Service */
};
/* MADT: Processor Local APIC Structure */
@@ -386,20 +390,20 @@
u8 lint; /* Local APIC LINT# */
};
-/* flags for acpi_madr_gicc flags word */
+/* flags for acpi_madt_gicc flags word */
enum {
- ACPI_MADRF_ENABLED = BIT(0),
- ACPI_MADRF_PERF = BIT(1),
- ACPI_MADRF_VGIC = BIT(2),
+ ACPI_MADTF_ENABLED = BIT(0),
+ ACPI_MADTF_PERF = BIT(1),
+ ACPI_MADTF_VGIC = BIT(2),
};
/**
- * struct __packed acpi_madr_gicc - GIC CPU interface (type 0xb)
+ * struct __packed acpi_madt_gicc - GIC CPU interface (type 0xb)
*
* This holds information about the Generic Interrupt Controller (GIC) CPU
* interface. See ACPI Spec v6.3 section 5.2.12.14
*/
-struct acpi_madr_gicc {
+struct acpi_madt_gicc {
u8 type;
u8 length;
u16 reserved;
@@ -421,12 +425,12 @@
} __packed;
/**
- * struct __packed acpi_madr_gicc - GIC distributor (type 0xc)
+ * struct __packed acpi_madt_gicc - GIC distributor (type 0xc)
*
* This holds information about the Generic Interrupt Controller (GIC)
* Distributor interface. See ACPI Spec v6.3 section 5.2.12.15
*/
-struct acpi_madr_gicd {
+struct acpi_madt_gicd {
u8 type;
u8 length;
u16 reserved;
@@ -437,6 +441,35 @@
u8 reserved3[3];
} __packed;
+/**
+ * struct __packed acpi_madt_gicr - GIC Redistributor (type 0xe)
+ *
+ * This holds information about the Generic Interrupt Controller (GIC)
+ * Redistributor interface. See ACPI Spec v6.3 section 5.2.12.17
+ */
+struct acpi_madt_gicr {
+ u8 type;
+ u8 length;
+ u16 reserved;
+ u64 discovery_range_base_address;
+ u32 discovery_range_length;
+} __packed;
+
+/**
+ * struct __packed acpi_madt_its - GIC Interrupt Translation Service (type 0xf)
+ *
+ * This holds information about the Interrupt Translation Service (ITS)
+ * Structure. See ACPI Spec v6.3 section 5.2.12.18
+ */
+struct acpi_madt_its {
+ u8 type;
+ u8 length;
+ u16 reserved;
+ u32 gic_its_id;
+ u64 physical_base_address;
+ u32 reserved2;
+} __packed;
+
/* MCFG (PCI Express MMIO config space BAR description table) */
struct acpi_mcfg {
struct acpi_table_header header;
@@ -707,6 +740,8 @@
u32 virt_el2_flags;
} __packed;
+#define GTDT_FLAG_INT_ACTIVE_LOW BIT(1)
+
/**
* struct acpi_bgrt - Boot Graphics Resource Table (BGRT)
*
@@ -797,6 +832,117 @@
u16 line_size;
} __packed;
+/** IORT - IO Remapping Table revision 6
+ * Document number: ARM DEN 0049E.e, Sep 2022
+ */
+struct acpi_table_iort {
+ struct acpi_table_header header;
+ u32 node_count;
+ u32 node_offset;
+ u32 reserved;
+} __packed;
+
+/*
+ * IORT subtables
+ */
+struct acpi_iort_node {
+ u8 type;
+ u16 length;
+ u8 revision;
+ u32 identifier;
+ u32 mapping_count;
+ u32 mapping_offset;
+ char node_data[];
+} __packed;
+
+/* Values for subtable Type above */
+enum acpi_iort_node_type {
+ ACPI_IORT_NODE_ITS_GROUP = 0x00,
+ ACPI_IORT_NODE_NAMED_COMPONENT = 0x01,
+ ACPI_IORT_NODE_PCI_ROOT_COMPLEX = 0x02,
+ ACPI_IORT_NODE_SMMU = 0x03,
+ ACPI_IORT_NODE_SMMU_V3 = 0x04,
+ ACPI_IORT_NODE_PMCG = 0x05,
+ ACPI_IORT_NODE_RMR = 0x06,
+};
+
+/* ITS Group revision 1 */
+struct acpi_iort_its_group {
+ u32 its_count;
+ u32 identifiers[]; /* GIC ITS identifier array */
+} __packed;
+
+/* PCI root complex node revision 2 */
+struct acpi_iort_rc {
+ u64 mem_access_properties;
+ u32 ats_attributes;
+ u32 pci_segment_number;
+ u8 memory_address_size_limit;
+ u8 reserved[3];
+} __packed;
+
+/* SMMUv3 revision 5 */
+struct acpi_iort_smmu_v3 {
+ u64 base_address; /* SMMUv3 base address */
+ u32 flags;
+ u32 reserved;
+ u64 vatos_address;
+ u32 model;
+ u32 event_gsiv;
+ u32 pri_gsiv;
+ u32 gerr_gsiv;
+ u32 sync_gsiv;
+ u32 pxm;
+ u32 id_mapping_index;
+} __packed;
+
+/* Masks for Flags field above */
+#define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE (1)
+#define ACPI_IORT_SMMU_V3_HTTU_OVERRIDE (3 << 1)
+#define ACPI_IORT_SMMU_V3_PXM_VALID (1 << 3)
+#define ACPI_IORT_SMMU_V3_DEVICEID_VALID (1 << 4)
+
+struct acpi_iort_id_mapping {
+ u32 input_base; /* Lowest value in input range */
+ u32 id_count; /* Number of IDs */
+ u32 output_base; /* Lowest value in output range */
+ u32 output_reference; /* A reference to the output node */
+ u32 flags;
+} __packed;
+
+/* Masks for Flags field above for IORT subtable */
+#define ACPI_IORT_ID_SINGLE_MAPPING (1)
+
+/* Named Component revision 4 */
+struct acpi_iort_named_component {
+ u32 node_flags;
+ u64 memory_properties; /* Memory access properties */
+ u8 memory_address_limit; /* Memory address size limit */
+ char device_name[]; /* Path of namespace object */
+} __packed;
+
+/* Masks for Flags field above */
+#define ACPI_IORT_NC_STALL_SUPPORTED (1)
+#define ACPI_IORT_NC_PASID_BITS (31 << 1)
+
+struct acpi_iort_root_complex {
+ u64 memory_properties; /* Memory access properties */
+ u32 ats_attribute;
+ u32 pci_segment_number;
+ u8 memory_address_limit;/* Memory address size limit */
+ u16 pasid_capabilities; /* PASID Capabilities */
+ u8 reserved; /* Reserved, must be zero */
+ u32 flags; /* Flags */
+} __packed;
+
+/* Masks for ats_attribute field above */
+#define ACPI_IORT_ATS_SUPPORTED (1) /* The root complex ATS support */
+#define ACPI_IORT_PRI_SUPPORTED (1 << 1) /* The root complex PRI support */
+#define ACPI_IORT_PASID_FWD_SUPPORTED (1 << 2) /* The root complex PASID forward support */
+
+/* Masks for pasid_capabilities field above */
+#define ACPI_IORT_PASID_MAX_WIDTH (0x1F) /* Bits 0-4 */
+
/* Tables defined/reserved by ACPI and generated by U-Boot */
enum acpi_tables {
ACPITAB_BERT,
@@ -806,12 +952,14 @@
ACPITAB_ECDT,
ACPITAB_FACS,
ACPITAB_FADT,
+ ACPITAB_GTDT,
ACPITAB_HEST,
ACPITAB_HPET,
ACPITAB_IVRS,
ACPITAB_MADT,
ACPITAB_MCFG,
ACPITAB_NHLT,
+ ACPITAB_PPTT,
ACPITAB_RSDP,
ACPITAB_RSDT,
ACPITAB_SLIT,
@@ -847,6 +995,19 @@
int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags);
/**
+ * acpi_create_mcfg_mmconfig() - Create a MCFG table entry
+ *
+ * @mmconfig: Place to put the table
+ * @base: Base address of the ECAM space
+ * @seg_nr: PCI segment number
+ * @start: PCI bus start number
+ * @end: PCI bus end number
+ * Return: size of data written in bytes
+ */
+int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 base,
+ u16 seg_nr, u8 start, u8 end);
+
+/**
* acpi_create_dbg2() - Create a DBG2 table
*
* This table describes how to access the debug UART
@@ -914,6 +1075,17 @@
}
/**
+ * acpi_write_dbg2_pci_uart() - Write out a DBG2 table
+ *
+ * @ctx: Current ACPI context
+ * @dev: Debug UART device to describe
+ * @access_size: Access size for UART (e.g. ACPI_ACCESS_SIZE_DWORD_ACCESS)
+ * Return: 0 if OK, -ve on error
+ */
+int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,
+ uint access_size);
+
+/**
* acpi_write_rsdp() - Write out an RSDP indicating where the ACPI tables are
*
* @rsdp: Address to write RSDP
@@ -944,6 +1116,138 @@
int acpi_fill_csrt(struct acpi_ctx *ctx);
/**
+ * acpi_fill_fadt() - Fill out the body of the FADT
+ *
+ * Must be implemented in SoC specific code or in mainboard code.
+ *
+ * @fadt: Pointer to FADT to update
+ */
+void acpi_fill_fadt(struct acpi_fadt *fadt);
+
+/**
+ * acpi_fill_iort() - Fill out the body of the IORT table
+ *
+ * Should be implemented in SoC specific code.
+ *
+ * @ctx: ACPI context to write to
+ * @offset: Offset from the start of the IORT
+ */
+int acpi_fill_iort(struct acpi_ctx *ctx);
+
+/**
+ * acpi_iort_add_its_group() - Add ITS group node to IORT table
+ *
+ * Called by SoC specific code within acpi_fill_iort().
+ *
+ * @ctx: ACPI context to write to
+ * @its_count: Elements in identifiers
+ * @identifiers: The array of ITS identifiers. These IDs must match the value
+ * used in the Multiple APIC Description Table (MADT) GIC ITS
+ * structure for each relevant ITS unit.
+ * @return Offset of table within parent
+ */
+int acpi_iort_add_its_group(struct acpi_ctx *ctx,
+ const u32 its_count,
+ const u32 *identifiers);
+
+/**
+ * acpi_iort_add_named_component() - Add named component to IORT table
+ *
+ * Called by SoC specific code within acpi_fill_iort().
+ *
+ * @ctx: ACPI context to write to
+ * @node_flags: Node flags
+ * @memory_properties: Memory properties
+ * @memory_address_limit: Memory address limit
+ * @device_name: ACPI device path
+ * @return Offset of table within parent
+ */
+int acpi_iort_add_named_component(struct acpi_ctx *ctx,
+ const u32 node_flags,
+ const u64 memory_properties,
+ const u8 memory_address_limit,
+ const char *device_name);
+
+/**
+ * acpi_iort_add_rc() - Add PCI root complex node to IORT table
+ *
+ * Called by SoC specific code within acpi_fill_iort().
+ *
+ * @ctx: ACPI context to write to
+ * @mem_access_properties: Memory access properties
+ * @ats_attributes: Support for ATS and its ancillary feature
+ * @pci_segment_number: The PCI segment number, as in MCFG
+ * @memory_address_size_limit: The number of address bits, starting from LSB
+ * @num_mappings: Number of elements in map
+ * @map: ID mappings for this node
+ * @return Offset of table within parent
+ */
+int acpi_iort_add_rc(struct acpi_ctx *ctx,
+ const u64 mem_access_properties,
+ const u32 ats_attributes,
+ const u32 pci_segment_number,
+ const u8 memory_address_size_limit,
+ const int num_mappings,
+ const struct acpi_iort_id_mapping *map);
+
+/**
+ * acpi_iort_add_smmu_v3() - Add PCI root complex node to IORT table
+ *
+ * Called by SoC specific code within acpi_fill_iort().
+ *
+ * @ctx: ACPI context to write to
+ * @base_address: Base address of SMMU
+ * @flags: SMMUv3 flags
+ * @vatos_address: Optional, set to zero if not supported
+ * @model: Model ID
+ * @event_gsiv: GSIV of the Event interrupt if SPI based
+ * @pri_gsiv: GSIV of the PRI interrupt if SPI based
+ * @gerr_gsiv: GSIV of the GERR interrupt if GSIV based
+ * @sync_gsiv: TGSIV of the Sync interrupt if GSIV based
+ * @pxm: Proximity Domain
+ * @id_mapping_index: If all the SMMU control interrupts are GSIV based,
+ * this field is ignored. Index into the array of ID
+ * mapping otherwise.
+ * @num_mappings: Number of elements in map
+ * @map: ID mappings for this node
+ * @return Offset of table within parent
+ */
+int acpi_iort_add_smmu_v3(struct acpi_ctx *ctx,
+ const u64 base_address,
+ const u32 flags,
+ const u64 vatos_address,
+ const u32 model,
+ const u32 event_gsiv,
+ const u32 pri_gsiv,
+ const u32 gerr_gsiv,
+ const u32 sync_gsiv,
+ const u32 pxm,
+ const u32 id_mapping_index,
+ const int num_mappings,
+ const struct acpi_iort_id_mapping *map);
+
+/**
+ * acpi_fill_madt() - Fill out the body of the MADT
+ *
+ * Must be implemented in SoC specific code.
+ *
+ * @madt: The MADT to update
+ * @ctx: ACPI context to write MADT sub-tables to
+ * @return Pointer to the end of tables, where the next tables can be written
+ */
+void *acpi_fill_madt(struct acpi_madt *madt, struct acpi_ctx *ctx);
+
+/**
+ * acpi_write_park() - Installs the ACPI parking protocol.
+ *
+ * Sets up the ACPI parking protocol and installs the spinning code for
+ * secondary CPUs.
+ *
+ * @madt: The MADT to update
+ */
+void acpi_write_park(struct acpi_madt *madt);
+
+/**
* acpi_get_rsdp_addr() - get ACPI RSDP table address
*
* This routine returns the ACPI RSDP table address in the system memory.
diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h
index 3aa94d7..16df85b 100644
--- a/include/acpi/acpigen.h
+++ b/include/acpi/acpigen.h
@@ -833,6 +833,7 @@
*
* This emits a Processor package header with the required information. The
* caller must complete the information and call acpigen_pop_len() at the end
+ * Deprecated since ACPI 6.0.
*
* @ctx: ACPI context pointer
* @cpuindex: CPU number
@@ -843,6 +844,17 @@
u32 pblock_addr, uint pblock_len);
/**
+ * acpigen_write_processor_device() - Write a Processor device
+ *
+ * Write a device with _HID ACPI0007 identifying a processor.
+ * Replacement for the Processor OpCode.
+ *
+ * @ctx: ACPI context pointer
+ * @cpuindex: CPU number
+ */
+void acpigen_write_processor_device(struct acpi_ctx *ctx, uint cpuindex);
+
+/**
* acpigen_write_processor_package() - Write a package containing the processors
*
* The package containins the name of each processor in the SoC
diff --git a/include/bloblist.h b/include/bloblist.h
index b0706b5..ff32d3f 100644
--- a/include/bloblist.h
+++ b/include/bloblist.h
@@ -110,6 +110,7 @@
BLOBLISTT_ACPI_TABLES = 4,
BLOBLISTT_TPM_EVLOG = 5,
BLOBLISTT_TPM_CRB_BASE = 6,
+ BLOBLISTT_ACPI_PP = 7,
/* Standard area to allocate blobs used across firmware components */
BLOBLISTT_AREA_FIRMWARE = 0x10,
diff --git a/include/configs/imx8mp_navqp.h b/include/configs/imx8mp_navqp.h
new file mode 100644
index 0000000..802438a
--- /dev/null
+++ b/include/configs/imx8mp_navqp.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ * Copyright 2024 Gilles Talis <gilles.talis@gmail.com>
+ */
+
+#ifndef __IMX8MP_NAVQP_H
+#define __IMX8MP_NAVQP_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 2)
+
+#include <config_distro_bootcmd.h>
+
+/* Initial environment variables */
+#define CFG_EXTRA_ENV_SETTINGS \
+ BOOTENV
+
+/* Link Definitions */
+
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x80000
+
+/* 8GB DDR */
+#define CFG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM 0x40000000
+#define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */
+#define PHYS_SDRAM_2 0x100000000
+#define PHYS_SDRAM_2_SIZE 0x140000000 /* 5 GB */
+
+#endif
diff --git a/include/configs/iot2050.h b/include/configs/iot2050.h
index 94a9c76..5c58c7b 100644
--- a/include/configs/iot2050.h
+++ b/include/configs/iot2050.h
@@ -24,6 +24,9 @@
func(USB, usb, 2)
#endif
+/* DDR Configuration */
+#define CFG_SYS_SDRAM_BASE1 0x880000000
+
/*
* This defines all MMC devices, even if the basic variant has no mmc1.
* The non-supported device will be removed from the boot targets during
@@ -39,7 +42,7 @@
#define CFG_ENV_FLAGS_LIST_STATIC \
"board_uuid:sw,board_name:sw,board_serial:sw,board_a5e:sw," \
"mlfb:sw,fw_version:sw,seboot_version:sw," \
- "m2_manuel_config:sw," \
+ "m2_manual_config:sw," \
"eth1addr:mw,eth2addr:mw,watchdog_timeout_ms:dw,boot_targets:sw"
#endif
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
index 2f594bf..cf4fcb9 100644
--- a/include/configs/qemu-riscv.h
+++ b/include/configs/qemu-riscv.h
@@ -22,6 +22,7 @@
"stderr=serial,vidconsole\0"
#define BOOT_TARGET_DEVICES(func) \
+ func(NVME, nvme, 0) \
func(VIRTIO, virtio, 0) \
func(VIRTIO, virtio, 1) \
func(SCSI, scsi, 0) \
diff --git a/include/configs/qemu-sbsa.h b/include/configs/qemu-sbsa.h
new file mode 100644
index 0000000..aff7816
--- /dev/null
+++ b/include/configs/qemu-sbsa.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2024 9elements GmbH
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Physical memory map */
+
+/* SECURE_FLASH */
+#define SBSA_SECURE_FLASH_BASE_ADDR 0x00000000
+#define SBSA_SECURE_FLASH_LENGTH 0x10000000
+
+/* FLASH */
+#define SBSA_FLASH_BASE_ADDR 0x10000000
+#define SBSA_FLASH_LENGTH 0x10000000
+
+/* PERIPH */
+#define SBSA_PERIPH_BASE_ADDR 0x40000000
+
+/* GIC_DIST */
+#define SBSA_GIC_DIST_BASE_ADDR 0x40060000
+#define SBSA_GIC_DIST_LENGTH 0x00020000
+
+#define SBSA_GIC_VBASE_ADDR 0x2c020000
+#define SBSA_GIC_VBASE_LENGTH 0x00010000
+
+#define SBSA_GIC_HBASE_ADDR 0x2c010000
+#define SBSA_GIC_HBASE_LENGTH 0x00010000
+
+/* GIC_REDIST */
+#define SBSA_GIC_REDIST_BASE_ADDR 0x40080000
+#define SBSA_GIC_REDIST_LENGTH 0x04000000
+
+/* GIC_ITS */
+#define SBSA_GIC_ITS_BASE_ADDR 0x44081000
+
+/* UART */
+#define SBSA_UART_BASE_ADDR 0x60000000
+#define SBSA_UART_LENGTH 0x00001000
+
+/* SMMU */
+#define SBSA_SMMU_BASE_ADDR 0x60050000
+
+/* SATA */
+#define SBSA_AHCI_BASE_ADDR 0x60100000
+#define SBSA_AHCI_LENGTH 0x00010000
+
+/* xHCI */
+#define SBSA_XHCI_BASE_ADDR 0x60110000
+#define SBSA_XHCI_LENGTH 0x00010000
+
+/* PIO */
+#define SBSA_PIO_BASE_ADDR 0x7fff0000
+#define SBSA_PIO_LENGTH 0x00010000
+
+/* PCIE_MMIO */
+#define SBSA_PCIE_MMIO_BASE_ADDR 0x80000000
+#define SBSA_PCIE_MMIO_LENGTH 0x70000000
+#define SBSA_PCIE_MMIO_END 0xefffffff
+
+/* PCIE_ECAM */
+#define SBSA_PCIE_ECAM_BASE_ADDR 0xf0000000
+#define SBSA_PCIE_ECAM_LENGTH 0x10000000
+#define SBSA_PCIE_ECAM_END 0xffffffff
+
+/* PCIE_MMIO_HIGH */
+#ifdef __ACPI__
+#define SBSA_PCIE_MMIO_HIGH_BASE_ADDR 0x100000000
+#define SBSA_PCIE_MMIO_HIGH_LENGTH 0xFF00000000
+#define SBSA_PCIE_MMIO_HIGH_END 0xFFFFFFFFFF
+#else
+#define SBSA_PCIE_MMIO_HIGH_BASE_ADDR 0x100000000ULL
+#define SBSA_PCIE_MMIO_HIGH_LENGTH 0xFF00000000ULL
+#define SBSA_PCIE_MMIO_HIGH_END 0xFFFFFFFFFFULL
+#endif
+
+/* MEM */
+#ifdef __ACPI__
+#define SBSA_MEM_BASE_ADDR 0x10000000000
+#else
+#define SBSA_MEM_BASE_ADDR 0x10000000000ULL
+#endif
+
+#define CFG_SYS_INIT_RAM_ADDR SBSA_MEM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE 0x1000000
+
+#endif /* __CONFIG_H */
diff --git a/include/cpu_func.h b/include/cpu_func.h
index 45e8a0a..7e81c43 100644
--- a/include/cpu_func.h
+++ b/include/cpu_func.h
@@ -69,6 +69,20 @@
void invalidate_dcache_range(unsigned long start, unsigned long stop);
void invalidate_dcache_all(void);
void invalidate_icache_all(void);
+/**
+ * noncached_init() - Initialize non-cached memory region
+ *
+ * Initialize non-cached memory area. This memory region will be typically
+ * located right below the malloc() area and mapped uncached in the MMU.
+ *
+ * It is called during the generic post-relocation init sequence.
+ *
+ * Return: 0 if OK
+ */
+int noncached_init(void);
+void noncached_set_region(void);
+
+phys_addr_t noncached_alloc(size_t size, size_t align);
enum {
/* Disable caches (else flush caches but leave them active) */
diff --git a/include/dm/acpi.h b/include/dm/acpi.h
index 3adfe21..d6bc0c0 100644
--- a/include/dm/acpi.h
+++ b/include/dm/acpi.h
@@ -147,6 +147,22 @@
int (*write_tables)(const struct udevice *dev, struct acpi_ctx *ctx);
/**
+ * fill_madt() - Generate MADT sub-tables for a device
+ *
+ * This is called to create the MADT table. The method should write out
+ * whatever sub-table is needed by this device. It will end up in the
+ * MADT table.
+ *
+ * Note that this is called 'fill' because the entire contents of the
+ * MADT is build by calling this method on all devices.
+ *
+ * @dev: Device to write
+ * @ctx: ACPI context to use
+ * @return 0 if OK, -ve on error
+ */
+ int (*fill_madt)(const struct udevice *dev, struct acpi_ctx *ctx);
+
+ /**
* fill_ssdt() - Generate SSDT code for a device
*
* This is called to create the SSDT code. The method should write out
@@ -232,6 +248,16 @@
int acpi_write_dev_tables(struct acpi_ctx *ctx);
/**
+ * acpi_fill_madt_subtbl() - Generate ACPI tables for MADT
+ *
+ * This is called to create the MADT sub-tables for all devices.
+ *
+ * @ctx: ACPI context to use
+ * Return: 0 if OK, -ve on error
+ */
+int acpi_fill_madt_subtbl(struct acpi_ctx *ctx);
+
+/**
* acpi_fill_ssdt() - Generate ACPI tables for SSDT
*
* This is called to create the SSDT code for all devices.
diff --git a/include/dt-bindings/clock/r8a774a1-cpg-mssr.h b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h
deleted file mode 100644
index e355363..0000000
--- a/include/dt-bindings/clock/r8a774a1-cpg-mssr.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2018 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a774a1 CPG Core Clocks */
-#define R8A774A1_CLK_Z 0
-#define R8A774A1_CLK_Z2 1
-#define R8A774A1_CLK_ZG 2
-#define R8A774A1_CLK_ZTR 3
-#define R8A774A1_CLK_ZTRD2 4
-#define R8A774A1_CLK_ZT 5
-#define R8A774A1_CLK_ZX 6
-#define R8A774A1_CLK_S0D1 7
-#define R8A774A1_CLK_S0D2 8
-#define R8A774A1_CLK_S0D3 9
-#define R8A774A1_CLK_S0D4 10
-#define R8A774A1_CLK_S0D6 11
-#define R8A774A1_CLK_S0D8 12
-#define R8A774A1_CLK_S0D12 13
-#define R8A774A1_CLK_S1D2 14
-#define R8A774A1_CLK_S1D4 15
-#define R8A774A1_CLK_S2D1 16
-#define R8A774A1_CLK_S2D2 17
-#define R8A774A1_CLK_S2D4 18
-#define R8A774A1_CLK_S3D1 19
-#define R8A774A1_CLK_S3D2 20
-#define R8A774A1_CLK_S3D4 21
-#define R8A774A1_CLK_LB 22
-#define R8A774A1_CLK_CL 23
-#define R8A774A1_CLK_ZB3 24
-#define R8A774A1_CLK_ZB3D2 25
-#define R8A774A1_CLK_ZB3D4 26
-#define R8A774A1_CLK_CR 27
-#define R8A774A1_CLK_CRD2 28
-#define R8A774A1_CLK_SD0H 29
-#define R8A774A1_CLK_SD0 30
-#define R8A774A1_CLK_SD1H 31
-#define R8A774A1_CLK_SD1 32
-#define R8A774A1_CLK_SD2H 33
-#define R8A774A1_CLK_SD2 34
-#define R8A774A1_CLK_SD3H 35
-#define R8A774A1_CLK_SD3 36
-#define R8A774A1_CLK_RPC 37
-#define R8A774A1_CLK_RPCD2 38
-#define R8A774A1_CLK_MSO 39
-#define R8A774A1_CLK_HDMI 40
-#define R8A774A1_CLK_CSI0 41
-#define R8A774A1_CLK_CP 42
-#define R8A774A1_CLK_CPEX 43
-#define R8A774A1_CLK_R 44
-#define R8A774A1_CLK_OSC 45
-#define R8A774A1_CLK_CANFD 46
-
-#endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a774b1-cpg-mssr.h b/include/dt-bindings/clock/r8a774b1-cpg-mssr.h
deleted file mode 100644
index 1355451..0000000
--- a/include/dt-bindings/clock/r8a774b1-cpg-mssr.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2019 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a774b1 CPG Core Clocks */
-#define R8A774B1_CLK_Z 0
-#define R8A774B1_CLK_ZG 1
-#define R8A774B1_CLK_ZTR 2
-#define R8A774B1_CLK_ZTRD2 3
-#define R8A774B1_CLK_ZT 4
-#define R8A774B1_CLK_ZX 5
-#define R8A774B1_CLK_S0D1 6
-#define R8A774B1_CLK_S0D2 7
-#define R8A774B1_CLK_S0D3 8
-#define R8A774B1_CLK_S0D4 9
-#define R8A774B1_CLK_S0D6 10
-#define R8A774B1_CLK_S0D8 11
-#define R8A774B1_CLK_S0D12 12
-#define R8A774B1_CLK_S1D2 13
-#define R8A774B1_CLK_S1D4 14
-#define R8A774B1_CLK_S2D1 15
-#define R8A774B1_CLK_S2D2 16
-#define R8A774B1_CLK_S2D4 17
-#define R8A774B1_CLK_S3D1 18
-#define R8A774B1_CLK_S3D2 19
-#define R8A774B1_CLK_S3D4 20
-#define R8A774B1_CLK_LB 21
-#define R8A774B1_CLK_CL 22
-#define R8A774B1_CLK_ZB3 23
-#define R8A774B1_CLK_ZB3D2 24
-#define R8A774B1_CLK_CR 25
-#define R8A774B1_CLK_DDR 26
-#define R8A774B1_CLK_SD0H 27
-#define R8A774B1_CLK_SD0 28
-#define R8A774B1_CLK_SD1H 29
-#define R8A774B1_CLK_SD1 30
-#define R8A774B1_CLK_SD2H 31
-#define R8A774B1_CLK_SD2 32
-#define R8A774B1_CLK_SD3H 33
-#define R8A774B1_CLK_SD3 34
-#define R8A774B1_CLK_RPC 35
-#define R8A774B1_CLK_RPCD2 36
-#define R8A774B1_CLK_MSO 37
-#define R8A774B1_CLK_HDMI 38
-#define R8A774B1_CLK_CSI0 39
-#define R8A774B1_CLK_CP 40
-#define R8A774B1_CLK_CPEX 41
-#define R8A774B1_CLK_R 42
-#define R8A774B1_CLK_OSC 43
-#define R8A774B1_CLK_CANFD 44
-
-#endif /* __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a774c0-cpg-mssr.h b/include/dt-bindings/clock/r8a774c0-cpg-mssr.h
deleted file mode 100644
index 8ad9cd6..0000000
--- a/include/dt-bindings/clock/r8a774c0-cpg-mssr.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a774c0 CPG Core Clocks */
-#define R8A774C0_CLK_Z2 0
-#define R8A774C0_CLK_ZG 1
-#define R8A774C0_CLK_ZTR 2
-#define R8A774C0_CLK_ZT 3
-#define R8A774C0_CLK_ZX 4
-#define R8A774C0_CLK_S0D1 5
-#define R8A774C0_CLK_S0D3 6
-#define R8A774C0_CLK_S0D6 7
-#define R8A774C0_CLK_S0D12 8
-#define R8A774C0_CLK_S0D24 9
-#define R8A774C0_CLK_S1D1 10
-#define R8A774C0_CLK_S1D2 11
-#define R8A774C0_CLK_S1D4 12
-#define R8A774C0_CLK_S2D1 13
-#define R8A774C0_CLK_S2D2 14
-#define R8A774C0_CLK_S2D4 15
-#define R8A774C0_CLK_S3D1 16
-#define R8A774C0_CLK_S3D2 17
-#define R8A774C0_CLK_S3D4 18
-#define R8A774C0_CLK_S0D6C 19
-#define R8A774C0_CLK_S3D1C 20
-#define R8A774C0_CLK_S3D2C 21
-#define R8A774C0_CLK_S3D4C 22
-#define R8A774C0_CLK_LB 23
-#define R8A774C0_CLK_CL 24
-#define R8A774C0_CLK_ZB3 25
-#define R8A774C0_CLK_ZB3D2 26
-#define R8A774C0_CLK_CR 27
-#define R8A774C0_CLK_CRD2 28
-#define R8A774C0_CLK_SD0H 29
-#define R8A774C0_CLK_SD0 30
-#define R8A774C0_CLK_SD1H 31
-#define R8A774C0_CLK_SD1 32
-#define R8A774C0_CLK_SD3H 33
-#define R8A774C0_CLK_SD3 34
-#define R8A774C0_CLK_RPC 35
-#define R8A774C0_CLK_RPCD2 36
-#define R8A774C0_CLK_ZA2 37
-#define R8A774C0_CLK_ZA8 38
-#define R8A774C0_CLK_Z2D 39
-#define R8A774C0_CLK_MSO 40
-#define R8A774C0_CLK_R 41
-#define R8A774C0_CLK_OSC 42
-#define R8A774C0_CLK_LV0 43
-#define R8A774C0_CLK_LV1 44
-#define R8A774C0_CLK_CSI0 45
-#define R8A774C0_CLK_CP 46
-#define R8A774C0_CLK_CPEX 47
-#define R8A774C0_CLK_CANFD 48
-
-#endif /* __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a774e1-cpg-mssr.h b/include/dt-bindings/clock/r8a774e1-cpg-mssr.h
deleted file mode 100644
index b2fc1d1..0000000
--- a/include/dt-bindings/clock/r8a774e1-cpg-mssr.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2020 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* R8A774E1 CPG Core Clocks */
-#define R8A774E1_CLK_Z 0
-#define R8A774E1_CLK_Z2 1
-#define R8A774E1_CLK_ZG 2
-#define R8A774E1_CLK_ZTR 3
-#define R8A774E1_CLK_ZTRD2 4
-#define R8A774E1_CLK_ZT 5
-#define R8A774E1_CLK_ZX 6
-#define R8A774E1_CLK_S0D1 7
-#define R8A774E1_CLK_S0D2 8
-#define R8A774E1_CLK_S0D3 9
-#define R8A774E1_CLK_S0D4 10
-#define R8A774E1_CLK_S0D6 11
-#define R8A774E1_CLK_S0D8 12
-#define R8A774E1_CLK_S0D12 13
-#define R8A774E1_CLK_S1D2 14
-#define R8A774E1_CLK_S1D4 15
-#define R8A774E1_CLK_S2D1 16
-#define R8A774E1_CLK_S2D2 17
-#define R8A774E1_CLK_S2D4 18
-#define R8A774E1_CLK_S3D1 19
-#define R8A774E1_CLK_S3D2 20
-#define R8A774E1_CLK_S3D4 21
-#define R8A774E1_CLK_LB 22
-#define R8A774E1_CLK_CL 23
-#define R8A774E1_CLK_ZB3 24
-#define R8A774E1_CLK_ZB3D2 25
-#define R8A774E1_CLK_ZB3D4 26
-#define R8A774E1_CLK_CR 27
-#define R8A774E1_CLK_CRD2 28
-#define R8A774E1_CLK_SD0H 29
-#define R8A774E1_CLK_SD0 30
-#define R8A774E1_CLK_SD1H 31
-#define R8A774E1_CLK_SD1 32
-#define R8A774E1_CLK_SD2H 33
-#define R8A774E1_CLK_SD2 34
-#define R8A774E1_CLK_SD3H 35
-#define R8A774E1_CLK_SD3 36
-#define R8A774E1_CLK_RPC 37
-#define R8A774E1_CLK_RPCD2 38
-#define R8A774E1_CLK_MSO 39
-#define R8A774E1_CLK_HDMI 40
-#define R8A774E1_CLK_CSI0 41
-#define R8A774E1_CLK_CP 42
-#define R8A774E1_CLK_CPEX 43
-#define R8A774E1_CLK_R 44
-#define R8A774E1_CLK_OSC 45
-#define R8A774E1_CLK_CANFD 46
-
-#endif /* __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a7790-cpg-mssr.h b/include/dt-bindings/clock/r8a7790-cpg-mssr.h
deleted file mode 100644
index c5955b5..0000000
--- a/include/dt-bindings/clock/r8a7790-cpg-mssr.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2015 Renesas Electronics Corp.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a7790 CPG Core Clocks */
-#define R8A7790_CLK_Z 0
-#define R8A7790_CLK_Z2 1
-#define R8A7790_CLK_ZG 2
-#define R8A7790_CLK_ZTR 3
-#define R8A7790_CLK_ZTRD2 4
-#define R8A7790_CLK_ZT 5
-#define R8A7790_CLK_ZX 6
-#define R8A7790_CLK_ZS 7
-#define R8A7790_CLK_HP 8
-#define R8A7790_CLK_I 9
-#define R8A7790_CLK_B 10
-#define R8A7790_CLK_LB 11
-#define R8A7790_CLK_P 12
-#define R8A7790_CLK_CL 13
-#define R8A7790_CLK_M2 14
-#define R8A7790_CLK_ADSP 15
-#define R8A7790_CLK_IMP 16
-#define R8A7790_CLK_ZB3 17
-#define R8A7790_CLK_ZB3D2 18
-#define R8A7790_CLK_DDR 19
-#define R8A7790_CLK_SDH 20
-#define R8A7790_CLK_SD0 21
-#define R8A7790_CLK_SD1 22
-#define R8A7790_CLK_SD2 23
-#define R8A7790_CLK_SD3 24
-#define R8A7790_CLK_MMC0 25
-#define R8A7790_CLK_MMC1 26
-#define R8A7790_CLK_MP 27
-#define R8A7790_CLK_SSP 28
-#define R8A7790_CLK_SSPRS 29
-#define R8A7790_CLK_QSPI 30
-#define R8A7790_CLK_CP 31
-#define R8A7790_CLK_RCAN 32
-#define R8A7790_CLK_R 33
-#define R8A7790_CLK_OSC 34
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a7791-cpg-mssr.h b/include/dt-bindings/clock/r8a7791-cpg-mssr.h
deleted file mode 100644
index aadd06c..0000000
--- a/include/dt-bindings/clock/r8a7791-cpg-mssr.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2015 Renesas Electronics Corp.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a7791 CPG Core Clocks */
-#define R8A7791_CLK_Z 0
-#define R8A7791_CLK_ZG 1
-#define R8A7791_CLK_ZTR 2
-#define R8A7791_CLK_ZTRD2 3
-#define R8A7791_CLK_ZT 4
-#define R8A7791_CLK_ZX 5
-#define R8A7791_CLK_ZS 6
-#define R8A7791_CLK_HP 7
-#define R8A7791_CLK_I 8
-#define R8A7791_CLK_B 9
-#define R8A7791_CLK_LB 10
-#define R8A7791_CLK_P 11
-#define R8A7791_CLK_CL 12
-#define R8A7791_CLK_M2 13
-#define R8A7791_CLK_ADSP 14
-#define R8A7791_CLK_ZB3 15
-#define R8A7791_CLK_ZB3D2 16
-#define R8A7791_CLK_DDR 17
-#define R8A7791_CLK_SDH 18
-#define R8A7791_CLK_SD0 19
-#define R8A7791_CLK_SD2 20
-#define R8A7791_CLK_SD3 21
-#define R8A7791_CLK_MMC0 22
-#define R8A7791_CLK_MP 23
-#define R8A7791_CLK_SSP 24
-#define R8A7791_CLK_SSPRS 25
-#define R8A7791_CLK_QSPI 26
-#define R8A7791_CLK_CP 27
-#define R8A7791_CLK_RCAN 28
-#define R8A7791_CLK_R 29
-#define R8A7791_CLK_OSC 30
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a7792-cpg-mssr.h b/include/dt-bindings/clock/r8a7792-cpg-mssr.h
deleted file mode 100644
index 829c44d..0000000
--- a/include/dt-bindings/clock/r8a7792-cpg-mssr.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2015 Renesas Electronics Corp.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a7792 CPG Core Clocks */
-#define R8A7792_CLK_Z 0
-#define R8A7792_CLK_ZG 1
-#define R8A7792_CLK_ZTR 2
-#define R8A7792_CLK_ZTRD2 3
-#define R8A7792_CLK_ZT 4
-#define R8A7792_CLK_ZX 5
-#define R8A7792_CLK_ZS 6
-#define R8A7792_CLK_HP 7
-#define R8A7792_CLK_I 8
-#define R8A7792_CLK_B 9
-#define R8A7792_CLK_LB 10
-#define R8A7792_CLK_P 11
-#define R8A7792_CLK_CL 12
-#define R8A7792_CLK_M2 13
-#define R8A7792_CLK_IMP 14
-#define R8A7792_CLK_ZB3 15
-#define R8A7792_CLK_ZB3D2 16
-#define R8A7792_CLK_DDR 17
-#define R8A7792_CLK_SD 18
-#define R8A7792_CLK_MP 19
-#define R8A7792_CLK_QSPI 20
-#define R8A7792_CLK_CP 21
-#define R8A7792_CLK_CPEX 22
-#define R8A7792_CLK_RCAN 23
-#define R8A7792_CLK_R 24
-#define R8A7792_CLK_OSC 25
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a7793-cpg-mssr.h b/include/dt-bindings/clock/r8a7793-cpg-mssr.h
deleted file mode 100644
index d1ff646..0000000
--- a/include/dt-bindings/clock/r8a7793-cpg-mssr.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2015 Renesas Electronics Corp.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a7793 CPG Core Clocks */
-#define R8A7793_CLK_Z 0
-#define R8A7793_CLK_ZG 1
-#define R8A7793_CLK_ZTR 2
-#define R8A7793_CLK_ZTRD2 3
-#define R8A7793_CLK_ZT 4
-#define R8A7793_CLK_ZX 5
-#define R8A7793_CLK_ZS 6
-#define R8A7793_CLK_HP 7
-#define R8A7793_CLK_I 8
-#define R8A7793_CLK_B 9
-#define R8A7793_CLK_LB 10
-#define R8A7793_CLK_P 11
-#define R8A7793_CLK_CL 12
-#define R8A7793_CLK_M2 13
-#define R8A7793_CLK_ADSP 14
-#define R8A7793_CLK_ZB3 15
-#define R8A7793_CLK_ZB3D2 16
-#define R8A7793_CLK_DDR 17
-#define R8A7793_CLK_SDH 18
-#define R8A7793_CLK_SD0 19
-#define R8A7793_CLK_SD2 20
-#define R8A7793_CLK_SD3 21
-#define R8A7793_CLK_MMC0 22
-#define R8A7793_CLK_MP 23
-#define R8A7793_CLK_SSP 24
-#define R8A7793_CLK_SSPRS 25
-#define R8A7793_CLK_QSPI 26
-#define R8A7793_CLK_CP 27
-#define R8A7793_CLK_RCAN 28
-#define R8A7793_CLK_R 29
-#define R8A7793_CLK_OSC 30
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a7794-cpg-mssr.h b/include/dt-bindings/clock/r8a7794-cpg-mssr.h
deleted file mode 100644
index 6314e23..0000000
--- a/include/dt-bindings/clock/r8a7794-cpg-mssr.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2015 Renesas Electronics Corp.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a7794 CPG Core Clocks */
-#define R8A7794_CLK_Z2 0
-#define R8A7794_CLK_ZG 1
-#define R8A7794_CLK_ZTR 2
-#define R8A7794_CLK_ZTRD2 3
-#define R8A7794_CLK_ZT 4
-#define R8A7794_CLK_ZX 5
-#define R8A7794_CLK_ZS 6
-#define R8A7794_CLK_HP 7
-#define R8A7794_CLK_I 8
-#define R8A7794_CLK_B 9
-#define R8A7794_CLK_LB 10
-#define R8A7794_CLK_P 11
-#define R8A7794_CLK_CL 12
-#define R8A7794_CLK_CP 13
-#define R8A7794_CLK_M2 14
-#define R8A7794_CLK_ADSP 15
-#define R8A7794_CLK_ZB3 16
-#define R8A7794_CLK_ZB3D2 17
-#define R8A7794_CLK_DDR 18
-#define R8A7794_CLK_SDH 19
-#define R8A7794_CLK_SD0 20
-#define R8A7794_CLK_SD2 21
-#define R8A7794_CLK_SD3 22
-#define R8A7794_CLK_MMC0 23
-#define R8A7794_CLK_MP 24
-#define R8A7794_CLK_QSPI 25
-#define R8A7794_CLK_CPEX 26
-#define R8A7794_CLK_RCAN 27
-#define R8A7794_CLK_R 28
-#define R8A7794_CLK_OSC 29
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a7795-cpg-mssr.h b/include/dt-bindings/clock/r8a7795-cpg-mssr.h
deleted file mode 100644
index 92b3e2a..0000000
--- a/include/dt-bindings/clock/r8a7795-cpg-mssr.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2015 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a7795 CPG Core Clocks */
-#define R8A7795_CLK_Z 0
-#define R8A7795_CLK_Z2 1
-#define R8A7795_CLK_ZR 2
-#define R8A7795_CLK_ZG 3
-#define R8A7795_CLK_ZTR 4
-#define R8A7795_CLK_ZTRD2 5
-#define R8A7795_CLK_ZT 6
-#define R8A7795_CLK_ZX 7
-#define R8A7795_CLK_S0D1 8
-#define R8A7795_CLK_S0D4 9
-#define R8A7795_CLK_S1D1 10
-#define R8A7795_CLK_S1D2 11
-#define R8A7795_CLK_S1D4 12
-#define R8A7795_CLK_S2D1 13
-#define R8A7795_CLK_S2D2 14
-#define R8A7795_CLK_S2D4 15
-#define R8A7795_CLK_S3D1 16
-#define R8A7795_CLK_S3D2 17
-#define R8A7795_CLK_S3D4 18
-#define R8A7795_CLK_LB 19
-#define R8A7795_CLK_CL 20
-#define R8A7795_CLK_ZB3 21
-#define R8A7795_CLK_ZB3D2 22
-#define R8A7795_CLK_CR 23
-#define R8A7795_CLK_CRD2 24
-#define R8A7795_CLK_SD0H 25
-#define R8A7795_CLK_SD0 26
-#define R8A7795_CLK_SD1H 27
-#define R8A7795_CLK_SD1 28
-#define R8A7795_CLK_SD2H 29
-#define R8A7795_CLK_SD2 30
-#define R8A7795_CLK_SD3H 31
-#define R8A7795_CLK_SD3 32
-#define R8A7795_CLK_SSP2 33
-#define R8A7795_CLK_SSP1 34
-#define R8A7795_CLK_SSPRS 35
-#define R8A7795_CLK_RPC 36
-#define R8A7795_CLK_RPCD2 37
-#define R8A7795_CLK_MSO 38
-#define R8A7795_CLK_CANFD 39
-#define R8A7795_CLK_HDMI 40
-#define R8A7795_CLK_CSI0 41
-/* CLK_CSIREF was removed */
-#define R8A7795_CLK_CP 43
-#define R8A7795_CLK_CPEX 44
-#define R8A7795_CLK_R 45
-#define R8A7795_CLK_OSC 46
-
-/* r8a7795 ES2.0 CPG Core Clocks */
-#define R8A7795_CLK_S0D2 47
-#define R8A7795_CLK_S0D3 48
-#define R8A7795_CLK_S0D6 49
-#define R8A7795_CLK_S0D8 50
-#define R8A7795_CLK_S0D12 51
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a7796-cpg-mssr.h b/include/dt-bindings/clock/r8a7796-cpg-mssr.h
deleted file mode 100644
index c0957cf..0000000
--- a/include/dt-bindings/clock/r8a7796-cpg-mssr.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2016 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a7796 CPG Core Clocks */
-#define R8A7796_CLK_Z 0
-#define R8A7796_CLK_Z2 1
-#define R8A7796_CLK_ZR 2
-#define R8A7796_CLK_ZG 3
-#define R8A7796_CLK_ZTR 4
-#define R8A7796_CLK_ZTRD2 5
-#define R8A7796_CLK_ZT 6
-#define R8A7796_CLK_ZX 7
-#define R8A7796_CLK_S0D1 8
-#define R8A7796_CLK_S0D2 9
-#define R8A7796_CLK_S0D3 10
-#define R8A7796_CLK_S0D4 11
-#define R8A7796_CLK_S0D6 12
-#define R8A7796_CLK_S0D8 13
-#define R8A7796_CLK_S0D12 14
-#define R8A7796_CLK_S1D1 15
-#define R8A7796_CLK_S1D2 16
-#define R8A7796_CLK_S1D4 17
-#define R8A7796_CLK_S2D1 18
-#define R8A7796_CLK_S2D2 19
-#define R8A7796_CLK_S2D4 20
-#define R8A7796_CLK_S3D1 21
-#define R8A7796_CLK_S3D2 22
-#define R8A7796_CLK_S3D4 23
-#define R8A7796_CLK_LB 24
-#define R8A7796_CLK_CL 25
-#define R8A7796_CLK_ZB3 26
-#define R8A7796_CLK_ZB3D2 27
-#define R8A7796_CLK_ZB3D4 28
-#define R8A7796_CLK_CR 29
-#define R8A7796_CLK_CRD2 30
-#define R8A7796_CLK_SD0H 31
-#define R8A7796_CLK_SD0 32
-#define R8A7796_CLK_SD1H 33
-#define R8A7796_CLK_SD1 34
-#define R8A7796_CLK_SD2H 35
-#define R8A7796_CLK_SD2 36
-#define R8A7796_CLK_SD3H 37
-#define R8A7796_CLK_SD3 38
-#define R8A7796_CLK_SSP2 39
-#define R8A7796_CLK_SSP1 40
-#define R8A7796_CLK_SSPRS 41
-#define R8A7796_CLK_RPC 42
-#define R8A7796_CLK_RPCD2 43
-#define R8A7796_CLK_MSO 44
-#define R8A7796_CLK_CANFD 45
-#define R8A7796_CLK_HDMI 46
-#define R8A7796_CLK_CSI0 47
-/* CLK_CSIREF was removed */
-#define R8A7796_CLK_CP 49
-#define R8A7796_CLK_CPEX 50
-#define R8A7796_CLK_R 51
-#define R8A7796_CLK_OSC 52
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a77961-cpg-mssr.h b/include/dt-bindings/clock/r8a77961-cpg-mssr.h
deleted file mode 100644
index 7921d78..0000000
--- a/include/dt-bindings/clock/r8a77961-cpg-mssr.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2019 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a77961 CPG Core Clocks */
-#define R8A77961_CLK_Z 0
-#define R8A77961_CLK_Z2 1
-#define R8A77961_CLK_ZR 2
-#define R8A77961_CLK_ZG 3
-#define R8A77961_CLK_ZTR 4
-#define R8A77961_CLK_ZTRD2 5
-#define R8A77961_CLK_ZT 6
-#define R8A77961_CLK_ZX 7
-#define R8A77961_CLK_S0D1 8
-#define R8A77961_CLK_S0D2 9
-#define R8A77961_CLK_S0D3 10
-#define R8A77961_CLK_S0D4 11
-#define R8A77961_CLK_S0D6 12
-#define R8A77961_CLK_S0D8 13
-#define R8A77961_CLK_S0D12 14
-#define R8A77961_CLK_S1D1 15
-#define R8A77961_CLK_S1D2 16
-#define R8A77961_CLK_S1D4 17
-#define R8A77961_CLK_S2D1 18
-#define R8A77961_CLK_S2D2 19
-#define R8A77961_CLK_S2D4 20
-#define R8A77961_CLK_S3D1 21
-#define R8A77961_CLK_S3D2 22
-#define R8A77961_CLK_S3D4 23
-#define R8A77961_CLK_LB 24
-#define R8A77961_CLK_CL 25
-#define R8A77961_CLK_ZB3 26
-#define R8A77961_CLK_ZB3D2 27
-#define R8A77961_CLK_ZB3D4 28
-#define R8A77961_CLK_CR 29
-#define R8A77961_CLK_CRD2 30
-#define R8A77961_CLK_SD0H 31
-#define R8A77961_CLK_SD0 32
-#define R8A77961_CLK_SD1H 33
-#define R8A77961_CLK_SD1 34
-#define R8A77961_CLK_SD2H 35
-#define R8A77961_CLK_SD2 36
-#define R8A77961_CLK_SD3H 37
-#define R8A77961_CLK_SD3 38
-#define R8A77961_CLK_SSP2 39
-#define R8A77961_CLK_SSP1 40
-#define R8A77961_CLK_SSPRS 41
-#define R8A77961_CLK_RPC 42
-#define R8A77961_CLK_RPCD2 43
-#define R8A77961_CLK_MSO 44
-#define R8A77961_CLK_CANFD 45
-#define R8A77961_CLK_HDMI 46
-#define R8A77961_CLK_CSI0 47
-/* CLK_CSIREF was removed */
-#define R8A77961_CLK_CP 49
-#define R8A77961_CLK_CPEX 50
-#define R8A77961_CLK_R 51
-#define R8A77961_CLK_OSC 52
-
-#endif /* __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a77965-cpg-mssr.h b/include/dt-bindings/clock/r8a77965-cpg-mssr.h
deleted file mode 100644
index 6d3b5a9..0000000
--- a/include/dt-bindings/clock/r8a77965-cpg-mssr.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a77965 CPG Core Clocks */
-#define R8A77965_CLK_Z 0
-#define R8A77965_CLK_ZR 1
-#define R8A77965_CLK_ZG 2
-#define R8A77965_CLK_ZTR 3
-#define R8A77965_CLK_ZTRD2 4
-#define R8A77965_CLK_ZT 5
-#define R8A77965_CLK_ZX 6
-#define R8A77965_CLK_S0D1 7
-#define R8A77965_CLK_S0D2 8
-#define R8A77965_CLK_S0D3 9
-#define R8A77965_CLK_S0D4 10
-#define R8A77965_CLK_S0D6 11
-#define R8A77965_CLK_S0D8 12
-#define R8A77965_CLK_S0D12 13
-#define R8A77965_CLK_S1D1 14
-#define R8A77965_CLK_S1D2 15
-#define R8A77965_CLK_S1D4 16
-#define R8A77965_CLK_S2D1 17
-#define R8A77965_CLK_S2D2 18
-#define R8A77965_CLK_S2D4 19
-#define R8A77965_CLK_S3D1 20
-#define R8A77965_CLK_S3D2 21
-#define R8A77965_CLK_S3D4 22
-#define R8A77965_CLK_LB 23
-#define R8A77965_CLK_CL 24
-#define R8A77965_CLK_ZB3 25
-#define R8A77965_CLK_ZB3D2 26
-#define R8A77965_CLK_CR 27
-#define R8A77965_CLK_CRD2 28
-#define R8A77965_CLK_SD0H 29
-#define R8A77965_CLK_SD0 30
-#define R8A77965_CLK_SD1H 31
-#define R8A77965_CLK_SD1 32
-#define R8A77965_CLK_SD2H 33
-#define R8A77965_CLK_SD2 34
-#define R8A77965_CLK_SD3H 35
-#define R8A77965_CLK_SD3 36
-#define R8A77965_CLK_SSP2 37
-#define R8A77965_CLK_SSP1 38
-#define R8A77965_CLK_SSPRS 39
-#define R8A77965_CLK_RPC 40
-#define R8A77965_CLK_RPCD2 41
-#define R8A77965_CLK_MSO 42
-#define R8A77965_CLK_CANFD 43
-#define R8A77965_CLK_HDMI 44
-#define R8A77965_CLK_CSI0 45
-#define R8A77965_CLK_CP 46
-#define R8A77965_CLK_CPEX 47
-#define R8A77965_CLK_R 48
-#define R8A77965_CLK_OSC 49
-
-#endif /* __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a77970-cpg-mssr.h b/include/dt-bindings/clock/r8a77970-cpg-mssr.h
deleted file mode 100644
index 6145ebe..0000000
--- a/include/dt-bindings/clock/r8a77970-cpg-mssr.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2016 Renesas Electronics Corp.
- * Copyright (C) 2017 Cogent Embedded, Inc.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a77970 CPG Core Clocks */
-#define R8A77970_CLK_Z2 0
-#define R8A77970_CLK_ZR 1
-#define R8A77970_CLK_ZTR 2
-#define R8A77970_CLK_ZTRD2 3
-#define R8A77970_CLK_ZT 4
-#define R8A77970_CLK_ZX 5
-#define R8A77970_CLK_S1D1 6
-#define R8A77970_CLK_S1D2 7
-#define R8A77970_CLK_S1D4 8
-#define R8A77970_CLK_S2D1 9
-#define R8A77970_CLK_S2D2 10
-#define R8A77970_CLK_S2D4 11
-#define R8A77970_CLK_LB 12
-#define R8A77970_CLK_CL 13
-#define R8A77970_CLK_ZB3 14
-#define R8A77970_CLK_ZB3D2 15
-#define R8A77970_CLK_DDR 16
-#define R8A77970_CLK_CR 17
-#define R8A77970_CLK_CRD2 18
-#define R8A77970_CLK_SD0H 19
-#define R8A77970_CLK_SD0 20
-#define R8A77970_CLK_RPC 21
-#define R8A77970_CLK_RPCD2 22
-#define R8A77970_CLK_MSO 23
-#define R8A77970_CLK_CANFD 24
-#define R8A77970_CLK_CSI0 25
-#define R8A77970_CLK_FRAY 26
-#define R8A77970_CLK_CP 27
-#define R8A77970_CLK_CPEX 28
-#define R8A77970_CLK_R 29
-#define R8A77970_CLK_OSC 30
-
-#endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a77980-cpg-mssr.h b/include/dt-bindings/clock/r8a77980-cpg-mssr.h
deleted file mode 100644
index a4c0d76..0000000
--- a/include/dt-bindings/clock/r8a77980-cpg-mssr.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2018 Renesas Electronics Corp.
- * Copyright (C) 2018 Cogent Embedded, Inc.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a77980 CPG Core Clocks */
-#define R8A77980_CLK_Z2 0
-#define R8A77980_CLK_ZR 1
-#define R8A77980_CLK_ZTR 2
-#define R8A77980_CLK_ZTRD2 3
-#define R8A77980_CLK_ZT 4
-#define R8A77980_CLK_ZX 5
-#define R8A77980_CLK_S0D1 6
-#define R8A77980_CLK_S0D2 7
-#define R8A77980_CLK_S0D3 8
-#define R8A77980_CLK_S0D4 9
-#define R8A77980_CLK_S0D6 10
-#define R8A77980_CLK_S0D12 11
-#define R8A77980_CLK_S0D24 12
-#define R8A77980_CLK_S1D1 13
-#define R8A77980_CLK_S1D2 14
-#define R8A77980_CLK_S1D4 15
-#define R8A77980_CLK_S2D1 16
-#define R8A77980_CLK_S2D2 17
-#define R8A77980_CLK_S2D4 18
-#define R8A77980_CLK_S3D1 19
-#define R8A77980_CLK_S3D2 20
-#define R8A77980_CLK_S3D4 21
-#define R8A77980_CLK_LB 22
-#define R8A77980_CLK_CL 23
-#define R8A77980_CLK_ZB3 24
-#define R8A77980_CLK_ZB3D2 25
-#define R8A77980_CLK_ZB3D4 26
-#define R8A77980_CLK_SD0H 27
-#define R8A77980_CLK_SD0 28
-#define R8A77980_CLK_RPC 29
-#define R8A77980_CLK_RPCD2 30
-#define R8A77980_CLK_MSO 31
-#define R8A77980_CLK_CANFD 32
-#define R8A77980_CLK_CSI0 33
-#define R8A77980_CLK_CP 34
-#define R8A77980_CLK_CPEX 35
-#define R8A77980_CLK_R 36
-#define R8A77980_CLK_OSC 37
-
-#endif /* __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a77990-cpg-mssr.h b/include/dt-bindings/clock/r8a77990-cpg-mssr.h
deleted file mode 100644
index a596a48..0000000
--- a/include/dt-bindings/clock/r8a77990-cpg-mssr.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a77990 CPG Core Clocks */
-#define R8A77990_CLK_Z2 0
-#define R8A77990_CLK_ZR 1
-#define R8A77990_CLK_ZG 2
-#define R8A77990_CLK_ZTR 3
-#define R8A77990_CLK_ZT 4
-#define R8A77990_CLK_ZX 5
-#define R8A77990_CLK_S0D1 6
-#define R8A77990_CLK_S0D3 7
-#define R8A77990_CLK_S0D6 8
-#define R8A77990_CLK_S0D12 9
-#define R8A77990_CLK_S0D24 10
-#define R8A77990_CLK_S1D1 11
-#define R8A77990_CLK_S1D2 12
-#define R8A77990_CLK_S1D4 13
-#define R8A77990_CLK_S2D1 14
-#define R8A77990_CLK_S2D2 15
-#define R8A77990_CLK_S2D4 16
-#define R8A77990_CLK_S3D1 17
-#define R8A77990_CLK_S3D2 18
-#define R8A77990_CLK_S3D4 19
-#define R8A77990_CLK_S0D6C 20
-#define R8A77990_CLK_S3D1C 21
-#define R8A77990_CLK_S3D2C 22
-#define R8A77990_CLK_S3D4C 23
-#define R8A77990_CLK_LB 24
-#define R8A77990_CLK_CL 25
-#define R8A77990_CLK_ZB3 26
-#define R8A77990_CLK_ZB3D2 27
-#define R8A77990_CLK_CR 28
-#define R8A77990_CLK_CRD2 29
-#define R8A77990_CLK_SD0H 30
-#define R8A77990_CLK_SD0 31
-#define R8A77990_CLK_SD1H 32
-#define R8A77990_CLK_SD1 33
-#define R8A77990_CLK_SD3H 34
-#define R8A77990_CLK_SD3 35
-#define R8A77990_CLK_RPC 36
-#define R8A77990_CLK_RPCD2 37
-#define R8A77990_CLK_ZA2 38
-#define R8A77990_CLK_ZA8 39
-#define R8A77990_CLK_Z2D 40
-#define R8A77990_CLK_CANFD 41
-#define R8A77990_CLK_MSO 42
-#define R8A77990_CLK_R 43
-#define R8A77990_CLK_OSC 44
-#define R8A77990_CLK_LV0 45
-#define R8A77990_CLK_LV1 46
-#define R8A77990_CLK_CSI0 47
-#define R8A77990_CLK_CP 48
-#define R8A77990_CLK_CPEX 49
-
-#endif /* __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a77995-cpg-mssr.h b/include/dt-bindings/clock/r8a77995-cpg-mssr.h
deleted file mode 100644
index fd701c4..0000000
--- a/include/dt-bindings/clock/r8a77995-cpg-mssr.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2017 Glider bvba
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a77995 CPG Core Clocks */
-#define R8A77995_CLK_Z2 0
-#define R8A77995_CLK_ZG 1
-#define R8A77995_CLK_ZTR 2
-#define R8A77995_CLK_ZT 3
-#define R8A77995_CLK_ZX 4
-#define R8A77995_CLK_S0D1 5
-#define R8A77995_CLK_S1D1 6
-#define R8A77995_CLK_S1D2 7
-#define R8A77995_CLK_S1D4 8
-#define R8A77995_CLK_S2D1 9
-#define R8A77995_CLK_S2D2 10
-#define R8A77995_CLK_S2D4 11
-#define R8A77995_CLK_S3D1 12
-#define R8A77995_CLK_S3D2 13
-#define R8A77995_CLK_S3D4 14
-#define R8A77995_CLK_S1D4C 15
-#define R8A77995_CLK_S3D1C 16
-#define R8A77995_CLK_S3D2C 17
-#define R8A77995_CLK_S3D4C 18
-#define R8A77995_CLK_LB 19
-#define R8A77995_CLK_CL 20
-#define R8A77995_CLK_ZB3 21
-#define R8A77995_CLK_ZB3D2 22
-#define R8A77995_CLK_CR 23
-#define R8A77995_CLK_CRD2 24
-#define R8A77995_CLK_SD0H 25
-#define R8A77995_CLK_SD0 26
-/* CLK_SSP2 was removed */
-/* CLK_SSP1 was removed */
-#define R8A77995_CLK_RPC 29
-#define R8A77995_CLK_RPCD2 30
-#define R8A77995_CLK_ZA2 31
-#define R8A77995_CLK_ZA8 32
-#define R8A77995_CLK_Z2D 33
-#define R8A77995_CLK_CANFD 34
-#define R8A77995_CLK_MSO 35
-#define R8A77995_CLK_R 36
-#define R8A77995_CLK_OSC 37
-#define R8A77995_CLK_LV0 38
-#define R8A77995_CLK_LV1 39
-#define R8A77995_CLK_CP 40
-#define R8A77995_CLK_CPEX 41
-
-#endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a779a0-cpg-mssr.h b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
deleted file mode 100644
index f1d737c..0000000
--- a/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2020 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a779A0 CPG Core Clocks */
-#define R8A779A0_CLK_Z0 0
-#define R8A779A0_CLK_ZX 1
-#define R8A779A0_CLK_Z1 2
-#define R8A779A0_CLK_ZR 3
-#define R8A779A0_CLK_ZS 4
-#define R8A779A0_CLK_ZT 5
-#define R8A779A0_CLK_ZTR 6
-#define R8A779A0_CLK_S1D1 7
-#define R8A779A0_CLK_S1D2 8
-#define R8A779A0_CLK_S1D4 9
-#define R8A779A0_CLK_S1D8 10
-#define R8A779A0_CLK_S1D12 11
-#define R8A779A0_CLK_S3D1 12
-#define R8A779A0_CLK_S3D2 13
-#define R8A779A0_CLK_S3D4 14
-#define R8A779A0_CLK_LB 15
-#define R8A779A0_CLK_CP 16
-#define R8A779A0_CLK_CL 17
-#define R8A779A0_CLK_CL16MCK 18
-#define R8A779A0_CLK_ZB30 19
-#define R8A779A0_CLK_ZB30D2 20
-#define R8A779A0_CLK_ZB30D4 21
-#define R8A779A0_CLK_ZB31 22
-#define R8A779A0_CLK_ZB31D2 23
-#define R8A779A0_CLK_ZB31D4 24
-#define R8A779A0_CLK_SD0H 25
-#define R8A779A0_CLK_SD0 26
-#define R8A779A0_CLK_RPC 27
-#define R8A779A0_CLK_RPCD2 28
-#define R8A779A0_CLK_MSO 29
-#define R8A779A0_CLK_CANFD 30
-#define R8A779A0_CLK_CSI0 31
-#define R8A779A0_CLK_FRAY 32
-#define R8A779A0_CLK_DSI 33
-#define R8A779A0_CLK_VIP 34
-#define R8A779A0_CLK_ADGH 35
-#define R8A779A0_CLK_CNNDSP 36
-#define R8A779A0_CLK_ICU 37
-#define R8A779A0_CLK_ICUD2 38
-#define R8A779A0_CLK_VCBUS 39
-#define R8A779A0_CLK_CBFUSA 40
-#define R8A779A0_CLK_R 41
-#define R8A779A0_CLK_OSC 42
-
-#endif /* __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a779f0-cpg-mssr.h b/include/dt-bindings/clock/r8a779f0-cpg-mssr.h
deleted file mode 100644
index c34be56..0000000
--- a/include/dt-bindings/clock/r8a779f0-cpg-mssr.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
-/*
- * Copyright (C) 2021 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a779f0 CPG Core Clocks */
-
-#define R8A779F0_CLK_ZX 0
-#define R8A779F0_CLK_ZS 1
-#define R8A779F0_CLK_ZT 2
-#define R8A779F0_CLK_ZTR 3
-#define R8A779F0_CLK_S0D2 4
-#define R8A779F0_CLK_S0D3 5
-#define R8A779F0_CLK_S0D4 6
-#define R8A779F0_CLK_S0D2_MM 7
-#define R8A779F0_CLK_S0D3_MM 8
-#define R8A779F0_CLK_S0D4_MM 9
-#define R8A779F0_CLK_S0D2_RT 10
-#define R8A779F0_CLK_S0D3_RT 11
-#define R8A779F0_CLK_S0D4_RT 12
-#define R8A779F0_CLK_S0D6_RT 13
-#define R8A779F0_CLK_S0D3_PER 14
-#define R8A779F0_CLK_S0D6_PER 15
-#define R8A779F0_CLK_S0D12_PER 16
-#define R8A779F0_CLK_S0D24_PER 17
-#define R8A779F0_CLK_S0D2_HSC 18
-#define R8A779F0_CLK_S0D3_HSC 19
-#define R8A779F0_CLK_S0D4_HSC 20
-#define R8A779F0_CLK_S0D6_HSC 21
-#define R8A779F0_CLK_S0D12_HSC 22
-#define R8A779F0_CLK_S0D2_CC 23
-#define R8A779F0_CLK_CL 24
-#define R8A779F0_CLK_CL16M 25
-#define R8A779F0_CLK_CL16M_MM 26
-#define R8A779F0_CLK_CL16M_RT 27
-#define R8A779F0_CLK_CL16M_PER 28
-#define R8A779F0_CLK_CL16M_HSC 29
-#define R8A779F0_CLK_Z0 30
-#define R8A779F0_CLK_Z1 31
-#define R8A779F0_CLK_ZB3 32
-#define R8A779F0_CLK_ZB3D2 33
-#define R8A779F0_CLK_ZB3D4 34
-#define R8A779F0_CLK_SD0H 35
-#define R8A779F0_CLK_SD0 36
-#define R8A779F0_CLK_RPC 37
-#define R8A779F0_CLK_RPCD2 38
-#define R8A779F0_CLK_MSO 39
-#define R8A779F0_CLK_SASYNCRT 40
-#define R8A779F0_CLK_SASYNCPERD1 41
-#define R8A779F0_CLK_SASYNCPERD2 42
-#define R8A779F0_CLK_SASYNCPERD4 43
-#define R8A779F0_CLK_DBGSOC_HSC 44
-#define R8A779F0_CLK_RSW2 45
-#define R8A779F0_CLK_OSC 46
-#define R8A779F0_CLK_ZR 47
-#define R8A779F0_CLK_CPEX 48
-#define R8A779F0_CLK_CBFUSA 49
-#define R8A779F0_CLK_R 50
-
-#endif /* __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
deleted file mode 100644
index 7850cdc..0000000
--- a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (C) 2022 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a779g0 CPG Core Clocks */
-
-#define R8A779G0_CLK_ZX 0
-#define R8A779G0_CLK_ZS 1
-#define R8A779G0_CLK_ZT 2
-#define R8A779G0_CLK_ZTR 3
-#define R8A779G0_CLK_S0D2 4
-#define R8A779G0_CLK_S0D3 5
-#define R8A779G0_CLK_S0D4 6
-#define R8A779G0_CLK_S0D1_VIO 7
-#define R8A779G0_CLK_S0D2_VIO 8
-#define R8A779G0_CLK_S0D4_VIO 9
-#define R8A779G0_CLK_S0D8_VIO 10
-#define R8A779G0_CLK_S0D1_VC 11
-#define R8A779G0_CLK_S0D2_VC 12
-#define R8A779G0_CLK_S0D4_VC 13
-#define R8A779G0_CLK_S0D2_MM 14
-#define R8A779G0_CLK_S0D4_MM 15
-#define R8A779G0_CLK_S0D2_U3DG 16
-#define R8A779G0_CLK_S0D4_U3DG 17
-#define R8A779G0_CLK_S0D2_RT 18
-#define R8A779G0_CLK_S0D3_RT 19
-#define R8A779G0_CLK_S0D4_RT 20
-#define R8A779G0_CLK_S0D6_RT 21
-#define R8A779G0_CLK_S0D24_RT 22
-#define R8A779G0_CLK_S0D2_PER 23
-#define R8A779G0_CLK_S0D3_PER 24
-#define R8A779G0_CLK_S0D4_PER 25
-#define R8A779G0_CLK_S0D6_PER 26
-#define R8A779G0_CLK_S0D12_PER 27
-#define R8A779G0_CLK_S0D24_PER 28
-#define R8A779G0_CLK_S0D1_HSC 29
-#define R8A779G0_CLK_S0D2_HSC 30
-#define R8A779G0_CLK_S0D4_HSC 31
-#define R8A779G0_CLK_S0D2_CC 32
-#define R8A779G0_CLK_SVD1_IR 33
-#define R8A779G0_CLK_SVD2_IR 34
-#define R8A779G0_CLK_SVD1_VIP 35
-#define R8A779G0_CLK_SVD2_VIP 36
-#define R8A779G0_CLK_CL 37
-#define R8A779G0_CLK_CL16M 38
-#define R8A779G0_CLK_CL16M_MM 39
-#define R8A779G0_CLK_CL16M_RT 40
-#define R8A779G0_CLK_CL16M_PER 41
-#define R8A779G0_CLK_CL16M_HSC 42
-#define R8A779G0_CLK_Z0 43
-#define R8A779G0_CLK_ZB3 44
-#define R8A779G0_CLK_ZB3D2 45
-#define R8A779G0_CLK_ZB3D4 46
-#define R8A779G0_CLK_ZG 47
-#define R8A779G0_CLK_SD0H 48
-#define R8A779G0_CLK_SD0 49
-#define R8A779G0_CLK_RPC 50
-#define R8A779G0_CLK_RPCD2 51
-#define R8A779G0_CLK_MSO 52
-#define R8A779G0_CLK_CANFD 53
-#define R8A779G0_CLK_CSI 54
-#define R8A779G0_CLK_FRAY 55
-#define R8A779G0_CLK_IPC 56
-#define R8A779G0_CLK_SASYNCRT 57
-#define R8A779G0_CLK_SASYNCPERD1 58
-#define R8A779G0_CLK_SASYNCPERD2 59
-#define R8A779G0_CLK_SASYNCPERD4 60
-#define R8A779G0_CLK_VIOBUS 61
-#define R8A779G0_CLK_VIOBUSD2 62
-#define R8A779G0_CLK_VCBUS 63
-#define R8A779G0_CLK_VCBUSD2 64
-#define R8A779G0_CLK_DSIEXT 65
-#define R8A779G0_CLK_DSIREF 66
-#define R8A779G0_CLK_ADGH 67
-#define R8A779G0_CLK_OSC 68
-#define R8A779G0_CLK_ZR0 69
-#define R8A779G0_CLK_ZR1 70
-#define R8A779G0_CLK_ZR2 71
-#define R8A779G0_CLK_IMPA 72
-#define R8A779G0_CLK_IMPAD4 73
-#define R8A779G0_CLK_CPEX 74
-#define R8A779G0_CLK_CBFUSA 75
-#define R8A779G0_CLK_R 76
-#define R8A779G0_CLK_CP 77
-
-#endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h b/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h
deleted file mode 100644
index 7ab6cfb..0000000
--- a/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (C) 2023 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a779h0 CPG Core Clocks */
-
-#define R8A779H0_CLK_ZX 0
-#define R8A779H0_CLK_ZD 1
-#define R8A779H0_CLK_ZS 2
-#define R8A779H0_CLK_ZT 3
-#define R8A779H0_CLK_ZTR 4
-#define R8A779H0_CLK_S0D2 5
-#define R8A779H0_CLK_S0D3 6
-#define R8A779H0_CLK_S0D4 7
-#define R8A779H0_CLK_S0D1_VIO 8
-#define R8A779H0_CLK_S0D2_VIO 9
-#define R8A779H0_CLK_S0D4_VIO 10
-#define R8A779H0_CLK_S0D8_VIO 11
-#define R8A779H0_CLK_VIOBUSD1 12
-#define R8A779H0_CLK_VIOBUSD2 13
-#define R8A779H0_CLK_S0D1_VC 14
-#define R8A779H0_CLK_S0D2_VC 15
-#define R8A779H0_CLK_S0D4_VC 16
-#define R8A779H0_CLK_VCBUSD1 17
-#define R8A779H0_CLK_VCBUSD2 18
-#define R8A779H0_CLK_S0D2_MM 19
-#define R8A779H0_CLK_S0D4_MM 20
-#define R8A779H0_CLK_S0D2_U3DG 21
-#define R8A779H0_CLK_S0D4_U3DG 22
-#define R8A779H0_CLK_S0D2_RT 23
-#define R8A779H0_CLK_S0D3_RT 24
-#define R8A779H0_CLK_S0D4_RT 25
-#define R8A779H0_CLK_S0D6_RT 26
-#define R8A779H0_CLK_S0D2_PER 27
-#define R8A779H0_CLK_S0D3_PER 28
-#define R8A779H0_CLK_S0D4_PER 29
-#define R8A779H0_CLK_S0D6_PER 30
-#define R8A779H0_CLK_S0D12_PER 31
-#define R8A779H0_CLK_S0D24_PER 32
-#define R8A779H0_CLK_S0D1_HSC 33
-#define R8A779H0_CLK_S0D2_HSC 34
-#define R8A779H0_CLK_S0D4_HSC 35
-#define R8A779H0_CLK_S0D8_HSC 36
-#define R8A779H0_CLK_SVD1_IR 37
-#define R8A779H0_CLK_SVD2_IR 38
-#define R8A779H0_CLK_IMPAD1 39
-#define R8A779H0_CLK_IMPAD4 40
-#define R8A779H0_CLK_IMPB 41
-#define R8A779H0_CLK_SVD1_VIP 42
-#define R8A779H0_CLK_SVD2_VIP 43
-#define R8A779H0_CLK_CL 44
-#define R8A779H0_CLK_CL16M 45
-#define R8A779H0_CLK_CL16M_MM 46
-#define R8A779H0_CLK_CL16M_RT 47
-#define R8A779H0_CLK_CL16M_PER 48
-#define R8A779H0_CLK_CL16M_HSC 49
-#define R8A779H0_CLK_ZC0 50
-#define R8A779H0_CLK_ZC1 51
-#define R8A779H0_CLK_ZC2 52
-#define R8A779H0_CLK_ZC3 53
-#define R8A779H0_CLK_ZB3 54
-#define R8A779H0_CLK_ZB3D2 55
-#define R8A779H0_CLK_ZB3D4 56
-#define R8A779H0_CLK_ZG 57
-#define R8A779H0_CLK_SD0H 58
-#define R8A779H0_CLK_SD0 59
-#define R8A779H0_CLK_RPC 60
-#define R8A779H0_CLK_RPCD2 61
-#define R8A779H0_CLK_MSO 62
-#define R8A779H0_CLK_CANFD 63
-#define R8A779H0_CLK_CSI 64
-#define R8A779H0_CLK_FRAY 65
-#define R8A779H0_CLK_IPC 66
-#define R8A779H0_CLK_SASYNCRT 67
-#define R8A779H0_CLK_SASYNCPERD1 68
-#define R8A779H0_CLK_SASYNCPERD2 69
-#define R8A779H0_CLK_SASYNCPERD4 70
-#define R8A779H0_CLK_DSIEXT 71
-#define R8A779H0_CLK_DSIREF 72
-#define R8A779H0_CLK_ADGH 73
-#define R8A779H0_CLK_OSC 74
-#define R8A779H0_CLK_ZR0 75
-#define R8A779H0_CLK_ZR1 76
-#define R8A779H0_CLK_ZR2 77
-#define R8A779H0_CLK_RGMII 78
-#define R8A779H0_CLK_CPEX 79
-#define R8A779H0_CLK_CP 80
-#define R8A779H0_CLK_CBFUSA 81
-#define R8A779H0_CLK_R 82
-
-#endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/renesas-cpg-mssr.h b/include/dt-bindings/clock/renesas-cpg-mssr.h
deleted file mode 100644
index 569a3cc..0000000
--- a/include/dt-bindings/clock/renesas-cpg-mssr.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (C) 2015 Renesas Electronics Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__
-
-#define CPG_CORE 0 /* Core Clock */
-#define CPG_MOD 1 /* Module Clock */
-
-#endif /* __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/power/r8a774a1-sysc.h b/include/dt-bindings/power/r8a774a1-sysc.h
deleted file mode 100644
index 580f431..0000000
--- a/include/dt-bindings/power/r8a774a1-sysc.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2018 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_POWER_R8A774A1_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A774A1_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A774A1_PD_CA57_CPU0 0
-#define R8A774A1_PD_CA57_CPU1 1
-#define R8A774A1_PD_CA53_CPU0 5
-#define R8A774A1_PD_CA53_CPU1 6
-#define R8A774A1_PD_CA53_CPU2 7
-#define R8A774A1_PD_CA53_CPU3 8
-#define R8A774A1_PD_CA57_SCU 12
-#define R8A774A1_PD_A3VC 14
-#define R8A774A1_PD_3DG_A 17
-#define R8A774A1_PD_3DG_B 18
-#define R8A774A1_PD_CA53_SCU 21
-#define R8A774A1_PD_A2VC0 25
-#define R8A774A1_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A774A1_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A774A1_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a774b1-sysc.h b/include/dt-bindings/power/r8a774b1-sysc.h
deleted file mode 100644
index 3737364..0000000
--- a/include/dt-bindings/power/r8a774b1-sysc.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2019 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_POWER_R8A774B1_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A774B1_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A774B1_PD_CA57_CPU0 0
-#define R8A774B1_PD_CA57_CPU1 1
-#define R8A774B1_PD_A3VP 9
-#define R8A774B1_PD_CA57_SCU 12
-#define R8A774B1_PD_A3VC 14
-#define R8A774B1_PD_3DG_A 17
-#define R8A774B1_PD_3DG_B 18
-#define R8A774B1_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A774B1_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a774c0-sysc.h b/include/dt-bindings/power/r8a774c0-sysc.h
deleted file mode 100644
index 9922d4c..0000000
--- a/include/dt-bindings/power/r8a774c0-sysc.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2018 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_POWER_R8A774C0_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A774C0_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A774C0_PD_CA53_CPU0 5
-#define R8A774C0_PD_CA53_CPU1 6
-#define R8A774C0_PD_A3VC 14
-#define R8A774C0_PD_3DG_A 17
-#define R8A774C0_PD_3DG_B 18
-#define R8A774C0_PD_CA53_SCU 21
-#define R8A774C0_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A774C0_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A774C0_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a774e1-sysc.h b/include/dt-bindings/power/r8a774e1-sysc.h
deleted file mode 100644
index 7edb816..0000000
--- a/include/dt-bindings/power/r8a774e1-sysc.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2020 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_POWER_R8A774E1_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A774E1_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A774E1_PD_CA57_CPU0 0
-#define R8A774E1_PD_CA57_CPU1 1
-#define R8A774E1_PD_CA57_CPU2 2
-#define R8A774E1_PD_CA57_CPU3 3
-#define R8A774E1_PD_CA53_CPU0 5
-#define R8A774E1_PD_CA53_CPU1 6
-#define R8A774E1_PD_CA53_CPU2 7
-#define R8A774E1_PD_CA53_CPU3 8
-#define R8A774E1_PD_A3VP 9
-#define R8A774E1_PD_CA57_SCU 12
-#define R8A774E1_PD_A3VC 14
-#define R8A774E1_PD_3DG_A 17
-#define R8A774E1_PD_3DG_B 18
-#define R8A774E1_PD_3DG_C 19
-#define R8A774E1_PD_3DG_D 20
-#define R8A774E1_PD_CA53_SCU 21
-#define R8A774E1_PD_3DG_E 22
-#define R8A774E1_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A774E1_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7790-sysc.h b/include/dt-bindings/power/r8a7790-sysc.h
deleted file mode 100644
index bcb4905..0000000
--- a/include/dt-bindings/power/r8a7790-sysc.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 Glider bvba
- */
-#ifndef __DT_BINDINGS_POWER_R8A7790_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A7790_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A7790_PD_CA15_CPU0 0
-#define R8A7790_PD_CA15_CPU1 1
-#define R8A7790_PD_CA15_CPU2 2
-#define R8A7790_PD_CA15_CPU3 3
-#define R8A7790_PD_CA7_CPU0 5
-#define R8A7790_PD_CA7_CPU1 6
-#define R8A7790_PD_CA7_CPU2 7
-#define R8A7790_PD_CA7_CPU3 8
-#define R8A7790_PD_CA15_SCU 12
-#define R8A7790_PD_SH_4A 16
-#define R8A7790_PD_RGX 20
-#define R8A7790_PD_CA7_SCU 21
-#define R8A7790_PD_IMP 24
-
-/* Always-on power area */
-#define R8A7790_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A7790_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7791-sysc.h b/include/dt-bindings/power/r8a7791-sysc.h
deleted file mode 100644
index 1d20fae..0000000
--- a/include/dt-bindings/power/r8a7791-sysc.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 Glider bvba
- */
-#ifndef __DT_BINDINGS_POWER_R8A7791_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A7791_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A7791_PD_CA15_CPU0 0
-#define R8A7791_PD_CA15_CPU1 1
-#define R8A7791_PD_CA15_SCU 12
-#define R8A7791_PD_SH_4A 16
-#define R8A7791_PD_SGX 20
-
-/* Always-on power area */
-#define R8A7791_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A7791_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7792-sysc.h b/include/dt-bindings/power/r8a7792-sysc.h
deleted file mode 100644
index dd3a466..0000000
--- a/include/dt-bindings/power/r8a7792-sysc.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 Cogent Embedded Inc.
- */
-#ifndef __DT_BINDINGS_POWER_R8A7792_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A7792_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A7792_PD_CA15_CPU0 0
-#define R8A7792_PD_CA15_CPU1 1
-#define R8A7792_PD_CA15_SCU 12
-#define R8A7792_PD_SGX 20
-#define R8A7792_PD_IMP 24
-
-/* Always-on power area */
-#define R8A7792_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A7792_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7793-sysc.h b/include/dt-bindings/power/r8a7793-sysc.h
deleted file mode 100644
index 056998c..0000000
--- a/include/dt-bindings/power/r8a7793-sysc.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 Glider bvba
- */
-#ifndef __DT_BINDINGS_POWER_R8A7793_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A7793_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- *
- * Note that R-Car M2-N is identical to R-Car M2-W w.r.t. power domains.
- */
-
-#define R8A7793_PD_CA15_CPU0 0
-#define R8A7793_PD_CA15_CPU1 1
-#define R8A7793_PD_CA15_SCU 12
-#define R8A7793_PD_SH_4A 16
-#define R8A7793_PD_SGX 20
-
-/* Always-on power area */
-#define R8A7793_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A7793_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7794-sysc.h b/include/dt-bindings/power/r8a7794-sysc.h
deleted file mode 100644
index 4d6c708..0000000
--- a/include/dt-bindings/power/r8a7794-sysc.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 Glider bvba
- */
-#ifndef __DT_BINDINGS_POWER_R8A7794_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A7794_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A7794_PD_CA7_CPU0 5
-#define R8A7794_PD_CA7_CPU1 6
-#define R8A7794_PD_SH_4A 16
-#define R8A7794_PD_SGX 20
-#define R8A7794_PD_CA7_SCU 21
-
-/* Always-on power area */
-#define R8A7794_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A7794_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7795-sysc.h b/include/dt-bindings/power/r8a7795-sysc.h
deleted file mode 100644
index ff53238..0000000
--- a/include/dt-bindings/power/r8a7795-sysc.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 Glider bvba
- */
-#ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A7795_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A7795_PD_CA57_CPU0 0
-#define R8A7795_PD_CA57_CPU1 1
-#define R8A7795_PD_CA57_CPU2 2
-#define R8A7795_PD_CA57_CPU3 3
-#define R8A7795_PD_CA53_CPU0 5
-#define R8A7795_PD_CA53_CPU1 6
-#define R8A7795_PD_CA53_CPU2 7
-#define R8A7795_PD_CA53_CPU3 8
-#define R8A7795_PD_A3VP 9
-#define R8A7795_PD_CA57_SCU 12
-#define R8A7795_PD_CR7 13
-#define R8A7795_PD_A3VC 14
-#define R8A7795_PD_3DG_A 17
-#define R8A7795_PD_3DG_B 18
-#define R8A7795_PD_3DG_C 19
-#define R8A7795_PD_3DG_D 20
-#define R8A7795_PD_CA53_SCU 21
-#define R8A7795_PD_3DG_E 22
-#define R8A7795_PD_A3IR 24
-#define R8A7795_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A7795_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A7795_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7796-sysc.h b/include/dt-bindings/power/r8a7796-sysc.h
deleted file mode 100644
index 7e6fc06..0000000
--- a/include/dt-bindings/power/r8a7796-sysc.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 Glider bvba
- */
-#ifndef __DT_BINDINGS_POWER_R8A7796_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A7796_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A7796_PD_CA57_CPU0 0
-#define R8A7796_PD_CA57_CPU1 1
-#define R8A7796_PD_CA53_CPU0 5
-#define R8A7796_PD_CA53_CPU1 6
-#define R8A7796_PD_CA53_CPU2 7
-#define R8A7796_PD_CA53_CPU3 8
-#define R8A7796_PD_CA57_SCU 12
-#define R8A7796_PD_CR7 13
-#define R8A7796_PD_A3VC 14
-#define R8A7796_PD_3DG_A 17
-#define R8A7796_PD_3DG_B 18
-#define R8A7796_PD_CA53_SCU 21
-#define R8A7796_PD_A3IR 24
-#define R8A7796_PD_A2VC0 25
-#define R8A7796_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A7796_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A7796_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a77961-sysc.h b/include/dt-bindings/power/r8a77961-sysc.h
deleted file mode 100644
index 7a38009..0000000
--- a/include/dt-bindings/power/r8a77961-sysc.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2019 Glider bvba
- */
-#ifndef __DT_BINDINGS_POWER_R8A77961_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A77961_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A77961_PD_CA57_CPU0 0
-#define R8A77961_PD_CA57_CPU1 1
-#define R8A77961_PD_CA53_CPU0 5
-#define R8A77961_PD_CA53_CPU1 6
-#define R8A77961_PD_CA53_CPU2 7
-#define R8A77961_PD_CA53_CPU3 8
-#define R8A77961_PD_CA57_SCU 12
-#define R8A77961_PD_CR7 13
-#define R8A77961_PD_A3VC 14
-#define R8A77961_PD_3DG_A 17
-#define R8A77961_PD_3DG_B 18
-#define R8A77961_PD_CA53_SCU 21
-#define R8A77961_PD_A3IR 24
-#define R8A77961_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A77961_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A77961_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a77965-sysc.h b/include/dt-bindings/power/r8a77965-sysc.h
deleted file mode 100644
index de82d8a..0000000
--- a/include/dt-bindings/power/r8a77965-sysc.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
- * Copyright (C) 2016 Glider bvba
- */
-
-#ifndef __DT_BINDINGS_POWER_R8A77965_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A77965_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A77965_PD_CA57_CPU0 0
-#define R8A77965_PD_CA57_CPU1 1
-#define R8A77965_PD_A3VP 9
-#define R8A77965_PD_CA57_SCU 12
-#define R8A77965_PD_CR7 13
-#define R8A77965_PD_A3VC 14
-#define R8A77965_PD_3DG_A 17
-#define R8A77965_PD_3DG_B 18
-#define R8A77965_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A77965_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A77965_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a77970-sysc.h b/include/dt-bindings/power/r8a77970-sysc.h
deleted file mode 100644
index 9dcdbd5..0000000
--- a/include/dt-bindings/power/r8a77970-sysc.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2017 Cogent Embedded Inc.
- */
-#ifndef __DT_BINDINGS_POWER_R8A77970_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A77970_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A77970_PD_CA53_CPU0 5
-#define R8A77970_PD_CA53_CPU1 6
-#define R8A77970_PD_CA53_SCU 21
-#define R8A77970_PD_A2IR0 23
-#define R8A77970_PD_A3IR 24
-#define R8A77970_PD_A2IR1 27
-#define R8A77970_PD_A2DP 28
-#define R8A77970_PD_A2CN 29
-#define R8A77970_PD_A2SC0 30
-#define R8A77970_PD_A2SC1 31
-
-/* Always-on power area */
-#define R8A77970_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A77970_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a77980-sysc.h b/include/dt-bindings/power/r8a77980-sysc.h
deleted file mode 100644
index e12c858..0000000
--- a/include/dt-bindings/power/r8a77980-sysc.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2018 Renesas Electronics Corp.
- * Copyright (C) 2018 Cogent Embedded, Inc.
- */
-#ifndef __DT_BINDINGS_POWER_R8A77980_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A77980_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A77980_PD_A2SC2 0
-#define R8A77980_PD_A2SC3 1
-#define R8A77980_PD_A2SC4 2
-#define R8A77980_PD_A2DP0 3
-#define R8A77980_PD_A2DP1 4
-#define R8A77980_PD_CA53_CPU0 5
-#define R8A77980_PD_CA53_CPU1 6
-#define R8A77980_PD_CA53_CPU2 7
-#define R8A77980_PD_CA53_CPU3 8
-#define R8A77980_PD_A2CN 10
-#define R8A77980_PD_A3VIP0 11
-#define R8A77980_PD_A2IR5 12
-#define R8A77980_PD_CR7 13
-#define R8A77980_PD_A2IR4 15
-#define R8A77980_PD_CA53_SCU 21
-#define R8A77980_PD_A2IR0 23
-#define R8A77980_PD_A3IR 24
-#define R8A77980_PD_A3VIP1 25
-#define R8A77980_PD_A3VIP2 26
-#define R8A77980_PD_A2IR1 27
-#define R8A77980_PD_A2IR2 28
-#define R8A77980_PD_A2IR3 29
-#define R8A77980_PD_A2SC0 30
-#define R8A77980_PD_A2SC1 31
-
-/* Always-on power area */
-#define R8A77980_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A77980_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a77990-sysc.h b/include/dt-bindings/power/r8a77990-sysc.h
deleted file mode 100644
index 944d85b..0000000
--- a/include/dt-bindings/power/r8a77990-sysc.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_POWER_R8A77990_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A77990_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A77990_PD_CA53_CPU0 5
-#define R8A77990_PD_CA53_CPU1 6
-#define R8A77990_PD_CR7 13
-#define R8A77990_PD_A3VC 14
-#define R8A77990_PD_3DG_A 17
-#define R8A77990_PD_3DG_B 18
-#define R8A77990_PD_CA53_SCU 21
-#define R8A77990_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A77990_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A77990_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a77995-sysc.h b/include/dt-bindings/power/r8a77995-sysc.h
deleted file mode 100644
index f2b3550..0000000
--- a/include/dt-bindings/power/r8a77995-sysc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2017 Glider bvba
- */
-#ifndef __DT_BINDINGS_POWER_R8A77995_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A77995_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A77995_PD_CA53_CPU0 5
-#define R8A77995_PD_CA53_SCU 21
-
-/* Always-on power area */
-#define R8A77995_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A77995_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a779a0-sysc.h b/include/dt-bindings/power/r8a779a0-sysc.h
deleted file mode 100644
index 57929e4..0000000
--- a/include/dt-bindings/power/r8a779a0-sysc.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2020 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_POWER_R8A779A0_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A779A0_SYSC_H__
-
-/*
- * These power domain indices match the Power Domain Register Numbers (PDR)
- */
-
-#define R8A779A0_PD_A1E0D0C0 0
-#define R8A779A0_PD_A1E0D0C1 1
-#define R8A779A0_PD_A1E0D1C0 2
-#define R8A779A0_PD_A1E0D1C1 3
-#define R8A779A0_PD_A1E1D0C0 4
-#define R8A779A0_PD_A1E1D0C1 5
-#define R8A779A0_PD_A1E1D1C0 6
-#define R8A779A0_PD_A1E1D1C1 7
-#define R8A779A0_PD_A2E0D0 16
-#define R8A779A0_PD_A2E0D1 17
-#define R8A779A0_PD_A2E1D0 18
-#define R8A779A0_PD_A2E1D1 19
-#define R8A779A0_PD_A3E0 20
-#define R8A779A0_PD_A3E1 21
-#define R8A779A0_PD_3DG_A 24
-#define R8A779A0_PD_3DG_B 25
-#define R8A779A0_PD_A1CNN2 32
-#define R8A779A0_PD_A1DSP0 33
-#define R8A779A0_PD_A2IMP01 34
-#define R8A779A0_PD_A2DP0 35
-#define R8A779A0_PD_A2CV0 36
-#define R8A779A0_PD_A2CV1 37
-#define R8A779A0_PD_A2CV4 38
-#define R8A779A0_PD_A2CV6 39
-#define R8A779A0_PD_A2CN2 40
-#define R8A779A0_PD_A1CNN0 41
-#define R8A779A0_PD_A2CN0 42
-#define R8A779A0_PD_A3IR 43
-#define R8A779A0_PD_A1CNN1 44
-#define R8A779A0_PD_A1DSP1 45
-#define R8A779A0_PD_A2IMP23 46
-#define R8A779A0_PD_A2DP1 47
-#define R8A779A0_PD_A2CV2 48
-#define R8A779A0_PD_A2CV3 49
-#define R8A779A0_PD_A2CV5 50
-#define R8A779A0_PD_A2CV7 51
-#define R8A779A0_PD_A2CN1 52
-#define R8A779A0_PD_A3VIP0 56
-#define R8A779A0_PD_A3VIP1 57
-#define R8A779A0_PD_A3VIP2 58
-#define R8A779A0_PD_A3VIP3 59
-#define R8A779A0_PD_A3ISP01 60
-#define R8A779A0_PD_A3ISP23 61
-
-/* Always-on power area */
-#define R8A779A0_PD_ALWAYS_ON 64
-
-#endif /* __DT_BINDINGS_POWER_R8A779A0_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a779f0-sysc.h b/include/dt-bindings/power/r8a779f0-sysc.h
deleted file mode 100644
index cde1536..0000000
--- a/include/dt-bindings/power/r8a779f0-sysc.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
-/*
- * Copyright (C) 2021 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_POWER_R8A779F0_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A779F0_SYSC_H__
-
-/*
- * These power domain indices match the Power Domain Register Numbers (PDR)
- */
-
-#define R8A779F0_PD_A1E0D0C0 0
-#define R8A779F0_PD_A1E0D0C1 1
-#define R8A779F0_PD_A1E0D1C0 2
-#define R8A779F0_PD_A1E0D1C1 3
-#define R8A779F0_PD_A1E1D0C0 4
-#define R8A779F0_PD_A1E1D0C1 5
-#define R8A779F0_PD_A1E1D1C0 6
-#define R8A779F0_PD_A1E1D1C1 7
-#define R8A779F0_PD_A2E0D0 16
-#define R8A779F0_PD_A2E0D1 17
-#define R8A779F0_PD_A2E1D0 18
-#define R8A779F0_PD_A2E1D1 19
-#define R8A779F0_PD_A3E0 20
-#define R8A779F0_PD_A3E1 21
-
-/* Always-on power area */
-#define R8A779F0_PD_ALWAYS_ON 64
-
-#endif /* __DT_BINDINGS_POWER_R8A779A0_SYSC_H__*/
diff --git a/include/dt-bindings/power/r8a779g0-sysc.h b/include/dt-bindings/power/r8a779g0-sysc.h
deleted file mode 100644
index c7b139f..0000000
--- a/include/dt-bindings/power/r8a779g0-sysc.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (C) 2022 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_POWER_R8A779G0_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A779G0_SYSC_H__
-
-/*
- * These power domain indices match the Power Domain Register Numbers (PDR)
- */
-
-#define R8A779G0_PD_A1E0D0C0 0
-#define R8A779G0_PD_A1E0D0C1 1
-#define R8A779G0_PD_A1E0D1C0 2
-#define R8A779G0_PD_A1E0D1C1 3
-#define R8A779G0_PD_A2E0D0 16
-#define R8A779G0_PD_A2E0D1 17
-#define R8A779G0_PD_A3E0 20
-#define R8A779G0_PD_A33DGA 24
-#define R8A779G0_PD_A23DGB 25
-#define R8A779G0_PD_A1DSP0 33
-#define R8A779G0_PD_A2IMP01 34
-#define R8A779G0_PD_A2PSC 35
-#define R8A779G0_PD_A2CV0 36
-#define R8A779G0_PD_A2CV1 37
-#define R8A779G0_PD_A1CNN0 41
-#define R8A779G0_PD_A2CN0 42
-#define R8A779G0_PD_A3IR 43
-#define R8A779G0_PD_A1DSP1 45
-#define R8A779G0_PD_A2IMP23 46
-#define R8A779G0_PD_A2DMA 47
-#define R8A779G0_PD_A2CV2 48
-#define R8A779G0_PD_A2CV3 49
-#define R8A779G0_PD_A1DSP2 53
-#define R8A779G0_PD_A1DSP3 54
-#define R8A779G0_PD_A3VIP0 56
-#define R8A779G0_PD_A3VIP1 57
-#define R8A779G0_PD_A3VIP2 58
-#define R8A779G0_PD_A3ISP0 60
-#define R8A779G0_PD_A3ISP1 61
-#define R8A779G0_PD_A3DUL 62
-
-/* Always-on power area */
-#define R8A779G0_PD_ALWAYS_ON 64
-
-#endif /* __DT_BINDINGS_POWER_R8A779G0_SYSC_H__*/
diff --git a/include/dt-bindings/power/renesas,r8a779h0-sysc.h b/include/dt-bindings/power/renesas,r8a779h0-sysc.h
deleted file mode 100644
index f27976f..0000000
--- a/include/dt-bindings/power/renesas,r8a779h0-sysc.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (C) 2023 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__
-#define __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__
-
-/*
- * These power domain indices match the Power Domain Register Numbers (PDR)
- */
-
-#define R8A779H0_PD_A1E0D0C0 0
-#define R8A779H0_PD_A1E0D0C1 1
-#define R8A779H0_PD_A1E0D0C2 2
-#define R8A779H0_PD_A1E0D0C3 3
-#define R8A779H0_PD_A2E0D0 16
-#define R8A779H0_PD_A3CR0 21
-#define R8A779H0_PD_A3CR1 22
-#define R8A779H0_PD_A3CR2 23
-#define R8A779H0_PD_A33DGA 24
-#define R8A779H0_PD_A23DGB 25
-#define R8A779H0_PD_C4 31
-#define R8A779H0_PD_A1DSP0 33
-#define R8A779H0_PD_A2IMP01 34
-#define R8A779H0_PD_A2PSC 35
-#define R8A779H0_PD_A2CV0 36
-#define R8A779H0_PD_A2CV1 37
-#define R8A779H0_PD_A3IMR0 38
-#define R8A779H0_PD_A3IMR1 39
-#define R8A779H0_PD_A3VC 40
-#define R8A779H0_PD_A2CN0 42
-#define R8A779H0_PD_A1CN0 44
-#define R8A779H0_PD_A1DSP1 45
-#define R8A779H0_PD_A2DMA 47
-#define R8A779H0_PD_A2CV2 48
-#define R8A779H0_PD_A2CV3 49
-#define R8A779H0_PD_A3IMR2 50
-#define R8A779H0_PD_A3IMR3 51
-#define R8A779H0_PD_A3PCI 52
-#define R8A779H0_PD_A2PCIPHY 53
-#define R8A779H0_PD_A3VIP0 56
-#define R8A779H0_PD_A3VIP2 58
-#define R8A779H0_PD_A3ISP0 60
-#define R8A779H0_PD_A3DUL 62
-
-/* Always-on power area */
-#define R8A779H0_PD_ALWAYS_ON 64
-
-#endif /* __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__ */
diff --git a/include/ext_common.h b/include/ext_common.h
index b09bbde..6e17fbd 100644
--- a/include/ext_common.h
+++ b/include/ext_common.h
@@ -173,20 +173,38 @@
__le32 bg_reserved;
};
-/* The ext2 inode. */
+/**
+ * struct ext2_inode - ext2 inode
+ *
+ * For details see Linux file
+ * Documentation/filesystems/ext4/inodes.rst.
+ */
struct ext2_inode {
+ /** @mode: file mode */
__le16 mode;
+ /** @uid: lower 16 bits of owner UID */
__le16 uid;
+ /** @size: lower 32 bits of file size */
__le32 size;
+ /** @atime: last access time */
__le32 atime;
+ /** @ctime: last change time */
__le32 ctime;
+ /** @mtime: last modification time */
__le32 mtime;
+ /** @dtime: deletion time */
__le32 dtime;
+ /** @gid: lower 16 bits of group ID */
__le16 gid;
+ /** @nlinks: number of hard links */
__le16 nlinks;
- __le32 blockcnt; /* Blocks of either 512 or block_size bytes */
+ /** @blockcnt: lower 32 bit of block count */
+ __le32 blockcnt;
+ /** @flags: inode flags */
__le32 flags;
+ /** @osd1: operating system specific data */
__le32 osd1;
+ /** @b: block map or extent tree */
union {
struct datablocks {
__le32 dir_blocks[INDIRECT_BLOCKS];
@@ -197,10 +215,19 @@
char symlink[60];
char inline_data[60];
} b;
+ /** @version: file version (for NFS) */
__le32 version;
+ /** @acl: lower 32 bit of extended attribute block */
__le32 acl;
- __le32 size_high; /* previously dir_acl, but never used */
+ /** @size_high - dir_acl on ext2/3, upper 32 size bits on ext4
+ *
+ * In ext2/3 this field was named i_dir_acl, though it was usually set
+ * to zero and never used.
+ */
+ __le32 size_high;
+ /** @fragment_addr - (obsolete) fragment address */
__le32 fragment_addr;
+ /** @osd2: operating system specific data */
__le32 osd2[3];
};
diff --git a/include/fs.h b/include/fs.h
index ef540e7..6372756 100644
--- a/include/fs.h
+++ b/include/fs.h
@@ -25,7 +25,7 @@
* do_fat_fsload - Run the fatload command
*
* @cmdtp: Command information for fatload
- * @flag: Command flags (CMD_FLAG_...)
+ * @flag: Command flags (CMD_FLAG\_...)
* @argc: Number of arguments
* @argv: List of arguments
* Return: result (see enum command_ret_t)
@@ -37,7 +37,7 @@
* do_ext2load - Run the ext2load command
*
* @cmdtp: Command information for ext2load
- * @flag: Command flags (CMD_FLAG_...)
+ * @flag: Command flags (CMD_FLAG\_...)
* @argc: Number of arguments
* @argv: List of arguments
* Return: result (see enum command_ret_t)
@@ -145,7 +145,7 @@
* @offset: offset in the file from where to start reading
* @len: the number of bytes to read. Use 0 to read entire file.
* @actread: returns the actual number of bytes read
- * Return: 0 if OK with valid *actread, -1 on error conditions
+ * Return: 0 if OK with valid @actread, -1 on error conditions
*/
int fs_read(const char *filename, ulong addr, loff_t offset, loff_t len,
loff_t *actread);
@@ -160,7 +160,7 @@
* @offset: offset in the file from where to start writing
* @len: the number of bytes to write
* @actwrite: returns the actual number of bytes written
- * Return: 0 if OK with valid *actwrite, -1 on error conditions
+ * Return: 0 if OK with valid @actwrite, -1 on error conditions
*/
int fs_write(const char *filename, ulong addr, loff_t offset, loff_t len,
loff_t *actwrite);
@@ -186,57 +186,73 @@
unsigned int type;
/** @size: file size */
loff_t size;
- /** @flags: attribute flags (FS_ATTR_*) */
+ /** @attr: attribute flags (FS_ATTR_*) */
u32 attr;
- /** create_time: time of creation */
+ /** @create_time: time of creation */
struct rtc_time create_time;
- /** access_time: time of last access */
+ /** @access_time: time of last access */
struct rtc_time access_time;
- /** change_time: time of last modification */
+ /** @change_time: time of last modification */
struct rtc_time change_time;
- /** name: file name */
+ /** @name: file name */
char name[FS_DIRENT_NAME_LEN];
};
-/* Note: fs_dir_stream should be treated as opaque to the user of fs layer */
+/**
+ * struct fs_dir_stream - Structure representing an opened directory
+ *
+ * Struct fs_dir_stream should be treated opaque to the user of fs layer.
+ * The fields @desc and @part are used by the fs layer.
+ * File system drivers pass additional private fields with the pointers
+ * to this structure.
+ *
+ * @desc: block device descriptor
+ * @part: partition number
+ */
struct fs_dir_stream {
- /* private to fs. layer: */
struct blk_desc *desc;
int part;
};
-/*
+/**
* fs_opendir - Open a directory
*
- * @filename: the path to directory to open
- * Return: a pointer to the directory stream or NULL on error and errno
- * set appropriately
+ * .. note::
+ * The returned struct fs_dir_stream should be treated opaque to the
+ * user of the fs layer.
+ *
+ * @filename: path to the directory to open
+ * Return:
+ * A pointer to the directory stream or NULL on error and errno set
+ * appropriately
*/
struct fs_dir_stream *fs_opendir(const char *filename);
-/*
+/**
* fs_readdir - Read the next directory entry in the directory stream.
*
- * Works in an analogous way to posix readdir(). The previously returned
- * directory entry is no longer valid after calling fs_readdir() again.
+ * fs_readir works in an analogous way to posix readdir().
+ * The previously returned directory entry is no longer valid after calling
+ * fs_readdir() again.
* After fs_closedir() is called, the returned directory entry is no
* longer valid.
*
* @dirs: the directory stream
- * Return: the next directory entry (only valid until next fs_readdir() or
- * fs_closedir() call, do not attempt to free()) or NULL if the end of
- * the directory is reached.
+ * Return:
+ * the next directory entry (only valid until next fs_readdir() or
+ * fs_closedir() call, do not attempt to free()) or NULL if the end of
+ * the directory is reached.
*/
struct fs_dirent *fs_readdir(struct fs_dir_stream *dirs);
-/*
+/**
* fs_closedir - close a directory stream
*
* @dirs: the directory stream
*/
void fs_closedir(struct fs_dir_stream *dirs);
-/*
+/**
* fs_unlink - delete a file or directory
*
* If a given name is a directory, it will be deleted only if it's empty
@@ -246,7 +262,7 @@
*/
int fs_unlink(const char *filename);
-/*
+/**
* fs_mkdir - Create a directory
*
* @filename: Name of directory to create
@@ -292,7 +308,7 @@
* do_fs_types - List supported filesystems.
*
* @cmdtp: Command information for fstypes
- * @flag: Command flags (CMD_FLAG_...)
+ * @flag: Command flags (CMD_FLAG\_...)
* @argc: Number of arguments
* @argv: List of arguments
* Return: result (see enum command_ret_t)
diff --git a/include/irq.h b/include/irq.h
index 5638c10..0fbc1a5 100644
--- a/include/irq.h
+++ b/include/irq.h
@@ -200,6 +200,20 @@
*/
int irq_read_and_clear(struct irq *irq);
+/**
+ * irq_get_interrupt_parent() - returns the interrupt parent
+ *
+ * Walks the devicetree and returns the interrupt parent's ofnode
+ * for the specified device.
+ *
+ * @dev: device
+ * @interrupt_parent: The interrupt parent's ofnode'
+ * Return: 0 success, or error value
+ *
+ */
+int irq_get_interrupt_parent(const struct udevice *dev,
+ struct udevice **interrupt_parent);
+
struct phandle_2_arg;
/**
* irq_get_by_phandle() - Get an irq by its phandle information (of-platadata)
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 655a6d1..b8b207f 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -308,7 +308,7 @@
SNOR_F_BROKEN_RESET = BIT(6),
SNOR_F_SOFT_RESET = BIT(7),
SNOR_F_IO_MODE_EN_VOLATILE = BIT(8),
-#if defined(CONFIG_SPI_ADVANCE)
+#if defined(CONFIG_SPI_STACKED_PARALLEL)
SNOR_F_HAS_STACKED = BIT(9),
SNOR_F_HAS_PARALLEL = BIT(10),
#else
diff --git a/include/lmb.h b/include/lmb.h
index e46abf4..2201d6f 100644
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -14,6 +14,9 @@
* Copyright (C) 2001 Peter Bergner, IBM Corp.
*/
+#define LMB_ALLOC_ANYWHERE 0
+#define LMB_ALIST_INITIAL_SIZE 4
+
/**
* enum lmb_flags - definition of memory region attributes
* @LMB_NONE: no special request
@@ -95,32 +98,6 @@
phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size);
phys_size_t lmb_get_free_size(phys_addr_t addr);
-/**
- * lmb_alloc_flags() - Allocate memory region with specified attributes
- * @size: Size of the region requested
- * @align: Alignment of the memory region requested
- * @flags: Memory region attributes to be set
- *
- * Allocate a region of memory with the attributes specified through the
- * parameter.
- *
- * Return: base address on success, 0 on error
- */
-phys_addr_t lmb_alloc_flags(phys_size_t size, ulong align, uint flags);
-
-/**
- * lmb_alloc_base_flags() - Allocate specified memory region with specified attributes
- * @size: Size of the region requested
- * @align: Alignment of the memory region requested
- * @max_addr: Maximum address of the requested region
- * @flags: Memory region attributes to be set
- *
- * Allocate a region of memory with the attributes specified through the
- * parameter. The max_addr parameter is used to specify the maximum address
- * below which the requested region should be allocated.
- *
- * Return: base address on success, 0 on error
- */
phys_addr_t lmb_alloc_base_flags(phys_size_t size, ulong align,
phys_addr_t max_addr, uint flags);
diff --git a/include/serial.h b/include/serial.h
index eabc49f..e5f6d98 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -124,6 +124,7 @@
enum serial_chip_type {
SERIAL_CHIP_UNKNOWN = -1,
SERIAL_CHIP_16550_COMPATIBLE,
+ SERIAL_CHIP_PL01X,
};
enum adr_space_type {
diff --git a/lib/Kconfig b/lib/Kconfig
index fc2db74..56ffdfa 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -315,6 +315,22 @@
by the operating system. It defines platform-independent interfaces
for configuration and power management monitoring.
+config ACPI_PARKING_PROTOCOL
+ bool "Support ACPI parking protocol method"
+ depends on GENERATE_ACPI_TABLE
+ depends on ARMV8_MULTIENTRY
+ depends on BLOBLIST_TABLES
+ default y if !SEC_FIRMWARE_ARMV8_PSCI && !ARMV8_PSCI
+ help
+ Say Y here to support "ACPI parking protocol" enable method
+ for booting Linux.
+
+ To use this feature, you must do:
+ - Bring secondary CPUs into U-Boot proper in a board-specific
+ manner. This must be done *after* relocation. Otherwise, the
+ secondary CPUs will spin in unprotected memory-area because the
+ master CPU protects the relocated spin code.
+
config SPL_TINY_MEMSET
bool "Use a very small memset() in SPL"
depends on SPL
@@ -988,12 +1004,15 @@
config BLOBLIST_TABLES
bool "Put tables in a bloblist"
- depends on X86 && BLOBLIST
+ depends on BLOBLIST
+ default y if (ARM && EFI_LOADER && GENERATE_ACPI_TABLE)
+ default n
help
- Normally tables are placed at address 0xf0000 and can be up to 64KB
- long. With this option, tables are instead placed in the bloblist
- with a pointer from 0xf0000. The size can then be larger and the
- tables can be placed high in memory.
+ On x86 normally tables are placed at address 0xf0000 and can be up
+ to 64KB long. With this option, tables are instead placed in the
+ bloblist with a pointer from 0xf0000. The size can then be larger
+ and the tables can be placed high in memory.
+ On other architectures the tables are always placed in high memory.
config GENERATE_SMBIOS_TABLE
bool "Generate an SMBIOS (System Management BIOS) table"
diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c
index 6dbfdb2..150f750 100644
--- a/lib/acpi/acpi_table.c
+++ b/lib/acpi/acpi_table.c
@@ -5,15 +5,28 @@
* Copyright 2019 Google LLC
*/
-#include <dm.h>
+#include <bloblist.h>
#include <cpu.h>
+#include <dm.h>
+#include <efi_api.h>
+#include <efi_loader.h>
#include <log.h>
#include <mapmem.h>
#include <tables_csum.h>
+#include <serial.h>
#include <version_string.h>
#include <acpi/acpi_table.h>
+#include <acpi/acpi_device.h>
#include <asm/global_data.h>
#include <dm/acpi.h>
+#include <linux/sizes.h>
+#include <linux/log2.h>
+
+enum {
+ TABLE_SIZE = SZ_64K,
+};
+
+DECLARE_GLOBAL_DATA_PTR;
/*
* OEM_REVISION is 32-bit unsigned number. It should be increased only when
@@ -61,9 +74,9 @@
{
switch (table) {
case ACPITAB_FADT:
- return ACPI_FADT_REV_ACPI_3_0;
+ return ACPI_FADT_REV_ACPI_6_0;
case ACPITAB_MADT:
- return ACPI_MADT_REV_ACPI_3_0;
+ return ACPI_MADT_REV_ACPI_6_2;
case ACPITAB_MCFG:
return ACPI_MCFG_REV_ACPI_3_0;
case ACPITAB_TCPA:
@@ -105,6 +118,10 @@
return 1;
case ACPITAB_SPCR:
return 2;
+ case ACPITAB_PPTT: /* ACPI 6.2: 1 */
+ return 1;
+ case ACPITAB_GTDT: /* ACPI 6.2: 2, ACPI 6.3: 3 */
+ return 2;
default:
return -EINVAL;
}
@@ -151,55 +168,148 @@
struct acpi_rsdt *rsdt;
struct acpi_xsdt *xsdt;
- /* The RSDT is mandatory while the XSDT is not */
- rsdt = ctx->rsdt;
+ /* On legacy x86 platforms the RSDT is mandatory while the XSDT is not.
+ * On other platforms there might be no memory below 4GiB, thus RSDT is NULL.
+ */
+ if (ctx->rsdt) {
+ rsdt = ctx->rsdt;
+
+ /* This should always be MAX_ACPI_TABLES */
+ entries_num = ARRAY_SIZE(rsdt->entry);
+
+ for (i = 0; i < entries_num; i++) {
+ if (rsdt->entry[i] == 0)
+ break;
+ }
- /* This should always be MAX_ACPI_TABLES */
- entries_num = ARRAY_SIZE(rsdt->entry);
+ if (i >= entries_num) {
+ log_err("ACPI: Error: too many tables\n");
+ return -E2BIG;
+ }
- for (i = 0; i < entries_num; i++) {
- if (rsdt->entry[i] == 0)
- break;
+ /* Add table to the RSDT */
+ rsdt->entry[i] = nomap_to_sysmem(table);
+
+ /* Fix RSDT length or the kernel will assume invalid entries */
+ rsdt->header.length = sizeof(struct acpi_table_header) +
+ (sizeof(u32) * (i + 1));
+
+ /* Re-calculate checksum */
+ rsdt->header.checksum = 0;
+ rsdt->header.checksum = table_compute_checksum((u8 *)rsdt,
+ rsdt->header.length);
}
- if (i >= entries_num) {
- log_err("ACPI: Error: too many tables\n");
- return -E2BIG;
+ if (ctx->xsdt) {
+ /*
+ * And now the same thing for the XSDT. We use the same index as for
+ * now we want the XSDT and RSDT to always be in sync in U-Boot
+ */
+ xsdt = ctx->xsdt;
+
+ /* This should always be MAX_ACPI_TABLES */
+ entries_num = ARRAY_SIZE(xsdt->entry);
+
+ for (i = 0; i < entries_num; i++) {
+ if (xsdt->entry[i] == 0)
+ break;
+ }
+
+ if (i >= entries_num) {
+ log_err("ACPI: Error: too many tables\n");
+ return -E2BIG;
+ }
+
+ /* Add table to the XSDT */
+ xsdt->entry[i] = nomap_to_sysmem(table);
+
+ /* Fix XSDT length */
+ xsdt->header.length = sizeof(struct acpi_table_header) +
+ (sizeof(u64) * (i + 1));
+
+ /* Re-calculate checksum */
+ xsdt->header.checksum = 0;
+ xsdt->header.checksum = table_compute_checksum((u8 *)xsdt,
+ xsdt->header.length);
}
- /* Add table to the RSDT */
- rsdt->entry[i] = nomap_to_sysmem(table);
+ return 0;
+}
- /* Fix RSDT length or the kernel will assume invalid entries */
- rsdt->header.length = sizeof(struct acpi_table_header) +
- (sizeof(u32) * (i + 1));
+int acpi_write_fadt(struct acpi_ctx *ctx, const struct acpi_writer *entry)
+{
+ struct acpi_table_header *header;
+ struct acpi_fadt *fadt;
- /* Re-calculate checksum */
- rsdt->header.checksum = 0;
- rsdt->header.checksum = table_compute_checksum((u8 *)rsdt,
- rsdt->header.length);
+ fadt = ctx->current;
+ header = &fadt->header;
- /*
- * And now the same thing for the XSDT. We use the same index as for
- * now we want the XSDT and RSDT to always be in sync in U-Boot
- */
- xsdt = ctx->xsdt;
+ memset((void *)fadt, '\0', sizeof(struct acpi_fadt));
- /* Add table to the XSDT */
- xsdt->entry[i] = nomap_to_sysmem(table);
+ acpi_fill_header(header, "FACP");
+ header->length = sizeof(struct acpi_fadt);
+ header->revision = acpi_get_table_revision(ACPITAB_FADT);
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
+ memcpy(header->creator_id, ASLC_ID, 4);
+ header->creator_revision = 1;
+ fadt->minor_revision = 2;
+
+ fadt->x_firmware_ctrl = map_to_sysmem(ctx->facs);
+ fadt->x_dsdt = map_to_sysmem(ctx->dsdt);
+
+ if (fadt->x_firmware_ctrl < 0x100000000ULL)
+ fadt->firmware_ctrl = fadt->x_firmware_ctrl;
+
+ if (fadt->x_dsdt < 0x100000000ULL)
+ fadt->dsdt = fadt->x_dsdt;
- /* Fix XSDT length */
- xsdt->header.length = sizeof(struct acpi_table_header) +
- (sizeof(u64) * (i + 1));
+ fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED;
- /* Re-calculate checksum */
- xsdt->header.checksum = 0;
- xsdt->header.checksum = table_compute_checksum((u8 *)xsdt,
- xsdt->header.length);
+ acpi_fill_fadt(fadt);
+
+ header->checksum = table_compute_checksum(fadt, header->length);
+
+ return acpi_add_fadt(ctx, fadt);
+}
+
+ACPI_WRITER(5fadt, "FADT", acpi_write_fadt, 0);
+
+int acpi_write_madt(struct acpi_ctx *ctx, const struct acpi_writer *entry)
+{
+ struct acpi_table_header *header;
+ struct acpi_madt *madt;
+ void *current;
+
+ madt = ctx->current;
+
+ memset(madt, '\0', sizeof(struct acpi_madt));
+ header = &madt->header;
+
+ /* Fill out header fields */
+ acpi_fill_header(header, "APIC");
+ header->length = sizeof(struct acpi_madt);
+ header->revision = acpi_get_table_revision(ACPITAB_MADT);
+
+ acpi_inc(ctx, sizeof(struct acpi_madt));
+ /* TODO: Get rid of acpi_fill_madt and use driver model */
+ current = acpi_fill_madt(madt, ctx);
+
+ /* (Re)calculate length and checksum */
+ header->length = (uintptr_t)current - (uintptr_t)madt;
+
+ if (IS_ENABLED(CONFIG_ACPI_PARKING_PROTOCOL))
+ acpi_write_park(madt);
+
+ header->checksum = table_compute_checksum((void *)madt, header->length);
+ acpi_add_table(ctx, madt);
+ ctx->current = (void *)madt + madt->header.length;
return 0;
}
+ACPI_WRITER(5madt, "MADT", acpi_write_madt, 0);
+
void acpi_create_dbg2(struct acpi_dbg2_header *dbg2,
int port_type, int port_subtype,
struct acpi_gen_regaddr *address, u32 address_size,
@@ -262,3 +372,451 @@
header->length = current - (uintptr_t)dbg2;
header->checksum = table_compute_checksum(dbg2, header->length);
}
+
+int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,
+ uint access_size)
+{
+ struct acpi_dbg2_header *dbg2 = ctx->current;
+ char path[ACPI_PATH_MAX];
+ struct acpi_gen_regaddr address;
+ u64 addr;
+ int ret;
+
+ if (!device_active(dev)) {
+ log_info("Device not enabled\n");
+ return -EACCES;
+ }
+ /*
+ * PCI devices don't remember their resource allocation information in
+ * U-Boot at present. We assume that MMIO is used for the UART and that
+ * the address space is 32 bytes: ns16550 uses 8 registers of up to
+ * 32-bits each. This is only for debugging so it is not a big deal.
+ */
+ addr = dm_pci_read_bar32(dev, 0);
+ log_debug("UART addr %lx\n", (ulong)addr);
+
+ ret = acpi_device_path(dev, path, sizeof(path));
+ if (ret)
+ return log_msg_ret("path", ret);
+
+ memset(&address, '\0', sizeof(address));
+ address.space_id = ACPI_ADDRESS_SPACE_MEMORY;
+ address.addrl = (uint32_t)addr;
+ address.addrh = (uint32_t)((addr >> 32) & 0xffffffff);
+ address.access_size = access_size;
+
+ ret = acpi_device_path(dev, path, sizeof(path));
+ if (ret)
+ return log_msg_ret("path", ret);
+ acpi_create_dbg2(dbg2, ACPI_DBG2_SERIAL_PORT,
+ ACPI_DBG2_16550_COMPATIBLE, &address, 0x1000, path);
+
+ acpi_inc_align(ctx, dbg2->header.length);
+ acpi_add_table(ctx, dbg2);
+
+ return 0;
+}
+
+static int acpi_write_spcr(struct acpi_ctx *ctx, const struct acpi_writer *entry)
+{
+ struct serial_device_info serial_info = {0};
+ u64 serial_address, serial_offset;
+ struct acpi_table_header *header;
+ struct acpi_spcr *spcr;
+ struct udevice *dev;
+ uint serial_config;
+ uint serial_width;
+ int access_size;
+ int space_id;
+ int ret = -ENODEV;
+
+ spcr = ctx->current;
+ header = &spcr->header;
+
+ memset(spcr, '\0', sizeof(struct acpi_spcr));
+
+ /* Fill out header fields */
+ acpi_fill_header(header, "SPCR");
+ header->length = sizeof(struct acpi_spcr);
+ header->revision = 2;
+
+ /* Read the device once, here. It is reused below */
+ dev = gd->cur_serial_dev;
+ if (dev)
+ ret = serial_getinfo(dev, &serial_info);
+ if (ret)
+ serial_info.type = SERIAL_CHIP_UNKNOWN;
+
+ /* Encode chip type */
+ switch (serial_info.type) {
+ case SERIAL_CHIP_16550_COMPATIBLE:
+ spcr->interface_type = ACPI_DBG2_16550_COMPATIBLE;
+ break;
+ case SERIAL_CHIP_PL01X:
+ spcr->interface_type = ACPI_DBG2_ARM_PL011;
+ break;
+ case SERIAL_CHIP_UNKNOWN:
+ default:
+ spcr->interface_type = ACPI_DBG2_UNKNOWN;
+ break;
+ }
+
+ /* Encode address space */
+ switch (serial_info.addr_space) {
+ case SERIAL_ADDRESS_SPACE_MEMORY:
+ space_id = ACPI_ADDRESS_SPACE_MEMORY;
+ break;
+ case SERIAL_ADDRESS_SPACE_IO:
+ default:
+ space_id = ACPI_ADDRESS_SPACE_IO;
+ break;
+ }
+
+ serial_width = serial_info.reg_width * 8;
+ serial_offset = ((u64)serial_info.reg_offset) << serial_info.reg_shift;
+ serial_address = serial_info.addr + serial_offset;
+
+ /* Encode register access size */
+ switch (serial_info.reg_shift) {
+ case 0:
+ access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+ break;
+ case 1:
+ access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
+ break;
+ case 2:
+ access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+ break;
+ case 3:
+ access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS;
+ break;
+ default:
+ access_size = ACPI_ACCESS_SIZE_UNDEFINED;
+ break;
+ }
+
+ debug("UART type %u @ %llx\n", spcr->interface_type, serial_address);
+
+ /* Fill GAS */
+ spcr->serial_port.space_id = space_id;
+ spcr->serial_port.bit_width = serial_width;
+ spcr->serial_port.bit_offset = 0;
+ spcr->serial_port.access_size = access_size;
+ spcr->serial_port.addrl = lower_32_bits(serial_address);
+ spcr->serial_port.addrh = upper_32_bits(serial_address);
+
+ /* Encode baud rate */
+ switch (serial_info.baudrate) {
+ case 9600:
+ spcr->baud_rate = 3;
+ break;
+ case 19200:
+ spcr->baud_rate = 4;
+ break;
+ case 57600:
+ spcr->baud_rate = 6;
+ break;
+ case 115200:
+ spcr->baud_rate = 7;
+ break;
+ default:
+ spcr->baud_rate = 0;
+ break;
+ }
+
+ serial_config = SERIAL_DEFAULT_CONFIG;
+ if (dev)
+ ret = serial_getconfig(dev, &serial_config);
+
+ spcr->parity = SERIAL_GET_PARITY(serial_config);
+ spcr->stop_bits = SERIAL_GET_STOP(serial_config);
+
+ /* No PCI devices for now */
+ spcr->pci_device_id = 0xffff;
+ spcr->pci_vendor_id = 0xffff;
+
+ /*
+ * SPCR has no clue if the UART base clock speed is different
+ * to the default one. However, the SPCR 1.04 defines baud rate
+ * 0 as a preconfigured state of UART and OS is supposed not
+ * to touch the configuration of the serial device.
+ */
+ if (serial_info.clock != SERIAL_DEFAULT_CLOCK)
+ spcr->baud_rate = 0;
+
+ /* Fix checksum */
+ header->checksum = table_compute_checksum((void *)spcr, header->length);
+
+ acpi_add_table(ctx, spcr);
+ acpi_inc(ctx, spcr->header.length);
+
+ return 0;
+}
+
+ACPI_WRITER(5spcr, "SPCR", acpi_write_spcr, 0);
+
+__weak int acpi_fill_iort(struct acpi_ctx *ctx)
+{
+ return 0;
+}
+
+int acpi_iort_add_its_group(struct acpi_ctx *ctx,
+ const u32 its_count,
+ const u32 *identifiers)
+{
+ struct acpi_iort_node *node;
+ struct acpi_iort_its_group *group;
+ int offset;
+
+ offset = ctx->current - ctx->tab_start;
+
+ node = ctx->current;
+ memset(node, '\0', sizeof(struct acpi_iort_node));
+
+ node->type = ACPI_IORT_NODE_ITS_GROUP;
+ node->revision = 1;
+
+ node->length = sizeof(struct acpi_iort_node);
+ node->length += sizeof(struct acpi_iort_its_group);
+ node->length += sizeof(u32) * its_count;
+
+ group = (struct acpi_iort_its_group *)node->node_data;
+ group->its_count = its_count;
+ memcpy(&group->identifiers, identifiers, sizeof(u32) * its_count);
+
+ ctx->current += node->length;
+
+ return offset;
+}
+
+int acpi_iort_add_named_component(struct acpi_ctx *ctx,
+ const u32 node_flags,
+ const u64 memory_properties,
+ const u8 memory_address_limit,
+ const char *device_name)
+{
+ struct acpi_iort_node *node;
+ struct acpi_iort_named_component *comp;
+ int offset;
+
+ offset = ctx->current - ctx->tab_start;
+
+ node = ctx->current;
+ memset(node, '\0', sizeof(struct acpi_iort_node));
+
+ node->type = ACPI_IORT_NODE_NAMED_COMPONENT;
+ node->revision = 4;
+ node->length = sizeof(struct acpi_iort_node);
+ node->length += sizeof(struct acpi_iort_named_component);
+ node->length += strlen(device_name) + 1;
+
+ comp = (struct acpi_iort_named_component *)node->node_data;
+
+ comp->node_flags = node_flags;
+ comp->memory_properties = memory_properties;
+ comp->memory_address_limit = memory_address_limit;
+ memcpy(comp->device_name, device_name, strlen(device_name) + 1);
+
+ ctx->current += node->length;
+
+ return offset;
+}
+
+int acpi_iort_add_rc(struct acpi_ctx *ctx,
+ const u64 mem_access_properties,
+ const u32 ats_attributes,
+ const u32 pci_segment_number,
+ const u8 memory_address_size_limit,
+ const int num_mappings,
+ const struct acpi_iort_id_mapping *map)
+{
+ struct acpi_iort_id_mapping *mapping;
+ struct acpi_iort_node *node;
+ struct acpi_iort_rc *rc;
+ int offset;
+
+ offset = ctx->current - ctx->tab_start;
+
+ node = ctx->current;
+ memset(node, '\0', sizeof(struct acpi_iort_node));
+
+ node->type = ACPI_IORT_NODE_PCI_ROOT_COMPLEX;
+ node->revision = 2;
+
+ node->length = sizeof(struct acpi_iort_node);
+ node->length += sizeof(struct acpi_iort_rc);
+ node->length += sizeof(struct acpi_iort_id_mapping) * num_mappings;
+
+ rc = (struct acpi_iort_rc *)node->node_data;
+ rc->mem_access_properties = mem_access_properties;
+ rc->ats_attributes = ats_attributes;
+ rc->pci_segment_number = pci_segment_number;
+ rc->memory_address_size_limit = memory_address_size_limit;
+
+ mapping = (struct acpi_iort_id_mapping *)(rc + 1);
+ for (int i = 0; i < num_mappings; i++) {
+ memcpy(mapping, &map[i], sizeof(struct acpi_iort_id_mapping));
+ mapping++;
+ }
+
+ ctx->current += node->length;
+
+ return offset;
+}
+
+int acpi_iort_add_smmu_v3(struct acpi_ctx *ctx,
+ const u64 base_address,
+ const u32 flags,
+ const u64 vatos_address,
+ const u32 model,
+ const u32 event_gsiv,
+ const u32 pri_gsiv,
+ const u32 gerr_gsiv,
+ const u32 sync_gsiv,
+ const u32 pxm,
+ const u32 id_mapping_index,
+ const int num_mappings,
+ const struct acpi_iort_id_mapping *map)
+{
+ struct acpi_iort_node *node;
+ struct acpi_iort_smmu_v3 *smmu;
+ struct acpi_iort_id_mapping *mapping;
+ int offset;
+
+ offset = ctx->current - ctx->tab_start;
+
+ node = ctx->current;
+ memset(node, '\0', sizeof(struct acpi_iort_node));
+
+ node->type = ACPI_IORT_NODE_SMMU_V3;
+ node->revision = 5;
+ node->mapping_count = num_mappings;
+ node->mapping_offset = sizeof(struct acpi_iort_node) + sizeof(struct acpi_iort_smmu_v3);
+
+ node->length = sizeof(struct acpi_iort_node);
+ node->length += sizeof(struct acpi_iort_smmu_v3);
+ node->length += sizeof(struct acpi_iort_id_mapping) * num_mappings;
+
+ smmu = (struct acpi_iort_smmu_v3 *)node->node_data;
+
+ smmu->base_address = base_address;
+ smmu->flags = flags;
+ smmu->vatos_address = vatos_address;
+ smmu->model = model;
+ smmu->event_gsiv = event_gsiv;
+ smmu->pri_gsiv = pri_gsiv;
+ smmu->gerr_gsiv = gerr_gsiv;
+ smmu->sync_gsiv = sync_gsiv;
+ smmu->pxm = pxm;
+ smmu->id_mapping_index = id_mapping_index;
+
+ mapping = (struct acpi_iort_id_mapping *)(smmu + 1);
+ for (int i = 0; i < num_mappings; i++) {
+ memcpy(mapping, &map[i], sizeof(struct acpi_iort_id_mapping));
+ mapping++;
+ }
+
+ ctx->current += node->length;
+
+ return offset;
+}
+
+static int acpi_write_iort(struct acpi_ctx *ctx, const struct acpi_writer *entry)
+{
+ struct acpi_table_iort *iort;
+ struct acpi_iort_node *node;
+ u32 offset;
+ int ret;
+
+ iort = ctx->current;
+ ctx->tab_start = ctx->current;
+ memset(iort, '\0', sizeof(struct acpi_table_iort));
+
+ acpi_fill_header(&iort->header, "IORT");
+ iort->header.revision = 1;
+ iort->header.creator_revision = 1;
+ iort->header.length = sizeof(struct acpi_table_iort);
+ iort->node_offset = sizeof(struct acpi_table_iort);
+
+ acpi_inc(ctx, sizeof(struct acpi_table_iort));
+
+ offset = sizeof(struct acpi_table_iort);
+ ret = acpi_fill_iort(ctx);
+ if (ret) {
+ ctx->current = iort;
+ return log_msg_ret("fill", ret);
+ }
+
+ /* Count nodes filled in */
+ for (node = (void *)iort + iort->node_offset;
+ node->length > 0 && (void *)node < ctx->current;
+ node = (void *)node + node->length)
+ iort->node_count++;
+
+ /* (Re)calculate length and checksum */
+ iort->header.length = ctx->current - (void *)iort;
+ iort->header.checksum = table_compute_checksum((void *)iort, iort->header.length);
+ log_debug("IORT at %p, length %x\n", iort, iort->header.length);
+
+ /* Drop the table if it is empty */
+ if (iort->header.length == sizeof(struct acpi_table_iort))
+ return log_msg_ret("fill", -ENOENT);
+ acpi_add_table(ctx, iort);
+
+ return 0;
+}
+
+ACPI_WRITER(5iort, "IORT", acpi_write_iort, 0);
+
+/*
+ * Allocate memory for ACPI tables and write ACPI tables to the
+ * allocated buffer.
+ *
+ * Return: status code
+ */
+static int alloc_write_acpi_tables(void)
+{
+ u64 table_end;
+ void *addr;
+
+ if (IS_ENABLED(CONFIG_X86) ||
+ IS_ENABLED(CONFIG_QFW_ACPI) ||
+ IS_ENABLED(CONFIG_SANDBOX)) {
+ log_debug("Skipping writing ACPI tables as already done\n");
+ return 0;
+ }
+
+ if (!IS_ENABLED(CONFIG_BLOBLIST_TABLES)) {
+ log_debug("Skipping writing ACPI tables as BLOBLIST_TABLES is not selected\n");
+ return 0;
+ }
+
+ /* Align the table to a 4KB boundary to keep EFI happy */
+ addr = bloblist_add(BLOBLISTT_ACPI_TABLES, TABLE_SIZE,
+ ilog2(SZ_4K));
+
+ if (!addr)
+ return log_msg_ret("mem", -ENOMEM);
+
+ gd->arch.table_start_high = virt_to_phys(addr);
+ gd->arch.table_end_high = gd->arch.table_start_high + TABLE_SIZE;
+
+ table_end = write_acpi_tables(gd->arch.table_start_high);
+ if (!table_end) {
+ log_err("Can't create ACPI configuration table\n");
+ return -EINTR;
+ }
+
+ log_debug("- wrote 'acpi' to %lx, end %llx\n", gd->arch.table_start_high, table_end);
+ if (table_end > gd->arch.table_end_high) {
+ log_err("Out of space for configuration tables: need %llx, have %x\n",
+ table_end - gd->arch.table_start_high, TABLE_SIZE);
+ return log_msg_ret("acpi", -ENOSPC);
+ }
+
+ log_debug("- done writing tables\n");
+
+ return 0;
+}
+
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, alloc_write_acpi_tables);
diff --git a/lib/acpi/acpigen.c b/lib/acpi/acpigen.c
index ecff5a5..fa9dad3 100644
--- a/lib/acpi/acpigen.c
+++ b/lib/acpi/acpigen.c
@@ -361,6 +361,17 @@
acpigen_emit_byte(ctx, pblock_len);
}
+void acpigen_write_processor_device(struct acpi_ctx *ctx, uint cpuindex)
+{
+ char pscope[16];
+
+ snprintf(pscope, sizeof(pscope), ACPI_CPU_STRING, cpuindex);
+ acpigen_write_device(ctx, pscope);
+ acpigen_write_name_string(ctx, "_HID", "ACPI0007");
+ acpigen_write_name_integer(ctx, "_UID", cpuindex);
+ acpigen_pop_len(ctx); /* Device */
+}
+
void acpigen_write_processor_package(struct acpi_ctx *ctx,
const char *const name,
const uint first_core,
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 69b2c93..066f0ca 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -545,6 +545,8 @@
config EFI_HTTP_BOOT
bool "EFI HTTP Boot support"
+ depends on NET || NET_LWIP
+ select CMD_NET
select CMD_DNS
select CMD_WGET
select BLKMAP
diff --git a/lib/efi_loader/dtbdump.c b/lib/efi_loader/dtbdump.c
index 9f1d8fb..a3d59a2 100644
--- a/lib/efi_loader/dtbdump.c
+++ b/lib/efi_loader/dtbdump.c
@@ -225,7 +225,7 @@
* @systable: system table
* Return: device tree or NULL
*/
-void *get_dtb(struct efi_system_table *systable)
+static void *get_dtb(struct efi_system_table *systable)
{
void *dtb = NULL;
efi_uintn_t i;
@@ -246,7 +246,7 @@
* @pos: UTF-16 string
* Return: pointer to first non-whitespace
*/
-u16 *skip_whitespace(u16 *pos)
+static u16 *skip_whitespace(u16 *pos)
{
for (; *pos && *pos <= 0x20; ++pos)
;
@@ -260,7 +260,7 @@
* @keyword: keyword to be searched
* Return: true fi @string starts with the keyword
*/
-bool starts_with(u16 *string, u16 *keyword)
+static bool starts_with(u16 *string, u16 *keyword)
{
for (; *keyword; ++string, ++keyword) {
if (*string != *keyword)
@@ -272,7 +272,7 @@
/**
* do_help() - print help
*/
-void do_help(void)
+static void do_help(void)
{
error(u"dump - print device-tree\r\n");
error(u"load <dtb> - load device-tree from file\r\n");
@@ -332,7 +332,7 @@
* @filename: file name
* Return: status code
*/
-efi_status_t do_load(u16 *filename)
+static efi_status_t do_load(u16 *filename)
{
struct efi_dt_fixup_protocol *dt_fixup_prot;
struct efi_simple_file_system_protocol *file_system;
@@ -469,7 +469,7 @@
* @filename: file name
* Return: status code
*/
-efi_status_t do_save(u16 *filename)
+static efi_status_t do_save(u16 *filename)
{
struct efi_simple_file_system_protocol *file_system;
efi_uintn_t dtb_size;
diff --git a/lib/efi_loader/efi_bootbin.c b/lib/efi_loader/efi_bootbin.c
index a87006b..bf38392 100644
--- a/lib/efi_loader/efi_bootbin.c
+++ b/lib/efi_loader/efi_bootbin.c
@@ -137,6 +137,7 @@
*/
file_path = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE,
(uintptr_t)source_buffer,
+ (uintptr_t)source_buffer +
source_size);
/*
* Make sure that device for device_path exist
diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
index a3aa2b8..f9b5988 100644
--- a/lib/efi_loader/efi_bootmgr.c
+++ b/lib/efi_loader/efi_bootmgr.c
@@ -385,7 +385,7 @@
* @ctx: event context
* Return: status code
*/
-efi_status_t efi_bootmgr_release_uridp(struct uridp_context *ctx)
+static efi_status_t efi_bootmgr_release_uridp(struct uridp_context *ctx)
{
efi_status_t ret = EFI_SUCCESS;
efi_status_t ret2 = EFI_SUCCESS;
diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c
index 9de3b95..d744458 100644
--- a/lib/efi_loader/efi_device_path.c
+++ b/lib/efi_loader/efi_device_path.c
@@ -1073,7 +1073,8 @@
efi_get_image_parameters(&image_addr, &image_size);
dp = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE,
- (uintptr_t)image_addr, image_size);
+ (uintptr_t)image_addr,
+ (uintptr_t)image_addr + image_size);
} else if (IS_ENABLED(CONFIG_NETDEVICES) && !strcmp(dev, "Net")) {
dp = efi_dp_from_eth();
} else if (!strcmp(dev, "Uart")) {
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index 93a9a5a..1f3de0a 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -561,11 +561,9 @@
{
struct efi_disk_obj *disk;
struct blk_desc *desc;
- int diskid;
efi_status_t ret;
desc = dev_get_uclass_plat(dev);
- diskid = desc->devnum;
ret = efi_disk_add_dev(NULL, NULL, desc,
NULL, 0, &disk, agent_handle);
@@ -608,7 +606,6 @@
struct disk_part *part_data;
struct disk_partition *info;
unsigned int part;
- int diskid;
struct efi_handler *handler;
struct efi_device_path *dp_parent;
struct efi_disk_obj *disk;
@@ -618,7 +615,6 @@
return -1;
desc = dev_get_uclass_plat(dev_get_parent(dev));
- diskid = desc->devnum;
part_data = dev_get_uclass_plat(dev);
part = part_data->partnum;
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index 3d742fa..d2f5d56 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -472,7 +472,8 @@
switch (type) {
case EFI_ALLOCATE_ANY_PAGES:
/* Any page */
- addr = (u64)lmb_alloc_flags(len, EFI_PAGE_SIZE, flags);
+ addr = (u64)lmb_alloc_base_flags(len, EFI_PAGE_SIZE,
+ LMB_ALLOC_ANYWHERE, flags);
if (!addr)
return EFI_OUT_OF_RESOURCES;
break;
@@ -520,7 +521,6 @@
efi_status_t efi_free_pages(uint64_t memory, efi_uintn_t pages)
{
u64 len;
- uint flags;
long status;
efi_status_t ret;
@@ -535,18 +535,17 @@
return EFI_INVALID_PARAMETER;
}
- flags = LMB_NOOVERWRITE | LMB_NONOTIFY;
len = (u64)pages << EFI_PAGE_SHIFT;
+ /*
+ * The 'memory' variable for sandbox holds a pointer which has already
+ * been mapped with map_sysmem() from efi_allocate_pages(). Convert
+ * it back to an address LMB understands
+ */
status = lmb_free_flags(map_to_sysmem((void *)(uintptr_t)memory), len,
- flags);
+ LMB_NOOVERWRITE);
if (status)
return EFI_NOT_FOUND;
- ret = efi_add_memory_map_pg(memory, pages, EFI_CONVENTIONAL_MEMORY,
- false);
- if (ret != EFI_SUCCESS)
- return EFI_NOT_FOUND;
-
return ret;
}
diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c
index 45f451e..866a529 100644
--- a/lib/efi_loader/efi_tcg2.c
+++ b/lib/efi_loader/efi_tcg2.c
@@ -789,7 +789,7 @@
/**
* tcg2_uninit - remove the final event table and free efi memory on failures
*/
-void tcg2_uninit(void)
+static void tcg2_uninit(void)
{
efi_status_t ret;
diff --git a/lib/efi_loader/smbiosdump.c b/lib/efi_loader/smbiosdump.c
index 2f0b91a..d7f2ba3 100644
--- a/lib/efi_loader/smbiosdump.c
+++ b/lib/efi_loader/smbiosdump.c
@@ -289,7 +289,7 @@
* @len: length of buffer
* Return: checksum
*/
-u8 checksum(void *buf, int len)
+static u8 checksum(void *buf, int len)
{
u8 ret = 0;
@@ -304,7 +304,7 @@
*
* Return: status code
*/
-efi_status_t do_check(void)
+static efi_status_t do_check(void)
{
struct smbios3_entry *smbios3_anchor;
void *table, *table_end;
@@ -401,7 +401,7 @@
* @buf: buffer to write
* @size: size of the buffer
*/
-efi_status_t save_file(u16 *filename, void *buf, efi_uintn_t size)
+static efi_status_t save_file(u16 *filename, void *buf, efi_uintn_t size)
{
efi_uintn_t ret;
struct efi_simple_file_system_protocol *file_system;
diff --git a/lib/efi_selftest/efi_selftest_hii.c b/lib/efi_selftest/efi_selftest_hii.c
index f219c01..c363df4 100644
--- a/lib/efi_selftest/efi_selftest_hii.c
+++ b/lib/efi_selftest/efi_selftest_hii.c
@@ -913,7 +913,7 @@
goto out;
}
- efi_st_printf("got languages are %s\n", languages);
+ efi_st_printf("Available languages: %s\n", languages);
result = EFI_ST_SUCCESS;
diff --git a/lib/efi_selftest/efi_selftest_hii_data.c b/lib/efi_selftest/efi_selftest_hii_data.c
index d19f068..5fc8901 100644
--- a/lib/efi_selftest/efi_selftest_hii_data.c
+++ b/lib/efi_selftest/efi_selftest_hii_data.c
@@ -39,7 +39,7 @@
/* HII keyboard layout */
#define EFI_NULL_MODIFIER 0x0000
-u8 packagelist1[] = {
+static u8 packagelist1[] = {
// EFI_HII_PACKAGE_LIST_HEADER, length = 20
// SimpleFont, Font, GUID, Form, String, Image, DevicePath,
// (74) (110) 20 (8) 78 (67) (8)
@@ -262,7 +262,7 @@
EFI_HII_PACKAGE_END
};
-u8 packagelist2[] = {
+static u8 packagelist2[] = {
// EFI_HII_PACKAGE_LIST_HEADER, length = 20
// SimpleFont, Font, GUID, KeyboardLayout, Form, End
// (74) (122) 20 192 (8) 4
@@ -424,30 +424,10 @@
EFI_HII_PACKAGE_END // 1
};
-efi_guid_t packagelist_guid1 =
- EFI_GUID(0x03abcd89, 0x03f4, 0x7044,
- 0x81, 0xde, 0x99, 0xb1, 0x81, 0x20, 0xf7, 0x68);
-
-efi_guid_t packagelist_guid2 =
- EFI_GUID(0x8685ded3, 0x1bce, 0x43f3,
- 0xa2, 0x0c, 0xa3, 0x06, 0xec, 0x69, 0x72, 0xdd);
-
-efi_guid_t kb_layout_guid11 =
+static efi_guid_t kb_layout_guid11 =
EFI_GUID(0x8d40e495, 0xe2aa, 0x4c6f,
0x89, 0x70, 0x68, 0x85, 0x09, 0xee, 0xc7, 0xd2);
-efi_guid_t kb_layout_guid12 =
- EFI_GUID(0x2ae60b3e, 0xb9d6, 0x49d8,
- 0x9a, 0x16, 0xc2, 0x48, 0xf1, 0xeb, 0xa8, 0xdb);
-
-efi_guid_t kb_layout_guid21 =
- EFI_GUID(0xe0f56a1f, 0xdf6b, 0x4a7e,
- 0xa3, 0x9a, 0xe7, 0xa5, 0x19, 0x15, 0x45, 0xd6);
-
-efi_guid_t kb_layout_guid22 =
- EFI_GUID(0x47be6ac9, 0x54cc, 0x46f9,
- 0xa2, 0x62, 0xd5, 0x3b, 0x25, 0x6a, 0x0c, 0x34);
-
-efi_guid_t package_guid =
+static efi_guid_t package_guid =
EFI_GUID(0x0387c95a, 0xd703, 0x2346,
0xb2, 0xab, 0xd0, 0xc7, 0xdd, 0x90, 0x44, 0xf8);
diff --git a/lib/lmb.c b/lib/lmb.c
index eec99c1..2ed0da2 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -27,9 +27,6 @@
#define MAP_OP_FREE (u8)0x2
#define MAP_OP_ADD (u8)0x3
-#define LMB_ALLOC_ANYWHERE 0
-#define LMB_ALIST_INITIAL_SIZE 4
-
static struct lmb lmb;
static bool lmb_should_notify(enum lmb_flags flags)
@@ -38,9 +35,8 @@
CONFIG_IS_ENABLED(EFI_LOADER);
}
-static int __maybe_unused lmb_map_update_notify(phys_addr_t addr,
- phys_size_t size,
- u8 op)
+static int lmb_map_update_notify(phys_addr_t addr, phys_size_t size, u8 op,
+ enum lmb_flags flags)
{
u64 efi_addr;
u64 pages;
@@ -51,6 +47,9 @@
return -1;
}
+ if (!lmb_should_notify(flags))
+ return 0;
+
efi_addr = (uintptr_t)map_sysmem(addr, 0);
pages = efi_size_in_pages(size + (efi_addr & EFI_PAGE_MASK));
efi_addr &= ~EFI_PAGE_MASK;
@@ -64,9 +63,10 @@
log_err("%s: LMB Map notify failure %lu\n", __func__,
status & ~EFI_ERROR_MASK);
return -1;
- } else {
- return 0;
}
+ unmap_sysmem((void *)(uintptr_t)efi_addr);
+
+ return 0;
}
static void lmb_print_region_flags(enum lmb_flags flags)
@@ -76,6 +76,7 @@
do {
bitpos = flags ? fls(flags) - 1 : 0;
+ assert_noisy(bitpos < ARRAY_SIZE(flag_str));
printf("%s", flag_str[bitpos]);
flags &= ~(1ull << bitpos);
puts(flags ? ", " : "\n");
@@ -450,7 +451,7 @@
}
if (coalesced)
- return coalesced;
+ return 0;
if (alist_full(lmb_rgn_lst) &&
!alist_expand_by(lmb_rgn_lst, lmb_rgn_lst->alloc))
@@ -487,13 +488,10 @@
struct alist *lmb_rgn_lst = &lmb.free_mem;
ret = lmb_add_region(lmb_rgn_lst, base, size);
- if (ret < 0)
+ if (ret)
return ret;
- if (lmb_should_notify(LMB_NONE))
- return lmb_map_update_notify(base, size, MAP_OP_ADD);
-
- return 0;
+ return lmb_map_update_notify(base, size, MAP_OP_ADD, LMB_NONE);
}
static long _lmb_free(phys_addr_t base, phys_size_t size)
@@ -566,10 +564,7 @@
if (ret < 0)
return ret;
- if (lmb_should_notify(flags))
- return lmb_map_update_notify(base, size, MAP_OP_FREE);
-
- return ret;
+ return lmb_map_update_notify(base, size, MAP_OP_FREE, flags);
}
long lmb_free(phys_addr_t base, phys_size_t size)
@@ -583,13 +578,10 @@
struct alist *lmb_rgn_lst = &lmb.used_mem;
ret = lmb_add_region_flags(lmb_rgn_lst, base, size, flags);
- if (ret < 0)
- return -1;
-
- if (lmb_should_notify(flags))
- return lmb_map_update_notify(base, size, MAP_OP_RESERVE);
+ if (ret)
+ return ret;
- return ret;
+ return lmb_map_update_notify(base, size, MAP_OP_RESERVE, flags);
}
long lmb_reserve(phys_addr_t base, phys_size_t size)
@@ -621,7 +613,6 @@
static phys_addr_t _lmb_alloc_base(phys_size_t size, ulong align,
phys_addr_t max_addr, enum lmb_flags flags)
{
- u8 op;
int ret;
long i, rgn;
phys_addr_t base = 0;
@@ -651,16 +642,14 @@
if (rgn < 0) {
/* This area isn't reserved, take it */
if (lmb_add_region_flags(&lmb.used_mem, base,
- size, flags) < 0)
+ size, flags))
return 0;
- if (lmb_should_notify(flags)) {
- op = MAP_OP_RESERVE;
- ret = lmb_map_update_notify(base, size,
- op);
- if (ret)
- return ret;
- }
+ ret = lmb_map_update_notify(base, size,
+ MAP_OP_RESERVE,
+ flags);
+ if (ret)
+ return ret;
return base;
}
@@ -679,23 +668,6 @@
return lmb_alloc_base(size, align, LMB_ALLOC_ANYWHERE);
}
-/**
- * lmb_alloc_flags() - Allocate memory region with specified attributes
- * @size: Size of the region requested
- * @align: Alignment of the memory region requested
- * @flags: Memory region attributes to be set
- *
- * Allocate a region of memory with the attributes specified through the
- * parameter.
- *
- * Return: base address on success, 0 on error
- */
-phys_addr_t lmb_alloc_flags(phys_size_t size, ulong align, uint flags)
-{
- return _lmb_alloc_base(size, align, LMB_ALLOC_ANYWHERE,
- flags);
-}
-
phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr)
{
phys_addr_t alloc;
diff --git a/scripts/dtc/pylibfdt/libfdt.i_shipped b/scripts/dtc/pylibfdt/libfdt.i_shipped
index 56cc5d4..e465948 100644
--- a/scripts/dtc/pylibfdt/libfdt.i_shipped
+++ b/scripts/dtc/pylibfdt/libfdt.i_shipped
@@ -1037,7 +1037,7 @@
fdt_string(fdt1, fdt32_to_cpu($1->nameoff)));
buff = PyByteArray_FromStringAndSize(
(const char *)($1 + 1), fdt32_to_cpu($1->len));
- resultobj = SWIG_Python_AppendOutput(resultobj, buff);
+ resultobj = SWIG_AppendOutput(resultobj, buff);
}
}
@@ -1076,7 +1076,7 @@
%typemap(argout) int *depth {
PyObject *val = Py_BuildValue("i", *arg$argnum);
- resultobj = SWIG_Python_AppendOutput(resultobj, val);
+ resultobj = SWIG_AppendOutput(resultobj, val);
}
%apply int *depth { int *depth };
@@ -1092,7 +1092,7 @@
if (PyTuple_GET_SIZE(resultobj) == 0)
resultobj = val;
else
- resultobj = SWIG_Python_AppendOutput(resultobj, val);
+ resultobj = SWIG_AppendOutput(resultobj, val);
}
}
diff --git a/test/boot/bootdev.c b/test/boot/bootdev.c
index 369105c..369c611 100644
--- a/test/boot/bootdev.c
+++ b/test/boot/bootdev.c
@@ -630,7 +630,7 @@
ut_assertok(bootdev_next_label(&iter, &dev, &mflags));
ut_assert_nextline("scanning bus for devices...");
ut_assert_skip_to_line(
- " Capacity: 1.9 MB = 0.0 GB (4095 x 512)");
+ " Capacity: 2.0 MB = 0.0 GB (4096 x 512)");
ut_assert_console_end();
ut_assertnonnull(dev);
ut_asserteq_str("scsi.id0lun0.bootdev", dev->name);
diff --git a/test/cmd/Makefile b/test/cmd/Makefile
index 4b487c1..fe7a216 100644
--- a/test/cmd/Makefile
+++ b/test/cmd/Makefile
@@ -25,16 +25,16 @@
ifdef CONFIG_CMD_PCI
obj-$(CONFIG_CMD_PCI_MPS) += pci_mps.o
endif
-obj-$(CONFIG_CMD_PINMUX) += pinmux.o
-obj-$(CONFIG_CMD_PWM) += pwm.o
obj-$(CONFIG_CMD_SEAMA) += seama.o
ifdef CONFIG_SANDBOX
obj-$(CONFIG_CMD_MBR) += mbr.o
+obj-$(CONFIG_CMD_PINMUX) += pinmux.o
+obj-$(CONFIG_CMD_PWM) += pwm.o
obj-$(CONFIG_CMD_READ) += rw.o
obj-$(CONFIG_CMD_SETEXPR) += setexpr.o
+obj-$(CONFIG_CMD_TEMPERATURE) += temperature.o
ifdef CONFIG_NET
obj-$(CONFIG_CMD_WGET) += wget.o
endif
obj-$(CONFIG_ARM_FFA_TRANSPORT) += armffa.o
endif
-obj-$(CONFIG_CMD_TEMPERATURE) += temperature.o
diff --git a/test/cmd/mem_copy.c b/test/cmd/mem_copy.c
index 1ba0ceb..67eca32 100644
--- a/test/cmd/mem_copy.c
+++ b/test/cmd/mem_copy.c
@@ -21,7 +21,7 @@
static int do_test(struct unit_test_state *uts,
const char *suffix, int d, int s, int count)
{
- const long addr = 0x1000;
+ const long addr = CONFIG_SYS_LOAD_ADDR + 0x1000;
u8 shadow[BUF_SIZE];
u8 *buf;
int i, w, bytes;
diff --git a/test/dm/acpi.c b/test/dm/acpi.c
index 7ccd7f8..39a26bb 100644
--- a/test/dm/acpi.c
+++ b/test/dm/acpi.c
@@ -95,6 +95,21 @@
return acpi_copy_name(out_name, ACPI_TEST_DEV_NAME);
}
+static int testacpi_fill_madt(const struct udevice *dev, struct acpi_ctx *ctx)
+{
+ u64 *data = ctx->current;
+
+ /* Only fill madt once */
+ if (device_get_uclass_id(dev->parent) != UCLASS_TEST_ACPI)
+ return 0;
+
+ *data = 0xdeadbeef;
+
+ acpi_inc(ctx, sizeof(u64));
+
+ return 0;
+}
+
static int testacpi_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx)
{
const char *data;
@@ -124,6 +139,7 @@
struct acpi_ops testacpi_ops = {
.get_name = testacpi_get_name,
.write_tables = testacpi_write_tables,
+ .fill_madt = testacpi_fill_madt,
.fill_ssdt = testacpi_fill_ssdt,
.inject_dsdt = testacpi_inject_dsdt,
};
@@ -527,6 +543,33 @@
}
DM_TEST(dm_test_acpi_fill_ssdt, UTF_SCAN_PDATA | UTF_SCAN_FDT);
+/* Test acpi_fill_madt() */
+static int dm_test_acpi_fill_madt(struct unit_test_state *uts)
+{
+ struct acpi_ctx ctx;
+ u64 *buf;
+
+ buf = malloc(BUF_SIZE);
+ ut_assertnonnull(buf);
+
+ acpi_reset_items();
+ ctx.current = buf;
+ buf[1] = 'z'; /* sentinel */
+ ut_assertok(acpi_fill_madt_subtbl(&ctx));
+
+ /*
+ * These values come from acpi-test2's acpi-ssdt-test-data property.
+ * This device comes first because of u-boot,acpi-ssdt-order
+ */
+ ut_asserteq(0xdeadbeef, buf[0]);
+
+ ut_asserteq('z', buf[1]);
+
+ return 0;
+}
+
+DM_TEST(dm_test_acpi_fill_madt, UTF_SCAN_PDATA | UTF_SCAN_FDT);
+
/* Test acpi_inject_dsdt() */
static int dm_test_acpi_inject_dsdt(struct unit_test_state *uts)
{
diff --git a/test/dm/irq.c b/test/dm/irq.c
index 836f2d8..ca3e188 100644
--- a/test/dm/irq.c
+++ b/test/dm/irq.c
@@ -76,6 +76,21 @@
}
DM_TEST(dm_test_request, UTF_SCAN_PDATA | UTF_SCAN_FDT);
+/* Test of irq_get_by_index() */
+static int dm_test_irq_get_by_index(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+ struct irq irq;
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_TEST_FDT, "f-test",
+ &dev));
+ ut_assertok(irq_get_by_index(dev, 0, &irq));
+ ut_asserteq(4, irq.id);
+
+ return 0;
+}
+DM_TEST(dm_test_irq_get_by_index, UTF_SCAN_PDATA | UTF_SCAN_FDT);
+
/* Test of irq_get_acpi() */
static int dm_test_irq_get_acpi(struct unit_test_state *uts)
{
diff --git a/test/hush/Makefile b/test/hush/Makefile
index a2d9881..4c3a0be 100644
--- a/test/hush/Makefile
+++ b/test/hush/Makefile
@@ -5,6 +5,8 @@
obj-y += cmd_ut_hush.o
obj-y += if.o
+ifdef CONFIG_CONSOLE_RECORD
obj-y += dollar.o
+endif
obj-y += list.o
obj-y += loop.o
diff --git a/test/lib/lmb.c b/test/lib/lmb.c
index b2c54fb..c917115 100644
--- a/test/lib/lmb.c
+++ b/test/lib/lmb.c
@@ -473,7 +473,7 @@
/* allocate overlapping region should return the coalesced count */
ret = lmb_reserve(0x40011000, 0x10000);
- ut_asserteq(ret, 1);
+ ut_asserteq(ret, 0);
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x11000,
0, 0, 0, 0);
/* allocate 3nd region */
@@ -748,13 +748,13 @@
/* merge after */
ret = lmb_reserve_flags(0x40020000, 0x10000, LMB_NOMAP);
- ut_asserteq(ret, 1);
+ ut_asserteq(ret, 0);
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x20000,
0, 0, 0, 0);
/* merge before */
ret = lmb_reserve_flags(0x40000000, 0x10000, LMB_NOMAP);
- ut_asserteq(ret, 1);
+ ut_asserteq(ret, 0);
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40000000, 0x30000,
0, 0, 0, 0);
@@ -770,7 +770,7 @@
/* test that old API use LMB_NONE */
ret = lmb_reserve(0x40040000, 0x10000);
- ut_asserteq(ret, 1);
+ ut_asserteq(ret, 0);
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, 0x40000000, 0x30000,
0x40030000, 0x20000, 0, 0);
@@ -789,7 +789,7 @@
/* merge with 2 adjacent regions */
ret = lmb_reserve_flags(0x40060000, 0x10000, LMB_NOMAP);
- ut_asserteq(ret, 2);
+ ut_asserteq(ret, 0);
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 3, 0x40000000, 0x30000,
0x40030000, 0x20000, 0x40050000, 0x30000);
diff --git a/test/py/tests/test_efi_loader.py b/test/py/tests/test_efi_loader.py
index 707b2c9..3343493 100644
--- a/test/py/tests/test_efi_loader.py
+++ b/test/py/tests/test_efi_loader.py
@@ -182,7 +182,7 @@
do_test_efi_helloworld_net(u_boot_console, PROTO_TFTP);
@pytest.mark.buildconfigspec('of_control')
-@pytest.mark.buildconfigspec('cmd_bootefi_hello_compile')
+@pytest.mark.buildconfigspec('bootefi_hello_compile')
@pytest.mark.buildconfigspec('cmd_wget')
def test_efi_helloworld_net_http(u_boot_console):
"""Run the helloworld.efi binary via HTTP.
diff --git a/test/py/tests/test_eficonfig/test_eficonfig.py b/test/py/tests/test_eficonfig/test_eficonfig.py
index 1d8e033..d98de52 100644
--- a/test/py/tests/test_eficonfig/test_eficonfig.py
+++ b/test/py/tests/test_eficonfig/test_eficonfig.py
@@ -117,7 +117,7 @@
press_up_down_enter_and_wait(0, 0, True, 'Quit')
# Press the enter key to select 'Description:' entry, then enter Description
- press_up_down_enter_and_wait(0, 0, True, 'enter description:')
+ press_up_down_enter_and_wait(0, 0, True, 'Enter description:')
# Send Description user input, press ENTER key to complete
send_user_input_and_wait('test 1', 'Quit')
@@ -166,7 +166,7 @@
press_up_down_enter_and_wait(0, 0, True, 'Quit')
# Press the enter key to select 'Description:' entry, then enter Description
- press_up_down_enter_and_wait(0, 0, True, 'enter description:')
+ press_up_down_enter_and_wait(0, 0, True, 'Enter description:')
# Send Description user input, press ENTER key to complete
send_user_input_and_wait('test 2', 'Quit')
@@ -278,7 +278,7 @@
u_boot_console.p.expect([i])
# Press the enter key to select 'Description:' entry, then enter Description
- press_up_down_enter_and_wait(0, 0, True, 'enter description:')
+ press_up_down_enter_and_wait(0, 0, True, 'Enter description:')
# Send Description user input, press ENTER key to complete
send_user_input_and_wait('test 3', 'Quit')
diff --git a/test/py/tests/test_event_dump.py b/test/py/tests/test_event_dump.py
index e282c67..45143c1 100644
--- a/test/py/tests/test_event_dump.py
+++ b/test/py/tests/test_event_dump.py
@@ -18,6 +18,7 @@
-------------------- ------------------------------ ------------------------------
EVT_FT_FIXUP bootmeth_vbe_ft_fixup .*boot/vbe_request.c:.*
EVT_FT_FIXUP bootmeth_vbe_simple_ft_fixup .*boot/vbe_simple_os.c:.*
+EVT_LAST_STAGE_INIT alloc_write_acpi_tables .*lib/acpi/acpi_table.c:.*
EVT_LAST_STAGE_INIT install_smbios_table .*lib/efi_loader/efi_smbios.c:.*
EVT_MISC_INIT_F sandbox_early_getopt_check .*arch/sandbox/cpu/start.c:.*
EVT_TEST h_adder_simple .*test/common/event.c:'''
diff --git a/test/py/tests/test_spi.py b/test/py/tests/test_spi.py
index 3160d58..caca930 100644
--- a/test/py/tests/test_spi.py
+++ b/test/py/tests/test_spi.py
@@ -693,4 +693,16 @@
u_boot_console, 'read', offset, size, addr, 1, error_msg, EXPECTED_READ
)
+ # Read to relocation address
+ output = u_boot_console.run_command('bdinfo')
+ m = re.search('relocaddr\s*= (.+)', output)
+ res_area = int(m.group(1), 16)
+
+ start = 0
+ size = 0x2000
+ error_msg = 'ERROR: trying to overwrite reserved memory'
+ flash_ops(
+ u_boot_console, 'read', start, size, res_area, 1, error_msg, EXPECTED_READ
+ )
+
i = i + 1
diff --git a/tools/binman/etype/nxp_imx8mcst.py b/tools/binman/etype/nxp_imx8mcst.py
index a7d8db4..dd9f226 100644
--- a/tools/binman/etype/nxp_imx8mcst.py
+++ b/tools/binman/etype/nxp_imx8mcst.py
@@ -165,6 +165,8 @@
args = ['-i', cfg_fname, '-o', output_fname]
if self.cst.run_cmd(*args) is not None:
outdata = tools.read_file(output_fname)
+ # fixme: 0x2000 should be CONFIG_CSF_SIZE
+ outdata += tools.get_bytes(0, 0x2000 - 0x20 - len(outdata))
return data + outdata
else:
# Bintool is missing; just use the input data as the output