tree fd2a7d7ad46a3c33bf8a082740012187526c4382
parent 4de4f385e345b4b421be7e667584f4613232bebc
author Michal Simek <michal.simek@xilinx.com> 1581001163 +0100
committer Michal Simek <michal.simek@xilinx.com> 1582887850 +0100

net: phy: dp83867: Clean force link good bit

On Xilinx ZynqMP revA board initial value of PHYCR register is 0x5448 which
means FORCE_LINK_GOOD is already setup. Origin code was doing write but the
new code is doing read/modify/write and keep this bit untouched. That's why
ethernet stop to work.
The patch is cleaning this bit when PHYCR value is composed.

Tested on Xilinx zcu102-revA and zcu104-rev1.0 boards.

Fixes: 37d6265f2bfa ("net: phy: dp83867: refactor rgmii configuration")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>