arm: dts: agilex5: Enable XGMAC
Enable XGMAC for SoCFPGA Agilex5 devkit.
Link: https://lore.kernel.org/all/20241204064755.10226-2-mun.yew.tham@intel.com/
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
index 9eb21d6..540b266 100644
--- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
@@ -3,6 +3,7 @@
* U-Boot additions
*
* Copyright (C) 2024 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*/
#include "socfpga_agilex5-u-boot.dtsi"
@@ -122,3 +123,36 @@
bootph-all;
};
+&gmac0 {
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-handle = <&emac0_phy0>;
+
+ max-frame-size = <9000>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwxgmac-mdio";
+ emac0_phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+&gmac2 {
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-handle = <&emac2_phy0>;
+
+ max-frame-size = <9000>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwxgmac-mdio";
+ emac2_phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};