tree abee130bc9075de43eb494b30e102a907ffda992
parent 05241172f548c7103a41c4953698c4840f855f48
author Dave Liu <daveliu@freescale.com> 1260980676 -0600
committer Kumar Gala <galak@kernel.crashing.org> 1262720950 -0600

fsl-ddr: Fix power-down timing settings

1. TIMING_CFG_0[ACT_PD_EXIT] was set to 6 clocks, but
   It should be set to tXP parameter, tXP=max(3CK, 7.5ns)
2. TIMING_CFG_0[PRE_PD_EXIT] was set to 6 clocks, but
   It should be set to tXP (if MR0[A12]=1) else to tXPDLL parameter
   We are setting the mode register MR0[A12]='1'

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>