video: dw-mipi-dsi: permit configuring the escape clock rate
The Amlogic D-PHY in the Amlogic AXG SoC Family does support a frequency
higher than 10MHz for the TX Escape Clock, thus make the target rate
configurable.
This is based on the Linux commit [1] and adapted to the U-Boot driver.
[1] a328ca7e4af3 ("drm/bridge: dw-mipi-dsi: permit configuring the escape clock rate")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
diff --git a/drivers/video/dw_mipi_dsi.c b/drivers/video/dw_mipi_dsi.c
index 44a60ac..4055ef4 100644
--- a/drivers/video/dw_mipi_dsi.c
+++ b/drivers/video/dw_mipi_dsi.c
@@ -485,15 +485,27 @@
static void dw_mipi_dsi_init_pll(struct dw_mipi_dsi *dsi)
{
+ const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
+ unsigned int esc_rate;
+ u32 esc_clk_division;
+
/*
* The maximum permitted escape clock is 20MHz and it is derived from
- * lanebyteclk, which is running at "lane_mbps / 8". Thus we want:
+ * lanebyteclk, which is running at "lane_mbps / 8".
+ */
+ if (phy_ops->get_esc_clk_rate)
+ phy_ops->get_esc_clk_rate(dsi->device, &esc_rate);
+ else
+ esc_rate = 20; /* Default to 20MHz */
+
+ /*
+ * We want:
*
- * (lane_mbps >> 3) / esc_clk_division < 20
+ * (lane_mbps >> 3) / esc_clk_division < X
* which is:
- * (lane_mbps >> 3) / 20 > esc_clk_division
+ * (lane_mbps >> 3) / X > esc_clk_division
*/
- u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
+ esc_clk_division = (dsi->lane_mbps >> 3) / esc_rate + 1;
dsi_write(dsi, DSI_PWR_UP, RESET);