tree 1ebe802fb2be793b4318badd06dfd157ad1125ad
parent cdd74b3636a2503c3dbc199946aabfcd3f2ad8b7
author Jonas Schwöbel <jonasschwoebel@yahoo.de> 1741071731 +0200
committer Svyatoslav Ryhel <clamor95@gmail.com> 1741707592 +0200

ARM: tegra: clock: fix PLLD/PLLD2 related clock calculations

While PLLD/D2 is the nominal parent clock, all derived clocks are generated
from its single output, plld_out0, which is PLLD/D2 divided by two. Direct
use of PLLD/D2 is absent in peripheral clock configurations. Therefore,
clock derivation formulas must take in account this division.

Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>