avr32: Add simple paging support
Use the MMU hardware to set up 1:1 mappings between physical and virtual
addresses. This allows us to bypass the cache when accessing the flash
without having to do any physical-to-virtual address mapping in the CFI
driver.
The virtual memory mappings are defined at compile time through a sorted
array of virtual memory range objects. When a TLB miss exception
happens, the exception handler does a binary search through the array
until it finds a matching entry and loads it into the TLB. The u-boot
image itself is covered by a fixed TLB entry which is never replaced.
This makes the 'saveenv' command work again on ATNGW100 and other boards
using the CFI driver, hopefully without breaking any rules.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
diff --git a/board/mimc/mimc200/mimc200.c b/board/mimc/mimc200/mimc200.c
index 9940669..470adba 100644
--- a/board/mimc/mimc200/mimc200.c
+++ b/board/mimc/mimc200/mimc200.c
@@ -27,12 +27,32 @@
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/hmatrix.h>
+#include <asm/arch/mmu.h>
#include <asm/arch/portmux.h>
#include <atmel_lcdc.h>
#include <lcd.h>
#include "../../../arch/avr32/cpu/hsmc3.h"
+struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
+ {
+ .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
+ .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_NONE,
+ }, {
+ .virt_pgno = EBI_SRAM_CS2_BASE >> PAGE_SHIFT,
+ .nr_pages = EBI_SRAM_CS2_SIZE >> PAGE_SHIFT,
+ .phys = (EBI_SRAM_CS2_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_NONE,
+ }, {
+ .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
+ .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_WRBACK,
+ },
+};
+
#if defined(CONFIG_LCD)
/* 480x272x16 @ 72 Hz */
vidinfo_t panel_info = {