riscv: remove cache enablement in start.S
Cache could be enabled in harts_early_init board-specific hook,
so remove cache enablement in start.S
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index a9e1935..8e58f64 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -210,10 +210,6 @@
bnez s2, secondary_hart_loop
#endif
- /* Enable cache */
- jal icache_enable
- jal dcache_enable
-
#ifdef CONFIG_DEBUG_UART
jal debug_uart_init
#endif