arm: atmel: Add SAMA5D2 Xplained board
The board supports following features:
- Boot media support: SD card/e.MMC/SPI flash,
- Support LCD display (optional, disabled by default),
- Support ethernet,
- Support USB mass storage.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
[fix checkpatch warnings]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index fdaf328..c333647 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -71,6 +71,10 @@
select CPU_ARM926EJS
select SUPPORT_SPL
+config TARGET_SAMA5D2_XPLAINED
+ bool "SAMA5D2 Xplained board"
+ select CPU_V7
+
config TARGET_SAMA5D3_XPLAINED
bool "SAMA5D3 Xplained board"
select CPU_V7
@@ -123,6 +127,7 @@
source "board/atmel/at91sam9n12ek/Kconfig"
source "board/atmel/at91sam9rlek/Kconfig"
source "board/atmel/at91sam9x5ek/Kconfig"
+source "board/atmel/sama5d2_xplained/Kconfig"
source "board/atmel/sama5d3_xplained/Kconfig"
source "board/atmel/sama5d3xek/Kconfig"
source "board/atmel/sama5d4_xplained/Kconfig"
diff --git a/arch/arm/mach-at91/armv7/Makefile b/arch/arm/mach-at91/armv7/Makefile
index f4f35a4..9538bc1 100644
--- a/arch/arm/mach-at91/armv7/Makefile
+++ b/arch/arm/mach-at91/armv7/Makefile
@@ -8,6 +8,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
+obj-$(CONFIG_SAMA5D2) += sama5d2_devices.o
obj-$(CONFIG_SAMA5D3) += sama5d3_devices.o
obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o
obj-y += clock.o
diff --git a/arch/arm/mach-at91/armv7/sama5d2_devices.c b/arch/arm/mach-at91/armv7/sama5d2_devices.c
new file mode 100644
index 0000000..88f8f2c
--- /dev/null
+++ b/arch/arm/mach-at91/armv7/sama5d2_devices.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2015 Atmel Corporation
+ * Wenyou Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/sama5d2.h>
+
+char *get_cpu_name()
+{
+ unsigned int extension_id = get_extension_chip_id();
+
+ if (cpu_is_sama5d2()) {
+ switch (extension_id) {
+ case ARCH_EXID_SAMA5D21CU:
+ return "SAMA5D21";
+ case ARCH_EXID_SAMA5D22CU:
+ return "SAMA5D22-CU";
+ case ARCH_EXID_SAMA5D22CN:
+ return "SAMA5D22-CN";
+ case ARCH_EXID_SAMA5D23CU:
+ return "SAMA5D23-CU";
+ case ARCH_EXID_SAMA5D24CX:
+ return "SAMA5D24-CX";
+ case ARCH_EXID_SAMA5D24CU:
+ return "SAMA5D24-CU";
+ case ARCH_EXID_SAMA5D26CU:
+ return "SAMA5D26-CU";
+ case ARCH_EXID_SAMA5D27CU:
+ return "SAMA5D27-CU";
+ case ARCH_EXID_SAMA5D27CN:
+ return "SAMA5D27-CN";
+ case ARCH_EXID_SAMA5D28CU:
+ return "SAMA5D28-CU";
+ case ARCH_EXID_SAMA5D28CN:
+ return "SAMA5D28-CN";
+ }
+ }
+
+ return "Unknown CPU type";
+}
+
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+void at91_udp_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
+
+ at91_periph_clk_enable(ATMEL_ID_UDPHS);
+}
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 5a51be6..3f50f77 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -78,7 +78,8 @@
#define AT91_PMC_PLLXR_DIV(x) (x & 0xFF)
#define AT91_PMC_PLLXR_PLLCOUNT(x) ((x & 0x3F) << 8)
#define AT91_PMC_PLLXR_OUT(x) ((x & 0x03) << 14)
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
+#if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \
+ defined(CONFIG_SAMA5D4)
#define AT91_PMC_PLLXR_MUL(x) ((x & 0x7F) << 18)
#else
#define AT91_PMC_PLLXR_MUL(x) ((x & 0x7FF) << 16)
@@ -97,7 +98,8 @@
#define AT91_PMC_MCKR_CSS_PLLB 0x00000003
#define AT91_PMC_MCKR_CSS_MASK 0x00000003
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
+#if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \
+ defined(CONFIG_SAMA5D4) || \
defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
#define AT91_PMC_MCKR_PRES_1 0x00000000
#define AT91_PMC_MCKR_PRES_2 0x00000010
@@ -127,10 +129,7 @@
#else
#define AT91_PMC_MCKR_MDIV_1 0x00000000
#define AT91_PMC_MCKR_MDIV_2 0x00000100
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
- defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
#define AT91_PMC_MCKR_MDIV_3 0x00000300
-#endif
#define AT91_PMC_MCKR_MDIV_4 0x00000200
#define AT91_PMC_MCKR_MDIV_MASK 0x00000300
#endif
diff --git a/arch/arm/mach-at91/include/mach/atmel_usba_udc.h b/arch/arm/mach-at91/include/mach/atmel_usba_udc.h
index 38b5012..46a329b 100644
--- a/arch/arm/mach-at91/include/mach/atmel_usba_udc.h
+++ b/arch/arm/mach-at91/include/mach/atmel_usba_udc.h
@@ -31,7 +31,8 @@
EP("ep5", 5, 1024, 3, 1, 1),
EP("ep6", 6, 1024, 3, 1, 1),
};
-#elif defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
+#elif defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \
+ defined(CONFIG_SAMA5D4)
static struct usba_ep_data usba_udc_ep[] = {
EP("ep0", 0, 64, 1, 0, 0),
EP("ep1", 1, 1024, 3, 1, 0),
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index ff6b71b..38abfda 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -23,6 +23,8 @@
# include <asm/arch/at91sam9g45.h>
#elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
# include <asm/arch/at91sam9x5.h>
+#elif defined(CONFIG_SAMA5D2)
+# include <asm/arch/sama5d2.h>
#elif defined(CONFIG_SAMA5D3)
# include <asm/arch/sama5d3.h>
#elif defined(CONFIG_SAMA5D4)
diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h
new file mode 100644
index 0000000..c85571c
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/sama5d2.h
@@ -0,0 +1,203 @@
+/*
+ * Chip-specific header file for the SAMA5D2 SoC
+ *
+ * Copyright (C) 2015 Atmel
+ * Wenyou Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SAMA5D2_H
+#define __SAMA5D2_H
+
+/*
+ * definitions to be used in other places
+ */
+#define CONFIG_AT91FAMILY /* It's a member of AT91 */
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define ATMEL_ID_FIQ 0 /* FIQ Interrupt ID */
+/* 1 */
+#define ATMEL_ID_ARM 2 /* Performance Monitor Unit */
+#define ATMEL_ID_PIT 3 /* Periodic Interval Timer Interrupt */
+#define ATMEL_ID_WDT 4 /* Watchdog Timer Interrupt */
+#define ATMEL_ID_GMAC 5 /* Ethernet MAC */
+#define ATMEL_ID_XDMAC0 6 /* DMA Controller 0 */
+#define ATMEL_ID_XDMAC1 7 /* DMA Controller 1 */
+#define ATMEL_ID_ICM 8 /* Integrity Check Monitor */
+#define ATMEL_ID_AES 9 /* Advanced Encryption Standard */
+#define ATMEL_ID_AESB 10 /* AES bridge */
+#define ATMEL_ID_TDES 11 /* Triple Data Encryption Standard */
+#define ATMEL_ID_SHA 12 /* SHA Signature */
+#define ATMEL_ID_MPDDRC 13 /* MPDDR Controller */
+#define ATMEL_ID_MATRIX1 14 /* H32MX, 32-bit AHB Matrix */
+#define ATMEL_ID_MATRIX0 15 /* H64MX, 64-bit AHB Matrix */
+#define ATMEL_ID_SECUMOD 16 /* Secure Module */
+#define ATMEL_ID_HSMC 17 /* Multi-bit ECC interrupt */
+#define ATMEL_ID_PIOA 18 /* Parallel I/O Controller A */
+#define ATMEL_ID_FLEXCOM0 19 /* FLEXCOM0 */
+#define ATMEL_ID_FLEXCOM1 20 /* FLEXCOM1 */
+#define ATMEL_ID_FLEXCOM2 21 /* FLEXCOM2 */
+#define ATMEL_ID_FLEXCOM3 22 /* FLEXCOM3 */
+#define ATMEL_ID_FLEXCOM4 23 /* FLEXCOM4 */
+#define ATMEL_ID_UART0 24 /* UART0 */
+#define ATMEL_ID_UART1 25 /* UART1 */
+#define ATMEL_ID_UART2 26 /* UART2 */
+#define ATMEL_ID_UART3 27 /* UART3 */
+#define ATMEL_ID_UART4 28 /* UART4 */
+#define ATMEL_ID_TWIHS0 29 /* Two-wire Interface 0 */
+#define ATMEL_ID_TWIHS1 30 /* Two-wire Interface 1 */
+#define ATMEL_ID_SDMMC0 31 /* Secure Data Memory Card Controller 0 */
+#define ATMEL_ID_SDMMC1 32 /* Secure Data Memory Card Controller 1 */
+#define ATMEL_ID_SPI0 33 /* Serial Peripheral Interface 0 */
+#define ATMEL_ID_SPI1 34 /* Serial Peripheral Interface 1 */
+#define ATMEL_ID_TC0 35 /* Timer Counter 0 (ch.0,1,2) */
+#define ATMEL_ID_TC1 36 /* Timer Counter 1 (ch.3,4,5) */
+/* 37 */
+#define ATMEL_ID_PWM 38 /* PWMController0 (ch. 0,1,2,3) */
+/* 39 */
+#define ATMEL_ID_ADC 40 /* Touch Screen ADC Controller */
+#define ATMEL_ID_UHPHS 41 /* USB Host High Speed */
+#define ATMEL_ID_UDPHS 42 /* USB Device High Speed */
+#define ATMEL_ID_SSC0 43 /* Serial Synchronous Controller 0 */
+#define ATMEL_ID_SSC1 44 /* Serial Synchronous Controller 1 */
+#define ATMEL_ID_LCDC 45 /* LCD Controller */
+#define ATMEL_ID_ISI 46 /* Image Sensor Controller, for A5D2, named after ISC */
+#define ATMEL_ID_TRNG 47 /* True Random Number Generator */
+#define ATMEL_ID_PDMIC 48 /* PDM Interface Controller */
+#define ATMEL_ID_AIC_IRQ 49 /* IRQ Interrupt ID */
+#define ATMEL_ID_SFC 50 /* Fuse Controller */
+#define ATMEL_ID_SECURAM 51 /* Secure RAM */
+#define ATMEL_ID_QSPI0 52 /* QSPI0 */
+#define ATMEL_ID_QSPI1 53 /* QSPI1 */
+#define ATMEL_ID_I2SC0 54 /* Inter-IC Sound Controller 0 */
+#define ATMEL_ID_I2SC1 55 /* Inter-IC Sound Controller 1 */
+#define ATMEL_ID_CAN0_INT0 56 /* MCAN 0 Interrupt0 */
+#define ATMEL_ID_CAN1_INT0 57 /* MCAN 1 Interrupt0 */
+/* 58 */
+#define ATMEL_ID_CLASSD 59 /* Audio Class D Amplifier */
+#define ATMEL_ID_SFR 60 /* Special Function Register */
+#define ATMEL_ID_SAIC 61 /* Secured AIC */
+#define ATMEL_ID_AIC 62 /* Advanced Interrupt Controller */
+#define ATMEL_ID_L2CC 63 /* L2 Cache Controller */
+#define ATMEL_ID_CAN0_INT1 64 /* MCAN 0 Interrupt1 */
+#define ATMEL_ID_CAN1_INT1 65 /* MCAN 1 Interrupt1 */
+#define ATMEL_ID_GMAC_Q1 66 /* GMAC Queue 1 Interrupt */
+#define ATMEL_ID_GMAC_Q2 67 /* GMAC Queue 2 Interrupt */
+#define ATMEL_ID_PIOB 68 /* Parallel I/O Controller B */
+#define ATMEL_ID_PIOC 69 /* Parallel I/O Controller C */
+#define ATMEL_ID_PIOD 70 /* Parallel I/O Controller D */
+#define ATMEL_ID_SDMMC0_TIMER 71 /* Secure Data Memory Card Controller 0 (TIMER) */
+#define ATMEL_ID_SDMMC1_TIMER 72 /* Secure Data Memory Card Controller 1 (TIMER) */
+/* 73 */
+#define ATMEL_ID_SYS 74 /* System Controller Interrupt */
+#define ATMEL_ID_ACC 75 /* Analog Comparator */
+#define ATMEL_ID_RXLP 76 /* UART Low-Power */
+#define ATMEL_ID_SFRBU 77 /* Special Function Register BackUp */
+#define ATMEL_ID_CHIPID 78 /* Chip ID */
+
+/*
+ * User Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_LCDC 0xf0000000
+#define ATMEL_BASE_XDMAC1 0xf0004000
+#define ATMEL_BASE_MPDDRC 0xf000c000
+#define ATMEL_BASE_XDMAC0 0xf0010000
+#define ATMEL_BASE_PMC 0xf0014000
+#define ATMEL_BASE_QSPI0 0xf0020000
+#define ATMEL_BASE_QSPI1 0xf0024000
+#define ATMEL_BASE_SPI0 0xf8000000
+#define ATMEL_BASE_GMAC 0xf8008000
+#define ATMEL_BASE_TC0 0xf800c000
+#define ATMEL_BASE_TC1 0xf8010000
+#define ATMEL_BASE_HSMC 0xf8014000
+#define ATMEL_BASE_UART0 0xf801c000
+#define ATMEL_BASE_UART1 0xf8020000
+#define ATMEL_BASE_UART2 0xf8024000
+#define ATMEL_BASE_TWI0 0xf8028000
+#define ATMEL_BASE_SYSC 0xf8048000
+#define ATMEL_BASE_SPI1 0xfc000000
+#define ATMEL_BASE_UART3 0xfc008000
+#define ATMEL_BASE_UART4 0xfc00c000
+#define ATMEL_BASE_TWI1 0xfc028000
+#define ATMEL_BASE_UDPHS 0xfc02c000
+
+#define ATMEL_BASE_PIOA 0xfc038000
+
+#define ATMEL_CHIPID_CIDR 0xfc069000
+#define ATMEL_CHIPID_EXID 0xfc069004
+
+/*
+ * Address Memory Space
+ */
+#define ATMEL_BASE_DDRCS 0x20000000
+#define ATMEL_BASE_QSPI0_AES_MEM 0x90000000
+#define ATMEL_BASE_QSPI1_AES_MEM 0x98000000
+#define ATMEL_BASE_SDMMC0 0xa0000000
+#define ATMEL_BASE_SDMMC1 0xb0000000
+#define ATMEL_BASE_QSPI0_MEM 0xd0000000
+#define ATMEL_BASE_QSPI1_MEM 0xd8000000
+
+/*
+ * Internal Memories
+ */
+#define ATMEL_BASE_UDPHS_FIFO 0x00300000 /* USB Device HS controller */
+#define ATMEL_BASE_OHCI 0x00400000 /* USB Host controller (OHCI) */
+#define ATMEL_BASE_EHCI 0x00500000 /* USB Host controller (EHCI) */
+
+/*
+ * SYSC Spawns
+ */
+#define ATMEL_BASE_RSTC ATMEL_BASE_SYSC
+#define ATMEL_BASE_SHDWC (ATMEL_BASE_SYSC + 0x10)
+#define ATMEL_BASE_PIT (ATMEL_BASE_SYSC + 0x30)
+#define ATMEL_BASE_WDT (ATMEL_BASE_SYSC + 0x40)
+#define ATMEL_BASE_SCKC (ATMEL_BASE_SYSC + 0x50)
+#define ATMEL_BASE_RTC (ATMEL_BASE_SYSC + 0xb0)
+
+/*
+ * Other misc definitions
+ */
+#define ATMEL_BASE_PMECC (ATMEL_BASE_HSMC + 0x70)
+#define ATMEL_BASE_PMERRLOC (ATMEL_BASE_HSMC + 0x500)
+
+#define ATMEL_BASE_PIOB (ATMEL_BASE_PIOA + 0x40)
+#define ATMEL_BASE_PIOC (ATMEL_BASE_PIOB + 0x40)
+#define ATMEL_BASE_PIOD (ATMEL_BASE_PIOC + 0x40)
+
+#define ATMEL_PIO_PORTS 4
+#define CPU_HAS_PCR
+#define CPU_HAS_H32MXDIV
+
+/* SAMA5D2 series chip id definitions */
+#define ARCH_ID_SAMA5D2 0x8a5c08c0
+#define ARCH_EXID_SAMA5D21CU 0x0000005a
+#define ARCH_EXID_SAMA5D22CU 0x00000059
+#define ARCH_EXID_SAMA5D22CN 0x00000069
+#define ARCH_EXID_SAMA5D23CU 0x00000058
+#define ARCH_EXID_SAMA5D24CX 0x00000004
+#define ARCH_EXID_SAMA5D24CU 0x00000014
+#define ARCH_EXID_SAMA5D26CU 0x00000012
+#define ARCH_EXID_SAMA5D27CU 0x00000011
+#define ARCH_EXID_SAMA5D27CN 0x00000021
+#define ARCH_EXID_SAMA5D28CU 0x00000010
+#define ARCH_EXID_SAMA5D28CN 0x00000020
+
+#define cpu_is_sama5d2() (get_chip_id() == ARCH_ID_SAMA5D2)
+
+/* PIT Timer(PIT_PIIR) */
+#define CONFIG_SYS_TIMER_COUNTER 0xf804803c
+
+/* No PMECC Galois table in ROM */
+#define NO_GALOIS_TABLE_IN_ROM
+
+#ifndef __ASSEMBLY__
+unsigned int get_chip_id(void);
+unsigned int get_extension_chip_id(void);
+unsigned int has_lcdc(void);
+char *get_cpu_name(void);
+#endif
+
+#endif