pci: layerscape: Only set EP CFG READY bit
In ls_pcie_ep_enable_cfg(), as part of EP setup,config ready bit
of pci controller is set, so that RC can read the config space of EP.
While setting the config ready bit, LTSSM_EN bit in same register was
also inadvertently getting cleared. This restarts the link training
between RC and EP.
Update code to just set the desired CFG_READY bit (bit 0),
while leaving the other bits unchanged.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index db1375a..5ad7c28 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -406,7 +406,11 @@
static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie)
{
- ctrl_writel(pcie, PCIE_CONFIG_READY, PCIE_PF_CONFIG);
+ u32 config;
+
+ config = ctrl_readl(pcie, PCIE_PF_CONFIG);
+ config |= PCIE_CONFIG_READY;
+ ctrl_writel(pcie, config, PCIE_PF_CONFIG);
}
static void ls_pcie_setup_ep(struct ls_pcie *pcie)