commit c63c35073aa2c13b83d4f43c3a776a00f1e7d736
author Stephen Warren <swarren@nvidia.com> Mon Mar 04 13:29:40 2013 +0000
committer Albert ARIBAUD <albert.u.boot@aribaud.net> Fri Mar 22 16:45:22 2013 +0100
tree c364b86a037f3845d638d3f57e891623f4b3305f
parent c4ab97154f524160e08699a89671e369ea76306b

ARM: implement erratum 716044 workaround

Add common code to enable the workaround for ARM erratum 716044. This
will be enabled for Tegra.

Signed-off-by: Stephen Warren <swarren@nvidia.com>

README

diff --git a/README b/README
index 7f2506a..616bfb0 100644
--- a/README
+++ b/README
@@ -485,6 +485,7 @@
 		Thumb2 this flag will result in Thumb2 code generated by
 		GCC.
 
+		CONFIG_ARM_ERRATA_716044
 		CONFIG_ARM_ERRATA_742230
 		CONFIG_ARM_ERRATA_743622
 		CONFIG_ARM_ERRATA_751472

arch/arm/cpu/armv7/start.S

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index fa5fad1..c0e1849 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -310,6 +310,12 @@
 #endif
 	mcr	p15, 0, r0, c1, c0, 0
 
+#ifdef CONFIG_ARM_ERRATA_716044
+	mrc	p15, 0, r0, c1, c0, 0	@ read system control register
+	orr	r0, r0, #1 << 11	@ set bit #11
+	mcr	p15, 0, r0, c1, c0, 0	@ write system control register
+#endif
+
 #ifdef CONFIG_ARM_ERRATA_742230
 	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
 	orr	r0, r0, #1 << 4		@ set bit #4