fpga: zynqpl: Correct PL bitstream loading sequence for zynqaes
Correct the PL bitstream loading sequence for zynqaes command by
clearing the loaded PL bitstream before loading the new encrypted
bitstream using the zynq aes command. This was done by setting
the PROG_B same as in case of fpgaload commands.
This patch fixes the issue of loading the encrypted PL bitstream
onto the PL in which a bitstream has already been loaded
successfully.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
diff --git a/board/xilinx/zynq/cmds.c b/board/xilinx/zynq/cmds.c
index 0c46de7..d5e7d70 100644
--- a/board/xilinx/zynq/cmds.c
+++ b/board/xilinx/zynq/cmds.c
@@ -399,7 +399,8 @@
status = zynq_decrypt_load(part_load_addr,
part_img_len,
part_dst_addr,
- part_data_len);
+ part_data_len,
+ BIT_NONE);
if (status != 0) {
printf("DECRYPTION_FAIL\n");
return -1;
@@ -438,6 +439,7 @@
char *endp;
u32 srcaddr, srclen, dstaddr, dstlen;
int status;
+ u8 imgtype = BIT_NONE;
if (argc < 5 && argc > cmdtp->maxargs)
return CMD_RET_USAGE;
@@ -464,7 +466,8 @@
if (dstlen % 4)
dstlen = roundup(dstlen, 4);
- status = zynq_decrypt_load(srcaddr, srclen >> 2, dstaddr, dstlen >> 2);
+ status = zynq_decrypt_load(srcaddr, srclen >> 2, dstaddr,
+ dstlen >> 2, imgtype);
if (status != 0)
return CMD_RET_FAILURE;
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index dcfe513..4ab354b 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -204,7 +204,7 @@
/* Clear loopback bit */
clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
- if (bstype != BIT_PARTIAL) {
+ if (bstype != BIT_PARTIAL && bstype != BIT_NONE) {
zynq_slcr_devcfg_disable();
/* Setting PCFG_PROG_B signal to high */
@@ -511,7 +511,8 @@
* Load the encrypted image from src addr and decrypt the image and
* place it back the decrypted image into dstaddr.
*/
-int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen)
+int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
+ u8 bstype)
{
if (srcaddr < SZ_1M || dstaddr < SZ_1M) {
printf("%s: src and dst addr should be > 1M\n",
@@ -519,7 +520,7 @@
return FPGA_FAIL;
}
- if (zynq_dma_xfer_init(BIT_NONE)) {
+ if (zynq_dma_xfer_init(bstype)) {
printf("%s: zynq_dma_xfer_init FAIL\n", __func__);
return FPGA_FAIL;
}
diff --git a/include/zynqpl.h b/include/zynqpl.h
index 766e691..d7dc064 100644
--- a/include/zynqpl.h
+++ b/include/zynqpl.h
@@ -12,7 +12,8 @@
#include <xilinx.h>
#ifdef CONFIG_CMD_ZYNQ_AES
-int zynq_decrypt_load(u32 srcaddr, u32 dstaddr, u32 srclen, u32 dstlen);
+int zynq_decrypt_load(u32 srcaddr, u32 dstaddr, u32 srclen, u32 dstlen,
+ u8 bstype);
#endif
extern struct xilinx_fpga_op zynq_op;