Merge patch series "Add remoteproc driver for AM62a SoC"
Hari Nagalla <hnagalla@ti.com> says:
This series adds relevant ip data in remoteproc driver for AM62a devices.
Logs: https://paste.sr.ht/~hnagalla/5e20838705c1d688bca81886dad56451b56d3913
diff --git a/MAINTAINERS b/MAINTAINERS
index 7a3b4d3..6853288 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -598,6 +598,22 @@
S: Supported
F: arch/arm/dts/am335x-sancloud*
+ARM SC5XX
+M: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+M: Greg Malysa <greg.malysa@timesys.com>
+M: Ian Roberts <ian.roberts@timesys.com>
+M: Vasileios Bimpikas <vasileios.bimpikas@analog.com>
+M: Utsav Agarwal <utsav.agarwal@analog.com>
+M: Arturs Artamonovs <arturs.artamonovs@analog.com>
+S: Supported
+T: git https://github.com/analogdevicesinc/lnxdsp-u-boot
+F: arch/arm/include/asm/arch-adi/
+F: arch/arm/mach-sc5xx/
+F: drivers/clk/adi/
+F: drivers/serial/serial_adi_uart4.c
+F: drivers/timer/adi_sc5xx_timer.c
+F: include/env/adi/
+
ARM SNAPDRAGON
M: Caleb Connolly <caleb.connolly@linaro.org>
M: Neil Armstrong <neil.armstrong@linaro.org>
diff --git a/api/api.c b/api/api.c
index 89003c1..d22132f 100644
--- a/api/api.c
+++ b/api/api.c
@@ -7,11 +7,13 @@
#include <config.h>
#include <command.h>
-#include <common.h>
#include <env.h>
#include <malloc.h>
+#include <time.h>
#include <env_internal.h>
+#include <vsprintf.h>
#include <linux/delay.h>
+#include <linux/errno.h>
#include <linux/types.h>
#include <api_public.h>
#include <u-boot/crc.h>
diff --git a/api/api_display.c b/api/api_display.c
index 2e877a8..8fd078c 100644
--- a/api/api_display.c
+++ b/api/api_display.c
@@ -3,9 +3,9 @@
* Copyright (c) 2011 The Chromium OS Authors.
*/
-#include <common.h>
#include <api_public.h>
#include <log.h>
+#include <linux/types.h>
/* TODO(clchiou): add support of video device */
diff --git a/api/api_net.c b/api/api_net.c
index 7515c26..264ff53 100644
--- a/api/api_net.c
+++ b/api/api_net.c
@@ -6,7 +6,6 @@
*/
#include <config.h>
-#include <common.h>
#include <net.h>
#include <linux/types.h>
#include <api_public.h>
diff --git a/api/api_storage.c b/api/api_storage.c
index 78becbe..3d2d9d6 100644
--- a/api/api_storage.c
+++ b/api/api_storage.c
@@ -6,10 +6,10 @@
*/
#include <config.h>
-#include <common.h>
#include <api_public.h>
#include <part.h>
#include <scsi.h>
+#include <linux/types.h>
#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
#include <usb.h>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 93e12d8..8d46707 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1852,6 +1852,9 @@
development platform that supports the QorIQ LS1046A
Layerscape Architecture processor.
+config ARCH_SC5XX
+ bool "Analog Devices SC5XX-processor family"
+
config TARGET_SL28
bool "Support sl28"
select ARCH_LS1028A
@@ -2285,6 +2288,8 @@
source "arch/arm/mach-s5pc1xx/Kconfig"
+source "arch/arm/mach-sc5xx/Kconfig"
+
source "arch/arm/mach-snapdragon/Kconfig"
source "arch/arm/mach-socfpga/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index a4266a3..734c6d6 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -78,6 +78,7 @@
machine-$(CONFIG_ARCH_RENESAS) += renesas
machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx
+machine-$(CONFIG_ARCH_SC5XX) += sc5xx
machine-$(CONFIG_ARCH_SNAPDRAGON) += snapdragon
machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
machine-$(CONFIG_ARCH_STM32) += stm32
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 9f0fb36..199335c 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -191,6 +191,14 @@
Exception handling at all exception levels for External Abort and
SError interrupt exception are taken in EL3.
+config ARMV8_UDELAY_EVENT_STREAM
+ bool "Use the event stream for udelay"
+ default y if ARCH_VEXPRESS64
+ help
+ Use the event stream provided by the AArch64 architectural timer for
+ delays. This is more efficient than the default polling
+ implementation.
+
menuconfig ARMV8_CRYPTO
bool "ARM64 Accelerated Cryptographic Algorithms"
diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c
index e4aa5a4..1de7ec5 100644
--- a/arch/arm/cpu/armv8/generic_timer.c
+++ b/arch/arm/cpu/armv8/generic_timer.c
@@ -114,3 +114,30 @@
return val / get_tbclk();
}
+
+#if CONFIG_IS_ENABLED(ARMV8_UDELAY_EVENT_STREAM)
+void __udelay(unsigned long usec)
+{
+ u64 target = get_ticks() + usec_to_tick(usec);
+
+ /* At EL2 or above, use the event stream to avoid polling CNTPCT_EL0 so often */
+ if (current_el() >= 2) {
+ u32 cnthctl_val;
+ const u8 event_period = 0x7;
+
+ asm volatile("mrs %0, cnthctl_el2" : "=r" (cnthctl_val));
+ asm volatile("msr cnthctl_el2, %0" : : "r"
+ (cnthctl_val | CNTHCTL_EL2_EVNT_EN | CNTHCTL_EL2_EVNT_I(event_period)));
+
+ while (get_ticks() + (1ULL << event_period) <= target)
+ wfe();
+
+ /* Reset the event stream */
+ asm volatile("msr cnthctl_el2, %0" : : "r" (cnthctl_val));
+ }
+
+ /* Fall back to polling CNTPCT_EL0 */
+ while (get_ticks() <= target)
+ ;
+}
+#endif
diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
index fb20320..967a2bd 100644
--- a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
@@ -54,6 +54,15 @@
>;
};
+&usbss0 {
+ bootph-all;
+};
+
+&usb0 {
+ dr_mode = "peripheral";
+ bootph-all;
+};
+
#ifdef CONFIG_TARGET_AM625_A53_BEAGLEPLAY
#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
diff --git a/arch/arm/dts/k3-am625-sk-u-boot.dtsi b/arch/arm/dts/k3-am625-sk-u-boot.dtsi
index fa778b0..1fc0d40 100644
--- a/arch/arm/dts/k3-am625-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-sk-u-boot.dtsi
@@ -46,3 +46,12 @@
&cpsw_port2 {
status = "disabled";
};
+
+&usbss0 {
+ bootph-all;
+};
+
+&usb0 {
+ dr_mode = "peripheral";
+ bootph-all;
+};
diff --git a/arch/arm/dts/k3-j7200-binman.dtsi b/arch/arm/dts/k3-j7200-binman.dtsi
index 06db865..e8020fe 100644
--- a/arch/arm/dts/k3-j7200-binman.dtsi
+++ b/arch/arm/dts/k3-j7200-binman.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-binman.dtsi"
@@ -48,6 +48,52 @@
};
&binman {
+ tiboot3-j7200-hs-evm.bin {
+ filename = "tiboot3-j7200-hs-evm.bin";
+ ti-secure-rom {
+ content = <&u_boot_spl_sr1>, <&ti_fs_enc_sr1>, <&combined_tifs_cfg_sr1>,
+ <&combined_dm_cfg_sr1>, <&sysfw_inner_cert_sr1>;
+ combined;
+ dm-data;
+ core-opts = <2>;
+ sysfw-inner-cert;
+ keyfile = "custMpk.pem";
+ sw-rev = <1>;
+ content-sbl = <&u_boot_spl_sr1>;
+ content-sysfw = <&ti_fs_enc_sr1>;
+ content-sysfw-data = <&combined_tifs_cfg_sr1>;
+ content-sysfw-inner-cert = <&sysfw_inner_cert_sr1>;
+ content-dm-data = <&combined_dm_cfg_sr1>;
+ load = <0x41c00000>;
+ load-sysfw = <0x40000>;
+ load-sysfw-data = <0x7f000>;
+ load-dm-data = <0x41c80000>;
+ };
+ u_boot_spl_sr1: u-boot-spl {
+ no-expanded;
+ };
+ ti_fs_enc_sr1: ti-fs-enc.bin {
+ filename = "ti-sysfw/ti-fs-firmware-j7200-hs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+ combined_tifs_cfg_sr1: combined-tifs-cfg.bin {
+ filename = "combined-tifs-cfg.bin";
+ type = "blob-ext";
+ };
+ sysfw_inner_cert_sr1: sysfw-inner-cert {
+ filename = "ti-sysfw/ti-fs-firmware-j7200-hs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+ combined_dm_cfg_sr1: combined-dm-cfg.bin {
+ filename = "combined-dm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+};
+
+&binman {
tiboot3-j7200_sr2-hs-evm.bin {
filename = "tiboot3-j7200_sr2-hs-evm.bin";
ti-secure-rom {
@@ -93,6 +139,53 @@
};
&binman {
+ tiboot3-j7200-hs-fs-evm.bin {
+ filename = "tiboot3-j7200-hs-fs-evm.bin";
+ ti-secure-rom {
+ content = <&u_boot_spl_fs_sr1>, <&ti_fs_enc_fs_sr1>,
+ <&combined_tifs_cfg_fs_sr1>, <&combined_dm_cfg_fs_sr1>,
+ <&sysfw_inner_cert_fs_sr1>;
+ combined;
+ dm-data;
+ core-opts = <2>;
+ sysfw-inner-cert;
+ keyfile = "custMpk.pem";
+ sw-rev = <1>;
+ content-sbl = <&u_boot_spl_fs_sr1>;
+ content-sysfw = <&ti_fs_enc_fs_sr1>;
+ content-sysfw-data = <&combined_tifs_cfg_fs_sr1>;
+ content-sysfw-inner-cert = <&sysfw_inner_cert_fs_sr1>;
+ content-dm-data = <&combined_dm_cfg_fs_sr1>;
+ load = <0x41c00000>;
+ load-sysfw = <0x40000>;
+ load-sysfw-data = <0x7f000>;
+ load-dm-data = <0x41c80000>;
+ };
+ u_boot_spl_fs_sr1: u-boot-spl {
+ no-expanded;
+ };
+ ti_fs_enc_fs_sr1: ti-fs-enc.bin {
+ filename = "ti-sysfw/ti-fs-firmware-j7200-hs-fs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+ combined_tifs_cfg_fs_sr1: combined-tifs-cfg.bin {
+ filename = "combined-tifs-cfg.bin";
+ type = "blob-ext";
+ };
+ sysfw_inner_cert_fs_sr1: sysfw-inner-cert {
+ filename = "ti-sysfw/ti-fs-firmware-j7200-hs-fs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+ combined_dm_cfg_fs_sr1: combined-dm-cfg.bin {
+ filename = "combined-dm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+};
+
+&binman {
tiboot3-j7200_sr2-hs-fs-evm.bin {
filename = "tiboot3-j7200_sr2-hs-fs-evm.bin";
ti-secure-rom {
diff --git a/arch/arm/dts/k3-j721e-binman.dtsi b/arch/arm/dts/k3-j721e-binman.dtsi
index 75a6e95..1514d89 100644
--- a/arch/arm/dts/k3-j721e-binman.dtsi
+++ b/arch/arm/dts/k3-j721e-binman.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-binman.dtsi"
@@ -130,6 +130,94 @@
};
&binman {
+ tiboot3-j721e_sr1_1-hs-fs-evm.bin {
+ filename = "tiboot3-j721e_sr1_1-hs-fs-evm.bin";
+ ti-secure-rom {
+ content = <&u_boot_spl_fs_sr1_1>;
+ core = "public";
+ core-opts = <2>;
+ load = <CONFIG_SPL_TEXT_BASE>;
+ keyfile = "custMpk.pem";
+ };
+ u_boot_spl_fs_sr1_1: u-boot-spl {
+ no-expanded;
+ };
+ };
+ sysfw_fs_sr1_1 {
+ filename = "sysfw.bin_fs_sr1_1";
+ ti-fs-cert-fs.bin {
+ filename = "ti-sysfw/ti-fs-firmware-j721e_sr1_1-hs-fs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+ ti-fs-firmware-j721e-hs-fs-enc.bin {
+ filename = "ti-sysfw/ti-fs-firmware-j721e_sr1_1-hs-fs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+ };
+ itb_fs_sr1_1 {
+ filename = "sysfw-j721e_sr1_1-hs-fs-evm.itb";
+ fit {
+ description = "SYSFW and Config fragments";
+ #address-cells = <1>;
+ images {
+ sysfw.bin {
+ description = "sysfw";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ blob-ext {
+ filename = "sysfw.bin_fs_sr1_1";
+ };
+ };
+ board-cfg.bin {
+ description = "board-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ board-cfg {
+ filename = "board-cfg.bin";
+ type = "blob-ext";
+ };
+
+ };
+ pm-cfg.bin {
+ description = "pm-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ pm-cfg {
+ filename = "pm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+ rm-cfg.bin {
+ description = "rm-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ rm-cfg {
+ filename = "rm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+ sec-cfg.bin {
+ description = "sec-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ sec-cfg {
+ filename = "sec-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+ };
+ };
+ };
+};
+
+&binman {
tiboot3-j721e_sr2-hs-fs-evm.bin {
filename = "tiboot3-j721e_sr2-hs-fs-evm.bin";
ti-secure-rom {
diff --git a/arch/arm/include/asm/arch-adi/sc5xx/sc5xx.h b/arch/arm/include/asm/arch-adi/sc5xx/sc5xx.h
new file mode 100644
index 0000000..683e3d4
--- /dev/null
+++ b/arch/arm/include/asm/arch-adi/sc5xx/sc5xx.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ * Contact: Greg Malysa <greg.malysa@timesys.com>
+ */
+#ifndef ARCH_ADI_SC5XX_SC5XX_H
+#define ARCH_ADI_SC5XX_SC5XX_H
+
+#include <linux/types.h>
+
+#define TWI0_CLKDIV 0x31001400 // TWI0 SCL Clock Divider Register
+#define TWI1_CLKDIV 0x31001500 // TWI1 SCL Clock Divider Register
+#define TWI2_CLKDIV 0x31001600 // TWI2 SCL Clock Divider Register
+
+const char *sc5xx_get_boot_mode(u32 *bmode);
+void sc5xx_enable_rgmii(void);
+
+void sc5xx_enable_ns_sharc_access(uintptr_t securec0_base);
+void sc5xx_disable_spu0(uintptr_t spu0_start, uintptr_t spu0_end);
+void sc5xx_enable_pmu(void);
+
+/**
+ * Per-SoC init function to be used to initialize hw-specific things. Examples:
+ * enable PMU on armv7, enable coresight timer on armv8, etc.
+ */
+void sc5xx_soc_init(void);
+
+/*
+ * Reconfigure SPI memory map region for OSPI use. The adi-spi3 driver
+ * does not use the memory map, while the OSPI driver requires it. Only
+ * available on sc59x and sc59x-64
+ */
+void sc59x_remap_ospi(void);
+
+#endif
diff --git a/arch/arm/include/asm/arch-adi/sc5xx/soc.h b/arch/arm/include/asm/arch-adi/sc5xx/soc.h
new file mode 100644
index 0000000..430dbe2
--- /dev/null
+++ b/arch/arm/include/asm/arch-adi/sc5xx/soc.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ * Contact: Greg Malysa <greg.malysa@timesys.com>
+ */
+
+#ifndef BOARD_ADI_COMMON_SOC_H
+#define BOARD_ADI_COMMON_SOC_H
+
+#include <phy.h>
+
+void fixup_dp83867_phy(struct phy_device *phydev);
+
+#endif
diff --git a/arch/arm/include/asm/arch-adi/sc5xx/spl.h b/arch/arm/include/asm/arch-adi/sc5xx/spl.h
new file mode 100644
index 0000000..c215e6b
--- /dev/null
+++ b/arch/arm/include/asm/arch-adi/sc5xx/spl.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ * Contact: Greg Malysa <greg.malysa@timesys.com>
+ */
+#ifndef ARCH_ADI_SC5XX_SPL_H
+#define ARCH_ADI_SC5XX_SPL_H
+
+#include <linux/types.h>
+
+struct adi_boot_args {
+ phys_addr_t addr;
+ u32 flags;
+ u32 cmd;
+};
+
+extern u32 bmode;
+
+/**
+ * This table stores the arguments to the rom boot function per bootmode,
+ * and it is populated per SoC in the corresponding SoC support file (sc7x, sc58x,
+ * and so on).
+ */
+extern const struct adi_boot_args adi_rom_boot_args[8];
+
+/**
+ * Struct layout for the boot config is also specific to an SoC, so you should
+ * only access it inside an SoC-specific boot hook function, which will be called
+ * from the boot rom while going from SPL to proper u-boot
+ */
+struct ADI_ROM_BOOT_CONFIG;
+int32_t adi_rom_boot_hook(struct ADI_ROM_BOOT_CONFIG *cfg, int32_t cause);
+
+typedef void (*adi_rom_boot_fn)(void *address, uint32_t flags, int32_t count,
+ void *hook, uint32_t command);
+
+extern adi_rom_boot_fn adi_rom_boot;
+
+#endif
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 43f7503..7e30cac 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -69,8 +69,10 @@
/*
* CNTHCTL_EL2 bits definitions
*/
-#define CNTHCTL_EL2_EL1PCEN_EN (1 << 1) /* Physical timer regs accessible */
-#define CNTHCTL_EL2_EL1PCTEN_EN (1 << 0) /* Physical counter accessible */
+#define CNTHCTL_EL2_EVNT_EN BIT(2) /* Enable the event stream */
+#define CNTHCTL_EL2_EVNT_I(val) ((val) << 4) /* Event stream trigger bits */
+#define CNTHCTL_EL2_EL1PCEN_EN (1 << 1) /* Physical timer regs accessible */
+#define CNTHCTL_EL2_EL1PCTEN_EN (1 << 0) /* Physical counter accessible */
/*
* HCR_EL2 bits definitions
@@ -154,6 +156,13 @@
"wfi" : : : "memory"); \
})
+#define wfe() \
+ ({asm volatile( \
+ "wfe" : : : "memory"); \
+ })
+
+#define sev() asm volatile("sev")
+
static inline unsigned int current_el(void)
{
unsigned long el;
@@ -369,6 +378,8 @@
#ifdef __ARM_ARCH_7A__
#define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
+#define wfe() __asm__ __volatile__ ("wfe" : : : "memory")
+#define sev() __asm__ __volatile__ ("sev")
#else
#define wfi()
#endif
diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h
index 5d0beba..0aed4c3 100644
--- a/arch/arm/mach-exynos/include/mach/system.h
+++ b/arch/arm/mach-exynos/include/mach/system.h
@@ -36,25 +36,6 @@
#define USB20_PHY_CFG_HOST_LINK_EN (1 << 0)
-/*
- * This instruction causes an event to be signaled to all cores
- * within a multiprocessor system. If SEV is implemented,
- * WFE must also be implemented.
- */
-#define sev() __asm__ __volatile__ ("sev\n\t" : : );
-/*
- * If the Event Register is not set, WFE suspends execution until
- * one of the following events occurs:
- * - an IRQ interrupt, unless masked by the CPSR I-bit
- * - an FIQ interrupt, unless masked by the CPSR F-bit
- * - an Imprecise Data abort, unless masked by the CPSR A-bit
- * - a Debug Entry request, if Debug is enabled
- * - an Event signaled by another processor using the SEV instruction.
- * If the Event Register is set, WFE clears it and returns immediately.
- * If WFE is implemented, SEV must also be implemented.
- */
-#define wfe() __asm__ __volatile__ ("wfe\n\t" : : );
-
/* Move 0xd3 value to CPSR register to enable SVC mode */
#define svc32_mode_en() __asm__ __volatile__ \
("@ I&F disable, Mode: 0x13 - SVC\n\t" \
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 1bd5233..2b3ebd5 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -6,23 +6,12 @@
obj-$(CONFIG_ARM64) += arm64/
obj-$(CONFIG_CPU_V7R) += r5/
obj-$(CONFIG_OF_LIBFDT) += common_fdt.o
-ifeq ($(CONFIG_OF_LIBFDT)$(CONFIG_OF_SYSTEM_SETUP),yy)
-obj-$(CONFIG_SOC_K3_AM654) += am654_fdt.o
-obj-$(CONFIG_SOC_K3_J721E) += j721e_fdt.o
-obj-$(CONFIG_SOC_K3_J721S2) += j721s2_fdt.o
-obj-$(CONFIG_SOC_K3_AM625) += am625_fdt.o
-obj-$(CONFIG_SOC_K3_AM62A7) += am62a7_fdt.o
-obj-$(CONFIG_SOC_K3_J784S4) += j784s4_fdt.o
-endif
-ifeq ($(CONFIG_SPL_BUILD),y)
-obj-$(CONFIG_SOC_K3_AM654) += am654_init.o
-obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o
-obj-$(CONFIG_SOC_K3_J721S2) += j721s2_init.o
-obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
-obj-$(CONFIG_SOC_K3_AM625) += am625_init.o
-obj-$(CONFIG_SOC_K3_AM62A7) += am62a7_init.o
-obj-$(CONFIG_SOC_K3_J784S4) += j784s4_init.o
-obj-$(CONFIG_SOC_K3_AM62P5) += am62p5_init.o
-endif
obj-y += common.o security.o
+obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
+obj-$(CONFIG_SOC_K3_AM62P5) += am62px/
obj-$(CONFIG_SOC_K3_AM625) += am62x/
+obj-$(CONFIG_SOC_K3_AM642) += am64x/
+obj-$(CONFIG_SOC_K3_AM654) += am65x/
+obj-$(CONFIG_SOC_K3_J721E) += j721e/
+obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
+obj-$(CONFIG_SOC_K3_J784S4) += j784s4/
diff --git a/arch/arm/mach-k3/am62ax/Makefile b/arch/arm/mach-k3/am62ax/Makefile
new file mode 100644
index 0000000..1717ca3
--- /dev/null
+++ b/arch/arm/mach-k3/am62ax/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+# Andrew Davis <afd@ti.com>
+
+obj-$(CONFIG_OF_SYSTEM_SETUP) += am62a7_fdt.o
+obj-$(CONFIG_SPL_BUILD) += am62a7_init.o
diff --git a/arch/arm/mach-k3/am62a7_fdt.c b/arch/arm/mach-k3/am62ax/am62a7_fdt.c
similarity index 93%
rename from arch/arm/mach-k3/am62a7_fdt.c
rename to arch/arm/mach-k3/am62ax/am62a7_fdt.c
index d67f012..7f764ab 100644
--- a/arch/arm/mach-k3/am62a7_fdt.c
+++ b/arch/arm/mach-k3/am62ax/am62a7_fdt.c
@@ -4,9 +4,10 @@
*/
#include <asm/hardware.h>
-#include "common_fdt.h"
#include <fdt_support.h>
+#include "../common_fdt.h"
+
int ft_system_setup(void *blob, struct bd_info *bd)
{
fdt_fixup_reserved(blob, "tfa", CONFIG_K3_ATF_LOAD_ADDR, 0x80000);
diff --git a/arch/arm/mach-k3/am62a7_init.c b/arch/arm/mach-k3/am62ax/am62a7_init.c
similarity index 98%
rename from arch/arm/mach-k3/am62a7_init.c
rename to arch/arm/mach-k3/am62ax/am62a7_init.c
index 658828c..0f62f39 100644
--- a/arch/arm/mach-k3/am62a7_init.c
+++ b/arch/arm/mach-k3/am62ax/am62a7_init.c
@@ -8,12 +8,13 @@
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
-#include "sysfw-loader.h"
-#include "common.h"
#include <dm.h>
#include <dm/uclass-internal.h>
#include <dm/pinctrl.h>
+#include "../sysfw-loader.h"
+#include "../common.h"
+
struct fwl_data cbass_main_fwls[] = {
{ "FSS_DAT_REG3", 7, 8 },
};
diff --git a/arch/arm/mach-k3/am62px/Makefile b/arch/arm/mach-k3/am62px/Makefile
new file mode 100644
index 0000000..5902862
--- /dev/null
+++ b/arch/arm/mach-k3/am62px/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+# Andrew Davis <afd@ti.com>
+
+obj-$(CONFIG_SPL_BUILD) += am62p5_init.o
diff --git a/arch/arm/mach-k3/am62p5_init.c b/arch/arm/mach-k3/am62px/am62p5_init.c
similarity index 98%
rename from arch/arm/mach-k3/am62p5_init.c
rename to arch/arm/mach-k3/am62px/am62p5_init.c
index aab99aa..34ed01c 100644
--- a/arch/arm/mach-k3/am62p5_init.c
+++ b/arch/arm/mach-k3/am62px/am62p5_init.c
@@ -8,12 +8,13 @@
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
-#include "sysfw-loader.h"
-#include "common.h"
#include <dm.h>
#include <dm/uclass-internal.h>
#include <dm/pinctrl.h>
+#include "../sysfw-loader.h"
+#include "../common.h"
+
struct fwl_data cbass_main_fwls[] = {
{ "FSS_DAT_REG3", 7, 8 },
};
diff --git a/arch/arm/mach-k3/am62x/Makefile b/arch/arm/mach-k3/am62x/Makefile
index acf09c3..8494cdd 100644
--- a/arch/arm/mach-k3/am62x/Makefile
+++ b/arch/arm/mach-k3/am62x/Makefile
@@ -1,2 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_OF_SYSTEM_SETUP) += am625_fdt.o
+obj-$(CONFIG_SPL_BUILD) += am625_init.o
obj-y += boot.o
diff --git a/arch/arm/mach-k3/am625_fdt.c b/arch/arm/mach-k3/am62x/am625_fdt.c
similarity index 98%
rename from arch/arm/mach-k3/am625_fdt.c
rename to arch/arm/mach-k3/am62x/am625_fdt.c
index c56adef..8fe200a 100644
--- a/arch/arm/mach-k3/am625_fdt.c
+++ b/arch/arm/mach-k3/am62x/am625_fdt.c
@@ -4,9 +4,10 @@
*/
#include <asm/hardware.h>
-#include "common_fdt.h"
#include <fdt_support.h>
+#include "../common_fdt.h"
+
static void fdt_fixup_cores_nodes_am625(void *blob, int core_nr)
{
char node_path[32];
diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am62x/am625_init.c
similarity index 99%
rename from arch/arm/mach-k3/am625_init.c
rename to arch/arm/mach-k3/am62x/am625_init.c
index 668f9a5..ed8d24e 100644
--- a/arch/arm/mach-k3/am625_init.c
+++ b/arch/arm/mach-k3/am62x/am625_init.c
@@ -9,13 +9,14 @@
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
-#include "sysfw-loader.h"
-#include "common.h"
#include <dm.h>
#include <dm/uclass-internal.h>
#include <dm/pinctrl.h>
#include <dm/ofnode.h>
+#include "../sysfw-loader.h"
+#include "../common.h"
+
#define RTC_BASE_ADDRESS 0x2b1f0000
#define REG_K3RTC_S_CNT_LSW (RTC_BASE_ADDRESS + 0x18)
#define REG_K3RTC_KICK0 (RTC_BASE_ADDRESS + 0x70)
diff --git a/arch/arm/mach-k3/am64x/Makefile b/arch/arm/mach-k3/am64x/Makefile
new file mode 100644
index 0000000..d0b2862
--- /dev/null
+++ b/arch/arm/mach-k3/am64x/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_SPL_BUILD) += am642_init.o
+obj-y += boot.o
diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am64x/am642_init.c
similarity index 77%
rename from arch/arm/mach-k3/am642_init.c
rename to arch/arm/mach-k3/am64x/am642_init.c
index 80c3cb3..41812b7 100644
--- a/arch/arm/mach-k3/am642_init.c
+++ b/arch/arm/mach-k3/am64x/am642_init.c
@@ -11,8 +11,6 @@
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
-#include "sysfw-loader.h"
-#include "common.h"
#include <linux/soc/ti/ti_sci_protocol.h>
#include <dm.h>
#include <dm/uclass-internal.h>
@@ -21,6 +19,9 @@
#include <dm/root.h>
#include <command.h>
+#include "../sysfw-loader.h"
+#include "../common.h"
+
#define CTRLMMR_MCU_RST_CTRL 0x04518170
#define CTRLMMR_MCU_RST_SRC (MCU_CTRL_MMR0_BASE + 0x18178)
@@ -285,97 +286,7 @@
}
}
-static u32 __get_backup_bootmedia(u32 main_devstat)
-{
- u32 bkup_bootmode =
- (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >>
- MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT;
- u32 bkup_bootmode_cfg =
- (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >>
- MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT;
-
- switch (bkup_bootmode) {
- case BACKUP_BOOT_DEVICE_UART:
- return BOOT_DEVICE_UART;
-
- case BACKUP_BOOT_DEVICE_DFU:
- if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK)
- return BOOT_DEVICE_USB;
- return BOOT_DEVICE_DFU;
-
-
- case BACKUP_BOOT_DEVICE_ETHERNET:
- return BOOT_DEVICE_ETHERNET;
-
- case BACKUP_BOOT_DEVICE_MMC:
- if (bkup_bootmode_cfg)
- return BOOT_DEVICE_MMC2;
- return BOOT_DEVICE_MMC1;
-
- case BACKUP_BOOT_DEVICE_SPI:
- return BOOT_DEVICE_SPI;
-
- case BACKUP_BOOT_DEVICE_I2C:
- return BOOT_DEVICE_I2C;
- };
-
- return BOOT_DEVICE_RAM;
-}
-
-static u32 __get_primary_bootmedia(u32 main_devstat)
-{
- u32 bootmode = (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
- MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
- u32 bootmode_cfg =
- (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
- MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
-
- switch (bootmode) {
- case BOOT_DEVICE_OSPI:
- fallthrough;
- case BOOT_DEVICE_QSPI:
- fallthrough;
- case BOOT_DEVICE_XSPI:
- fallthrough;
- case BOOT_DEVICE_SPI:
- return BOOT_DEVICE_SPI;
-
- case BOOT_DEVICE_ETHERNET_RGMII:
- fallthrough;
- case BOOT_DEVICE_ETHERNET_RMII:
- return BOOT_DEVICE_ETHERNET;
-
- case BOOT_DEVICE_EMMC:
- return BOOT_DEVICE_MMC1;
-
- case BOOT_DEVICE_NAND:
- return BOOT_DEVICE_NAND;
-
- case BOOT_DEVICE_MMC:
- if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
- MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
- return BOOT_DEVICE_MMC2;
- return BOOT_DEVICE_MMC1;
-
- case BOOT_DEVICE_DFU:
- if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >>
- MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT)
- return BOOT_DEVICE_USB;
- return BOOT_DEVICE_DFU;
-
- case BOOT_DEVICE_NOBOOT:
- return BOOT_DEVICE_RAM;
- }
-
- return bootmode;
-}
-
u32 spl_boot_device(void)
{
- u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
-
- if (bootindex == K3_PRIMARY_BOOTMODE)
- return __get_primary_bootmedia(devstat);
- else
- return __get_backup_bootmedia(devstat);
+ return get_boot_device();
}
diff --git a/arch/arm/mach-k3/am64x/boot.c b/arch/arm/mach-k3/am64x/boot.c
new file mode 100644
index 0000000..ce8ae94
--- /dev/null
+++ b/arch/arm/mach-k3/am64x/boot.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spl.h>
+
+static u32 __get_backup_bootmedia(u32 main_devstat)
+{
+ u32 bkup_bootmode =
+ (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >>
+ MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT;
+ u32 bkup_bootmode_cfg =
+ (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >>
+ MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT;
+
+ switch (bkup_bootmode) {
+ case BACKUP_BOOT_DEVICE_UART:
+ return BOOT_DEVICE_UART;
+
+ case BACKUP_BOOT_DEVICE_DFU:
+ if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK)
+ return BOOT_DEVICE_USB;
+ return BOOT_DEVICE_DFU;
+
+ case BACKUP_BOOT_DEVICE_ETHERNET:
+ return BOOT_DEVICE_ETHERNET;
+
+ case BACKUP_BOOT_DEVICE_MMC:
+ if (bkup_bootmode_cfg)
+ return BOOT_DEVICE_MMC2;
+ return BOOT_DEVICE_MMC1;
+
+ case BACKUP_BOOT_DEVICE_SPI:
+ return BOOT_DEVICE_SPI;
+
+ case BACKUP_BOOT_DEVICE_I2C:
+ return BOOT_DEVICE_I2C;
+ };
+
+ return BOOT_DEVICE_RAM;
+}
+
+static u32 __get_primary_bootmedia(u32 main_devstat)
+{
+ u32 bootmode = (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
+ MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
+ u32 bootmode_cfg =
+ (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
+ MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
+
+ switch (bootmode) {
+ case BOOT_DEVICE_OSPI:
+ fallthrough;
+ case BOOT_DEVICE_QSPI:
+ fallthrough;
+ case BOOT_DEVICE_XSPI:
+ fallthrough;
+ case BOOT_DEVICE_SPI:
+ return BOOT_DEVICE_SPI;
+
+ case BOOT_DEVICE_ETHERNET_RGMII:
+ fallthrough;
+ case BOOT_DEVICE_ETHERNET_RMII:
+ return BOOT_DEVICE_ETHERNET;
+
+ case BOOT_DEVICE_EMMC:
+ return BOOT_DEVICE_MMC1;
+
+ case BOOT_DEVICE_NAND:
+ return BOOT_DEVICE_NAND;
+
+ case BOOT_DEVICE_MMC:
+ if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
+ MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
+ return BOOT_DEVICE_MMC2;
+ return BOOT_DEVICE_MMC1;
+
+ case BOOT_DEVICE_DFU:
+ if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >>
+ MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT)
+ return BOOT_DEVICE_USB;
+ return BOOT_DEVICE_DFU;
+
+ case BOOT_DEVICE_NOBOOT:
+ return BOOT_DEVICE_RAM;
+ }
+
+ return bootmode;
+}
+
+u32 get_boot_device(void)
+{
+ u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
+ u32 bootmode = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
+ u32 bootmedia;
+
+ if (bootmode == K3_PRIMARY_BOOTMODE)
+ bootmedia = __get_primary_bootmedia(devstat);
+ else
+ bootmedia = __get_backup_bootmedia(devstat);
+
+ debug("%s: devstat = 0x%x bootmedia = 0x%x bootmode = %d\n",
+ __func__, devstat, bootmedia, bootmode);
+
+ return bootmedia;
+}
diff --git a/arch/arm/mach-k3/am65x/Makefile b/arch/arm/mach-k3/am65x/Makefile
new file mode 100644
index 0000000..20d5f1d
--- /dev/null
+++ b/arch/arm/mach-k3/am65x/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+# Andrew Davis <afd@ti.com>
+
+obj-$(CONFIG_OF_SYSTEM_SETUP) += am654_fdt.o
+obj-$(CONFIG_SPL_BUILD) += am654_init.o
diff --git a/arch/arm/mach-k3/am654_fdt.c b/arch/arm/mach-k3/am65x/am654_fdt.c
similarity index 88%
rename from arch/arm/mach-k3/am654_fdt.c
rename to arch/arm/mach-k3/am65x/am654_fdt.c
index 652fe8d..bcb1520 100644
--- a/arch/arm/mach-k3/am654_fdt.c
+++ b/arch/arm/mach-k3/am65x/am654_fdt.c
@@ -3,9 +3,10 @@
* Copyright 2023 Toradex - https://www.toradex.com/
*/
-#include "common_fdt.h"
#include <fdt_support.h>
+#include "../common_fdt.h"
+
int ft_system_setup(void *blob, struct bd_info *bd)
{
return fdt_fixup_msmc_ram_k3(blob);
diff --git a/arch/arm/mach-k3/am654_init.c b/arch/arm/mach-k3/am65x/am654_init.c
similarity index 99%
rename from arch/arm/mach-k3/am654_init.c
rename to arch/arm/mach-k3/am65x/am654_init.c
index 7c2a143..a4f0380 100644
--- a/arch/arm/mach-k3/am654_init.c
+++ b/arch/arm/mach-k3/am65x/am654_init.c
@@ -12,8 +12,6 @@
#include <asm/io.h>
#include <spl.h>
#include <asm/arch/hardware.h>
-#include "sysfw-loader.h"
-#include "common.h"
#include <dm.h>
#include <dm/uclass-internal.h>
#include <dm/pinctrl.h>
@@ -22,6 +20,9 @@
#include <mmc.h>
#include <stdlib.h>
+#include "../sysfw-loader.h"
+#include "../common.h"
+
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_K3_LOAD_SYSFW
diff --git a/arch/arm/mach-k3/j721e/Makefile b/arch/arm/mach-k3/j721e/Makefile
new file mode 100644
index 0000000..982b88d
--- /dev/null
+++ b/arch/arm/mach-k3/j721e/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+# Andrew Davis <afd@ti.com>
+
+obj-$(CONFIG_OF_SYSTEM_SETUP) += j721e_fdt.o
+obj-$(CONFIG_SPL_BUILD) += j721e_init.o
diff --git a/arch/arm/mach-k3/am654_fdt.c b/arch/arm/mach-k3/j721e/j721e_fdt.c
similarity index 88%
copy from arch/arm/mach-k3/am654_fdt.c
copy to arch/arm/mach-k3/j721e/j721e_fdt.c
index 652fe8d..bcb1520 100644
--- a/arch/arm/mach-k3/am654_fdt.c
+++ b/arch/arm/mach-k3/j721e/j721e_fdt.c
@@ -3,9 +3,10 @@
* Copyright 2023 Toradex - https://www.toradex.com/
*/
-#include "common_fdt.h"
#include <fdt_support.h>
+#include "../common_fdt.h"
+
int ft_system_setup(void *blob, struct bd_info *bd)
{
return fdt_fixup_msmc_ram_k3(blob);
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e/j721e_init.c
similarity index 99%
rename from arch/arm/mach-k3/j721e_init.c
rename to arch/arm/mach-k3/j721e/j721e_init.c
index 7ee9b75..c2024f2 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e/j721e_init.c
@@ -11,8 +11,6 @@
#include <asm/io.h>
#include <asm/armv7_mpu.h>
#include <asm/arch/hardware.h>
-#include "sysfw-loader.h"
-#include "common.h"
#include <linux/soc/ti/ti_sci_protocol.h>
#include <dm.h>
#include <dm/uclass-internal.h>
@@ -22,6 +20,9 @@
#include <mmc.h>
#include <remoteproc.h>
+#include "../sysfw-loader.h"
+#include "../common.h"
+
#ifdef CONFIG_K3_LOAD_SYSFW
struct fwl_data cbass_hc_cfg0_fwls[] = {
#if defined(CONFIG_TARGET_J721E_R5_EVM)
diff --git a/arch/arm/mach-k3/j721e_fdt.c b/arch/arm/mach-k3/j721e_fdt.c
deleted file mode 100644
index 652fe8d..0000000
--- a/arch/arm/mach-k3/j721e_fdt.c
+++ /dev/null
@@ -1,12 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright 2023 Toradex - https://www.toradex.com/
- */
-
-#include "common_fdt.h"
-#include <fdt_support.h>
-
-int ft_system_setup(void *blob, struct bd_info *bd)
-{
- return fdt_fixup_msmc_ram_k3(blob);
-}
diff --git a/arch/arm/mach-k3/j721s2/Makefile b/arch/arm/mach-k3/j721s2/Makefile
new file mode 100644
index 0000000..ceef682
--- /dev/null
+++ b/arch/arm/mach-k3/j721s2/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+# Andrew Davis <afd@ti.com>
+
+obj-$(CONFIG_OF_SYSTEM_SETUP) += j721s2_fdt.o
+obj-$(CONFIG_SPL_BUILD) += j721s2_init.o
diff --git a/arch/arm/mach-k3/am654_fdt.c b/arch/arm/mach-k3/j721s2/j721s2_fdt.c
similarity index 88%
copy from arch/arm/mach-k3/am654_fdt.c
copy to arch/arm/mach-k3/j721s2/j721s2_fdt.c
index 652fe8d..bcb1520 100644
--- a/arch/arm/mach-k3/am654_fdt.c
+++ b/arch/arm/mach-k3/j721s2/j721s2_fdt.c
@@ -3,9 +3,10 @@
* Copyright 2023 Toradex - https://www.toradex.com/
*/
-#include "common_fdt.h"
#include <fdt_support.h>
+#include "../common_fdt.h"
+
int ft_system_setup(void *blob, struct bd_info *bd)
{
return fdt_fixup_msmc_ram_k3(blob);
diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2/j721s2_init.c
similarity index 99%
rename from arch/arm/mach-k3/j721s2_init.c
rename to arch/arm/mach-k3/j721s2/j721s2_init.c
index 3374889..fe9766e 100644
--- a/arch/arm/mach-k3/j721s2_init.c
+++ b/arch/arm/mach-k3/j721s2/j721s2_init.c
@@ -11,8 +11,6 @@
#include <asm/io.h>
#include <asm/armv7_mpu.h>
#include <asm/arch/hardware.h>
-#include "sysfw-loader.h"
-#include "common.h"
#include <linux/soc/ti/ti_sci_protocol.h>
#include <dm.h>
#include <dm/uclass-internal.h>
@@ -21,6 +19,9 @@
#include <mmc.h>
#include <remoteproc.h>
+#include "../sysfw-loader.h"
+#include "../common.h"
+
struct fwl_data cbass_hc_cfg0_fwls[] = {
{ "PCIE0_CFG", 2577, 7 },
{ "EMMC8SS0_CFG", 2579, 4 },
diff --git a/arch/arm/mach-k3/j721s2_fdt.c b/arch/arm/mach-k3/j721s2_fdt.c
deleted file mode 100644
index 652fe8d..0000000
--- a/arch/arm/mach-k3/j721s2_fdt.c
+++ /dev/null
@@ -1,12 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright 2023 Toradex - https://www.toradex.com/
- */
-
-#include "common_fdt.h"
-#include <fdt_support.h>
-
-int ft_system_setup(void *blob, struct bd_info *bd)
-{
- return fdt_fixup_msmc_ram_k3(blob);
-}
diff --git a/arch/arm/mach-k3/j784s4/Makefile b/arch/arm/mach-k3/j784s4/Makefile
new file mode 100644
index 0000000..6d1841e
--- /dev/null
+++ b/arch/arm/mach-k3/j784s4/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+# Andrew Davis <afd@ti.com>
+
+obj-$(CONFIG_OF_SYSTEM_SETUP) += j784s4_fdt.o
+obj-$(CONFIG_SPL_BUILD) += j784s4_init.o
diff --git a/arch/arm/mach-k3/j784s4_fdt.c b/arch/arm/mach-k3/j784s4/j784s4_fdt.c
similarity index 91%
rename from arch/arm/mach-k3/j784s4_fdt.c
rename to arch/arm/mach-k3/j784s4/j784s4_fdt.c
index d05ed8b..e127509 100644
--- a/arch/arm/mach-k3/j784s4_fdt.c
+++ b/arch/arm/mach-k3/j784s4/j784s4_fdt.c
@@ -6,9 +6,10 @@
* Apurva Nandan <a-nandan@ti.com>
*/
-#include "common_fdt.h"
#include <fdt_support.h>
+#include "../common_fdt.h"
+
int ft_system_setup(void *blob, struct bd_info *bd)
{
return fdt_fixup_msmc_ram_k3(blob);
diff --git a/arch/arm/mach-k3/j784s4_init.c b/arch/arm/mach-k3/j784s4/j784s4_init.c
similarity index 99%
rename from arch/arm/mach-k3/j784s4_init.c
rename to arch/arm/mach-k3/j784s4/j784s4_init.c
index ae44203..1ce13e0 100644
--- a/arch/arm/mach-k3/j784s4_init.c
+++ b/arch/arm/mach-k3/j784s4/j784s4_init.c
@@ -11,8 +11,6 @@
#include <asm/io.h>
#include <asm/armv7_mpu.h>
#include <asm/arch/hardware.h>
-#include "sysfw-loader.h"
-#include "common.h"
#include <linux/soc/ti/ti_sci_protocol.h>
#include <dm.h>
#include <dm/uclass-internal.h>
@@ -20,6 +18,9 @@
#include <mmc.h>
#include <remoteproc.h>
+#include "../sysfw-loader.h"
+#include "../common.h"
+
#define J784S4_MAX_DDR_CONTROLLERS 4
struct fwl_data infra_cbass0_fwls[] = {
diff --git a/arch/arm/mach-sc5xx/Kconfig b/arch/arm/mach-sc5xx/Kconfig
new file mode 100644
index 0000000..3846b4f
--- /dev/null
+++ b/arch/arm/mach-sc5xx/Kconfig
@@ -0,0 +1,475 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# (C) Copyright 2022 - Analog Devices, Inc.
+#
+# Written and/or maintained by Timesys Corporation
+#
+# Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+# Contact: Greg Malysa <greg.malysa@timesys.com>
+#
+
+# All 32-bit platforms require SYS_ARM_CACHE_WRITETHROUGH
+# But it is ignored if selected here, so it must be in the defconfig
+
+if ARCH_SC5XX
+
+config SC57X
+ bool
+ select SUPPORT_SPL
+ select CPU_V7A
+ select PANIC_HANG
+ select COMMON_CLK_ADI_SC57X
+ select TIMER
+ select ADI_SC5XX_TIMER
+
+config SC58X
+ bool
+ select SUPPORT_SPL
+ select CPU_V7A
+ select PANIC_HANG
+ select COMMON_CLK_ADI_SC58X
+ select TIMER
+ select ADI_SC5XX_TIMER
+
+config SC59X
+ bool
+ select SUPPORT_SPL
+ select CPU_V7A
+ select PANIC_HANG
+ select COMMON_CLK_ADI_SC594
+ select TIMER
+ select ADI_SC5XX_TIMER
+ select NOP_PHY
+
+config SC59X_64
+ bool
+ select SUPPORT_SPL
+ select PANIC_HANG
+ select MMC_SDHCI_ADMA_FORCE_32BIT
+ select ARM64
+ select DM
+ select DM_SERIAL
+ select COMMON_CLK_ADI_SC598
+ select GICV3
+ select GIC_600_CLEAR_RDPD
+ select NOP_PHY
+
+config SC_BOOT_MODE
+ int "SC5XX boot mode select"
+ default 1
+ range 0 7
+ help
+ Mode 0: do nothing, just idle
+ Mode 1: boot ldr out of serial flash
+ Mode 7: boot ldr over uart
+
+config SC_BOOT_SPI_BUS
+ int "sc5xx spi boot bus"
+ default 2
+ range 0 4
+ help
+ This is the SPI peripheral number to use for booting, X in the
+ expression `sf probe X:Y`
+
+config SC_BOOT_SPI_SSEL
+ int "sc5xx spi boot chipselect"
+ default 1
+ range 0 6
+ help
+ This is the SPI chip select number to use for booting, Y in the
+ expression `sf probe X:Y`
+
+config SC_BOOT_OSPI_BUS
+ int "sc5xx ospi boot bus"
+ default 0
+ help
+ This is the OSPI peripheral number to use for booting, X in the
+ expression `sf probe X:Y`
+
+config SC_BOOT_OSPI_SSEL
+ int "sc5xx ospi boot chipselect"
+ default 0
+ help
+ This is the OSPI chip select number to use for booting, Y in the
+ expression `sf probe X:Y`
+
+config SYS_FLASH_BASE
+ hex
+ default 0x60000000
+
+config UART_CONSOLE
+ int
+ default 0
+
+config UART4_SERIAL
+ bool
+ depends on DM_SERIAL
+ default y
+
+config WDT_ADI
+ bool
+ default y
+
+config WATCHDOG_TIMEOUT_MSECS
+ int
+ default 30000
+
+config DW_PORTS
+ int
+ default 1
+
+config ADI_BUG_EZKHW21
+ bool "SC584 EZKIT phy bug workaround"
+ depends on SC58X
+ help
+ This workaround affects the SC584 EZKIT and addresses bug EZKHW21.
+ It disables gigabit ethernet mode and limits the board to 100 Mbps
+
+config ADI_CARRIER_SOMCRR_EZKIT
+ bool "Support the EV-SOMCRR-EZKIT"
+ depends on (SC59X || SC59X_64)
+ help
+ Say y to include support for the EV-SOMCRR-EZKIT carrier board,
+ which is compatible with the SC594 and SC598 SOMs. The EZKIT is
+ mutually incompatible with the EZLITE.
+
+config ADI_CARRIER_SOMCRR_EZLITE
+ bool "Support the EV-SOMCRR-EZLITE"
+ depends on (SC59X || SC59X_64)
+ help
+ Say y to include support for the EV-SOMCRR-EZLITE carrier board,
+ which is compatible with the SC594 and SC598 SOMs. The EZLITE is
+ mutually incompatible with the EZKIT.
+
+config ADI_SPL_FORCE_BMODE
+ int "Force the SPL to use this BMODE device during next boot stage"
+ default 0
+ range 0 9
+ depends on SPL
+ help
+ Force the SPL to use this BMODE device during next boot stage.
+ For example, if booting via QSPI, we can force the second stage
+ Of the boot process to use other peripherals via:
+ 1 = QSPI -> QSPI
+ 5 = QSPI -> OSPI
+ 6 = QSPI -> eMMC
+
+config ADI_USE_DMC0
+ bool "Configure DMC0"
+ default y
+ help
+ During hardware initialization, channel 0 of the DMC will be
+ initialized. Select this if you have DMC0 connected to external
+ DDR memory. This is expected to be true for every board using
+ an SC5xx SoC.
+
+config ADI_USE_DMC1
+ bool "Configure DMC1"
+ help
+ During hardware initialization, channel 1 of the DMC will be
+ initialized. Not all processors have a DMC1. Select this if your
+ SoC has DMC1 and you have it connected to external DDR memory.
+
+config ADI_USE_DDR2
+ bool "Configure DMC for DDR2 mode"
+ help
+ Configure the DMC in DDR2 mode. The default is DDR3 and not all
+ parts may actually support DDR2. Please consult the manual for
+ the SoC that you are using to determine if DDR2 mode is supported.
+ This also requires that DDR2 memory is present on the board or it
+ will probably cause strange failure.
+
+menu "Clock configuration"
+
+config CGU0_DF_DIV
+ int "CGU0_DF_DIV"
+ range 0 1
+ help
+ Select 0 to pass CLKIN to PLL
+ Select 1 to pass CLKIN/2 to PLL
+
+config CGU0_VCO_MULT
+ int "CGU0_VCO_MULT"
+ range 0 127
+ help
+ VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL
+ A value of 0 means 128
+
+config CGU0_CCLK_DIV
+ int "CGU0_CCLK_DIV"
+ range 0 31
+ help
+ CCLK_DIV controls the core clock divider
+ A value of 0 means 32
+ CCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / CCLK_DIV
+
+config CGU0_SCLK_DIV
+ int "CGU0_SCLK_DIV"
+ range 0 31
+ help
+ SCLK_DIV controls the system clock divider
+ A value of 0 means 32
+ SCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / SYSCLK_DIV
+
+config CGU0_SCLK0_DIV
+ int "CGU0_SCLK0_DIV"
+ range 0 7
+ help
+ A value of 0 means 8
+ SCLK0 = SCLK / SCLK0_DIV
+
+config CGU0_SCLK1_DIV
+ int "CGU0_SCLK1_DIV"
+ depends on (SC57X || SC58X)
+ range 0 7
+ help
+ A value of 0 means 8
+ SCLK1 = SCLK / SCLK1_DIV
+
+config CGU0_DCLK_DIV
+ int "CGU0_DCLK_DIV"
+ range 0 31
+ help
+ DCLK_DIV controls the DDR clock divider
+ A value of 0 means 32
+ DCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / DCLK_DIV
+
+config CGU0_OCLK_DIV
+ int "CGU0_OCLK_DIV"
+ range 0 127
+ help
+ OCLK_DIV controls the output clock divider
+ A value of 0 means 128
+ OCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / OCLK_DIV
+
+config CGU0_DIV_S1SELEX
+ int "CGU0_DIV_S1SELEX"
+ depends on !SC57X && !SC58X
+ range 0 255
+ help
+ CGU0 SCLK1 Extended divisor register.
+ A value of 0 means 256.
+ SCLK1 = ((CLKIN / (1 + DF)) * VCO_MULT) / DIV_S1SELEX
+
+config CGU0_CLKOUTSEL
+ int "CGU0_CLKOUTSEL"
+ default 0
+ range 0 31
+ help
+ Select signal driven through CLKOUT pin multiplexer.
+ This value varies on each SOC. Refer to
+ CGU_CLKOUTSEL.CLKOUTSEL in the Hardware Reference Manual
+ for values applicable to each SOC.
+ Commonly, values 0 and 1 select CLKIN0 or CLKIN1 respectively.
+
+config CGU1_PLL3_DDRCLK
+ bool "DDRCLK From 3rd PLL"
+ depends on SC59X_64
+ help
+ 3rd PLL output is connected to DMC block when set.
+ When cleared, DDR clock is CLKO3 output of CDU.
+
+config CGU1_PLL3_VCO_MSEL
+ int "CGU0_PLL3_VCO_MSEL"
+ depends on CGU1_PLL3_DDRCLK
+ range 1 128
+ help
+ PLL multiplier value for the 3rd PLL.
+ DCLK = (CLKIN * PLL3_VCO_MSEL) / PLL3_DCLK_DIV
+
+config CGU1_PLL3_DCLK_DIV
+ int "CGU0_PLL3_DCLK_DIV"
+ depends on CGU1_PLL3_DDRCLK
+ range 1 32
+ help
+ PLL divider value for the 3rd PLL.
+ DCLK = (CLKIN * PLL3_VCO_MSEL) / PLL3_DCLK_DIV
+
+config CGU1_DF_DIV
+ int "CGU1_DF_DIV"
+ range 0 1
+ help
+ Select 0 to pass CLKIN to PLL
+ Select 1 to pass CLKIN/2 to PLL
+
+config CGU1_VCO_MULT
+ int "CGU1_VCO_MULT"
+ range 0 127
+ help
+ VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL
+ A value of 0 means 128
+
+config CGU1_CCLK_DIV
+ int "CGU1_CCLK_DIV"
+ range 0 31
+ help
+ CCLK_DIV controls the core clock divider
+ A value of 0 means 32
+ CCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / CCLK_DIV
+
+config CGU1_SCLK_DIV
+ int "CGU1_SCLK_DIV"
+ range 0 31
+ help
+ SCLK_DIV controls the system clock divider
+ A value of 0 means 32
+ SCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / SYSCLK_DIV
+
+config CGU1_SCLK0_DIV
+ int "CGU1_SCLK0_DIV"
+ depends on (SC57X || SC58X || SC59X)
+ range 0 7
+ help
+ A value of 0 means 8
+ SCLK0 = SCLK / SCLK0_DIV
+
+config CGU1_SCLK1_DIV
+ int "CGU1_SCLK1_DIV"
+ depends on (SC57X || SC58X)
+ range 0 7
+ help
+ A value of 0 means 8
+ SCLK1 = SCLK / SCLK1_DIV
+
+config CGU1_DCLK_DIV
+ int "CGU1_DCLK_DIV"
+ range 0 31
+ help
+ DCLK_DIV controls the DDR clock divider
+ A value of 0 means 32
+ DCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / DCLK_DIV
+
+config CGU1_OCLK_DIV
+ int "CGU1_OCLK_DIV"
+ range 0 127
+ help
+ OCLK_DIV controls the output clock divider
+ A value of 0 means 128
+ OCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / OCLK_DIV
+
+config CGU1_DIV_S0SELEX
+ int "CGU1_DIV_S0SELEX"
+ depends on !SC57X && !SC58X && !SC59X
+ range 0 255
+ help
+ CGU1 SCLK0 Extended divisor register.
+ A value of 0 means 256.
+ SCLK0 = ((CLKIN / (1 + DF)) * VCO_MULT) / DIV_S0SELEX
+
+config CGU1_DIV_S1SELEX
+ int "CGU1_DIV_S1SELEX"
+ depends on !SC57X && !SC58X
+ range 0 255
+ help
+ CGU1 SCLK1 Extended divisor register.
+ A value of 0 means 256.
+ SCLK1 = ((CLKIN / (1 + DF)) * VCO_MULT) / DIV_S1SELEX
+
+config CDU0_CGU1_CLKIN
+ int "CDU0 CGU1 CLKINn Select"
+ default 0
+ range 0 1
+ help
+ Selects source clock for CGU1.
+ 0 for CLKIN0
+ 1 for CLKIN1
+
+config CDU0_CLKO0
+ int "CDU0_CLKO0"
+ range 1 7
+ help
+ Clock source select. Refer to SOC Hardware Reference Manual
+
+config CDU0_CLKO1
+ int "CDU0_CLKO1"
+ range 1 7
+ help
+ Clock source select. Refer to SOC Hardware Reference Manual
+
+config CDU0_CLKO2
+ int "CDU0_CLKO2"
+ range 1 7
+ help
+ Clock source select. Refer to SOC Hardware Reference Manual
+
+config CDU0_CLKO3
+ int "CDU0_CLKO3"
+ range 1 7
+ help
+ Clock source select. Refer to SOC Hardware Reference Manual
+
+config CDU0_CLKO4
+ int "CDU0_CLKO4"
+ range 1 7
+ help
+ Clock source select. Refer to SOC Hardware Reference Manual
+
+config CDU0_CLKO5
+ int "CDU0_CLKO5"
+ range 1 7
+ help
+ Clock source select. Refer to SOC Hardware Reference Manual
+
+config CDU0_CLKO6
+ int "CDU0_CLKO6"
+ range 1 7
+ help
+ Clock source select. Refer to SOC Hardware Reference Manual
+
+config CDU0_CLKO7
+ int "CDU0_CLKO7"
+ range 1 7
+ help
+ Clock source select. Refer to SOC Hardware Reference Manual
+
+config CDU0_CLKO8
+ int "CDU0_CLKO8"
+ range 1 7
+ help
+ Clock source select. Refer to SOC Hardware Reference Manual
+
+config CDU0_CLKO9
+ int "CDU0_CLKO9"
+ range 1 7
+ help
+ Clock source select. Refer to SOC Hardware Reference Manual
+
+config CDU0_CLKO10
+ int "CDU0_CLKO10"
+ range 1 7
+ depends on (SC59X || SC59X_64)
+ help
+ Clock source select. Refer to SOC Hardware Reference Manual
+
+config CDU0_CLKO12
+ int "CDU0_CLKO12"
+ range 1 7
+ depends on (SC59X || SC59X_64)
+ help
+ Clock source select. Refer to SOC Hardware Reference Manual
+
+config CDU0_CLKO13
+ int "CDU0_CLKO13"
+ range 1 7
+ depends on SC59X_64
+ help
+ Clock source select. Refer to SOC Hardware Reference Manual
+
+config CDU0_CLKO14
+ int "CDU0_CLKO14"
+ range 1 7
+ depends on SC59X_64
+ help
+ Clock source select. Refer to SOC Hardware Reference Manual
+
+endmenu
+
+config ADI_GPIO
+ bool
+ default y
+
+config PINCTRL_ADI
+ bool
+ default y
+
+endif
diff --git a/arch/arm/mach-sc5xx/Makefile b/arch/arm/mach-sc5xx/Makefile
new file mode 100644
index 0000000..eeb56c0
--- /dev/null
+++ b/arch/arm/mach-sc5xx/Makefile
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# (C) Copyright 2022 - Analog Devices, Inc.
+#
+# Written and/or maintained by Timesys Corporation
+#
+# Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+# Contact: Greg Malysa <greg.malysa@timesys.com>
+#
+
+obj-y += soc.o init/
+
+obj-$(CONFIG_SC57X) += sc57x.o
+obj-$(CONFIG_SC58X) += sc58x.o
+obj-$(CONFIG_SC59X) += sc59x.o
+obj-$(CONFIG_SC59X_64) += sc59x_64.o
+
+obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_SYSCON) += rcu.o
diff --git a/arch/arm/mach-sc5xx/config.mk b/arch/arm/mach-sc5xx/config.mk
new file mode 100644
index 0000000..580964e
--- /dev/null
+++ b/arch/arm/mach-sc5xx/config.mk
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# (C) Copyright 2022 - Analog Devices, Inc.
+#
+# Written and/or maintained by Timesys Corporation
+#
+# Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+# Contact: Greg Malysa <greg.malysa@timesys.com>
+#
+
+ifdef CONFIG_SPL_BUILD
+INPUTS-y += $(obj)/u-boot-spl.ldr
+endif
+
+LDR_FLAGS += --bcode=$(CONFIG_SC_BOOT_MODE)
+LDR_FLAGS += --use-vmas
diff --git a/arch/arm/mach-sc5xx/init/Makefile b/arch/arm/mach-sc5xx/init/Makefile
new file mode 100644
index 0000000..9d4920f
--- /dev/null
+++ b/arch/arm/mach-sc5xx/init/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# (C) Copyright 2022 - Analog Devices, Inc.
+#
+# Written and/or maintained by Timesys Corporation
+#
+# Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+# Contact: Greg Malysa <greg.malysa@timesys.com>
+#
+
+obj-y += dmcinit.o clkinit.o
diff --git a/arch/arm/mach-sc5xx/init/clkinit.c b/arch/arm/mach-sc5xx/init/clkinit.c
new file mode 100644
index 0000000..ae53cd6
--- /dev/null
+++ b/arch/arm/mach-sc5xx/init/clkinit.c
@@ -0,0 +1,558 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ * Contact: Greg Malysa <greg.malysa@timesys.com>
+ */
+
+#include <asm/arch-adi/sc5xx/sc5xx.h>
+#include <asm/io.h>
+#include <linux/types.h>
+#include "clkinit.h"
+#include "dmcinit.h"
+
+#ifdef CONFIG_CGU0_SCLK0_DIV
+ #define VAL_CGU0_SCLK0_DIV CONFIG_CGU0_SCLK0_DIV
+#else
+ #define VAL_CGU0_SCLK0_DIV 1
+#endif
+#ifdef CONFIG_CGU0_SCLK1_DIV
+ #define VAL_CGU0_SCLK1_DIV CONFIG_CGU0_SCLK1_DIV
+#else
+ #define VAL_CGU0_SCLK1_DIV 1
+#endif
+#ifdef CONFIG_CGU0_DIV_S0SELEX
+ #define VAL_CGU0_DIV_S0SELEX CONFIG_CGU0_DIV_S0SELEX
+#else
+ #define VAL_CGU0_DIV_S0SELEX -1
+#endif
+#ifdef CONFIG_CGU0_DIV_S1SELEX
+ #define VAL_CGU0_DIV_S1SELEX CONFIG_CGU0_DIV_S1SELEX
+#else
+ #define VAL_CGU0_DIV_S1SELEX -1
+#endif
+#ifdef CONFIG_CGU0_CLKOUTSEL
+ #define VAL_CGU0_CLKOUTSEL CONFIG_CGU0_CLKOUTSEL
+#else
+ #define VAL_CGU0_CLKOUTSEL -1
+#endif
+#ifdef CONFIG_CGU1_SCLK0_DIV
+ #define VAL_CGU1_SCLK0_DIV CONFIG_CGU1_SCLK0_DIV
+#else
+ #define VAL_CGU1_SCLK0_DIV 1
+#endif
+#ifdef CONFIG_CGU1_SCLK1_DIV
+ #define VAL_CGU1_SCLK1_DIV CONFIG_CGU1_SCLK1_DIV
+#else
+ #define VAL_CGU1_SCLK1_DIV 1
+#endif
+#ifdef CONFIG_CGU1_DIV_S0SELEX
+ #define VAL_CGU1_DIV_S0SELEX CONFIG_CGU1_DIV_S0SELEX
+#else
+ #define VAL_CGU1_DIV_S0SELEX -1
+#endif
+#ifdef CONFIG_CGU1_DIV_S1SELEX
+ #define VAL_CGU1_DIV_S1SELEX CONFIG_CGU1_DIV_S1SELEX
+#else
+ #define VAL_CGU1_DIV_S1SELEX -1
+#endif
+#ifdef CONFIG_CGU1_CLKOUTSEL
+ #define VAL_CGU1_CLKOUTSEL CONFIG_CGU1_CLKOUTSEL
+#else
+ #define VAL_CGU1_CLKOUTSEL -1
+#endif
+
+#define REG_MISC_REG10_tst_addr 0x310A902C
+
+#define CGU0_REGBASE 0x3108D000
+#define CGU1_REGBASE 0x3108E000
+
+#define CGU_CTL 0x00 // CGU0 Control Register
+#define CGU_PLLCTL 0x04 // CGU0 PLL Control Register
+#define CGU_STAT 0x08 // CGU0 Status Register
+#define CGU_DIV 0x0C // CGU0 Clocks Divisor Register
+#define CGU_CLKOUTSEL 0x10 // CGU0 CLKOUT Select Register
+#define CGU_DIVEX 0x40 // CGU0 DIV Register Extension
+
+#define BITP_CGU_DIV_OSEL 22 // OUTCLK Divisor
+#define BITP_CGU_DIV_DSEL 16 // DCLK Divisor
+#define BITP_CGU_DIV_S1SEL 13 // SCLK 1 Divisor
+#define BITP_CGU_DIV_SYSSEL 8 // SYSCLK Divisor
+#define BITP_CGU_DIV_S0SEL 5 // SCLK 0 Divisor
+#define BITP_CGU_DIV_CSEL 0 // CCLK Divisor
+
+#define BITP_CGU_CTL_MSEL 8 // Multiplier Select
+#define BITP_CGU_CTL_DF 0 // Divide Frequency
+
+#define BITM_CGU_STAT_CLKSALGN 0x00000008
+#define BITM_CGU_STAT_PLOCK 0x00000004
+#define BITM_CGU_STAT_PLLBP 0x00000002
+#define BITM_CGU_STAT_PLLEN 0x00000001
+
+/* PLL Multiplier and Divisor Selections (Required Value, Bit Position) */
+/* PLL Multiplier Select */
+#define MSEL(X) (((X) << BITP_CGU_CTL_MSEL) & \
+ BITM_CGU_CTL_MSEL)
+/* Divide frequency[true or false] */
+#define DF(X) (((X) << BITP_CGU_CTL_DF) & \
+ BITM_CGU_CTL_DF)
+/* Core Clock Divisor Select */
+#define CSEL(X) (((X) << BITP_CGU_DIV_CSEL) & \
+ BITM_CGU_DIV_CSEL)
+/* System Clock Divisor Select */
+#define SYSSEL(X) (((X) << BITP_CGU_DIV_SYSSEL) & \
+ BITM_CGU_DIV_SYSSEL)
+/* SCLK0 Divisor Select */
+#define S0SEL(X) (((X) << BITP_CGU_DIV_S0SEL) & \
+ BITM_CGU_DIV_S0SEL)
+/* SCLK1 Divisor Select */
+#define S1SEL(X) (((X) << BITP_CGU_DIV_S1SEL) & \
+ BITM_CGU_DIV_S1SEL)
+/* DDR Clock Divisor Select */
+#define DSEL(X) (((X) << BITP_CGU_DIV_DSEL) & \
+ BITM_CGU_DIV_DSEL)
+/* OUTCLK Divisor Select */
+#define OSEL(X) (((X) << BITP_CGU_DIV_OSEL) & \
+ BITM_CGU_DIV_OSEL)
+/* CLKOUT select */
+#define CLKOUTSEL(X) (((X) << BITP_CGU_CLKOUTSEL_CLKOUTSEL) & \
+ BITM_CGU_CLKOUTSEL_CLKOUTSEL)
+#define S0SELEX(X) (((X) << BITP_CGU_DIVEX_S0SELEX) & \
+ BITM_CGU_DIVEX_S0SELEX)
+#define S1SELEX(X) (((X) << BITP_CGU_DIVEX_S1SELEX) & \
+ BITM_CGU_DIVEX_S1SELEX)
+
+struct CGU_Settings {
+ phys_addr_t rbase;
+ u32 ctl_MSEL:7;
+ u32 ctl_DF:1;
+ u32 div_CSEL:5;
+ u32 div_SYSSEL:5;
+ u32 div_S0SEL:3;
+ u32 div_S1SEL:3;
+ u32 div_DSEL:5;
+ u32 div_OSEL:7;
+ s16 divex_S0SELEX;
+ s16 divex_S1SELEX;
+ s8 clkoutsel;
+};
+
+/* CGU Registers */
+#define BITM_CGU_CTL_LOCK 0x80000000 /* Lock */
+
+#define BITM_CGU_CTL_MSEL 0x00007F00 /* Multiplier Select */
+#define BITM_CGU_CTL_DF 0x00000001 /* Divide Frequency */
+#define BITM_CGU_CTL_S1SELEXEN 0x00020000 /* SCLK1 Extension Divider Enable */
+#define BITM_CGU_CTL_S0SELEXEN 0x00010000 /* SCLK0 Extension Divider Enable */
+
+#define BITM_CGU_DIV_LOCK 0x80000000 /* Lock */
+#define BITM_CGU_DIV_UPDT 0x40000000 /* Update Clock Divisors */
+#define BITM_CGU_DIV_ALGN 0x20000000 /* Align */
+#define BITM_CGU_DIV_OSEL 0x1FC00000 /* OUTCLK Divisor */
+#define BITM_CGU_DIV_DSEL 0x001F0000 /* DCLK Divisor */
+#define BITM_CGU_DIV_S1SEL 0x0000E000 /* SCLK 1 Divisor */
+#define BITM_CGU_DIV_SYSSEL 0x00001F00 /* SYSCLK Divisor */
+#define BITM_CGU_DIV_S0SEL 0x000000E0 /* SCLK 0 Divisor */
+#define BITM_CGU_DIV_CSEL 0x0000001F /* CCLK Divisor */
+
+#define BITP_CGU_DIVEX_S0SELEX 0
+#define BITM_CGU_DIVEX_S0SELEX 0x000000FF /* SCLK 0 Extension Divisor */
+
+#define BITP_CGU_DIVEX_S1SELEX 16
+#define BITM_CGU_DIVEX_S1SELEX 0x00FF0000 /* SCLK 1 Extension Divisor */
+
+#define BITM_CGU_PLLCTL_PLLEN 0x00000008 /* PLL Enable */
+#define BITM_CGU_PLLCTL_PLLBPCL 0x00000002 /* PLL Bypass Clear */
+#define BITM_CGU_PLLCTL_PLLBPST 0x00000001 /* PLL Bypass Set */
+
+#define BITP_CGU_CLKOUTSEL_CLKOUTSEL 0 /* CLKOUT Select */
+#define BITM_CGU_CLKOUTSEL_CLKOUTSEL 0x0000001F /* CLKOUT Select */
+
+#define CGU_STAT_MASK (BITM_CGU_STAT_PLLEN | BITM_CGU_STAT_PLOCK | \
+ BITM_CGU_STAT_CLKSALGN)
+#define CGU_STAT_ALGN_LOCK (BITM_CGU_STAT_PLLEN | BITM_CGU_STAT_PLOCK)
+
+/* Clock Distribution Unit Registers */
+#define REG_CDU0_CFG0 0x3108F000
+#define REG_CDU0_CFG1 0x3108F004
+#define REG_CDU0_CFG2 0x3108F008
+#define REG_CDU0_CFG3 0x3108F00C
+#define REG_CDU0_CFG4 0x3108F010
+#define REG_CDU0_CFG5 0x3108F014
+#define REG_CDU0_CFG6 0x3108F018
+#define REG_CDU0_CFG7 0x3108F01C
+#define REG_CDU0_CFG8 0x3108F020
+#define REG_CDU0_CFG9 0x3108F024
+#define REG_CDU0_CFG10 0x3108F028
+#define REG_CDU0_CFG11 0x3108F02C
+#define REG_CDU0_CFG12 0x3108F030
+#define REG_CDU0_CFG13 0x3108F034
+#define REG_CDU0_CFG14 0x3108F038
+#define REG_CDU0_STAT 0x3108F040
+#define REG_CDU0_CLKINSEL 0x3108F044
+#define REG_CDU0_REVID 0x3108F048
+
+#define BITM_REG10_MSEL3 0x000007F0
+#define BITP_REG10_MSEL3 4
+
+#define BITM_REG10_DSEL3 0x0001F000
+#define BITP_REG10_DSEL3 12
+
+/* Selected clock macros */
+#define CGUn_MULT(cgu) ((CONFIG_CGU##cgu##_VCO_MULT == 0) ? \
+ 128 : CONFIG_CGU##cgu##_VCO_MULT)
+#define CGUn_DIV(clkname, cgu) ((CONFIG_CGU##cgu##_##clkname##_DIV == 0) ? \
+ 32 : CONFIG_CGU##cgu##_##clkname##_DIV)
+#define CCLK1_n_RATIO(cgu) (((CGUn_MULT(cgu)) / \
+ (1 + CONFIG_CGU##cgu##_DF_DIV)) / \
+ CGUn_DIV(CCLK, cgu))
+#define CCLK2_n_RATIO(cgu) (((CGUn_MULT(cgu) * 2) / 3) / \
+ (1 + CONFIG_CGU##cgu##_DF_DIV))
+#define DCLK_n_RATIO(cgu) (((CGUn_MULT(cgu)) / \
+ (1 + CONFIG_CGU##cgu##_DF_DIV)) / \
+ CGUn_DIV(DCLK, cgu))
+#define SYSCLK_n_RATIO(cgu) (((CGUn_MULT(cgu)) / \
+ (1 + CONFIG_CGU##cgu##_DF_DIV)) / \
+ CGUn_DIV(SCLK, cgu))
+#define PLL3_RATIO ((CONFIG_CGU1_PLL3_VCO_MSEL) / \
+ (CONFIG_CGU1_PLL3_DCLK_DIV))
+
+#if (1 == CONFIG_CDU0_CLKO2)
+ #define ARMCLK_IN 0
+ #define ARMCLK_RATIO CCLK1_n_RATIO(0)
+#elif (3 == CONFIG_CDU0_CLKO2) && \
+ (defined(CONFIG_SC57X) || defined(CONFIG_SC58X))
+ #define ARMCLK_IN 0
+ #define ARMCLK_RATIO SYSCLK_n_RATIO(0)
+#elif (5 == CONFIG_CDU0_CLKO2) && defined(CONFIG_SC59X_64)
+ #define ARMCLK_IN 0
+ #define ARMCLK_RATIO CCLK2_n_RATIO(0)
+#elif (7 == CONFIG_CDU0_CLKO2) && defined(CONFIG_SC59X_64)
+ #define ARMCLK_IN CDU0_CGU1_CLKIN
+ #define ARMCLK_RATIO CCLK2_n_RATIO(1)
+#endif
+
+#ifdef CONFIG_CGU1_PLL3_DDRCLK
+ #define DDRCLK_IN CDU0_CGU1_CLKIN
+ #define DDRCLK_RATIO PLL3_RATIO
+#elif (1 == CONFIG_CDU0_CLKO3)
+ #define DDRCLK_IN 0
+ #define DDRCLK_RATIO DCLK_n_RATIO(0)
+#elif (3 == CONFIG_CDU0_CLKO3)
+ #define DDRCLK_IN CDU0_CGU1_CLKIN
+ #define DDRCLK_RATIO DCLK_n_RATIO(1)
+#endif
+
+#ifndef ARMCLK_RATIO
+ #error Invalid/unknown ARMCLK selection!
+#endif
+#ifndef DDRCLK_RATIO
+ #error Invalid/unknown DDRCLK selection!
+#endif
+
+#define ARMDDR_CLK_RATIO_FPERCISION 1000
+
+#if ARMCLK_IN != DDRCLK_IN
+ #ifndef CUSTOM_ARMDDR_CLK_RATIO
+ /**
+ * SYS_CLKINx are defined within the device tree, not configs.
+ * Thus, we can only determine cross-CGU clock ratios if they
+ * use the same SYS_CLKINx.
+ */
+ #error Define CUSTOM_ARMDDR_CLK_RATIO for different SYS_CLKINs
+ #else
+ #define ARMDDR_CLK_RATIO CUSTOM_ARMDDR_CLK_RATIO
+ #endif
+#else
+ #define ARMDDR_CLK_RATIO (ARMDDR_CLK_RATIO_FPERCISION *\
+ ARMCLK_RATIO / DDRCLK_RATIO)
+#endif
+
+void dmcdelay(uint32_t delay)
+{
+ /* There is no zero-overhead loop on ARM, so assume each iteration
+ * takes 4 processor cycles (based on examination of -O3 and -Ofast
+ * output).
+ */
+ u32 i, remainder;
+
+ /* Convert DDR cycles to core clock cycles */
+ u32 f = delay * ARMDDR_CLK_RATIO;
+
+ delay = f + 500;
+ delay /= ARMDDR_CLK_RATIO_FPERCISION;
+
+ /* Round up to multiple of 4 */
+ remainder = delay % 4;
+ if (remainder != 0u)
+ delay += (4u - remainder);
+
+ for (i = 0; i < delay; i += 4)
+ asm("nop");
+}
+
+static void program_cgu(const struct CGU_Settings *cgu)
+{
+ const uintptr_t b = cgu->rbase;
+ const bool use_extension0 = cgu->divex_S0SELEX >= 0;
+ const bool use_extension1 = cgu->divex_S1SELEX >= 0;
+ u32 temp;
+
+ temp = OSEL(cgu->div_OSEL);
+ temp |= SYSSEL(cgu->div_SYSSEL);
+ temp |= CSEL(cgu->div_CSEL);
+ temp |= DSEL(cgu->div_DSEL);
+ temp |= (S0SEL(cgu->div_S0SEL));
+ temp |= (S1SEL(cgu->div_S1SEL));
+ temp &= ~BITM_CGU_DIV_LOCK;
+
+ //Put PLL in to Bypass Mode
+ writel(BITM_CGU_PLLCTL_PLLEN | BITM_CGU_PLLCTL_PLLBPST,
+ b + CGU_PLLCTL);
+ while (!(readl(b + CGU_STAT) & BITM_CGU_STAT_PLLBP))
+ ;
+
+ while (!((readl(b + CGU_STAT) & CGU_STAT_MASK) == CGU_STAT_ALGN_LOCK))
+ ;
+
+ dmcdelay(1000);
+
+ writel(temp & (~BITM_CGU_DIV_ALGN) & (~BITM_CGU_DIV_UPDT),
+ b + CGU_DIV);
+
+ dmcdelay(1000);
+
+ temp = MSEL(cgu->ctl_MSEL) | DF(cgu->ctl_DF);
+ if (use_extension0)
+ temp |= BITM_CGU_CTL_S0SELEXEN;
+ if (use_extension1)
+ temp |= BITM_CGU_CTL_S1SELEXEN;
+
+ writel(temp & (~BITM_CGU_CTL_LOCK), b + CGU_CTL);
+
+ if (use_extension0 || use_extension1) {
+ u32 mask = BITM_CGU_CTL_S1SELEXEN | BITM_CGU_CTL_S0SELEXEN;
+
+ while (!(readl(b + CGU_CTL) & mask))
+ ;
+
+ temp = readl(b + CGU_DIVEX);
+
+ if (use_extension0) {
+ temp &= ~BITM_CGU_DIVEX_S0SELEX;
+ temp |= S0SELEX(cgu->divex_S0SELEX);
+ }
+
+ if (use_extension1) {
+ temp &= ~BITM_CGU_DIVEX_S1SELEX;
+ temp |= S1SELEX(cgu->divex_S1SELEX);
+ }
+
+ writel(temp, b + CGU_DIVEX);
+ }
+
+ dmcdelay(1000);
+
+ //Take PLL out of Bypass Mode
+ writel(BITM_CGU_PLLCTL_PLLEN | BITM_CGU_PLLCTL_PLLBPCL,
+ b + CGU_PLLCTL);
+ while ((readl(b + CGU_STAT) &
+ (BITM_CGU_STAT_PLLBP | BITM_CGU_STAT_CLKSALGN)))
+ ;
+
+ dmcdelay(1000);
+
+ if (cgu->clkoutsel >= 0) {
+ temp = readl(b + CGU_CLKOUTSEL);
+ temp &= ~BITM_CGU_CLKOUTSEL_CLKOUTSEL;
+ temp |= CLKOUTSEL(cgu->clkoutsel);
+ writel(temp, b + CGU_CLKOUTSEL);
+ }
+}
+
+void adi_config_third_pll(void)
+{
+#if defined(CONFIG_CGU1_PLL3_VCO_MSEL) && defined(CONFIG_CGU1_PLL3_DCLK_DIV)
+ u32 temp;
+
+ u32 msel = CONFIG_CGU1_PLL3_VCO_MSEL - 1;
+ u32 dsel = CONFIG_CGU1_PLL3_DCLK_DIV - 1;
+
+ temp = readl(REG_MISC_REG10_tst_addr);
+ temp &= 0xFFFE0000;
+ writel(temp, REG_MISC_REG10_tst_addr);
+
+ dmcdelay(4000u);
+
+ //update MSEL [10:4]
+ temp = readl(REG_MISC_REG10_tst_addr);
+ temp |= ((msel << BITP_REG10_MSEL3) & BITM_REG10_MSEL3);
+ writel(temp, REG_MISC_REG10_tst_addr);
+
+ temp = readl(REG_MISC_REG10_tst_addr);
+ temp |= 0x2;
+ writel(temp, REG_MISC_REG10_tst_addr);
+
+ dmcdelay(100000u);
+
+ temp = readl(REG_MISC_REG10_tst_addr);
+ temp |= 0x1;
+ writel(temp, REG_MISC_REG10_tst_addr);
+
+ temp = readl(REG_MISC_REG10_tst_addr);
+ temp |= 0x800;
+ writel(temp, REG_MISC_REG10_tst_addr);
+
+ temp = readl(REG_MISC_REG10_tst_addr);
+ temp &= 0xFFFFF7F8;
+ writel(temp, REG_MISC_REG10_tst_addr);
+
+ dmcdelay(4000u);
+
+ temp = readl(REG_MISC_REG10_tst_addr);
+ temp |= ((dsel << BITP_REG10_DSEL3) & BITM_REG10_DSEL3);
+ writel(temp, REG_MISC_REG10_tst_addr);
+
+ temp = readl(REG_MISC_REG10_tst_addr);
+ temp |= 0x4;
+ writel(temp, REG_MISC_REG10_tst_addr);
+
+ dmcdelay(100000u);
+
+ temp = readl(REG_MISC_REG10_tst_addr);
+ temp |= 0x1;
+ writel(temp, REG_MISC_REG10_tst_addr);
+
+ temp = readl(REG_MISC_REG10_tst_addr);
+ temp |= 0x800;
+ writel(temp, REG_MISC_REG10_tst_addr);
+#endif
+}
+
+static void Active_To_Fullon(const struct CGU_Settings *pCGU)
+{
+ u32 tmp;
+
+ while (1) {
+ tmp = readl(pCGU->rbase + CGU_STAT);
+ if ((tmp & BITM_CGU_STAT_PLLEN) &&
+ (tmp & BITM_CGU_STAT_PLLBP))
+ break;
+ }
+
+ writel(BITM_CGU_PLLCTL_PLLBPCL, pCGU->rbase + CGU_PLLCTL);
+
+ while (1) {
+ tmp = readl(pCGU->rbase + CGU_STAT);
+ if ((tmp & BITM_CGU_STAT_PLLEN) &&
+ ~(tmp & BITM_CGU_STAT_PLLBP) &&
+ ~(tmp & BITM_CGU_STAT_CLKSALGN))
+ break;
+ }
+}
+
+static void CGU_Init(const struct CGU_Settings *pCGU)
+{
+ const uintptr_t b = pCGU->rbase;
+
+#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64)
+ if (readl(b + CGU_STAT) & BITM_CGU_STAT_PLLEN)
+ writel(BITM_CGU_PLLCTL_PLLEN, b + CGU_PLLCTL);
+
+ dmcdelay(1000);
+#endif
+
+ /* Check if processor is in Active mode */
+ if (readl(b + CGU_STAT) & BITM_CGU_STAT_PLLBP)
+ Active_To_Fullon(pCGU);
+
+#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64)
+ dmcdelay(1000);
+#endif
+
+ program_cgu(pCGU);
+}
+
+void cgu_init(void)
+{
+ const struct CGU_Settings dividers0 = {
+ .rbase = CGU0_REGBASE,
+ .ctl_MSEL = CONFIG_CGU0_VCO_MULT,
+ .ctl_DF = CONFIG_CGU0_DF_DIV,
+ .div_CSEL = CONFIG_CGU0_CCLK_DIV,
+ .div_SYSSEL = CONFIG_CGU0_SCLK_DIV,
+ .div_S0SEL = VAL_CGU0_SCLK0_DIV,
+ .div_S1SEL = VAL_CGU0_SCLK1_DIV,
+ .div_DSEL = CONFIG_CGU0_DCLK_DIV,
+ .div_OSEL = CONFIG_CGU0_OCLK_DIV,
+ .divex_S0SELEX = VAL_CGU0_DIV_S0SELEX,
+ .divex_S1SELEX = VAL_CGU0_DIV_S1SELEX,
+ .clkoutsel = VAL_CGU0_CLKOUTSEL,
+ };
+ const struct CGU_Settings dividers1 = {
+ .rbase = CGU1_REGBASE,
+ .ctl_MSEL = CONFIG_CGU1_VCO_MULT,
+ .ctl_DF = CONFIG_CGU1_DF_DIV,
+ .div_CSEL = CONFIG_CGU1_CCLK_DIV,
+ .div_SYSSEL = CONFIG_CGU1_SCLK_DIV,
+ .div_S0SEL = VAL_CGU1_SCLK0_DIV,
+ .div_S1SEL = VAL_CGU1_SCLK1_DIV,
+ .div_DSEL = CONFIG_CGU1_DCLK_DIV,
+ .div_OSEL = CONFIG_CGU1_OCLK_DIV,
+ .divex_S0SELEX = VAL_CGU1_DIV_S0SELEX,
+ .divex_S1SELEX = VAL_CGU1_DIV_S1SELEX,
+ .clkoutsel = VAL_CGU1_CLKOUTSEL,
+ };
+
+ CGU_Init(÷rs0);
+ CGU_Init(÷rs1);
+}
+
+#define CONFIGURE_CDU0(a, b, c) \
+ writel(a, b); \
+ while (readl(REG_CDU0_STAT) & (1 << (c)))
+
+void cdu_init(void)
+{
+ while (readl(REG_CDU0_STAT) & 0xffff)
+ ;
+ writel((CONFIG_CDU0_CGU1_CLKIN & 0x1), REG_CDU0_CLKINSEL);
+
+ CONFIGURE_CDU0(CONFIG_CDU0_CLKO0, REG_CDU0_CFG0, 0);
+ CONFIGURE_CDU0(CONFIG_CDU0_CLKO1, REG_CDU0_CFG1, 1);
+ CONFIGURE_CDU0(CONFIG_CDU0_CLKO2, REG_CDU0_CFG2, 2);
+ CONFIGURE_CDU0(CONFIG_CDU0_CLKO3, REG_CDU0_CFG3, 3);
+ CONFIGURE_CDU0(CONFIG_CDU0_CLKO4, REG_CDU0_CFG4, 4);
+ CONFIGURE_CDU0(CONFIG_CDU0_CLKO5, REG_CDU0_CFG5, 5);
+ CONFIGURE_CDU0(CONFIG_CDU0_CLKO6, REG_CDU0_CFG6, 6);
+ CONFIGURE_CDU0(CONFIG_CDU0_CLKO7, REG_CDU0_CFG7, 7);
+ CONFIGURE_CDU0(CONFIG_CDU0_CLKO8, REG_CDU0_CFG8, 8);
+ CONFIGURE_CDU0(CONFIG_CDU0_CLKO9, REG_CDU0_CFG9, 9);
+#ifdef CONFIG_CDU0_CLKO10
+ CONFIGURE_CDU0(CONFIG_CDU0_CLKO10, REG_CDU0_CFG10, 10);
+#endif
+#ifdef CONFIG_CDU0_CLKO12
+ CONFIGURE_CDU0(CONFIG_CDU0_CLKO12, REG_CDU0_CFG12, 12);
+#endif
+#ifdef CONFIG_CDU0_CLKO13
+ CONFIGURE_CDU0(CONFIG_CDU0_CLKO13, REG_CDU0_CFG13, 13);
+#endif
+#ifdef CONFIG_CDU0_CLKO14
+ CONFIGURE_CDU0(CONFIG_CDU0_CLKO14, REG_CDU0_CFG14, 14);
+#endif
+}
+
+void clks_init(void)
+{
+ adi_dmc_reset_lanes(true);
+
+ cdu_init();
+ cgu_init();
+
+ adi_config_third_pll();
+
+ adi_dmc_reset_lanes(false);
+}
diff --git a/arch/arm/mach-sc5xx/init/clkinit.h b/arch/arm/mach-sc5xx/init/clkinit.h
new file mode 100644
index 0000000..b05f432
--- /dev/null
+++ b/arch/arm/mach-sc5xx/init/clkinit.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ * Contact: Greg Malysa <greg.malysa@timesys.com>
+ */
+
+#ifndef CLKINIT_H_
+#define CLKINIT_H_
+
+void clks_init(void);
+
+void dmcdelay(uint32_t delay);
+
+#endif
diff --git a/arch/arm/mach-sc5xx/init/dmcinit.c b/arch/arm/mach-sc5xx/init/dmcinit.c
new file mode 100644
index 0000000..e375b5c
--- /dev/null
+++ b/arch/arm/mach-sc5xx/init/dmcinit.c
@@ -0,0 +1,954 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ * Contact: Greg Malysa <greg.malysa@timesys.com>
+ */
+
+#include <asm/io.h>
+#include <asm/arch-adi/sc5xx/sc5xx.h>
+#include <linux/types.h>
+#include "clkinit.h"
+#include "dmcinit.h"
+
+#define REG_DMC0_BASE 0x31070000
+#define REG_DMC1_BASE 0x31073000
+
+#define REG_DMC_CTL 0x0004 // Control Register
+#define REG_DMC_STAT 0x0008 // Status Register
+#define REG_DMC_CFG 0x0040 // Configuration Register
+#define REG_DMC_TR0 0x0044 // Timing 0 Register
+#define REG_DMC_TR1 0x0048 // Timing 1 Register
+#define REG_DMC_TR2 0x004C // Timing 2 Register
+#define REG_DMC_MR 0x0060 // Shadow MR Register (DDR3)
+#define REG_DMC_EMR1 0x0064 // Shadow EMR1 Register
+#define REG_DMC_EMR2 0x0068 // Shadow EMR2 Register
+#define REG_DMC_EMR3 0x006C
+#define REG_DMC_DLLCTL 0x0080 // DLL Control Register
+#define REG_DMC_DT_CALIB_ADDR 0x0090 // Data Calibration Address Register
+#define REG_DMC_CPHY_CTL 0x01C0 // Controller to PHY Interface Register
+
+/* SC57x && SC58x DMC REGs */
+#define REG_DMC_PHY_CTL0 0x1000 // PHY Control 0 Register
+#define REG_DMC_PHY_CTL1 0x1004 // PHY Control 1 Register
+#define REG_DMC_PHY_CTL2 0x1008 // PHY Control 2 Register
+#define REG_DMC_PHY_CTL3 0x100c // PHY Control 3 Register
+#define REG_DMC_PHY_CTL4 0x1010 // PHY Control 4 Register
+#define REG_DMC_CAL_PADCTL0 0x1034 // CALIBRATION PAD CTL 0 Register
+#define REG_DMC_CAL_PADCTL2 0x103C // CALIBRATION PAD CTL2 Register
+/* END */
+
+/* SC59x DMC REGs */
+#define REG_DMC_DDR_LANE0_CTL0 0x1000 // Data Lane 0 Control Register 0
+#define REG_DMC_DDR_LANE0_CTL1 0x1004 // Data Lane 0 Control Register 1
+#define REG_DMC_DDR_LANE1_CTL0 0x100C // Data Lane 1 Control Register 0
+#define REG_DMC_DDR_LANE1_CTL1 0x1010 // Data Lane 1 Control Register 1
+#define REG_DMC_DDR_ROOT_CTL 0x1018 // DDR ROOT Module Control Register
+#define REG_DMC_DDR_ZQ_CTL0 0x1034 // DDR Calibration Control Register 0
+#define REG_DMC_DDR_ZQ_CTL1 0x1038 // DDR Calibration Control Register 1
+#define REG_DMC_DDR_ZQ_CTL2 0x103C // DDR Calibration Control Register 2
+#define REG_DMC_DDR_CA_CTL 0x1068 // DDR CA Lane Control Register
+/* END */
+
+#define REG_DMC_DDR_SCRATCH_2 0x1074
+#define REG_DMC_DDR_SCRATCH_3 0x1078
+#define REG_DMC_DDR_SCRATCH_6 0x1084
+#define REG_DMC_DDR_SCRATCH_7 0x1088
+
+#define REG_DMC_DDR_SCRATCH_STAT0 0x107C
+#define REG_DMC_DDR_SCRATCH_STAT1 0x1080
+
+#define DMC0_DATA_CALIB_ADD 0x80000000
+#define DMC1_DATA_CALIB_ADD 0xC0000000
+
+#define BITM_DMC_CFG_EXTBANK 0x0000F000 /* External Banks */
+#define ENUM_DMC_CFG_EXTBANK1 0x00000000 /* EXTBANK: 1 External Bank */
+#define BITM_DMC_CFG_SDRSIZE 0x00000F00 /* SDRAM Size */
+#define ENUM_DMC_CFG_SDRSIZE64 0x00000000 /* SDRSIZE: 64M Bit SDRAM (LPDDR Only) */
+#define ENUM_DMC_CFG_SDRSIZE128 0x00000100 /* SDRSIZE: 128M Bit SDRAM (LPDDR Only) */
+#define ENUM_DMC_CFG_SDRSIZE256 0x00000200 /* SDRSIZE: 256M Bit SDRAM */
+#define ENUM_DMC_CFG_SDRSIZE512 0x00000300 /* SDRSIZE: 512M Bit SDRAM */
+#define ENUM_DMC_CFG_SDRSIZE1G 0x00000400 /* SDRSIZE: 1G Bit SDRAM */
+#define ENUM_DMC_CFG_SDRSIZE2G 0x00000500 /* SDRSIZE: 2G Bit SDRAM */
+#define ENUM_DMC_CFG_SDRSIZE4G 0x00000600 /* SDRSIZE: 4G Bit SDRAM */
+#define ENUM_DMC_CFG_SDRSIZE8G 0x00000700 /* SDRSIZE: 8G Bit SDRAM */
+#define BITM_DMC_CFG_SDRWID 0x000000F0 /* SDRAM Width */
+#define ENUM_DMC_CFG_SDRWID16 0x00000020 /* SDRWID: 16-Bit Wide SDRAM */
+#define BITM_DMC_CFG_IFWID 0x0000000F /* Interface Width */
+#define ENUM_DMC_CFG_IFWID16 0x00000002 /* IFWID: 16-Bit Wide Interface */
+
+#define BITM_DMC_CTL_DDR3EN 0x00000001
+#define BITM_DMC_CTL_INIT 0x00000004
+#define BITP_DMC_STAT_INITDONE 2 /* Initialization Done */
+#define BITM_DMC_STAT_INITDONE 0x00000004
+
+#define BITP_DMC_CTL_AL_EN 27
+#define BITP_DMC_CTL_ZQCL 25 /* ZQ Calibration Long */
+#define BITP_DMC_CTL_ZQCS 24 /* ZQ Calibration Short */
+#define BITP_DMC_CTL_DLLCAL 13 /* DLL Calibration Start */
+#define BITP_DMC_CTL_PPREF 12 /* Postpone Refresh */
+#define BITP_DMC_CTL_RDTOWR 9 /* Read-to-Write Cycle */
+#define BITP_DMC_CTL_ADDRMODE 8 /* Addressing (Page/Bank) Mode */
+#define BITP_DMC_CTL_RESET 7 /* Reset SDRAM */
+#define BITP_DMC_CTL_PREC 6 /* Precharge */
+#define BITP_DMC_CTL_DPDREQ 5 /* Deep Power Down Request */
+#define BITP_DMC_CTL_PDREQ 4 /* Power Down Request */
+#define BITP_DMC_CTL_SRREQ 3 /* Self Refresh Request */
+#define BITP_DMC_CTL_INIT 2 /* Initialize DRAM Start */
+#define BITP_DMC_CTL_LPDDR 1 /* Low Power DDR Mode */
+#define BITP_DMC_CTL_DDR3EN 0 /* DDR3 Mode */
+
+#ifdef CONFIG_TARGET_SC584_EZKIT
+ #define DMC_PADCTL2_VALUE 0x0078283C
+#elif CONFIG_TARGET_SC573_EZKIT
+ #define DMC_PADCTL2_VALUE 0x00782828
+#elif CONFIG_TARGET_SC589_MINI || CONFIG_TARGET_SC589_EZKIT
+ #define DMC_PADCTL2_VALUE 0x00783C3C
+#elif defined(CONFIG_SC57X) || defined(CONFIG_SC58X)
+ #error "PADCTL2 not specified for custom board!"
+#else
+ //Newer DMC. Legacy calibration obsolete
+ #define DMC_PADCTL2_VALUE 0x0
+#endif
+
+#define DMC_CPHYCTL_VALUE 0x0000001A
+
+#define BITP_DMC_MR1_QOFF 12 /* Output Buffer Enable */
+#define BITP_DMC_MR1_TDQS 11 /* Termination Data Strobe */
+#define BITP_DMC_MR1_RTT2 9 /* Rtt_nom */
+#define BITP_DMC_MR1_WL 7 /* Write Leveling Enable. */
+#define BITP_DMC_MR1_RTT1 6 /* Rtt_nom */
+#define BITP_DMC_MR1_DIC1 5 /* Output Driver Impedance Control */
+#define BITP_DMC_MR1_AL 3 /* Additive Latency */
+#define BITP_DMC_MR1_RTT0 2 /* Rtt_nom */
+#define BITP_DMC_MR1_DIC0 1 /* Output Driver Impedance control */
+#define BITP_DMC_MR1_DLLEN 0 /* DLL Enable */
+
+#define BITP_DMC_MR2_CWL 3 /* CAS write Latency */
+
+#define BITP_DMC_TR0_TMRD 28 /* Timing Mode Register Delay */
+#define BITP_DMC_TR0_TRC 20 /* Timing Row Cycle */
+#define BITP_DMC_TR0_TRAS 12 /* Timing Row Active Time */
+#define BITP_DMC_TR0_TRP 8 /* Timing RAS Precharge. */
+#define BITP_DMC_TR0_TWTR 4 /* Timing Write to Read */
+#define BITP_DMC_TR0_TRCD 0 /* Timing RAS to CAS Delay */
+
+#define BITP_DMC_TR1_TRRD 28 /* Timing Read-Read Delay */
+#define BITP_DMC_TR1_TRFC 16 /* Timing Refresh-to-Command */
+#define BITP_DMC_TR1_TREF 0 /* Timing Refresh Interval */
+
+#define BITP_DMC_TR2_TCKE 20 /* Timing Clock Enable */
+#define BITP_DMC_TR2_TXP 16 /* Timing Exit Powerdown */
+#define BITP_DMC_TR2_TWR 12 /* Timing Write Recovery */
+#define BITP_DMC_TR2_TRTP 8 /* Timing Read-to-Precharge */
+#define BITP_DMC_TR2_TFAW 0 /* Timing Four-Activated-Window */
+
+#define BITP_DMC_MR_PD 12 /* Active Powerdown Mode */
+#define BITP_DMC_MR_WRRECOV 9 /* Write Recovery */
+#define BITP_DMC_MR_DLLRST 8 /* DLL Reset */
+#define BITP_DMC_MR_CL 4 /* CAS Latency */
+#define BITP_DMC_MR_CL0 2 /* CAS Latency */
+#define BITP_DMC_MR_BLEN 0 /* Burst Length */
+
+#define BITP_DMC_DLLCTL_DATACYC 8 /* Data Cycles */
+#define BITP_DMC_DLLCTL_DLLCALRDCNT 0 /* DLL Calibration RD Count */
+
+#define BITM_DMC_DLLCTL_DATACYC 0x00000F00 /* Data Cycles */
+#define BITM_DMC_DLLCTL_DLLCALRDCNT 0x000000FF /* DLL Calib RD Count */
+
+#define BITP_DMC_STAT_PHYRDPHASE 20 /* PHY Read Phase */
+
+#define BITM_DMC_DDR_LANE0_CTL0_CB_RSTDAT 0x08000000 /* Rst Data Pads */
+#define BITM_DMC_DDR_LANE1_CTL0_CB_RSTDAT 0x08000000 /* Rst Data Pads */
+#define BITM_DMC_DDR_LANE0_CTL1_COMP_DCYCLE 0x00000002 /* Compute Dcycle */
+#define BITM_DMC_DDR_LANE1_CTL1_COMP_DCYCLE 0x00000002 /* Compute Dcycle */
+#define BITM_DMC_DDR_LANE1_CTL0_CB_RSTDLL 0x00000100 /* Rst Lane DLL */
+#define BITM_DMC_DDR_LANE0_CTL0_CB_RSTDLL 0x00000100 /* Rst Lane DLL */
+#define BITP_DMC_DDR_ROOT_CTL_PIPE_OFSTDCYCLE 10 /* Pipeline offset for PHYC_DATACYCLE */
+#define BITM_DMC_DDR_ROOT_CTL_SW_REFRESH 0x00002000 /* Refresh Lane DLL Code */
+#define BITM_DMC_DDR_CA_CTL_SW_REFRESH 0x00004000 /* Refresh Lane DLL Code */
+
+#define BITP_DMC_CTL_RL_DQS 26 /* RL_DQS */
+#define BITM_DMC_CTL_RL_DQS 0x04000000 /* RL_DQS */
+#define BITP_DMC_EMR3_MPR 2 /* Multi Purpose Read Enable (Read Leveling)*/
+#define BITM_DMC_EMR3_MPR 0x00000004 /* Multi Purpose Read Enable (Read Leveling)*/
+#define BITM_DMC_MR1_WL 0x00000080 /* Write Leveling Enable.*/
+#define BITM_DMC_STAT_PHYRDPHASE 0x00F00000 /* PHY Read Phase */
+
+#define BITP_DMC_DDR_LANE0_CTL1_BYPCODE 10
+#define BITM_DMC_DDR_LANE0_CTL1_BYPCODE 0x00007C00
+#define BITP_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN 15
+#define BITM_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN 0x00008000
+
+#define DMC_ZQCTL0_VALUE 0x00785A64
+#define DMC_ZQCTL1_VALUE 0
+#define DMC_ZQCTL2_VALUE 0x70000000
+
+#define DMC_TRIG_CALIB 0
+#define DMC_OFSTDCYCLE 2
+
+#define BITP_DMC_CAL_PADCTL0_RTTCALEN 31 /* RTT Calibration Enable */
+#define BITP_DMC_CAL_PADCTL0_PDCALEN 30 /* PULLDOWN Calib Enable */
+#define BITP_DMC_CAL_PADCTL0_PUCALEN 29 /* PULLUP Calib Enable */
+#define BITP_DMC_CAL_PADCTL0_CALSTRT 28 /* Start New Calib ( Hardware Cleared) */
+#define BITM_DMC_CAL_PADCTL0_RTTCALEN 0x80000000 /* RTT Calibration Enable */
+#define BITM_DMC_CAL_PADCTL0_PDCALEN 0x40000000 /* PULLDOWN Calib Enable */
+#define BITM_DMC_CAL_PADCTL0_PUCALEN 0x20000000 /* PULLUP Calib Enable */
+#define BITM_DMC_CAL_PADCTL0_CALSTRT 0x10000000 /* Start New Calib ( Hardware Cleared) */
+#define ENUM_DMC_PHY_CTL4_DDR3 0x00000000 /* DDRMODE: DDR3 Mode */
+#define ENUM_DMC_PHY_CTL4_DDR2 0x00000001 /* DDRMODE: DDR2 Mode */
+#define ENUM_DMC_PHY_CTL4_LPDDR 0x00000003 /* DDRMODE: LPDDR Mode */
+
+#define BITP_DMC_DDR_ZQ_CTL0_IMPRTT 16 /* Data/DQS ODT */
+#define BITP_DMC_DDR_ZQ_CTL0_IMPWRDQ 8 /* Data/DQS/DM/CLK Drive Strength */
+#define BITP_DMC_DDR_ZQ_CTL0_IMPWRADD 0 /* Address/Command Drive Strength */
+#define BITM_DMC_DDR_ZQ_CTL0_IMPRTT 0x00FF0000 /* Data/DQS ODT */
+#define BITM_DMC_DDR_ZQ_CTL0_IMPWRDQ 0x0000FF00 /* Data/DQS/DM/CLK Drive Strength */
+#define BITM_DMC_DDR_ZQ_CTL0_IMPWRADD 0x000000FF /* Address/Command Drive Strength */
+
+#define BITM_DMC_DDR_ROOT_CTL_TRIG_RD_XFER_ALL 0x00200000 /* All Lane Read Status */
+
+#if defined(CONFIG_ADI_USE_DDR2)
+ #define DMC_MR0_VALUE \
+ ((DMC_BL / 4 + 1) << BITP_DMC_MR_BLEN) | \
+ (DMC_CL << BITP_DMC_MR_CL) | \
+ (DMC_WRRECOV << BITP_DMC_MR_WRRECOV)
+
+ #define DMC_MR1_VALUE \
+ (DMC_MR1_AL << BITP_DMC_MR1_AL | 0x04) \
+
+ #define DMC_MR2_VALUE 0
+ #define DMC_MR3_VALUE 0
+
+ #define DMC_CTL_VALUE \
+ (DMC_RDTOWR << BITP_DMC_CTL_RDTOWR) | \
+ (1 << BITP_DMC_CTL_DLLCAL) | \
+ (BITM_DMC_CTL_INIT)
+#else
+ #define DMC_MR0_VALUE \
+ (0 << BITP_DMC_MR_BLEN) | \
+ (DMC_CL0 << BITP_DMC_MR_CL0) | \
+ (DMC_CL123 << BITP_DMC_MR_CL) | \
+ (DMC_WRRECOV << BITP_DMC_MR_WRRECOV) | \
+ (1 << BITP_DMC_MR_DLLRST)
+
+ #define DMC_MR1_VALUE \
+ (DMC_MR1_DLLEN << BITP_DMC_MR1_DLLEN) | \
+ (DMC_MR1_DIC0 << BITP_DMC_MR1_DIC0) | \
+ (DMC_MR1_RTT0 << BITP_DMC_MR1_RTT0) | \
+ (DMC_MR1_AL << BITP_DMC_MR1_AL) | \
+ (DMC_MR1_DIC1 << BITP_DMC_MR1_DIC1) | \
+ (DMC_MR1_RTT1 << BITP_DMC_MR1_RTT1) | \
+ (DMC_MR1_RTT2 << BITP_DMC_MR1_RTT2) | \
+ (DMC_MR1_WL << BITP_DMC_MR1_WL) | \
+ (DMC_MR1_TDQS << BITP_DMC_MR1_TDQS) | \
+ (DMC_MR1_QOFF << BITP_DMC_MR1_QOFF)
+
+ #define DMC_MR2_VALUE \
+ ((DMC_WL) << BITP_DMC_MR2_CWL)
+
+ #define DMC_MR3_VALUE \
+ ((DMC_WL) << BITP_DMC_MR2_CWL)
+
+ #define DMC_CTL_VALUE \
+ (DMC_RDTOWR << BITP_DMC_CTL_RDTOWR) | \
+ (BITM_DMC_CTL_INIT) | \
+ (BITM_DMC_CTL_DDR3EN) | \
+ (DMC_CTL_AL_EN << BITP_DMC_CTL_AL_EN)
+#endif
+
+#define DMC_DLLCTL_VALUE \
+ (DMC_DATACYC << BITP_DMC_DLLCTL_DATACYC) | \
+ (DMC_DLLCALRDCNT << BITP_DMC_DLLCTL_DLLCALRDCNT)
+
+#define DMC_CFG_VALUE \
+ ENUM_DMC_CFG_IFWID16 | \
+ ENUM_DMC_CFG_SDRWID16 | \
+ SDR_CHIP_SIZE | \
+ ENUM_DMC_CFG_EXTBANK1
+
+#define DMC_TR0_VALUE \
+ (DMC_TRCD << BITP_DMC_TR0_TRCD) | \
+ (DMC_TWTR << BITP_DMC_TR0_TWTR) | \
+ (DMC_TRP << BITP_DMC_TR0_TRP) | \
+ (DMC_TRAS << BITP_DMC_TR0_TRAS) | \
+ (DMC_TRC << BITP_DMC_TR0_TRC) | \
+ (DMC_TMRD << BITP_DMC_TR0_TMRD)
+
+#define DMC_TR1_VALUE \
+ (DMC_TREF << BITP_DMC_TR1_TREF) | \
+ (DMC_TRFC << BITP_DMC_TR1_TRFC) | \
+ (DMC_TRRD << BITP_DMC_TR1_TRRD)
+
+#define DMC_TR2_VALUE \
+ (DMC_TFAW << BITP_DMC_TR2_TFAW) | \
+ (DMC_TRTP << BITP_DMC_TR2_TRTP) | \
+ (DMC_TWR << BITP_DMC_TR2_TWR) | \
+ (DMC_TXP << BITP_DMC_TR2_TXP) | \
+ (DMC_TCKE << BITP_DMC_TR2_TCKE)
+
+enum DDR_MODE {
+ DDR3_MODE,
+ DDR2_MODE,
+ LPDDR_MODE,
+};
+
+enum CALIBRATION_MODE {
+ CALIBRATION_LEGACY,
+ CALIBRATION_METHOD1,
+ CALIBRATION_METHOD2,
+};
+
+static struct dmc_param {
+ phys_addr_t reg;
+ u32 ddr_mode;
+ u32 padctl2_value;
+ u32 dmc_cphyctl_value;
+ u32 dmc_cfg_value;
+ u32 dmc_dllctl_value;
+ u32 dmc_ctl_value;
+ u32 dmc_tr0_value;
+ u32 dmc_tr1_value;
+ u32 dmc_tr2_value;
+ u32 dmc_mr0_value;
+ u32 dmc_mr1_value;
+ u32 dmc_mr2_value;
+ u32 dmc_mr3_value;
+ u32 dmc_zqctl0_value;
+ u32 dmc_zqctl1_value;
+ u32 dmc_zqctl2_value;
+ u32 dmc_data_calib_add_value;
+ bool phy_init_required;
+ bool anomaly_20000037_applicable;
+ enum CALIBRATION_MODE calib_mode;
+} dmc;
+
+#ifdef CONFIG_SC59X_64
+#define DQS_DEFAULT_DELAY 3ul
+
+#define DELAYTRIM 1
+#define LANE0_DQS_DELAY 1
+#define LANE1_DQS_DELAY 1
+
+#define CLKDIR 0ul
+
+#define DQSTRIM 0
+#define DQSCODE 0ul
+
+#define CLKTRIM 0
+#define CLKCODE 0ul
+#endif
+
+static inline void calibration_legacy(void)
+{
+ u32 temp;
+
+ /* 1. Set DDR mode to DDR3/DDR2/LPDDR in DMCx_PHY_CTL4 register */
+ if (dmc.ddr_mode == DDR3_MODE)
+ writel(ENUM_DMC_PHY_CTL4_DDR3, dmc.reg + REG_DMC_PHY_CTL4);
+ else if (dmc.ddr_mode == DDR2_MODE)
+ writel(ENUM_DMC_PHY_CTL4_DDR2, dmc.reg + REG_DMC_PHY_CTL4);
+ else if (dmc.ddr_mode == LPDDR_MODE)
+ writel(ENUM_DMC_PHY_CTL4_LPDDR, dmc.reg + REG_DMC_PHY_CTL4);
+
+ /*
+ * 2. Make sure that the bits 6, 7, 25, and 27 of the DMC_PHY_
+ * CTL3 register are set
+ */
+ writel(0x0A0000C0, dmc.reg + REG_DMC_PHY_CTL3);
+
+ /*
+ * 3. For DDR2/DDR3 mode, make sure that the bits 0, 1, 2, 3 of
+ * the DMC_PHY_CTL0 register and the bits 26, 27, 28, 29, 30, 31
+ * of the DMC_PHY_CTL2 are set.
+ */
+ if (dmc.ddr_mode == DDR3_MODE ||
+ dmc.ddr_mode == DDR2_MODE) {
+ writel(0XFC000000, dmc.reg + REG_DMC_PHY_CTL2);
+ writel(0x0000000f, dmc.reg + REG_DMC_PHY_CTL0);
+ }
+
+ writel(0x00000000, dmc.reg + REG_DMC_PHY_CTL1);
+
+ /* 4. For DDR3 mode, set bit 1 and configure bits [5:2] of the
+ * DMC_CPHY_CTL register with WL=CWL+AL in DCLK cycles.
+ */
+ if (dmc.ddr_mode == DDR3_MODE)
+ writel(dmc.dmc_cphyctl_value, dmc.reg + REG_DMC_CPHY_CTL);
+ /* 5. Perform On Die Termination(ODT) & Driver Impedance Calibration */
+ if (dmc.ddr_mode == LPDDR_MODE) {
+ /* Bypass processor ODT */
+ writel(0x80000, dmc.reg + REG_DMC_PHY_CTL1);
+ } else {
+ /* Set bits RTTCALEN, PDCALEN, PUCALEN of register */
+ temp = BITM_DMC_CAL_PADCTL0_RTTCALEN |
+ BITM_DMC_CAL_PADCTL0_PDCALEN |
+ BITM_DMC_CAL_PADCTL0_PUCALEN;
+ writel(temp, dmc.reg + REG_DMC_CAL_PADCTL0);
+ /* Configure ODT and drive impedance values in the
+ * DMCx_CAL_PADCTL2 register
+ */
+ writel(dmc.padctl2_value, dmc.reg + REG_DMC_CAL_PADCTL2);
+ /* start calibration */
+ temp |= BITM_DMC_CAL_PADCTL0_CALSTRT;
+ writel(temp, dmc.reg + REG_DMC_CAL_PADCTL0);
+ /* Wait for PAD calibration to complete - 300 DCLK cycle.
+ * Worst case: CCLK=450 MHz, DCLK=125 MHz
+ */
+ dmcdelay(300);
+ }
+}
+
+static inline void calibration_method1(void)
+{
+#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64)
+ writel(dmc.dmc_zqctl0_value, dmc.reg + REG_DMC_DDR_ZQ_CTL0);
+ writel(dmc.dmc_zqctl1_value, dmc.reg + REG_DMC_DDR_ZQ_CTL1);
+ writel(dmc.dmc_zqctl2_value, dmc.reg + REG_DMC_DDR_ZQ_CTL2);
+
+ /* Generate the trigger */
+ writel(0x0ul, dmc.reg + REG_DMC_DDR_CA_CTL);
+ writel(0x0ul, dmc.reg + REG_DMC_DDR_ROOT_CTL);
+ writel(0x00010000ul, dmc.reg + REG_DMC_DDR_ROOT_CTL);
+ dmcdelay(8000u);
+
+ /* The [31:26] bits may change if pad ring changes */
+ writel(0x0C000001ul | DMC_TRIG_CALIB, dmc.reg + REG_DMC_DDR_CA_CTL);
+ dmcdelay(8000u);
+ writel(0x0ul, dmc.reg + REG_DMC_DDR_CA_CTL);
+ writel(0x0ul, dmc.reg + REG_DMC_DDR_ROOT_CTL);
+#endif
+}
+
+static inline void calibration_method2(void)
+{
+#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64)
+ u32 stat_value = 0x0u;
+ u32 drv_pu, drv_pd, odt_pu, odt_pd;
+ u32 ro_dt, clk_dqs_drv_impedance;
+ u32 temp;
+
+ /* Reset trigger */
+ writel(0x0ul, dmc.reg + REG_DMC_DDR_CA_CTL);
+ writel(0x0ul, dmc.reg + REG_DMC_DDR_ROOT_CTL);
+ writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_3);
+ writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_2);
+
+ /* Writing internal registers in calib pad to zero. Calib mode set
+ * to 1 [26], trig M1 S1 write [16], this enables usage of scratch
+ * registers instead of ZQCTL registers
+ */
+ writel(0x04010000ul, dmc.reg + REG_DMC_DDR_ROOT_CTL);
+ dmcdelay(2500u);
+
+ /* TRIGGER FOR M2-S2 WRITE -> slave id 31:26 trig m2,s2 write
+ * bit 1->1 slave1 address is 4
+ */
+ writel(0x10000002ul, dmc.reg + REG_DMC_DDR_CA_CTL);
+ dmcdelay(2500u);
+
+ /* reset Trigger */
+ writel(0x0u, dmc.reg + REG_DMC_DDR_CA_CTL);
+ writel(0x0u, dmc.reg + REG_DMC_DDR_ROOT_CTL);
+
+ /* write to slave 1, make the power down bit high */
+ writel(0x1ul << 12, dmc.reg + REG_DMC_DDR_SCRATCH_3);
+ writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_2);
+ dmcdelay(2500u);
+
+ /* Calib mode set to 1 [26], trig M1 S1 write [16] */
+ writel(0x04010000ul, dmc.reg + REG_DMC_DDR_ROOT_CTL);
+ dmcdelay(2500u);
+
+ writel(0x10000002ul, dmc.reg + REG_DMC_DDR_CA_CTL);
+ dmcdelay(2500u);
+
+ writel(0x0ul, dmc.reg + REG_DMC_DDR_CA_CTL);
+ writel(0x0ul, dmc.reg + REG_DMC_DDR_ROOT_CTL);
+ writel(0x0, dmc.reg + REG_DMC_DDR_SCRATCH_3);
+
+ /* for slave 0 */
+ writel(dmc.dmc_zqctl0_value, dmc.reg + REG_DMC_DDR_SCRATCH_2);
+
+ /* Calib mode set to 1 [26], trig M1 S1 write [16] */
+ writel(0x04010000ul, dmc.reg + REG_DMC_DDR_ROOT_CTL);
+ dmcdelay(2500u);
+
+ writel(0x0C000002ul, dmc.reg + REG_DMC_DDR_CA_CTL);
+ dmcdelay(2500u);
+
+ writel(0x0ul, dmc.reg + REG_DMC_DDR_CA_CTL);
+ writel(0x0ul, dmc.reg + REG_DMC_DDR_ROOT_CTL);
+
+ /* writing to slave 1
+ * calstrt is 0, but other programming is done
+ *
+ * make power down LOW again, to kickstart BIAS circuit
+ */
+ writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_3);
+ writel(0x30000000ul, dmc.reg + REG_DMC_DDR_SCRATCH_2);
+
+ /* write to ca_ctl lane, calib mode set to 1 [26],
+ * trig M1 S1 write [16]
+ */
+ writel(0x04010000ul, dmc.reg + REG_DMC_DDR_ROOT_CTL);
+ dmcdelay(2500u);
+
+ /* copies data to lane controller slave
+ * TRIGGER FOR M2-S2 WRITE -> slave id 31:26
+ * trig m2,s2 write bit 1->1
+ * slave1 address is 4
+ */
+ writel(0x10000002ul, dmc.reg + REG_DMC_DDR_CA_CTL);
+ dmcdelay(2500u);
+
+ /* reset Trigger */
+ writel(0x0ul, dmc.reg + REG_DMC_DDR_CA_CTL);
+ writel(0x0ul, dmc.reg + REG_DMC_DDR_ROOT_CTL);
+ writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_3);
+ writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_2);
+ writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_3);
+ writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_2);
+ writel(0x04010000ul, dmc.reg + REG_DMC_DDR_ROOT_CTL);
+ dmcdelay(2500u);
+ writel(0x10000002ul, dmc.reg + REG_DMC_DDR_CA_CTL);
+ dmcdelay(2500u);
+ writel(0x0ul, dmc.reg + REG_DMC_DDR_CA_CTL);
+ writel(0x0ul, dmc.reg + REG_DMC_DDR_ROOT_CTL);
+ writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_3);
+ writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_2);
+ writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_3);
+ writel(0x50000000ul, dmc.reg + REG_DMC_DDR_SCRATCH_2);
+ writel(0x04010000ul, dmc.reg + REG_DMC_DDR_ROOT_CTL);
+ dmcdelay(2500u);
+ writel(0x10000002ul, dmc.reg + REG_DMC_DDR_CA_CTL);
+ dmcdelay(2500u);
+ writel(0u, dmc.reg + REG_DMC_DDR_CA_CTL);
+ writel(0u, dmc.reg + REG_DMC_DDR_ROOT_CTL);
+ writel(0x0C000004u, dmc.reg + REG_DMC_DDR_CA_CTL);
+ dmcdelay(2500u);
+ writel(BITM_DMC_DDR_ROOT_CTL_TRIG_RD_XFER_ALL,
+ dmc.reg + REG_DMC_DDR_ROOT_CTL);
+ dmcdelay(2500u);
+ writel(0u, dmc.reg + REG_DMC_DDR_CA_CTL);
+ writel(0u, dmc.reg + REG_DMC_DDR_ROOT_CTL);
+ // calculate ODT PU and PD values
+ stat_value = ((readl(dmc.reg + REG_DMC_DDR_SCRATCH_7) & 0x0000FFFFu) <<
+ 16);
+ stat_value |= ((readl(dmc.reg + REG_DMC_DDR_SCRATCH_6) & 0xFFFF0000u) >>
+ 16);
+ clk_dqs_drv_impedance = ((dmc.dmc_zqctl0_value) &
+ BITM_DMC_DDR_ZQ_CTL0_IMPWRDQ) >> BITP_DMC_DDR_ZQ_CTL0_IMPWRDQ;
+ ro_dt = ((dmc.dmc_zqctl0_value) & BITM_DMC_DDR_ZQ_CTL0_IMPRTT) >>
+ BITP_DMC_DDR_ZQ_CTL0_IMPRTT;
+ drv_pu = stat_value & 0x0000003Fu;
+ drv_pd = (stat_value >> 12) & 0x0000003Fu;
+ odt_pu = (drv_pu * clk_dqs_drv_impedance) / ro_dt;
+ odt_pd = (drv_pd * clk_dqs_drv_impedance) / ro_dt;
+ temp = ((1uL << 24) |
+ ((drv_pd & 0x0000003Fu)) |
+ ((odt_pd & 0x0000003Fu) << 6) |
+ ((drv_pu & 0x0000003Fu) << 12) |
+ ((odt_pu & 0x0000003Fu) << 18));
+ temp |= readl(dmc.reg + REG_DMC_DDR_SCRATCH_2);
+ writel(temp, dmc.reg + REG_DMC_DDR_SCRATCH_2);
+ writel(0x0C010000u, dmc.reg + REG_DMC_DDR_ROOT_CTL);
+ dmcdelay(2500u);
+ writel(0x08000002u, dmc.reg + REG_DMC_DDR_CA_CTL);
+ dmcdelay(2500u);
+ writel(0u, dmc.reg + REG_DMC_DDR_CA_CTL);
+ writel(0u, dmc.reg + REG_DMC_DDR_ROOT_CTL);
+ writel(0x04010000u, dmc.reg + REG_DMC_DDR_ROOT_CTL);
+ dmcdelay(2500u);
+ writel(0x80000002u, dmc.reg + REG_DMC_DDR_CA_CTL);
+ dmcdelay(2500u);
+ writel(0u, dmc.reg + REG_DMC_DDR_CA_CTL);
+ writel(0u, dmc.reg + REG_DMC_DDR_ROOT_CTL);
+#endif
+}
+
+static inline void adi_dmc_lane_reset(bool reset, uint32_t dmc_no)
+{
+#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64)
+ u32 temp;
+ phys_addr_t base = (dmc_no == 0) ? REG_DMC0_BASE : REG_DMC1_BASE;
+ phys_addr_t ln0 = base + REG_DMC_DDR_LANE0_CTL0;
+ phys_addr_t ln1 = base + REG_DMC_DDR_LANE1_CTL0;
+
+ if (reset) {
+ temp = readl(ln0);
+ temp |= BITM_DMC_DDR_LANE0_CTL0_CB_RSTDLL;
+ writel(temp, ln0);
+
+ temp = readl(ln1);
+ temp |= BITM_DMC_DDR_LANE1_CTL0_CB_RSTDLL;
+ writel(temp, ln1);
+ } else {
+ temp = readl(ln0);
+ temp &= ~BITM_DMC_DDR_LANE0_CTL0_CB_RSTDLL;
+ writel(temp, ln0);
+
+ temp = readl(ln1);
+ temp &= ~BITM_DMC_DDR_LANE1_CTL0_CB_RSTDLL;
+ writel(temp, ln1);
+ }
+ dmcdelay(9000u);
+#endif
+}
+
+void adi_dmc_reset_lanes(bool reset)
+{
+ if (!IS_ENABLED(CONFIG_ADI_USE_DDR2)) {
+ if (IS_ENABLED(CONFIG_SC59X) || IS_ENABLED(CONFIG_SC59X_64)) {
+ if (IS_ENABLED(CONFIG_ADI_USE_DMC0))
+ adi_dmc_lane_reset(reset, 0);
+ if (IS_ENABLED(CONFIG_ADI_USE_DMC1))
+ adi_dmc_lane_reset(reset, 1);
+ }
+ else {
+ u32 temp = reset ? 0x800 : 0x0;
+
+ if (IS_ENABLED(CONFIG_ADI_USE_DMC0))
+ writel(temp, REG_DMC0_BASE + REG_DMC_PHY_CTL0);
+ if (IS_ENABLED(CONFIG_ADI_USE_DMC1))
+ writel(temp, REG_DMC1_BASE + REG_DMC_PHY_CTL0);
+ }
+ }
+}
+
+static inline void dmc_controller_init(void)
+{
+#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64)
+ u32 phyphase, rd_cnt, t_EMR1, t_EMR3, t_CTL, data_cyc, temp;
+#endif
+
+ /* 1. Program the DMC controller registers: DMCx_CFG, DMCx_TR0,
+ * DMCx_TR1, DMCx_TR2, DMCx_MR(DDR2/LPDDR)/DMCx_MR0(DDR3),
+ * DMCx_EMR1(DDR2)/DMCx_MR1(DDR3),
+ * DMCx_EMR2(DDR2)/DMCx_EMR(LPDDR)/DMCx_MR2(DDR3)
+ */
+ writel(dmc.dmc_cfg_value, dmc.reg + REG_DMC_CFG);
+ writel(dmc.dmc_tr0_value, dmc.reg + REG_DMC_TR0);
+ writel(dmc.dmc_tr1_value, dmc.reg + REG_DMC_TR1);
+ writel(dmc.dmc_tr2_value, dmc.reg + REG_DMC_TR2);
+ writel(dmc.dmc_mr0_value, dmc.reg + REG_DMC_MR);
+ writel(dmc.dmc_mr1_value, dmc.reg + REG_DMC_EMR1);
+ writel(dmc.dmc_mr2_value, dmc.reg + REG_DMC_EMR2);
+
+#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64)
+ writel(dmc.dmc_mr3_value, dmc.reg + REG_DMC_EMR3);
+ writel(dmc.dmc_dllctl_value, dmc.reg + REG_DMC_DLLCTL);
+ dmcdelay(2000u);
+
+ temp = readl(dmc.reg + REG_DMC_DDR_CA_CTL);
+ temp |= BITM_DMC_DDR_CA_CTL_SW_REFRESH;
+ writel(temp, dmc.reg + REG_DMC_DDR_CA_CTL);
+ dmcdelay(5u);
+
+ temp = readl(dmc.reg + REG_DMC_DDR_ROOT_CTL);
+ temp |= BITM_DMC_DDR_ROOT_CTL_SW_REFRESH |
+ (DMC_OFSTDCYCLE << BITP_DMC_DDR_ROOT_CTL_PIPE_OFSTDCYCLE);
+ writel(temp, dmc.reg + REG_DMC_DDR_ROOT_CTL);
+#endif
+
+ /* 2. Make sure that the REG_DMC_DT_CALIB_ADDR register is programmed
+ * to an unused DMC location corresponding to a burst of 16 bytes
+ * (by default it is the starting address of the DMC address range).
+ */
+#ifndef CONFIG_SC59X
+ writel(dmc.dmc_data_calib_add_value, dmc.reg + REG_DMC_DT_CALIB_ADDR);
+#endif
+ /* 3. Program the DMCx_CTL register with INIT bit set to start
+ * the DMC initialization sequence
+ */
+ writel(dmc.dmc_ctl_value, dmc.reg + REG_DMC_CTL);
+ /* 4. Wait for the DMC initialization to complete by polling
+ * DMCx_STAT.INITDONE bit.
+ */
+
+#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64)
+ dmcdelay(722000u);
+
+ /* Add necessary delay depending on the configuration */
+ t_EMR1 = (dmc.dmc_mr1_value & BITM_DMC_MR1_WL) >> BITP_DMC_MR1_WL;
+
+ dmcdelay(600u);
+ if (t_EMR1 != 0u)
+ while ((readl(dmc.reg + REG_DMC_EMR1) & BITM_DMC_MR1_WL) != 0)
+ ;
+
+ t_EMR3 = (dmc.dmc_mr3_value & BITM_DMC_EMR3_MPR) >>
+ BITP_DMC_EMR3_MPR;
+ dmcdelay(2000u);
+ if (t_EMR3 != 0u)
+ while ((readl(dmc.reg + REG_DMC_EMR3) & BITM_DMC_EMR3_MPR) != 0)
+ ;
+
+ t_CTL = (dmc.dmc_ctl_value & BITM_DMC_CTL_RL_DQS) >> BITP_DMC_CTL_RL_DQS;
+ dmcdelay(600u);
+ if (t_CTL != 0u)
+ while ((readl(dmc.reg + REG_DMC_CTL) & BITM_DMC_CTL_RL_DQS) != 0)
+ ;
+#endif
+
+ /* check if DMC initialization finished*/
+ while ((readl(dmc.reg + REG_DMC_STAT) & BITM_DMC_STAT_INITDONE) == 0)
+ ;
+
+#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64)
+ /* toggle DCYCLE */
+ temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL1);
+ temp |= BITM_DMC_DDR_LANE0_CTL1_COMP_DCYCLE;
+ writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL1);
+
+ temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL1);
+ temp |= BITM_DMC_DDR_LANE1_CTL1_COMP_DCYCLE;
+ writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL1);
+
+ dmcdelay(10u);
+
+ temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL1);
+ temp &= (~BITM_DMC_DDR_LANE0_CTL1_COMP_DCYCLE);
+ writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL1);
+
+ temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL1);
+ temp &= (~BITM_DMC_DDR_LANE1_CTL1_COMP_DCYCLE);
+ writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL1);
+
+ /* toggle RSTDAT */
+ temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL0);
+ temp |= BITM_DMC_DDR_LANE0_CTL0_CB_RSTDAT;
+ writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL0);
+
+ temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL0);
+ temp &= (~BITM_DMC_DDR_LANE0_CTL0_CB_RSTDAT);
+ writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL0);
+
+ temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL0);
+ temp |= BITM_DMC_DDR_LANE1_CTL0_CB_RSTDAT;
+ writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL0);
+
+ temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL0);
+ temp &= (~BITM_DMC_DDR_LANE1_CTL0_CB_RSTDAT);
+ writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL0);
+
+ dmcdelay(2500u);
+
+ /* Program phyphase*/
+ phyphase = (readl(dmc.reg + REG_DMC_STAT) &
+ BITM_DMC_STAT_PHYRDPHASE) >> BITP_DMC_STAT_PHYRDPHASE;
+ data_cyc = (phyphase << BITP_DMC_DLLCTL_DATACYC) &
+ BITM_DMC_DLLCTL_DATACYC;
+ rd_cnt = dmc.dmc_dllctl_value;
+ rd_cnt <<= BITP_DMC_DLLCTL_DLLCALRDCNT;
+ rd_cnt &= BITM_DMC_DLLCTL_DLLCALRDCNT;
+ writel(rd_cnt | data_cyc, dmc.reg + REG_DMC_DLLCTL);
+ writel((dmc.dmc_ctl_value & (~BITM_DMC_CTL_INIT) &
+ (~BITM_DMC_CTL_RL_DQS)), dmc.reg + REG_DMC_CTL);
+
+#if DELAYTRIM
+ /* DQS delay trim*/
+ u32 stat_value, WL_code_LDQS, WL_code_UDQS;
+
+ /* For LDQS */
+ temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL1) | (0x000000D0);
+ writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL1);
+ dmcdelay(2500u);
+ writel(0x00400000, dmc.reg + REG_DMC_DDR_ROOT_CTL);
+ dmcdelay(2500u);
+ writel(0x0, dmc.reg + REG_DMC_DDR_ROOT_CTL);
+ stat_value = (readl(dmc.reg + REG_DMC_DDR_SCRATCH_STAT0) &
+ (0xFFFF0000)) >> 16;
+ WL_code_LDQS = (stat_value) & (0x0000001F);
+
+ temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL1);
+ temp &= ~(BITM_DMC_DDR_LANE0_CTL1_BYPCODE |
+ BITM_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN);
+ writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL1);
+
+ /* If write leveling is enabled */
+ if ((dmc.dmc_mr1_value & BITM_DMC_MR1_WL) >> BITP_DMC_MR1_WL) {
+ temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL1);
+ temp |= (((WL_code_LDQS + LANE0_DQS_DELAY) <<
+ BITP_DMC_DDR_LANE0_CTL1_BYPCODE) &
+ BITM_DMC_DDR_LANE0_CTL1_BYPCODE) |
+ BITM_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN;
+ writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL1);
+ } else {
+ temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL1);
+ temp |= (((DQS_DEFAULT_DELAY + LANE0_DQS_DELAY) <<
+ BITP_DMC_DDR_LANE0_CTL1_BYPCODE) &
+ BITM_DMC_DDR_LANE0_CTL1_BYPCODE) |
+ BITM_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN;
+ writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL1);
+ }
+ dmcdelay(2500u);
+
+ /* For UDQS */
+ temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL1) | (0x000000D0);
+ writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL1);
+ dmcdelay(2500u);
+ writel(0x00800000, dmc.reg + REG_DMC_DDR_ROOT_CTL);
+ dmcdelay(2500u);
+ writel(0x0, dmc.reg + REG_DMC_DDR_ROOT_CTL);
+ stat_value = (readl(dmc.reg + REG_DMC_DDR_SCRATCH_STAT1) &
+ (0xFFFF0000)) >> 16;
+ WL_code_UDQS = (stat_value) & (0x0000001F);
+
+ temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL1);
+ temp &= ~(BITM_DMC_DDR_LANE0_CTL1_BYPCODE |
+ BITM_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN);
+ writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL1);
+
+ /* If write leveling is enabled */
+ if ((dmc.dmc_mr1_value & BITM_DMC_MR1_WL) >> BITP_DMC_MR1_WL) {
+ temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL1);
+ temp |= (((WL_code_UDQS + LANE1_DQS_DELAY) <<
+ BITP_DMC_DDR_LANE0_CTL1_BYPCODE) &
+ BITM_DMC_DDR_LANE0_CTL1_BYPCODE) |
+ BITM_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN;
+ writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL1);
+ } else {
+ temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL1);
+ temp |= (((DQS_DEFAULT_DELAY + LANE1_DQS_DELAY) <<
+ BITP_DMC_DDR_LANE0_CTL1_BYPCODE) &
+ BITM_DMC_DDR_LANE0_CTL1_BYPCODE) |
+ BITM_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN;
+ writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL1);
+ }
+ dmcdelay(2500u);
+#endif
+
+#else
+ /* 5. Program the DMCx_CTL.DLLCTL register with 0x948 value
+ * (DATACYC=9, DLLCALRDCNT=72).
+ */
+ writel(0x00000948, dmc.reg + REG_DMC_DLLCTL);
+#endif
+
+ /* 6. Workaround for anomaly#20000037 */
+ if (dmc.anomaly_20000037_applicable) {
+ /* Perform dummy read to any DMC location */
+ readl(0x80000000);
+
+ writel(readl(dmc.reg + REG_DMC_PHY_CTL0) | 0x1000,
+ dmc.reg + REG_DMC_PHY_CTL0);
+ /* Clear DMCx_PHY_CTL0.RESETDAT bit */
+ writel(readl(dmc.reg + REG_DMC_PHY_CTL0) & (~0x1000),
+ dmc.reg + REG_DMC_PHY_CTL0);
+ }
+}
+
+static inline void dmc_init(void)
+{
+ /* PHY Calibration+Initialization */
+ if (!dmc.phy_init_required)
+ goto out;
+
+ switch (dmc.calib_mode) {
+ case CALIBRATION_LEGACY:
+ calibration_legacy();
+ break;
+ case CALIBRATION_METHOD1:
+ calibration_method1();
+ break;
+ case CALIBRATION_METHOD2:
+ calibration_method2();
+ break;
+ }
+
+#if DQSTRIM
+ /* DQS duty trim */
+ temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL0);
+ temp |= ((DQSCODE) << BITP_DMC_DDR_LANE0_CTL0_BYPENB) &
+ (BITM_DMC_DDR_LANE1_CTL0_BYPENB |
+ BITM_DMC_DDR_LANE0_CTL0_BYPSELP |
+ BITM_DMC_DDR_LANE0_CTL0_BYPCODE);
+ writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL0);
+
+ temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL0);
+ temp |= ((DQSCODE) << BITP_DMC_DDR_LANE1_CTL0_BYPENB) &
+ (BITM_DMC_DDR_LANE1_CTL1_BYPCODE |
+ BITM_DMC_DDR_LANE1_CTL0_BYPSELP |
+ BITM_DMC_DDR_LANE1_CTL0_BYPCODE);
+ writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL0);
+#endif
+
+#if CLKTRIM
+ /* Clock duty trim */
+ temp = readl(dmc.reg + REG_DMC_DDR_CA_CTL);
+ temp |= (((CLKCODE << BITP_DMC_DDR_CA_CTL_BYPCODE1) &
+ BITM_DMC_DDR_CA_CTL_BYPCODE1) |
+ BITM_DMC_DDR_CA_CTL_BYPENB |
+ ((CLKDIR << BITP_DMC_DDR_CA_CTL_BYPSELP) &
+ BITM_DMC_DDR_CA_CTL_BYPSELP));
+ writel(temp, dmc.reg + REG_DMC_DDR_CA_CTL);
+#endif
+
+out:
+ /* Controller Initialization */
+ dmc_controller_init();
+}
+
+static inline void __dmc_config(uint32_t dmc_no)
+{
+ if (dmc_no == 0) {
+ dmc.reg = REG_DMC0_BASE;
+ dmc.dmc_data_calib_add_value = DMC0_DATA_CALIB_ADD;
+ } else if (dmc_no == 1) {
+ dmc.reg = REG_DMC1_BASE;
+ dmc.dmc_data_calib_add_value = DMC1_DATA_CALIB_ADD;
+ } else {
+ return;
+ }
+
+ if (IS_ENABLED(CONFIG_ADI_USE_DDR2))
+ dmc.ddr_mode = DDR2_MODE;
+ else
+ dmc.ddr_mode = DDR3_MODE;
+
+ dmc.phy_init_required = true;
+
+#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64)
+ dmc.anomaly_20000037_applicable = false;
+ dmc.dmc_dllctl_value = DMC_DLLCTL_VALUE;
+ dmc.calib_mode = CALIBRATION_METHOD2;
+#else
+ dmc.anomaly_20000037_applicable = true;
+ dmc.calib_mode = CALIBRATION_LEGACY;
+#endif
+
+ dmc.dmc_ctl_value = DMC_CTL_VALUE;
+ dmc.dmc_cfg_value = DMC_CFG_VALUE;
+ dmc.dmc_tr0_value = DMC_TR0_VALUE;
+ dmc.dmc_tr1_value = DMC_TR1_VALUE;
+ dmc.dmc_tr2_value = DMC_TR2_VALUE;
+ dmc.dmc_mr0_value = DMC_MR0_VALUE;
+ dmc.dmc_mr1_value = DMC_MR1_VALUE;
+ dmc.dmc_mr2_value = DMC_MR2_VALUE;
+
+#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64)
+ dmc.dmc_mr3_value = DMC_MR3_VALUE;
+ dmc.dmc_zqctl0_value = DMC_ZQCTL0_VALUE;
+ dmc.dmc_zqctl1_value = DMC_ZQCTL1_VALUE;
+ dmc.dmc_zqctl2_value = DMC_ZQCTL2_VALUE;
+#endif
+
+ dmc.padctl2_value = DMC_PADCTL2_VALUE;
+ dmc.dmc_cphyctl_value = DMC_CPHYCTL_VALUE;
+
+ /* Initialize DMC now */
+ dmc_init();
+}
+
+void DMC_Config(void)
+{
+ if (IS_ENABLED(CONFIG_ADI_USE_DMC0))
+ __dmc_config(0);
+
+ if (IS_ENABLED(CONFIG_ADI_USE_DMC1))
+ __dmc_config(1);
+}
diff --git a/arch/arm/mach-sc5xx/init/dmcinit.h b/arch/arm/mach-sc5xx/init/dmcinit.h
new file mode 100644
index 0000000..46ff729
--- /dev/null
+++ b/arch/arm/mach-sc5xx/init/dmcinit.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ * Contact: Greg Malysa <greg.malysa@timesys.com>
+ */
+
+#ifndef DMCINIT_H_
+#define DMCINIT_H_
+
+#include <config.h>
+
+#ifdef MEM_MT41K512M16HA
+ #include "mem/mt41k512m16ha.h"
+#elif defined(MEM_MT41K128M16JT)
+ #include "mem/mt41k128m16jt.h"
+#elif defined(MEM_MT47H128M16RT)
+ #include "mem/mt47h128m16rt.h"
+#elif defined(MEM_IS43TR16512BL)
+ #include "mem/is43tr16512bl.h"
+#else
+ #error "No DDR part name is defined for this board."
+#endif
+
+void DMC_Config(void);
+void adi_dmc_reset_lanes(bool reset);
+
+#endif
diff --git a/arch/arm/mach-sc5xx/init/mem/is43tr16512bl.h b/arch/arm/mach-sc5xx/init/mem/is43tr16512bl.h
new file mode 100644
index 0000000..a583837
--- /dev/null
+++ b/arch/arm/mach-sc5xx/init/mem/is43tr16512bl.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ * Contact: Greg Malysa <greg.malysa@timesys.com>
+ */
+
+#ifndef IS43TR16512BL_H
+#define IS43TR16512BL_H
+
+/* DMC0 setup for the EV-21593-SOM and EV-SC594-SOM :
+ * - uses a single 8GB IS43TR16512BL-125KBL DDR3 chip configured for
+ * 800 MHz DCLK.
+ * DMC0 setup for the EV-SC594-SOMS :
+ * - uses a single 4GB IS43TR16256BL-093NBL DDR3 chip configured for
+ * 800 MHz DCLK.
+ */
+#define DMC_DLLCALRDCNT 240
+#define DMC_DATACYC 12
+#define DMC_TRCD 11
+#define DMC_TWTR 6
+#define DMC_TRP 11
+#define DMC_TRAS 28
+#define DMC_TRC 39
+#define DMC_TMRD 4
+#define DMC_TREF 6240
+#define DMC_TRRD 6
+#define DMC_TFAW 32
+#define DMC_TRTP 6
+#define DMC_TWR 12
+#define DMC_TXP 5
+#define DMC_TCKE 4
+#define DMC_CL0 0
+#define DMC_CL123 7
+#define DMC_WRRECOV 6
+#define DMC_MR1_DLLEN 0
+#define DMC_MR1_DIC0 0
+#define DMC_MR1_RTT0 0
+#define DMC_MR1_AL 0
+#define DMC_MR1_DIC1 0
+#define DMC_MR1_RTT1 1
+#define DMC_MR1_WL 0
+#define DMC_MR1_RTT2 0
+#define DMC_MR1_TDQS 0
+#define DMC_MR1_QOFF 0
+#define DMC_WL 3
+#define DMC_RDTOWR 5
+#define DMC_CTL_AL_EN 1
+#if defined(MEM_ISSI_4Gb_DDR3_800MHZ)
+ #define SDR_CHIP_SIZE (ENUM_DMC_CFG_SDRSIZE4G)
+ #define DMC_TRFC 208ul
+#elif defined(MEM_ISSI_8Gb_DDR3_800MHZ)
+ #define SDR_CHIP_SIZE (ENUM_DMC_CFG_SDRSIZE8G)
+ #define DMC_TRFC 280ul
+#else
+ #error "Need to select MEM_ISSI_4Gb_DDR3_800MHZ or MEM_ISSI_8Gb_DDR3_800MHZ"
+#endif
+
+#endif
diff --git a/arch/arm/mach-sc5xx/init/mem/mt41k128m16jt.h b/arch/arm/mach-sc5xx/init/mem/mt41k128m16jt.h
new file mode 100644
index 0000000..8827775
--- /dev/null
+++ b/arch/arm/mach-sc5xx/init/mem/mt41k128m16jt.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ * Contact: Greg Malysa <greg.malysa@timesys.com>
+ */
+
+#ifndef MT41K128M16JT_H
+#define MT41K128M16JT_H
+
+/* Default DDR3 part assumed: MT41K128M16JT-125, 2Gb part */
+/* For DCLK= 450 MHz */
+#define DMC_DLLCALRDCNT 72
+#define DMC_DATACYC 9
+#define DMC_TRCD 6
+#define DMC_TWTR 4
+#define DMC_TRP 6
+#define DMC_TRAS 17
+#define DMC_TRC 23
+#define DMC_TMRD 4
+#define DMC_TREF 3510
+#define DMC_TRFC 72
+#define DMC_TRRD 4
+#define DMC_TFAW 17
+#define DMC_TRTP 4
+#define DMC_TWR 7
+#define DMC_TXP 4
+#define DMC_TCKE 3
+#define DMC_CL0 0
+#define DMC_CL123 3
+#define DMC_WRRECOV (DMC_TWR - 1)
+#define DMC_MR1_DLLEN 0
+#define DMC_MR1_DIC0 1
+#define DMC_MR1_RTT0 1
+#define DMC_MR1_AL 0
+#define DMC_MR1_DIC1 0
+#define DMC_MR1_RTT1 0
+#define DMC_MR1_WL 0
+#define DMC_MR1_RTT2 0
+#define DMC_MR1_TDQS 0
+#define DMC_MR1_QOFF 0
+#define DMC_WL 1
+#define DMC_RDTOWR 2
+#define DMC_CTL_AL_EN 0
+#define SDR_CHIP_SIZE ENUM_DMC_CFG_SDRSIZE2G
+
+#endif
diff --git a/arch/arm/mach-sc5xx/init/mem/mt41k512m16ha.h b/arch/arm/mach-sc5xx/init/mem/mt41k512m16ha.h
new file mode 100644
index 0000000..5735b87
--- /dev/null
+++ b/arch/arm/mach-sc5xx/init/mem/mt41k512m16ha.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ * Contact: Greg Malysa <greg.malysa@timesys.com>
+ */
+
+#ifndef MT41K512M16HA_H
+#define MT41K512M16HA_H
+
+/* Default DDR3 part assumed: MT41K512M16HA-107, 8Gb part */
+/* For DCLK= 450 MHz */
+#define DMC_DLLCALRDCNT 72
+#define DMC_DATACYC 9
+#define DMC_TRCD 7
+#define DMC_TWTR 4
+#define DMC_TRP 7
+#define DMC_TRAS 10
+#define DMC_TRC 16
+#define DMC_TMRD 4
+#define DMC_TREF 3510
+#define DMC_TRFC 158
+#define DMC_TRRD 6
+#define DMC_TFAW 16
+#define DMC_TRTP 4
+#define DMC_TWR 7
+#define DMC_TXP 3
+#define DMC_TCKE 3
+#define DMC_CL0 0
+#define DMC_CL123 3
+#define DMC_WRRECOV (DMC_TWR - 1)
+#define DMC_MR1_DLLEN 0
+#define DMC_MR1_DIC0 1
+#define DMC_MR1_RTT0 1
+#define DMC_MR1_AL 0
+#define DMC_MR1_DIC1 0
+#define DMC_MR1_RTT1 0
+#define DMC_MR1_WL 0
+#define DMC_MR1_RTT2 0
+#define DMC_MR1_TDQS 0
+#define DMC_MR1_QOFF 0
+#define DMC_WL 1
+#define DMC_RDTOWR 2
+#define DMC_CTL_AL_EN 0
+#define SDR_CHIP_SIZE ENUM_DMC_CFG_SDRSIZE8G
+
+#endif
diff --git a/arch/arm/mach-sc5xx/init/mem/mt47h128m16rt.h b/arch/arm/mach-sc5xx/init/mem/mt47h128m16rt.h
new file mode 100644
index 0000000..5ada7f2
--- /dev/null
+++ b/arch/arm/mach-sc5xx/init/mem/mt47h128m16rt.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ * Contact: Greg Malysa <greg.malysa@timesys.com>
+ */
+
+#ifndef MT47H128M16RT_H
+#define MT47H128M16RT_H
+
+/* Default DDR2 part: MT47H128M16RT-25E XIT:C, 2 Gb part */
+/* For DCLK= 400 MHz */
+#define DMC_DLLCALRDCNT 72
+#define DMC_DATACYC 9
+#define DMC_TRCD 5
+#define DMC_TWTR 3
+#define DMC_TRP 5
+#define DMC_TRAS 16
+#define DMC_TRC 22
+#define DMC_TMRD 2
+#define DMC_TREF 3120
+#define DMC_TRFC 78
+#define DMC_TRRD 4
+#define DMC_TFAW 18
+#define DMC_TRTP 3
+#define DMC_TWR 6
+#define DMC_TXP 2
+#define DMC_TCKE 3
+#define DMC_CL 5
+#define DMC_WRRECOV (DMC_TWR - 1)
+#define DMC_MR1_DLLEN 0
+#define DMC_MR1_DIC0 1
+#define DMC_MR1_RTT0 1
+#define DMC_MR1_AL 4
+#define DMC_MR1_DIC1 0
+#define DMC_MR1_RTT1 0
+#define DMC_MR1_WL 0
+#define DMC_MR1_RTT2 0
+#define DMC_MR1_TDQS 0
+#define DMC_MR1_QOFF 0
+#define DMC_BL 4
+#define DMC_RDTOWR 2
+#define DMC_CTL_AL_EN 0
+#define SDR_CHIP_SIZE ENUM_DMC_CFG_SDRSIZE2G
+
+#endif
diff --git a/arch/arm/mach-sc5xx/rcu.c b/arch/arm/mach-sc5xx/rcu.c
new file mode 100644
index 0000000..4935750
--- /dev/null
+++ b/arch/arm/mach-sc5xx/rcu.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2024 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Contact: Ian Roberts <ian.roberts@timesys.com>
+ */
+
+#include <dm.h>
+#include <syscon.h>
+
+static const struct udevice_id adi_syscon_ids[] = {
+ { .compatible = "adi,reset-controller" },
+ { }
+};
+
+U_BOOT_DRIVER(syscon_sc5xx_rcu) = {
+ .name = "sc5xx_rcu",
+ .id = UCLASS_SYSCON,
+ .of_match = adi_syscon_ids,
+};
diff --git a/arch/arm/mach-sc5xx/sc57x.c b/arch/arm/mach-sc5xx/sc57x.c
new file mode 100644
index 0000000..b058768
--- /dev/null
+++ b/arch/arm/mach-sc5xx/sc57x.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2024 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ * Contact: Greg Malysa <greg.malysa@timesys.com>
+ */
+
+#include <asm/io.h>
+#include <asm/arch-adi/sc5xx/sc5xx.h>
+#include <asm/arch-adi/sc5xx/spl.h>
+
+#define REG_SPU0_SECUREC0 0x3108B980
+#define REG_PADS0_PCFG0 0x31004404
+#define REG_SPU0_SECUREP_START 0x3108BA00
+#define REG_SPU0_SECUREP_END 0x3108BD24
+
+adi_rom_boot_fn adi_rom_boot = (adi_rom_boot_fn)0x000000e1;
+
+void sc5xx_enable_rgmii(void)
+{
+ writel((readl(REG_PADS0_PCFG0) | 0xc), REG_PADS0_PCFG0);
+}
+
+void sc5xx_soc_init(void)
+{
+ sc5xx_enable_ns_sharc_access(REG_SPU0_SECUREC0);
+ sc5xx_disable_spu0(REG_SPU0_SECUREP_START, REG_SPU0_SECUREP_END);
+ sc5xx_enable_pmu();
+}
diff --git a/arch/arm/mach-sc5xx/sc58x.c b/arch/arm/mach-sc5xx/sc58x.c
new file mode 100644
index 0000000..0f89277
--- /dev/null
+++ b/arch/arm/mach-sc5xx/sc58x.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2024 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ * Contact: Greg Malysa <greg.malysa@timesys.com>
+ */
+
+#include <asm/io.h>
+#include <asm/arch-adi/sc5xx/sc5xx.h>
+#include <asm/arch-adi/sc5xx/spl.h>
+
+#define REG_SPU0_SECUREC0 0x3108C980
+#define REG_PADS0_PCFG0 0x31004404
+#define REG_SPU0_SECUREP_START 0x3108CA00
+#define REG_SPU0_SECUREP_END 0x3108CCF0
+
+adi_rom_boot_fn adi_rom_boot = (adi_rom_boot_fn)0x000000e1;
+
+void sc5xx_enable_rgmii(void)
+{
+ writel((readl(REG_PADS0_PCFG0) | 0xc), REG_PADS0_PCFG0);
+}
+
+void sc5xx_soc_init(void)
+{
+ sc5xx_enable_ns_sharc_access(REG_SPU0_SECUREC0);
+ sc5xx_disable_spu0(REG_SPU0_SECUREP_START, REG_SPU0_SECUREP_END);
+ sc5xx_enable_pmu();
+}
diff --git a/arch/arm/mach-sc5xx/sc59x.c b/arch/arm/mach-sc5xx/sc59x.c
new file mode 100644
index 0000000..174c6f5
--- /dev/null
+++ b/arch/arm/mach-sc5xx/sc59x.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2024 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ * Contact: Greg Malysa <greg.malysa@timesys.com>
+ */
+
+#include <asm/io.h>
+#include <asm/arch-adi/sc5xx/sc5xx.h>
+#include <asm/arch-adi/sc5xx/spl.h>
+
+#define REG_SPU0_SECUREC0 0x3108B980
+#define REG_PADS0_PCFG0 0x31004604
+#define REG_SPU0_SECUREP_START 0x3108BA00
+#define REG_SPU0_SECUREP_END 0x3108BD24
+
+#define REG_SCB5_SPI2_OSPI_REMAP 0x30400000
+#define BITM_SCB5_SPI2_OSPI_REMAP_REMAP 0x00000003
+#define ENUM_SCB5_SPI2_OSPI_REMAP_OSPI0 0x00000001
+
+adi_rom_boot_fn adi_rom_boot = (adi_rom_boot_fn)0x000000e9;
+
+void sc5xx_enable_rgmii(void)
+{
+ writel((readl(REG_PADS0_PCFG0) | 0xc), REG_PADS0_PCFG0);
+}
+
+void sc59x_remap_ospi(void)
+{
+ clrsetbits_le32(REG_SCB5_SPI2_OSPI_REMAP,
+ BITM_SCB5_SPI2_OSPI_REMAP_REMAP,
+ ENUM_SCB5_SPI2_OSPI_REMAP_OSPI0);
+}
+
+void sc5xx_soc_init(void)
+{
+ sc5xx_enable_ns_sharc_access(REG_SPU0_SECUREC0);
+ sc5xx_disable_spu0(REG_SPU0_SECUREP_START, REG_SPU0_SECUREP_END);
+ sc5xx_enable_pmu();
+}
diff --git a/arch/arm/mach-sc5xx/sc59x_64.c b/arch/arm/mach-sc5xx/sc59x_64.c
new file mode 100644
index 0000000..82537bf
--- /dev/null
+++ b/arch/arm/mach-sc5xx/sc59x_64.c
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2024 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ * Contact: Greg Malysa <greg.malysa@timesys.com>
+ */
+
+#include <asm/io.h>
+#include <asm/arch-adi/sc5xx/sc5xx.h>
+#include <asm/arch-adi/sc5xx/spl.h>
+
+#define REG_TSGENWR0_CNTCR 0x310AE000
+#define REG_PADS0_PCFG0 0x31004604
+#define REG_RCU0_BCODE 0x3108C028
+
+#define REG_SPU0_SECUREP_START 0x3108BA00
+#define REG_SPU0_WP_START 0x3108B400
+#define REG_SPU0_SECUREC0 0x3108B980
+
+#define REG_SCB5_SPI2_OSPI_REMAP 0x30400000
+#define BITM_SCB5_SPI2_OSPI_REMAP_REMAP 0x00000003
+#define ENUM_SCB5_SPI2_OSPI_REMAP_OSPI0 0x00000001
+
+adi_rom_boot_fn adi_rom_boot = (adi_rom_boot_fn)0x000000e4;
+
+void sc5xx_enable_rgmii(void)
+{
+ writel((readl(REG_PADS0_PCFG0) | 0xc), REG_PADS0_PCFG0);
+
+ // Set dw for little endian operation as well
+ writel(readl(REG_PADS0_PCFG0) & ~(1 << 19), REG_PADS0_PCFG0);
+ writel(readl(REG_PADS0_PCFG0) & ~(1 << 20), REG_PADS0_PCFG0);
+}
+
+void sc59x_remap_ospi(void)
+{
+ clrsetbits_le32(REG_SCB5_SPI2_OSPI_REMAP,
+ BITM_SCB5_SPI2_OSPI_REMAP_REMAP,
+ ENUM_SCB5_SPI2_OSPI_REMAP_OSPI0);
+}
+
+/**
+ * SPU/SMPU configuration is the default for permissive access from non-secure
+ * EL1. If TFA and OPTEE are configured, they run *after* this code, as the
+ * current boot flow is SPL -> TFA -> OPTEE -> Proper -> Linux, and will
+ * be expected to configure peripheral security correctly. If they are not
+ * configured, then this permissive setting will allow Linux (which always
+ * runs in NS EL1) to control all access to these peripherals. Without it,
+ * the peripherals would simply be unavailable in a non-security build,
+ * which is not OK.
+ */
+void sc5xx_soc_init(void)
+{
+ phys_addr_t smpus[] = {
+ 0x31007800, //SMPU0
+ 0x31083800, //SMPU2
+ 0x31084800, //SMPU3
+ 0x31085800, //SMPU4
+ 0x31086800, //SMPU5
+ 0x31087800, //SMPU6
+ 0x310A0800, //SMPU9
+ 0x310A1800, //SMPU11
+ 0x31012800, //SMPU12
+ };
+ size_t i;
+
+ // Enable coresight timer
+ writel(1, REG_TSGENWR0_CNTCR);
+
+ //Do not rerun preboot routine --
+ // Without this, hardware resets triggered by RCU0_CTL:SYSRST
+ // lead to a deadlock somewhere in the boot ROM
+ writel(0x200, REG_RCU0_BCODE);
+
+ /* Alter outstanding transactions property of A55*/
+ writel(0x1, 0x30643108); /* SCB6 A55 M0 Ib.fn Mod */
+ isb();
+
+ /* configure DDR prefetch behavior, per ADI */
+ writel(0x1, 0x31076000);
+
+ /* configure smart mode, per ADI */
+ writel(0x1307, 0x31076004);
+
+ // Disable SPU and SPU WP registers
+ sc5xx_disable_spu0(REG_SPU0_SECUREP_START, REG_SPU0_SECUREP_START + 4*213);
+ sc5xx_disable_spu0(REG_SPU0_WP_START, REG_SPU0_WP_START + 4*213);
+
+ /* configure smpus permissively */
+ for (i = 0; i < ARRAY_SIZE(smpus); ++i)
+ writel(0x500, smpus[i]);
+
+ sc5xx_enable_ns_sharc_access(REG_SPU0_SECUREC0);
+}
diff --git a/arch/arm/mach-sc5xx/soc.c b/arch/arm/mach-sc5xx/soc.c
new file mode 100644
index 0000000..8f13127
--- /dev/null
+++ b/arch/arm/mach-sc5xx/soc.c
@@ -0,0 +1,179 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ * Contact: Greg Malysa <greg.malysa@timesys.com>
+ */
+
+#include <asm/arch-adi/sc5xx/sc5xx.h>
+#include <asm/arch-adi/sc5xx/soc.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <cpu_func.h>
+
+#ifdef CONFIG_SC58X
+ #define RCU0_CTL 0x3108B000
+ #define RCU0_STAT 0x3108B004
+ #define RCU0_CRCTL 0x3108B008
+ #define RCU0_CRSTAT 0x3108B00C
+ #define RCU0_SIDIS 0x3108B010
+ #define RCU0_MSG_SET 0x3108B064
+#elif defined(CONFIG_SC57X) || defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64)
+ #define RCU0_CTL 0x3108C000
+ #define RCU0_STAT 0x3108C004
+ #define RCU0_CRCTL 0x3108C008
+ #define RCU0_CRSTAT 0x3108C00C
+ #define RCU0_SIDIS 0x3108C01C
+ #define RCU0_MSG_SET 0x3108C070
+#else
+ #error "No SC5xx SoC CONFIG_ enabled"
+#endif
+
+#define BITP_RCU_STAT_BMODE 8
+#define BITM_RCU_STAT_BMODE 0x00000F00
+
+#define REG_ARMPMU0_PMCR 0x31121E04
+#define REG_ARMPMU0_PMUSERENR 0x31121E08
+#define REG_ARMPMU0_PMLAR 0x31121FB0
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void reset_cpu(void)
+{
+ u32 val = readl(RCU0_CTL);
+ writel(val | 1, RCU0_CTL);
+}
+
+void enable_caches(void)
+{
+ if (!IS_ENABLED(CONFIG_SYS_DCACHE_OFF))
+ dcache_enable();
+}
+
+void sc5xx_enable_ns_sharc_access(uintptr_t securec0_base)
+{
+ writel(0, securec0_base);
+ writel(0, securec0_base + 0x4);
+ writel(0, securec0_base + 0x8);
+}
+
+void sc5xx_disable_spu0(uintptr_t spu0_start, uintptr_t spu0_end)
+{
+ for (uintptr_t i = spu0_start; i <= spu0_end; i += 4)
+ writel(0, i);
+}
+
+/**
+ * PMU is only available on armv7 platforms and all share the same location
+ */
+void sc5xx_enable_pmu(void)
+{
+ if (!IS_ENABLED(CONFIG_SC59X_64)) {
+ writel(readl(REG_ARMPMU0_PMUSERENR) | 0x01, REG_ARMPMU0_PMUSERENR);
+ writel(0xc5acce55, REG_ARMPMU0_PMLAR);
+ writel(readl(REG_ARMPMU0_PMCR) | (1 << 1), REG_ARMPMU0_PMCR);
+ }
+}
+
+const char *sc5xx_get_boot_mode(u32 *bmode)
+{
+ static const char * const bmodes[] = {
+ "JTAG/BOOTROM",
+ "QSPI Master",
+ "QSPI Slave",
+ "UART",
+ "LP0 Slave",
+ "OSPI",
+#ifdef CONFIG_SC59X_64
+ "eMMC"
+#endif
+ };
+ u32 local_mode;
+
+ local_mode = (readl(RCU0_STAT) & BITM_RCU_STAT_BMODE) >> BITP_RCU_STAT_BMODE;
+
+#if CONFIG_ADI_SPL_FORCE_BMODE != 0
+ /*
+ * In case we want to force boot sequences such as:
+ * QSPI -> OSPI
+ * QSPI -> eMMC
+ * If this is not set, then we will always try to use the BMODE setting
+ * for both stages... i.e.
+ * QSPI -> QSPI
+ */
+
+ // (Don't allow skipping JTAG/UART BMODE settings)
+ if (local_mode != 0 && local_mode != 3)
+ local_mode = CONFIG_ADI_SPL_FORCE_BMODE;
+#endif
+
+ *bmode = local_mode;
+
+ if (local_mode >= 0 && local_mode <= ARRAY_SIZE(bmodes))
+ return bmodes[local_mode];
+ return "unknown";
+}
+
+void print_cpu_id(void)
+{
+ if (!IS_ENABLED(CONFIG_ARM64)) {
+ u32 cpuid = 0;
+
+ __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0" : "=r"(cpuid));
+
+ printf("Detected Revision: %d.%d\n", cpuid & 0xf00000 >> 20, cpuid & 0xf);
+ }
+}
+
+int print_cpuinfo(void)
+{
+ u32 bmode;
+
+ printf("CPU: ADSP %s (%s boot)\n", CONFIG_LDR_CPU, sc5xx_get_boot_mode(&bmode));
+ print_cpu_id();
+
+ return 0;
+}
+
+void fixup_dp83867_phy(struct phy_device *phydev)
+{
+ int phy_data = 0;
+
+ phy_data = phy_read(phydev, MDIO_DEVAD_NONE, 0x32);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x32, (1 << 7) | phy_data);
+ int cfg3 = 0;
+ #define MII_DP83867_CFG3 (0x1e)
+ /*
+ * Pin INT/PWDN on DP83867 should be configured as an Interrupt Output
+ * instead of a Power-Down Input on ADI SC5XX boards in order to
+ * prevent the signal interference from other peripherals during they
+ * are running at the same time.
+ */
+ cfg3 = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG3);
+ cfg3 |= (1 << 7);
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG3, cfg3);
+
+ // Mystery second port fixup on ezkits with two PHYs
+ if (CONFIG_DW_PORTS & 2)
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x11, 3);
+
+ if (IS_ENABLED(CONFIG_ADI_BUG_EZKHW21)) {
+ phydev->advertising &= PHY_BASIC_FEATURES;
+ phydev->speed = SPEED_100;
+ }
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ if (IS_ENABLED(CONFIG_ADI_BUG_EZKHW21))
+ phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x3100);
+}
+
+int dram_init(void)
+{
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
+ return 0;
+}
diff --git a/arch/arm/mach-sc5xx/spl.c b/arch/arm/mach-sc5xx/spl.c
new file mode 100644
index 0000000..68e0310
--- /dev/null
+++ b/arch/arm/mach-sc5xx/spl.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ * Contact: Greg Malysa <greg.malysa@timesys.com>
+ */
+
+#include <spl.h>
+#include <asm/arch-adi/sc5xx/sc5xx.h>
+#include <asm/arch-adi/sc5xx/spl.h>
+#include "init/clkinit.h"
+#include "init/dmcinit.h"
+
+static bool adi_start_uboot_proper;
+
+static int adi_sf_default_bus = CONFIG_SF_DEFAULT_BUS;
+static int adi_sf_default_cs = CONFIG_SF_DEFAULT_CS;
+static int adi_sf_default_speed = CONFIG_SF_DEFAULT_SPEED;
+
+u32 bmode;
+
+int spl_start_uboot(void)
+{
+ return adi_start_uboot_proper;
+}
+
+unsigned int spl_spi_get_default_speed(void)
+{
+ return adi_sf_default_speed;
+}
+
+unsigned int spl_spi_get_default_bus(void)
+{
+ return adi_sf_default_bus;
+}
+
+unsigned int spl_spi_get_default_cs(void)
+{
+ return adi_sf_default_cs;
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ const char *bmodestring = sc5xx_get_boot_mode(&bmode);
+
+ printf("ADI Boot Mode: 0x%x (%s)\n", bmode, bmodestring);
+
+ /*
+ * By default everything goes back to the bootrom, where we'll read table
+ * parameters and ask for another image to be loaded
+ */
+ spl_boot_list[0] = BOOT_DEVICE_BOOTROM;
+
+ if (bmode == 0) {
+ printf("SPL execution has completed. Please load U-Boot Proper via JTAG");
+ while (1)
+ ;
+ }
+}
+
+int32_t __weak adi_rom_boot_hook(struct ADI_ROM_BOOT_CONFIG *config, int32_t cause)
+{
+ return 0;
+}
+
+int board_return_to_bootrom(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
+{
+#if CONFIG_ADI_SPL_FORCE_BMODE != 0
+ // see above
+ if (bmode != 0 && bmode != 3)
+ bmode = CONFIG_ADI_SPL_FORCE_BMODE;
+#endif
+
+ if (bmode >= (ARRAY_SIZE(adi_rom_boot_args)))
+ bmode = 0;
+
+ adi_rom_boot((void *)adi_rom_boot_args[bmode].addr,
+ adi_rom_boot_args[bmode].flags,
+ 0, &adi_rom_boot_hook,
+ adi_rom_boot_args[bmode].cmd);
+ return 0;
+};
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ clks_init();
+ DMC_Config();
+ sc5xx_soc_init();
+
+ ret = spl_early_init();
+ if (ret)
+ panic("spl_early_init() failed\n");
+
+ preloader_console_init();
+}
+
diff --git a/board/beagle/beagleplay/beagleplay.env b/board/beagle/beagleplay/beagleplay.env
index bbf6b92..8dbfc2f 100644
--- a/board/beagle/beagleplay/beagleplay.env
+++ b/board/beagle/beagleplay/beagleplay.env
@@ -1,5 +1,6 @@
#include <env/ti/ti_common.env>
#include <env/ti/mmc.env>
+#include <env/ti/k3_dfu.env>
name_kern=Image
console=ttyS2,115200n8
diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile
index 3feb00f..c34fc50 100644
--- a/board/phytec/common/Makefile
+++ b/board/phytec/common/Makefile
@@ -5,6 +5,8 @@
ifdef CONFIG_SPL_BUILD
# necessary to create built-in.o
obj- := __dummy__.o
+else
+obj-$(CONFIG_ARCH_K3) += k3/
endif
obj-y += phytec_som_detection.o
diff --git a/board/phytec/common/k3/Makefile b/board/phytec/common/k3/Makefile
new file mode 100644
index 0000000..bcca1a9
--- /dev/null
+++ b/board/phytec/common/k3/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0+
+obj-y += board.o
diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c
new file mode 100644
index 0000000..9cb168c
--- /dev/null
+++ b/board/phytec/common/k3/board.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
+ * Author: Wadim Egorov <w.egorov@phytec.de>
+ */
+
+#include <env_internal.h>
+#include <spl.h>
+#include <asm/arch/hardware.h>
+
+#if IS_ENABLED(CONFIG_ENV_IS_IN_FAT) || IS_ENABLED(CONFIG_ENV_IS_IN_MMC)
+int mmc_get_env_dev(void)
+{
+ u32 boot_device = get_boot_device();
+
+ switch (boot_device) {
+ case BOOT_DEVICE_MMC1:
+ return 0;
+ case BOOT_DEVICE_MMC2:
+ return 1;
+ };
+
+ return CONFIG_SYS_MMC_ENV_DEV;
+}
+#endif
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ u32 boot_device = get_boot_device();
+
+ if (prio)
+ return ENVL_UNKNOWN;
+
+ switch (boot_device) {
+ case BOOT_DEVICE_MMC1:
+ case BOOT_DEVICE_MMC2:
+ if (CONFIG_IS_ENABLED(ENV_IS_IN_FAT))
+ return ENVL_FAT;
+ if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC))
+ return ENVL_MMC;
+ case BOOT_DEVICE_SPI:
+ if (CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH))
+ return ENVL_SPI_FLASH;
+ default:
+ return ENVL_NOWHERE;
+ };
+}
+
+#if IS_ENABLED(CONFIG_BOARD_LATE_INIT)
+int board_late_init(void)
+{
+ u32 boot_device = get_boot_device();
+
+ switch (boot_device) {
+ case BOOT_DEVICE_MMC1:
+ env_set_ulong("mmcdev", 0);
+ env_set("boot", "mmc");
+ break;
+ case BOOT_DEVICE_MMC2:
+ env_set_ulong("mmcdev", 1);
+ env_set("boot", "mmc");
+ break;
+ case BOOT_DEVICE_SPI:
+ env_set("boot", "spi");
+ break;
+ case BOOT_DEVICE_ETHERNET:
+ env_set("boot", "net");
+ break;
+ };
+
+ return 0;
+}
+#endif
diff --git a/board/phytec/phycore_am62x/phycore-am62x.c b/board/phytec/phycore_am62x/phycore-am62x.c
index 618b4c3..a082b88 100644
--- a/board/phytec/phycore_am62x/phycore-am62x.c
+++ b/board/phytec/phycore_am62x/phycore-am62x.c
@@ -5,11 +5,8 @@
*/
#include <asm/io.h>
-#include <env.h>
-#include <env_internal.h>
#include <spl.h>
#include <fdt_support.h>
-#include <asm/arch/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -57,67 +54,3 @@
MCU_CTRL_DEVICE_CLKOUT_32K_CTRL);
}
#endif
-
-#if IS_ENABLED(CONFIG_ENV_IS_IN_FAT) || IS_ENABLED(CONFIG_ENV_IS_IN_MMC)
-int mmc_get_env_dev(void)
-{
- u32 boot_device = get_boot_device();
-
- switch (boot_device) {
- case BOOT_DEVICE_MMC1:
- return 0;
- case BOOT_DEVICE_MMC2:
- return 1;
- };
-
- return CONFIG_SYS_MMC_ENV_DEV;
-}
-#endif
-
-enum env_location env_get_location(enum env_operation op, int prio)
-{
- u32 boot_device = get_boot_device();
-
- if (prio)
- return ENVL_UNKNOWN;
-
- switch (boot_device) {
- case BOOT_DEVICE_MMC1:
- case BOOT_DEVICE_MMC2:
- if (CONFIG_IS_ENABLED(ENV_IS_IN_FAT))
- return ENVL_FAT;
- if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC))
- return ENVL_MMC;
- case BOOT_DEVICE_SPI:
- if (CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH))
- return ENVL_SPI_FLASH;
- default:
- return ENVL_NOWHERE;
- };
-}
-
-#if IS_ENABLED(CONFIG_BOARD_LATE_INIT)
-int board_late_init(void)
-{
- u32 boot_device = get_boot_device();
-
- switch (boot_device) {
- case BOOT_DEVICE_MMC1:
- env_set_ulong("mmcdev", 0);
- env_set("boot", "mmc");
- break;
- case BOOT_DEVICE_MMC2:
- env_set_ulong("mmcdev", 1);
- env_set("boot", "mmc");
- break;
- case BOOT_DEVICE_SPI:
- env_set("boot", "spi");
- break;
- case BOOT_DEVICE_ETHERNET:
- env_set("boot", "net");
- break;
- };
-
- return 0;
-}
-#endif
diff --git a/board/ti/am62x/am62x.env b/board/ti/am62x/am62x.env
index 9cb186c..09b9b16 100644
--- a/board/ti/am62x/am62x.env
+++ b/board/ti/am62x/am62x.env
@@ -1,5 +1,6 @@
#include <env/ti/ti_common.env>
#include <env/ti/mmc.env>
+#include <env/ti/k3_dfu.env>
name_kern=Image
console=ttyS2,115200n8
diff --git a/cmd/sandbox/exception.c b/cmd/sandbox/exception.c
index cfa153d..f9c847d 100644
--- a/cmd/sandbox/exception.c
+++ b/cmd/sandbox/exception.c
@@ -19,7 +19,11 @@
static int do_undefined(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
+#ifdef __powerpc__
+ asm volatile (".long 0xffffffff\n");
+#else
asm volatile (".word 0xffff\n");
+#endif
return CMD_RET_FAILURE;
}
diff --git a/configs/am62x_a53_usbdfu.config b/configs/am62x_a53_usbdfu.config
new file mode 100644
index 0000000..3a19cf2
--- /dev/null
+++ b/configs/am62x_a53_usbdfu.config
@@ -0,0 +1,29 @@
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_DFU=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_SPL_USB_DWC3_GENERIC=y
+CONFIG_SPL_USB_DWC3_AM62=y
+CONFIG_USB_DWC3_AM62=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/am62x_beagleplay_a53_defconfig b/configs/am62x_beagleplay_a53_defconfig
index 4f1be1d..ec62670 100644
--- a/configs/am62x_beagleplay_a53_defconfig
+++ b/configs/am62x_beagleplay_a53_defconfig
@@ -121,3 +121,5 @@
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
CONFIG_LZO=y
CONFIG_EFI_SET_TIME=y
+
+#include <configs/am62x_a53_usbdfu.config>
diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig
index 6c708dc..16294a6 100644
--- a/configs/am62x_evm_a53_defconfig
+++ b/configs/am62x_evm_a53_defconfig
@@ -68,6 +68,7 @@
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_TI_SCI=y
+CONFIG_DFU_SF=y
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
@@ -111,3 +112,5 @@
CONFIG_SYSRESET_TI_SCI=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
CONFIG_EFI_SET_TIME=y
+
+#include <configs/am62x_a53_usbdfu.config>
diff --git a/configs/am62x_r5_usbdfu.config b/configs/am62x_r5_usbdfu.config
new file mode 100644
index 0000000..772bb2a
--- /dev/null
+++ b/configs/am62x_r5_usbdfu.config
@@ -0,0 +1,28 @@
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000
+CONFIG_MISC=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_SPL_USB_DWC3_GENERIC=y
+CONFIG_SPL_USB_DWC3_AM62=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_DFU=y
+# CONFIG_SPL_MMC is not set
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+# CONFIG_SPL_SPI is not set
+# CONFIG_SPL_SYS_MALLOC is not set
+# CONFIG_CMD_GPT is not set
+# CONFIG_CMD_MMC is not set
+# CONFIG_CMD_FAT is not set
+# CONFIG_MMC_SDHCI is not set
diff --git a/configs/phycore_am64x_a53_defconfig b/configs/phycore_am64x_a53_defconfig
index 1a93597..1064fb0 100644
--- a/configs/phycore_am64x_a53_defconfig
+++ b/configs/phycore_am64x_a53_defconfig
@@ -38,6 +38,7 @@
CONFIG_BOOTSTD_FULL=y
CONFIG_BOOTCOMMAND="run mmcboot; bootflow scan -lb"
CONFIG_DEFAULT_FDT_FILE="oftree"
+CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x180000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
diff --git a/doc/board/beagle/am62x_beagleplay.rst b/doc/board/beagle/am62x_beagleplay.rst
index 7784e62..cdc6102 100644
--- a/doc/board/beagle/am62x_beagleplay.rst
+++ b/doc/board/beagle/am62x_beagleplay.rst
@@ -268,7 +268,19 @@
- USB Device Firmware Upgrade (DFU) mode
To switch to SD card boot mode, hold the USR button while powering on
-with Type-C power supply, then release when power LED lights up.
+with a USB type C power supply, then release when power LED lights up.
+
+DFU based boot
+--------------
+
+To boot the board over DFU, ensure there is no SD card inserted with a
+bootloader. Hold the USR switch while plugging into the type C to boot into DFU
+mode. After power-on the build artifacts needs to be uploaded one by one with a
+tool like dfu-util.
+
+.. include:: ../ti/am62x_sk.rst
+ :start-after: .. am62x_evm_rst_include_start_dfu_boot
+ :end-before: .. am62x_evm_rst_include_end_dfu_boot
Debugging U-Boot
----------------
diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst
index b12dc85..d5f7fe3 100644
--- a/doc/board/ti/am62x_sk.rst
+++ b/doc/board/ti/am62x_sk.rst
@@ -109,6 +109,20 @@
:start-after: .. k3_rst_include_start_build_steps_spl_r5
:end-before: .. k3_rst_include_end_build_steps_spl_r5
+* 3.1.1 Alternative build of R5 for DFU boot:
+
+As the SPL size can get too big when building with support for booting both
+from local storage *and* DFU an extra config fragment should be used to enable
+DFU support (and disable storage support)
+
+.. prompt:: bash $
+
+ export UBOOT_CFG_CORTEXR="${UBOOT_CFG_CORTEXR} am62x_r5_usbdfu.config"
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_spl_r5
+ :end-before: .. k3_rst_include_end_build_steps_spl_r5
+
* 3.2 A53:
.. include:: ../ti/k3.rst
@@ -251,6 +265,29 @@
For SW2 and SW1, the switch state in the "ON" position = 1.
+DFU based boot
+--------------
+
+To boot the board over DFU, set the switches to DFU mode and connect to the
+USB type C DRD port on the board. After power-on the build artifacts needs to be
+uploaded one by one with a tool like dfu-util.
+
+.. am62x_evm_rst_include_start_dfu_boot
+
+The initial ROM will have a DFU alt named `bootloader` for the initial R5 spl
+upload. The next stages as exposed by U-Boot have target alts matching the name
+of the artifacts, for these a USB reset has to be done after each upload.
+
+When using dfu-util the following commands can be used to boot to a U-Boot shell:
+
+.. prompt:: bash $
+
+ dfu-util -a bootloader -D tiboot3.bin
+ dfu-util -R -a tispl -D tispl.bin
+ dfu-util -R -a u-boot.img -D u-boot.img
+
+.. am62x_evm_rst_include_end_dfu_boot
+
Debugging U-Boot
----------------
diff --git a/doc/develop/codingstyle.rst b/doc/develop/codingstyle.rst
index f6248cd..fa3cd6a 100644
--- a/doc/develop/codingstyle.rst
+++ b/doc/develop/codingstyle.rst
@@ -110,9 +110,8 @@
You should follow this ordering in U-Boot. In all cases, they should be listed
in alphabetical order. First comes headers which are located directly in our
-top-level include diretory. This excludes the common.h header file which is to
-be removed. Second are headers within subdirectories, Finally directory-local
-includes should be listed. See this example:
+top-level include diretory. Second are headers within subdirectories, Finally
+directory-local includes should be listed. See this example:
.. code-block:: C
@@ -129,9 +128,6 @@
``#ifndef USE_HOSTCC`` to avoid including U-Boot specific include files. See
common/image.c for an example.
-If you encounter code which still uses <common.h> a patch to remove that and
-replace it with any required include files directly is much appreciated.
-
If your file uses driver model, include <dm.h> in the C file. Do not include
dm.h in a header file. Try to use forward declarations (e.g. ``struct
udevice``) instead.
diff --git a/doc/develop/tests_writing.rst b/doc/develop/tests_writing.rst
index bb1145d..44b544f 100644
--- a/doc/develop/tests_writing.rst
+++ b/doc/develop/tests_writing.rst
@@ -281,7 +281,6 @@
Create a new file in test/ or a subdirectory and define a macro to register the
suite. For example::
- #include <common.h>
#include <console.h>
#include <mapmem.h>
#include <dm/test.h>
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index bda6873..9acbc47 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -246,6 +246,7 @@
This clock driver adds support for clock realted settings for
ZynqMP platform.
+source "drivers/clk/adi/Kconfig"
source "drivers/clk/analogbits/Kconfig"
source "drivers/clk/at91/Kconfig"
source "drivers/clk/exynos/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 638ad04..847b9b2 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -12,6 +12,7 @@
obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o
obj-$(CONFIG_$(SPL_TPL_)CLK_GPIO) += clk-gpio.o
+obj-y += adi/
obj-y += analogbits/
obj-y += imx/
obj-$(CONFIG_CLK_JH7110) += starfive/
diff --git a/drivers/clk/adi/Kconfig b/drivers/clk/adi/Kconfig
new file mode 100644
index 0000000..5745bed
--- /dev/null
+++ b/drivers/clk/adi/Kconfig
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# (C) Copyright 2022 - Analog Devices, Inc.
+#
+# Written and/or maintained by Timesys Corporation
+#
+# Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+# Contact: Greg Malysa <greg.malysa@timesys.com>
+#
+
+config COMMON_CLK_ADI_SHARED
+ bool "Enable shared ADI clock framework code"
+ help
+ Required for shared code between SoC clock drivers. Automatically
+ selected by an appropriate SoC-specific clock driver version.
+
+config COMMON_CLK_ADI_SC598
+ bool "Clock driver for ADI SC598 SoCs"
+ select DM
+ select CLK
+ select CLK_CCF
+ select OF_CONTROL
+ select CMD_CLK
+ select SPL_DM if SPL
+ select SPL_CLK if SPL
+ select SPL_CLK_CCF if SPL
+ select SPL_OF_CONTROL if SPL
+ select COMMON_CLK_ADI_SHARED
+ depends on SC59X_64
+ help
+ This driver supports the system clocks on Analog Devices SC598-series
+ SoCs. It includes CGU and CDU clocks and supports gating unused clocks.
+ Modifying PLL configuration is not supported; that must be done prior
+ to booting the kernel. Clock dividers after the PLLs may be configured.
+
+config COMMON_CLK_ADI_SC594
+ bool "Clock driver for ADI SC594 SoCs"
+ select DM
+ select CLK
+ select CLK_CCF
+ select OF_CONTROL
+ select CMD_CLK
+ select SPL_DM if SPL
+ select SPL_CLK if SPL
+ select SPL_CLK_CCF if SPL
+ select SPL_OF_CONTROL if SPL
+ select COMMON_CLK_ADI_SHARED
+ depends on SC59X
+ help
+ This driver supports the system clocks on Analog Devices SC594-series
+ SoCs. It includes CGU and CDU clocks and supports gating unused clocks.
+ Modifying PLL configuration is not supported; that must be done prior
+ to booting the kernel. Clock dividers after the PLLs may be configured.
+
+config COMMON_CLK_ADI_SC58X
+ bool "Clock driver for ADI SC58X SoCs"
+ select DM
+ select CLK
+ select CLK_CCF
+ select OF_CONTROL
+ select CMD_CLK
+ select COMMON_CLK_ADI_SHARED
+ depends on SC58X
+ help
+ This driver supports the system clocks on Analog Devices SC58x-series
+ SoCs. It includes CGU and CDU clocks and supports gating unused clocks.
+ Modifying PLL configuration is not supported; that must be done prior
+ to booting the kernel. Clock dividers after the PLLs may be configured.
+
+config COMMON_CLK_ADI_SC57X
+ bool "Clock driver for ADI SC57X SoCs"
+ select DM
+ select CLK
+ select CLK_CCF
+ select OF_CONTROL
+ select CMD_CLK
+ select COMMON_CLK_ADI_SHARED
+ depends on SC57X
+ help
+ This driver supports the system clocks on Analog Devices SC57x-series
+ SoCs. It includes CGU and CDU clocks and supports gating unused clocks.
+ Modifying PLL configuration is not supported; that must be done prior
+ to booting the kernel. Clock dividers after the PLLs may be configured.
diff --git a/drivers/clk/adi/Makefile b/drivers/clk/adi/Makefile
new file mode 100644
index 0000000..f3f1fd9
--- /dev/null
+++ b/drivers/clk/adi/Makefile
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# (C) Copyright 2022 - Analog Devices, Inc.
+#
+# Written and/or maintained by Timesys Corporation
+#
+# Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+# Contact: Greg Malysa <greg.malysa@timesys.com>
+#
+
+obj-$(CONFIG_COMMON_CLK_ADI_SHARED) += clk-shared.o clk-adi-pll.o
+
+obj-$(CONFIG_COMMON_CLK_ADI_SC594) += clk-adi-sc594.o
+obj-$(CONFIG_COMMON_CLK_ADI_SC598) += clk-adi-sc598.o
+obj-$(CONFIG_COMMON_CLK_ADI_SC58X) += clk-adi-sc58x.o
+obj-$(CONFIG_COMMON_CLK_ADI_SC57X) += clk-adi-sc57x.o
diff --git a/drivers/clk/adi/clk-adi-pll.c b/drivers/clk/adi/clk-adi-pll.c
new file mode 100644
index 0000000..372baa9
--- /dev/null
+++ b/drivers/clk/adi/clk-adi-pll.c
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Author: Greg Malysa <greg.malysa@timesys.com>
+ *
+ * Ported from Linux: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ */
+
+#include <clk.h>
+#include <clk-uclass.h>
+#include <asm/io.h>
+#include <dm/device.h>
+#include <linux/compiler_types.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+
+#include "clk.h"
+
+#define ADI_CLK_PLL_GENERIC "adi_clk_pll_generic"
+
+struct clk_sc5xx_cgu_pll {
+ struct clk clk;
+ void __iomem *base;
+ u32 mask;
+ u32 max;
+ u32 m_offset;
+ u8 shift;
+ bool half_m;
+};
+
+#define to_clk_sc5xx_cgu_pll(_clk) container_of(_clk, struct clk_sc5xx_cgu_pll, clk)
+
+static unsigned long sc5xx_cgu_pll_get_rate(struct clk *clk)
+{
+ struct clk_sc5xx_cgu_pll *pll = to_clk_sc5xx_cgu_pll(dev_get_clk_ptr(clk->dev));
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+
+ u32 reg = readl(pll->base);
+ u32 m = ((reg & pll->mask) >> pll->shift) + pll->m_offset;
+
+ if (m == 0)
+ m = pll->max;
+
+ if (pll->half_m)
+ return parent_rate * m * 2;
+ return parent_rate * m;
+}
+
+static const struct clk_ops clk_sc5xx_cgu_pll_ops = {
+ .get_rate = sc5xx_cgu_pll_get_rate,
+};
+
+struct clk *sc5xx_cgu_pll(const char *name, const char *parent_name,
+ void __iomem *base, u8 shift, u8 width, u32 m_offset,
+ bool half_m)
+{
+ struct clk_sc5xx_cgu_pll *pll;
+ struct clk *clk;
+ int ret;
+ char *drv_name = ADI_CLK_PLL_GENERIC;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ pll->base = base;
+ pll->shift = shift;
+ pll->mask = GENMASK(width - 1, 0) << shift;
+ pll->max = pll->mask + 1;
+ pll->m_offset = m_offset;
+ pll->half_m = half_m;
+
+ clk = &pll->clk;
+
+ ret = clk_register(clk, drv_name, name, parent_name);
+ if (ret) {
+ pr_err("Failed to register %s in %s: %d\n", name, __func__, ret);
+ kfree(pll);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+U_BOOT_DRIVER(clk_adi_pll_generic) = {
+ .name = ADI_CLK_PLL_GENERIC,
+ .id = UCLASS_CLK,
+ .ops = &clk_sc5xx_cgu_pll_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/adi/clk-adi-sc57x.c b/drivers/clk/adi/clk-adi-sc57x.c
new file mode 100644
index 0000000..b17563f
--- /dev/null
+++ b/drivers/clk/adi/clk-adi-sc57x.c
@@ -0,0 +1,206 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Author: Greg Malysa <greg.malysa@timesys.com>
+ *
+ * Ported from Linux: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ */
+
+#include <clk.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dt-bindings/clock/adi-sc5xx-clock.h>
+#include <linux/compiler_types.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/printk.h>
+#include <linux/types.h>
+
+#include "clk.h"
+
+static const char * const cgu1_in_sels[] = {"sys_clkin0", "sys_clkin1"};
+static const char * const sharc0_sels[] = {"cclk0_0", "sysclk_0", "dummy", "dummy"};
+static const char * const sharc1_sels[] = {"cclk0_0", "sysclk_0", "dummy", "dummy"};
+static const char * const arm_sels[] = {"cclk1_0", "sysclk_0", "dummy", "dummy"};
+static const char * const cdu_ddr_sels[] = {"dclk_0", "dclk_1", "dummy", "dummy"};
+static const char * const can_sels[] = {"oclk_0", "oclk_1", "dclk_1", "oclk_0_half"};
+static const char * const spdif_sels[] = {"oclk_0", "oclk_1", "dclk_1", "dclk_0"};
+static const char * const gige_sels[] = {"sclk1_0", "sclk1_1", "cclk0_1", "oclk_0"};
+static const char * const sdio_sels[] = {"oclk_0_half", "cclk1_1_half", "cclk1_1",
+ "dclk_1"};
+
+static int sc57x_clock_probe(struct udevice *dev)
+{
+ void __iomem *cgu0;
+ void __iomem *cgu1;
+ void __iomem *cdu;
+ int ret;
+ struct resource res;
+
+ struct clk *clks[ADSP_SC57X_CLK_END];
+ struct clk dummy, clkin0, clkin1;
+
+ ret = dev_read_resource_byname(dev, "cgu0", &res);
+ if (ret)
+ return ret;
+ cgu0 = devm_ioremap(dev, res.start, resource_size(&res));
+
+ ret = dev_read_resource_byname(dev, "cgu1", &res);
+ if (ret)
+ return ret;
+ cgu1 = devm_ioremap(dev, res.start, resource_size(&res));
+
+ ret = dev_read_resource_byname(dev, "cdu", &res);
+ if (ret)
+ return ret;
+ cdu = devm_ioremap(dev, res.start, resource_size(&res));
+
+ // Input clock configuration
+ clk_get_by_name(dev, "dummy", &dummy);
+ clk_get_by_name(dev, "sys_clkin0", &clkin0);
+ clk_get_by_name(dev, "sys_clkin1", &clkin1);
+
+ clks[ADSP_SC57X_CLK_DUMMY] = &dummy;
+ clks[ADSP_SC57X_CLK_SYS_CLKIN0] = &clkin0;
+ clks[ADSP_SC57X_CLK_SYS_CLKIN1] = &clkin1;
+
+ clks[ADSP_SC57X_CLK_CGU1_IN] = clk_register_mux(NULL, "cgu1_in_sel", cgu1_in_sels,
+ 2, CLK_SET_RATE_PARENT,
+ cdu + CDU_CLKINSEL, 0, 1, 0);
+
+ // CGU configuration and internal clocks
+ clks[ADSP_SC57X_CLK_CGU0_PLL_IN] = clk_register_divider(NULL, "cgu0_df",
+ "sys_clkin0",
+ CLK_SET_RATE_PARENT,
+ cgu0 + CGU_CTL, 0, 1, 0);
+ clks[ADSP_SC57X_CLK_CGU1_PLL_IN] = clk_register_divider(NULL, "cgu1_df",
+ "cgu1_in_sel",
+ CLK_SET_RATE_PARENT,
+ cgu1 + CGU_CTL, 0, 1, 0);
+
+ // VCO output == PLL output
+ clks[ADSP_SC57X_CLK_CGU0_PLLCLK] = sc5xx_cgu_pll("cgu0_pllclk", "cgu0_df",
+ cgu0 + CGU_CTL, CGU_MSEL_SHIFT,
+ CGU_MSEL_WIDTH, 0, false);
+ clks[ADSP_SC57X_CLK_CGU1_PLLCLK] = sc5xx_cgu_pll("cgu1_pllclk", "cgu1_df",
+ cgu1 + CGU_CTL, CGU_MSEL_SHIFT,
+ CGU_MSEL_WIDTH, 0, false);
+
+ // Dividers from pll output
+ clks[ADSP_SC57X_CLK_CGU0_CDIV] = cgu_divider("cgu0_cdiv", "cgu0_pllclk",
+ cgu0 + CGU_DIV, 0, 5, 0);
+ clks[ADSP_SC57X_CLK_CGU0_SYSCLK] = cgu_divider("sysclk_0", "cgu0_pllclk",
+ cgu0 + CGU_DIV, 8, 5, 0);
+ clks[ADSP_SC57X_CLK_CGU0_DDIV] = cgu_divider("cgu0_ddiv", "cgu0_pllclk",
+ cgu0 + CGU_DIV, 16, 5, 0);
+ clks[ADSP_SC57X_CLK_CGU0_ODIV] = cgu_divider("cgu0_odiv", "cgu0_pllclk",
+ cgu0 + CGU_DIV, 22, 7, 0);
+ clks[ADSP_SC57X_CLK_CGU0_S0SELDIV] = cgu_divider("cgu0_s0seldiv", "sysclk_0",
+ cgu0 + CGU_DIV, 5, 3, 0);
+ clks[ADSP_SC57X_CLK_CGU0_S1SELDIV] = cgu_divider("cgu0_s1seldiv", "sysclk_0",
+ cgu0 + CGU_DIV, 13, 3, 0);
+
+ clks[ADSP_SC57X_CLK_CGU1_CDIV] = cgu_divider("cgu1_cdiv", "cgu1_pllclk",
+ cgu1 + CGU_DIV, 0, 5, 0);
+ clks[ADSP_SC57X_CLK_CGU1_SYSCLK] = cgu_divider("sysclk_1", "cgu1_pllclk",
+ cgu1 + CGU_DIV, 8, 5, 0);
+ clks[ADSP_SC57X_CLK_CGU1_DDIV] = cgu_divider("cgu1_ddiv", "cgu1_pllclk",
+ cgu1 + CGU_DIV, 16, 5, 0);
+ clks[ADSP_SC57X_CLK_CGU1_ODIV] = cgu_divider("cgu1_odiv", "cgu1_pllclk",
+ cgu1 + CGU_DIV, 22, 7, 0);
+ clks[ADSP_SC57X_CLK_CGU1_S0SELDIV] = cgu_divider("cgu1_s0seldiv",
+ "sysclk_1", cgu1 + CGU_DIV, 5,
+ 3, 0);
+ clks[ADSP_SC57X_CLK_CGU1_S1SELDIV] = cgu_divider("cgu1_s1seldiv",
+ "sysclk_1", cgu1 + CGU_DIV, 13,
+ 3, 0);
+
+ // Gates to enable CGU outputs
+ clks[ADSP_SC57X_CLK_CGU0_CCLK0] = cgu_gate("cclk0_0", "cgu0_cdiv",
+ cgu0 + CGU_CCBF_DIS, 0);
+ clks[ADSP_SC57X_CLK_CGU0_CCLK1] = cgu_gate("cclk1_0", "cgu0_cdiv",
+ cgu1 + CGU_CCBF_DIS, 1);
+ clks[ADSP_SC57X_CLK_CGU0_OCLK] = cgu_gate("oclk_0", "cgu0_odiv",
+ cgu0 + CGU_SCBF_DIS, 3);
+ clks[ADSP_SC57X_CLK_CGU0_DCLK] = cgu_gate("dclk_0", "cgu0_ddiv",
+ cgu0 + CGU_SCBF_DIS, 2);
+ clks[ADSP_SC57X_CLK_CGU0_SCLK1] = cgu_gate("sclk1_0", "cgu0_s1seldiv",
+ cgu0 + CGU_SCBF_DIS, 1);
+ clks[ADSP_SC57X_CLK_CGU0_SCLK0] = cgu_gate("sclk0_0", "cgu0_s0seldiv",
+ cgu0 + CGU_SCBF_DIS, 0);
+
+ clks[ADSP_SC57X_CLK_CGU1_CCLK0] = cgu_gate("cclk0_1", "cgu1_cdiv",
+ cgu1 + CGU_CCBF_DIS, 0);
+ clks[ADSP_SC57X_CLK_CGU1_CCLK1] = cgu_gate("cclk1_1", "cgu1_cdiv",
+ cgu1 + CGU_CCBF_DIS, 1);
+ clks[ADSP_SC57X_CLK_CGU1_OCLK] = cgu_gate("oclk_1", "cgu1_odiv",
+ cgu1 + CGU_SCBF_DIS, 3);
+ clks[ADSP_SC57X_CLK_CGU1_DCLK] = cgu_gate("dclk_1", "cgu1_ddiv",
+ cgu1 + CGU_SCBF_DIS, 2);
+ clks[ADSP_SC57X_CLK_CGU1_SCLK1] = cgu_gate("sclk1_1", "cgu1_s1seldiv",
+ cgu1 + CGU_SCBF_DIS, 1);
+ clks[ADSP_SC57X_CLK_CGU1_SCLK0] = cgu_gate("sclk0_1", "cgu1_s0seldiv",
+ cgu1 + CGU_SCBF_DIS, 0);
+
+ // Extra half rate clocks generated in the CDU
+ clks[ADSP_SC57X_CLK_OCLK0_HALF] = clk_register_fixed_factor(NULL, "oclk_0_half",
+ "oclk_0",
+ CLK_SET_RATE_PARENT,
+ 1, 2);
+ clks[ADSP_SC57X_CLK_CCLK1_1_HALF] = clk_register_fixed_factor(NULL,
+ "cclk1_1_half",
+ "cclk1_1",
+ CLK_SET_RATE_PARENT,
+ 1, 2);
+
+ // CDU output muxes
+ clks[ADSP_SC57X_CLK_SHARC0_SEL] = cdu_mux("sharc0_sel", cdu + CDU_CFG0,
+ sharc0_sels);
+ clks[ADSP_SC57X_CLK_SHARC1_SEL] = cdu_mux("sharc1_sel", cdu + CDU_CFG1,
+ sharc1_sels);
+ clks[ADSP_SC57X_CLK_ARM_SEL] = cdu_mux("arm_sel", cdu + CDU_CFG2, arm_sels);
+ clks[ADSP_SC57X_CLK_CDU_DDR_SEL] = cdu_mux("cdu_ddr_sel", cdu + CDU_CFG3,
+ cdu_ddr_sels);
+ clks[ADSP_SC57X_CLK_CAN_SEL] = cdu_mux("can_sel", cdu + CDU_CFG4, can_sels);
+ clks[ADSP_SC57X_CLK_SPDIF_SEL] = cdu_mux("spdif_sel", cdu + CDU_CFG5, spdif_sels);
+ clks[ADSP_SC57X_CLK_GIGE_SEL] = cdu_mux("gige_sel", cdu + CDU_CFG7, gige_sels);
+ clks[ADSP_SC57X_CLK_SDIO_SEL] = cdu_mux("sdio_sel", cdu + CDU_CFG9, sdio_sels);
+
+ // CDU output enable gates
+ clks[ADSP_SC57X_CLK_SHARC0] = cdu_gate("sharc0", "sharc0_sel", cdu + CDU_CFG0,
+ CLK_IS_CRITICAL);
+ clks[ADSP_SC57X_CLK_SHARC1] = cdu_gate("sharc1", "sharc1_sel", cdu + CDU_CFG1,
+ CLK_IS_CRITICAL);
+ clks[ADSP_SC57X_CLK_ARM] = cdu_gate("arm", "arm_sel", cdu + CDU_CFG2,
+ CLK_IS_CRITICAL);
+ clks[ADSP_SC57X_CLK_CDU_DDR] = cdu_gate("cdu_ddr", "cdu_ddr_sel", cdu + CDU_CFG3,
+ CLK_IS_CRITICAL);
+ clks[ADSP_SC57X_CLK_CAN] = cdu_gate("can", "can_sel", cdu + CDU_CFG4, 0);
+ clks[ADSP_SC57X_CLK_SPDIF] = cdu_gate("spdif", "spdif_sel", cdu + CDU_CFG5, 0);
+ clks[ADSP_SC57X_CLK_GIGE] = cdu_gate("gige", "gige_sel", cdu + CDU_CFG7, 0);
+ clks[ADSP_SC57X_CLK_SDIO] = cdu_gate("sdio", "sdio_sel", cdu + CDU_CFG9, 0);
+
+ ret = cdu_check_clocks(clks, ARRAY_SIZE(clks));
+ if (ret)
+ pr_err("CDU error detected\n");
+
+ return ret;
+}
+
+static const struct udevice_id adi_sc57x_clk_ids[] = {
+ { .compatible = "adi,sc57x-clocks" },
+ { },
+};
+
+U_BOOT_DRIVER(adi_sc57x_clk) = {
+ .name = "clk_adi_sc57x",
+ .id = UCLASS_CLK,
+ .of_match = adi_sc57x_clk_ids,
+ .ops = &adi_clk_ops,
+ .probe = sc57x_clock_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/adi/clk-adi-sc58x.c b/drivers/clk/adi/clk-adi-sc58x.c
new file mode 100644
index 0000000..05a0fed
--- /dev/null
+++ b/drivers/clk/adi/clk-adi-sc58x.c
@@ -0,0 +1,222 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Author: Greg Malysa <greg.malysa@timesys.com>
+ *
+ * Ported from Linux: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ */
+
+#include <clk.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dt-bindings/clock/adi-sc5xx-clock.h>
+#include <linux/compiler_types.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/printk.h>
+#include <linux/types.h>
+
+#include "clk.h"
+
+static const char * const cgu1_in_sels[] = {"sys_clkin0", "sys_clkin1"};
+static const char * const sharc0_sels[] = {"cclk0_0", "sysclk_0", "dummy", "dummy"};
+static const char * const sharc1_sels[] = {"cclk0_0", "sysclk_0", "dummy", "dummy"};
+static const char * const arm_sels[] = {"cclk1_0", "sysclk_0", "dummy", "dummy"};
+static const char * const cdu_ddr_sels[] = {"dclk_0", "dclk_1", "dummy", "dummy"};
+static const char * const can_sels[] = {"oclk_0", "oclk_1", "dclk_1", "dummy"};
+static const char * const spdif_sels[] = {"oclk_0", "oclk_1", "dclk_1", "dclk_0"};
+static const char * const reserved_sels[] = {"sclk0_0", "oclk_0", "dummy", "dummy"};
+static const char * const gige_sels[] = {"sclk0_0", "sclk1_1", "cclk0_1", "oclk_0"};
+static const char * const lp_sels[] = {"sclk0_0", "sclk0_1", "cclk1_1", "dclk_1"};
+static const char * const sdio_sels[] = {"oclk_0_half", "cclk1_1_half", "cclk1_1",
+ "dclk_1"};
+
+static int sc58x_clock_probe(struct udevice *dev)
+{
+ void __iomem *cgu0;
+ void __iomem *cgu1;
+ void __iomem *cdu;
+ int ret;
+ struct resource res;
+
+ struct clk *clks[ADSP_SC58X_CLK_END];
+ struct clk dummy, clkin0, clkin1;
+
+ ret = dev_read_resource_byname(dev, "cgu0", &res);
+ if (ret)
+ return ret;
+ cgu0 = devm_ioremap(dev, res.start, resource_size(&res));
+
+ ret = dev_read_resource_byname(dev, "cgu1", &res);
+ if (ret)
+ return ret;
+ cgu1 = devm_ioremap(dev, res.start, resource_size(&res));
+
+ ret = dev_read_resource_byname(dev, "cdu", &res);
+ if (ret)
+ return ret;
+ cdu = devm_ioremap(dev, res.start, resource_size(&res));
+
+ // Input clock configuration
+ clk_get_by_name(dev, "dummy", &dummy);
+ clk_get_by_name(dev, "sys_clkin0", &clkin0);
+ clk_get_by_name(dev, "sys_clkin1", &clkin1);
+
+ clks[ADSP_SC58X_CLK_DUMMY] = &dummy;
+ clks[ADSP_SC58X_CLK_SYS_CLKIN0] = &clkin0;
+ clks[ADSP_SC58X_CLK_SYS_CLKIN1] = &clkin1;
+
+ clks[ADSP_SC58X_CLK_CGU1_IN] = clk_register_mux(NULL, "cgu1_in_sel", cgu1_in_sels,
+ 2, CLK_SET_RATE_PARENT,
+ cdu + CDU_CLKINSEL, 0, 1, 0);
+
+ // CGU configuration and internal clocks
+ clks[ADSP_SC58X_CLK_CGU0_PLL_IN] = clk_register_divider(NULL, "cgu0_df",
+ "sys_clkin0",
+ CLK_SET_RATE_PARENT,
+ cgu0 + CGU_CTL, 0, 1, 0);
+ clks[ADSP_SC58X_CLK_CGU1_PLL_IN] = clk_register_divider(NULL, "cgu1_df",
+ "cgu1_in_sel",
+ CLK_SET_RATE_PARENT,
+ cgu1 + CGU_CTL, 0, 1, 0);
+
+ // VCO output inside PLL
+ clks[ADSP_SC58X_CLK_CGU0_VCO_OUT] = sc5xx_cgu_pll("cgu0_vco", "cgu0_df",
+ cgu0 + CGU_CTL, CGU_MSEL_SHIFT,
+ CGU_MSEL_WIDTH, 0, false);
+ clks[ADSP_SC58X_CLK_CGU1_VCO_OUT] = sc5xx_cgu_pll("cgu1_vco", "cgu1_df",
+ cgu1 + CGU_CTL, CGU_MSEL_SHIFT,
+ CGU_MSEL_WIDTH, 0, false);
+
+ // Final PLL output
+ clks[ADSP_SC58X_CLK_CGU0_PLLCLK] = clk_register_fixed_factor(NULL, "cgu0_pllclk",
+ "cgu0_vco",
+ CLK_SET_RATE_PARENT,
+ 1, 1);
+ clks[ADSP_SC58X_CLK_CGU1_PLLCLK] = clk_register_fixed_factor(NULL, "cgu1_pllclk",
+ "cgu1_vco",
+ CLK_SET_RATE_PARENT,
+ 1, 1);
+
+ // Dividers from pll output
+ clks[ADSP_SC58X_CLK_CGU0_CDIV] = cgu_divider("cgu0_cdiv", "cgu0_pllclk",
+ cgu0 + CGU_DIV, 0, 5, 0);
+ clks[ADSP_SC58X_CLK_CGU0_SYSCLK] = cgu_divider("sysclk_0", "cgu0_pllclk",
+ cgu0 + CGU_DIV, 8, 5, 0);
+ clks[ADSP_SC58X_CLK_CGU0_DDIV] = cgu_divider("cgu0_ddiv", "cgu0_pllclk",
+ cgu0 + CGU_DIV, 16, 5, 0);
+ clks[ADSP_SC58X_CLK_CGU0_ODIV] = cgu_divider("cgu0_odiv", "cgu0_pllclk",
+ cgu0 + CGU_DIV, 22, 7, 0);
+ clks[ADSP_SC58X_CLK_CGU0_S0SELDIV] = cgu_divider("cgu0_s0seldiv", "sysclk_0",
+ cgu0 + CGU_DIV, 5, 3, 0);
+ clks[ADSP_SC58X_CLK_CGU0_S1SELDIV] = cgu_divider("cgu0_s1seldiv", "sysclk_0",
+ cgu0 + CGU_DIV, 13, 3, 0);
+
+ clks[ADSP_SC58X_CLK_CGU1_CDIV] = cgu_divider("cgu1_cdiv", "cgu1_pllclk",
+ cgu1 + CGU_DIV, 0, 5, 0);
+ clks[ADSP_SC58X_CLK_CGU1_SYSCLK] = cgu_divider("sysclk_1", "cgu1_pllclk",
+ cgu1 + CGU_DIV, 8, 5, 0);
+ clks[ADSP_SC58X_CLK_CGU1_DDIV] = cgu_divider("cgu1_ddiv", "cgu1_pllclk",
+ cgu1 + CGU_DIV, 16, 5, 0);
+ clks[ADSP_SC58X_CLK_CGU1_ODIV] = cgu_divider("cgu1_odiv", "cgu1_pllclk",
+ cgu1 + CGU_DIV, 22, 7, 0);
+ clks[ADSP_SC58X_CLK_CGU1_S0SELDIV] = cgu_divider("cgu1_s0seldiv", "sysclk_1",
+ cgu1 + CGU_DIV, 5, 3, 0);
+ clks[ADSP_SC58X_CLK_CGU1_S1SELDIV] = cgu_divider("cgu1_s1seldiv", "sysclk_1",
+ cgu1 + CGU_DIV, 13, 3, 0);
+
+ // Gates to enable CGU outputs
+ clks[ADSP_SC58X_CLK_CGU0_CCLK0] = cgu_gate("cclk0_0", "cgu0_cdiv",
+ cgu0 + CGU_CCBF_DIS, 0);
+ clks[ADSP_SC58X_CLK_CGU0_CCLK1] = cgu_gate("cclk1_0", "cgu0_cdiv",
+ cgu1 + CGU_CCBF_DIS, 1);
+ clks[ADSP_SC58X_CLK_CGU0_OCLK] = cgu_gate("oclk_0", "cgu0_odiv",
+ cgu0 + CGU_SCBF_DIS, 3);
+ clks[ADSP_SC58X_CLK_CGU0_DCLK] = cgu_gate("dclk_0", "cgu0_ddiv",
+ cgu0 + CGU_SCBF_DIS, 2);
+ clks[ADSP_SC58X_CLK_CGU0_SCLK1] = cgu_gate("sclk1_0", "cgu0_s1seldiv",
+ cgu0 + CGU_SCBF_DIS, 1);
+ clks[ADSP_SC58X_CLK_CGU0_SCLK0] = cgu_gate("sclk0_0", "cgu0_s0seldiv",
+ cgu0 + CGU_SCBF_DIS, 0);
+
+ clks[ADSP_SC58X_CLK_CGU1_CCLK0] = cgu_gate("cclk0_1", "cgu1_cdiv",
+ cgu1 + CGU_CCBF_DIS, 0);
+ clks[ADSP_SC58X_CLK_CGU1_CCLK1] = cgu_gate("cclk1_1", "cgu1_cdiv",
+ cgu1 + CGU_CCBF_DIS, 1);
+ clks[ADSP_SC58X_CLK_CGU1_OCLK] = cgu_gate("oclk_1", "cgu1_odiv",
+ cgu1 + CGU_SCBF_DIS, 3);
+ clks[ADSP_SC58X_CLK_CGU1_DCLK] = cgu_gate("dclk_1", "cgu1_ddiv",
+ cgu1 + CGU_SCBF_DIS, 2);
+ clks[ADSP_SC58X_CLK_CGU1_SCLK1] = cgu_gate("sclk1_1", "cgu1_s1seldiv",
+ cgu1 + CGU_SCBF_DIS, 1);
+ clks[ADSP_SC58X_CLK_CGU1_SCLK0] = cgu_gate("sclk0_1", "cgu1_s0seldiv",
+ cgu1 + CGU_SCBF_DIS, 0);
+
+ // Extra half rate clocks generated in the CDU
+ clks[ADSP_SC58X_CLK_OCLK0_HALF] = clk_register_fixed_factor(NULL, "oclk_0_half",
+ "oclk_0",
+ CLK_SET_RATE_PARENT,
+ 1, 2);
+ clks[ADSP_SC58X_CLK_CCLK1_1_HALF] = clk_register_fixed_factor(NULL,
+ "cclk1_1_half",
+ "cclk1_1",
+ CLK_SET_RATE_PARENT,
+ 1, 2);
+
+ // CDU output muxes
+ clks[ADSP_SC58X_CLK_SHARC0_SEL] = cdu_mux("sharc0_sel", cdu + CDU_CFG0,
+ sharc0_sels);
+ clks[ADSP_SC58X_CLK_SHARC1_SEL] = cdu_mux("sharc1_sel", cdu + CDU_CFG1,
+ sharc1_sels);
+ clks[ADSP_SC58X_CLK_ARM_SEL] = cdu_mux("arm_sel", cdu + CDU_CFG2, arm_sels);
+ clks[ADSP_SC58X_CLK_CDU_DDR_SEL] = cdu_mux("cdu_ddr_sel", cdu + CDU_CFG3,
+ cdu_ddr_sels);
+ clks[ADSP_SC58X_CLK_CAN_SEL] = cdu_mux("can_sel", cdu + CDU_CFG4, can_sels);
+ clks[ADSP_SC58X_CLK_SPDIF_SEL] = cdu_mux("spdif_sel", cdu + CDU_CFG5, spdif_sels);
+ clks[ADSP_SC58X_CLK_RESERVED_SEL] = cdu_mux("reserved_sel", cdu + CDU_CFG6,
+ reserved_sels);
+ clks[ADSP_SC58X_CLK_GIGE_SEL] = cdu_mux("gige_sel", cdu + CDU_CFG7, gige_sels);
+ clks[ADSP_SC58X_CLK_LP_SEL] = cdu_mux("lp_sel", cdu + CDU_CFG8, lp_sels);
+ clks[ADSP_SC58X_CLK_SDIO_SEL] = cdu_mux("sdio_sel", cdu + CDU_CFG9, sdio_sels);
+
+ // CDU output enable gates
+ clks[ADSP_SC58X_CLK_SHARC0] = cdu_gate("sharc0", "sharc0_sel", cdu + CDU_CFG0,
+ CLK_IS_CRITICAL);
+ clks[ADSP_SC58X_CLK_SHARC1] = cdu_gate("sharc1", "sharc1_sel", cdu + CDU_CFG1,
+ CLK_IS_CRITICAL);
+ clks[ADSP_SC58X_CLK_ARM] = cdu_gate("arm", "arm_sel", cdu + CDU_CFG2,
+ CLK_IS_CRITICAL);
+ clks[ADSP_SC58X_CLK_CDU_DDR] = cdu_gate("cdu_ddr", "cdu_ddr_sel", cdu + CDU_CFG3,
+ CLK_IS_CRITICAL);
+ clks[ADSP_SC58X_CLK_CAN] = cdu_gate("can", "can_sel", cdu + CDU_CFG4, 0);
+ clks[ADSP_SC58X_CLK_SPDIF] = cdu_gate("spdif", "spdif_sel", cdu + CDU_CFG5, 0);
+ clks[ADSP_SC58X_CLK_RESERVED] = cdu_gate("reserved", "reserved_sel",
+ cdu + CDU_CFG6, 0);
+ clks[ADSP_SC58X_CLK_GIGE] = cdu_gate("gige", "gige_sel", cdu + CDU_CFG7, 0);
+ clks[ADSP_SC58X_CLK_LP] = cdu_gate("lp", "lp_sel", cdu + CDU_CFG8, 0);
+ clks[ADSP_SC58X_CLK_SDIO] = cdu_gate("sdio", "sdio_sel", cdu + CDU_CFG9, 0);
+
+ ret = cdu_check_clocks(clks, ARRAY_SIZE(clks));
+ if (ret)
+ pr_err("CDU error detected\n");
+
+ return ret;
+}
+
+static const struct udevice_id adi_sc58x_clk_ids[] = {
+ { .compatible = "adi,sc58x-clocks" },
+ { },
+};
+
+U_BOOT_DRIVER(adi_sc58x_clk) = {
+ .name = "clk_adi_sc58x",
+ .id = UCLASS_CLK,
+ .of_match = adi_sc58x_clk_ids,
+ .ops = &adi_clk_ops,
+ .probe = sc58x_clock_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/adi/clk-adi-sc594.c b/drivers/clk/adi/clk-adi-sc594.c
new file mode 100644
index 0000000..c80bbf9
--- /dev/null
+++ b/drivers/clk/adi/clk-adi-sc594.c
@@ -0,0 +1,231 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Author: Greg Malysa <greg.malysa@timesys.com>
+ *
+ * Ported from Linux: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ */
+
+#include <clk.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dt-bindings/clock/adi-sc5xx-clock.h>
+#include <linux/compiler_types.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/printk.h>
+#include <linux/types.h>
+
+#include "clk.h"
+
+static const char * const cgu1_in_sels[] = {"sys_clkin0", "sys_clkin1"};
+static const char * const cgu0_s1sels[] = {"cgu0_s1seldiv", "cgu0_s1selexdiv"};
+static const char * const cgu1_s1sels[] = {"cgu1_s1seldiv", "cgu1_s1selexdiv"};
+static const char * const sharc0_sels[] = {"cclk0_0", "dummy", "dummy", "dummy"};
+static const char * const sharc1_sels[] = {"cclk0_0", "dummy", "dummy", "dummy"};
+static const char * const arm_sels[] = {"cclk1_0", "dummy", "dummy", "dummy"};
+static const char * const cdu_ddr_sels[] = {"dclk_0", "dclk_1", "dummy", "dummy"};
+static const char * const can_sels[] = {"oclk_0", "oclk_1", "dummy", "dummy"};
+static const char * const spdif_sels[] = {"sclk1_0", "dummy", "dummy", "dummy"};
+static const char * const spi_sels[] = {"sclk0_0", "oclk_0", "dummy", "dummy"};
+static const char * const gige_sels[] = {"sclk0_0", "sclk0_1", "cclk0_1", "dummy"};
+static const char * const lp_sels[] = {"oclk_0", "sclk0_0", "cclk0_1", "dummy"};
+static const char * const lpddr_sels[] = {"oclk_0", "dclk_0", "sysclkin_1", "dummy"};
+static const char * const ospi_sels[] = {"sysclk_0", "sclk0_0", "sclk1_1", "dummy"};
+static const char * const trace_sels[] = {"sclk0_0", "dummy", "dummy", "dummy"};
+
+static int sc594_clock_probe(struct udevice *dev)
+{
+ void __iomem *cgu0;
+ void __iomem *cgu1;
+ void __iomem *cdu;
+ int ret;
+ struct resource res;
+
+ struct clk *clks[ADSP_SC594_CLK_END];
+ struct clk dummy, clkin0, clkin1;
+
+ ret = dev_read_resource_byname(dev, "cgu0", &res);
+ if (ret)
+ return ret;
+ cgu0 = devm_ioremap(dev, res.start, resource_size(&res));
+
+ ret = dev_read_resource_byname(dev, "cgu1", &res);
+ if (ret)
+ return ret;
+ cgu1 = devm_ioremap(dev, res.start, resource_size(&res));
+
+ ret = dev_read_resource_byname(dev, "cdu", &res);
+ if (ret)
+ return ret;
+ cdu = devm_ioremap(dev, res.start, resource_size(&res));
+
+ // Input clock configuration
+ clk_get_by_name(dev, "dummy", &dummy);
+ clk_get_by_name(dev, "sys_clkin0", &clkin0);
+ clk_get_by_name(dev, "sys_clkin1", &clkin1);
+
+ clks[ADSP_SC594_CLK_DUMMY] = &dummy;
+ clks[ADSP_SC594_CLK_SYS_CLKIN0] = &clkin0;
+ clks[ADSP_SC594_CLK_SYS_CLKIN1] = &clkin1;
+ clks[ADSP_SC594_CLK_CGU1_IN] = clk_register_mux(NULL, "cgu1_in_sel", cgu1_in_sels,
+ 2, CLK_SET_RATE_PARENT,
+ cdu + CDU_CLKINSEL, 0, 1, 0);
+
+ // CGU configuration and internal clocks
+ clks[ADSP_SC594_CLK_CGU0_PLL_IN] = clk_register_divider(NULL, "cgu0_df",
+ "sys_clkin0",
+ CLK_SET_RATE_PARENT,
+ cgu0 + CGU_CTL, 0, 1, 0);
+ clks[ADSP_SC594_CLK_CGU1_PLL_IN] = clk_register_divider(NULL, "cgu1_df",
+ "cgu1_in_sel",
+ CLK_SET_RATE_PARENT,
+ cgu1 + CGU_CTL, 0, 1, 0);
+
+ // VCO output inside PLL
+ clks[ADSP_SC594_CLK_CGU0_VCO_OUT] = sc5xx_cgu_pll("cgu0_vco", "cgu0_df",
+ cgu0 + CGU_CTL, CGU_MSEL_SHIFT,
+ CGU_MSEL_WIDTH, 0, false);
+ clks[ADSP_SC594_CLK_CGU1_VCO_OUT] = sc5xx_cgu_pll("cgu1_vco", "cgu1_df",
+ cgu1 + CGU_CTL, CGU_MSEL_SHIFT,
+ CGU_MSEL_WIDTH, 0, false);
+
+ // Final PLL output
+ clks[ADSP_SC594_CLK_CGU0_PLLCLK] = clk_register_fixed_factor(NULL, "cgu0_pllclk",
+ "cgu0_vco",
+ CLK_SET_RATE_PARENT,
+ 1, 1);
+ clks[ADSP_SC594_CLK_CGU1_PLLCLK] = clk_register_fixed_factor(NULL, "cgu1_pllclk",
+ "cgu1_vco",
+ CLK_SET_RATE_PARENT,
+ 1, 1);
+
+ // Dividers from pll output
+ clks[ADSP_SC594_CLK_CGU0_CDIV] = cgu_divider("cgu0_cdiv", "cgu0_pllclk",
+ cgu0 + CGU_DIV, 0, 5, 0);
+ clks[ADSP_SC594_CLK_CGU0_SYSCLK] = cgu_divider("sysclk_0", "cgu0_pllclk",
+ cgu0 + CGU_DIV, 8, 5, 0);
+ clks[ADSP_SC594_CLK_CGU0_DDIV] = cgu_divider("cgu0_ddiv", "cgu0_pllclk",
+ cgu0 + CGU_DIV, 16, 5, 0);
+ clks[ADSP_SC594_CLK_CGU0_ODIV] = cgu_divider("cgu0_odiv", "cgu0_pllclk",
+ cgu0 + CGU_DIV, 22, 7, 0);
+ clks[ADSP_SC594_CLK_CGU0_S0SELDIV] = cgu_divider("cgu0_s0seldiv", "sysclk_0",
+ cgu0 + CGU_DIV, 5, 3, 0);
+ clks[ADSP_SC594_CLK_CGU0_S1SELDIV] = cgu_divider("cgu0_s1seldiv", "sysclk_0",
+ cgu0 + CGU_DIV, 13, 3, 0);
+ clks[ADSP_SC594_CLK_CGU0_S1SELEXDIV] = cgu_divider("cgu0_s1selexdiv",
+ "cgu0_pllclk",
+ cgu0 + CGU_DIVEX, 16, 8, 0);
+ clks[ADSP_SC594_CLK_CGU0_S1SEL] = clk_register_mux(NULL, "cgu0_sclk1sel",
+ cgu0_s1sels, 2,
+ CLK_SET_RATE_PARENT,
+ cgu0 + CGU_CTL, 17, 1, 0);
+
+ clks[ADSP_SC594_CLK_CGU1_CDIV] = cgu_divider("cgu1_cdiv", "cgu1_pllclk",
+ cgu1 + CGU_DIV, 0, 5, 0);
+ clks[ADSP_SC594_CLK_CGU1_SYSCLK] = cgu_divider("sysclk_1", "cgu1_pllclk",
+ cgu1 + CGU_DIV, 8, 5, 0);
+ clks[ADSP_SC594_CLK_CGU1_DDIV] = cgu_divider("cgu1_ddiv", "cgu1_pllclk",
+ cgu1 + CGU_DIV, 16, 5, 0);
+ clks[ADSP_SC594_CLK_CGU1_ODIV] = cgu_divider("cgu1_odiv", "cgu1_pllclk",
+ cgu1 + CGU_DIV, 22, 7, 0);
+ clks[ADSP_SC594_CLK_CGU1_S0SELDIV] = cgu_divider("cgu1_s0seldiv", "sysclk_1",
+ cgu1 + CGU_DIV, 5, 3, 0);
+ clks[ADSP_SC594_CLK_CGU1_S1SELDIV] = cgu_divider("cgu1_s1seldiv", "sysclk_1",
+ cgu1 + CGU_DIV, 13, 3, 0);
+ clks[ADSP_SC594_CLK_CGU1_S1SELEXDIV] = cgu_divider("cgu1_s1selexdiv",
+ "cgu1_pllclk",
+ cgu1 + CGU_DIVEX, 16, 8, 0);
+ clks[ADSP_SC594_CLK_CGU1_S1SEL] = clk_register_mux(NULL, "cgu1_sclk1sel",
+ cgu1_s1sels, 2,
+ CLK_SET_RATE_PARENT,
+ cgu1 + CGU_CTL, 17, 1, 0);
+
+ // Gates to enable CGU outputs
+ clks[ADSP_SC594_CLK_CGU0_CCLK0] = cgu_gate("cclk0_0", "cgu0_cdiv",
+ cgu0 + CGU_CCBF_DIS, 0);
+ clks[ADSP_SC594_CLK_CGU0_CCLK1] = cgu_gate("cclk1_0", "cgu0_cdiv",
+ cgu1 + CGU_CCBF_DIS, 1);
+ clks[ADSP_SC594_CLK_CGU0_OCLK] = cgu_gate("oclk_0", "cgu0_odiv",
+ cgu0 + CGU_SCBF_DIS, 3);
+ clks[ADSP_SC594_CLK_CGU0_DCLK] = cgu_gate("dclk_0", "cgu0_ddiv",
+ cgu0 + CGU_SCBF_DIS, 2);
+ clks[ADSP_SC594_CLK_CGU0_SCLK1] = cgu_gate("sclk1_0", "cgu0_sclk1sel",
+ cgu0 + CGU_SCBF_DIS, 1);
+ clks[ADSP_SC594_CLK_CGU0_SCLK0] = cgu_gate("sclk0_0", "cgu0_s0seldiv",
+ cgu0 + CGU_SCBF_DIS, 0);
+
+ clks[ADSP_SC594_CLK_CGU1_CCLK0] = cgu_gate("cclk0_1", "cgu1_cdiv",
+ cgu1 + CGU_CCBF_DIS, 0);
+ clks[ADSP_SC594_CLK_CGU1_CCLK1] = cgu_gate("cclk1_1", "cgu1_cdiv",
+ cgu1 + CGU_CCBF_DIS, 1);
+ clks[ADSP_SC594_CLK_CGU1_OCLK] = cgu_gate("oclk_1", "cgu1_odiv",
+ cgu1 + CGU_SCBF_DIS, 3);
+ clks[ADSP_SC594_CLK_CGU1_DCLK] = cgu_gate("dclk_1", "cgu1_ddiv",
+ cgu1 + CGU_SCBF_DIS, 2);
+ clks[ADSP_SC594_CLK_CGU1_SCLK1] = cgu_gate("sclk1_1", "cgu1_sclk1sel",
+ cgu1 + CGU_SCBF_DIS, 1);
+ clks[ADSP_SC594_CLK_CGU1_SCLK0] = cgu_gate("sclk0_1", "cgu1_s0seldiv",
+ cgu1 + CGU_SCBF_DIS, 0);
+
+ // CDU output muxes
+ clks[ADSP_SC594_CLK_SHARC0_SEL] = cdu_mux("sharc0_sel", cdu + CDU_CFG0,
+ sharc0_sels);
+ clks[ADSP_SC594_CLK_SHARC1_SEL] = cdu_mux("sharc1_sel", cdu + CDU_CFG1,
+ sharc1_sels);
+ clks[ADSP_SC594_CLK_ARM_SEL] = cdu_mux("arm_sel", cdu + CDU_CFG2, arm_sels);
+ clks[ADSP_SC594_CLK_CDU_DDR_SEL] = cdu_mux("cdu_ddr_sel", cdu + CDU_CFG3,
+ cdu_ddr_sels);
+ clks[ADSP_SC594_CLK_CAN_SEL] = cdu_mux("can_sel", cdu + CDU_CFG4, can_sels);
+ clks[ADSP_SC594_CLK_SPDIF_SEL] = cdu_mux("spdif_sel", cdu + CDU_CFG5, spdif_sels);
+ clks[ADSP_SC594_CLK_RESERVED_SEL] = cdu_mux("spi_sel", cdu + CDU_CFG6, spi_sels);
+ clks[ADSP_SC594_CLK_GIGE_SEL] = cdu_mux("gige_sel", cdu + CDU_CFG7, gige_sels);
+ clks[ADSP_SC594_CLK_LP_SEL] = cdu_mux("lp_sel", cdu + CDU_CFG8, lp_sels);
+ clks[ADSP_SC594_CLK_LPDDR_SEL] = cdu_mux("lpddr_sel", cdu + CDU_CFG9, lpddr_sels);
+ clks[ADSP_SC594_CLK_OSPI_SEL] = cdu_mux("ospi_sel", cdu + CDU_CFG10,
+ ospi_sels);
+ clks[ADSP_SC594_CLK_TRACE_SEL] = cdu_mux("trace_sel", cdu + CDU_CFG12,
+ trace_sels);
+
+ // CDU output enable gates
+ clks[ADSP_SC594_CLK_SHARC0] = cdu_gate("sharc0", "sharc0_sel",
+ cdu + CDU_CFG0, CLK_IS_CRITICAL);
+ clks[ADSP_SC594_CLK_SHARC1] = cdu_gate("sharc1", "sharc1_sel",
+ cdu + CDU_CFG1, CLK_IS_CRITICAL);
+ clks[ADSP_SC594_CLK_ARM] = cdu_gate("arm", "arm_sel", cdu + CDU_CFG2,
+ CLK_IS_CRITICAL);
+ clks[ADSP_SC594_CLK_CDU_DDR] = cdu_gate("cdu_ddr", "cdu_ddr_sel",
+ cdu + CDU_CFG3, CLK_IS_CRITICAL);
+ clks[ADSP_SC594_CLK_CAN] = cdu_gate("can", "can_sel", cdu + CDU_CFG4, 0);
+ clks[ADSP_SC594_CLK_SPDIF] = cdu_gate("spdif", "spdif_sel", cdu + CDU_CFG5, 0);
+ clks[ADSP_SC594_CLK_SPI] = cdu_gate("spi", "spi_sel", cdu + CDU_CFG6, 0);
+ clks[ADSP_SC594_CLK_GIGE] = cdu_gate("gige", "gige_sel", cdu + CDU_CFG7, 0);
+ clks[ADSP_SC594_CLK_LP] = cdu_gate("lp", "lp_sel", cdu + CDU_CFG8, 0);
+ clks[ADSP_SC594_CLK_LPDDR] = cdu_gate("lpddr", "lpddr_sel", cdu + CDU_CFG9, 0);
+ clks[ADSP_SC594_CLK_OSPI] = cdu_gate("ospi", "ospi_sel", cdu + CDU_CFG10, 0);
+ clks[ADSP_SC594_CLK_TRACE] = cdu_gate("trace", "trace_sel", cdu + CDU_CFG12, 0);
+
+ ret = cdu_check_clocks(clks, ARRAY_SIZE(clks));
+ if (ret)
+ pr_err("CDU error detected\n");
+
+ return ret;
+}
+
+static const struct udevice_id adi_sc594_clk_ids[] = {
+ { .compatible = "adi,sc594-clocks" },
+ { },
+};
+
+U_BOOT_DRIVER(adi_sc594_clk) = {
+ .name = "clk_adi_sc594",
+ .id = UCLASS_CLK,
+ .of_match = adi_sc594_clk_ids,
+ .ops = &adi_clk_ops,
+ .probe = sc594_clock_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/adi/clk-adi-sc598.c b/drivers/clk/adi/clk-adi-sc598.c
new file mode 100644
index 0000000..d4a16ac
--- /dev/null
+++ b/drivers/clk/adi/clk-adi-sc598.c
@@ -0,0 +1,308 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Author: Greg Malysa <greg.malysa@timesys.com>
+ *
+ * Ported from Linux: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ */
+
+#include <clk.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dt-bindings/clock/adi-sc5xx-clock.h>
+#include <linux/compiler_types.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/printk.h>
+#include <linux/types.h>
+
+#include "clk.h"
+
+static const char * const cgu1_in_sels[] = {"sys_clkin0", "sys_clkin1"};
+static const char * const cgu0_s1sels[] = {"cgu0_s1seldiv", "cgu0_s1selexdiv"};
+static const char * const cgu1_s0sels[] = {"cgu1_s0seldiv", "cgu1_s0selexdiv"};
+static const char * const cgu1_s1sels[] = {"cgu1_s1seldiv", "cgu1_s1selexdiv"};
+static const char * const sharc0_sels[] = {"cclk0_0", "dummy", "dummy", "dummy"};
+static const char * const sharc1_sels[] = {"cclk0_0", "dummy", "dummy", "dummy"};
+static const char * const arm_sels[] = {"dummy", "dummy", "cclk2_0", "cclk2_1"};
+static const char * const cdu_ddr_sels[] = {"dclk_0", "dclk_1", "dummy", "dummy"};
+static const char * const can_sels[] = {"dummy", "oclk_1", "dummy", "dummy"};
+static const char * const spdif_sels[] = {"sclk1_0", "dummy", "dummy", "dummy"};
+static const char * const spi_sels[] = {"sclk0_0", "oclk_0", "dummy", "dummy"};
+static const char * const gige_sels[] = {"sclk0_0", "sclk0_1", "dummy", "dummy"};
+static const char * const lp_sels[] = {"oclk_0", "sclk0_0", "cclk0_1", "dummy"};
+static const char * const lp_ddr_sels[] = {"oclk_0", "dclk_0", "sysclk_1", "dummy"};
+static const char * const ospi_refclk_sels[] = {"sysclk_0", "sclk0_0", "sclk1_1",
+ "dummy"};
+static const char * const trace_sels[] = {"sclk0_0", "dummy", "dummy", "dummy"};
+static const char * const emmc_sels[] = {"oclk_0", "sclk0_1", "dclk_0_half",
+ "dclk_1_half"};
+static const char * const emmc_timer_sels[] = {"dummy", "sclk1_1_half", "dummy",
+ "dummy"};
+static const char * const ddr_sels[] = {"cdu_ddr", "3pll_ddiv"};
+
+static int sc598_clock_probe(struct udevice *dev)
+{
+ void __iomem *cgu0;
+ void __iomem *cgu1;
+ void __iomem *cdu;
+ void __iomem *pll3;
+ int ret;
+ struct resource res;
+
+ struct clk *clks[ADSP_SC598_CLK_END];
+ struct clk dummy, clkin0, clkin1;
+
+ ret = dev_read_resource_byname(dev, "cgu0", &res);
+ if (ret)
+ return ret;
+ cgu0 = devm_ioremap(dev, res.start, resource_size(&res));
+
+ ret = dev_read_resource_byname(dev, "cgu1", &res);
+ if (ret)
+ return ret;
+ cgu1 = devm_ioremap(dev, res.start, resource_size(&res));
+
+ ret = dev_read_resource_byname(dev, "cdu", &res);
+ if (ret)
+ return ret;
+ cdu = devm_ioremap(dev, res.start, resource_size(&res));
+
+ ret = dev_read_resource_byname(dev, "pll3", &res);
+ if (ret)
+ return ret;
+ pll3 = devm_ioremap(dev, res.start, resource_size(&res));
+
+ // We only access this one register for pll3
+ pll3 = pll3 + PLL3_OFFSET;
+
+ // Input clock configuration
+ clk_get_by_name(dev, "dummy", &dummy);
+ clk_get_by_name(dev, "sys_clkin0", &clkin0);
+ clk_get_by_name(dev, "sys_clkin1", &clkin1);
+
+ clks[ADSP_SC598_CLK_DUMMY] = &dummy;
+ clks[ADSP_SC598_CLK_SYS_CLKIN0] = &clkin0;
+ clks[ADSP_SC598_CLK_SYS_CLKIN1] = &clkin1;
+
+ clks[ADSP_SC598_CLK_CGU1_IN] = clk_register_mux(NULL, "cgu1_in_sel", cgu1_in_sels,
+ 2, CLK_SET_RATE_PARENT,
+ cdu + CDU_CLKINSEL, 0, 1, 0);
+
+ // 3rd pll reuses cgu1 clk in selection, feeds directly into 3pll df
+ // changing the cgu1 in sel mux will affect 3pll so reuse the same clocks
+
+ // CGU configuration and internal clocks
+ clks[ADSP_SC598_CLK_CGU0_PLL_IN] = clk_register_divider(NULL, "cgu0_df",
+ "sys_clkin0",
+ CLK_SET_RATE_PARENT,
+ cgu0 + CGU_CTL, 0, 1, 0);
+ clks[ADSP_SC598_CLK_CGU1_PLL_IN] = clk_register_divider(NULL, "cgu1_df",
+ "cgu1_in_sel",
+ CLK_SET_RATE_PARENT,
+ cgu1 + CGU_CTL, 0, 1, 0);
+ clks[ADSP_SC598_CLK_3PLL_PLL_IN] = clk_register_divider(NULL, "3pll_df",
+ "cgu1_in_sel",
+ CLK_SET_RATE_PARENT,
+ pll3, 3, 1, 0);
+
+ // VCO output inside PLL
+ clks[ADSP_SC598_CLK_CGU0_VCO_OUT] = sc5xx_cgu_pll("cgu0_vco", "cgu0_df",
+ cgu0 + CGU_CTL, CGU_MSEL_SHIFT,
+ CGU_MSEL_WIDTH, 0, true);
+ clks[ADSP_SC598_CLK_CGU1_VCO_OUT] = sc5xx_cgu_pll("cgu1_vco", "cgu1_df",
+ cgu1 + CGU_CTL, CGU_MSEL_SHIFT,
+ CGU_MSEL_WIDTH, 0, true);
+ clks[ADSP_SC598_CLK_3PLL_VCO_OUT] = sc5xx_cgu_pll("3pll_vco", "3pll_df",
+ pll3, PLL3_MSEL_SHIFT,
+ PLL3_MSEL_WIDTH, 1, true);
+
+ // Final PLL output
+ clks[ADSP_SC598_CLK_CGU0_PLLCLK] = clk_register_fixed_factor(NULL, "cgu0_pllclk",
+ "cgu0_vco",
+ CLK_SET_RATE_PARENT,
+ 1, 2);
+ clks[ADSP_SC598_CLK_CGU1_PLLCLK] = clk_register_fixed_factor(NULL, "cgu1_pllclk",
+ "cgu1_vco",
+ CLK_SET_RATE_PARENT,
+ 1, 2);
+ clks[ADSP_SC598_CLK_3PLL_PLLCLK] = clk_register_fixed_factor(NULL, "3pll_pllclk",
+ "3pll_vco",
+ CLK_SET_RATE_PARENT,
+ 1, 2);
+
+ // Dividers from pll output
+ clks[ADSP_SC598_CLK_CGU0_CDIV] = cgu_divider("cgu0_cdiv", "cgu0_pllclk",
+ cgu0 + CGU_DIV, 0, 5, 0);
+ clks[ADSP_SC598_CLK_CGU0_SYSCLK] = cgu_divider("sysclk_0", "cgu0_pllclk",
+ cgu0 + CGU_DIV, 8, 5, 0);
+ clks[ADSP_SC598_CLK_CGU0_DDIV] = cgu_divider("cgu0_ddiv", "cgu0_pllclk",
+ cgu0 + CGU_DIV, 16, 5, 0);
+ clks[ADSP_SC598_CLK_CGU0_ODIV] = cgu_divider("cgu0_odiv", "cgu0_pllclk",
+ cgu0 + CGU_DIV, 22, 7, 0);
+ clks[ADSP_SC598_CLK_CGU0_S0SELDIV] = cgu_divider("cgu0_s0seldiv", "sysclk_0",
+ cgu0 + CGU_DIV, 5, 3, 0);
+ clks[ADSP_SC598_CLK_CGU0_S1SELDIV] = cgu_divider("cgu0_s1seldiv", "sysclk_0",
+ cgu0 + CGU_DIV, 13, 3, 0);
+ clks[ADSP_SC598_CLK_CGU0_S1SELEXDIV] = cgu_divider("cgu0_s1selexdiv",
+ "cgu0_pllclk",
+ cgu0 + CGU_DIVEX, 16, 8, 0);
+ clks[ADSP_SC598_CLK_CGU0_S1SEL] = clk_register_mux(NULL, "cgu0_sclk1sel",
+ cgu0_s1sels, 2,
+ CLK_SET_RATE_PARENT,
+ cgu0 + CGU_CTL, 17, 1, 0);
+ clks[ADSP_SC598_CLK_CGU0_CCLK2] = clk_register_fixed_factor(NULL, "cclk2_0",
+ "cgu0_vco",
+ CLK_SET_RATE_PARENT,
+ 1, 3);
+
+ clks[ADSP_SC598_CLK_CGU1_CDIV] = cgu_divider("cgu1_cdiv", "cgu1_pllclk",
+ cgu1 + CGU_DIV, 0, 5, 0);
+ clks[ADSP_SC598_CLK_CGU1_SYSCLK] = cgu_divider("sysclk_1", "cgu1_pllclk",
+ cgu1 + CGU_DIV, 8, 5, 0);
+ clks[ADSP_SC598_CLK_CGU1_DDIV] = cgu_divider("cgu1_ddiv", "cgu1_pllclk",
+ cgu1 + CGU_DIV, 16, 5, 0);
+ clks[ADSP_SC598_CLK_CGU1_ODIV] = cgu_divider("cgu1_odiv", "cgu1_pllclk",
+ cgu1 + CGU_DIV, 22, 7, 0);
+ clks[ADSP_SC598_CLK_CGU1_S0SELDIV] = cgu_divider("cgu1_s0seldiv", "sysclk_1",
+ cgu1 + CGU_DIV, 5, 3, 0);
+ clks[ADSP_SC598_CLK_CGU1_S1SELDIV] = cgu_divider("cgu1_s1seldiv", "sysclk_1",
+ cgu1 + CGU_DIV, 13, 3, 0);
+ clks[ADSP_SC598_CLK_CGU1_S0SELEXDIV] = cgu_divider("cgu1_s0selexdiv",
+ "cgu1_pllclk",
+ cgu1 + CGU_DIVEX, 0, 8, 0);
+ clks[ADSP_SC598_CLK_CGU1_S1SELEXDIV] = cgu_divider("cgu1_s1selexdiv",
+ "cgu1_pllclk",
+ cgu1 + CGU_DIVEX, 16, 8, 0);
+ clks[ADSP_SC598_CLK_CGU1_S0SEL] = clk_register_mux(NULL, "cgu1_sclk0sel",
+ cgu1_s0sels, 2,
+ CLK_SET_RATE_PARENT,
+ cgu1 + CGU_CTL, 16, 1, 0);
+ clks[ADSP_SC598_CLK_CGU1_S1SEL] = clk_register_mux(NULL, "cgu1_sclk1sel",
+ cgu1_s1sels, 2,
+ CLK_SET_RATE_PARENT,
+ cgu1 + CGU_CTL, 17, 1, 0);
+ clks[ADSP_SC598_CLK_CGU1_CCLK2] = clk_register_fixed_factor(NULL, "cclk2_1",
+ "cgu1_vco",
+ CLK_SET_RATE_PARENT,
+ 1, 3);
+
+ clks[ADSP_SC598_CLK_3PLL_DDIV] = clk_register_divider(NULL, "3pll_ddiv",
+ "3pll_pllclk",
+ CLK_SET_RATE_PARENT, pll3,
+ 12, 5, 0);
+
+ // Gates to enable CGU outputs
+ clks[ADSP_SC598_CLK_CGU0_CCLK0] = cgu_gate("cclk0_0", "cgu0_cdiv",
+ cgu0 + CGU_CCBF_DIS, 0);
+ clks[ADSP_SC598_CLK_CGU0_OCLK] = cgu_gate("oclk_0", "cgu0_odiv",
+ cgu0 + CGU_SCBF_DIS, 3);
+ clks[ADSP_SC598_CLK_CGU0_DCLK] = cgu_gate("dclk_0", "cgu0_ddiv",
+ cgu0 + CGU_SCBF_DIS, 2);
+ clks[ADSP_SC598_CLK_CGU0_SCLK1] = cgu_gate("sclk1_0", "cgu0_sclk1sel",
+ cgu0 + CGU_SCBF_DIS, 1);
+ clks[ADSP_SC598_CLK_CGU0_SCLK0] = cgu_gate("sclk0_0", "cgu0_s0seldiv",
+ cgu0 + CGU_SCBF_DIS, 0);
+
+ clks[ADSP_SC598_CLK_CGU1_CCLK0] = cgu_gate("cclk0_1", "cgu1_cdiv",
+ cgu1 + CGU_CCBF_DIS, 0);
+ clks[ADSP_SC598_CLK_CGU1_OCLK] = cgu_gate("oclk_1", "cgu1_odiv",
+ cgu1 + CGU_SCBF_DIS, 3);
+ clks[ADSP_SC598_CLK_CGU1_DCLK] = cgu_gate("dclk_1", "cgu1_ddiv",
+ cgu1 + CGU_SCBF_DIS, 2);
+ clks[ADSP_SC598_CLK_CGU1_SCLK1] = cgu_gate("sclk1_1", "cgu1_sclk1sel",
+ cgu1 + CGU_SCBF_DIS, 1);
+ clks[ADSP_SC598_CLK_CGU1_SCLK0] = cgu_gate("sclk0_1", "cgu1_sclk0sel",
+ cgu1 + CGU_SCBF_DIS, 0);
+
+ // Extra half rate clocks generated in the CDU
+ clks[ADSP_SC598_CLK_DCLK0_HALF] = clk_register_fixed_factor(NULL, "dclk_0_half",
+ "dclk_0",
+ CLK_SET_RATE_PARENT,
+ 1, 2);
+ clks[ADSP_SC598_CLK_DCLK1_HALF] = clk_register_fixed_factor(NULL, "dclk_1_half",
+ "dclk_1",
+ CLK_SET_RATE_PARENT,
+ 1, 2);
+ clks[ADSP_SC598_CLK_CGU1_SCLK1_HALF] = clk_register_fixed_factor(NULL,
+ "sclk1_1_half",
+ "sclk1_1",
+ CLK_SET_RATE_PARENT,
+ 1, 2);
+
+ // CDU output muxes
+ clks[ADSP_SC598_CLK_SHARC0_SEL] = cdu_mux("sharc0_sel", cdu + CDU_CFG0,
+ sharc0_sels);
+ clks[ADSP_SC598_CLK_SHARC1_SEL] = cdu_mux("sharc1_sel", cdu + CDU_CFG1,
+ sharc1_sels);
+ clks[ADSP_SC598_CLK_ARM_SEL] = cdu_mux("arm_sel", cdu + CDU_CFG2, arm_sels);
+ clks[ADSP_SC598_CLK_CDU_DDR_SEL] = cdu_mux("cdu_ddr_sel", cdu + CDU_CFG3,
+ cdu_ddr_sels);
+ clks[ADSP_SC598_CLK_CAN_SEL] = cdu_mux("can_sel", cdu + CDU_CFG4, can_sels);
+ clks[ADSP_SC598_CLK_SPDIF_SEL] = cdu_mux("spdif_sel", cdu + CDU_CFG5, spdif_sels);
+ clks[ADSP_SC598_CLK_SPI_SEL] = cdu_mux("spi_sel", cdu + CDU_CFG6, spi_sels);
+ clks[ADSP_SC598_CLK_GIGE_SEL] = cdu_mux("gige_sel", cdu + CDU_CFG7, gige_sels);
+ clks[ADSP_SC598_CLK_LP_SEL] = cdu_mux("lp_sel", cdu + CDU_CFG8, lp_sels);
+ clks[ADSP_SC598_CLK_LP_DDR_SEL] = cdu_mux("lp_ddr_sel", cdu + CDU_CFG9,
+ lp_ddr_sels);
+ clks[ADSP_SC598_CLK_OSPI_REFCLK_SEL] = cdu_mux("ospi_refclk_sel", cdu + CDU_CFG10,
+ ospi_refclk_sels);
+ clks[ADSP_SC598_CLK_TRACE_SEL] = cdu_mux("trace_sel", cdu + CDU_CFG12,
+ trace_sels);
+ clks[ADSP_SC598_CLK_EMMC_SEL] = cdu_mux("emmc_sel", cdu + CDU_CFG13, emmc_sels);
+ clks[ADSP_SC598_CLK_EMMC_TIMER_QMC_SEL] = cdu_mux("emmc_timer_qmc_sel",
+ cdu + CDU_CFG14,
+ emmc_timer_sels);
+
+ // CDU output enable gates
+ clks[ADSP_SC598_CLK_SHARC0] = cdu_gate("sharc0", "sharc0_sel", cdu + CDU_CFG0,
+ CLK_IS_CRITICAL);
+ clks[ADSP_SC598_CLK_SHARC1] = cdu_gate("sharc1", "sharc1_sel", cdu + CDU_CFG1,
+ CLK_IS_CRITICAL);
+ clks[ADSP_SC598_CLK_ARM] = cdu_gate("arm", "arm_sel", cdu + CDU_CFG2,
+ CLK_IS_CRITICAL);
+ clks[ADSP_SC598_CLK_CDU_DDR] = cdu_gate("cdu_ddr", "cdu_ddr_sel", cdu + CDU_CFG3,
+ 0);
+ clks[ADSP_SC598_CLK_CAN] = cdu_gate("can", "can_sel", cdu + CDU_CFG4, 0);
+ clks[ADSP_SC598_CLK_SPDIF] = cdu_gate("spdif", "spdif_sel", cdu + CDU_CFG5, 0);
+ clks[ADSP_SC598_CLK_SPI] = cdu_gate("spi", "spi_sel", cdu + CDU_CFG6, 0);
+ clks[ADSP_SC598_CLK_GIGE] = cdu_gate("gige", "gige_sel", cdu + CDU_CFG7, 0);
+ clks[ADSP_SC598_CLK_LP] = cdu_gate("lp", "lp_sel", cdu + CDU_CFG8, 0);
+ clks[ADSP_SC598_CLK_LP_DDR] = cdu_gate("lp_ddr", "lp_ddr_sel", cdu + CDU_CFG9, 0);
+ clks[ADSP_SC598_CLK_OSPI_REFCLK] = cdu_gate("ospi_refclk", "ospi_refclk_sel",
+ cdu + CDU_CFG10, 0);
+ clks[ADSP_SC598_CLK_TRACE] = cdu_gate("trace", "trace_sel", cdu + CDU_CFG12, 0);
+ clks[ADSP_SC598_CLK_EMMC] = cdu_gate("emmc", "emmc_sel", cdu + CDU_CFG13, 0);
+ clks[ADSP_SC598_CLK_EMMC_TIMER_QMC] = cdu_gate("emmc_timer_qmc",
+ "emmc_timer_qmc_sel",
+ cdu + CDU_CFG14, 0);
+
+ // Dedicated DDR output mux
+ clks[ADSP_SC598_CLK_DDR] = clk_register_mux(NULL, "ddr", ddr_sels, 2,
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ pll3, 11, 1, 0);
+
+ ret = cdu_check_clocks(clks, ARRAY_SIZE(clks));
+ if (ret)
+ pr_err("CDU error detected\n");
+
+ return ret;
+}
+
+static const struct udevice_id adi_sc598_clk_ids[] = {
+ { .compatible = "adi,sc598-clocks" },
+ { },
+};
+
+U_BOOT_DRIVER(adi_sc598_clk) = {
+ .name = "clk_adi_sc598",
+ .id = UCLASS_CLK,
+ .of_match = adi_sc598_clk_ids,
+ .ops = &adi_clk_ops,
+ .probe = sc598_clock_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/adi/clk-shared.c b/drivers/clk/adi/clk-shared.c
new file mode 100644
index 0000000..dcadcaf
--- /dev/null
+++ b/drivers/clk/adi/clk-shared.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Author: Greg Malysa <greg.malysa@timesys.com>
+ */
+
+#include "clk.h"
+
+static ulong adi_get_rate(struct clk *clk)
+{
+ struct clk *c;
+ int ret;
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ return clk_get_rate(c);
+}
+
+static ulong adi_set_rate(struct clk *clk, ulong rate)
+{
+ //Not yet implemented
+ return 0;
+}
+
+static int adi_enable(struct clk *clk)
+{
+ //Not yet implemented
+ return 0;
+}
+
+static int adi_disable(struct clk *clk)
+{
+ //Not yet implemented
+ return 0;
+}
+
+const struct clk_ops adi_clk_ops = {
+ .set_rate = adi_set_rate,
+ .get_rate = adi_get_rate,
+ .enable = adi_enable,
+ .disable = adi_disable,
+};
+
diff --git a/drivers/clk/adi/clk.h b/drivers/clk/adi/clk.h
new file mode 100644
index 0000000..f230205
--- /dev/null
+++ b/drivers/clk/adi/clk.h
@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Author: Greg Malysa <greg.malysa@timesys.com>
+ *
+ * Ported from Linux: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ */
+
+#ifndef CLK_ADI_CLK_H
+#define CLK_ADI_CLK_H
+
+#include <linux/compiler_types.h>
+#include <linux/types.h>
+#include <linux/clk-provider.h>
+
+#define CGU_CTL 0x00
+#define CGU_PLLCTL 0x04
+#define CGU_STAT 0x08
+#define CGU_DIV 0x0C
+#define CGU_CLKOUTSEL 0x10
+#define CGU_OSCWDCTL 0x14
+#define CGU_TSCTL 0x18
+#define CGU_TSVALUE0 0x1C
+#define CGU_TSVALUE1 0x20
+#define CGU_TSCOUNT0 0x24
+#define CGU_TSCOUNT1 0x28
+#define CGU_CCBF_DIS 0x2C
+#define CGU_CCBF_STAT 0x30
+#define CGU_SCBF_DIS 0x38
+#define CGU_SCBF_STAT 0x3C
+#define CGU_DIVEX 0x40
+#define CGU_REVID 0x48
+
+#define CDU_CFG0 0x00
+#define CDU_CFG1 0x04
+#define CDU_CFG2 0x08
+#define CDU_CFG3 0x0C
+#define CDU_CFG4 0x10
+#define CDU_CFG5 0x14
+#define CDU_CFG6 0x18
+#define CDU_CFG7 0x1C
+#define CDU_CFG8 0x20
+#define CDU_CFG9 0x24
+#define CDU_CFG10 0x28
+#define CDU_CFG11 0x2C
+#define CDU_CFG12 0x30
+#define CDU_CFG13 0x34
+#define CDU_CFG14 0x38
+
+#define PLL3_OFFSET 0x2c
+
+#define CDU_CLKINSEL 0x44
+
+#define CGU_MSEL_SHIFT 8
+#define CGU_MSEL_WIDTH 7
+
+#define PLL3_MSEL_SHIFT 4
+#define PLL3_MSEL_WIDTH 7
+
+#define CDU_MUX_SIZE 4
+#define CDU_MUX_SHIFT 1
+#define CDU_MUX_WIDTH 2
+#define CDU_EN_BIT 0
+
+extern const struct clk_ops adi_clk_ops;
+
+struct clk *sc5xx_cgu_pll(const char *name, const char *parent_name,
+ void __iomem *base, u8 shift, u8 width, u32 m_offset, bool half_m);
+
+/**
+ * All CDU clock muxes are the same size
+ */
+static inline struct clk *cdu_mux(const char *name, void __iomem *reg,
+ const char * const *parents)
+{
+ return clk_register_mux(NULL, name, parents, CDU_MUX_SIZE,
+ CLK_SET_RATE_PARENT, reg, CDU_MUX_SHIFT, CDU_MUX_WIDTH, 0);
+}
+
+static inline struct clk *cgu_divider(const char *name, const char *parent,
+ void __iomem *reg, u8 shift, u8 width, u8 extra_flags)
+{
+ return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
+ reg, shift, width, CLK_DIVIDER_MAX_AT_ZERO | extra_flags);
+}
+
+static inline struct clk *cdu_gate(const char *name, const char *parent,
+ void __iomem *reg, u32 flags)
+{
+ return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT | flags,
+ reg, CDU_EN_BIT, 0, NULL);
+}
+
+static inline struct clk *cgu_gate(const char *name, const char *parent,
+ void __iomem *reg, u8 bit)
+{
+ return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, bit,
+ CLK_GATE_SET_TO_DISABLE, NULL);
+}
+
+static inline int cdu_check_clocks(struct clk *clks[], size_t count)
+{
+ size_t i;
+
+ for (i = 0; i < count; ++i) {
+ if (clks[i]) {
+ if (IS_ERR(clks[i])) {
+ pr_err("Clock %zu failed to register: %ld\n", i, PTR_ERR(clks[i]));
+ return PTR_ERR(clks[i]);
+ }
+ clks[i]->id = i;
+ } else {
+ pr_err("ADI Clock framework: Null pointer detected on clock %zu\n", i);
+ }
+ }
+
+ return 0;
+}
+
+#endif
diff --git a/drivers/crypto/nuvoton/npcm_sha.c b/drivers/crypto/nuvoton/npcm_sha.c
index f06be86..6da1620 100644
--- a/drivers/crypto/nuvoton/npcm_sha.c
+++ b/drivers/crypto/nuvoton/npcm_sha.c
@@ -1,867 +1,344 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (c) 2022 Nuvoton Technology Corp.
+ * Copyright (c) 2024 Nuvoton Technology Corp.
*/
#include <dm.h>
#include <hash.h>
#include <malloc.h>
-#include <uboot_aes.h>
#include <asm/io.h>
+#include <linux/iopoll.h>
-#define HASH_DIG_H_NUM 8
+#define SHA512_BLOCK_LENGTH (1024 / 8)
+/* Register fields */
#define HASH_CTR_STS_SHA_EN BIT(0)
#define HASH_CTR_STS_SHA_BUSY BIT(1)
#define HASH_CTR_STS_SHA_RST BIT(2)
#define HASH_CFG_SHA1_SHA2 BIT(0)
+#define SHA512_CMD_SHA_512 BIT(3)
+#define SHA512_CMD_INTERNAL_ROUND BIT(2)
+#define SHA512_CMD_WRITE BIT(1)
+#define SHA512_CMD_READ BIT(0)
-/* SHA type */
-enum npcm_sha_type {
- npcm_sha_type_sha2 = 0,
- npcm_sha_type_sha1,
- npcm_sha_type_num
+enum {
+ type_sha1 = 0,
+ type_sha256,
+ type_sha384,
+ type_sha512,
};
struct npcm_sha_regs {
- unsigned int hash_data_in;
- unsigned char hash_ctr_sts;
- unsigned char reserved_0[0x03];
- unsigned char hash_cfg;
- unsigned char reserved_1[0x03];
- unsigned char hash_ver;
- unsigned char reserved_2[0x13];
- unsigned int hash_dig[HASH_DIG_H_NUM];
+ u8 data_in;
+ u8 data_out;
+ u8 ctr_sts;
+ u8 hash_cfg;
+ u8 sha512_cmd;
};
-struct npcm_sha_priv {
- struct npcm_sha_regs *regs;
+struct hash_info {
+ u32 block_sz;
+ u32 digest_len;
+ u8 length_bytes;
+ u8 type;
};
-static struct npcm_sha_priv *sha_priv;
-
-#ifdef SHA_DEBUG_MODULE
-#define sha_print(fmt, args...) printf(fmt, ##args)
-#else
-#define sha_print(fmt, args...) (void)0
-#endif
-
-#define SHA_BLOCK_LENGTH (512 / 8)
-#define SHA_2_HASH_LENGTH (256 / 8)
-#define SHA_1_HASH_LENGTH (160 / 8)
-#define SHA_HASH_LENGTH(type) ((type == npcm_sha_type_sha2) ? \
- (SHA_2_HASH_LENGTH) : (SHA_1_HASH_LENGTH))
-
-#define SHA_SECRUN_BUFF_SIZE 64
-#define SHA_TIMEOUT 100
-#define SHA_DATA_LAST_BYTE 0x80
-
-#define SHA2_NUM_OF_SELF_TESTS 3
-#define SHA1_NUM_OF_SELF_TESTS 4
-
-#define NUVOTON_ALIGNMENT 4
-
-/*-----------------------------------------------------------------------------*/
-/* SHA instance struct handler */
-/*-----------------------------------------------------------------------------*/
-struct SHA_HANDLE_T {
- u32 hv[SHA_2_HASH_LENGTH / sizeof(u32)];
- u32 length0;
- u32 length1;
- u32 block[SHA_BLOCK_LENGTH / sizeof(u32)];
- u8 type;
- bool active;
+struct message_block {
+ u64 length[2];
+ u64 nonhash_sz;
+ u8 buffer[SHA512_BLOCK_LENGTH * 2];
};
-// The # of bytes currently in the sha block buffer
-#define SHA_BUFF_POS(length) ((length) & (SHA_BLOCK_LENGTH - 1))
-
-// The # of free bytes in the sha block buffer
-#define SHA_BUFF_FREE(length) (SHA_BLOCK_LENGTH - SHA_BUFF_POS(length))
+struct npcm_sha_priv {
+ void *base;
+ struct npcm_sha_regs *regs;
+ struct hash_info *hash;
+ struct message_block block;
+ bool internal_round;
+ bool support_sha512;
+};
-static void SHA_FlushLocalBuffer_l(const u32 *buff);
-static int SHA_BusyWait_l(void);
-static void SHA_GetShaDigest_l(u8 *hashdigest, u8 type);
-static void SHA_SetShaDigest_l(const u32 *hashdigest, u8 type);
-static void SHA_SetBlock_l(const u8 *data, u32 len, u16 position, u32 *block);
-static void SHA_ClearBlock_l(u16 len, u16 position, u32 *block);
-static void SHA_SetLength32_l(struct SHA_HANDLE_T *handleptr, u32 *block);
+static struct npcm_sha_regs npcm_sha_reg_tbl[] = {
+ { .data_in = 0x0, .data_out = 0x20, .ctr_sts = 0x4, .hash_cfg = 0x8 },
+ { .data_in = 0x10, .data_out = 0x1c, .ctr_sts = 0x14, .sha512_cmd = 0x18 },
+};
-static int SHA_Init(struct SHA_HANDLE_T *handleptr);
-static int SHA_Start(struct SHA_HANDLE_T *handleptr, u8 type);
-static int SHA_Update(struct SHA_HANDLE_T *handleptr, const u8 *buffer, u32 len);
-static int SHA_Finish(struct SHA_HANDLE_T *handleptr, u8 *hashdigest);
-static int SHA_Reset(void);
-static int SHA_Power(bool on);
-#ifdef SHA_PRINT
-static void SHA_PrintRegs(void);
-static void SHA_PrintVersion(void);
-#endif
+static struct hash_info npcm_hash_tbl[] = {
+ { .type = type_sha1, .block_sz = 64, .digest_len = 160, .length_bytes = 8 },
+ { .type = type_sha256, .block_sz = 64, .digest_len = 256, .length_bytes = 8 },
+ { .type = type_sha384, .block_sz = 128, .digest_len = 384, .length_bytes = 16 },
+ { .type = type_sha512, .block_sz = 128, .digest_len = 512, .length_bytes = 16 },
+};
-static struct SHA_HANDLE_T sha_handle;
+static struct npcm_sha_priv *sha_priv;
-/*----------------------------------------------------------------------------*/
-/* Checks if give function returns int error, and returns the error */
-/* immediately after SHA disabling */
-/*----------------------------------------------------------------------------*/
-int npcm_sha_check(int status)
+static int npcm_sha_init(u8 type)
{
- if (status != 0) {
- SHA_Power(false);
- return status;
- }
- return 0;
-}
+ struct message_block *block = &sha_priv->block;
-/*----------------------------------------------------------------------------*/
-/* Function: npcm_sha_calc */
-/* */
-/* Parameters: type - SHA module type */
-/* inBuff - Pointer to a buffer containing the data to */
-/* be hashed */
-/* len - Length of the data to hash */
-/* hashDigest - Pointer to a buffer where the reseulting */
-/* digest will be copied to */
-/* */
-/* Returns: 0 on success or other int error code on error */
-/* Side effects: */
-/* Description: */
-/* This routine performs complete SHA calculation in one */
-/* step */
-/*----------------------------------------------------------------------------*/
-int npcm_sha_calc(u8 type, const u8 *inbuff, u32 len, u8 *hashdigest)
-{
- int status;
- struct SHA_HANDLE_T handle;
+ if (type > type_sha512 ||
+ (!sha_priv->support_sha512 &&
+ (type == type_sha384 || type == type_sha512)))
+ return -ENOTSUPP;
- SHA_Init(&handle);
- SHA_Power(true);
- SHA_Reset();
- SHA_Start(&handle, type);
- status = SHA_Update(&handle, inbuff, len);
- npcm_sha_check(status);
- status = SHA_Finish(&handle, hashdigest);
- npcm_sha_check(status);
- SHA_Power(false);
+ sha_priv->regs = &npcm_sha_reg_tbl[type / 2];
+ sha_priv->hash = &npcm_hash_tbl[type];
+ block->length[0] = 0;
+ block->length[1] = 0;
+ block->nonhash_sz = 0;
+ sha_priv->internal_round = false;
return 0;
}
-/*
- * Computes hash value of input pbuf using h/w acceleration
- *
- * @param in_addr A pointer to the input buffer
- * @param bufleni Byte length of input buffer
- * @param out_addr A pointer to the output buffer. When complete
- * 32 bytes are copied to pout[0]...pout[31]. Thus, a user
- * should allocate at least 32 bytes at pOut in advance.
- * @param chunk_size chunk size for sha256
- */
-void hw_sha256(const uchar *in_addr, uint buflen, uchar *out_addr, uint chunk_size)
-{
- puts("\nhw_sha256 using BMC HW accelerator\t");
- npcm_sha_calc(npcm_sha_type_sha2, (u8 *)in_addr, buflen, (u8 *)out_addr);
-}
-
-/*
- * Computes hash value of input pbuf using h/w acceleration
- *
- * @param in_addr A pointer to the input buffer
- * @param bufleni Byte length of input buffer
- * @param out_addr A pointer to the output buffer. When complete
- * 32 bytes are copied to pout[0]...pout[31]. Thus, a user
- * should allocate at least 32 bytes at pOut in advance.
- * @param chunk_size chunk_size for sha1
- */
-void hw_sha1(const uchar *in_addr, uint buflen, uchar *out_addr, uint chunk_size)
-{
- puts("\nhw_sha1 using BMC HW accelerator\t");
- npcm_sha_calc(npcm_sha_type_sha1, (u8 *)in_addr, buflen, (u8 *)out_addr);
-}
-
-/*
- * Create the context for sha progressive hashing using h/w acceleration
- *
- * @algo: Pointer to the hash_algo struct
- * @ctxp: Pointer to the pointer of the context for hashing
- * @return 0 if ok, -ve on error
- */
-int hw_sha_init(struct hash_algo *algo, void **ctxp)
-{
- const char *algo_name1 = "sha1";
- const char *algo_name2 = "sha256";
-
- SHA_Init(&sha_handle);
- SHA_Power(true);
- SHA_Reset();
- if (!strcmp(algo_name1, algo->name))
- return SHA_Start(&sha_handle, npcm_sha_type_sha1);
- else if (!strcmp(algo_name2, algo->name))
- return SHA_Start(&sha_handle, npcm_sha_type_sha2);
- else
- return -EPROTO;
-}
-
-/*
- * Update buffer for sha progressive hashing using h/w acceleration
- *
- * The context is freed by this function if an error occurs.
- *
- * @algo: Pointer to the hash_algo struct
- * @ctx: Pointer to the context for hashing
- * @buf: Pointer to the buffer being hashed
- * @size: Size of the buffer being hashed
- * @is_last: 1 if this is the last update; 0 otherwise
- * @return 0 if ok, -ve on error
- */
-int hw_sha_update(struct hash_algo *algo, void *ctx, const void *buf,
- unsigned int size, int is_last)
+static void npcm_sha_reset(void)
{
- return SHA_Update(&sha_handle, buf, size);
-}
+ struct npcm_sha_regs *regs = sha_priv->regs;
+ struct hash_info *hash = sha_priv->hash;
+ u8 val;
-/*
- * Copy sha hash result at destination location
- *
- * The context is freed after completion of hash operation or after an error.
- *
- * @algo: Pointer to the hash_algo struct
- * @ctx: Pointer to the context for hashing
- * @dest_buf: Pointer to the destination buffer where hash is to be copied
- * @size: Size of the buffer being hashed
- * @return 0 if ok, -ve on error
- */
-int hw_sha_finish(struct hash_algo *algo, void *ctx, void *dest_buf, int size)
-{
- int status;
+ if (hash->type == type_sha1)
+ writeb(HASH_CFG_SHA1_SHA2, sha_priv->base + regs->hash_cfg);
+ else if (hash->type == type_sha256)
+ writeb(0, sha_priv->base + regs->hash_cfg);
+ else if (hash->type == type_sha384)
+ writeb(0, sha_priv->base + regs->sha512_cmd);
+ else if (hash->type == type_sha512)
+ writeb(SHA512_CMD_SHA_512, sha_priv->base + regs->sha512_cmd);
- status = SHA_Finish(&sha_handle, dest_buf);
- npcm_sha_check(status);
- return SHA_Power(false);
+ val = readb(sha_priv->base + regs->ctr_sts) & ~HASH_CTR_STS_SHA_EN;
+ writeb(val | HASH_CTR_STS_SHA_RST, sha_priv->base + regs->ctr_sts);
}
-/*----------------------------------------------------------------------------*/
-/* Function: SHA_Init */
-/* */
-/* Parameters: handlePtr - SHA processing handle pointer */
-/* Returns: 0 on success or other int error code on error. */
-/* Side effects: */
-/* Description: */
-/* This routine initialize the SHA module */
-/*----------------------------------------------------------------------------*/
-static int SHA_Init(struct SHA_HANDLE_T *handleptr)
+static void npcm_sha_enable(bool on)
{
- handleptr->active = false;
+ struct npcm_sha_regs *regs = sha_priv->regs;
+ u8 val;
- return 0;
+ val = readb(sha_priv->base + regs->ctr_sts) & ~HASH_CTR_STS_SHA_EN;
+ val |= on;
+ writeb(val | on, sha_priv->base + regs->ctr_sts);
}
-/*----------------------------------------------------------------------------*/
-/* Function: SHA_Start */
-/* */
-/* Parameters: handlePtr - SHA processing handle pointer */
-/* type - SHA module type */
-/* */
-/* Returns: 0 on success or other int error code on error. */
-/* Side effects: */
-/* Description: */
-/* This routine start a single SHA process */
-/*----------------------------------------------------------------------------*/
-static int SHA_Start(struct SHA_HANDLE_T *handleptr, u8 type)
+static int npcm_sha_flush_block(u8 *block)
{
struct npcm_sha_regs *regs = sha_priv->regs;
-
- // Initialize handle
- handleptr->length0 = 0;
- handleptr->length1 = 0;
- handleptr->type = type;
- handleptr->active = true;
+ struct hash_info *hash = sha_priv->hash;
+ u32 *blk_dw = (u32 *)block;
+ u8 val;
+ int i;
- // Set SHA type
- writeb(handleptr->type & HASH_CFG_SHA1_SHA2, ®s->hash_cfg);
+ if (readb_poll_timeout(sha_priv->base + regs->ctr_sts, val,
+ !(val & HASH_CTR_STS_SHA_BUSY), 100))
+ return -ETIMEDOUT;
- // Reset SHA hardware
- SHA_Reset();
-
- /* The handlePtr->hv is initialized with the correct IV as the SHA engine
- * automatically fill the HASH_DIG_Hn registers according to SHA spec
- * (following SHA_RST assertion)
- */
- SHA_GetShaDigest_l((u8 *)handleptr->hv, type);
+ if (hash->type == type_sha384 || hash->type == type_sha512) {
+ val = SHA512_CMD_WRITE;
+ if (hash->type == type_sha512)
+ val |= SHA512_CMD_SHA_512;
+ if (sha_priv->internal_round)
+ val |= SHA512_CMD_INTERNAL_ROUND;
+ writeb(val, sha_priv->base + regs->sha512_cmd);
+ }
+ for (i = 0; i < (hash->block_sz / sizeof(u32)); i++)
+ writel(blk_dw[i], sha_priv->base + regs->data_in);
- // Init block with zeros
- memset(handleptr->block, 0, sizeof(handleptr->block));
+ sha_priv->internal_round = true;
return 0;
}
-/*----------------------------------------------------------------------------*/
-/* Function: SHA_Update */
-/* */
-/* Parameters: handlePtr - SHA processing handle pointer */
-/* buffer - Pointer to the data that will be added to */
-/* the hash calculation */
-/* len - Length of data to add to SHA calculation */
-/* */
-/* */
-/* Returns: 0 on success or other int error code on error */
-/* Side effects: */
-/* Description: */
-/* This routine adds data to previously started SHA */
-/* calculation */
-/*----------------------------------------------------------------------------*/
-static int SHA_Update(struct SHA_HANDLE_T *handleptr, const u8 *buffer, u32 len)
+static int npcm_sha_update_block(const u8 *in, u32 len)
{
- struct npcm_sha_regs *regs = sha_priv->regs;
- u32 localbuffer[SHA_SECRUN_BUFF_SIZE / sizeof(u32)];
- u32 bufferlen = len;
- u16 pos = 0;
- u8 *blockptr;
- int status;
+ struct message_block *block = &sha_priv->block;
+ struct hash_info *hash = sha_priv->hash;
+ u8 *buffer = &block->buffer[0];
+ u32 block_sz = hash->block_sz;
+ u32 hash_sz;
- // Error check
- if (!handleptr->active)
- return -EPROTO;
+ hash_sz = (block->nonhash_sz + len) > block_sz ?
+ (block_sz - block->nonhash_sz) : len;
+ memcpy(buffer + block->nonhash_sz, in, hash_sz);
+ block->nonhash_sz += hash_sz;
+ block->length[0] += hash_sz;
+ if (block->length[0] < hash_sz)
+ block->length[1]++;
- // Wait till SHA is not busy
- status = SHA_BusyWait_l();
- npcm_sha_check(status);
-
- // Set SHA type
- writeb(handleptr->type & HASH_CFG_SHA1_SHA2, ®s->hash_cfg);
-
- // Write SHA latest digest into SHA module
- SHA_SetShaDigest_l(handleptr->hv, handleptr->type);
+ if (block->nonhash_sz == block_sz) {
+ block->nonhash_sz = 0;
+ if (npcm_sha_flush_block(buffer))
+ return -EBUSY;
+ }
- // Set number of unhashed bytes which remained from last update
- pos = SHA_BUFF_POS(handleptr->length0);
+ return hash_sz;
+}
- // Copy unhashed bytes which remained from last update to secrun buffer
- SHA_SetBlock_l((u8 *)handleptr->block, pos, 0, localbuffer);
+static int npcm_sha_update(const u8 *input, u32 len)
+{
+ int hash_sz;
while (len) {
- // Wait for the hardware to be available (in case we are hashing)
- status = SHA_BusyWait_l();
- npcm_sha_check(status);
-
- // Move as much bytes as we can into the secrun buffer
- bufferlen = min(len, SHA_BUFF_FREE(handleptr->length0));
-
- // Copy current given buffer to the secrun buffer
- SHA_SetBlock_l((u8 *)buffer, bufferlen, pos, localbuffer);
-
- // Update size of hashed bytes
- handleptr->length0 += bufferlen;
-
- if (handleptr->length0 < bufferlen)
- handleptr->length1++;
-
- // Update length of data left to digest
- len -= bufferlen;
-
- // Update given buffer pointer
- buffer += bufferlen;
-
- // If secrun buffer is full
- if (SHA_BUFF_POS(handleptr->length0) == 0) {
- /* We just filled up the buffer perfectly, so let it hash (we'll
- * unload the hash only when we are done with all hashing)
- */
- SHA_FlushLocalBuffer_l(localbuffer);
-
- pos = 0;
- bufferlen = 0;
+ hash_sz = npcm_sha_update_block(input, len);
+ if (hash_sz < 0) {
+ printf("SHA512 module busy\n");
+ return -EBUSY;
}
+ len -= hash_sz;
+ input += hash_sz;
}
- // Wait till SHA is not busy
- status = SHA_BusyWait_l();
- npcm_sha_check(status);
-
- /* Copy unhashed bytes from given buffer to handle block for next update/finish */
- blockptr = (u8 *)handleptr->block;
- while (bufferlen)
- blockptr[--bufferlen + pos] = *(--buffer);
-
- // Save SHA current digest
- SHA_GetShaDigest_l((u8 *)handleptr->hv, handleptr->type);
-
return 0;
}
-/*----------------------------------------------------------------------------*/
-/* Function: SHA_Finish */
-/* */
-/* Parameters: handlePtr - SHA processing handle pointer */
-/* hashDigest - Pointer to a buffer where the final digest */
-/* will be copied to */
-/* */
-/* Returns: 0 on success or other int error code on error */
-/* Side effects: */
-/* Description: */
-/* This routine finish SHA calculation and get */
-/* the resulting SHA digest */
-/*----------------------------------------------------------------------------*/
-static int SHA_Finish(struct SHA_HANDLE_T *handleptr, u8 *hashdigest)
+static int npcm_sha_finish(u8 *out)
{
struct npcm_sha_regs *regs = sha_priv->regs;
- u32 localbuffer[SHA_SECRUN_BUFF_SIZE / sizeof(u32)];
- const u8 lastbyte = SHA_DATA_LAST_BYTE;
- u16 pos;
- int status;
-
- // Error check
- if (!handleptr->active)
- return -EPROTO;
-
- // Set SHA type
- writeb(handleptr->type & HASH_CFG_SHA1_SHA2, ®s->hash_cfg);
-
- // Wait till SHA is not busy
- status = SHA_BusyWait_l();
- npcm_sha_check(status);
-
- // Finish off the current buffer with the SHA spec'ed padding
- pos = SHA_BUFF_POS(handleptr->length0);
-
- // Init SHA digest
- SHA_SetShaDigest_l(handleptr->hv, handleptr->type);
-
- // Load data into secrun buffer
- SHA_SetBlock_l((u8 *)handleptr->block, pos, 0, localbuffer);
-
- // Set data last byte as in SHA algorithm spec
- SHA_SetBlock_l(&lastbyte, 1, pos++, localbuffer);
-
- // If the remainder of data is longer then one block
- if (pos > (SHA_BLOCK_LENGTH - 8)) {
- /* The length will be in the next block Pad the rest of the last block with 0's */
- SHA_ClearBlock_l((SHA_BLOCK_LENGTH - pos), pos, localbuffer);
+ struct message_block *block = &sha_priv->block;
+ struct hash_info *hash = sha_priv->hash;
+ u8 *buffer = &block->buffer[0];
+ u32 block_sz = hash->block_sz;
+ u32 *out32 = (u32 *)out;
+ u32 zero_len, val;
+ u64 *length;
+ u8 reg_data_out;
+ int i;
- // Hash the current block
- SHA_FlushLocalBuffer_l(localbuffer);
-
- pos = 0;
-
- // Wait till SHA is not busy
- status = SHA_BusyWait_l();
- npcm_sha_check(status);
+ /* Padding, minimal padding size is last_byte+length_bytes */
+ if ((block_sz - block->nonhash_sz) >= (hash->length_bytes + 1))
+ zero_len = block_sz - block->nonhash_sz - (hash->length_bytes + 1);
+ else
+ zero_len = block_sz * 2 - block->nonhash_sz - (hash->length_bytes + 1);
+ /* Last byte */
+ buffer[block->nonhash_sz++] = 0x80;
+ /* Zero bits padding */
+ memset(&buffer[block->nonhash_sz], 0, zero_len);
+ block->nonhash_sz += zero_len;
+ /* Message length */
+ length = (u64 *)&buffer[block->nonhash_sz];
+ if (hash->length_bytes == 16) {
+ *length++ = cpu_to_be64(block->length[1] << 3 | block->length[0] >> 61);
+ block->nonhash_sz += 8;
}
-
- // Pad the rest of the last block with 0's except for the last 8-3 bytes
- SHA_ClearBlock_l((SHA_BLOCK_LENGTH - (8 - 3)) - pos, pos, localbuffer);
-
- /* The last 8-3 bytes are set to the bit-length of the message in big-endian form */
- SHA_SetLength32_l(handleptr, localbuffer);
-
- // Hash all that, and save the hash for the caller
- SHA_FlushLocalBuffer_l(localbuffer);
-
- // Wait till SHA is not busy
- status = SHA_BusyWait_l();
- npcm_sha_check(status);
-
- // Save SHA final digest into given buffer
- SHA_GetShaDigest_l(hashdigest, handleptr->type);
-
- // Free handle
- handleptr->active = false;
+ *length = cpu_to_be64(block->length[0] << 3);
+ block->nonhash_sz += 8;
+ if (npcm_sha_flush_block(&block->buffer[0]))
+ return -ETIMEDOUT;
- return 0;
-}
-
-/*----------------------------------------------------------------------------*/
-/* Function: SHA_Reset */
-/* */
-/* Parameters: none */
-/* Returns: none */
-/* Side effects: */
-/* Description: */
-/* This routine reset SHA module */
-/*----------------------------------------------------------------------------*/
-static int SHA_Reset(void)
-{
- struct npcm_sha_regs *regs = sha_priv->regs;
+ /* After padding, the last message may produce 2 blocks */
+ if (block->nonhash_sz > block_sz) {
+ if (npcm_sha_flush_block(&block->buffer[block_sz]))
+ return -ETIMEDOUT;
+ }
+ /* Read digest */
+ if (readb_poll_timeout(sha_priv->base + regs->ctr_sts, val,
+ !(val & HASH_CTR_STS_SHA_BUSY), 100))
+ return -ETIMEDOUT;
+ if (hash->type == type_sha384)
+ writeb(SHA512_CMD_READ, sha_priv->base + regs->sha512_cmd);
+ else if (hash->type == type_sha512)
+ writeb(SHA512_CMD_SHA_512 | SHA512_CMD_READ,
+ sha_priv->base + regs->sha512_cmd);
- writel(readl(®s->hash_ctr_sts) | HASH_CTR_STS_SHA_RST, ®s->hash_ctr_sts);
+ reg_data_out = regs->data_out;
+ for (i = 0; i < (hash->digest_len / 32); i++) {
+ *out32 = readl(sha_priv->base + reg_data_out);
+ out32++;
+ if (hash->type == type_sha1 || hash->type == type_sha256)
+ reg_data_out += 4;
+ }
return 0;
}
-/*----------------------------------------------------------------------------*/
-/* Function: SHA_Power */
-/* */
-/* Parameters: on - true enable the module, false disable the module */
-/* Returns: none */
-/* Side effects: */
-/* Description: */
-/* This routine set SHA module power on/off */
-/*----------------------------------------------------------------------------*/
-static int SHA_Power(bool on)
+int npcm_sha_calc(const u8 *input, u32 len, u8 *output, u8 type)
{
- struct npcm_sha_regs *regs = sha_priv->regs;
- u8 hash_sts;
-
- hash_sts = readb(®s->hash_ctr_sts) & ~HASH_CTR_STS_SHA_EN;
- writeb(hash_sts | (on & HASH_CTR_STS_SHA_EN), ®s->hash_ctr_sts);
+ if (npcm_sha_init(type))
+ return -ENOTSUPP;
+ npcm_sha_reset();
+ npcm_sha_enable(true);
+ npcm_sha_update(input, len);
+ npcm_sha_finish(output);
+ npcm_sha_enable(false);
return 0;
}
-#ifdef SHA_PRINT
-/*----------------------------------------------------------------------------*/
-/* Function: SHA_PrintRegs */
-/* */
-/* Parameters: none */
-/* Returns: none */
-/* Side effects: */
-/* Description: */
-/* This routine prints the module registers */
-/*----------------------------------------------------------------------------*/
-static void SHA_PrintRegs(void)
-{
-#ifdef SHA_DEBUG_MODULE
- struct npcm_sha_regs *regs = sha_priv->regs;
-#endif
- unsigned int i;
-
- sha_print("/*--------------*/\n");
- sha_print("/* SHA */\n");
- sha_print("/*--------------*/\n\n");
-
- sha_print("HASH_CTR_STS = 0x%02X\n", readb(®s->hash_ctr_sts));
- sha_print("HASH_CFG = 0x%02X\n", readb(®s->hash_cfg));
-
- for (i = 0; i < HASH_DIG_H_NUM; i++)
- sha_print("HASH_DIG_H%d = 0x%08X\n", i, readl(®s->hash_dig[i]));
-
- sha_print("HASH_VER = 0x%08X\n", readb(®s->hash_ver));
-
- sha_print("\n");
-}
-
-/*----------------------------------------------------------------------------*/
-/* Function: SHA_PrintVersion */
-/* */
-/* Parameters: none */
-/* Returns: none */
-/* Side effects: */
-/* Description: */
-/* This routine prints the module version */
-/*----------------------------------------------------------------------------*/
-static void SHA_PrintVersion(void)
+void hw_sha512(const unsigned char *input, unsigned int len,
+ unsigned char *output, unsigned int chunk_sz)
{
- struct npcm_sha_regs *regs = sha_priv->regs;
-
- printf("SHA MODULE VER = %d\n", readb(®s->hash_ver));
+ if (!sha_priv->support_sha512) {
+ puts(" HW accelerator not support\n");
+ return;
+ }
+ puts(" using BMC HW accelerator\n");
+ npcm_sha_calc(input, len, output, type_sha512);
}
-#endif
-/*----------------------------------------------------------------------------*/
-/* Function: npcm_sha_selftest */
-/* */
-/* Parameters: type - SHA module type */
-/* Returns: 0 on success or other int error code on error */
-/* Side effects: */
-/* Description: */
-/* This routine performs various tests on the SHA HW and SW */
-/*----------------------------------------------------------------------------*/
-int npcm_sha_selftest(u8 type)
+void hw_sha384(const unsigned char *input, unsigned int len,
+ unsigned char *output, unsigned int chunk_sz)
{
- int status;
- struct SHA_HANDLE_T handle;
- u8 hashdigest[max(SHA_1_HASH_LENGTH, SHA_2_HASH_LENGTH)];
- u16 i, j;
-
- /*------------------------------------------------------------------------*/
- /* SHA1 tests info */
- /*------------------------------------------------------------------------*/
-
- static const u8 sha1selftestbuff[SHA1_NUM_OF_SELF_TESTS][94] = {
- {"abc"},
- {"abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"},
- {"0123456789012345678901234567890123456789012345678901234567890123"},
- {0x30, 0x5c, 0x30, 0x2c, 0x02, 0x01, 0x00, 0x30, 0x09, 0x06, 0x05, 0x2b,
- 0x0e, 0x03, 0x02, 0x1a, 0x05, 0x00, 0x30, 0x06, 0x06, 0x04, 0x67, 0x2a,
- 0x01, 0x0c, 0x04, 0x14, 0xe1, 0xb6, 0x93, 0xfe, 0x33, 0x43, 0xc1, 0x20,
- 0x5d, 0x4b, 0xaa, 0xb8, 0x63, 0xfb, 0xcf, 0x6c, 0x46, 0x1e, 0x88, 0x04,
- 0x30, 0x2c, 0x02, 0x01, 0x00, 0x30, 0x09, 0x06, 0x05, 0x2b, 0x0e, 0x03,
- 0x02, 0x1a, 0x05, 0x00, 0x30, 0x06, 0x06, 0x04, 0x67, 0x2a, 0x01, 0x0c,
- 0x04, 0x14, 0x13, 0xc1, 0x0c, 0xfc, 0xc8, 0x92, 0xd7, 0xde, 0x07, 0x1c,
- 0x40, 0xde, 0x4f, 0xcd, 0x07, 0x5b, 0x68, 0x20, 0x5a, 0x6c}
- };
-
- static const u8 sha1selftestbufflen[SHA1_NUM_OF_SELF_TESTS] = {
- 3, 56, 64, 94
- };
-
- static const u8 sha1selftestexpres[SHA1_NUM_OF_SELF_TESTS][SHA_1_HASH_LENGTH] = {
- {0xA9, 0x99, 0x3E, 0x36,
- 0x47, 0x06, 0x81, 0x6A,
- 0xBA, 0x3E, 0x25, 0x71,
- 0x78, 0x50, 0xC2, 0x6C,
- 0x9C, 0xD0, 0xD8, 0x9D},
- {0x84, 0x98, 0x3E, 0x44,
- 0x1C, 0x3B, 0xD2, 0x6E,
- 0xBA, 0xAE, 0x4A, 0xA1,
- 0xF9, 0x51, 0x29, 0xE5,
- 0xE5, 0x46, 0x70, 0xF1},
- {0xCF, 0x08, 0x00, 0xF7,
- 0x64, 0x4A, 0xCE, 0x3C,
- 0xB4, 0xC3, 0xFA, 0x33,
- 0x38, 0x8D, 0x3B, 0xA0,
- 0xEA, 0x3C, 0x8B, 0x6E},
- {0xc9, 0x84, 0x45, 0xc8,
- 0x64, 0x04, 0xb1, 0xe3,
- 0x3c, 0x6b, 0x0a, 0x8c,
- 0x8b, 0x80, 0x94, 0xfc,
- 0xf3, 0xc9, 0x98, 0xab}
- };
-
- /*------------------------------------------------------------------------*/
- /* SHA2 tests info */
- /*------------------------------------------------------------------------*/
-
- static const u8 sha2selftestbuff[SHA2_NUM_OF_SELF_TESTS][100] = {
- { "abc" },
- { "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq" },
- {'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a',
- 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a',
- 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a',
- 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a',
- 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a',
- 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a',
- 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a',
- 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a',
- 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a',
- 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a'}
- };
-
- static const u8 sha2selftestbufflen[SHA2_NUM_OF_SELF_TESTS] = {
- 3, 56, 100
- };
-
- static const u8 sha2selftestexpres[SHA2_NUM_OF_SELF_TESTS][SHA_2_HASH_LENGTH] = {
- /*
- * SHA-256 test vectors
- */
- { 0xBA, 0x78, 0x16, 0xBF, 0x8F, 0x01, 0xCF, 0xEA,
- 0x41, 0x41, 0x40, 0xDE, 0x5D, 0xAE, 0x22, 0x23,
- 0xB0, 0x03, 0x61, 0xA3, 0x96, 0x17, 0x7A, 0x9C,
- 0xB4, 0x10, 0xFF, 0x61, 0xF2, 0x00, 0x15, 0xAD },
- { 0x24, 0x8D, 0x6A, 0x61, 0xD2, 0x06, 0x38, 0xB8,
- 0xE5, 0xC0, 0x26, 0x93, 0x0C, 0x3E, 0x60, 0x39,
- 0xA3, 0x3C, 0xE4, 0x59, 0x64, 0xFF, 0x21, 0x67,
- 0xF6, 0xEC, 0xED, 0xD4, 0x19, 0xDB, 0x06, 0xC1 },
- { 0xCD, 0xC7, 0x6E, 0x5C, 0x99, 0x14, 0xFB, 0x92,
- 0x81, 0xA1, 0xC7, 0xE2, 0x84, 0xD7, 0x3E, 0x67,
- 0xF1, 0x80, 0x9A, 0x48, 0xA4, 0x97, 0x20, 0x0E,
- 0x04, 0x6D, 0x39, 0xCC, 0xC7, 0x11, 0x2C, 0xD0 },
- };
-
- if (type == npcm_sha_type_sha1) {
- /*--------------------------------------------------------------------*/
- /* SHA 1 TESTS */
- /*--------------------------------------------------------------------*/
- for (i = 0; i < SHA1_NUM_OF_SELF_TESTS; i++) {
- if (i != 3) {
- status = npcm_sha_calc(npcm_sha_type_sha1, sha1selftestbuff[i], sha1selftestbufflen[i], hashdigest);
- npcm_sha_check(status);
- } else {
- SHA_Power(true);
- SHA_Reset();
- status = SHA_Start(&handle, npcm_sha_type_sha1);
- npcm_sha_check(status);
- status = SHA_Update(&handle, sha1selftestbuff[i], 73);
- npcm_sha_check(status);
- status = SHA_Update(&handle, &sha1selftestbuff[i][73], sha1selftestbufflen[i] - 73);
- npcm_sha_check(status);
- status = SHA_Finish(&handle, hashdigest);
- npcm_sha_check(status);
- SHA_Power(false);
- }
-
- if (memcmp(hashdigest, sha1selftestexpres[i], SHA_1_HASH_LENGTH))
- return -1;
- }
-
- } else {
- /*--------------------------------------------------------------------*/
- /* SHA 2 TESTS */
- /*--------------------------------------------------------------------*/
- for (i = 0; i < SHA2_NUM_OF_SELF_TESTS; i++) {
- SHA_Power(true);
- SHA_Reset();
- status = SHA_Start(&handle, npcm_sha_type_sha2);
- npcm_sha_check(status);
- if (i == 2) {
- for (j = 0; j < 10000; j++) { //not working
- status = SHA_Update(&handle, sha2selftestbuff[i], sha2selftestbufflen[i]);
- npcm_sha_check(status);
- }
- } else {
- status = SHA_Update(&handle, sha2selftestbuff[i], sha2selftestbufflen[i]);
- npcm_sha_check(status);
- }
-
- status = SHA_Finish(&handle, hashdigest);
- npcm_sha_check(status);
- SHA_Power(false);
- if (memcmp(hashdigest, sha2selftestexpres[i], SHA_2_HASH_LENGTH))
- return -1;
-
- npcm_sha_calc(npcm_sha_type_sha2, sha2selftestbuff[i], sha2selftestbufflen[i], hashdigest);
- if (memcmp(hashdigest, sha2selftestexpres[i], SHA_2_HASH_LENGTH))
- return -1;
- }
+ if (!sha_priv->support_sha512) {
+ puts(" HW accelerator not support\n");
+ return;
}
-
- return 0;
+ puts(" using BMC HW accelerator\n");
+ npcm_sha_calc(input, len, output, type_sha384);
}
-/*----------------------------------------------------------------------------*/
-/* Function: SHA_FlushLocalBuffer_l */
-/* */
-/* Parameters: */
-/* Returns: none */
-/* Side effects: */
-/* Description: This routine flush secrun buffer to SHA module */
-/*----------------------------------------------------------------------------*/
-static void SHA_FlushLocalBuffer_l(const u32 *buff)
+void hw_sha256(const unsigned char *input, unsigned int len,
+ unsigned char *output, unsigned int chunk_sz)
{
- struct npcm_sha_regs *regs = sha_priv->regs;
- u32 i;
-
- for (i = 0; i < (SHA_BLOCK_LENGTH / sizeof(u32)); i++)
- writel(buff[i], ®s->hash_data_in);
+ puts(" using BMC HW accelerator\n");
+ npcm_sha_calc(input, len, output, type_sha256);
}
-/*----------------------------------------------------------------------------*/
-/* Function: SHA_BusyWait_l */
-/* */
-/* Parameters: */
-/* Returns: 0 if no error was found or DEFS_STATUS_ERROR otherwise */
-/* Side effects: */
-/* Description: This routine wait for SHA unit to no longer be busy */
-/*----------------------------------------------------------------------------*/
-static int SHA_BusyWait_l(void)
+void hw_sha1(const unsigned char *input, unsigned int len,
+ unsigned char *output, unsigned int chunk_sz)
{
- struct npcm_sha_regs *regs = sha_priv->regs;
- u32 timeout = SHA_TIMEOUT;
-
- do {
- if (timeout-- == 0)
- return -ETIMEDOUT;
- } while ((readb(®s->hash_ctr_sts) & HASH_CTR_STS_SHA_BUSY)
- == HASH_CTR_STS_SHA_BUSY);
-
- return 0;
+ puts(" using BMC HW accelerator\n");
+ npcm_sha_calc(input, len, output, type_sha1);
}
-/*----------------------------------------------------------------------------*/
-/* Function: SHA_GetShaDigest_l */
-/* */
-/* Parameters: hashDigest - buffer for the hash output. */
-/* type - SHA module type */
-/* Returns: none */
-/* Side effects: */
-/* Description: This routine copy the hash digest from the hardware */
-/* and into given buffer (in ram) */
-/*----------------------------------------------------------------------------*/
-static void SHA_GetShaDigest_l(u8 *hashdigest, u8 type)
+int hw_sha_init(struct hash_algo *algo, void **ctxp)
{
- struct npcm_sha_regs *regs = sha_priv->regs;
- u16 j;
- u8 len = SHA_HASH_LENGTH(type) / sizeof(u32);
-
- // Copy Bytes from SHA module to given buffer
- for (j = 0; j < len; j++)
- ((u32 *)hashdigest)[j] = readl(®s->hash_dig[j]);
-}
+ if (!strcmp("sha1", algo->name)) {
+ npcm_sha_init(type_sha1);
+ } else if (!strcmp("sha256", algo->name)) {
+ npcm_sha_init(type_sha256);
+ } else if (!strcmp("sha384", algo->name)) {
+ if (!sha_priv->support_sha512)
+ return -ENOTSUPP;
+ npcm_sha_init(type_sha384);
+ } else if (!strcmp("sha512", algo->name)) {
+ if (!sha_priv->support_sha512)
+ return -ENOTSUPP;
+ npcm_sha_init(type_sha512);
+ } else {
+ return -ENOTSUPP;
+ }
-/*----------------------------------------------------------------------------*/
-/* Function: SHA_SetShaDigest_l */
-/* */
-/* Parameters: hashDigest - input buffer to set as hash digest */
-/* type - SHA module type */
-/* Returns: none */
-/* Side effects: */
-/* Description: This routine set the hash digest in the hardware from */
-/* a given buffer (in ram) */
-/*----------------------------------------------------------------------------*/
-static void SHA_SetShaDigest_l(const u32 *hashdigest, u8 type)
-{
- struct npcm_sha_regs *regs = sha_priv->regs;
- u16 j;
- u8 len = SHA_HASH_LENGTH(type) / sizeof(u32);
+ printf("Using npcm SHA engine\n");
+ npcm_sha_reset();
+ npcm_sha_enable(true);
- // Copy Bytes from given buffer to SHA module
- for (j = 0; j < len; j++)
- writel(hashdigest[j], ®s->hash_dig[j]);
+ return 0;
}
-/*----------------------------------------------------------------------------*/
-/* Function: SHA_SetBlock_l */
-/* */
-/* Parameters: data - data to copy */
-/* len - size of data */
-/* position - byte offset into the block at which data */
-/* should be placed */
-/* block - block buffer */
-/* Returns: none */
-/* Side effects: */
-/* Description: This routine load bytes into block buffer */
-/*----------------------------------------------------------------------------*/
-static void SHA_SetBlock_l(const u8 *data, u32 len, u16 position, u32 *block)
+int hw_sha_update(struct hash_algo *algo, void *ctx, const void *buf,
+ unsigned int size, int is_last)
{
- u8 *dest = (u8 *)block;
-
- memcpy(dest + position, data, len);
+ return npcm_sha_update(buf, size);
}
-/*----------------------------------------------------------------------------*/
-/* Function: SHA_SetBlock_l */
-/* */
-/* Parameters: */
-/* len - size of data */
-/* position - byte offset into the block at which data */
-/* should be placed */
-/* block - block buffer */
-/* Returns: none */
-/* Side effects: */
-/* Description: This routine load zero's into the block buffer */
-/*----------------------------------------------------------------------------*/
-static void SHA_ClearBlock_l(u16 len, u16 position, u32 *block)
+int hw_sha_finish(struct hash_algo *algo, void *ctx, void *dest_buf,
+ int size)
{
- u8 *dest = (u8 *)block;
+ int ret;
- memset(dest + position, 0, len);
-}
-
-/*----------------------------------------------------------------------------*/
-/* Function: SHA_SetLength32_l */
-/* */
-/* Parameters: */
-/* handlePtr - SHA processing handle pointer */
-/* block - block buffer */
-/* Returns: none */
-/* Side effects: */
-/* Description: This routine set the length of the hash's data */
-/* len is the 32-bit byte length of the message */
-/*lint -efunc(734,SHA_SetLength32_l) Supperess loss of percision lint warning */
-/*----------------------------------------------------------------------------*/
-static void SHA_SetLength32_l(struct SHA_HANDLE_T *handleptr, u32 *block)
-{
- u16 *secrunbufferswappedptr = (u16 *)(void *)(block);
+ ret = npcm_sha_finish(dest_buf);
+ npcm_sha_enable(false);
- secrunbufferswappedptr[(SHA_BLOCK_LENGTH / sizeof(u16)) - 1] = (u16)
- ((handleptr->length0 << 3) << 8) | ((u16)(handleptr->length0 << 3) >> 8);
- secrunbufferswappedptr[(SHA_BLOCK_LENGTH / sizeof(u16)) - 2] = (u16)
- ((handleptr->length0 >> (16 - 3)) >> 8) | ((u16)(handleptr->length0 >> (16 - 3)) << 8);
- secrunbufferswappedptr[(SHA_BLOCK_LENGTH / sizeof(u16)) - 3] = (u16)
- ((handleptr->length1 << 3) << 8) | ((u16)(handleptr->length1 << 3) >> 8);
- secrunbufferswappedptr[(SHA_BLOCK_LENGTH / sizeof(u16)) - 4] = (u16)
- ((handleptr->length1 >> (16 - 3)) >> 8) | ((u16)(handleptr->length1 >> (16 - 3)) << 8);
+ return ret;
}
static int npcm_sha_bind(struct udevice *dev)
@@ -870,12 +347,15 @@
if (!sha_priv)
return -ENOMEM;
- sha_priv->regs = dev_remap_addr_index(dev, 0);
- if (!sha_priv->regs) {
+ sha_priv->base = dev_read_addr_ptr(dev);
+ if (!sha_priv->base) {
printf("Cannot find sha reg address, binding failed\n");
return -EINVAL;
}
+ if (IS_ENABLED(CONFIG_ARCH_NPCM8XX))
+ sha_priv->support_sha512 = true;
+
printf("SHA: NPCM SHA module bind OK\n");
return 0;
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index b2d7b49..b4ff033 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -193,6 +193,24 @@
This driver supports the XGMAC in Calxeda Highbank and Midway
machines.
+config DWC_ETH_XGMAC
+ bool "Synopsys DWC Ethernet XGMAC device support"
+ select PHYLIB
+ help
+ This driver supports the Synopsys Designware Ethernet XGMAC (10G
+ Ethernet MAC) IP block. The IP supports many options for bus type,
+ clocking/reset structure, and feature list.
+
+config DWC_ETH_XGMAC_SOCFPGA
+ bool "Synopsys DWC Ethernet XGMAC device support for SOCFPGA"
+ select REGMAP
+ select SYSCON
+ depends on DWC_ETH_XGMAC
+ default y if TARGET_SOCFPGA_AGILEX5
+ help
+ The Synopsys Designware Ethernet XGMAC IP block with specific
+ configuration used in Intel SoC FPGA chip.
+
config DRIVER_DM9000
bool "Davicom DM9000 controller driver"
help
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index dc34045..dce7168 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -22,6 +22,8 @@
obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
obj-$(CONFIG_DWC_ETH_QOS_ROCKCHIP) += dwc_eth_qos_rockchip.o
obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o
+obj-$(CONFIG_DWC_ETH_XGMAC) += dwc_eth_xgmac.o
+obj-$(CONFIG_DWC_ETH_XGMAC_SOCFPGA) += dwc_eth_xgmac_socfpga.o
obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o
obj-$(CONFIG_DWC_ETH_QOS_STM32) += dwc_eth_qos_stm32.o
obj-$(CONFIG_E1000) += e1000.o
diff --git a/drivers/net/dwc_eth_xgmac.c b/drivers/net/dwc_eth_xgmac.c
new file mode 100644
index 0000000..d3e5f92
--- /dev/null
+++ b/drivers/net/dwc_eth_xgmac.c
@@ -0,0 +1,1165 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023, Intel Corporation.
+ *
+ * Portions based on U-Boot's dwc_eth_qos.c.
+ */
+
+/*
+ * This driver supports the Synopsys Designware Ethernet XGMAC (10G Ethernet
+ * MAC) IP block. The IP supports multiple options for bus type, clocking/
+ * reset structure, and feature list.
+ *
+ * The driver is written such that generic core logic is kept separate from
+ * configuration-specific logic. Code that interacts with configuration-
+ * specific resources is split out into separate functions to avoid polluting
+ * common code. If/when this driver is enhanced to support multiple
+ * configurations, the core code should be adapted to call all configuration-
+ * specific functions through function pointers, with the definition of those
+ * function pointers being supplied by struct udevice_id xgmac_ids[]'s .data
+ * field.
+ *
+ * This configuration uses an AXI master/DMA bus, an AHB slave/register bus,
+ * contains the DMA, MTL, and MAC sub-blocks, and supports a single RGMII PHY.
+ * This configuration also has SW control over all clock and reset signals to
+ * the HW block.
+ */
+
+#define LOG_CATEGORY UCLASS_ETH
+
+#include <clk.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <errno.h>
+#include <eth_phy.h>
+#include <log.h>
+#include <malloc.h>
+#include <memalign.h>
+#include <miiphy.h>
+#include <net.h>
+#include <netdev.h>
+#include <phy.h>
+#include <reset.h>
+#include <wait_bit.h>
+#include <asm/cache.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+#include "dwc_eth_xgmac.h"
+
+static void *xgmac_alloc_descs(struct xgmac_priv *xgmac, unsigned int num)
+{
+ return memalign(ARCH_DMA_MINALIGN, num * xgmac->desc_size);
+}
+
+static void xgmac_free_descs(void *descs)
+{
+ free(descs);
+}
+
+static struct xgmac_desc *xgmac_get_desc(struct xgmac_priv *xgmac,
+ unsigned int num, bool rx)
+{
+ return (rx ? xgmac->rx_descs : xgmac->tx_descs) +
+ (num * xgmac->desc_size);
+}
+
+void xgmac_inval_desc_generic(void *desc)
+{
+ unsigned long start;
+ unsigned long end;
+
+ if (!desc) {
+ pr_err("%s invalid input buffer\n", __func__);
+ return;
+ }
+
+ start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
+ end = ALIGN(start + sizeof(struct xgmac_desc),
+ ARCH_DMA_MINALIGN);
+
+ invalidate_dcache_range(start, end);
+}
+
+void xgmac_flush_desc_generic(void *desc)
+{
+ unsigned long start;
+ unsigned long end;
+
+ if (!desc) {
+ pr_err("%s invalid input buffer\n", __func__);
+ return;
+ }
+
+ start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
+ end = ALIGN(start + sizeof(struct xgmac_desc),
+ ARCH_DMA_MINALIGN);
+
+ flush_dcache_range(start, end);
+}
+
+void xgmac_inval_buffer_generic(void *buf, size_t size)
+{
+ unsigned long start;
+ unsigned long end;
+
+ if (!buf) {
+ pr_err("%s invalid input buffer\n", __func__);
+ return;
+ }
+
+ start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
+ end = ALIGN((unsigned long)buf + size,
+ ARCH_DMA_MINALIGN);
+
+ invalidate_dcache_range(start, end);
+}
+
+void xgmac_flush_buffer_generic(void *buf, size_t size)
+{
+ unsigned long start;
+ unsigned long end;
+
+ if (!buf) {
+ pr_err("%s invalid input buffer\n", __func__);
+ return;
+ }
+
+ start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
+ end = ALIGN((unsigned long)buf + size,
+ ARCH_DMA_MINALIGN);
+
+ flush_dcache_range(start, end);
+}
+
+static int xgmac_mdio_wait_idle(struct xgmac_priv *xgmac)
+{
+ return wait_for_bit_le32(&xgmac->mac_regs->mdio_data,
+ XGMAC_MAC_MDIO_ADDRESS_SBUSY, false,
+ XGMAC_TIMEOUT_100MS, true);
+}
+
+static int xgmac_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad,
+ int mdio_reg)
+{
+ struct xgmac_priv *xgmac = bus->priv;
+ u32 val;
+ u32 hw_addr;
+ int ret;
+
+ debug("%s(dev=%p, addr=0x%x, reg=%d):\n", __func__, xgmac->dev, mdio_addr,
+ mdio_reg);
+
+ ret = xgmac_mdio_wait_idle(xgmac);
+ if (ret) {
+ pr_err("MDIO not idle at entry: %d\n", ret);
+ return ret;
+ }
+
+ /* Set clause 22 format */
+ val = BIT(mdio_addr);
+ writel(val, &xgmac->mac_regs->mdio_clause_22_port);
+
+ hw_addr = (mdio_addr << XGMAC_MAC_MDIO_ADDRESS_PA_SHIFT) |
+ (mdio_reg & XGMAC_MAC_MDIO_REG_ADDR_C22P_MASK);
+
+ val = xgmac->config->config_mac_mdio <<
+ XGMAC_MAC_MDIO_ADDRESS_CR_SHIFT;
+
+ val |= XGMAC_MAC_MDIO_ADDRESS_SADDR |
+ XGMAC_MDIO_SINGLE_CMD_ADDR_CMD_READ |
+ XGMAC_MAC_MDIO_ADDRESS_SBUSY;
+
+ ret = xgmac_mdio_wait_idle(xgmac);
+ if (ret) {
+ pr_err("MDIO not idle at entry: %d\n", ret);
+ return ret;
+ }
+
+ writel(hw_addr, &xgmac->mac_regs->mdio_address);
+ writel(val, &xgmac->mac_regs->mdio_data);
+
+ ret = xgmac_mdio_wait_idle(xgmac);
+ if (ret) {
+ pr_err("MDIO read didn't complete: %d\n", ret);
+ return ret;
+ }
+
+ val = readl(&xgmac->mac_regs->mdio_data);
+ val &= XGMAC_MAC_MDIO_DATA_GD_MASK;
+
+ debug("%s: val=0x%x\n", __func__, val);
+
+ return val;
+}
+
+static int xgmac_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad,
+ int mdio_reg, u16 mdio_val)
+{
+ struct xgmac_priv *xgmac = bus->priv;
+ u32 val;
+ u32 hw_addr;
+ int ret;
+
+ debug("%s(dev=%p, addr=0x%x, reg=%d, val=0x%x):\n", __func__, xgmac->dev,
+ mdio_addr, mdio_reg, mdio_val);
+
+ ret = xgmac_mdio_wait_idle(xgmac);
+ if (ret) {
+ pr_err("MDIO not idle at entry: %d\n", ret);
+ return ret;
+ }
+
+ /* Set clause 22 format */
+ val = BIT(mdio_addr);
+ writel(val, &xgmac->mac_regs->mdio_clause_22_port);
+
+ hw_addr = (mdio_addr << XGMAC_MAC_MDIO_ADDRESS_PA_SHIFT) |
+ (mdio_reg & XGMAC_MAC_MDIO_REG_ADDR_C22P_MASK);
+
+ hw_addr |= (mdio_reg >> XGMAC_MAC_MDIO_ADDRESS_PA_SHIFT) <<
+ XGMAC_MAC_MDIO_ADDRESS_DA_SHIFT;
+
+ val = (xgmac->config->config_mac_mdio <<
+ XGMAC_MAC_MDIO_ADDRESS_CR_SHIFT);
+
+ val |= XGMAC_MAC_MDIO_ADDRESS_SADDR |
+ mdio_val | XGMAC_MDIO_SINGLE_CMD_ADDR_CMD_WRITE |
+ XGMAC_MAC_MDIO_ADDRESS_SBUSY;
+
+ ret = xgmac_mdio_wait_idle(xgmac);
+ if (ret) {
+ pr_err("MDIO not idle at entry: %d\n", ret);
+ return ret;
+ }
+
+ writel(hw_addr, &xgmac->mac_regs->mdio_address);
+ writel(val, &xgmac->mac_regs->mdio_data);
+
+ ret = xgmac_mdio_wait_idle(xgmac);
+ if (ret) {
+ pr_err("MDIO write didn't complete: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int xgmac_set_full_duplex(struct udevice *dev)
+{
+ struct xgmac_priv *xgmac = dev_get_priv(dev);
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ clrbits_le32(&xgmac->mac_regs->mac_extended_conf, XGMAC_MAC_EXT_CONF_HD);
+
+ return 0;
+}
+
+static int xgmac_set_half_duplex(struct udevice *dev)
+{
+ struct xgmac_priv *xgmac = dev_get_priv(dev);
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ setbits_le32(&xgmac->mac_regs->mac_extended_conf, XGMAC_MAC_EXT_CONF_HD);
+
+ /* WAR: Flush TX queue when switching to half-duplex */
+ setbits_le32(&xgmac->mtl_regs->txq0_operation_mode,
+ XGMAC_MTL_TXQ0_OPERATION_MODE_FTQ);
+
+ return 0;
+}
+
+static int xgmac_set_gmii_speed(struct udevice *dev)
+{
+ struct xgmac_priv *xgmac = dev_get_priv(dev);
+ u32 val;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ val = XGMAC_MAC_CONF_SS_1G_GMII << XGMAC_MAC_CONF_SS_SHIFT;
+ writel(val, &xgmac->mac_regs->tx_configuration);
+
+ return 0;
+}
+
+static int xgmac_set_mii_speed_100(struct udevice *dev)
+{
+ struct xgmac_priv *xgmac = dev_get_priv(dev);
+ u32 val;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ val = XGMAC_MAC_CONF_SS_100M_MII << XGMAC_MAC_CONF_SS_SHIFT;
+ writel(val, &xgmac->mac_regs->tx_configuration);
+
+ return 0;
+}
+
+static int xgmac_set_mii_speed_10(struct udevice *dev)
+{
+ struct xgmac_priv *xgmac = dev_get_priv(dev);
+ u32 val;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ val = XGMAC_MAC_CONF_SS_2_10M_MII << XGMAC_MAC_CONF_SS_SHIFT;
+ writel(val, &xgmac->mac_regs->tx_configuration);
+
+ return 0;
+}
+
+static int xgmac_adjust_link(struct udevice *dev)
+{
+ struct xgmac_priv *xgmac = dev_get_priv(dev);
+ int ret;
+ bool en_calibration;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ if (xgmac->phy->duplex)
+ ret = xgmac_set_full_duplex(dev);
+ else
+ ret = xgmac_set_half_duplex(dev);
+ if (ret < 0) {
+ pr_err("xgmac_set_*_duplex() failed: %d\n", ret);
+ return ret;
+ }
+
+ switch (xgmac->phy->speed) {
+ case SPEED_1000:
+ en_calibration = true;
+ ret = xgmac_set_gmii_speed(dev);
+ break;
+ case SPEED_100:
+ en_calibration = true;
+ ret = xgmac_set_mii_speed_100(dev);
+ break;
+ case SPEED_10:
+ en_calibration = false;
+ ret = xgmac_set_mii_speed_10(dev);
+ break;
+ default:
+ pr_err("invalid speed %d\n", xgmac->phy->speed);
+ return -EINVAL;
+ }
+ if (ret < 0) {
+ pr_err("xgmac_set_*mii_speed*() failed: %d\n", ret);
+ return ret;
+ }
+
+ if (en_calibration) {
+ ret = xgmac->config->ops->xgmac_calibrate_pads(dev);
+ if (ret < 0) {
+ pr_err("xgmac_calibrate_pads() failed: %d\n",
+ ret);
+ return ret;
+ }
+ } else {
+ ret = xgmac->config->ops->xgmac_disable_calibration(dev);
+ if (ret < 0) {
+ pr_err("xgmac_disable_calibration() failed: %d\n",
+ ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int xgmac_write_hwaddr(struct udevice *dev)
+{
+ struct eth_pdata *plat = dev_get_plat(dev);
+ struct xgmac_priv *xgmac = dev_get_priv(dev);
+ u32 val;
+
+ /*
+ * This function may be called before start() or after stop(). At that
+ * time, on at least some configurations of the XGMAC HW, all clocks to
+ * the XGMAC HW block will be stopped, and a reset signal applied. If
+ * any register access is attempted in this state, bus timeouts or CPU
+ * hangs may occur. This check prevents that.
+ *
+ * A simple solution to this problem would be to not implement
+ * write_hwaddr(), since start() always writes the MAC address into HW
+ * anyway. However, it is desirable to implement write_hwaddr() to
+ * support the case of SW that runs subsequent to U-Boot which expects
+ * the MAC address to already be programmed into the XGMAC registers,
+ * which must happen irrespective of whether the U-Boot user (or
+ * scripts) actually made use of the XGMAC device, and hence
+ * irrespective of whether start() was ever called.
+ *
+ */
+ if (!xgmac->config->reg_access_always_ok && !xgmac->reg_access_ok)
+ return 0;
+
+ /* Update the MAC address */
+ val = (plat->enetaddr[5] << 8) |
+ (plat->enetaddr[4]);
+ writel(val, &xgmac->mac_regs->address0_high);
+ val = (plat->enetaddr[3] << 24) |
+ (plat->enetaddr[2] << 16) |
+ (plat->enetaddr[1] << 8) |
+ (plat->enetaddr[0]);
+ writel(val, &xgmac->mac_regs->address0_low);
+ return 0;
+}
+
+static int xgmac_read_rom_hwaddr(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct xgmac_priv *xgmac = dev_get_priv(dev);
+ int ret;
+
+ ret = xgmac->config->ops->xgmac_get_enetaddr(dev);
+ if (ret < 0)
+ return ret;
+
+ return !is_valid_ethaddr(pdata->enetaddr);
+}
+
+static int xgmac_get_phy_addr(struct xgmac_priv *priv, struct udevice *dev)
+{
+ struct ofnode_phandle_args phandle_args;
+ int reg;
+
+ if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+ &phandle_args)) {
+ debug("Failed to find phy-handle");
+ return -ENODEV;
+ }
+
+ priv->phy_of_node = phandle_args.node;
+
+ reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
+
+ return reg;
+}
+
+static int xgmac_start(struct udevice *dev)
+{
+ struct xgmac_priv *xgmac = dev_get_priv(dev);
+ int ret, i;
+ u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
+ ulong last_rx_desc;
+ ulong desc_pad;
+
+ struct xgmac_desc *tx_desc = NULL;
+ struct xgmac_desc *rx_desc = NULL;
+ int addr = -1;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ xgmac->tx_desc_idx = 0;
+ xgmac->rx_desc_idx = 0;
+
+ ret = xgmac->config->ops->xgmac_start_resets(dev);
+ if (ret < 0) {
+ pr_err("xgmac_start_resets() failed: %d\n", ret);
+ goto err;
+ }
+
+ xgmac->reg_access_ok = true;
+
+ ret = wait_for_bit_le32(&xgmac->dma_regs->mode,
+ XGMAC_DMA_MODE_SWR, false,
+ xgmac->config->swr_wait, false);
+ if (ret) {
+ pr_err("XGMAC_DMA_MODE_SWR stuck: %d\n", ret);
+ goto err_stop_resets;
+ }
+
+ ret = xgmac->config->ops->xgmac_calibrate_pads(dev);
+ if (ret < 0) {
+ pr_err("xgmac_calibrate_pads() failed: %d\n", ret);
+ goto err_stop_resets;
+ }
+
+ /*
+ * if PHY was already connected and configured,
+ * don't need to reconnect/reconfigure again
+ */
+ if (!xgmac->phy) {
+ addr = xgmac_get_phy_addr(xgmac, dev);
+ xgmac->phy = phy_connect(xgmac->mii, addr, dev,
+ xgmac->config->interface(dev));
+ if (!xgmac->phy) {
+ pr_err("phy_connect() failed\n");
+ goto err_stop_resets;
+ }
+
+ if (xgmac->max_speed) {
+ ret = phy_set_supported(xgmac->phy, xgmac->max_speed);
+ if (ret) {
+ pr_err("phy_set_supported() failed: %d\n", ret);
+ goto err_shutdown_phy;
+ }
+ }
+
+ xgmac->phy->node = xgmac->phy_of_node;
+ ret = phy_config(xgmac->phy);
+ if (ret < 0) {
+ pr_err("phy_config() failed: %d\n", ret);
+ goto err_shutdown_phy;
+ }
+ }
+
+ ret = phy_startup(xgmac->phy);
+ if (ret < 0) {
+ pr_err("phy_startup() failed: %d\n", ret);
+ goto err_shutdown_phy;
+ }
+
+ if (!xgmac->phy->link) {
+ pr_err("No link\n");
+ goto err_shutdown_phy;
+ }
+
+ ret = xgmac_adjust_link(dev);
+ if (ret < 0) {
+ pr_err("xgmac_adjust_link() failed: %d\n", ret);
+ goto err_shutdown_phy;
+ }
+
+ /* Configure MTL */
+
+ /* Enable Store and Forward mode for TX */
+ /* Program Tx operating mode */
+ setbits_le32(&xgmac->mtl_regs->txq0_operation_mode,
+ XGMAC_MTL_TXQ0_OPERATION_MODE_TSF |
+ (XGMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED <<
+ XGMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT));
+
+ /* Transmit Queue weight */
+ writel(0x10, &xgmac->mtl_regs->txq0_quantum_weight);
+
+ /* Enable Store and Forward mode for RX, since no jumbo frame */
+ setbits_le32(&xgmac->mtl_regs->rxq0_operation_mode,
+ XGMAC_MTL_RXQ0_OPERATION_MODE_RSF);
+
+ /* Transmit/Receive queue fifo size; use all RAM for 1 queue */
+ val = readl(&xgmac->mac_regs->hw_feature1);
+ tx_fifo_sz = (val >> XGMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) &
+ XGMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK;
+ rx_fifo_sz = (val >> XGMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) &
+ XGMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK;
+
+ /*
+ * r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting.
+ * r/tqs is encoded as (n / 256) - 1.
+ */
+ tqs = (128 << tx_fifo_sz) / 256 - 1;
+ rqs = (128 << rx_fifo_sz) / 256 - 1;
+
+ clrsetbits_le32(&xgmac->mtl_regs->txq0_operation_mode,
+ XGMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK <<
+ XGMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT,
+ tqs << XGMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT);
+ clrsetbits_le32(&xgmac->mtl_regs->rxq0_operation_mode,
+ XGMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK <<
+ XGMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT,
+ rqs << XGMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT);
+
+ setbits_le32(&xgmac->mtl_regs->rxq0_operation_mode,
+ XGMAC_MTL_RXQ0_OPERATION_MODE_EHFC);
+
+ /* Configure MAC */
+ clrsetbits_le32(&xgmac->mac_regs->rxq_ctrl0,
+ XGMAC_MAC_RXQ_CTRL0_RXQ0EN_MASK <<
+ XGMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT,
+ xgmac->config->config_mac <<
+ XGMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
+
+ /* Multicast and Broadcast Queue Enable */
+ setbits_le32(&xgmac->mac_regs->rxq_ctrl1,
+ XGMAC_MAC_RXQ_CTRL1_MCBCQEN);
+
+ /* enable promise mode and receive all mode */
+ setbits_le32(&xgmac->mac_regs->mac_packet_filter,
+ XGMAC_MAC_PACKET_FILTER_RA |
+ XGMAC_MAC_PACKET_FILTER_PR);
+
+ /* Set TX flow control parameters */
+ /* Set Pause Time */
+ setbits_le32(&xgmac->mac_regs->q0_tx_flow_ctrl,
+ XGMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK <<
+ XGMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT);
+
+ /* Assign priority for RX flow control */
+ clrbits_le32(&xgmac->mac_regs->rxq_ctrl2,
+ XGMAC_MAC_RXQ_CTRL2_PSRQ0_MASK <<
+ XGMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT);
+
+ /* Enable flow control */
+ setbits_le32(&xgmac->mac_regs->q0_tx_flow_ctrl,
+ XGMAC_MAC_Q0_TX_FLOW_CTRL_TFE);
+ setbits_le32(&xgmac->mac_regs->rx_flow_ctrl,
+ XGMAC_MAC_RX_FLOW_CTRL_RFE);
+
+ clrbits_le32(&xgmac->mac_regs->tx_configuration,
+ XGMAC_MAC_CONF_JD);
+
+ clrbits_le32(&xgmac->mac_regs->rx_configuration,
+ XGMAC_MAC_CONF_JE |
+ XGMAC_MAC_CONF_GPSLCE |
+ XGMAC_MAC_CONF_WD);
+
+ setbits_le32(&xgmac->mac_regs->rx_configuration,
+ XGMAC_MAC_CONF_ACS |
+ XGMAC_MAC_CONF_CST);
+
+ ret = xgmac_write_hwaddr(dev);
+ if (ret < 0) {
+ pr_err("xgmac_write_hwaddr() failed: %d\n", ret);
+ goto err;
+ }
+
+ /* Configure DMA */
+ clrsetbits_le32(&xgmac->dma_regs->sysbus_mode,
+ XGMAC_DMA_SYSBUS_MODE_AAL,
+ XGMAC_DMA_SYSBUS_MODE_EAME |
+ XGMAC_DMA_SYSBUS_MODE_UNDEF);
+
+ /* Enable OSP mode */
+ setbits_le32(&xgmac->dma_regs->ch0_tx_control,
+ XGMAC_DMA_CH0_TX_CONTROL_OSP);
+
+ /* RX buffer size. Must be a multiple of bus width */
+ clrsetbits_le32(&xgmac->dma_regs->ch0_rx_control,
+ XGMAC_DMA_CH0_RX_CONTROL_RBSZ_MASK <<
+ XGMAC_DMA_CH0_RX_CONTROL_RBSZ_SHIFT,
+ XGMAC_MAX_PACKET_SIZE <<
+ XGMAC_DMA_CH0_RX_CONTROL_RBSZ_SHIFT);
+
+ desc_pad = (xgmac->desc_size - sizeof(struct xgmac_desc)) /
+ xgmac->config->axi_bus_width;
+
+ setbits_le32(&xgmac->dma_regs->ch0_control,
+ XGMAC_DMA_CH0_CONTROL_PBLX8 |
+ (desc_pad << XGMAC_DMA_CH0_CONTROL_DSL_SHIFT));
+
+ /*
+ * Burst length must be < 1/2 FIFO size.
+ * FIFO size in tqs is encoded as (n / 256) - 1.
+ * Each burst is n * 8 (PBLX8) * 16 (AXI width) == 128 bytes.
+ * Half of n * 256 is n * 128, so pbl == tqs, modulo the -1.
+ */
+ pbl = tqs + 1;
+ if (pbl > 32)
+ pbl = 32;
+
+ clrsetbits_le32(&xgmac->dma_regs->ch0_tx_control,
+ XGMAC_DMA_CH0_TX_CONTROL_TXPBL_MASK <<
+ XGMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT,
+ pbl << XGMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT);
+
+ clrsetbits_le32(&xgmac->dma_regs->ch0_rx_control,
+ XGMAC_DMA_CH0_RX_CONTROL_RXPBL_MASK <<
+ XGMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT,
+ 8 << XGMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT);
+
+ /* DMA performance configuration */
+ val = (XGMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK <<
+ XGMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) |
+ (XGMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK <<
+ XGMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT) |
+ XGMAC_DMA_SYSBUS_MODE_EAME |
+ XGMAC_DMA_SYSBUS_MODE_BLEN16 |
+ XGMAC_DMA_SYSBUS_MODE_BLEN8 |
+ XGMAC_DMA_SYSBUS_MODE_BLEN4 |
+ XGMAC_DMA_SYSBUS_MODE_BLEN32;
+
+ writel(val, &xgmac->dma_regs->sysbus_mode);
+
+ /* Set up descriptors */
+
+ memset(xgmac->tx_descs, 0, xgmac->desc_size * XGMAC_DESCRIPTORS_TX);
+ memset(xgmac->rx_descs, 0, xgmac->desc_size * XGMAC_DESCRIPTORS_RX);
+
+ for (i = 0; i < XGMAC_DESCRIPTORS_TX; i++) {
+ tx_desc = (struct xgmac_desc *)xgmac_get_desc(xgmac, i, false);
+
+ xgmac->config->ops->xgmac_flush_desc(tx_desc);
+ }
+
+ for (i = 0; i < XGMAC_DESCRIPTORS_RX; i++) {
+ rx_desc = (struct xgmac_desc *)xgmac_get_desc(xgmac, i, true);
+
+ rx_desc->des0 = (uintptr_t)(xgmac->rx_dma_buf +
+ (i * XGMAC_MAX_PACKET_SIZE));
+ rx_desc->des3 = XGMAC_DESC3_OWN;
+ /* Flush the cache to the memory */
+ mb();
+ xgmac->config->ops->xgmac_flush_desc(rx_desc);
+ xgmac->config->ops->xgmac_inval_buffer(xgmac->rx_dma_buf +
+ (i * XGMAC_MAX_PACKET_SIZE),
+ XGMAC_MAX_PACKET_SIZE);
+ }
+
+ writel(0, &xgmac->dma_regs->ch0_txdesc_list_haddress);
+ writel((ulong)xgmac_get_desc(xgmac, 0, false),
+ &xgmac->dma_regs->ch0_txdesc_list_address);
+ writel(XGMAC_DESCRIPTORS_TX - 1,
+ &xgmac->dma_regs->ch0_txdesc_ring_length);
+ writel(0, &xgmac->dma_regs->ch0_rxdesc_list_haddress);
+ writel((ulong)xgmac_get_desc(xgmac, 0, true),
+ &xgmac->dma_regs->ch0_rxdesc_list_address);
+ writel(XGMAC_DESCRIPTORS_RX - 1,
+ &xgmac->dma_regs->ch0_rxdesc_ring_length);
+
+ /* Enable everything */
+ setbits_le32(&xgmac->dma_regs->ch0_tx_control,
+ XGMAC_DMA_CH0_TX_CONTROL_ST);
+ setbits_le32(&xgmac->dma_regs->ch0_rx_control,
+ XGMAC_DMA_CH0_RX_CONTROL_SR);
+ setbits_le32(&xgmac->mac_regs->tx_configuration,
+ XGMAC_MAC_CONF_TE);
+ setbits_le32(&xgmac->mac_regs->rx_configuration,
+ XGMAC_MAC_CONF_RE);
+
+ /* TX tail pointer not written until we need to TX a packet */
+ /*
+ * Point RX tail pointer at last descriptor. Ideally, we'd point at the
+ * first descriptor, implying all descriptors were available. However,
+ * that's not distinguishable from none of the descriptors being
+ * available.
+ */
+ last_rx_desc = (ulong)xgmac_get_desc(xgmac, XGMAC_DESCRIPTORS_RX - 1, true);
+ writel(last_rx_desc, &xgmac->dma_regs->ch0_rxdesc_tail_pointer);
+
+ xgmac->started = true;
+
+ debug("%s: OK\n", __func__);
+ return 0;
+
+err_shutdown_phy:
+ phy_shutdown(xgmac->phy);
+err_stop_resets:
+ xgmac->config->ops->xgmac_stop_resets(dev);
+err:
+ pr_err("FAILED: %d\n", ret);
+ return ret;
+}
+
+static void xgmac_stop(struct udevice *dev)
+{
+ struct xgmac_priv *xgmac = dev_get_priv(dev);
+ unsigned long start_time;
+ u32 val;
+ u32 trcsts;
+ u32 txqsts;
+ u32 prxq;
+ u32 rxqsts;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ if (!xgmac->started)
+ return;
+ xgmac->started = false;
+ xgmac->reg_access_ok = false;
+
+ /* Disable TX DMA */
+ clrbits_le32(&xgmac->dma_regs->ch0_tx_control,
+ XGMAC_DMA_CH0_TX_CONTROL_ST);
+
+ /* Wait for TX all packets to drain out of MTL */
+ start_time = get_timer(0);
+
+ while (get_timer(start_time) < XGMAC_TIMEOUT_100MS) {
+ val = readl(&xgmac->mtl_regs->txq0_debug);
+
+ trcsts = (val >> XGMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) &
+ XGMAC_MTL_TXQ0_DEBUG_TRCSTS_MASK;
+
+ txqsts = val & XGMAC_MTL_TXQ0_DEBUG_TXQSTS;
+
+ if (trcsts != XGMAC_MTL_TXQ0_DEBUG_TRCSTS_READ_STATE && !txqsts)
+ break;
+ }
+
+ /* Turn off MAC TX and RX */
+ clrbits_le32(&xgmac->mac_regs->tx_configuration,
+ XGMAC_MAC_CONF_RE);
+ clrbits_le32(&xgmac->mac_regs->rx_configuration,
+ XGMAC_MAC_CONF_RE);
+
+ /* Wait for all RX packets to drain out of MTL */
+ start_time = get_timer(0);
+
+ while (get_timer(start_time) < XGMAC_TIMEOUT_100MS) {
+ val = readl(&xgmac->mtl_regs->rxq0_debug);
+
+ prxq = (val >> XGMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT) &
+ XGMAC_MTL_RXQ0_DEBUG_PRXQ_MASK;
+
+ rxqsts = (val >> XGMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) &
+ XGMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK;
+
+ if (!prxq && !rxqsts)
+ break;
+ }
+
+ /* Turn off RX DMA */
+ clrbits_le32(&xgmac->dma_regs->ch0_rx_control,
+ XGMAC_DMA_CH0_RX_CONTROL_SR);
+
+ if (xgmac->phy)
+ phy_shutdown(xgmac->phy);
+
+ xgmac->config->ops->xgmac_stop_resets(dev);
+
+ debug("%s: OK\n", __func__);
+}
+
+static int xgmac_send(struct udevice *dev, void *packet, int length)
+{
+ struct xgmac_priv *xgmac = dev_get_priv(dev);
+ struct xgmac_desc *tx_desc;
+ unsigned long start_time;
+
+ debug("%s(dev=%p, packet=%p, length=%d):\n", __func__, dev, packet,
+ length);
+
+ memcpy(xgmac->tx_dma_buf, packet, length);
+ xgmac->config->ops->xgmac_flush_buffer(xgmac->tx_dma_buf, length);
+
+ tx_desc = xgmac_get_desc(xgmac, xgmac->tx_desc_idx, false);
+ xgmac->tx_desc_idx++;
+ xgmac->tx_desc_idx %= XGMAC_DESCRIPTORS_TX;
+
+ tx_desc->des0 = (ulong)xgmac->tx_dma_buf;
+ tx_desc->des1 = 0;
+ tx_desc->des2 = length;
+ /*
+ * Make sure that if HW sees the _OWN write below, it will see all the
+ * writes to the rest of the descriptor too.
+ */
+ mb();
+ tx_desc->des3 = XGMAC_DESC3_OWN | XGMAC_DESC3_FD | XGMAC_DESC3_LD | length;
+ xgmac->config->ops->xgmac_flush_desc(tx_desc);
+
+ writel((ulong)xgmac_get_desc(xgmac, xgmac->tx_desc_idx, false),
+ &xgmac->dma_regs->ch0_txdesc_tail_pointer);
+
+ start_time = get_timer(0);
+
+ while (get_timer(start_time) < XGMAC_TIMEOUT_100MS) {
+ xgmac->config->ops->xgmac_inval_desc(tx_desc);
+ if (!(readl(&tx_desc->des3) & XGMAC_DESC3_OWN))
+ return 0;
+ }
+ debug("%s: TX timeout\n", __func__);
+
+ return -ETIMEDOUT;
+}
+
+static int xgmac_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct xgmac_priv *xgmac = dev_get_priv(dev);
+ struct xgmac_desc *rx_desc;
+ int length;
+
+ debug("%s(dev=%p, flags=0x%x):\n", __func__, dev, flags);
+
+ rx_desc = xgmac_get_desc(xgmac, xgmac->rx_desc_idx, true);
+ xgmac->config->ops->xgmac_inval_desc(rx_desc);
+ if (rx_desc->des3 & XGMAC_DESC3_OWN) {
+ debug("%s: RX packet not available\n", __func__);
+ return -EAGAIN;
+ }
+
+ *packetp = xgmac->rx_dma_buf +
+ (xgmac->rx_desc_idx * XGMAC_MAX_PACKET_SIZE);
+ length = rx_desc->des3 & XGMAC_RDES3_PKT_LENGTH_MASK;
+ debug("%s: *packetp=%p, length=%d\n", __func__, *packetp, length);
+
+ xgmac->config->ops->xgmac_inval_buffer(*packetp, length);
+
+ return length;
+}
+
+static int xgmac_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+ struct xgmac_priv *xgmac = dev_get_priv(dev);
+ u32 idx, idx_mask = xgmac->desc_per_cacheline - 1;
+ uchar *packet_expected;
+ struct xgmac_desc *rx_desc;
+
+ debug("%s(packet=%p, length=%d)\n", __func__, packet, length);
+
+ packet_expected = xgmac->rx_dma_buf +
+ (xgmac->rx_desc_idx * XGMAC_MAX_PACKET_SIZE);
+ if (packet != packet_expected) {
+ debug("%s: Unexpected packet (expected %p)\n", __func__,
+ packet_expected);
+ return -EINVAL;
+ }
+
+ xgmac->config->ops->xgmac_inval_buffer(packet, length);
+
+ if ((xgmac->rx_desc_idx & idx_mask) == idx_mask) {
+ for (idx = xgmac->rx_desc_idx - idx_mask;
+ idx <= xgmac->rx_desc_idx;
+ idx++) {
+ rx_desc = xgmac_get_desc(xgmac, idx, true);
+ rx_desc->des0 = 0;
+ /* Flush the cache to the memory */
+ mb();
+ xgmac->config->ops->xgmac_flush_desc(rx_desc);
+ xgmac->config->ops->xgmac_inval_buffer(packet, length);
+ rx_desc->des0 = (u32)(ulong)(xgmac->rx_dma_buf +
+ (idx * XGMAC_MAX_PACKET_SIZE));
+ rx_desc->des1 = 0;
+ rx_desc->des2 = 0;
+ /*
+ * Make sure that if HW sees the _OWN write below,
+ * it will see all the writes to the rest of the
+ * descriptor too.
+ */
+ mb();
+ rx_desc->des3 = XGMAC_DESC3_OWN;
+ xgmac->config->ops->xgmac_flush_desc(rx_desc);
+ }
+ writel((ulong)rx_desc, &xgmac->dma_regs->ch0_rxdesc_tail_pointer);
+ }
+
+ xgmac->rx_desc_idx++;
+ xgmac->rx_desc_idx %= XGMAC_DESCRIPTORS_RX;
+
+ return 0;
+}
+
+static int xgmac_probe_resources_core(struct udevice *dev)
+{
+ struct xgmac_priv *xgmac = dev_get_priv(dev);
+ unsigned int desc_step;
+ int ret;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ /* Maximum distance between neighboring descriptors, in Bytes. */
+ desc_step = sizeof(struct xgmac_desc);
+
+ if (desc_step < ARCH_DMA_MINALIGN) {
+ /*
+ * The hardware implementation cannot place one descriptor
+ * per cacheline, it is necessary to place multiple descriptors
+ * per cacheline in memory and do cache management carefully.
+ */
+ xgmac->desc_size = BIT(fls(desc_step) - 1);
+ } else {
+ xgmac->desc_size = ALIGN(sizeof(struct xgmac_desc),
+ (unsigned int)ARCH_DMA_MINALIGN);
+ }
+ xgmac->desc_per_cacheline = ARCH_DMA_MINALIGN / xgmac->desc_size;
+
+ xgmac->tx_descs = xgmac_alloc_descs(xgmac, XGMAC_DESCRIPTORS_TX);
+ if (!xgmac->tx_descs) {
+ debug("%s: xgmac_alloc_descs(tx) failed\n", __func__);
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ xgmac->rx_descs = xgmac_alloc_descs(xgmac, XGMAC_DESCRIPTORS_RX);
+ if (!xgmac->rx_descs) {
+ debug("%s: xgmac_alloc_descs(rx) failed\n", __func__);
+ ret = -ENOMEM;
+ goto err_free_tx_descs;
+ }
+
+ xgmac->tx_dma_buf = memalign(XGMAC_BUFFER_ALIGN, XGMAC_MAX_PACKET_SIZE);
+ if (!xgmac->tx_dma_buf) {
+ debug("%s: memalign(tx_dma_buf) failed\n", __func__);
+ ret = -ENOMEM;
+ goto err_free_descs;
+ }
+ debug("%s: tx_dma_buf=%p\n", __func__, xgmac->tx_dma_buf);
+
+ xgmac->rx_dma_buf = memalign(XGMAC_BUFFER_ALIGN, XGMAC_RX_BUFFER_SIZE);
+ if (!xgmac->rx_dma_buf) {
+ debug("%s: memalign(rx_dma_buf) failed\n", __func__);
+ ret = -ENOMEM;
+ goto err_free_tx_dma_buf;
+ }
+ debug("%s: rx_dma_buf=%p\n", __func__, xgmac->rx_dma_buf);
+
+ xgmac->rx_pkt = malloc(XGMAC_MAX_PACKET_SIZE);
+ if (!xgmac->rx_pkt) {
+ debug("%s: malloc(rx_pkt) failed\n", __func__);
+ ret = -ENOMEM;
+ goto err_free_rx_dma_buf;
+ }
+ debug("%s: rx_pkt=%p\n", __func__, xgmac->rx_pkt);
+
+ xgmac->config->ops->xgmac_inval_buffer(xgmac->rx_dma_buf,
+ XGMAC_MAX_PACKET_SIZE * XGMAC_DESCRIPTORS_RX);
+
+ debug("%s: OK\n", __func__);
+ return 0;
+
+err_free_rx_dma_buf:
+ free(xgmac->rx_dma_buf);
+err_free_tx_dma_buf:
+ free(xgmac->tx_dma_buf);
+err_free_descs:
+ xgmac_free_descs(xgmac->rx_descs);
+err_free_tx_descs:
+ xgmac_free_descs(xgmac->tx_descs);
+err:
+
+ debug("%s: returns %d\n", __func__, ret);
+ return ret;
+}
+
+static int xgmac_remove_resources_core(struct udevice *dev)
+{
+ struct xgmac_priv *xgmac = dev_get_priv(dev);
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ free(xgmac->rx_pkt);
+ free(xgmac->rx_dma_buf);
+ free(xgmac->tx_dma_buf);
+ xgmac_free_descs(xgmac->rx_descs);
+ xgmac_free_descs(xgmac->tx_descs);
+
+ debug("%s: OK\n", __func__);
+ return 0;
+}
+
+/* board-specific Ethernet Interface initializations. */
+__weak int board_interface_eth_init(struct udevice *dev,
+ phy_interface_t interface_type)
+{
+ return 0;
+}
+
+static int xgmac_probe(struct udevice *dev)
+{
+ struct xgmac_priv *xgmac = dev_get_priv(dev);
+ int ret;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ xgmac->dev = dev;
+ xgmac->config = (void *)dev_get_driver_data(dev);
+
+ xgmac->regs = dev_read_addr(dev);
+ if (xgmac->regs == FDT_ADDR_T_NONE) {
+ pr_err("dev_read_addr() failed\n");
+ return -ENODEV;
+ }
+ xgmac->mac_regs = (void *)(xgmac->regs + XGMAC_MAC_REGS_BASE);
+ xgmac->mtl_regs = (void *)(xgmac->regs + XGMAC_MTL_REGS_BASE);
+ xgmac->dma_regs = (void *)(xgmac->regs + XGMAC_DMA_REGS_BASE);
+
+ xgmac->max_speed = dev_read_u32_default(dev, "max-speed", 0);
+
+ ret = xgmac_probe_resources_core(dev);
+ if (ret < 0) {
+ pr_err("xgmac_probe_resources_core() failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = xgmac->config->ops->xgmac_probe_resources(dev);
+ if (ret < 0) {
+ pr_err("xgmac_probe_resources() failed: %d\n", ret);
+ goto err_remove_resources_core;
+ }
+
+ ret = xgmac->config->ops->xgmac_start_clks(dev);
+ if (ret < 0) {
+ pr_err("xgmac_start_clks() failed: %d\n", ret);
+ return ret;
+ }
+
+ if (IS_ENABLED(CONFIG_DM_ETH_PHY))
+ xgmac->mii = eth_phy_get_mdio_bus(dev);
+
+ if (!xgmac->mii) {
+ xgmac->mii = mdio_alloc();
+ if (!xgmac->mii) {
+ pr_err("mdio_alloc() failed\n");
+ ret = -ENOMEM;
+ goto err_stop_clks;
+ }
+ xgmac->mii->read = xgmac_mdio_read;
+ xgmac->mii->write = xgmac_mdio_write;
+ xgmac->mii->priv = xgmac;
+ strcpy(xgmac->mii->name, dev->name);
+
+ ret = mdio_register(xgmac->mii);
+ if (ret < 0) {
+ pr_err("mdio_register() failed: %d\n", ret);
+ goto err_free_mdio;
+ }
+ }
+
+ if (IS_ENABLED(CONFIG_DM_ETH_PHY))
+ eth_phy_set_mdio_bus(dev, xgmac->mii);
+
+ debug("%s: OK\n", __func__);
+ return 0;
+
+err_free_mdio:
+ mdio_free(xgmac->mii);
+err_stop_clks:
+ xgmac->config->ops->xgmac_stop_clks(dev);
+err_remove_resources_core:
+ xgmac_remove_resources_core(dev);
+
+ debug("%s: returns %d\n", __func__, ret);
+ return ret;
+}
+
+static int xgmac_remove(struct udevice *dev)
+{
+ struct xgmac_priv *xgmac = dev_get_priv(dev);
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ mdio_unregister(xgmac->mii);
+ mdio_free(xgmac->mii);
+ xgmac->config->ops->xgmac_stop_clks(dev);
+ xgmac->config->ops->xgmac_remove_resources(dev);
+
+ xgmac_remove_resources_core(dev);
+
+ debug("%s: OK\n", __func__);
+ return 0;
+}
+
+int xgmac_null_ops(struct udevice *dev)
+{
+ return 0;
+}
+
+static const struct eth_ops xgmac_ops = {
+ .start = xgmac_start,
+ .stop = xgmac_stop,
+ .send = xgmac_send,
+ .recv = xgmac_recv,
+ .free_pkt = xgmac_free_pkt,
+ .write_hwaddr = xgmac_write_hwaddr,
+ .read_rom_hwaddr = xgmac_read_rom_hwaddr,
+};
+
+static const struct udevice_id xgmac_ids[] = {
+ {
+ .compatible = "intel,socfpga-dwxgmac",
+ .data = (ulong)&xgmac_socfpga_config
+ },
+ { }
+};
+
+U_BOOT_DRIVER(eth_xgmac) = {
+ .name = "eth_xgmac",
+ .id = UCLASS_ETH,
+ .of_match = of_match_ptr(xgmac_ids),
+ .probe = xgmac_probe,
+ .remove = xgmac_remove,
+ .ops = &xgmac_ops,
+ .priv_auto = sizeof(struct xgmac_priv),
+ .plat_auto = sizeof(struct eth_pdata),
+};
diff --git a/drivers/net/dwc_eth_xgmac.h b/drivers/net/dwc_eth_xgmac.h
new file mode 100644
index 0000000..259f815
--- /dev/null
+++ b/drivers/net/dwc_eth_xgmac.h
@@ -0,0 +1,298 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2023 Intel Coporation.
+ */
+
+#include <phy_interface.h>
+#include <linux/bitops.h>
+
+/* Core registers */
+
+#define XGMAC_MAC_REGS_BASE 0x000
+
+struct xgmac_mac_regs {
+ u32 tx_configuration; /* 0x000 */
+ u32 rx_configuration; /* 0x004 */
+ u32 mac_packet_filter; /* 0x008 */
+ u32 unused_00c[(0x070 - 0x00c) / 4]; /* 0x00c */
+ u32 q0_tx_flow_ctrl; /* 0x070 */
+ u32 unused_070[(0x090 - 0x074) / 4]; /* 0x074 */
+ u32 rx_flow_ctrl; /* 0x090 */
+ u32 unused_094[(0x0a0 - 0x094) / 4]; /* 0x094 */
+ u32 rxq_ctrl0; /* 0x0a0 */
+ u32 rxq_ctrl1; /* 0x0a4 */
+ u32 rxq_ctrl2; /* 0x0a8 */
+ u32 unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */
+ u32 us_tic_counter; /* 0x0dc */
+ u32 unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */
+ u32 hw_feature0; /* 0x11c */
+ u32 hw_feature1; /* 0x120 */
+ u32 hw_feature2; /* 0x124 */
+ u32 hw_feature3; /* 0x128 */
+ u32 hw_feature4; /* 0x12c */
+ u32 unused_130[(0x140 - 0x130) / 4]; /* 0x130 */
+ u32 mac_extended_conf; /* 0x140 */
+ u32 unused_144[(0x200 - 0x144) / 4]; /* 0x144 */
+ u32 mdio_address; /* 0x200 */
+ u32 mdio_data; /* 0x204 */
+ u32 mdio_cont_write_addr; /* 0x208 */
+ u32 mdio_cont_write_data; /* 0x20c */
+ u32 mdio_cont_scan_port_enable; /* 0x210 */
+ u32 mdio_intr_status; /* 0x214 */
+ u32 mdio_intr_enable; /* 0x218 */
+ u32 mdio_port_cnct_dsnct_status; /* 0x21c */
+ u32 mdio_clause_22_port; /* 0x220 */
+ u32 unused_224[(0x300 - 0x224) / 4]; /* 0x224 */
+ u32 address0_high; /* 0x300 */
+ u32 address0_low; /* 0x304 */
+};
+
+#define XGMAC_TIMEOUT_100MS 100000
+#define XGMAC_MAC_CONF_SS_SHIFT 29
+#define XGMAC_MAC_CONF_SS_10G_XGMII 0
+#define XGMAC_MAC_CONF_SS_2_5G_GMII 2
+#define XGMAC_MAC_CONF_SS_1G_GMII 3
+#define XGMAC_MAC_CONF_SS_100M_MII 4
+#define XGMAC_MAC_CONF_SS_5G_XGMII 5
+#define XGMAC_MAC_CONF_SS_2_5G_XGMII 6
+#define XGMAC_MAC_CONF_SS_2_10M_MII 7
+
+#define XGMAC_MAC_CONF_JD BIT(16)
+#define XGMAC_MAC_CONF_JE BIT(8)
+#define XGMAC_MAC_CONF_WD BIT(7)
+#define XGMAC_MAC_CONF_GPSLCE BIT(6)
+#define XGMAC_MAC_CONF_CST BIT(2)
+#define XGMAC_MAC_CONF_ACS BIT(1)
+#define XGMAC_MAC_CONF_TE BIT(0)
+#define XGMAC_MAC_CONF_RE BIT(0)
+
+#define XGMAC_MAC_EXT_CONF_HD BIT(24)
+
+#define XGMAC_MAC_PACKET_FILTER_RA BIT(31)
+#define XGMAC_MAC_PACKET_FILTER_PR BIT(0)
+
+#define XGMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16
+#define XGMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK GENMASK(15, 0)
+#define XGMAC_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1)
+
+#define XGMAC_MAC_RX_FLOW_CTRL_RFE BIT(0)
+#define XGMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0
+#define XGMAC_MAC_RXQ_CTRL0_RXQ0EN_MASK GENMASK(1, 0)
+#define XGMAC_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
+#define XGMAC_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
+#define XGMAC_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
+
+#define XGMAC_MAC_RXQ_CTRL1_MCBCQEN BIT(15)
+
+#define XGMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
+#define XGMAC_MAC_RXQ_CTRL2_PSRQ0_MASK GENMASK(7, 0)
+
+#define XGMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6
+#define XGMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK GENMASK(4, 0)
+#define XGMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0
+#define XGMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK GENMASK(4, 0)
+
+#define XGMAC_MDIO_SINGLE_CMD_SHIFT 16
+#define XGMAC_MDIO_SINGLE_CMD_ADDR_CMD_READ 3 << XGMAC_MDIO_SINGLE_CMD_SHIFT
+#define XGMAC_MDIO_SINGLE_CMD_ADDR_CMD_WRITE BIT(16)
+#define XGMAC_MAC_MDIO_ADDRESS_PA_SHIFT 16
+#define XGMAC_MAC_MDIO_ADDRESS_PA_MASK GENMASK(15, 0)
+#define XGMAC_MAC_MDIO_ADDRESS_DA_SHIFT 21
+#define XGMAC_MAC_MDIO_ADDRESS_CR_SHIFT 19
+#define XGMAC_MAC_MDIO_ADDRESS_CR_100_150 0
+#define XGMAC_MAC_MDIO_ADDRESS_CR_150_250 1
+#define XGMAC_MAC_MDIO_ADDRESS_CR_250_300 2
+#define XGMAC_MAC_MDIO_ADDRESS_CR_300_350 3
+#define XGMAC_MAC_MDIO_ADDRESS_CR_350_400 4
+#define XGMAC_MAC_MDIO_ADDRESS_CR_400_500 5
+#define XGMAC_MAC_MDIO_ADDRESS_SADDR BIT(18)
+#define XGMAC_MAC_MDIO_ADDRESS_SBUSY BIT(22)
+#define XGMAC_MAC_MDIO_REG_ADDR_C22P_MASK GENMASK(4, 0)
+#define XGMAC_MAC_MDIO_DATA_GD_MASK GENMASK(15, 0)
+
+/* MTL Registers */
+
+#define XGMAC_MTL_REGS_BASE 0x1000
+
+struct xgmac_mtl_regs {
+ u32 mtl_operation_mode; /* 0x1000 */
+ u32 unused_1004[(0x1030 - 0x1004) / 4]; /* 0x1004 */
+ u32 mtl_rxq_dma_map0; /* 0x1030 */
+ u32 mtl_rxq_dma_map1; /* 0x1034 */
+ u32 mtl_rxq_dma_map2; /* 0x1038 */
+ u32 mtl_rxq_dma_map3; /* 0x103c */
+ u32 mtl_tc_prty_map0; /* 0x1040 */
+ u32 mtl_tc_prty_map1; /* 0x1044 */
+ u32 unused_1048[(0x1100 - 0x1048) / 4]; /* 0x1048 */
+ u32 txq0_operation_mode; /* 0x1100 */
+ u32 unused_1104; /* 0x1104 */
+ u32 txq0_debug; /* 0x1108 */
+ u32 unused_100c[(0x1118 - 0x110c) / 4]; /* 0x110c */
+ u32 txq0_quantum_weight; /* 0x1118 */
+ u32 unused_111c[(0x1140 - 0x111c) / 4]; /* 0x111c */
+ u32 rxq0_operation_mode; /* 0x1140 */
+ u32 unused_1144; /* 0x1144 */
+ u32 rxq0_debug; /* 0x1148 */
+};
+
+#define XGMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16
+#define XGMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK GENMASK(8, 0)
+#define XGMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2
+#define XGMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2
+#define XGMAC_MTL_TXQ0_OPERATION_MODE_TSF BIT(1)
+#define XGMAC_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0)
+
+#define XGMAC_MTL_TXQ0_DEBUG_TXQSTS BIT(4)
+#define XGMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1
+#define XGMAC_MTL_TXQ0_DEBUG_TRCSTS_MASK GENMASK(2, 0)
+#define XGMAC_MTL_TXQ0_DEBUG_TRCSTS_READ_STATE 0x1
+
+#define XGMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 16
+#define XGMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK GENMASK(9, 0)
+#define XGMAC_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7)
+#define XGMAC_MTL_RXQ0_OPERATION_MODE_RSF BIT(5)
+
+#define XGMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16
+#define XGMAC_MTL_RXQ0_DEBUG_PRXQ_MASK GENMASK(14, 0)
+#define XGMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4
+#define XGMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK GENMASK(1, 0)
+
+/* DMA Registers */
+
+#define XGMAC_DMA_REGS_BASE 0x3000
+
+struct xgmac_dma_regs {
+ u32 mode; /* 0x3000 */
+ u32 sysbus_mode; /* 0x3004 */
+ u32 unused_3008[(0x3100 - 0x3008) / 4]; /* 0x3008 */
+ u32 ch0_control; /* 0x3100 */
+ u32 ch0_tx_control; /* 0x3104 */
+ u32 ch0_rx_control; /* 0x3108 */
+ u32 slot_func_control_status; /* 0x310c */
+ u32 ch0_txdesc_list_haddress; /* 0x3110 */
+ u32 ch0_txdesc_list_address; /* 0x3114 */
+ u32 ch0_rxdesc_list_haddress; /* 0x3118 */
+ u32 ch0_rxdesc_list_address; /* 0x311c */
+ u32 unused_3120; /* 0x3120 */
+ u32 ch0_txdesc_tail_pointer; /* 0x3124 */
+ u32 unused_3128; /* 0x3128 */
+ u32 ch0_rxdesc_tail_pointer; /* 0x312c */
+ u32 ch0_txdesc_ring_length; /* 0x3130 */
+ u32 ch0_rxdesc_ring_length; /* 0x3134 */
+ u32 unused_3138[(0x3160 - 0x3138) / 4]; /* 0x3138 */
+ u32 ch0_status; /* 0x3160 */
+};
+
+#define XGMAC_DMA_MODE_SWR BIT(0)
+#define XGMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT 24
+#define XGMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK GENMASK(4, 0)
+#define XGMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16
+#define XGMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK GENMASK(4, 0)
+#define XGMAC_DMA_SYSBUS_MODE_AAL BIT(12)
+#define XGMAC_DMA_SYSBUS_MODE_EAME BIT(11)
+#define XGMAC_DMA_SYSBUS_MODE_BLEN32 BIT(4)
+#define XGMAC_DMA_SYSBUS_MODE_BLEN16 BIT(3)
+#define XGMAC_DMA_SYSBUS_MODE_BLEN8 BIT(2)
+#define XGMAC_DMA_SYSBUS_MODE_BLEN4 BIT(1)
+#define XGMAC_DMA_SYSBUS_MODE_UNDEF BIT(0)
+
+#define XGMAC_DMA_CH0_CONTROL_DSL_SHIFT 18
+#define XGMAC_DMA_CH0_CONTROL_PBLX8 BIT(16)
+
+#define XGMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16
+#define XGMAC_DMA_CH0_TX_CONTROL_TXPBL_MASK GENMASK(5, 0)
+#define XGMAC_DMA_CH0_TX_CONTROL_OSP BIT(4)
+#define XGMAC_DMA_CH0_TX_CONTROL_ST BIT(0)
+
+#define XGMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16
+#define XGMAC_DMA_CH0_RX_CONTROL_RXPBL_MASK GENMASK(5, 0)
+#define XGMAC_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 4
+#define XGMAC_DMA_CH0_RX_CONTROL_RBSZ_MASK GENMASK(10, 0)
+#define XGMAC_DMA_CH0_RX_CONTROL_SR BIT(0)
+
+/* Descriptors */
+#define XGMAC_DESCRIPTORS_TX 8
+#define XGMAC_DESCRIPTORS_RX 8
+#define XGMAC_BUFFER_ALIGN ARCH_DMA_MINALIGN
+#define XGMAC_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN)
+#define XGMAC_RX_BUFFER_SIZE (XGMAC_DESCRIPTORS_RX * XGMAC_MAX_PACKET_SIZE)
+
+#define XGMAC_RDES3_PKT_LENGTH_MASK GENMASK(13, 0)
+
+struct xgmac_desc {
+ u32 des0;
+ u32 des1;
+ u32 des2;
+ u32 des3;
+};
+
+#define XGMAC_DESC3_OWN BIT(31)
+#define XGMAC_DESC3_FD BIT(29)
+#define XGMAC_DESC3_LD BIT(28)
+
+#define XGMAC_AXI_WIDTH_32 4
+#define XGMAC_AXI_WIDTH_64 8
+#define XGMAC_AXI_WIDTH_128 16
+
+struct xgmac_config {
+ bool reg_access_always_ok;
+ int swr_wait;
+ int config_mac;
+ int config_mac_mdio;
+ unsigned int axi_bus_width;
+ phy_interface_t (*interface)(const struct udevice *dev);
+ struct xgmac_ops *ops;
+};
+
+struct xgmac_ops {
+ void (*xgmac_inval_desc)(void *desc);
+ void (*xgmac_flush_desc)(void *desc);
+ void (*xgmac_inval_buffer)(void *buf, size_t size);
+ void (*xgmac_flush_buffer)(void *buf, size_t size);
+ int (*xgmac_probe_resources)(struct udevice *dev);
+ int (*xgmac_remove_resources)(struct udevice *dev);
+ int (*xgmac_stop_resets)(struct udevice *dev);
+ int (*xgmac_start_resets)(struct udevice *dev);
+ int (*xgmac_stop_clks)(struct udevice *dev);
+ int (*xgmac_start_clks)(struct udevice *dev);
+ int (*xgmac_calibrate_pads)(struct udevice *dev);
+ int (*xgmac_disable_calibration)(struct udevice *dev);
+ int (*xgmac_get_enetaddr)(struct udevice *dev);
+};
+
+struct xgmac_priv {
+ struct udevice *dev;
+ const struct xgmac_config *config;
+ fdt_addr_t regs;
+ struct xgmac_mac_regs *mac_regs;
+ struct xgmac_mtl_regs *mtl_regs;
+ struct xgmac_dma_regs *dma_regs;
+ struct reset_ctl reset_ctl;
+ struct reset_ctl_bulk reset_bulk;
+ struct clk clk_common;
+ struct mii_dev *mii;
+ struct phy_device *phy;
+ ofnode phy_of_node;
+ void *syscon_phy;
+ u32 syscon_phy_regshift;
+ u32 max_speed;
+ void *tx_descs;
+ void *rx_descs;
+ int tx_desc_idx, rx_desc_idx;
+ unsigned int desc_size;
+ unsigned int desc_per_cacheline;
+ void *tx_dma_buf;
+ void *rx_dma_buf;
+ void *rx_pkt;
+ bool started;
+ bool reg_access_ok;
+ bool clk_ck_enabled;
+};
+
+void xgmac_inval_desc_generic(void *desc);
+void xgmac_flush_desc_generic(void *desc);
+void xgmac_inval_buffer_generic(void *buf, size_t size);
+void xgmac_flush_buffer_generic(void *buf, size_t size);
+int xgmac_null_ops(struct udevice *dev);
+
+extern struct xgmac_config xgmac_socfpga_config;
diff --git a/drivers/net/dwc_eth_xgmac_socfpga.c b/drivers/net/dwc_eth_xgmac_socfpga.c
new file mode 100644
index 0000000..270c1b0
--- /dev/null
+++ b/drivers/net/dwc_eth_xgmac_socfpga.c
@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023, Intel Corporation
+ */
+#include <clk.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <errno.h>
+#include <eth_phy.h>
+#include <log.h>
+#include <malloc.h>
+#include <memalign.h>
+#include <miiphy.h>
+#include <net.h>
+#include <netdev.h>
+#include <phy.h>
+#include <reset.h>
+#include <wait_bit.h>
+#include <asm/arch/secure_reg_helper.h>
+#include <asm/arch/system_manager.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/cache.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+#include <dm/device_compat.h>
+#include "dwc_eth_xgmac.h"
+
+#define SOCFPGA_XGMAC_SYSCON_ARG_COUNT 2
+
+static int dwxgmac_socfpga_do_setphy(struct udevice *dev, u32 modereg)
+{
+ struct xgmac_priv *xgmac = dev_get_priv(dev);
+ int ret;
+
+ u32 modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK <<
+ xgmac->syscon_phy_regshift;
+
+ if (!(IS_ENABLED(CONFIG_SPL_BUILD)) && IS_ENABLED(CONFIG_SPL_ATF)) {
+ u32 index = ((u64)xgmac->syscon_phy - socfpga_get_sysmgr_addr() -
+ SYSMGR_SOC64_EMAC0) >> 2;
+
+ u32 id = SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0 + index;
+
+ ret = socfpga_secure_reg_update32(id,
+ modemask,
+ modereg <<
+ xgmac->syscon_phy_regshift);
+ if (ret) {
+ dev_err(dev, "Failed to set PHY register via SMC call\n");
+ return ret;
+ }
+
+ } else {
+ clrsetbits_le32(xgmac->phy, modemask, modereg);
+ }
+
+ return 0;
+}
+
+static int xgmac_probe_resources_socfpga(struct udevice *dev)
+{
+ struct xgmac_priv *xgmac = dev_get_priv(dev);
+ struct regmap *reg_map;
+ struct ofnode_phandle_args args;
+ void *range;
+ phy_interface_t interface;
+ int ret;
+ u32 modereg;
+
+ interface = xgmac->config->interface(dev);
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_MII:
+ case PHY_INTERFACE_MODE_GMII:
+ modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+ break;
+ default:
+ dev_err(dev, "Unsupported PHY mode\n");
+ return -EINVAL;
+ }
+
+ /* Get PHY syscon */
+ ret = dev_read_phandle_with_args(dev, "altr,sysmgr-syscon", NULL,
+ SOCFPGA_XGMAC_SYSCON_ARG_COUNT,
+ 0, &args);
+
+ if (ret) {
+ dev_err(dev, "Failed to get syscon: %d\n", ret);
+ return ret;
+ }
+
+ if (args.args_count != SOCFPGA_XGMAC_SYSCON_ARG_COUNT) {
+ dev_err(dev, "Invalid number of syscon args\n");
+ return -EINVAL;
+ }
+
+ reg_map = syscon_node_to_regmap(args.node);
+ if (IS_ERR(reg_map)) {
+ ret = PTR_ERR(reg_map);
+ dev_err(dev, "Failed to get reg_map: %d\n", ret);
+ return ret;
+ }
+
+ range = regmap_get_range(reg_map, 0);
+ if (!range) {
+ dev_err(dev, "Failed to get reg_map: %d\n", ret);
+ return -ENOMEM;
+ }
+
+ xgmac->syscon_phy = range + args.args[0];
+ xgmac->syscon_phy_regshift = args.args[1];
+
+ /* Get Reset Bulk */
+ ret = reset_get_bulk(dev, &xgmac->reset_bulk);
+ if (ret) {
+ dev_err(dev, "Failed to get reset: %d\n", ret);
+ return ret;
+ }
+
+ ret = reset_assert_bulk(&xgmac->reset_bulk);
+ if (ret) {
+ dev_err(dev, "XGMAC failed to assert reset: %d\n", ret);
+ return ret;
+ }
+
+ ret = dwxgmac_socfpga_do_setphy(dev, modereg);
+ if (ret)
+ return ret;
+
+ ret = reset_deassert_bulk(&xgmac->reset_bulk);
+ if (ret) {
+ dev_err(dev, "XGMAC failed to de-assert reset: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_get_by_name(dev, "stmmaceth", &xgmac->clk_common);
+ if (ret) {
+ pr_err("clk_get_by_name(stmmaceth) failed: %d", ret);
+ goto err_probe;
+ }
+ return 0;
+
+err_probe:
+ debug("%s: returns %d\n", __func__, ret);
+ return ret;
+}
+
+static int xgmac_get_enetaddr_socfpga(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct xgmac_priv *xgmac = dev_get_priv(dev);
+ u32 hi_addr, lo_addr;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ /* Read the MAC Address from the hardawre */
+ hi_addr = readl(&xgmac->mac_regs->address0_high);
+ lo_addr = readl(&xgmac->mac_regs->address0_low);
+
+ pdata->enetaddr[0] = lo_addr & 0xff;
+ pdata->enetaddr[1] = (lo_addr >> 8) & 0xff;
+ pdata->enetaddr[2] = (lo_addr >> 16) & 0xff;
+ pdata->enetaddr[3] = (lo_addr >> 24) & 0xff;
+ pdata->enetaddr[4] = hi_addr & 0xff;
+ pdata->enetaddr[5] = (hi_addr >> 8) & 0xff;
+
+ return !is_valid_ethaddr(pdata->enetaddr);
+}
+
+static int xgmac_start_resets_socfpga(struct udevice *dev)
+{
+ struct xgmac_priv *xgmac = dev_get_priv(dev);
+ int ret;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ ret = reset_assert_bulk(&xgmac->reset_bulk);
+ if (ret < 0) {
+ pr_err("xgmac reset assert failed: %d", ret);
+ return ret;
+ }
+
+ udelay(2);
+
+ ret = reset_deassert_bulk(&xgmac->reset_bulk);
+ if (ret < 0) {
+ pr_err("xgmac reset de-assert failed: %d", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static struct xgmac_ops xgmac_socfpga_ops = {
+ .xgmac_inval_desc = xgmac_inval_desc_generic,
+ .xgmac_flush_desc = xgmac_flush_desc_generic,
+ .xgmac_inval_buffer = xgmac_inval_buffer_generic,
+ .xgmac_flush_buffer = xgmac_flush_buffer_generic,
+ .xgmac_probe_resources = xgmac_probe_resources_socfpga,
+ .xgmac_remove_resources = xgmac_null_ops,
+ .xgmac_stop_resets = xgmac_null_ops,
+ .xgmac_start_resets = xgmac_start_resets_socfpga,
+ .xgmac_stop_clks = xgmac_null_ops,
+ .xgmac_start_clks = xgmac_null_ops,
+ .xgmac_calibrate_pads = xgmac_null_ops,
+ .xgmac_disable_calibration = xgmac_null_ops,
+ .xgmac_get_enetaddr = xgmac_get_enetaddr_socfpga,
+};
+
+struct xgmac_config __maybe_unused xgmac_socfpga_config = {
+ .reg_access_always_ok = false,
+ .swr_wait = 50,
+ .config_mac = XGMAC_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
+ .config_mac_mdio = XGMAC_MAC_MDIO_ADDRESS_CR_350_400,
+ .axi_bus_width = XGMAC_AXI_WIDTH_64,
+ .interface = dev_read_phy_mode,
+ .ops = &xgmac_socfpga_ops
+};
diff --git a/drivers/remoteproc/ipu_rproc.c b/drivers/remoteproc/ipu_rproc.c
index 996e658..2ca78b5 100644
--- a/drivers/remoteproc/ipu_rproc.c
+++ b/drivers/remoteproc/ipu_rproc.c
@@ -8,7 +8,6 @@
* Keerthy <j-keerthy@ti.com>
*/
-#include <common.h>
#include <hang.h>
#include <cpu_func.h>
#include <dm.h>
diff --git a/drivers/remoteproc/k3_system_controller.c b/drivers/remoteproc/k3_system_controller.c
index 071de40..71238a6 100644
--- a/drivers/remoteproc/k3_system_controller.c
+++ b/drivers/remoteproc/k3_system_controller.c
@@ -6,7 +6,6 @@
* Lokesh Vutla <lokeshvutla@ti.com>
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <remoteproc.h>
diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c
index 6ec55e2..9aec138 100644
--- a/drivers/remoteproc/pru_rproc.c
+++ b/drivers/remoteproc/pru_rproc.c
@@ -6,7 +6,6 @@
* Keerthy <j-keerthy@ti.com>
*/
-#include <common.h>
#include <dm.h>
#include <elf.h>
#include <dm/of_access.h>
@@ -399,10 +398,12 @@
{
u32 mask2 = 0x38000;
- if (device_is_compatible(dev, "ti,am654-rtu"))
+ if (device_is_compatible(dev, "ti,am654-rtu") ||
+ device_is_compatible(dev, "ti,am642-rtu"))
mask2 = 0x6000;
- if (device_is_compatible(dev, "ti,am654-tx-pru"))
+ if (device_is_compatible(dev, "ti,am654-tx-pru") ||
+ device_is_compatible(dev, "ti,am642-tx-pru"))
mask2 = 0xc000;
if ((priv->pru_iram & mask2) == mask2)
@@ -448,6 +449,9 @@
{ .compatible = "ti,am654-pru"},
{ .compatible = "ti,am654-rtu"},
{ .compatible = "ti,am654-tx-pru" },
+ { .compatible = "ti,am642-pru"},
+ { .compatible = "ti,am642-rtu"},
+ { .compatible = "ti,am642-tx-pru" },
{}
};
diff --git a/drivers/remoteproc/rproc-elf-loader.c b/drivers/remoteproc/rproc-elf-loader.c
index 5e070e5..ab1836b 100644
--- a/drivers/remoteproc/rproc-elf-loader.c
+++ b/drivers/remoteproc/rproc-elf-loader.c
@@ -2,7 +2,6 @@
/*
* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
*/
-#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <elf.h>
diff --git a/drivers/remoteproc/rproc-uclass.c b/drivers/remoteproc/rproc-uclass.c
index aa7f758..3ba2b40 100644
--- a/drivers/remoteproc/rproc-uclass.c
+++ b/drivers/remoteproc/rproc-uclass.c
@@ -7,7 +7,6 @@
#define LOG_CATEGORY UCLASS_REMOTEPROC
#define pr_fmt(fmt) "%s: " fmt, __func__
-#include <common.h>
#include <elf.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/remoteproc/sandbox_testproc.c b/drivers/remoteproc/sandbox_testproc.c
index f76f68e..ad575a7 100644
--- a/drivers/remoteproc/sandbox_testproc.c
+++ b/drivers/remoteproc/sandbox_testproc.c
@@ -4,7 +4,6 @@
* Texas Instruments Incorporated - https://www.ti.com/
*/
#define pr_fmt(fmt) "%s: " fmt, __func__
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/remoteproc/stm32_copro.c b/drivers/remoteproc/stm32_copro.c
index 3e322c4..f45da9a 100644
--- a/drivers/remoteproc/stm32_copro.c
+++ b/drivers/remoteproc/stm32_copro.c
@@ -4,7 +4,6 @@
*/
#define LOG_CATEGORY UCLASS_REMOTEPROC
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
diff --git a/drivers/remoteproc/ti_k3_arm64_rproc.c b/drivers/remoteproc/ti_k3_arm64_rproc.c
index 767493c..d3eb957 100644
--- a/drivers/remoteproc/ti_k3_arm64_rproc.c
+++ b/drivers/remoteproc/ti_k3_arm64_rproc.c
@@ -7,7 +7,6 @@
*
*/
-#include <common.h>
#include <dm.h>
#include <remoteproc.h>
#include <errno.h>
diff --git a/drivers/remoteproc/ti_k3_dsp_rproc.c b/drivers/remoteproc/ti_k3_dsp_rproc.c
index ed13729..076b6f2 100644
--- a/drivers/remoteproc/ti_k3_dsp_rproc.c
+++ b/drivers/remoteproc/ti_k3_dsp_rproc.c
@@ -7,7 +7,6 @@
* Suman Anna <s-anna@ti.com>
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <malloc.h>
diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c b/drivers/remoteproc/ti_k3_r5f_rproc.c
index 35835b2..74bf043 100644
--- a/drivers/remoteproc/ti_k3_r5f_rproc.c
+++ b/drivers/remoteproc/ti_k3_r5f_rproc.c
@@ -7,7 +7,6 @@
* Suman Anna <s-anna@ti.com>
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <malloc.h>
diff --git a/drivers/remoteproc/ti_power_proc.c b/drivers/remoteproc/ti_power_proc.c
index f55df4a..cf150af 100644
--- a/drivers/remoteproc/ti_power_proc.c
+++ b/drivers/remoteproc/ti_power_proc.c
@@ -4,7 +4,6 @@
* Texas Instruments Incorporated - https://www.ti.com/
*/
#define pr_fmt(fmt) "%s: " fmt, __func__
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
diff --git a/drivers/reset/reset-ast2500.c b/drivers/reset/reset-ast2500.c
index d9cecf3..0ed5396 100644
--- a/drivers/reset/reset-ast2500.c
+++ b/drivers/reset/reset-ast2500.c
@@ -4,7 +4,6 @@
* Copyright 2020 ASPEED Technology Inc.
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <misc.h>
diff --git a/drivers/reset/reset-ast2600.c b/drivers/reset/reset-ast2600.c
index 1732a45..ec7b9b6 100644
--- a/drivers/reset/reset-ast2600.c
+++ b/drivers/reset/reset-ast2600.c
@@ -3,7 +3,6 @@
* Copyright 2020 ASPEED Technology Inc.
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <misc.h>
diff --git a/drivers/reset/reset-bcm6345.c b/drivers/reset/reset-bcm6345.c
index 5383f59..6f14057 100644
--- a/drivers/reset/reset-bcm6345.c
+++ b/drivers/reset/reset-bcm6345.c
@@ -6,7 +6,6 @@
* Copyright (C) 2012 Jonas Gorski <jonas.gorski@gmail.com>
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/reset/reset-dra7.c b/drivers/reset/reset-dra7.c
index 05101a9..2f0ec4c 100644
--- a/drivers/reset/reset-dra7.c
+++ b/drivers/reset/reset-dra7.c
@@ -7,7 +7,6 @@
*/
#include <asm/io.h>
-#include <common.h>
#include <dm.h>
#include <reset-uclass.h>
#include <dm/device_compat.h>
diff --git a/drivers/reset/reset-hisilicon.c b/drivers/reset/reset-hisilicon.c
index 85e02b2..aca54cd 100644
--- a/drivers/reset/reset-hisilicon.c
+++ b/drivers/reset/reset-hisilicon.c
@@ -6,7 +6,6 @@
#include <log.h>
#include <malloc.h>
#include <asm/io.h>
-#include <common.h>
#include <dm.h>
#include <dt-bindings/reset/ti-syscon.h>
#include <reset-uclass.h>
diff --git a/drivers/reset/reset-hsdk.c b/drivers/reset/reset-hsdk.c
index 74b1173..747e73b 100644
--- a/drivers/reset/reset-hsdk.c
+++ b/drivers/reset/reset-hsdk.c
@@ -8,7 +8,6 @@
#include <log.h>
#include <asm/io.h>
-#include <common.h>
#include <dm.h>
#include <linux/bitops.h>
#include <linux/iopoll.h>
diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
index a3b3132..65a352b 100644
--- a/drivers/reset/reset-imx7.c
+++ b/drivers/reset/reset-imx7.c
@@ -6,7 +6,6 @@
#include <log.h>
#include <malloc.h>
#include <asm/io.h>
-#include <common.h>
#include <dm.h>
#include <dt-bindings/reset/imx7-reset.h>
#include <dt-bindings/reset/imx8mp-reset.h>
diff --git a/drivers/reset/reset-jh7110.c b/drivers/reset/reset-jh7110.c
index d6bdf6b..adf722d 100644
--- a/drivers/reset/reset-jh7110.c
+++ b/drivers/reset/reset-jh7110.c
@@ -5,7 +5,6 @@
*
*/
-#include <common.h>
#include <dm.h>
#include <dm/ofnode.h>
#include <dt-bindings/reset/starfive,jh7110-crg.h>
diff --git a/drivers/reset/reset-mediatek.c b/drivers/reset/reset-mediatek.c
index 97ed221..4b3afab 100644
--- a/drivers/reset/reset-mediatek.c
+++ b/drivers/reset/reset-mediatek.c
@@ -6,7 +6,6 @@
* Weijie Gao <weijie.gao@mediatek.com>
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <malloc.h>
diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c
index 9d0c8b3..6337cda 100644
--- a/drivers/reset/reset-meson.c
+++ b/drivers/reset/reset-meson.c
@@ -6,7 +6,6 @@
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <malloc.h>
diff --git a/drivers/reset/reset-mtmips.c b/drivers/reset/reset-mtmips.c
index 7bb8469..2db6766 100644
--- a/drivers/reset/reset-mtmips.c
+++ b/drivers/reset/reset-mtmips.c
@@ -5,7 +5,6 @@
* Author: Weijie Gao <weijie.gao@mediatek.com>
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/reset/reset-raspberrypi.c b/drivers/reset/reset-raspberrypi.c
index 804e32b..1792f08 100644
--- a/drivers/reset/reset-raspberrypi.c
+++ b/drivers/reset/reset-raspberrypi.c
@@ -4,7 +4,6 @@
*
* Copyright (C) 2020 Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
*/
-#include <common.h>
#include <dm.h>
#include <reset-uclass.h>
#include <asm/arch/msg.h>
diff --git a/drivers/reset/reset-rockchip.c b/drivers/reset/reset-rockchip.c
index 6cabaa1..876eb7d 100644
--- a/drivers/reset/reset-rockchip.c
+++ b/drivers/reset/reset-rockchip.c
@@ -3,7 +3,6 @@
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <malloc.h>
diff --git a/drivers/reset/reset-scmi.c b/drivers/reset/reset-scmi.c
index b76711f..6dc1fcb 100644
--- a/drivers/reset/reset-scmi.c
+++ b/drivers/reset/reset-scmi.c
@@ -5,7 +5,6 @@
#define LOG_CATEGORY UCLASS_RESET
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <reset-uclass.h>
diff --git a/drivers/reset/reset-sifive.c b/drivers/reset/reset-sifive.c
index 23513b2..65f8571 100644
--- a/drivers/reset/reset-sifive.c
+++ b/drivers/reset/reset-sifive.c
@@ -4,7 +4,6 @@
* Author: Sagar Kadam <sagar.kadam@sifive.com>
*/
-#include <common.h>
#include <dm.h>
#include <reset-uclass.h>
#include <asm/io.h>
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
index 6e3f03e..866437f 100644
--- a/drivers/reset/reset-socfpga.c
+++ b/drivers/reset/reset-socfpga.c
@@ -12,7 +12,6 @@
* Maxime Ripard <maxime.ripard@free-electrons.com>
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <malloc.h>
diff --git a/drivers/reset/reset-sunxi.c b/drivers/reset/reset-sunxi.c
index e484d1f..fd47e1f 100644
--- a/drivers/reset/reset-sunxi.c
+++ b/drivers/reset/reset-sunxi.c
@@ -4,7 +4,6 @@
* Author: Jagan Teki <jagan@amarulasolutions.com>
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/reset/reset-syscon.c b/drivers/reset/reset-syscon.c
index ff387ab..5be8c94 100644
--- a/drivers/reset/reset-syscon.c
+++ b/drivers/reset/reset-syscon.c
@@ -3,7 +3,6 @@
* Copyright (C) 2020 Sean Anderson
*/
-#include <common.h>
#include <dm.h>
#include <regmap.h>
#include <reset.h>
diff --git a/drivers/reset/reset-ti-sci.c b/drivers/reset/reset-ti-sci.c
index fd654a0..e69bcd4 100644
--- a/drivers/reset/reset-ti-sci.c
+++ b/drivers/reset/reset-ti-sci.c
@@ -8,7 +8,6 @@
* Loosely based on Linux kernel reset-ti-sci.c...
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c
index b972faf..fe4cebf 100644
--- a/drivers/reset/reset-uclass.c
+++ b/drivers/reset/reset-uclass.c
@@ -5,7 +5,6 @@
#define LOG_CATEGORY UCLASS_RESET
-#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include <log.h>
diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c
index 35e3cce..49b001f 100644
--- a/drivers/reset/reset-uniphier.c
+++ b/drivers/reset/reset-uniphier.c
@@ -5,7 +5,6 @@
* Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <malloc.h>
diff --git a/drivers/reset/reset-zynqmp.c b/drivers/reset/reset-zynqmp.c
index 87b4df5..b9c4f09 100644
--- a/drivers/reset/reset-zynqmp.c
+++ b/drivers/reset/reset-zynqmp.c
@@ -5,7 +5,6 @@
#define LOG_CATEGORY UCLASS_RESET
-#include <common.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <reset-uclass.h>
diff --git a/drivers/reset/rst-rk3588.c b/drivers/reset/rst-rk3588.c
index 2c524e4..eae2eb1 100644
--- a/drivers/reset/rst-rk3588.c
+++ b/drivers/reset/rst-rk3588.c
@@ -5,7 +5,6 @@
* Author: Sebastian Reichel <sebastian.reichel@collabora.com>
*/
-#include <common.h>
#include <dm.h>
#include <asm/arch-rockchip/clock.h>
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
diff --git a/drivers/reset/sandbox-reset-test.c b/drivers/reset/sandbox-reset-test.c
index 51b7981..dfacb76 100644
--- a/drivers/reset/sandbox-reset-test.c
+++ b/drivers/reset/sandbox-reset-test.c
@@ -3,7 +3,6 @@
* Copyright (c) 2016, NVIDIA CORPORATION.
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <malloc.h>
diff --git a/drivers/reset/sandbox-reset.c b/drivers/reset/sandbox-reset.c
index 97b1b92..adf9eed 100644
--- a/drivers/reset/sandbox-reset.c
+++ b/drivers/reset/sandbox-reset.c
@@ -3,7 +3,6 @@
* Copyright (c) 2016, NVIDIA CORPORATION.
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <malloc.h>
diff --git a/drivers/reset/sti-reset.c b/drivers/reset/sti-reset.c
index 5305270..412a0c5 100644
--- a/drivers/reset/sti-reset.c
+++ b/drivers/reset/sti-reset.c
@@ -4,7 +4,6 @@
* Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
*/
-#include <common.h>
#include <errno.h>
#include <log.h>
#include <malloc.h>
diff --git a/drivers/reset/stm32-reset.c b/drivers/reset/stm32-reset.c
index 0bbde29..9d4f361 100644
--- a/drivers/reset/stm32-reset.c
+++ b/drivers/reset/stm32-reset.c
@@ -6,7 +6,6 @@
#define LOG_CATEGORY UCLASS_RESET
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/reset/tegra-car-reset.c b/drivers/reset/tegra-car-reset.c
index 501e9ca..e3ecc8d 100644
--- a/drivers/reset/tegra-car-reset.c
+++ b/drivers/reset/tegra-car-reset.c
@@ -3,7 +3,6 @@
* Copyright (c) 2016, NVIDIA CORPORATION.
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <malloc.h>
diff --git a/drivers/reset/tegra186-reset.c b/drivers/reset/tegra186-reset.c
index d43da45..8962422 100644
--- a/drivers/reset/tegra186-reset.c
+++ b/drivers/reset/tegra186-reset.c
@@ -3,7 +3,6 @@
* Copyright (c) 2016, NVIDIA CORPORATION.
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <malloc.h>
diff --git a/drivers/rtc/abx80x.c b/drivers/rtc/abx80x.c
index 823aff0..1235b84 100644
--- a/drivers/rtc/abx80x.c
+++ b/drivers/rtc/abx80x.c
@@ -12,7 +12,6 @@
*
*/
-#include <common.h>
#include <dm.h>
#include <i2c.h>
#include <rtc.h>
diff --git a/drivers/rtc/davinci.c b/drivers/rtc/davinci.c
index c7ce41b..a20b73e 100644
--- a/drivers/rtc/davinci.c
+++ b/drivers/rtc/davinci.c
@@ -4,7 +4,6 @@
* Heiko Schocher <hs@denx.de>
* Copyright (C) 2021 Dario Binacchi <dariobin@libero.it>
*/
-#include <common.h>
#include <command.h>
#include <dm.h>
#include <clk.h>
diff --git a/drivers/rtc/ds1307.c b/drivers/rtc/ds1307.c
index 0e9d3d2..ba06ff9 100644
--- a/drivers/rtc/ds1307.c
+++ b/drivers/rtc/ds1307.c
@@ -13,7 +13,7 @@
* based on ds1337.c
*/
-#include <common.h>
+#include <config.h>
#include <command.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/rtc/ds1337.c b/drivers/rtc/ds1337.c
index 2c780ab..7eccf1c 100644
--- a/drivers/rtc/ds1337.c
+++ b/drivers/rtc/ds1337.c
@@ -11,7 +11,7 @@
* DS1337 Real Time Clock (RTC).
*/
-#include <common.h>
+#include <config.h>
#include <command.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/rtc/ds1374.c b/drivers/rtc/ds1374.c
index 89442f9..895dbba 100644
--- a/drivers/rtc/ds1374.c
+++ b/drivers/rtc/ds1374.c
@@ -13,7 +13,7 @@
* based on ds1337.c
*/
-#include <common.h>
+#include <config.h>
#include <command.h>
#include <rtc.h>
#include <i2c.h>
diff --git a/drivers/rtc/ds3231.c b/drivers/rtc/ds3231.c
index bd32ed2..d6267d6 100644
--- a/drivers/rtc/ds3231.c
+++ b/drivers/rtc/ds3231.c
@@ -14,7 +14,7 @@
* copied from ds1337.c
*/
-#include <common.h>
+#include <config.h>
#include <command.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/rtc/ds3232.c b/drivers/rtc/ds3232.c
index 16501cf..7314ba2 100644
--- a/drivers/rtc/ds3232.c
+++ b/drivers/rtc/ds3232.c
@@ -3,7 +3,6 @@
* (C) Copyright 2019, Vaisala Oyj
*/
-#include <common.h>
#include <command.h>
#include <dm.h>
#include <i2c.h>
diff --git a/drivers/rtc/emul_rtc.c b/drivers/rtc/emul_rtc.c
index 6f47d82..97a8d9b 100644
--- a/drivers/rtc/emul_rtc.c
+++ b/drivers/rtc/emul_rtc.c
@@ -5,11 +5,11 @@
* This driver emulates a real time clock based on timer ticks.
*/
-#include <common.h>
#include <div64.h>
#include <dm.h>
#include <env.h>
#include <rtc.h>
+#include <time.h>
#include <timestamp.h>
/**
diff --git a/drivers/rtc/ht1380.c b/drivers/rtc/ht1380.c
index 85fcee3..c202261 100644
--- a/drivers/rtc/ht1380.c
+++ b/drivers/rtc/ht1380.c
@@ -15,7 +15,6 @@
*
*/
-#include <common.h>
#include <dm.h>
#include <rtc.h>
#include <bcd.h>
diff --git a/drivers/rtc/i2c_rtc_emul.c b/drivers/rtc/i2c_rtc_emul.c
index c307d60..ea11c72 100644
--- a/drivers/rtc/i2c_rtc_emul.c
+++ b/drivers/rtc/i2c_rtc_emul.c
@@ -13,7 +13,6 @@
* time-keeping. It does not change the system time.
*/
-#include <common.h>
#include <dm.h>
#include <i2c.h>
#include <log.h>
diff --git a/drivers/rtc/isl1208.c b/drivers/rtc/isl1208.c
index 59a60b7..83db505 100644
--- a/drivers/rtc/isl1208.c
+++ b/drivers/rtc/isl1208.c
@@ -11,7 +11,6 @@
* ISL1208 Real Time Clock (RTC).
*/
-#include <common.h>
#include <command.h>
#include <dm.h>
#include <rtc.h>
diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c
index 891fe09..7bfea9e 100644
--- a/drivers/rtc/m41t62.c
+++ b/drivers/rtc/m41t62.c
@@ -16,7 +16,7 @@
/* #define DEBUG */
-#include <common.h>
+#include <config.h>
#include <command.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/rtc/mc13xxx-rtc.c b/drivers/rtc/mc13xxx-rtc.c
index 6c2aef8..9e396bc 100644
--- a/drivers/rtc/mc13xxx-rtc.c
+++ b/drivers/rtc/mc13xxx-rtc.c
@@ -3,7 +3,6 @@
* Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
*/
-#include <common.h>
#include <rtc.h>
#include <spi.h>
#include <power/pmic.h>
diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c
index 03ce081..c0d86c6 100644
--- a/drivers/rtc/mc146818.c
+++ b/drivers/rtc/mc146818.c
@@ -8,7 +8,6 @@
* Date & Time support for the MC146818 (PIXX4) RTC
*/
-#include <common.h>
#include <command.h>
#include <dm.h>
#include <rtc.h>
diff --git a/drivers/rtc/mcfrtc.c b/drivers/rtc/mcfrtc.c
index d2ac889..b5cc6b9 100644
--- a/drivers/rtc/mcfrtc.c
+++ b/drivers/rtc/mcfrtc.c
@@ -4,7 +4,6 @@
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
-#include <common.h>
#include <command.h>
#include <rtc.h>
diff --git a/drivers/rtc/mvrtc.c b/drivers/rtc/mvrtc.c
index 50240d5..f070c68 100644
--- a/drivers/rtc/mvrtc.c
+++ b/drivers/rtc/mvrtc.c
@@ -8,7 +8,6 @@
* Date & Time support for Marvell Integrated RTC
*/
-#include <common.h>
#include <command.h>
#include <dm.h>
#include <rtc.h>
diff --git a/drivers/rtc/mxsrtc.c b/drivers/rtc/mxsrtc.c
index be899a9..69d22a4 100644
--- a/drivers/rtc/mxsrtc.c
+++ b/drivers/rtc/mxsrtc.c
@@ -6,7 +6,6 @@
* on behalf of DENX Software Engineering GmbH
*/
-#include <common.h>
#include <rtc.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
diff --git a/drivers/rtc/pcf2127.c b/drivers/rtc/pcf2127.c
index 2f3fafb..27a340f 100644
--- a/drivers/rtc/pcf2127.c
+++ b/drivers/rtc/pcf2127.c
@@ -5,7 +5,6 @@
/* #define DEBUG */
-#include <common.h>
#include <command.h>
#include <dm.h>
#include <i2c.h>
diff --git a/drivers/rtc/pcf8563.c b/drivers/rtc/pcf8563.c
index 91a4124..03bef68 100644
--- a/drivers/rtc/pcf8563.c
+++ b/drivers/rtc/pcf8563.c
@@ -10,7 +10,7 @@
/* #define DEBUG */
-#include <common.h>
+#include <config.h>
#include <command.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/rtc/pl031.c b/drivers/rtc/pl031.c
index a1d3766..855ee91 100644
--- a/drivers/rtc/pl031.c
+++ b/drivers/rtc/pl031.c
@@ -6,7 +6,6 @@
* reference linux-2.6.20.6/drivers/rtc/rtc-pl031.c
*/
-#include <common.h>
#include <command.h>
#include <dm.h>
#include <errno.h>
diff --git a/drivers/rtc/pt7c4338.c b/drivers/rtc/pt7c4338.c
index e0a7bd3..79df078 100644
--- a/drivers/rtc/pt7c4338.c
+++ b/drivers/rtc/pt7c4338.c
@@ -18,7 +18,7 @@
* It has 56 bytes of nonvolatile RAM.
*/
-#include <common.h>
+#include <config.h>
#include <command.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/rtc/rtc-uclass.c b/drivers/rtc/rtc-uclass.c
index e5ae6ea..8f6c0c6 100644
--- a/drivers/rtc/rtc-uclass.c
+++ b/drivers/rtc/rtc-uclass.c
@@ -6,7 +6,6 @@
#define LOG_CATEGORY UCLASS_RTC
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/rtc/rv3029.c b/drivers/rtc/rv3029.c
index 9c53c7f..a82acec 100644
--- a/drivers/rtc/rv3029.c
+++ b/drivers/rtc/rv3029.c
@@ -7,7 +7,6 @@
* Michael Buesch <m@bues.ch>
*/
-#include <common.h>
#include <command.h>
#include <dm.h>
#include <i2c.h>
diff --git a/drivers/rtc/rv8803.c b/drivers/rtc/rv8803.c
index 06a4ae8..82b4372 100644
--- a/drivers/rtc/rv8803.c
+++ b/drivers/rtc/rv8803.c
@@ -10,7 +10,6 @@
*
*/
-#include <common.h>
#include <command.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/rtc/rx8010sj.c b/drivers/rtc/rx8010sj.c
index bf93b55..0d778f4 100644
--- a/drivers/rtc/rx8010sj.c
+++ b/drivers/rtc/rx8010sj.c
@@ -17,7 +17,7 @@
*/
#include <command.h>
-#include <common.h>
+#include <config.h>
#include <dm.h>
#include <i2c.h>
#include <rtc.h>
diff --git a/drivers/rtc/rx8025.c b/drivers/rtc/rx8025.c
index 1394c23..c789524 100644
--- a/drivers/rtc/rx8025.c
+++ b/drivers/rtc/rx8025.c
@@ -8,7 +8,6 @@
* Epson RX8025 RTC driver.
*/
-#include <common.h>
#include <command.h>
#include <dm.h>
#include <i2c.h>
diff --git a/drivers/rtc/s35392a.c b/drivers/rtc/s35392a.c
index 80f55c8..03fb9a0 100644
--- a/drivers/rtc/s35392a.c
+++ b/drivers/rtc/s35392a.c
@@ -18,7 +18,6 @@
*/
#include <command.h>
-#include <common.h>
#include <dm.h>
#include <i2c.h>
#include <linux/bitrev.h>
diff --git a/drivers/rtc/sandbox_rtc.c b/drivers/rtc/sandbox_rtc.c
index 657e5c7..4404501 100644
--- a/drivers/rtc/sandbox_rtc.c
+++ b/drivers/rtc/sandbox_rtc.c
@@ -4,7 +4,6 @@
* Written by Simon Glass <sjg@chromium.org>
*/
-#include <common.h>
#include <dm.h>
#include <i2c.h>
#include <rtc.h>
diff --git a/drivers/rtc/stm32_rtc.c b/drivers/rtc/stm32_rtc.c
index ec7584c..ee70c11 100644
--- a/drivers/rtc/stm32_rtc.c
+++ b/drivers/rtc/stm32_rtc.c
@@ -5,7 +5,6 @@
#define LOG_CATEGORY UCLASS_RTC
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <malloc.h>
diff --git a/drivers/rtc/zynqmp_rtc.c b/drivers/rtc/zynqmp_rtc.c
index ab9b93c..15122a0 100644
--- a/drivers/rtc/zynqmp_rtc.c
+++ b/drivers/rtc/zynqmp_rtc.c
@@ -5,7 +5,6 @@
#define LOG_CATEGORY UCLASS_RTC
-#include <common.h>
#include <dm.h>
#include <rtc.h>
#include <asm/io.h>
diff --git a/drivers/scsi/sandbox_scsi.c b/drivers/scsi/sandbox_scsi.c
index a7ac33c..544a024 100644
--- a/drivers/scsi/sandbox_scsi.c
+++ b/drivers/scsi/sandbox_scsi.c
@@ -9,7 +9,6 @@
#define LOG_CATEGORY UCLASS_SCSI
-#include <common.h>
#include <dm.h>
#include <os.h>
#include <malloc.h>
diff --git a/drivers/scsi/scsi-uclass.c b/drivers/scsi/scsi-uclass.c
index a7c1eaf..1ee8236 100644
--- a/drivers/scsi/scsi-uclass.c
+++ b/drivers/scsi/scsi-uclass.c
@@ -10,7 +10,6 @@
#define LOG_CATEGORY UCLASS_SCSI
-#include <common.h>
#include <dm.h>
#include <scsi.h>
diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c
index 79ee400..73cb835 100644
--- a/drivers/scsi/scsi.c
+++ b/drivers/scsi/scsi.c
@@ -6,7 +6,6 @@
#define LOG_CATEGORY UCLASS_SCSI
-#include <common.h>
#include <blk.h>
#include <bootdev.h>
#include <bootstage.h>
diff --git a/drivers/scsi/scsi_bootdev.c b/drivers/scsi/scsi_bootdev.c
index 218221f..28e4612 100644
--- a/drivers/scsi/scsi_bootdev.c
+++ b/drivers/scsi/scsi_bootdev.c
@@ -6,7 +6,6 @@
* Written by Simon Glass <sjg@chromium.org>
*/
-#include <common.h>
#include <bootdev.h>
#include <dm.h>
#include <init.h>
diff --git a/drivers/scsi/scsi_emul.c b/drivers/scsi/scsi_emul.c
index 6b8468f..d1bb926 100644
--- a/drivers/scsi/scsi_emul.c
+++ b/drivers/scsi/scsi_emul.c
@@ -11,7 +11,6 @@
#define LOG_CATEGORY UCLASS_SCSI
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <scsi.h>
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 403ab1d..dbe598b 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -65,3 +65,4 @@
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_USB_TTY) += usbtty.o
endif
+obj-$(CONFIG_UART4_SERIAL) += serial_adi_uart4.o
diff --git a/drivers/serial/altera_jtag_uart.c b/drivers/serial/altera_jtag_uart.c
index 9e39da7..3f706e1 100644
--- a/drivers/serial/altera_jtag_uart.c
+++ b/drivers/serial/altera_jtag_uart.c
@@ -4,7 +4,6 @@
* Scott McNutt <smcnutt@psyent.com>
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <serial.h>
diff --git a/drivers/serial/altera_uart.c b/drivers/serial/altera_uart.c
index 3592048..3c13ef2 100644
--- a/drivers/serial/altera_uart.c
+++ b/drivers/serial/altera_uart.c
@@ -4,7 +4,6 @@
* Scott McNutt <smcnutt@psyent.com>
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <serial.h>
diff --git a/drivers/serial/arm_dcc.c b/drivers/serial/arm_dcc.c
index a402a12..66af136 100644
--- a/drivers/serial/arm_dcc.c
+++ b/drivers/serial/arm_dcc.c
@@ -15,7 +15,6 @@
* this file might be covered by the GNU General Public License.
*/
-#include <common.h>
#include <dm.h>
#include <serial.h>
diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c
index 9827c00..7e45a80 100644
--- a/drivers/serial/atmel_usart.c
+++ b/drivers/serial/atmel_usart.c
@@ -5,7 +5,6 @@
* Modified to support C structur SoC access by
* Andreas Bießmann <biessmann@corscience.de>
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <errno.h>
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 6deb1d8..4963385 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -5,7 +5,7 @@
*/
#include <clock_legacy.h>
-#include <common.h>
+#include <config.h>
#include <clk.h>
#include <dm.h>
#include <errno.h>
diff --git a/drivers/serial/sandbox.c b/drivers/serial/sandbox.c
index f6ac3d2..ec0068e 100644
--- a/drivers/serial/sandbox.c
+++ b/drivers/serial/sandbox.c
@@ -9,7 +9,6 @@
* U-Boot.
*/
-#include <common.h>
#include <console.h>
#include <dm.h>
#include <os.h>
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index e4fa393..84f02f7 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -5,7 +5,7 @@
#define LOG_CATEGORY UCLASS_SERIAL
-#include <common.h>
+#include <config.h>
#include <dm.h>
#include <env_internal.h>
#include <errno.h>
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index 787edd5..dc4bb06 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -4,7 +4,7 @@
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
-#include <common.h>
+#include <config.h>
#include <env_internal.h>
#include <hang.h>
#include <serial.h>
diff --git a/drivers/serial/serial_adi_uart4.c b/drivers/serial/serial_adi_uart4.c
new file mode 100644
index 0000000..45f8315
--- /dev/null
+++ b/drivers/serial/serial_adi_uart4.c
@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Converted to driver model by Nathan Barrett-Morrison
+ *
+ * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ * Contact: Greg Malysa <greg.malysa@timesys.com>
+ *
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <serial.h>
+#include <asm/io.h>
+#include <dm/device_compat.h>
+#include <linux/bitops.h>
+
+/*
+ * UART4 Masks
+ */
+
+/* UART_CONTROL */
+#define UEN BIT(0)
+#define LOOP_ENA BIT(1)
+#define UMOD (3 << 4)
+#define UMOD_UART (0 << 4)
+#define UMOD_MDB BIT(4)
+#define UMOD_IRDA BIT(4)
+#define WLS (3 << 8)
+#define WLS_5 (0 << 8)
+#define WLS_6 BIT(8)
+#define WLS_7 (2 << 8)
+#define WLS_8 (3 << 8)
+#define STB BIT(12)
+#define STBH BIT(13)
+#define PEN BIT(14)
+#define EPS BIT(15)
+#define STP BIT(16)
+#define FPE BIT(17)
+#define FFE BIT(18)
+#define SB BIT(19)
+#define FCPOL BIT(22)
+#define RPOLC BIT(23)
+#define TPOLC BIT(24)
+#define MRTS BIT(25)
+#define XOFF BIT(26)
+#define ARTS BIT(27)
+#define ACTS BIT(28)
+#define RFIT BIT(29)
+#define RFRT BIT(30)
+
+/* UART_STATUS */
+#define DR BIT(0)
+#define OE BIT(1)
+#define PE BIT(2)
+#define FE BIT(3)
+#define BI BIT(4)
+#define THRE BIT(5)
+#define TEMT BIT(7)
+#define TFI BIT(8)
+#define ASTKY BIT(9)
+#define ADDR BIT(10)
+#define RO BIT(11)
+#define SCTS BIT(12)
+#define CTS BIT(16)
+#define RFCS BIT(17)
+
+/* UART_EMASK */
+#define ERBFI BIT(0)
+#define ETBEI BIT(1)
+#define ELSI BIT(2)
+#define EDSSI BIT(3)
+#define EDTPTI BIT(4)
+#define ETFI BIT(5)
+#define ERFCI BIT(6)
+#define EAWI BIT(7)
+#define ERXS BIT(8)
+#define ETXS BIT(9)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct uart4_reg {
+ u32 revid;
+ u32 control;
+ u32 status;
+ u32 scr;
+ u32 clock;
+ u32 emask;
+ u32 emaskst;
+ u32 emaskcl;
+ u32 rbr;
+ u32 thr;
+ u32 taip;
+ u32 tsr;
+ u32 rsr;
+ u32 txdiv_cnt;
+ u32 rxdiv_cnt;
+};
+
+struct adi_uart4_platdata {
+ // Hardware registers
+ struct uart4_reg *regs;
+
+ // Enable divide-by-one baud rate setting
+ bool edbo;
+};
+
+static int adi_uart4_set_brg(struct udevice *dev, int baudrate)
+{
+ struct adi_uart4_platdata *plat = dev_get_plat(dev);
+ struct uart4_reg *regs = plat->regs;
+ u32 divisor, uart_base_clk_rate;
+ struct clk uart_base_clk;
+
+ if (clk_get_by_index(dev, 0, &uart_base_clk)) {
+ dev_err(dev, "Could not get UART base clock\n");
+ return -1;
+ }
+
+ uart_base_clk_rate = clk_get_rate(&uart_base_clk);
+
+ if (plat->edbo) {
+ u16 divisor16 = (uart_base_clk_rate + (baudrate / 2)) / baudrate;
+
+ divisor = divisor16 | BIT(31);
+ } else {
+ // Divisor is only 16 bits
+ divisor = 0x0000ffff & ((uart_base_clk_rate + (baudrate * 8)) / (baudrate * 16));
+ }
+
+ writel(divisor, ®s->clock);
+ return 0;
+}
+
+static int adi_uart4_pending(struct udevice *dev, bool input)
+{
+ struct adi_uart4_platdata *plat = dev_get_plat(dev);
+ struct uart4_reg *regs = plat->regs;
+
+ if (input)
+ return (readl(®s->status) & DR) ? 1 : 0;
+ else
+ return (readl(®s->status) & THRE) ? 0 : 1;
+}
+
+static int adi_uart4_getc(struct udevice *dev)
+{
+ struct adi_uart4_platdata *plat = dev_get_plat(dev);
+ struct uart4_reg *regs = plat->regs;
+ int uart_rbr_val;
+
+ if (!adi_uart4_pending(dev, true))
+ return -EAGAIN;
+
+ uart_rbr_val = readl(®s->rbr);
+ writel(-1, ®s->status);
+
+ return uart_rbr_val;
+}
+
+static int adi_uart4_putc(struct udevice *dev, const char ch)
+{
+ struct adi_uart4_platdata *plat = dev_get_plat(dev);
+ struct uart4_reg *regs = plat->regs;
+
+ if (adi_uart4_pending(dev, false))
+ return -EAGAIN;
+
+ writel(ch, ®s->thr);
+ return 0;
+}
+
+static const struct dm_serial_ops adi_uart4_serial_ops = {
+ .setbrg = adi_uart4_set_brg,
+ .getc = adi_uart4_getc,
+ .putc = adi_uart4_putc,
+ .pending = adi_uart4_pending,
+};
+
+static int adi_uart4_of_to_plat(struct udevice *dev)
+{
+ struct adi_uart4_platdata *plat = dev_get_plat(dev);
+ fdt_addr_t addr;
+
+ addr = dev_read_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ plat->regs = (struct uart4_reg *)addr;
+ plat->edbo = dev_read_bool(dev, "adi,enable-edbo");
+
+ return 0;
+}
+
+static int adi_uart4_probe(struct udevice *dev)
+{
+ struct adi_uart4_platdata *plat = dev_get_plat(dev);
+ struct uart4_reg *regs = plat->regs;
+
+ /* always enable UART to 8-bit mode */
+ writel(UEN | UMOD_UART | WLS_8, ®s->control);
+
+ writel(-1, ®s->status);
+
+ return 0;
+}
+
+static const struct udevice_id adi_uart4_serial_ids[] = {
+ { .compatible = "adi,uart4" },
+ { }
+};
+
+U_BOOT_DRIVER(serial_adi_uart4) = {
+ .name = "serial_adi_uart4",
+ .id = UCLASS_SERIAL,
+ .of_match = adi_uart4_serial_ids,
+ .of_to_plat = adi_uart4_of_to_plat,
+ .plat_auto = sizeof(struct adi_uart4_platdata),
+ .probe = adi_uart4_probe,
+ .ops = &adi_uart4_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/serial/serial_ar933x.c b/drivers/serial/serial_ar933x.c
index 4f91634..4d92752 100644
--- a/drivers/serial/serial_ar933x.c
+++ b/drivers/serial/serial_ar933x.c
@@ -3,7 +3,6 @@
* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
*/
-#include <common.h>
#include <clock_legacy.h>
#include <dm.h>
#include <div64.h>
diff --git a/drivers/serial/serial_arc.c b/drivers/serial/serial_arc.c
index c2fc8a9..c0930cf 100644
--- a/drivers/serial/serial_arc.c
+++ b/drivers/serial/serial_arc.c
@@ -7,7 +7,6 @@
*
*/
-#include <common.h>
#include <dm.h>
#include <serial.h>
#include <asm/global_data.h>
diff --git a/drivers/serial/serial_bcm283x_mu.c b/drivers/serial/serial_bcm283x_mu.c
index 7585f79..7fa2624 100644
--- a/drivers/serial/serial_bcm283x_mu.c
+++ b/drivers/serial/serial_bcm283x_mu.c
@@ -14,7 +14,6 @@
/* Simple U-Boot driver for the BCM283x mini UART */
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <watchdog.h>
diff --git a/drivers/serial/serial_bcm283x_pl011.c b/drivers/serial/serial_bcm283x_pl011.c
index 09a9868..2abc1c4 100644
--- a/drivers/serial/serial_bcm283x_pl011.c
+++ b/drivers/serial/serial_bcm283x_pl011.c
@@ -3,7 +3,6 @@
* Copyright (c) 2018 Alexander Graf <agraf@suse.de>
*/
-#include <common.h>
#include <dm.h>
#include <asm/gpio.h>
#include <dm/pinctrl.h>
diff --git a/drivers/serial/serial_coreboot.c b/drivers/serial/serial_coreboot.c
index 23066e4..b1f69f6 100644
--- a/drivers/serial/serial_coreboot.c
+++ b/drivers/serial/serial_coreboot.c
@@ -7,7 +7,6 @@
#define LOG_CATGEGORY UCLASS_SERIAL
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <ns16550.h>
diff --git a/drivers/serial/serial_cortina.c b/drivers/serial/serial_cortina.c
index 6dc81a7..3ae8fb4 100644
--- a/drivers/serial/serial_cortina.c
+++ b/drivers/serial/serial_cortina.c
@@ -5,7 +5,6 @@
*
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <watchdog.h>
diff --git a/drivers/serial/serial_efi.c b/drivers/serial/serial_efi.c
index 0067576..5733eaaf 100644
--- a/drivers/serial/serial_efi.c
+++ b/drivers/serial/serial_efi.c
@@ -4,7 +4,6 @@
* Written by Simon Glass <sjg@chromium.org>
*/
-#include <common.h>
#include <debug_uart.h>
#include <dm.h>
#include <efi.h>
diff --git a/drivers/serial/serial_htif.c b/drivers/serial/serial_htif.c
index 5d2bf0a..2a93bbb 100644
--- a/drivers/serial/serial_htif.c
+++ b/drivers/serial/serial_htif.c
@@ -3,7 +3,6 @@
* Copyright (C) 2022 Ventana Micro Systems Inc.
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
diff --git a/drivers/serial/serial_intel_mid.c b/drivers/serial/serial_intel_mid.c
index bbf1905..4b528e4 100644
--- a/drivers/serial/serial_intel_mid.c
+++ b/drivers/serial/serial_intel_mid.c
@@ -3,7 +3,6 @@
* Copyright (c) 2017 Intel Corporation
*/
-#include <common.h>
#include <dm.h>
#include <ns16550.h>
#include <serial.h>
diff --git a/drivers/serial/serial_linflexuart.c b/drivers/serial/serial_linflexuart.c
index b449e55..ff66e69 100644
--- a/drivers/serial/serial_linflexuart.c
+++ b/drivers/serial/serial_linflexuart.c
@@ -3,7 +3,6 @@
* (C) Copyright 2013-2016 Freescale Semiconductor, Inc.
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <watchdog.h>
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index 3f2be72..a06e6dc 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -4,7 +4,6 @@
* Copyright 2013 Freescale Semiconductor, Inc.
*/
-#include <common.h>
#include <clock_legacy.h>
#include <clk.h>
#include <dm.h>
diff --git a/drivers/serial/serial_mcf.c b/drivers/serial/serial_mcf.c
index bb2afd0..7614357 100644
--- a/drivers/serial/serial_mcf.c
+++ b/drivers/serial/serial_mcf.c
@@ -15,7 +15,6 @@
* as serial console interface.
*/
-#include <common.h>
#include <dm.h>
#include <asm/global_data.h>
#include <dm/platform_data/serial_coldfire.h>
diff --git a/drivers/serial/serial_meson.c b/drivers/serial/serial_meson.c
index be5f380..bb79b97 100644
--- a/drivers/serial/serial_meson.c
+++ b/drivers/serial/serial_meson.c
@@ -3,7 +3,6 @@
* (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
diff --git a/drivers/serial/serial_mpc8xx.c b/drivers/serial/serial_mpc8xx.c
index d82760c..9ce3fc3 100644
--- a/drivers/serial/serial_mpc8xx.c
+++ b/drivers/serial/serial_mpc8xx.c
@@ -4,7 +4,6 @@
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
-#include <common.h>
#include <command.h>
#include <dm.h>
#include <serial.h>
diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
index a472e0b..757e5ea 100644
--- a/drivers/serial/serial_msm.c
+++ b/drivers/serial/serial_msm.c
@@ -8,7 +8,6 @@
* Based on Linux driver.
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <errno.h>
diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c
index 5260474..cb6c09f 100644
--- a/drivers/serial/serial_msm_geni.c
+++ b/drivers/serial/serial_msm_geni.c
@@ -9,7 +9,6 @@
#include <asm/io.h>
#include <clk.h>
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <linux/delay.h>
diff --git a/drivers/serial/serial_mtk.c b/drivers/serial/serial_mtk.c
index f146f2b..3f569c6 100644
--- a/drivers/serial/serial_mtk.c
+++ b/drivers/serial/serial_mtk.c
@@ -7,7 +7,7 @@
*/
#include <clk.h>
-#include <common.h>
+#include <config.h>
#include <div64.h>
#include <dm.h>
#include <dm/device_compat.h>
diff --git a/drivers/serial/serial_mvebu_a3700.c b/drivers/serial/serial_mvebu_a3700.c
index b2017c6..1a0b85e 100644
--- a/drivers/serial/serial_mvebu_a3700.c
+++ b/drivers/serial/serial_mvebu_a3700.c
@@ -4,7 +4,6 @@
* Copyright (C) 2021 Pali Rohár <pali@kernel.org>
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <serial.h>
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index cc85a50..c5fd740 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -3,7 +3,6 @@
* (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <watchdog.h>
diff --git a/drivers/serial/serial_mxs.c b/drivers/serial/serial_mxs.c
index 3659948..071bd09 100644
--- a/drivers/serial/serial_mxs.c
+++ b/drivers/serial/serial_mxs.c
@@ -2,7 +2,6 @@
/*
* Copyright (C) 2023 Marek Vasut <marex@denx.de>
*/
-#include <common.h>
#include <dm.h>
#include <malloc.h>
#include <serial.h>
diff --git a/drivers/serial/serial_npcm.c b/drivers/serial/serial_npcm.c
index 6bf3a94..661daf1 100644
--- a/drivers/serial/serial_npcm.c
+++ b/drivers/serial/serial_npcm.c
@@ -3,7 +3,6 @@
* Copyright (c) 2021 Nuvoton Technology Corp.
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <serial.h>
diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index 4014f68..577864b 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c
@@ -4,7 +4,7 @@
* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
*/
-#include <common.h>
+#include <config.h>
#include <clock_legacy.h>
#include <ns16550.h>
#include <serial.h>
diff --git a/drivers/serial/serial_nulldev.c b/drivers/serial/serial_nulldev.c
index f3ca7f5..78a9e0b 100644
--- a/drivers/serial/serial_nulldev.c
+++ b/drivers/serial/serial_nulldev.c
@@ -3,7 +3,6 @@
* Copyright (c) 2015 National Instruments
*/
-#include <common.h>
#include <dm.h>
#include <serial.h>
diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c
index 49ced8f..9467265 100644
--- a/drivers/serial/serial_omap.c
+++ b/drivers/serial/serial_omap.c
@@ -6,7 +6,7 @@
* Lokesh Vutla <lokeshvutla@ti.com>
*/
-#include <common.h>
+#include <config.h>
#include <dm.h>
#include <dt-structs.h>
#include <log.h>
diff --git a/drivers/serial/serial_owl.c b/drivers/serial/serial_owl.c
index 3b79578..8ce8aa3 100644
--- a/drivers/serial/serial_owl.c
+++ b/drivers/serial/serial_owl.c
@@ -6,7 +6,6 @@
* Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <errno.h>
diff --git a/drivers/serial/serial_pic32.c b/drivers/serial/serial_pic32.c
index 0a03a9a..a49c413 100644
--- a/drivers/serial/serial_pic32.c
+++ b/drivers/serial/serial_pic32.c
@@ -3,7 +3,6 @@
* (c) 2015 Paul Thacker <paul.thacker@microchip.com>
*
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <malloc.h>
diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index f04c21e..80c3596 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -10,7 +10,6 @@
/* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
-#include <common.h>
#include <asm/global_data.h>
/* For get_bus_freq() */
#include <clock_legacy.h>
diff --git a/drivers/serial/serial_rockchip.c b/drivers/serial/serial_rockchip.c
index f4e9422..8a15173 100644
--- a/drivers/serial/serial_rockchip.c
+++ b/drivers/serial/serial_rockchip.c
@@ -3,7 +3,6 @@
* Copyright (c) 2015 Google, Inc
*/
-#include <common.h>
#include <debug_uart.h>
#include <dm.h>
#include <dt-structs.h>
diff --git a/drivers/serial/serial_s5p4418_pl011.c b/drivers/serial/serial_s5p4418_pl011.c
index e4492e6..1fb954e 100644
--- a/drivers/serial/serial_s5p4418_pl011.c
+++ b/drivers/serial/serial_s5p4418_pl011.c
@@ -3,7 +3,6 @@
* Copyright (C) 2022 Stefan Bosch <stefan_b@posteo.net>
*/
-#include <common.h>
#include <dm.h>
#include <asm/arch/clk.h>
#include <asm/arch/reset.h>
diff --git a/drivers/serial/serial_semihosting.c b/drivers/serial/serial_semihosting.c
index cfa1ec3..56a5ec7 100644
--- a/drivers/serial/serial_semihosting.c
+++ b/drivers/serial/serial_semihosting.c
@@ -3,7 +3,6 @@
* Copyright (C) 2022 Sean Anderson <sean.anderson@seco.com>
*/
-#include <common.h>
#include <dm.h>
#include <malloc.h>
#include <serial.h>
diff --git a/drivers/serial/serial_sifive.c b/drivers/serial/serial_sifive.c
index c449f3f..e47828e 100644
--- a/drivers/serial/serial_sifive.c
+++ b/drivers/serial/serial_sifive.c
@@ -3,7 +3,6 @@
* Copyright (C) 2018 Anup Patel <anup@brainfault.org>
*/
-#include <common.h>
#include <clk.h>
#include <debug_uart.h>
#include <dm.h>
diff --git a/drivers/serial/serial_sti_asc.c b/drivers/serial/serial_sti_asc.c
index 40381b5..ef68e58 100644
--- a/drivers/serial/serial_sti_asc.c
+++ b/drivers/serial/serial_sti_asc.c
@@ -6,7 +6,6 @@
* Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <serial.h>
diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c
index fb03954..1ee5814 100644
--- a/drivers/serial/serial_stm32.c
+++ b/drivers/serial/serial_stm32.c
@@ -6,7 +6,6 @@
#define LOG_CATEGORY UCLASS_SERIAL
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c
index 27e4b92..a566ba7 100644
--- a/drivers/serial/serial_uniphier.c
+++ b/drivers/serial/serial_uniphier.c
@@ -5,7 +5,6 @@
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*/
-#include <common.h>
#include <dm.h>
#include <linux/bitfield.h>
#include <linux/bitops.h>
diff --git a/drivers/serial/serial_xen.c b/drivers/serial/serial_xen.c
index ab318b0..e05805f 100644
--- a/drivers/serial/serial_xen.c
+++ b/drivers/serial/serial_xen.c
@@ -3,7 +3,6 @@
* (C) 2018 NXP
* (C) 2020 EPAM Systems Inc.
*/
-#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <serial.h>
diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c
index 35df413..eb23410 100644
--- a/drivers/serial/serial_xuartlite.c
+++ b/drivers/serial/serial_xuartlite.c
@@ -8,7 +8,6 @@
*/
#include <config.h>
-#include <common.h>
#include <dm.h>
#include <asm/io.h>
#include <linux/bitops.h>
diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
index 1847d1f..55f13c0 100644
--- a/drivers/serial/serial_zynq.c
+++ b/drivers/serial/serial_zynq.c
@@ -5,7 +5,6 @@
*/
#include <clk.h>
-#include <common.h>
#include <debug_uart.h>
#include <dm.h>
#include <errno.h>
diff --git a/drivers/serial/usbtty.c b/drivers/serial/usbtty.c
index ecb6ba8..ae3ac80 100644
--- a/drivers/serial/usbtty.c
+++ b/drivers/serial/usbtty.c
@@ -7,7 +7,6 @@
* Bryan O'Donoghue, bodonoghue@codehermit.ie
*/
-#include <common.h>
#include <config.h>
#include <circbuf.h>
#include <env.h>
diff --git a/drivers/sm/meson-sm.c b/drivers/sm/meson-sm.c
index 15b3b0e..87eba14 100644
--- a/drivers/sm/meson-sm.c
+++ b/drivers/sm/meson-sm.c
@@ -5,7 +5,6 @@
* Author: Alexey Romanov <avromanov@salutedevices.com>
*/
-#include <common.h>
#include <dm.h>
#include <regmap.h>
#include <sm.h>
diff --git a/drivers/sm/sandbox-sm.c b/drivers/sm/sandbox-sm.c
index 109ddb2..a95e685 100644
--- a/drivers/sm/sandbox-sm.c
+++ b/drivers/sm/sandbox-sm.c
@@ -5,7 +5,6 @@
* Author: Alexey Romanov <avromanov@salutedevices.com>
*/
-#include <common.h>
#include <sm.h>
#include <sm-uclass.h>
#include <sandbox-sm.h>
diff --git a/drivers/sm/sm-uclass.c b/drivers/sm/sm-uclass.c
index 6a8b702..abca005 100644
--- a/drivers/sm/sm-uclass.c
+++ b/drivers/sm/sm-uclass.c
@@ -5,7 +5,6 @@
* Author: Alexey Romanov <avromanov@salutedevices.com>
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <sm-uclass.h>
diff --git a/drivers/smem/msm_smem.c b/drivers/smem/msm_smem.c
index 17ee6c8..ccd145f 100644
--- a/drivers/smem/msm_smem.c
+++ b/drivers/smem/msm_smem.c
@@ -5,7 +5,6 @@
* Copyright (c) 2018, Ramon Fried <ramon.fried@gmail.com>
*/
-#include <common.h>
#include <errno.h>
#include <dm.h>
#include <asm/global_data.h>
diff --git a/drivers/smem/sandbox_smem.c b/drivers/smem/sandbox_smem.c
index 7397e44..fec98e5 100644
--- a/drivers/smem/sandbox_smem.c
+++ b/drivers/smem/sandbox_smem.c
@@ -3,7 +3,6 @@
* Copyright (c) 2018 Ramon Fried <ramon.fried@gmail.com>
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <smem.h>
diff --git a/drivers/smem/smem-uclass.c b/drivers/smem/smem-uclass.c
index 8469076..4dea5cc 100644
--- a/drivers/smem/smem-uclass.c
+++ b/drivers/smem/smem-uclass.c
@@ -5,7 +5,6 @@
#define LOG_CATEGORY UCLASS_SMEM
-#include <common.h>
#include <dm.h>
#include <smem.h>
diff --git a/drivers/soc/soc-uclass.c b/drivers/soc/soc-uclass.c
index 8b3044f..744cdda 100644
--- a/drivers/soc/soc-uclass.c
+++ b/drivers/soc/soc-uclass.c
@@ -6,7 +6,6 @@
#define LOG_CATEGORY UCLASS_SOC
-#include <common.h>
#include <soc.h>
#include <dm.h>
#include <errno.h>
diff --git a/drivers/soc/soc_sandbox.c b/drivers/soc/soc_sandbox.c
index 15fdd99..8d621e8 100644
--- a/drivers/soc/soc_sandbox.c
+++ b/drivers/soc/soc_sandbox.c
@@ -6,7 +6,6 @@
* Dave Gerlach <d-gerlach@ti.com>
*/
-#include <common.h>
#include <dm.h>
#include <soc.h>
diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c
index 3a4e58b..b585e47 100644
--- a/drivers/soc/soc_ti_k3.c
+++ b/drivers/soc/soc_ti_k3.c
@@ -4,7 +4,6 @@
* Dave Gerlach <d-gerlach@ti.com>
*/
-#include <common.h>
#include <dm.h>
#include <soc.h>
diff --git a/drivers/soc/soc_xilinx_versal.c b/drivers/soc/soc_xilinx_versal.c
index 3d8c25c..7427f84 100644
--- a/drivers/soc/soc_xilinx_versal.c
+++ b/drivers/soc/soc_xilinx_versal.c
@@ -5,7 +5,6 @@
* Copyright (C) 2021 Xilinx, Inc.
*/
-#include <common.h>
#include <dm.h>
#include <soc.h>
#include <zynqmp_firmware.h>
diff --git a/drivers/soc/soc_xilinx_versal_net.c b/drivers/soc/soc_xilinx_versal_net.c
index 146d068..d64fc36 100644
--- a/drivers/soc/soc_xilinx_versal_net.c
+++ b/drivers/soc/soc_xilinx_versal_net.c
@@ -5,7 +5,6 @@
* Copyright (C) 2022, Advanced Micro Devices, Inc.
*/
-#include <common.h>
#include <dm.h>
#include <soc.h>
#include <zynqmp_firmware.h>
diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c
index d8b4f17..a2d5b82 100644
--- a/drivers/soc/soc_xilinx_zynqmp.c
+++ b/drivers/soc/soc_xilinx_zynqmp.c
@@ -9,7 +9,6 @@
* Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
*/
-#include <common.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <asm/cache.h>
diff --git a/drivers/soc/ti/k3-navss-ringacc.c b/drivers/soc/ti/k3-navss-ringacc.c
index ed39ff2..d3f3d47 100644
--- a/drivers/soc/ti/k3-navss-ringacc.c
+++ b/drivers/soc/ti/k3-navss-ringacc.c
@@ -5,7 +5,6 @@
* Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
*/
-#include <common.h>
#include <cpu_func.h>
#include <log.h>
#include <asm/cache.h>
diff --git a/drivers/soc/ti/keystone_serdes.c b/drivers/soc/ti/keystone_serdes.c
index 0e1bf8f..b196179 100644
--- a/drivers/soc/ti/keystone_serdes.c
+++ b/drivers/soc/ti/keystone_serdes.c
@@ -7,7 +7,6 @@
*/
#include <errno.h>
-#include <common.h>
#include <asm/io.h>
#include <asm/ti-common/keystone_serdes.h>
#include <linux/bitops.h>
diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c
index 4613909..e3bb2ed 100644
--- a/drivers/soc/ti/pruss.c
+++ b/drivers/soc/ti/pruss.c
@@ -5,7 +5,6 @@
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
-#include <common.h>
#include <dm.h>
#include <dm/of_access.h>
#include <errno.h>
@@ -205,6 +204,7 @@
static const struct udevice_id pruss_ids[] = {
{ .compatible = "ti,am654-icssg"},
+ { .compatible = "ti,am642-icssg"},
{}
};
diff --git a/drivers/sound/broadwell_i2s.c b/drivers/sound/broadwell_i2s.c
index 7f754e6..bc44b5e 100644
--- a/drivers/sound/broadwell_i2s.c
+++ b/drivers/sound/broadwell_i2s.c
@@ -9,7 +9,6 @@
#define LOG_CATEGORY UCLASS_I2S
-#include <common.h>
#include <dm.h>
#include <i2s.h>
#include <log.h>
diff --git a/drivers/sound/broadwell_sound.c b/drivers/sound/broadwell_sound.c
index 6e083fe..473f8d8 100644
--- a/drivers/sound/broadwell_sound.c
+++ b/drivers/sound/broadwell_sound.c
@@ -8,7 +8,6 @@
#define LOG_CATEGORY UCLASS_SOUND
-#include <common.h>
#include <audio_codec.h>
#include <dm.h>
#include <i2s.h>
diff --git a/drivers/sound/codec-uclass.c b/drivers/sound/codec-uclass.c
index 2cb233b..1c15606 100644
--- a/drivers/sound/codec-uclass.c
+++ b/drivers/sound/codec-uclass.c
@@ -6,7 +6,6 @@
#define LOG_CATEGORY UCLASS_AUDIO_CODEC
-#include <common.h>
#include <dm.h>
#include <audio_codec.h>
diff --git a/drivers/sound/da7219.c b/drivers/sound/da7219.c
index c1edef4..5b9b3f6 100644
--- a/drivers/sound/da7219.c
+++ b/drivers/sound/da7219.c
@@ -6,7 +6,6 @@
* Parts taken from coreboot
*/
-#include <common.h>
#include <dm.h>
#include <i2c.h>
#include <irq.h>
diff --git a/drivers/sound/hda_codec.c b/drivers/sound/hda_codec.c
index af6148e..da8bde6 100644
--- a/drivers/sound/hda_codec.c
+++ b/drivers/sound/hda_codec.c
@@ -7,7 +7,6 @@
#define LOG_CATEGORY UCLASS_SOUND
-#include <common.h>
#include <dm.h>
#include <hda_codec.h>
#include <log.h>
diff --git a/drivers/sound/i2s-uclass.c b/drivers/sound/i2s-uclass.c
index fc4f686..6263c4d 100644
--- a/drivers/sound/i2s-uclass.c
+++ b/drivers/sound/i2s-uclass.c
@@ -6,7 +6,6 @@
#define LOG_CATEGORY UCLASS_I2S
-#include <common.h>
#include <dm.h>
#include <i2s.h>
diff --git a/drivers/sound/i8254_beep.c b/drivers/sound/i8254_beep.c
index 5572dc4..7234ad4 100644
--- a/drivers/sound/i8254_beep.c
+++ b/drivers/sound/i8254_beep.c
@@ -3,7 +3,6 @@
* Copyright 2018 Google LLC
*/
-#include <common.h>
#include <dm.h>
#include <sound.h>
#include <asm/i8254.h>
diff --git a/drivers/sound/ivybridge_sound.c b/drivers/sound/ivybridge_sound.c
index d982219..aeeba1d 100644
--- a/drivers/sound/ivybridge_sound.c
+++ b/drivers/sound/ivybridge_sound.c
@@ -12,7 +12,6 @@
#define LOG_CATEGORY UCLASS_SOUND
-#include <common.h>
#include <dm.h>
#include <hda_codec.h>
#include <log.h>
diff --git a/drivers/sound/max98088.c b/drivers/sound/max98088.c
index c0463b8..d903764 100644
--- a/drivers/sound/max98088.c
+++ b/drivers/sound/max98088.c
@@ -8,7 +8,6 @@
* following the changes made in max98095.c
*/
-#include <common.h>
#include <audio_codec.h>
#include <div64.h>
#include <dm.h>
diff --git a/drivers/sound/max98090.c b/drivers/sound/max98090.c
index a798762..18a3ffa 100644
--- a/drivers/sound/max98090.c
+++ b/drivers/sound/max98090.c
@@ -5,7 +5,6 @@
* Copyright 2011 Maxim Integrated Products
*/
-#include <common.h>
#include <audio_codec.h>
#include <div64.h>
#include <dm.h>
diff --git a/drivers/sound/max98095.c b/drivers/sound/max98095.c
index d0f701a..96e772c 100644
--- a/drivers/sound/max98095.c
+++ b/drivers/sound/max98095.c
@@ -7,7 +7,6 @@
* Modified for U-Boot by R. Chandrasekar (rcsekar@samsung.com)
*/
-#include <common.h>
#include <audio_codec.h>
#include <dm.h>
#include <div64.h>
diff --git a/drivers/sound/max98357a.c b/drivers/sound/max98357a.c
index bdf6dc2..da56ffd 100644
--- a/drivers/sound/max98357a.c
+++ b/drivers/sound/max98357a.c
@@ -6,7 +6,6 @@
* Parts taken from coreboot
*/
-#include <common.h>
#include <audio_codec.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/sound/maxim_codec.c b/drivers/sound/maxim_codec.c
index 6553d95..98f094c 100644
--- a/drivers/sound/maxim_codec.c
+++ b/drivers/sound/maxim_codec.c
@@ -5,7 +5,6 @@
* Copyright 2011 Maxim Integrated Products
*/
-#include <common.h>
#include <div64.h>
#include <i2c.h>
#include <i2s.h>
diff --git a/drivers/sound/rockchip_i2s.c b/drivers/sound/rockchip_i2s.c
index 4e9e68a..5078dfb 100644
--- a/drivers/sound/rockchip_i2s.c
+++ b/drivers/sound/rockchip_i2s.c
@@ -7,7 +7,6 @@
#define LOG_CATEGORY UCLASS_I2S
-#include <common.h>
#include <dm.h>
#include <i2s.h>
#include <log.h>
diff --git a/drivers/sound/rockchip_sound.c b/drivers/sound/rockchip_sound.c
index 94058e6..418d2ef 100644
--- a/drivers/sound/rockchip_sound.c
+++ b/drivers/sound/rockchip_sound.c
@@ -6,7 +6,6 @@
#define LOG_CATEGORY UCLASS_SOUND
-#include <common.h>
#include <audio_codec.h>
#include <clk.h>
#include <dm.h>
diff --git a/drivers/sound/rt5677.c b/drivers/sound/rt5677.c
index b655bb4..b5c997c 100644
--- a/drivers/sound/rt5677.c
+++ b/drivers/sound/rt5677.c
@@ -5,7 +5,6 @@
#define LOG_CATEGORY UCLASS_SOUND
-#include <common.h>
#include <audio_codec.h>
#include <dm.h>
#include <i2c.h>
diff --git a/drivers/sound/samsung-i2s.c b/drivers/sound/samsung-i2s.c
index dc5a278..42175fd 100644
--- a/drivers/sound/samsung-i2s.c
+++ b/drivers/sound/samsung-i2s.c
@@ -4,11 +4,11 @@
* R. Chandrasekar <rcsekar@samsung.com>
*/
-#include <common.h>
#include <dm.h>
#include <i2s.h>
#include <log.h>
#include <sound.h>
+#include <time.h>
#include <asm/arch/clk.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/i2s-regs.h>
diff --git a/drivers/sound/samsung_sound.c b/drivers/sound/samsung_sound.c
index 473cedf..9150ad4 100644
--- a/drivers/sound/samsung_sound.c
+++ b/drivers/sound/samsung_sound.c
@@ -4,7 +4,6 @@
* Written by Simon Glass <sjg@chromium.org>
*/
-#include <common.h>
#include <audio_codec.h>
#include <dm.h>
#include <i2s.h>
diff --git a/drivers/sound/sandbox.c b/drivers/sound/sandbox.c
index c6cbd81..31ae153 100644
--- a/drivers/sound/sandbox.c
+++ b/drivers/sound/sandbox.c
@@ -5,7 +5,6 @@
#define LOG_CATEGORY UCLASS_SOUND
-#include <common.h>
#include <audio_codec.h>
#include <dm.h>
#include <i2s.h>
diff --git a/drivers/sound/sound-uclass.c b/drivers/sound/sound-uclass.c
index 2ffc4fc..b8a3dab 100644
--- a/drivers/sound/sound-uclass.c
+++ b/drivers/sound/sound-uclass.c
@@ -6,7 +6,6 @@
#define LOG_CATEGORY UCLASS_SOUND
-#include <common.h>
#include <dm.h>
#include <i2s.h>
#include <log.h>
diff --git a/drivers/sound/sound.c b/drivers/sound/sound.c
index c0fc50c..4fde298 100644
--- a/drivers/sound/sound.c
+++ b/drivers/sound/sound.c
@@ -4,9 +4,9 @@
* R. Chandrasekar <rcsekar@samsung.com>
*/
-#include <common.h>
#include <log.h>
#include <sound.h>
+#include <linux/string.h>
void sound_create_square_wave(uint sample_rate, unsigned short *data, int size,
uint freq, uint channels)
diff --git a/drivers/sound/tegra_ahub.c b/drivers/sound/tegra_ahub.c
index 495a29c..8f1b0c0 100644
--- a/drivers/sound/tegra_ahub.c
+++ b/drivers/sound/tegra_ahub.c
@@ -7,11 +7,11 @@
#define LOG_CATEGORY UCLASS_MISC
-#include <common.h>
#include <dm.h>
#include <i2s.h>
#include <log.h>
#include <misc.h>
+#include <time.h>
#include <asm/io.h>
#include <asm/arch-tegra/tegra_ahub.h>
#include <asm/arch-tegra/tegra_i2s.h>
diff --git a/drivers/sound/tegra_i2s.c b/drivers/sound/tegra_i2s.c
index 932f737..357aac3 100644
--- a/drivers/sound/tegra_i2s.c
+++ b/drivers/sound/tegra_i2s.c
@@ -5,7 +5,6 @@
*/
#define LOG_CATEGORY UCLASS_I2S
-#include <common.h>
#include <dm.h>
#include <i2s.h>
#include <log.h>
diff --git a/drivers/sound/tegra_sound.c b/drivers/sound/tegra_sound.c
index aef6a2e..152c929 100644
--- a/drivers/sound/tegra_sound.c
+++ b/drivers/sound/tegra_sound.c
@@ -6,7 +6,6 @@
#define LOG_CATEGORY UCLASS_I2S
-#include <common.h>
#include <audio_codec.h>
#include <dm.h>
#include <i2s.h>
diff --git a/drivers/sound/wm8994.c b/drivers/sound/wm8994.c
index fd64647..6b3091a 100644
--- a/drivers/sound/wm8994.c
+++ b/drivers/sound/wm8994.c
@@ -3,7 +3,6 @@
* Copyright (C) 2012 Samsung Electronics
* R. Chandrasekar <rcsekar@samsung.com>
*/
-#include <common.h>
#include <audio_codec.h>
#include <dm.h>
#include <div64.h>
diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c
index 989679e..8e227d1 100644
--- a/drivers/spi/altera_spi.c
+++ b/drivers/spi/altera_spi.c
@@ -6,7 +6,6 @@
* Copyright (c) 2005-2008 Analog Devices Inc.
* Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/spi/apple_spi.c b/drivers/spi/apple_spi.c
index f35f5af..5f94e9f 100644
--- a/drivers/spi/apple_spi.c
+++ b/drivers/spi/apple_spi.c
@@ -4,7 +4,6 @@
* Copyright The Asahi Linux Contributors
*/
-#include <common.h>
#include <dm.h>
#include <clk.h>
#include <spi.h>
diff --git a/drivers/spi/atcspi200_spi.c b/drivers/spi/atcspi200_spi.c
index 70cb242..929bf90 100644
--- a/drivers/spi/atcspi200_spi.c
+++ b/drivers/spi/atcspi200_spi.c
@@ -6,7 +6,6 @@
* Author: Rick Chen (rick@andestech.com)
*/
-#include <common.h>
#include <clk.h>
#include <log.h>
#include <malloc.h>
diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c
index 205567e..faefac7 100644
--- a/drivers/spi/ath79_spi.c
+++ b/drivers/spi/ath79_spi.c
@@ -3,7 +3,6 @@
* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
*/
-#include <common.h>
#include <clock_legacy.h>
#include <spi.h>
#include <dm.h>
diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
index bd73e4f..3efb661 100644
--- a/drivers/spi/atmel-quadspi.c
+++ b/drivers/spi/atmel-quadspi.c
@@ -12,7 +12,6 @@
#include <malloc.h>
#include <asm/io.h>
#include <clk.h>
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
index d4f0c4c..79f0100 100644
--- a/drivers/spi/atmel_spi.c
+++ b/drivers/spi/atmel_spi.c
@@ -2,7 +2,6 @@
/*
* Copyright (C) 2007 Atmel Corporation
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <fdtdec.h>
diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c
index 23ac5bb..1aa43fd 100644
--- a/drivers/spi/bcm63xx_hsspi.c
+++ b/drivers/spi/bcm63xx_hsspi.c
@@ -7,7 +7,6 @@
* Copyright (C) 2012-2013 Jonas Gorski <jogo@openwrt.org>
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/spi/bcm63xx_spi.c b/drivers/spi/bcm63xx_spi.c
index 889ac1f..595b41c 100644
--- a/drivers/spi/bcm63xx_spi.c
+++ b/drivers/spi/bcm63xx_spi.c
@@ -7,7 +7,6 @@
* Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/spi/bcmbca_hsspi.c b/drivers/spi/bcmbca_hsspi.c
index af45882..eff9e11 100644
--- a/drivers/spi/bcmbca_hsspi.c
+++ b/drivers/spi/bcmbca_hsspi.c
@@ -8,7 +8,6 @@
* Copyright (C) 2021 Broadcom Ltd
*/
-#include <common.h>
#include <asm/io.h>
#include <clk.h>
#include <spi.h>
diff --git a/drivers/spi/ca_sflash.c b/drivers/spi/ca_sflash.c
index 38bddd3..a99a8a4 100644
--- a/drivers/spi/ca_sflash.c
+++ b/drivers/spi/ca_sflash.c
@@ -7,7 +7,6 @@
* Author: PengPeng Chen <pengpeng.chen@cortina-access.com>
*/
-#include <common.h>
#include <malloc.h>
#include <clk.h>
#include <dm.h>
diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c
index c2be307..222f828 100644
--- a/drivers/spi/cadence_ospi_versal.c
+++ b/drivers/spi/cadence_ospi_versal.c
@@ -6,7 +6,6 @@
*/
#include <clk.h>
-#include <common.h>
#include <memalign.h>
#include <wait_bit.h>
#include <asm/io.h>
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index f4593c4..75e5223 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -4,7 +4,6 @@
* Altera Corporation <www.altera.com>
*/
-#include <common.h>
#include <clk.h>
#include <log.h>
#include <dm.h>
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index fb90532..93ab2b5 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -25,7 +25,6 @@
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include <common.h>
#include <log.h>
#include <asm/io.h>
#include <dma.h>
diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c
index 1a841b5..8234468 100644
--- a/drivers/spi/cf_spi.c
+++ b/drivers/spi/cf_spi.c
@@ -13,7 +13,6 @@
* TODO: fsl_dspi.c should work as a driver for the DSPI module.
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <asm/global_data.h>
diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
index 25f5e9f..04c134b 100644
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c
@@ -8,7 +8,7 @@
* Copyright (C) 2007 Atmel Corporation
*/
-#include <common.h>
+#include <config.h>
#include <log.h>
#include <spi.h>
#include <malloc.h>
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 22a79da..6bd48b1 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -11,7 +11,6 @@
*/
#define LOG_CATEGORY UCLASS_SPI
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <dm/device_compat.h>
diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c
index 1bcc3ad..1b9bf00 100644
--- a/drivers/spi/exynos_spi.c
+++ b/drivers/spi/exynos_spi.c
@@ -4,7 +4,6 @@
* Padmavathi Venna <padma.v@samsung.com>
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c
index 9b3d5a9..1d4d90c 100644
--- a/drivers/spi/fsl_dspi.c
+++ b/drivers/spi/fsl_dspi.c
@@ -11,7 +11,6 @@
#include <asm/global_data.h>
#include <linux/math64.h>
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
index b1d964d..2638ed2 100644
--- a/drivers/spi/fsl_espi.c
+++ b/drivers/spi/fsl_espi.c
@@ -8,7 +8,7 @@
* Chuanhua Han (chuanhua.han@nxp.com)
*/
-#include <common.h>
+#include <config.h>
#include <log.h>
#include <linux/bitops.h>
#include <linux/delay.h>
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 3f97730..8a0a53c 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -23,7 +23,6 @@
* Transition to spi-mem in spi-fsl-qspi.c
*/
-#include <common.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <log.h>
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 9142ffd..e48ca65 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -7,7 +7,6 @@
#define LOG_CATEGORY UCLASS_SPI
-#include <common.h>
#include <bootstage.h>
#include <div64.h>
#include <dm.h>
diff --git a/drivers/spi/iproc_qspi.c b/drivers/spi/iproc_qspi.c
index b5c2743..09f30c2 100644
--- a/drivers/spi/iproc_qspi.c
+++ b/drivers/spi/iproc_qspi.c
@@ -3,7 +3,6 @@
* Copyright 2020-2021 Broadcom
*/
-#include <common.h>
#include <dm.h>
#include <spi.h>
#include <spi-mem.h>
diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c
index 2bb7390..095cbea 100644
--- a/drivers/spi/kirkwood_spi.c
+++ b/drivers/spi/kirkwood_spi.c
@@ -7,7 +7,7 @@
* Derived from drivers/spi/mpc8xxx_spi.c
*/
-#include <common.h>
+#include <config.h>
#include <dm.h>
#include <log.h>
#include <malloc.h>
diff --git a/drivers/spi/meson_spifc.c b/drivers/spi/meson_spifc.c
index d99a151..d7ebb6b 100644
--- a/drivers/spi/meson_spifc.c
+++ b/drivers/spi/meson_spifc.c
@@ -7,7 +7,6 @@
* Amlogic Meson SPI Flash Controller driver
*/
-#include <common.h>
#include <log.h>
#include <spi.h>
#include <clk.h>
diff --git a/drivers/spi/microchip_coreqspi.c b/drivers/spi/microchip_coreqspi.c
index 5fe0c8e..234b168 100644
--- a/drivers/spi/microchip_coreqspi.c
+++ b/drivers/spi/microchip_coreqspi.c
@@ -5,7 +5,6 @@
* Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/spi/mpc8xx_spi.c b/drivers/spi/mpc8xx_spi.c
index e1448cc..7e72fb9 100644
--- a/drivers/spi/mpc8xx_spi.c
+++ b/drivers/spi/mpc8xx_spi.c
@@ -16,7 +16,6 @@
*
*/
-#include <common.h>
#include <dm.h>
#include <malloc.h>
#include <mpc8xx.h>
diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c
index 7d15390..cd624f4 100644
--- a/drivers/spi/mpc8xxx_spi.c
+++ b/drivers/spi/mpc8xxx_spi.c
@@ -4,7 +4,6 @@
* With help from the common/soft_spi and arch/powerpc/cpu/mpc8260 drivers
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <errno.h>
diff --git a/drivers/spi/mscc_bb_spi.c b/drivers/spi/mscc_bb_spi.c
index 95bea0d..ad4daeb 100644
--- a/drivers/spi/mscc_bb_spi.c
+++ b/drivers/spi/mscc_bb_spi.c
@@ -5,7 +5,6 @@
* Copyright (c) 2018 Microsemi Corporation
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/spi/mt7621_spi.c b/drivers/spi/mt7621_spi.c
index 3d00809..e46942d 100644
--- a/drivers/spi/mt7621_spi.c
+++ b/drivers/spi/mt7621_spi.c
@@ -8,7 +8,6 @@
* Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/spi/mtk_snfi_spi.c b/drivers/spi/mtk_snfi_spi.c
index 3decb37..830424b 100644
--- a/drivers/spi/mtk_snfi_spi.c
+++ b/drivers/spi/mtk_snfi_spi.c
@@ -5,7 +5,6 @@
* Author: Weijie Gao <weijie.gao@mediatek.com>
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <errno.h>
diff --git a/drivers/spi/mtk_snor.c b/drivers/spi/mtk_snor.c
index 4b7d4a6..f202b2f 100644
--- a/drivers/spi/mtk_snor.c
+++ b/drivers/spi/mtk_snor.c
@@ -7,7 +7,6 @@
// Some parts are based on drivers/spi/spi-mtk-nor.c of linux version
#include <clk.h>
-#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <dm/device.h>
diff --git a/drivers/spi/mvebu_a3700_spi.c b/drivers/spi/mvebu_a3700_spi.c
index bba2383..fde9b14 100644
--- a/drivers/spi/mvebu_a3700_spi.c
+++ b/drivers/spi/mvebu_a3700_spi.c
@@ -5,7 +5,6 @@
* Copyright (C) 2016 Stefan Roese <sr@denx.de>
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <malloc.h>
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index e291092..ff61a14 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -3,7 +3,7 @@
* Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
*/
-#include <common.h>
+#include <config.h>
#include <clk.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
index 773e26b..ad9e490 100644
--- a/drivers/spi/mxs_spi.c
+++ b/drivers/spi/mxs_spi.c
@@ -12,7 +12,6 @@
* GPIO driven chipselects are not supported.
*/
-#include <common.h>
#include <dm.h>
#include <dt-structs.h>
#include <cpu_func.h>
diff --git a/drivers/spi/npcm_pspi.c b/drivers/spi/npcm_pspi.c
index c944130..7708a96 100644
--- a/drivers/spi/npcm_pspi.c
+++ b/drivers/spi/npcm_pspi.c
@@ -3,7 +3,6 @@
* Copyright (c) 2021 Nuvoton Technology.
*/
-#include <common.h>
#include <dm.h>
#include <spi.h>
#include <clk.h>
diff --git a/drivers/spi/nxp_fspi.c b/drivers/spi/nxp_fspi.c
index 5db27f9..fefdaaa 100644
--- a/drivers/spi/nxp_fspi.c
+++ b/drivers/spi/nxp_fspi.c
@@ -33,7 +33,6 @@
* Frieder Schrempf <frieder.schrempf@kontron.de>
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <dm/device_compat.h>
diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index 5cce6ba..3d82fc7 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -16,9 +16,9 @@
* Modified by Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
*/
-#include <common.h>
#include <dm.h>
#include <spi.h>
+#include <time.h>
#include <malloc.h>
#include <asm/global_data.h>
#include <asm/io.h>
diff --git a/drivers/spi/pic32_spi.c b/drivers/spi/pic32_spi.c
index 45f07f0..e11ae7f 100644
--- a/drivers/spi/pic32_spi.c
+++ b/drivers/spi/pic32_spi.c
@@ -6,7 +6,6 @@
* Purna Chandra Mandal <purna.mandal@microchip.com>
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c
index e2b49eb..1e20701 100644
--- a/drivers/spi/pl022_spi.c
+++ b/drivers/spi/pl022_spi.c
@@ -10,7 +10,6 @@
*/
#include <clk.h>
-#include <common.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <fdtdec.h>
diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c
index 8aff223..e6b602c 100644
--- a/drivers/spi/renesas_rpc_spi.c
+++ b/drivers/spi/renesas_rpc_spi.c
@@ -5,7 +5,6 @@
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*/
-#include <common.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <clk.h>
diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index c8694fd..4571dc9 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -10,7 +10,6 @@
* Peter, Software Engineering, <superpeter.cai@gmail.com>.
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <dt-structs.h>
diff --git a/drivers/spi/sandbox_spi.c b/drivers/spi/sandbox_spi.c
index f844597..4cc0161 100644
--- a/drivers/spi/sandbox_spi.c
+++ b/drivers/spi/sandbox_spi.c
@@ -10,7 +10,6 @@
#define LOG_CATEGORY UCLASS_SPI
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <malloc.h>
diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c
index 7259499..b7364a6 100644
--- a/drivers/spi/sh_qspi.c
+++ b/drivers/spi/sh_qspi.c
@@ -8,7 +8,6 @@
#define LOG_CATEGORY UCLASS_SPI
-#include <common.h>
#include <console.h>
#include <malloc.h>
#include <spi.h>
diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c
index 0fa1433..9bdb4a5 100644
--- a/drivers/spi/soft_spi.c
+++ b/drivers/spi/soft_spi.c
@@ -9,7 +9,6 @@
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
index 7d5f101..d91d58d 100644
--- a/drivers/spi/spi-aspeed-smc.c
+++ b/drivers/spi/spi-aspeed-smc.c
@@ -12,7 +12,6 @@
#include <asm/io.h>
#include <clk.h>
-#include <common.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
diff --git a/drivers/spi/spi-emul-uclass.c b/drivers/spi/spi-emul-uclass.c
index 64bc19c..d92f36b 100644
--- a/drivers/spi/spi-emul-uclass.c
+++ b/drivers/spi/spi-emul-uclass.c
@@ -5,7 +5,6 @@
#define LOG_CATEGORY UCLASS_SPI_EMUL
-#include <common.h>
#include <dm.h>
#include <spi.h>
#include <spi_flash.h>
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index b7eca58..3579b7d 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -13,7 +13,6 @@
#include <linux/pm_runtime.h>
#include "internals.h"
#else
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <malloc.h>
diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
index f663b9d..b98bcd9 100644
--- a/drivers/spi/spi-mxic.c
+++ b/drivers/spi/spi-mxic.c
@@ -6,7 +6,6 @@
* zhengxunli <zhengxunli@mxic.com.tw>
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <errno.h>
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index 572cef1..836c550 100644
--- a/drivers/spi/spi-qup.c
+++ b/drivers/spi/spi-qup.c
@@ -15,7 +15,6 @@
#include <asm/gpio.h>
#include <asm/io.h>
#include <clk.h>
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <linux/delay.h>
diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c
index ea372a0..0c8666c 100644
--- a/drivers/spi/spi-sifive.c
+++ b/drivers/spi/spi-sifive.c
@@ -6,7 +6,6 @@
* SiFive SPI controller driver (master mode only)
*/
-#include <common.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <malloc.h>
diff --git a/drivers/spi/spi-sn-f-ospi.c b/drivers/spi/spi-sn-f-ospi.c
index e3633a5..fc82791 100644
--- a/drivers/spi/spi-sn-f-ospi.c
+++ b/drivers/spi/spi-sn-f-ospi.c
@@ -5,7 +5,6 @@
*/
#include <clk.h>
-#include <common.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <linux/bitfield.h>
diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c
index 9ec6b35..13725ee 100644
--- a/drivers/spi/spi-sunxi.c
+++ b/drivers/spi/spi-sunxi.c
@@ -18,7 +18,6 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c
index 553f968..eb522fd 100644
--- a/drivers/spi/spi-synquacer.c
+++ b/drivers/spi/spi-synquacer.c
@@ -6,7 +6,6 @@
*/
#include <clk.h>
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <time.h>
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index f4795e6..6e28172 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -5,7 +5,6 @@
#define LOG_CATEGORY UCLASS_SPI
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 22910de..50a076a 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -3,7 +3,6 @@
* Copyright (c) 2011 The Chromium OS Authors.
*/
-#include <common.h>
#include <fdtdec.h>
#include <malloc.h>
#include <spi.h>
diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index 2ffa201..2812a4d 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -9,7 +9,6 @@
#define LOG_CATEGORY UCLASS_SPI
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/spi/stm32_spi.c b/drivers/spi/stm32_spi.c
index ddb410a..97b83b1 100644
--- a/drivers/spi/stm32_spi.c
+++ b/drivers/spi/stm32_spi.c
@@ -7,7 +7,6 @@
#define LOG_CATEGORY UCLASS_SPI
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <errno.h>
diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c
index f0256d8..57f1a8f 100644
--- a/drivers/spi/tegra114_spi.c
+++ b/drivers/spi/tegra114_spi.c
@@ -5,7 +5,6 @@
* Copyright (c) 2010-2013 NVIDIA Corporation
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <time.h>
diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c
index 10e38cf..1911480 100644
--- a/drivers/spi/tegra20_sflash.c
+++ b/drivers/spi/tegra20_sflash.c
@@ -5,7 +5,6 @@
* With more help from omap3_spi SPI driver
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c
index d0e7885..d54a504 100644
--- a/drivers/spi/tegra20_slink.c
+++ b/drivers/spi/tegra20_slink.c
@@ -5,7 +5,6 @@
* Copyright (c) 2010-2013 NVIDIA Corporation
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <time.h>
diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c
index 5c8c185..b969a79 100644
--- a/drivers/spi/tegra210_qspi.c
+++ b/drivers/spi/tegra210_qspi.c
@@ -6,7 +6,6 @@
*
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <time.h>
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 99acb10..a16412e 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -5,7 +5,6 @@
* Copyright (C) 2013, Texas Instruments, Incorporated
*/
-#include <common.h>
#include <cpu_func.h>
#include <log.h>
#include <asm/cache.h>
diff --git a/drivers/spi/uniphier_spi.c b/drivers/spi/uniphier_spi.c
index 6402acb..8f2c0fb 100644
--- a/drivers/spi/uniphier_spi.c
+++ b/drivers/spi/uniphier_spi.c
@@ -5,7 +5,6 @@
*/
#include <clk.h>
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <time.h>
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 94ddf49..0e7fa3a 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -13,7 +13,6 @@
*/
#include <config.h>
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index cb52c0f..b71b9a6 100644
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -7,7 +7,6 @@
*/
#include <clk.h>
-#include <common.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <log.h>
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index b3e0858..ebcb5b6 100644
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -6,7 +6,6 @@
* Xilinx Zynq PS SPI controller driver (master mode only)
*/
-#include <common.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <log.h>
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index a323994..61349a4 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -7,7 +7,6 @@
#define LOG_CATEGORY UCLASS_SPI
-#include <common.h>
#include <cpu_func.h>
#include <log.h>
#include <asm/arch/sys_proto.h>
diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c
index 244de69..b0d6226 100644
--- a/drivers/spmi/spmi-msm.c
+++ b/drivers/spmi/spmi-msm.c
@@ -7,7 +7,6 @@
* Loosely based on Little Kernel driver
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
diff --git a/drivers/spmi/spmi-sandbox.c b/drivers/spmi/spmi-sandbox.c
index f677294..992b08d 100644
--- a/drivers/spmi/spmi-sandbox.c
+++ b/drivers/spmi/spmi-sandbox.c
@@ -7,7 +7,6 @@
* (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <spmi/spmi.h>
diff --git a/drivers/spmi/spmi-uclass.c b/drivers/spmi/spmi-uclass.c
index 9d9f46a..34fe8f6 100644
--- a/drivers/spmi/spmi-uclass.c
+++ b/drivers/spmi/spmi-uclass.c
@@ -7,7 +7,6 @@
#define LOG_CATEGORY UCLASS_SPMI
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <spmi/spmi.h>
diff --git a/drivers/sysinfo/gazerbeam.c b/drivers/sysinfo/gazerbeam.c
index c1fae6c..a3c9d53 100644
--- a/drivers/sysinfo/gazerbeam.c
+++ b/drivers/sysinfo/gazerbeam.c
@@ -4,7 +4,6 @@
* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
*/
-#include <common.h>
#include <dm.h>
#include <sysinfo.h>
#include <i2c.h>
diff --git a/drivers/sysinfo/gpio.c b/drivers/sysinfo/gpio.c
index 82f9030..aaca318 100644
--- a/drivers/sysinfo/gpio.c
+++ b/drivers/sysinfo/gpio.c
@@ -3,7 +3,6 @@
* Copyright (C) 2021 Sean Anderson <sean.anderson@seco.com>
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <sysinfo.h>
diff --git a/drivers/sysinfo/rcar3.c b/drivers/sysinfo/rcar3.c
index 7b12798..37e2ccc 100644
--- a/drivers/sysinfo/rcar3.c
+++ b/drivers/sysinfo/rcar3.c
@@ -3,7 +3,6 @@
* Copyright (C) 2021 Marek Vasut <marek.vasut+renesas@gmail.com>
*/
-#include <common.h>
#include <dm.h>
#include <i2c_eeprom.h>
#include <log.h>
diff --git a/drivers/sysinfo/sandbox.c b/drivers/sysinfo/sandbox.c
index d270a26..d397209 100644
--- a/drivers/sysinfo/sandbox.c
+++ b/drivers/sysinfo/sandbox.c
@@ -4,7 +4,6 @@
* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
*/
-#include <common.h>
#include <dm.h>
#include <sysinfo.h>
diff --git a/drivers/sysinfo/smbios.c b/drivers/sysinfo/smbios.c
index 80ebd19..a7ac8e3 100644
--- a/drivers/sysinfo/smbios.c
+++ b/drivers/sysinfo/smbios.c
@@ -4,7 +4,6 @@
* Written by Simon Glass <sjg@chromium.org>
*/
-#include <common.h>
#include <dm.h>
#include <sysinfo.h>
diff --git a/drivers/sysinfo/sysinfo-uclass.c b/drivers/sysinfo/sysinfo-uclass.c
index 10194d0..d77d1e3 100644
--- a/drivers/sysinfo/sysinfo-uclass.c
+++ b/drivers/sysinfo/sysinfo-uclass.c
@@ -6,7 +6,6 @@
#define LOG_CATEGORY UCLASS_SYSINFO
-#include <common.h>
#include <dm.h>
#include <sysinfo.h>
diff --git a/drivers/sysreset/poweroff_gpio.c b/drivers/sysreset/poweroff_gpio.c
index ad04e4b..d922002 100644
--- a/drivers/sysreset/poweroff_gpio.c
+++ b/drivers/sysreset/poweroff_gpio.c
@@ -11,7 +11,6 @@
* Copyright (C) 2012 Jamie Lentin
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/sysreset/sysreset-ti-sci.c b/drivers/sysreset/sysreset-ti-sci.c
index 0de1326..451fc5d 100644
--- a/drivers/sysreset/sysreset-ti-sci.c
+++ b/drivers/sysreset/sysreset-ti-sci.c
@@ -6,7 +6,6 @@
* Andreas Dannenberg <dannenberg@ti.com>
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/sysreset/sysreset-uclass.c b/drivers/sysreset/sysreset-uclass.c
index 6151b5f..0abb404 100644
--- a/drivers/sysreset/sysreset-uclass.c
+++ b/drivers/sysreset/sysreset-uclass.c
@@ -6,7 +6,6 @@
#define LOG_CATEGORY UCLASS_SYSRESET
-#include <common.h>
#include <command.h>
#include <cpu_func.h>
#include <dm.h>
diff --git a/drivers/sysreset/sysreset_ast.c b/drivers/sysreset/sysreset_ast.c
index 92fad96..ef09440 100644
--- a/drivers/sysreset/sysreset_ast.c
+++ b/drivers/sysreset/sysreset_ast.c
@@ -3,7 +3,6 @@
* (C) Copyright 2016 Google, Inc
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/sysreset/sysreset_at91.c b/drivers/sysreset/sysreset_at91.c
index fc85f31..457042c 100644
--- a/drivers/sysreset/sysreset_at91.c
+++ b/drivers/sysreset/sysreset_at91.c
@@ -7,7 +7,6 @@
#include <asm/io.h>
#include <asm/arch/at91_rstc.h>
#include <clk.h>
-#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <dm/device_compat.h>
diff --git a/drivers/sysreset/sysreset_gpio.c b/drivers/sysreset/sysreset_gpio.c
index de42b59..4701884 100644
--- a/drivers/sysreset/sysreset_gpio.c
+++ b/drivers/sysreset/sysreset_gpio.c
@@ -3,7 +3,6 @@
* Copyright (C) 2018 Xilinx, Inc. - Michal Simek
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/sysreset/sysreset_microblaze.c b/drivers/sysreset/sysreset_microblaze.c
index 83a7f77..b81d82f 100644
--- a/drivers/sysreset/sysreset_microblaze.c
+++ b/drivers/sysreset/sysreset_microblaze.c
@@ -3,7 +3,6 @@
* Copyright (C) 2018 Xilinx, Inc. - Michal Simek
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <sysreset.h>
diff --git a/drivers/sysreset/sysreset_mpc83xx.c b/drivers/sysreset/sysreset_mpc83xx.c
index ca48328..dca4929 100644
--- a/drivers/sysreset/sysreset_mpc83xx.c
+++ b/drivers/sysreset/sysreset_mpc83xx.c
@@ -4,7 +4,6 @@
* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
*/
-#include <common.h>
#include <command.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/sysreset/sysreset_octeon.c b/drivers/sysreset/sysreset_octeon.c
index ebdea6a..c162237 100644
--- a/drivers/sysreset/sysreset_octeon.c
+++ b/drivers/sysreset/sysreset_octeon.c
@@ -3,7 +3,6 @@
* Copyright (C) 2020 Stefan Roese <sr@denx.de>
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <sysreset.h>
diff --git a/drivers/sysreset/sysreset_psci.c b/drivers/sysreset/sysreset_psci.c
index aa09d0b..89b4f2d 100644
--- a/drivers/sysreset/sysreset_psci.c
+++ b/drivers/sysreset/sysreset_psci.c
@@ -3,7 +3,6 @@
* Copyright (C) 2017 Masahiro Yamada <yamada.masahiro@socionext.com>
*/
-#include <common.h>
#include <dm.h>
#include <sysreset.h>
#include <linux/errno.h>
diff --git a/drivers/sysreset/sysreset_resetctl.c b/drivers/sysreset/sysreset_resetctl.c
index 25bd5c9..fbe3999 100644
--- a/drivers/sysreset/sysreset_resetctl.c
+++ b/drivers/sysreset/sysreset_resetctl.c
@@ -5,7 +5,6 @@
* Author: Weijie Gao <weijie.gao@mediatek.com>
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <sysreset.h>
diff --git a/drivers/sysreset/sysreset_rockchip.c b/drivers/sysreset/sysreset_rockchip.c
index f353f9b..00308f9 100644
--- a/drivers/sysreset/sysreset_rockchip.c
+++ b/drivers/sysreset/sysreset_rockchip.c
@@ -3,7 +3,6 @@
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <sysreset.h>
diff --git a/drivers/sysreset/sysreset_sandbox.c b/drivers/sysreset/sysreset_sandbox.c
index c12eda8..93179f9 100644
--- a/drivers/sysreset/sysreset_sandbox.c
+++ b/drivers/sysreset/sysreset_sandbox.c
@@ -4,7 +4,6 @@
* Written by Simon Glass <sjg@chromium.org>
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <sysreset.h>
diff --git a/drivers/sysreset/sysreset_sbi.c b/drivers/sysreset/sysreset_sbi.c
index 5e8090d..4581912 100644
--- a/drivers/sysreset/sysreset_sbi.c
+++ b/drivers/sysreset/sysreset_sbi.c
@@ -3,7 +3,6 @@
* Copyright 2021, Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/sysreset/sysreset_socfpga.c b/drivers/sysreset/sysreset_socfpga.c
index 9b62dd5..a07b0f4 100644
--- a/drivers/sysreset/sysreset_socfpga.c
+++ b/drivers/sysreset/sysreset_socfpga.c
@@ -4,7 +4,6 @@
* Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <sysreset.h>
diff --git a/drivers/sysreset/sysreset_socfpga_soc64.c b/drivers/sysreset/sysreset_socfpga_soc64.c
index 9837aad..6f44792 100644
--- a/drivers/sysreset/sysreset_socfpga_soc64.c
+++ b/drivers/sysreset/sysreset_socfpga_soc64.c
@@ -4,7 +4,6 @@
* Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <sysreset.h>
diff --git a/drivers/sysreset/sysreset_sti.c b/drivers/sysreset/sysreset_sti.c
index edd90aa..110b7e2 100644
--- a/drivers/sysreset/sysreset_sti.c
+++ b/drivers/sysreset/sysreset_sti.c
@@ -4,7 +4,6 @@
* Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
*/
-#include <common.h>
#include <dm.h>
#include <regmap.h>
#include <syscon.h>
diff --git a/drivers/sysreset/sysreset_syscon.c b/drivers/sysreset/sysreset_syscon.c
index e468dac..57144fa 100644
--- a/drivers/sysreset/sysreset_syscon.c
+++ b/drivers/sysreset/sysreset_syscon.c
@@ -7,7 +7,6 @@
* Author: Feng Kan <fkan@apm.com>
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <regmap.h>
diff --git a/drivers/sysreset/sysreset_watchdog.c b/drivers/sysreset/sysreset_watchdog.c
index 6db5aa7..49c061e 100644
--- a/drivers/sysreset/sysreset_watchdog.c
+++ b/drivers/sysreset/sysreset_watchdog.c
@@ -3,7 +3,6 @@
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
*/
-#include <common.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <errno.h>
diff --git a/drivers/sysreset/sysreset_x86.c b/drivers/sysreset/sysreset_x86.c
index dc772b5..c2f28c6 100644
--- a/drivers/sysreset/sysreset_x86.c
+++ b/drivers/sysreset/sysreset_x86.c
@@ -5,7 +5,6 @@
* Generic reset driver for x86 processor
*/
-#include <common.h>
#include <dm.h>
#include <efi_loader.h>
#include <pch.h>
diff --git a/drivers/sysreset/sysreset_xtfpga.c b/drivers/sysreset/sysreset_xtfpga.c
index 84fbc79..ab71ea1 100644
--- a/drivers/sysreset/sysreset_xtfpga.c
+++ b/drivers/sysreset/sysreset_xtfpga.c
@@ -5,7 +5,7 @@
* (C) Copyright 2016 Cadence Design Systems Inc.
*/
-#include <common.h>
+#include <config.h>
#include <dm.h>
#include <errno.h>
#include <sysreset.h>
diff --git a/drivers/thermal/imx_scu_thermal.c b/drivers/thermal/imx_scu_thermal.c
index 3ec131c..fc2b0e2 100644
--- a/drivers/thermal/imx_scu_thermal.c
+++ b/drivers/thermal/imx_scu_thermal.c
@@ -4,7 +4,6 @@
*/
#include <config.h>
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
index 2f6343e..ea1fcc3 100644
--- a/drivers/thermal/imx_thermal.c
+++ b/drivers/thermal/imx_thermal.c
@@ -6,7 +6,6 @@
*/
#include <config.h>
-#include <common.h>
#include <div64.h>
#include <fuse.h>
#include <log.h>
diff --git a/drivers/thermal/imx_tmu.c b/drivers/thermal/imx_tmu.c
index ea6c832..70d002a 100644
--- a/drivers/thermal/imx_tmu.c
+++ b/drivers/thermal/imx_tmu.c
@@ -5,7 +5,6 @@
*/
#include <config.h>
-#include <common.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
diff --git a/drivers/thermal/thermal-uclass.c b/drivers/thermal/thermal-uclass.c
index 700df8a..f0fe912 100644
--- a/drivers/thermal/thermal-uclass.c
+++ b/drivers/thermal/thermal-uclass.c
@@ -5,7 +5,6 @@
#define LOG_CATEGORY UCLASS_THERMAL
-#include <common.h>
#include <dm.h>
#include <thermal.h>
#include <errno.h>
diff --git a/drivers/thermal/thermal_sandbox.c b/drivers/thermal/thermal_sandbox.c
index 7dc0d10..9af0d02 100644
--- a/drivers/thermal/thermal_sandbox.c
+++ b/drivers/thermal/thermal_sandbox.c
@@ -6,7 +6,6 @@
* Sandbox driver for the thermal uclass.
*/
-#include <common.h>
#include <dm.h>
#include <thermal.h>
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 60519c3..6b1de82 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -50,6 +50,14 @@
use an early timer. These functions must be supported by your timer
driver: timer_early_get_count() and timer_early_get_rate().
+config ADI_SC5XX_TIMER
+ bool "ADI ADSP-SC5xx Timer Support"
+ depends on TIMER && (SC57X || SC58X || SC59X || SC59X_64)
+ help
+ gptimer based timer support on ADI's ADSP-SC5xx platforms. Available
+ but not required on sc59x-64-based platforms (598 and similar).
+ Required on 32-bit platforms (sc57x, sc58x, sc594 and earlier).
+
config ALTERA_TIMER
bool "Altera timer support"
depends on TIMER
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index b93145e..fb95c88 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -3,6 +3,7 @@
# Copyright (C) 2015 Thomas Chou <thomas@wytron.com.tw>
obj-y += timer-uclass.o
+obj-$(CONFIG_ADI_SC5XX_TIMER) += adi_sc5xx_timer.o
obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
obj-$(CONFIG_$(SPL_)ANDES_PLMT_TIMER) += andes_plmt_timer.o
obj-$(CONFIG_ARC_TIMER) += arc_timer.o
diff --git a/drivers/timer/adi_sc5xx_timer.c b/drivers/timer/adi_sc5xx_timer.c
new file mode 100644
index 0000000..11c0984
--- /dev/null
+++ b/drivers/timer/adi_sc5xx_timer.c
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Converted to driver model by Nathan Barrett-Morrison
+ *
+ * Author: Greg Malysa <greg.malysa@timesys.com>
+ * Additional Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ *
+ * dm timer implementation for ADI ADSP-SC5xx SoCs
+ *
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <timer.h>
+#include <asm/io.h>
+#include <dm/device_compat.h>
+#include <linux/compiler_types.h>
+
+/*
+ * Timer Configuration Register Bits
+ */
+#define TIMER_OUT_DIS 0x0800
+#define TIMER_PULSE_HI 0x0080
+#define TIMER_MODE_PWM_CONT 0x000c
+
+#define __BFP(m) u16 m; u16 __pad_##m
+
+struct gptimer3 {
+ __BFP(config);
+ u32 counter;
+ u32 period;
+ u32 width;
+ u32 delay;
+};
+
+struct gptimer3_group_regs {
+ __BFP(run);
+ __BFP(enable);
+ __BFP(disable);
+ __BFP(stop_cfg);
+ __BFP(stop_cfg_set);
+ __BFP(stop_cfg_clr);
+ __BFP(data_imsk);
+ __BFP(stat_imsk);
+ __BFP(tr_msk);
+ __BFP(tr_ie);
+ __BFP(data_ilat);
+ __BFP(stat_ilat);
+ __BFP(err_status);
+ __BFP(bcast_per);
+ __BFP(bcast_wid);
+ __BFP(bcast_dly);
+};
+
+#define MAX_TIM_LOAD 0xFFFFFFFF
+
+struct adi_gptimer_priv {
+ struct gptimer3_group_regs __iomem *timer_group;
+ struct gptimer3 __iomem *timer_base;
+ u32 prev;
+ u64 upper;
+};
+
+static u64 adi_gptimer_get_count(struct udevice *udev)
+{
+ struct adi_gptimer_priv *priv = dev_get_priv(udev);
+
+ u32 now = readl(&priv->timer_base->counter);
+
+ if (now < priv->prev)
+ priv->upper += (1ull << 32);
+
+ priv->prev = now;
+
+ return (priv->upper + (u64)now);
+}
+
+static const struct timer_ops adi_gptimer_ops = {
+ .get_count = adi_gptimer_get_count,
+};
+
+static int adi_gptimer_probe(struct udevice *udev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(udev);
+ struct adi_gptimer_priv *priv = dev_get_priv(udev);
+ struct clk clk;
+ u16 imask;
+ int ret;
+
+ priv->timer_group = dev_remap_addr_index(udev, 0);
+ priv->timer_base = dev_remap_addr_index(udev, 1);
+ priv->upper = 0;
+ priv->prev = 0;
+
+ if (!priv->timer_group || !priv->timer_base) {
+ dev_err(udev, "Missing timer_group or timer_base reg entries\n");
+ return -ENODEV;
+ }
+
+ ret = clk_get_by_index(udev, 0, &clk);
+ if (ret < 0) {
+ dev_err(udev, "Missing clock reference for timer\n");
+ return ret;
+ }
+
+ ret = clk_enable(&clk);
+ if (ret) {
+ dev_err(udev, "Failed to enable clock\n");
+ return ret;
+ }
+
+ uc_priv->clock_rate = clk_get_rate(&clk);
+
+ /* Enable timer */
+ writew(TIMER_OUT_DIS | TIMER_MODE_PWM_CONT | TIMER_PULSE_HI,
+ &priv->timer_base->config);
+ writel(MAX_TIM_LOAD, &priv->timer_base->period);
+ writel(MAX_TIM_LOAD - 1, &priv->timer_base->width);
+
+ /* We only use timer 0 in uboot */
+ imask = readw(&priv->timer_group->data_imsk);
+ imask &= ~(1 << 0);
+ writew(imask, &priv->timer_group->data_imsk);
+ writew((1 << 0), &priv->timer_group->enable);
+
+ return 0;
+}
+
+static const struct udevice_id adi_gptimer_ids[] = {
+ { .compatible = "adi,sc5xx-gptimer" },
+ { },
+};
+
+U_BOOT_DRIVER(adi_gptimer) = {
+ .name = "adi_gptimer",
+ .id = UCLASS_TIMER,
+ .of_match = adi_gptimer_ids,
+ .priv_auto = sizeof(struct adi_gptimer_priv),
+ .probe = adi_gptimer_probe,
+ .ops = &adi_gptimer_ops,
+};
diff --git a/drivers/timer/altera_timer.c b/drivers/timer/altera_timer.c
index 040dc65..ece246c 100644
--- a/drivers/timer/altera_timer.c
+++ b/drivers/timer/altera_timer.c
@@ -7,7 +7,6 @@
* Scott McNutt <smcnutt@psyent.com>
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <timer.h>
diff --git a/drivers/timer/andes_plmt_timer.c b/drivers/timer/andes_plmt_timer.c
index 42dd4b6..20baaf6 100644
--- a/drivers/timer/andes_plmt_timer.c
+++ b/drivers/timer/andes_plmt_timer.c
@@ -8,7 +8,6 @@
* associated with timer tick.
*/
-#include <common.h>
#include <dm.h>
#include <timer.h>
#include <asm/io.h>
diff --git a/drivers/timer/arc_timer.c b/drivers/timer/arc_timer.c
index 497f8a0..413bcc3 100644
--- a/drivers/timer/arc_timer.c
+++ b/drivers/timer/arc_timer.c
@@ -3,7 +3,6 @@
* Copyright (C) 2016 Synopsys, Inc. All rights reserved.
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <timer.h>
diff --git a/drivers/timer/arm_global_timer.c b/drivers/timer/arm_global_timer.c
index 2e50d9f..b805792 100644
--- a/drivers/timer/arm_global_timer.c
+++ b/drivers/timer/arm_global_timer.c
@@ -6,7 +6,7 @@
* ARM Cortext A9 global timer driver
*/
-#include <common.h>
+#include <config.h>
#include <dm.h>
#include <clk.h>
#include <timer.h>
diff --git a/drivers/timer/arm_twd_timer.c b/drivers/timer/arm_twd_timer.c
index 40ccd16..2b2f359 100644
--- a/drivers/timer/arm_twd_timer.c
+++ b/drivers/timer/arm_twd_timer.c
@@ -27,7 +27,6 @@
* Alex Zuepke <azu@sysgo.de>
*/
-#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include <timer.h>
diff --git a/drivers/timer/ast_timer.c b/drivers/timer/ast_timer.c
index 78adc96..6601cab 100644
--- a/drivers/timer/ast_timer.c
+++ b/drivers/timer/ast_timer.c
@@ -3,7 +3,6 @@
* Copyright 2016 Google Inc.
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <timer.h>
diff --git a/drivers/timer/atmel_pit_timer.c b/drivers/timer/atmel_pit_timer.c
index 5cf46f2..0a367a5 100644
--- a/drivers/timer/atmel_pit_timer.c
+++ b/drivers/timer/atmel_pit_timer.c
@@ -4,7 +4,6 @@
* Wenyou.Yang <wenyou.yang@microchip.com>
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <timer.h>
diff --git a/drivers/timer/atmel_tcb_timer.c b/drivers/timer/atmel_tcb_timer.c
index 8c17987..3a328b2 100644
--- a/drivers/timer/atmel_tcb_timer.c
+++ b/drivers/timer/atmel_tcb_timer.c
@@ -5,7 +5,6 @@
* Author: Clément Léger <clement.leger@bootlin.com>
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <timer.h>
diff --git a/drivers/timer/cadence-ttc.c b/drivers/timer/cadence-ttc.c
index 2eff450..3cffb1b 100644
--- a/drivers/timer/cadence-ttc.c
+++ b/drivers/timer/cadence-ttc.c
@@ -3,7 +3,6 @@
* Copyright (C) 2018 Xilinx, Inc. (Michal Simek)
*/
-#include <common.h>
#include <bootstage.h>
#include <dm.h>
#include <errno.h>
diff --git a/drivers/timer/dw-apb-timer.c b/drivers/timer/dw-apb-timer.c
index 0607f75..77ccb98 100644
--- a/drivers/timer/dw-apb-timer.c
+++ b/drivers/timer/dw-apb-timer.c
@@ -5,7 +5,6 @@
* Copyright (C) 2018 Marek Vasut <marex@denx.de>
*/
-#include <common.h>
#include <dm.h>
#include <clk.h>
#include <dt-structs.h>
diff --git a/drivers/timer/fttmr010_timer.c b/drivers/timer/fttmr010_timer.c
index b6289e6..c41bbfc 100644
--- a/drivers/timer/fttmr010_timer.c
+++ b/drivers/timer/fttmr010_timer.c
@@ -5,7 +5,6 @@
*
* 23/08/2022 Port to DM
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <timer.h>
diff --git a/drivers/timer/imx-gpt-timer.c b/drivers/timer/imx-gpt-timer.c
index 9c3b64a..07b9fdb 100644
--- a/drivers/timer/imx-gpt-timer.c
+++ b/drivers/timer/imx-gpt-timer.c
@@ -4,7 +4,7 @@
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
-#include <common.h>
+#include <config.h>
#include <clk.h>
#include <dm.h>
#include <fdtdec.h>
diff --git a/drivers/timer/mchp-pit64b-timer.c b/drivers/timer/mchp-pit64b-timer.c
index c9806d7..1a5b2e6 100644
--- a/drivers/timer/mchp-pit64b-timer.c
+++ b/drivers/timer/mchp-pit64b-timer.c
@@ -7,7 +7,6 @@
* Author: Claudiu Beznea <claudiu.beznea@microchip.com>
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <timer.h>
diff --git a/drivers/timer/mpc83xx_timer.c b/drivers/timer/mpc83xx_timer.c
index 7814cb6..9da7447 100644
--- a/drivers/timer/mpc83xx_timer.c
+++ b/drivers/timer/mpc83xx_timer.c
@@ -4,7 +4,7 @@
* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
*/
-#include <common.h>
+#include <config.h>
#include <clk.h>
#include <dm.h>
#include <irq_func.h>
diff --git a/drivers/timer/mtk_timer.c b/drivers/timer/mtk_timer.c
index 223e63f..8216c28 100644
--- a/drivers/timer/mtk_timer.c
+++ b/drivers/timer/mtk_timer.c
@@ -7,7 +7,6 @@
*/
#include <clk.h>
-#include <common.h>
#include <dm.h>
#include <timer.h>
#include <asm/io.h>
diff --git a/drivers/timer/nomadik-mtu-timer.c b/drivers/timer/nomadik-mtu-timer.c
index 4d24de1..9a05582 100644
--- a/drivers/timer/nomadik-mtu-timer.c
+++ b/drivers/timer/nomadik-mtu-timer.c
@@ -12,7 +12,6 @@
* Copyright (C) 2010 Linus Walleij for ST-Ericsson
*/
-#include <common.h>
#include <dm.h>
#include <timer.h>
#include <asm/io.h>
diff --git a/drivers/timer/npcm-timer.c b/drivers/timer/npcm-timer.c
index 4562a6f..9463fd2 100644
--- a/drivers/timer/npcm-timer.c
+++ b/drivers/timer/npcm-timer.c
@@ -3,7 +3,6 @@
* Copyright (c) 2022 Nuvoton Technology Corp.
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <timer.h>
diff --git a/drivers/timer/omap-timer.c b/drivers/timer/omap-timer.c
index 9b6d97d..fda6356 100644
--- a/drivers/timer/omap-timer.c
+++ b/drivers/timer/omap-timer.c
@@ -5,7 +5,6 @@
* Copyright (C) 2015, Texas Instruments, Incorporated
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <timer.h>
diff --git a/drivers/timer/orion-timer.c b/drivers/timer/orion-timer.c
index 9cab27f..821b681 100644
--- a/drivers/timer/orion-timer.c
+++ b/drivers/timer/orion-timer.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
#include <asm/io.h>
-#include <common.h>
+#include <config.h>
#include <div64.h>
#include <dm/device.h>
#include <dm/fdtaddr.h>
diff --git a/drivers/timer/ostm_timer.c b/drivers/timer/ostm_timer.c
index 3bf0d46..314f956 100644
--- a/drivers/timer/ostm_timer.c
+++ b/drivers/timer/ostm_timer.c
@@ -5,7 +5,6 @@
* Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
*/
-#include <common.h>
#include <clock_legacy.h>
#include <malloc.h>
#include <asm/global_data.h>
diff --git a/drivers/timer/riscv_aclint_timer.c b/drivers/timer/riscv_aclint_timer.c
index 73fb879..35da1ea 100644
--- a/drivers/timer/riscv_aclint_timer.c
+++ b/drivers/timer/riscv_aclint_timer.c
@@ -4,7 +4,7 @@
* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
*/
-#include <common.h>
+#include <config.h>
#include <clk.h>
#include <div64.h>
#include <dm.h>
diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
index 169c03d..1f4980c 100644
--- a/drivers/timer/riscv_timer.c
+++ b/drivers/timer/riscv_timer.c
@@ -10,7 +10,7 @@
* This driver provides generic timer support for S-mode U-Boot.
*/
-#include <common.h>
+#include <config.h>
#include <div64.h>
#include <dm.h>
#include <errno.h>
diff --git a/drivers/timer/rockchip_timer.c b/drivers/timer/rockchip_timer.c
index e66c49a..96c010f 100644
--- a/drivers/timer/rockchip_timer.c
+++ b/drivers/timer/rockchip_timer.c
@@ -3,7 +3,6 @@
* Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH
*/
-#include <common.h>
#include <bootstage.h>
#include <dm.h>
#include <init.h>
diff --git a/drivers/timer/sandbox_timer.c b/drivers/timer/sandbox_timer.c
index 1da7e0c..e8b54a0 100644
--- a/drivers/timer/sandbox_timer.c
+++ b/drivers/timer/sandbox_timer.c
@@ -3,7 +3,6 @@
* Copyright (C) 2015 Thomas Chou <thomas@wytron.com.tw>
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <timer.h>
diff --git a/drivers/timer/sp804_timer.c b/drivers/timer/sp804_timer.c
index 8fd4afb..a254e29 100644
--- a/drivers/timer/sp804_timer.c
+++ b/drivers/timer/sp804_timer.c
@@ -4,7 +4,6 @@
* Copyright (C) 2022 Arm Ltd.
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <init.h>
diff --git a/drivers/timer/starfive-timer.c b/drivers/timer/starfive-timer.c
index 6ac7d7f..6b79c88 100644
--- a/drivers/timer/starfive-timer.c
+++ b/drivers/timer/starfive-timer.c
@@ -4,7 +4,6 @@
* Author: Kuan Lim Lee <kuanlim.lee@starfivetech.com>
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <time.h>
diff --git a/drivers/timer/stm32_timer.c b/drivers/timer/stm32_timer.c
index 1213a14..1dc21c5 100644
--- a/drivers/timer/stm32_timer.c
+++ b/drivers/timer/stm32_timer.c
@@ -6,7 +6,7 @@
#define LOG_CATEGORY UCLASS_TIMER
-#include <common.h>
+#include <config.h>
#include <clk.h>
#include <dm.h>
#include <fdtdec.h>
diff --git a/drivers/timer/tegra-timer.c b/drivers/timer/tegra-timer.c
index a867c64..3545424 100644
--- a/drivers/timer/tegra-timer.c
+++ b/drivers/timer/tegra-timer.c
@@ -3,7 +3,6 @@
* Copyright (C) 2022 Svyatoslav Ryhel <clamor95@gmail.com>
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <timer.h>
diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c
index 60ff655..8305f06 100644
--- a/drivers/timer/timer-uclass.c
+++ b/drivers/timer/timer-uclass.c
@@ -5,7 +5,6 @@
#define LOG_CATEGORY UCLASS_TIMER
-#include <common.h>
#include <clk.h>
#include <cpu.h>
#include <dm.h>
diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index f86a0b8..80c084f 100644
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -6,7 +6,6 @@
* arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
*/
-#include <common.h>
#include <bootstage.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/timer/xilinx-timer.c b/drivers/timer/xilinx-timer.c
index 172fd9f..54148aa 100644
--- a/drivers/timer/xilinx-timer.c
+++ b/drivers/timer/xilinx-timer.c
@@ -7,7 +7,6 @@
* Michal SIMEK <monstr@monstr.eu>
*/
-#include <common.h>
#include <dm.h>
#include <timer.h>
#include <regmap.h>
diff --git a/drivers/tpm/cr50_i2c.c b/drivers/tpm/cr50_i2c.c
index acf4c78..08ec179 100644
--- a/drivers/tpm/cr50_i2c.c
+++ b/drivers/tpm/cr50_i2c.c
@@ -7,12 +7,12 @@
#define LOG_CATEGORY UCLASS_TPM
-#include <common.h>
#include <dm.h>
#include <i2c.h>
#include <irq.h>
#include <log.h>
#include <spl.h>
+#include <time.h>
#include <tpm-common.h>
#include <tpm-v2.h>
#include <acpi/acpigen.h>
diff --git a/drivers/tpm/sandbox_common.c b/drivers/tpm/sandbox_common.c
index 7e0b250..596e015 100644
--- a/drivers/tpm/sandbox_common.c
+++ b/drivers/tpm/sandbox_common.c
@@ -7,7 +7,6 @@
#define LOG_CATEGORY UCLASS_TPM
-#include <common.h>
#include <tpm-v1.h>
#include <tpm-v2.h>
#include <asm/unaligned.h>
diff --git a/drivers/tpm/tpm-uclass.c b/drivers/tpm/tpm-uclass.c
index b2286f7..0fade2d 100644
--- a/drivers/tpm/tpm-uclass.c
+++ b/drivers/tpm/tpm-uclass.c
@@ -6,9 +6,9 @@
#define LOG_CATEGORY UCLASS_TPM
-#include <common.h>
#include <dm.h>
#include <log.h>
+#include <time.h>
#include <tpm_api.h>
#include <tpm-v1.h>
#include <tpm-v2.h>
diff --git a/drivers/tpm/tpm2_ftpm_tee.c b/drivers/tpm/tpm2_ftpm_tee.c
index c61ff2c..f2ced50 100644
--- a/drivers/tpm/tpm2_ftpm_tee.c
+++ b/drivers/tpm/tpm2_ftpm_tee.c
@@ -13,7 +13,6 @@
* https://github.com/microsoft/ms-tpm-20-ref/tree/master/Samples/ARM32-FirmwareTPM/optee_ta/fTPM
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <tpm-v2.h>
diff --git a/drivers/tpm/tpm2_tis_core.c b/drivers/tpm/tpm2_tis_core.c
index 81b9210..680a640 100644
--- a/drivers/tpm/tpm2_tis_core.c
+++ b/drivers/tpm/tpm2_tis_core.c
@@ -5,8 +5,8 @@
* Based on the Linux TIS core interface and U-Boot original SPI TPM driver
*/
-#include <common.h>
#include <dm.h>
+#include <time.h>
#include <tpm-v2.h>
#include <linux/delay.h>
#include <linux/unaligned/be_byteshift.h>
diff --git a/drivers/tpm/tpm2_tis_i2c.c b/drivers/tpm/tpm2_tis_i2c.c
index 99d1cf21..93efccc 100644
--- a/drivers/tpm/tpm2_tis_i2c.c
+++ b/drivers/tpm/tpm2_tis_i2c.c
@@ -3,7 +3,6 @@
* Copyright 2022 IBM Corp.
*/
-#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include <i2c.h>
diff --git a/drivers/tpm/tpm2_tis_mmio.c b/drivers/tpm/tpm2_tis_mmio.c
index a646ce4..dee5503 100644
--- a/drivers/tpm/tpm2_tis_mmio.c
+++ b/drivers/tpm/tpm2_tis_mmio.c
@@ -5,7 +5,6 @@
* Specifications at www.trustedcomputinggroup.org
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <tpm-v2.h>
diff --git a/drivers/tpm/tpm2_tis_sandbox.c b/drivers/tpm/tpm2_tis_sandbox.c
index d15a28d..50e308e 100644
--- a/drivers/tpm/tpm2_tis_sandbox.c
+++ b/drivers/tpm/tpm2_tis_sandbox.c
@@ -4,7 +4,6 @@
* Author: Miquel Raynal <miquel.raynal@bootlin.com>
*/
-#include <common.h>
#include <dm.h>
#include <tpm-v2.h>
#include <asm/state.h>
diff --git a/drivers/tpm/tpm2_tis_spi.c b/drivers/tpm/tpm2_tis_spi.c
index de9cf8f..28079b5 100644
--- a/drivers/tpm/tpm2_tis_spi.c
+++ b/drivers/tpm/tpm2_tis_spi.c
@@ -13,11 +13,11 @@
* It is based on the U-Boot driver tpm_tis_infineon_i2c.c.
*/
-#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include <log.h>
#include <spi.h>
+#include <time.h>
#include <tpm-v2.h>
#include <linux/bitops.h>
#include <linux/delay.h>
diff --git a/drivers/tpm/tpm_atmel_twi.c b/drivers/tpm/tpm_atmel_twi.c
index fd2a45d..05dd665 100644
--- a/drivers/tpm/tpm_atmel_twi.c
+++ b/drivers/tpm/tpm_atmel_twi.c
@@ -5,11 +5,11 @@
* Written by Dirk Eibach <dirk.eibach@gdsys.cc>
*/
-#include <common.h>
#include <display_options.h>
#include <dm.h>
#include <tpm-v1.h>
#include <i2c.h>
+#include <time.h>
#include <asm/unaligned.h>
#include <linux/delay.h>
diff --git a/drivers/tpm/tpm_tis_infineon.c b/drivers/tpm/tpm_tis_infineon.c
index 16f4af0..e2f6238 100644
--- a/drivers/tpm/tpm_tis_infineon.c
+++ b/drivers/tpm/tpm_tis_infineon.c
@@ -19,11 +19,11 @@
* Version: 2.1.1
*/
-#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include <i2c.h>
#include <log.h>
+#include <time.h>
#include <tpm-v1.h>
#include <linux/delay.h>
#include <linux/errno.h>
diff --git a/drivers/tpm/tpm_tis_lpc.c b/drivers/tpm/tpm_tis_lpc.c
index 13a133d..dec7acb 100644
--- a/drivers/tpm/tpm_tis_lpc.c
+++ b/drivers/tpm/tpm_tis_lpc.c
@@ -12,7 +12,6 @@
* slb9635), so this driver provides access to locality 0 only.
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <mapmem.h>
diff --git a/drivers/tpm/tpm_tis_sandbox.c b/drivers/tpm/tpm_tis_sandbox.c
index 7350e1c..2bc7dc8 100644
--- a/drivers/tpm/tpm_tis_sandbox.c
+++ b/drivers/tpm/tpm_tis_sandbox.c
@@ -3,7 +3,6 @@
* Copyright (c) 2013 Google, Inc
*/
-#include <common.h>
#include <display_options.h>
#include <dm.h>
#include <tpm-v1.h>
diff --git a/drivers/tpm/tpm_tis_st33zp24_i2c.c b/drivers/tpm/tpm_tis_st33zp24_i2c.c
index e0eeabb..1a265b2 100644
--- a/drivers/tpm/tpm_tis_st33zp24_i2c.c
+++ b/drivers/tpm/tpm_tis_st33zp24_i2c.c
@@ -12,7 +12,6 @@
* STMicroelectronics Protocol Stack Specification version 1.2.0.
*/
-#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include <i2c.h>
diff --git a/drivers/tpm/tpm_tis_st33zp24_spi.c b/drivers/tpm/tpm_tis_st33zp24_spi.c
index f0de8a6..2cf6903 100644
--- a/drivers/tpm/tpm_tis_st33zp24_spi.c
+++ b/drivers/tpm/tpm_tis_st33zp24_spi.c
@@ -12,7 +12,6 @@
* STMicroelectronics Protocol Stack Specification version 1.2.0.
*/
-#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include <log.h>
diff --git a/drivers/ufs/cdns-platform.c b/drivers/ufs/cdns-platform.c
index d1f3469..510a6a6 100644
--- a/drivers/ufs/cdns-platform.c
+++ b/drivers/ufs/cdns-platform.c
@@ -6,7 +6,6 @@
*/
#include <clk.h>
-#include <common.h>
#include <dm.h>
#include <ufs.h>
#include <asm/io.h>
diff --git a/drivers/ufs/ti-j721e-ufs.c b/drivers/ufs/ti-j721e-ufs.c
index 1860e0d..c5c0861 100644
--- a/drivers/ufs/ti-j721e-ufs.c
+++ b/drivers/ufs/ti-j721e-ufs.c
@@ -5,7 +5,6 @@
#include <asm/io.h>
#include <clk.h>
-#include <common.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
diff --git a/drivers/ufs/ufs-pci.c b/drivers/ufs/ufs-pci.c
index ad41358..871f3f5 100644
--- a/drivers/ufs/ufs-pci.c
+++ b/drivers/ufs/ufs-pci.c
@@ -4,7 +4,6 @@
* Author: Bin Meng <bmeng@tinylab.org>
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <pci.h>
diff --git a/drivers/ufs/ufs-uclass.c b/drivers/ufs/ufs-uclass.c
index 92fcdf4..334bfcf 100644
--- a/drivers/ufs/ufs-uclass.c
+++ b/drivers/ufs/ufs-uclass.c
@@ -7,7 +7,6 @@
#define LOG_CATEGORY UCLASS_UFS
-#include <common.h>
#include "ufs.h"
#include <dm.h>
diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c
index e4400f3..be64bf9 100644
--- a/drivers/ufs/ufs.c
+++ b/drivers/ufs/ufs.c
@@ -10,7 +10,6 @@
#include <bouncebuf.h>
#include <charset.h>
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <dm/device_compat.h>
diff --git a/drivers/ufs/ufs.h b/drivers/ufs/ufs.h
index 816a5ce..43042c2 100644
--- a/drivers/ufs/ufs.h
+++ b/drivers/ufs/ufs.h
@@ -2,6 +2,7 @@
#ifndef __UFS_H
#define __UFS_H
+#include <linux/types.h>
#include "unipro.h"
struct udevice;
diff --git a/drivers/usb/cdns3/cdns3-ti.c b/drivers/usb/cdns3/cdns3-ti.c
index 2e44aad..ac07226 100644
--- a/drivers/usb/cdns3/cdns3-ti.c
+++ b/drivers/usb/cdns3/cdns3-ti.c
@@ -5,7 +5,6 @@
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <dm/device_compat.h>
diff --git a/drivers/usb/cdns3/core.c b/drivers/usb/cdns3/core.c
index 12a741c..b4e9316 100644
--- a/drivers/usb/cdns3/core.c
+++ b/drivers/usb/cdns3/core.c
@@ -11,7 +11,6 @@
* Roger Quadros <rogerq@ti.com>
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <dm/device-internal.h>
diff --git a/drivers/usb/common/common.c b/drivers/usb/common/common.c
index 7137a56..13e9a61 100644
--- a/drivers/usb/common/common.c
+++ b/drivers/usb/common/common.c
@@ -6,7 +6,6 @@
* Texas Instruments Incorporated, <www.ti.com>
*/
-#include <common.h>
#include <dm.h>
#include <asm/global_data.h>
#include <linux/printk.h>
diff --git a/drivers/usb/common/fsl-dt-fixup.c b/drivers/usb/common/fsl-dt-fixup.c
index 00b8cd3..6a68bd7 100644
--- a/drivers/usb/common/fsl-dt-fixup.c
+++ b/drivers/usb/common/fsl-dt-fixup.c
@@ -7,7 +7,6 @@
* Author: Tor Krill tor@excito.com
*/
-#include <common.h>
#include <log.h>
#include <usb.h>
#include <asm/io.h>
diff --git a/drivers/usb/common/fsl-errata.c b/drivers/usb/common/fsl-errata.c
index 9eb1d23..89ae73f 100644
--- a/drivers/usb/common/fsl-errata.c
+++ b/drivers/usb/common/fsl-errata.c
@@ -5,7 +5,6 @@
* Copyright 2013 Freescale Semiconductor, Inc.
*/
-#include <common.h>
#include <hwconfig.h>
#include <fsl_errata.h>
#include<fsl_usb.h>
diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index c0c8c16..0100723 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -37,6 +37,20 @@
Select this for Xilinx ZynqMP and similar Platforms.
This wrapper supports Host and Peripheral operation modes.
+config SPL_USB_DWC3_AM62
+ bool "TI AM62 USB wrapper"
+ depends on SPL_DM_USB && SPL_USB_DWC3_GENERIC && SPL_SYSCON
+ help
+ Select this for TI AM62 Platforms.
+ This wrapper supports Host and Peripheral operation modes.
+
+config USB_DWC3_AM62
+ bool "TI AM62 USB wrapper"
+ depends on DM_USB && USB_DWC3_GENERIC && SYSCON
+ help
+ Select this for TI AM62 Platforms.
+ This wrapper supports Host and Peripheral operation modes.
+
config USB_DWC3_MESON_G12A
bool "Amlogic Meson G12A USB wrapper"
depends on DM_USB && USB_DWC3 && ARCH_MESON
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
index 97b4f71..a46b682 100644
--- a/drivers/usb/dwc3/Makefile
+++ b/drivers/usb/dwc3/Makefile
@@ -6,6 +6,7 @@
obj-$(CONFIG_USB_DWC3_GADGET) += gadget.o ep0.o
+obj-$(CONFIG_$(SPL_)USB_DWC3_AM62) += dwc3-am62.o
obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o
obj-$(CONFIG_USB_DWC3_MESON_G12A) += dwc3-meson-g12a.o
obj-$(CONFIG_USB_DWC3_MESON_GXL) += dwc3-meson-gxl.o
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 96e850b..c443d56 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -13,7 +13,6 @@
* commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA
*/
-#include <common.h>
#include <clk.h>
#include <cpu_func.h>
#include <malloc.h>
diff --git a/drivers/usb/dwc3/dwc3-am62.c b/drivers/usb/dwc3/dwc3-am62.c
new file mode 100644
index 0000000..9951960
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-am62.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * TI AM62 specific glue layer for DWC3
+ */
+
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+
+#include "dwc3-generic.h"
+
+#define USBSS_MODE_CONTROL 0x1c
+#define USBSS_PHY_CONFIG 0x8
+#define USBSS_PHY_VBUS_SEL_MASK GENMASK(2, 1)
+#define USBSS_PHY_VBUS_SEL_SHIFT 1
+#define USBSS_MODE_VALID BIT(0)
+#define PHY_PLL_REFCLK_MASK GENMASK(3, 0)
+static const int dwc3_ti_am62_rate_table[] = { /* in KHZ */
+ 9600,
+ 10000,
+ 12000,
+ 19200,
+ 20000,
+ 24000,
+ 25000,
+ 26000,
+ 38400,
+ 40000,
+ 58000,
+ 50000,
+ 52000,
+};
+
+static void dwc3_ti_am62_glue_configure(struct udevice *dev, int index,
+ enum usb_dr_mode mode)
+{
+ struct clk usb2_refclk;
+ int rate_code, i, ret;
+ unsigned long rate;
+ u32 reg;
+ void *usbss;
+ bool vbus_divider;
+ struct regmap *syscon;
+ struct ofnode_phandle_args args;
+
+ usbss = dev_remap_addr_index(dev, 0);
+ if (IS_ERR(usbss)) {
+ dev_err(dev, "can't map IOMEM resource\n");
+ return;
+ }
+
+ ret = clk_get_by_name(dev, "ref", &usb2_refclk);
+ if (ret) {
+ dev_err(dev, "can't get usb2_refclk\n");
+ return;
+ }
+
+ /* Calculate the rate code */
+ rate = clk_get_rate(&usb2_refclk);
+ rate /= 1000; /* To KHz */
+ for (i = 0; i < ARRAY_SIZE(dwc3_ti_am62_rate_table); i++) {
+ if (dwc3_ti_am62_rate_table[i] == rate)
+ break;
+ }
+
+ if (i == ARRAY_SIZE(dwc3_ti_am62_rate_table)) {
+ dev_err(dev, "unsupported usb2_refclk rate: %lu KHz\n", rate);
+ return;
+ }
+
+ rate_code = i;
+
+ /* Read the syscon property */
+ syscon = syscon_regmap_lookup_by_phandle(dev, "ti,syscon-phy-pll-refclk");
+ if (IS_ERR(syscon)) {
+ dev_err(dev, "unable to get ti,syscon-phy-pll-refclk regmap\n");
+ return;
+ }
+
+ ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "ti,syscon-phy-pll-refclk", NULL, 1,
+ 0, &args);
+ if (ret)
+ return;
+
+ /* Program PHY PLL refclk by reading syscon property */
+ ret = regmap_update_bits(syscon, args.args[0], PHY_PLL_REFCLK_MASK, rate_code);
+ if (ret) {
+ dev_err(dev, "failed to set phy pll reference clock rate\n");
+ return;
+ }
+
+ /* VBUS divider select */
+ reg = readl(usbss + USBSS_PHY_CONFIG);
+ vbus_divider = dev_read_bool(dev, "ti,vbus-divider");
+ if (vbus_divider)
+ reg |= 1 << USBSS_PHY_VBUS_SEL_SHIFT;
+
+ writel(reg, usbss + USBSS_PHY_CONFIG);
+
+ /* Set mode valid */
+ reg = readl(usbss + USBSS_MODE_CONTROL);
+ reg |= USBSS_MODE_VALID;
+ writel(reg, usbss + USBSS_MODE_CONTROL);
+}
+
+struct dwc3_glue_ops ti_am62_ops = {
+ .glue_configure = dwc3_ti_am62_glue_configure,
+};
+
+static const struct udevice_id dwc3_am62_match[] = {
+ { .compatible = "ti,am62-usb", .data = (ulong)&ti_am62_ops },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(dwc3_am62_wrapper) = {
+ .name = "dwc3-am62",
+ .id = UCLASS_SIMPLE_BUS,
+ .of_match = dwc3_am62_match,
+ .bind = dwc3_glue_bind,
+ .probe = dwc3_glue_probe,
+ .remove = dwc3_glue_remove,
+ .plat_auto = sizeof(struct dwc3_glue_data),
+};
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 7a00529..8db678e 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -7,7 +7,6 @@
* Based on dwc3-omap.c.
*/
-#include <common.h>
#include <cpu_func.h>
#include <log.h>
#include <dm.h>
diff --git a/drivers/usb/dwc3/dwc3-layerscape.c b/drivers/usb/dwc3/dwc3-layerscape.c
index c32df23..ff83bf7 100644
--- a/drivers/usb/dwc3/dwc3-layerscape.c
+++ b/drivers/usb/dwc3/dwc3-layerscape.c
@@ -7,7 +7,6 @@
* Based on dwc3-generic.c.
*/
-#include <common.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <dm/device-internal.h>
diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c
index 1a3e935..21e4f63 100644
--- a/drivers/usb/dwc3/dwc3-meson-g12a.c
+++ b/drivers/usb/dwc3/dwc3-meson-g12a.c
@@ -6,7 +6,6 @@
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
-#include <common.h>
#include <log.h>
#include <dm.h>
#include <dm/device-internal.h>
diff --git a/drivers/usb/dwc3/dwc3-meson-gxl.c b/drivers/usb/dwc3/dwc3-meson-gxl.c
index 2ce9157..3e693c5 100644
--- a/drivers/usb/dwc3/dwc3-meson-gxl.c
+++ b/drivers/usb/dwc3/dwc3-meson-gxl.c
@@ -7,7 +7,6 @@
*/
#define DEBUG
-#include <common.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-omap.c
index 53c4d48..4b219c3 100644
--- a/drivers/usb/dwc3/dwc3-omap.c
+++ b/drivers/usb/dwc3/dwc3-omap.c
@@ -13,7 +13,6 @@
* commit 7ee2566ff5 : usb: dwc3: dwc3-omap: get rid of ->prepare()/->complete()
*/
-#include <common.h>
#include <malloc.h>
#include <asm/io.h>
#include <dm.h>
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index 1133cf8..117d38a 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -12,7 +12,6 @@
*
* commit c00552ebaf : Merge 3.18-rc7 into usb-next
*/
-#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <dm/device_compat.h>
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 406d36c..4de007c 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -13,7 +13,6 @@
* commit 8e74475b0e : usb: dwc3: gadget: use udc-core's reset notifier
*/
-#include <common.h>
#include <cpu_func.h>
#include <log.h>
#include <malloc.h>
diff --git a/drivers/usb/dwc3/samsung_usb_phy.c b/drivers/usb/dwc3/samsung_usb_phy.c
index abbd413..0a77130 100644
--- a/drivers/usb/dwc3/samsung_usb_phy.c
+++ b/drivers/usb/dwc3/samsung_usb_phy.c
@@ -7,7 +7,7 @@
* Author: Joonyoung Shim <jy0922.shim@samsung.com>
*/
-#include <common.h>
+#include <asm/io.h>
#include <asm/arch/power.h>
#include <asm/arch/xhci-exynos.h>
#include <linux/delay.h>
diff --git a/drivers/usb/dwc3/ti_usb_phy.c b/drivers/usb/dwc3/ti_usb_phy.c
index 8ae1308..f0ecdea 100644
--- a/drivers/usb/dwc3/ti_usb_phy.c
+++ b/drivers/usb/dwc3/ti_usb_phy.c
@@ -16,7 +16,6 @@
* and remove" for phy-omap-usb2.c
*/
-#include <common.h>
#include <malloc.h>
#include <ti-usb-phy-uboot.h>
#include <dm/device_compat.h>
diff --git a/drivers/usb/emul/sandbox_flash.c b/drivers/usb/emul/sandbox_flash.c
index 7c5c1ab..24420e3 100644
--- a/drivers/usb/emul/sandbox_flash.c
+++ b/drivers/usb/emul/sandbox_flash.c
@@ -6,7 +6,6 @@
#define LOG_CATEGORY UCLASS_USB
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <malloc.h>
diff --git a/drivers/usb/emul/sandbox_hub.c b/drivers/usb/emul/sandbox_hub.c
index 084cc16..3b3e59f 100644
--- a/drivers/usb/emul/sandbox_hub.c
+++ b/drivers/usb/emul/sandbox_hub.c
@@ -4,7 +4,6 @@
* Written by Simon Glass <sjg@chromium.org>
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <usb.h>
diff --git a/drivers/usb/emul/sandbox_keyb.c b/drivers/usb/emul/sandbox_keyb.c
index 5ec1e98..db76988 100644
--- a/drivers/usb/emul/sandbox_keyb.c
+++ b/drivers/usb/emul/sandbox_keyb.c
@@ -4,7 +4,6 @@
* Written by Simon Glass <sjg@chromium.org>
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <os.h>
diff --git a/drivers/usb/emul/usb-emul-uclass.c b/drivers/usb/emul/usb-emul-uclass.c
index b31dc95..cdc18d6 100644
--- a/drivers/usb/emul/usb-emul-uclass.c
+++ b/drivers/usb/emul/usb-emul-uclass.c
@@ -6,7 +6,6 @@
#define LOG_CATEGORY UCLASS_USB_EMUL
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <usb.h>
diff --git a/drivers/usb/eth/asix.c b/drivers/usb/eth/asix.c
index 26dd312..c5a01ec 100644
--- a/drivers/usb/eth/asix.c
+++ b/drivers/usb/eth/asix.c
@@ -5,7 +5,6 @@
* Patched for AX88772B by Antmicro Ltd <www.antmicro.com>
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <net.h>
diff --git a/drivers/usb/eth/asix88179.c b/drivers/usb/eth/asix88179.c
index 2e737e6..7bfd285 100644
--- a/drivers/usb/eth/asix88179.c
+++ b/drivers/usb/eth/asix88179.c
@@ -5,7 +5,6 @@
* from the Linux AX88179_178a driver
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <usb.h>
diff --git a/drivers/usb/eth/mcs7830.c b/drivers/usb/eth/mcs7830.c
index d94204f..199fb7a 100644
--- a/drivers/usb/eth/mcs7830.c
+++ b/drivers/usb/eth/mcs7830.c
@@ -9,7 +9,6 @@
* MOSCHIP MCS7830 based (7730/7830/7832) USB 2.0 Ethernet Devices
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/usb/eth/r8152.c b/drivers/usb/eth/r8152.c
index 3c866f4..e3f20e0 100644
--- a/drivers/usb/eth/r8152.c
+++ b/drivers/usb/eth/r8152.c
@@ -4,7 +4,6 @@
*
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/usb/eth/r8152_fw.c b/drivers/usb/eth/r8152_fw.c
index a41abed..3159f30 100644
--- a/drivers/usb/eth/r8152_fw.c
+++ b/drivers/usb/eth/r8152_fw.c
@@ -3,7 +3,6 @@
* Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved.
*
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <linux/bitops.h>
diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c
index de6586e..b4fcb2c 100644
--- a/drivers/usb/eth/smsc95xx.c
+++ b/drivers/usb/eth/smsc95xx.c
@@ -6,7 +6,6 @@
* Copyright (C) 2007-2008 SMSC (Steve Glendinning)
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/usb/eth/usb_ether.c b/drivers/usb/eth/usb_ether.c
index 2e9af54..8bba3e0 100644
--- a/drivers/usb/eth/usb_ether.c
+++ b/drivers/usb/eth/usb_ether.c
@@ -3,7 +3,6 @@
* Copyright (c) 2011 The Chromium OS Authors.
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
index e573a03..86b2cbf 100644
--- a/drivers/usb/gadget/at91_udc.c
+++ b/drivers/usb/gadget/at91_udc.c
@@ -13,7 +13,6 @@
#undef VERBOSE_DEBUG
#undef PACKET_TRACE
-#include <common.h>
#include <dm/devres.h>
#include <linux/bug.h>
#include <linux/err.h>
diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
index 4c42074..f99553d 100644
--- a/drivers/usb/gadget/atmel_usba_udc.c
+++ b/drivers/usb/gadget/atmel_usba_udc.c
@@ -7,7 +7,6 @@
* Bo Shen <voice.shen@atmel.com>
*/
-#include <common.h>
#include <linux/bitops.h>
#include <linux/errno.h>
#include <asm/gpio.h>
diff --git a/drivers/usb/gadget/bcm_udc_otg_phy.c b/drivers/usb/gadget/bcm_udc_otg_phy.c
index c89cd57..98751910 100644
--- a/drivers/usb/gadget/bcm_udc_otg_phy.c
+++ b/drivers/usb/gadget/bcm_udc_otg_phy.c
@@ -4,7 +4,6 @@
*/
#include <config.h>
-#include <common.h>
#include <asm/io.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c
index 750d471..bbe03cf 100644
--- a/drivers/usb/gadget/ci_udc.c
+++ b/drivers/usb/gadget/ci_udc.c
@@ -7,7 +7,6 @@
* Murray.Jensen@cmst.csiro.au, 27-Jan-01.
*/
-#include <common.h>
#include <command.h>
#include <config.h>
#include <cpu_func.h>
diff --git a/drivers/usb/gadget/config.c b/drivers/usb/gadget/config.c
index e967826..1363ef9 100644
--- a/drivers/usb/gadget/config.c
+++ b/drivers/usb/gadget/config.c
@@ -8,7 +8,6 @@
* Remy Bohmer <linux@bohmer.net>
*/
-#include <common.h>
#include <asm/unaligned.h>
#include <linux/errno.h>
#include <linux/list.h>
diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c
index 27082f5..6bd395a 100644
--- a/drivers/usb/gadget/dwc2_udc_otg.c
+++ b/drivers/usb/gadget/dwc2_udc_otg.c
@@ -17,7 +17,6 @@
* Lukasz Majewski <l.majewski@samsumg.com>
*/
#undef DEBUG
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <generic-phy.h>
diff --git a/drivers/usb/gadget/dwc2_udc_otg_phy.c b/drivers/usb/gadget/dwc2_udc_otg_phy.c
index 7f8e956..c7eea7b 100644
--- a/drivers/usb/gadget/dwc2_udc_otg_phy.c
+++ b/drivers/usb/gadget/dwc2_udc_otg_phy.c
@@ -17,7 +17,6 @@
* Lukasz Majewski <l.majewski@samsumg.com>
*/
-#include <common.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/list.h>
diff --git a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
index 1c34b75..16b2a03 100644
--- a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
+++ b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
@@ -17,7 +17,6 @@
* Lukasz Majewski <l.majewski@samsumg.com>
*/
-#include <common.h>
#include <cpu_func.h>
#include <log.h>
#include <linux/bug.h>
diff --git a/drivers/usb/gadget/ep0.c b/drivers/usb/gadget/ep0.c
index c256cc3..9d08640 100644
--- a/drivers/usb/gadget/ep0.c
+++ b/drivers/usb/gadget/ep0.c
@@ -36,7 +36,6 @@
* XXX
*/
-#include <common.h>
#include <serial.h>
#include <usbdevice.h>
diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c
index bb0d297..0a70035 100644
--- a/drivers/usb/gadget/epautoconf.c
+++ b/drivers/usb/gadget/epautoconf.c
@@ -8,7 +8,6 @@
* Remy Bohmer <linux@bohmer.net>
*/
-#include <common.h>
#include <linux/usb/ch9.h>
#include <linux/errno.h>
#include <linux/usb/gadget.h>
diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c
index 36618f0..b8b29d3 100644
--- a/drivers/usb/gadget/ether.c
+++ b/drivers/usb/gadget/ether.c
@@ -7,7 +7,6 @@
* Copyright (C) 2008 Nokia Corporation
*/
-#include <common.h>
#include <console.h>
#include <env.h>
#include <log.h>
diff --git a/drivers/usb/gadget/f_acm.c b/drivers/usb/gadget/f_acm.c
index ba21612..f18c6a0 100644
--- a/drivers/usb/gadget/f_acm.c
+++ b/drivers/usb/gadget/f_acm.c
@@ -10,7 +10,6 @@
*/
#include <circbuf.h>
-#include <common.h>
#include <console.h>
#include <errno.h>
#include <g_dnl.h>
diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c
index 44877df..ca8b36e 100644
--- a/drivers/usb/gadget/f_dfu.c
+++ b/drivers/usb/gadget/f_dfu.c
@@ -16,7 +16,6 @@
#include <env.h>
#include <errno.h>
-#include <common.h>
#include <log.h>
#include <malloc.h>
diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
index 09e740c..8df0e3f 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -11,7 +11,6 @@
*/
#include <command.h>
#include <config.h>
-#include <common.h>
#include <env.h>
#include <errno.h>
#include <fastboot.h>
diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c
index ef90c7e..89a96db 100644
--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -244,7 +244,6 @@
#include <hexdump.h>
#include <log.h>
#include <malloc.h>
-#include <common.h>
#include <console.h>
#include <g_dnl.h>
#include <dm/devres.h>
diff --git a/drivers/usb/gadget/f_rockusb.c b/drivers/usb/gadget/f_rockusb.c
index 98a7ffa..d679cda 100644
--- a/drivers/usb/gadget/f_rockusb.c
+++ b/drivers/usb/gadget/f_rockusb.c
@@ -6,7 +6,6 @@
*/
#include <command.h>
#include <config.h>
-#include <common.h>
#include <env.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c
index ca2760c..8949691 100644
--- a/drivers/usb/gadget/f_sdp.c
+++ b/drivers/usb/gadget/f_sdp.c
@@ -17,7 +17,6 @@
*/
#include <errno.h>
-#include <common.h>
#include <console.h>
#include <env.h>
#include <log.h>
diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c
index 0e7529d..5437211 100644
--- a/drivers/usb/gadget/f_thor.c
+++ b/drivers/usb/gadget/f_thor.c
@@ -15,7 +15,6 @@
*/
#include <command.h>
-#include <common.h>
#include <console.h>
#include <dm.h>
#include <errno.h>
diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c
index afb7b74..b5b5f5d 100644
--- a/drivers/usb/gadget/g_dnl.c
+++ b/drivers/usb/gadget/g_dnl.c
@@ -6,7 +6,6 @@
* Lukasz Majewski <l.majewski@samsung.com>
*/
-#include <common.h>
#include <log.h>
#include <malloc.h>
diff --git a/drivers/usb/gadget/max3420_udc.c b/drivers/usb/gadget/max3420_udc.c
index fa655c9..5a227c0 100644
--- a/drivers/usb/gadget/max3420_udc.c
+++ b/drivers/usb/gadget/max3420_udc.c
@@ -1,6 +1,5 @@
// SPDX-License-Identifier: GPL-2.0+
-#include <common.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <asm/gpio.h>
diff --git a/drivers/usb/gadget/rndis.c b/drivers/usb/gadget/rndis.c
index e7276cc..5e6e5a0 100644
--- a/drivers/usb/gadget/rndis.c
+++ b/drivers/usb/gadget/rndis.c
@@ -18,7 +18,6 @@
* updates to merge with Linux 2.6, better match RNDIS spec
*/
-#include <common.h>
#include <log.h>
#include <net.h>
#include <malloc.h>
diff --git a/drivers/usb/gadget/udc/udc-core.c b/drivers/usb/gadget/udc/udc-core.c
index ba658d9..6bb419a 100644
--- a/drivers/usb/gadget/udc/udc-core.c
+++ b/drivers/usb/gadget/udc/udc-core.c
@@ -19,7 +19,6 @@
#include <malloc.h>
#include <asm/cache.h>
#include <linux/dma-mapping.h>
-#include <common.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <linux/usb/ch9.h>
diff --git a/drivers/usb/gadget/udc/udc-uclass.c b/drivers/usb/gadget/udc/udc-uclass.c
index 30ee1ca..5dc23a5 100644
--- a/drivers/usb/gadget/udc/udc-uclass.c
+++ b/drivers/usb/gadget/udc/udc-uclass.c
@@ -6,7 +6,6 @@
#define LOG_CATEGORY UCLASS_USB_GADGET_GENERIC
-#include <common.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <linux/printk.h>
diff --git a/drivers/usb/gadget/usbstring.c b/drivers/usb/gadget/usbstring.c
index e2464ad..4617a95 100644
--- a/drivers/usb/gadget/usbstring.c
+++ b/drivers/usb/gadget/usbstring.c
@@ -6,7 +6,6 @@
* Remy Bohmer <linux@bohmer.net>
*/
-#include <common.h>
#include <linux/errno.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 637eb2d..a9dbb85 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -4,7 +4,6 @@
* Copyright (C) 2014 Marek Vasut <marex@denx.de>
*/
-#include <common.h>
#include <clk.h>
#include <cpu_func.h>
#include <dm.h>
diff --git a/drivers/usb/host/dwc3-of-simple.c b/drivers/usb/host/dwc3-of-simple.c
index f9df59d..d52e7d2 100644
--- a/drivers/usb/host/dwc3-of-simple.c
+++ b/drivers/usb/host/dwc3-of-simple.c
@@ -10,7 +10,6 @@
* Author: Neil Armstrong <narmstron@baylibre.com>
*/
-#include <common.h>
#include <dm.h>
#include <reset.h>
#include <clk.h>
diff --git a/drivers/usb/host/dwc3-sti-glue.c b/drivers/usb/host/dwc3-sti-glue.c
index 4a3ab61..3e6834e 100644
--- a/drivers/usb/host/dwc3-sti-glue.c
+++ b/drivers/usb/host/dwc3-sti-glue.c
@@ -6,7 +6,6 @@
* Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
*/
-#include <common.h>
#include <log.h>
#include <asm/global_data.h>
#include <asm/io.h>
diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c
index c6d50fd..ee75122 100644
--- a/drivers/usb/host/ehci-atmel.c
+++ b/drivers/usb/host/ehci-atmel.c
@@ -5,7 +5,6 @@
* Written-by: Bo Shen <voice.shen@atmel.com>
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c
index c1cdd4b..1e4a5a0 100644
--- a/drivers/usb/host/ehci-exynos.c
+++ b/drivers/usb/host/ehci-exynos.c
@@ -6,7 +6,6 @@
* Vivek Gautam <gautam.vivek@samsung.com>
*/
-#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include <log.h>
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 0569dd5..ee3eb06 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -7,7 +7,6 @@
* Author: Tor Krill tor@excito.com
*/
-#include <common.h>
#include <env.h>
#include <log.h>
#include <pci.h>
diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c
index 936e304..23c3ed2 100644
--- a/drivers/usb/host/ehci-generic.c
+++ b/drivers/usb/host/ehci-generic.c
@@ -3,7 +3,6 @@
* Copyright (C) 2015 Alexey Brodkin <abrodkin@synopsys.com>
*/
-#include <common.h>
#include <clk.h>
#include <log.h>
#include <dm/device_compat.h>
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 9839aa1..7d5519c 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -6,7 +6,6 @@
*
* All rights reserved.
*/
-#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <errno.h>
diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c
index 6093c8f..ca0ab57 100644
--- a/drivers/usb/host/ehci-marvell.c
+++ b/drivers/usb/host/ehci-marvell.c
@@ -5,7 +5,6 @@
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*/
-#include <common.h>
#include <log.h>
#include <asm/global_data.h>
#include <asm/io.h>
diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c
index 98fe7bc..a081f71 100644
--- a/drivers/usb/host/ehci-msm.c
+++ b/drivers/usb/host/ehci-msm.c
@@ -7,7 +7,6 @@
* Based on Linux driver
*/
-#include <common.h>
#include <dm.h>
#include <dm/lists.h>
#include <errno.h>
diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c
index c112798..fb91265 100644
--- a/drivers/usb/host/ehci-mx5.c
+++ b/drivers/usb/host/ehci-mx5.c
@@ -4,7 +4,6 @@
* Copyright (C) 2010 Freescale Semiconductor, Inc.
*/
-#include <common.h>
#include <log.h>
#include <usb.h>
#include <errno.h>
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index a35fcca..31cd8a5 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -4,7 +4,6 @@
* Copyright (C) 2010 Freescale Semiconductor, Inc.
*/
-#include <common.h>
#include <clk.h>
#include <log.h>
#include <usb.h>
diff --git a/drivers/usb/host/ehci-mxs.c b/drivers/usb/host/ehci-mxs.c
index ddf7cc2..95af5c9 100644
--- a/drivers/usb/host/ehci-mxs.c
+++ b/drivers/usb/host/ehci-mxs.c
@@ -6,7 +6,6 @@
* on behalf of DENX Software Engineering GmbH
*/
-#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <errno.h>
diff --git a/drivers/usb/host/ehci-npcm.c b/drivers/usb/host/ehci-npcm.c
index 357a561..d2a9965 100644
--- a/drivers/usb/host/ehci-npcm.c
+++ b/drivers/usb/host/ehci-npcm.c
@@ -3,7 +3,6 @@
* Copyright (c) 2021 Nuvoton Technology Corp.
*/
-#include <common.h>
#include <dm.h>
#include <generic-phy.h>
#include <reset.h>
diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c
index 765336a..a95fcad 100644
--- a/drivers/usb/host/ehci-omap.c
+++ b/drivers/usb/host/ehci-omap.c
@@ -10,8 +10,8 @@
*
*/
-#include <common.h>
#include <log.h>
+#include <time.h>
#include <usb.h>
#include <linux/delay.h>
#include <usb/ulpi.h>
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index e98ab31..5726865 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -4,7 +4,6 @@
* All rights reserved.
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <init.h>
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index 2cf1625..343893b 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -5,7 +5,6 @@
* Copyright (c) 2013 Lucas Stach
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <linux/delay.h>
diff --git a/drivers/usb/host/ehci-vf.c b/drivers/usb/host/ehci-vf.c
index 648e136..5afe28e 100644
--- a/drivers/usb/host/ehci-vf.c
+++ b/drivers/usb/host/ehci-vf.c
@@ -6,7 +6,6 @@
* Based on ehci-mx6 driver
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <usb.h>
diff --git a/drivers/usb/host/ehci-zynq.c b/drivers/usb/host/ehci-zynq.c
index f7e458c..dfaff5c 100644
--- a/drivers/usb/host/ehci-zynq.c
+++ b/drivers/usb/host/ehci-zynq.c
@@ -5,7 +5,6 @@
* USB Low level initialization(Specific to zynq)
*/
-#include <common.h>
#include <dm.h>
#include <usb.h>
#include <asm/arch/hardware.h>
diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
index 9b955c1..b170f26 100644
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -4,7 +4,6 @@
* DENX Software Engineering <mk@denx.de>
*/
-#include <common.h>
#include <asm/arch/clk.h>
int usb_cpu_init(void)
diff --git a/drivers/usb/host/ohci-da8xx.c b/drivers/usb/host/ohci-da8xx.c
index d3d73d2..d321d14 100644
--- a/drivers/usb/host/ohci-da8xx.c
+++ b/drivers/usb/host/ohci-da8xx.c
@@ -3,7 +3,6 @@
* Copyright (C) 2012 Sughosh Ganu <urwithsughosh@gmail.com>
*/
-#include <common.h>
#include <malloc.h>
#include <asm/io.h>
#include <clk.h>
diff --git a/drivers/usb/host/ohci-generic.c b/drivers/usb/host/ohci-generic.c
index ceed191..f1325cd 100644
--- a/drivers/usb/host/ohci-generic.c
+++ b/drivers/usb/host/ohci-generic.c
@@ -3,7 +3,6 @@
* Copyright (C) 2015 Alexey Brodkin <abrodkin@synopsys.com>
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 3f44181..c020d13 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -27,7 +27,7 @@
* to activate workaround for bug #41 or this driver will NOT work!
*/
-#include <common.h>
+#include <config.h>
#include <cpu_func.h>
#include <asm/byteorder.h>
#include <dm.h>
diff --git a/drivers/usb/host/ohci-lpc32xx.c b/drivers/usb/host/ohci-lpc32xx.c
index a04b296..ed04cae 100644
--- a/drivers/usb/host/ohci-lpc32xx.c
+++ b/drivers/usb/host/ohci-lpc32xx.c
@@ -7,7 +7,6 @@
* Copyright (c) 2015 Tyco Fire Protection Products.
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <init.h>
diff --git a/drivers/usb/host/ohci-npcm.c b/drivers/usb/host/ohci-npcm.c
index 9e1d529..ffeb6bc 100644
--- a/drivers/usb/host/ohci-npcm.c
+++ b/drivers/usb/host/ohci-npcm.c
@@ -3,7 +3,6 @@
* Copyright (c) 2021 Nuvoton Technology Corp.
*/
-#include <common.h>
#include <dm.h>
#include <generic-phy.h>
#include <reset.h>
diff --git a/drivers/usb/host/ohci-pci.c b/drivers/usb/host/ohci-pci.c
index f061aec..f10f109 100644
--- a/drivers/usb/host/ohci-pci.c
+++ b/drivers/usb/host/ohci-pci.c
@@ -5,7 +5,6 @@
*
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <pci.h>
diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c
index 3ccbc16..f0b18bf 100644
--- a/drivers/usb/host/r8a66597-hcd.c
+++ b/drivers/usb/host/r8a66597-hcd.c
@@ -5,7 +5,6 @@
* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*/
-#include <common.h>
#include <console.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/usb/host/usb-sandbox.c b/drivers/usb/host/usb-sandbox.c
index 3d4f8d6..e26f0b2 100644
--- a/drivers/usb/host/usb-sandbox.c
+++ b/drivers/usb/host/usb-sandbox.c
@@ -4,7 +4,6 @@
* Written by Simon Glass <sjg@chromium.org>
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <usb.h>
diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c
index a1cd0ad..cd3a07e 100644
--- a/drivers/usb/host/usb-uclass.c
+++ b/drivers/usb/host/usb-uclass.c
@@ -8,7 +8,6 @@
#define LOG_CATEGORY UCLASS_USB
-#include <common.h>
#include <bootdev.h>
#include <dm.h>
#include <errno.h>
diff --git a/drivers/usb/host/usb_bootdev.c b/drivers/usb/host/usb_bootdev.c
index 7fa1c60..362b46d 100644
--- a/drivers/usb/host/usb_bootdev.c
+++ b/drivers/usb/host/usb_bootdev.c
@@ -6,7 +6,6 @@
* Written by Simon Glass <sjg@chromium.org>
*/
-#include <common.h>
#include <bootdev.h>
#include <dm.h>
#include <usb.h>
diff --git a/drivers/usb/host/xhci-brcm.c b/drivers/usb/host/xhci-brcm.c
index fe17924..2ffad14 100644
--- a/drivers/usb/host/xhci-brcm.c
+++ b/drivers/usb/host/xhci-brcm.c
@@ -3,7 +3,6 @@
* Copyright (C) 2019 Broadcom.
*/
-#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include <usb.h>
diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
index 6cebe1c..e3e0cef 100644
--- a/drivers/usb/host/xhci-dwc3.c
+++ b/drivers/usb/host/xhci-dwc3.c
@@ -8,7 +8,6 @@
*/
#include <clk.h>
-#include <common.h>
#include <dm.h>
#include <generic-phy.h>
#include <log.h>
diff --git a/drivers/usb/host/xhci-exynos5.c b/drivers/usb/host/xhci-exynos5.c
index 270be93..6a2d422 100644
--- a/drivers/usb/host/xhci-exynos5.c
+++ b/drivers/usb/host/xhci-exynos5.c
@@ -12,7 +12,6 @@
* exynos5 specific PHY-init sequence.
*/
-#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include <log.h>
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
index e67e09e..3484ae1 100644
--- a/drivers/usb/host/xhci-fsl.c
+++ b/drivers/usb/host/xhci-fsl.c
@@ -7,7 +7,6 @@
* Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
*/
-#include <common.h>
#include <log.h>
#include <usb.h>
#include <linux/errno.h>
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index 72b7530..045b0fb 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -13,7 +13,6 @@
* Vikas Sajjan <vikas.sajjan@samsung.com>
*/
-#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
index 63dfb79..7e288f0 100644
--- a/drivers/usb/host/xhci-mtk.c
+++ b/drivers/usb/host/xhci-mtk.c
@@ -5,7 +5,6 @@
*/
#include <clk.h>
-#include <common.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <dm/devres.h>
diff --git a/drivers/usb/host/xhci-mvebu.c b/drivers/usb/host/xhci-mvebu.c
index 46b89de..1338b10 100644
--- a/drivers/usb/host/xhci-mvebu.c
+++ b/drivers/usb/host/xhci-mvebu.c
@@ -5,7 +5,6 @@
* MVEBU USB HOST xHCI Controller
*/
-#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include <log.h>
diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/host/xhci-omap.c
index 501129d..66da94c 100644
--- a/drivers/usb/host/xhci-omap.c
+++ b/drivers/usb/host/xhci-omap.c
@@ -8,7 +8,6 @@
* Author: Dan Murphy <dmurphy@ti.com>
*/
-#include <common.h>
#include <log.h>
#include <usb.h>
#include <linux/errno.h>
diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index 11f1c02..f6972af 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -5,7 +5,6 @@
* All rights reserved.
*/
-#include <common.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <init.h>
diff --git a/drivers/usb/host/xhci-rcar.c b/drivers/usb/host/xhci-rcar.c
index fedcf78..38c5928 100644
--- a/drivers/usb/host/xhci-rcar.c
+++ b/drivers/usb/host/xhci-rcar.c
@@ -5,7 +5,6 @@
* Renesas RCar USB HOST xHCI Controller
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <fdtdec.h>
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index 910c5f3..1360a59 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -13,7 +13,6 @@
* Vikas Sajjan <vikas.sajjan@samsung.com>
*/
-#include <common.h>
#include <cpu_func.h>
#include <log.h>
#include <asm/byteorder.h>
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 741e186..d30725d3 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -19,7 +19,6 @@
* The quirk devices support hasn't been given yet.
*/
-#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <dm/device_compat.h>
diff --git a/drivers/usb/isp1760/isp1760-hcd.c b/drivers/usb/isp1760/isp1760-hcd.c
index a6c4d97..96c483f 100644
--- a/drivers/usb/isp1760/isp1760-hcd.c
+++ b/drivers/usb/isp1760/isp1760-hcd.c
@@ -7,7 +7,6 @@
*/
#include <hexdump.h>
-#include <common.h>
#include <asm/cache.h>
#include <cpu_func.h>
#include <dm.h>
diff --git a/drivers/usb/isp1760/isp1760-if.c b/drivers/usb/isp1760/isp1760-if.c
index c96ab45..54246b4 100644
--- a/drivers/usb/isp1760/isp1760-if.c
+++ b/drivers/usb/isp1760/isp1760-if.c
@@ -6,7 +6,6 @@
* (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
*/
-#include <common.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <dm/device_compat.h>
diff --git a/drivers/usb/isp1760/isp1760-uboot.c b/drivers/usb/isp1760/isp1760-uboot.c
index 203500a..8dcb776 100644
--- a/drivers/usb/isp1760/isp1760-uboot.c
+++ b/drivers/usb/isp1760/isp1760-uboot.c
@@ -6,7 +6,6 @@
*
*/
-#include <common.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <dm/device_compat.h>
diff --git a/drivers/usb/mtu3/mtu3_plat.c b/drivers/usb/mtu3/mtu3_plat.c
index b1b22b9..ca86b58 100644
--- a/drivers/usb/mtu3/mtu3_plat.c
+++ b/drivers/usb/mtu3/mtu3_plat.c
@@ -5,7 +5,6 @@
* Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
*/
-#include <common.h>
#include <dm/lists.h>
#include <linux/iopoll.h>
diff --git a/drivers/usb/musb-new/am35x.c b/drivers/usb/musb-new/am35x.c
index 0a52e09..42bc816 100644
--- a/drivers/usb/musb-new/am35x.c
+++ b/drivers/usb/musb-new/am35x.c
@@ -24,7 +24,6 @@
#include <plat/usb.h>
#else
-#include <common.h>
#include <asm/omap_musb.h>
#include <linux/bug.h>
#include <linux/delay.h>
diff --git a/drivers/usb/musb-new/da8xx.c b/drivers/usb/musb-new/da8xx.c
index 68fc0c3..7caf03c 100644
--- a/drivers/usb/musb-new/da8xx.c
+++ b/drivers/usb/musb-new/da8xx.c
@@ -13,7 +13,6 @@
*
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <dm/device-internal.h>
diff --git a/drivers/usb/musb-new/mt85xx.c b/drivers/usb/musb-new/mt85xx.c
index 1e632dc..14b28bb 100644
--- a/drivers/usb/musb-new/mt85xx.c
+++ b/drivers/usb/musb-new/mt85xx.c
@@ -9,7 +9,6 @@
*
* This file is part of the Inventra Controller Driver for Linux.
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <dm/device_compat.h>
diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c
index 00da554..257e768 100644
--- a/drivers/usb/musb-new/musb_core.c
+++ b/drivers/usb/musb-new/musb_core.c
@@ -79,7 +79,6 @@
#include <linux/platform_device.h>
#include <linux/io.h>
#else
-#include <common.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <usb.h>
diff --git a/drivers/usb/musb-new/musb_dsps.c b/drivers/usb/musb-new/musb_dsps.c
index a8ff743..b73f353 100644
--- a/drivers/usb/musb-new/musb_dsps.c
+++ b/drivers/usb/musb-new/musb_dsps.c
@@ -31,7 +31,6 @@
#include <plat/usb.h>
#else
-#include <common.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <asm/omap_musb.h>
diff --git a/drivers/usb/musb-new/musb_gadget.c b/drivers/usb/musb-new/musb_gadget.c
index c608396..29e225a 100644
--- a/drivers/usb/musb-new/musb_gadget.c
+++ b/drivers/usb/musb-new/musb_gadget.c
@@ -22,7 +22,6 @@
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#else
-#include <common.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <linux/bug.h>
diff --git a/drivers/usb/musb-new/musb_gadget_ep0.c b/drivers/usb/musb-new/musb_gadget_ep0.c
index 55ce8de..63eee31 100644
--- a/drivers/usb/musb-new/musb_gadget_ep0.c
+++ b/drivers/usb/musb-new/musb_gadget_ep0.c
@@ -18,7 +18,6 @@
#include <linux/device.h>
#include <linux/interrupt.h>
#else
-#include <common.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <linux/printk.h>
diff --git a/drivers/usb/musb-new/musb_host.c b/drivers/usb/musb-new/musb_host.c
index e5905d9..2f2fc7c 100644
--- a/drivers/usb/musb-new/musb_host.c
+++ b/drivers/usb/musb-new/musb_host.c
@@ -21,7 +21,6 @@
#include <linux/list.h>
#include <linux/dma-mapping.h>
#else
-#include <common.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <usb.h>
diff --git a/drivers/usb/musb-new/musb_uboot.c b/drivers/usb/musb-new/musb_uboot.c
index 7cea9a2..43ab324 100644
--- a/drivers/usb/musb-new/musb_uboot.c
+++ b/drivers/usb/musb-new/musb_uboot.c
@@ -1,4 +1,3 @@
-#include <common.h>
#include <console.h>
#include <dm.h>
#include <malloc.h>
diff --git a/drivers/usb/musb-new/omap2430.c b/drivers/usb/musb-new/omap2430.c
index 308eff8..c8dd730 100644
--- a/drivers/usb/musb-new/omap2430.c
+++ b/drivers/usb/musb-new/omap2430.c
@@ -8,7 +8,6 @@
*
* This file is part of the Inventra Controller Driver for Linux.
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <serial.h>
diff --git a/drivers/usb/musb-new/pic32.c b/drivers/usb/musb-new/pic32.c
index 4ed5e6e..0b25e58 100644
--- a/drivers/usb/musb-new/pic32.c
+++ b/drivers/usb/musb-new/pic32.c
@@ -9,7 +9,6 @@
* Based on the dsps "glue layer" code.
*/
-#include <common.h>
#include <dm.h>
#include <asm/global_data.h>
#include <dm/device_compat.h>
diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index 778b01b..b577ba4 100644
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c
@@ -15,7 +15,6 @@
*
* This file is part of the Inventra Controller Driver for Linux.
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <generic-phy.h>
diff --git a/drivers/usb/musb-new/ti-musb.c b/drivers/usb/musb-new/ti-musb.c
index ed5e519..76e8b88 100644
--- a/drivers/usb/musb-new/ti-musb.c
+++ b/drivers/usb/musb-new/ti-musb.c
@@ -5,7 +5,6 @@
* (C) Copyright 2016
* Texas Instruments Incorporated, <www.ti.com>
*/
-#include <common.h>
#include <command.h>
#include <console.h>
#include <dm.h>
diff --git a/drivers/usb/musb-new/ux500.c b/drivers/usb/musb-new/ux500.c
index 57c7d56..6b4ef3c 100644
--- a/drivers/usb/musb-new/ux500.c
+++ b/drivers/usb/musb-new/ux500.c
@@ -1,7 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/* Copyright (C) 2019 Stephan Gerhold */
-#include <common.h>
#include <dm.h>
#include <generic-phy.h>
#include <dm/device_compat.h>
diff --git a/drivers/usb/musb/am35x.c b/drivers/usb/musb/am35x.c
index f945f1f..2c23043 100644
--- a/drivers/usb/musb/am35x.c
+++ b/drivers/usb/musb/am35x.c
@@ -9,7 +9,6 @@
* Copyright (c) 2010 Texas Instruments Incorporated
*/
-#include <common.h>
#include <linux/delay.h>
#include "am35x.h"
diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
index 9651f07..260552e 100644
--- a/drivers/usb/musb/musb_core.c
+++ b/drivers/usb/musb/musb_core.c
@@ -8,7 +8,6 @@
* Author: Thomas Abraham t-abraham@ti.com, Texas Instruments
*/
-#include <common.h>
#include <linux/bitops.h>
#include "musb_core.h"
diff --git a/drivers/usb/musb/musb_hcd.c b/drivers/usb/musb/musb_hcd.c
index 4676cab..c95c6a4 100644
--- a/drivers/usb/musb/musb_hcd.c
+++ b/drivers/usb/musb/musb_hcd.c
@@ -7,7 +7,6 @@
* Author: Thomas Abraham t-abraham@ti.com, Texas Instruments
*/
-#include <common.h>
#include <log.h>
#include <usb.h>
#include <linux/delay.h>
diff --git a/drivers/usb/musb/musb_udc.c b/drivers/usb/musb/musb_udc.c
index 2ffcb7c..696855e 100644
--- a/drivers/usb/musb/musb_udc.c
+++ b/drivers/usb/musb/musb_udc.c
@@ -37,7 +37,6 @@
* -------------------------------------------------------------------------
*/
-#include <common.h>
#include <hang.h>
#include <serial.h>
#include <usbdevice.h>
diff --git a/drivers/usb/phy/rockchip_usb2_phy.c b/drivers/usb/phy/rockchip_usb2_phy.c
index c46ad86..9ec5b2d 100644
--- a/drivers/usb/phy/rockchip_usb2_phy.c
+++ b/drivers/usb/phy/rockchip_usb2_phy.c
@@ -3,7 +3,6 @@
* Copyright 2016 Rockchip Electronics Co., Ltd
*/
-#include <common.h>
#include <hang.h>
#include <log.h>
#include <asm/global_data.h>
diff --git a/drivers/usb/ulpi/omap-ulpi-viewport.c b/drivers/usb/ulpi/omap-ulpi-viewport.c
index 1b01cd4..6f0c3eb 100644
--- a/drivers/usb/ulpi/omap-ulpi-viewport.c
+++ b/drivers/usb/ulpi/omap-ulpi-viewport.c
@@ -7,7 +7,6 @@
* Author: Govindraj R <govindraj.raja@ti.com>
*/
-#include <common.h>
#include <log.h>
#include <asm/io.h>
#include <linux/delay.h>
diff --git a/drivers/usb/ulpi/ulpi-viewport.c b/drivers/usb/ulpi/ulpi-viewport.c
index 55a6280..bac20a0 100644
--- a/drivers/usb/ulpi/ulpi-viewport.c
+++ b/drivers/usb/ulpi/ulpi-viewport.c
@@ -13,7 +13,6 @@
* Copyright (C) 2011 Google, Inc.
*/
-#include <common.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <usb/ulpi.h>
diff --git a/drivers/usb/ulpi/ulpi.c b/drivers/usb/ulpi/ulpi.c
index b5d2c2c..128adcb 100644
--- a/drivers/usb/ulpi/ulpi.c
+++ b/drivers/usb/ulpi/ulpi.c
@@ -19,7 +19,6 @@
* Freescale Semiconductors
*/
-#include <common.h>
#include <exports.h>
#include <log.h>
#include <linux/delay.h>
diff --git a/drivers/video/anx9804.c b/drivers/video/anx9804.c
index 52b5988..a149e6f 100644
--- a/drivers/video/anx9804.c
+++ b/drivers/video/anx9804.c
@@ -9,7 +9,6 @@
* interface for driving eDP TFT displays.
*/
-#include <common.h>
#include <i2c.h>
#include <linux/delay.h>
#include "anx98xx-edp.h"
diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c
index 652ba14..89bc0ee 100644
--- a/drivers/video/atmel_hlcdfb.c
+++ b/drivers/video/atmel_hlcdfb.c
@@ -5,7 +5,6 @@
* Copyright (C) 2012 Atmel Corporation
*/
-#include <common.h>
#include <cpu_func.h>
#include <log.h>
#include <malloc.h>
diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
index 5a7a54a..281c3a1 100644
--- a/drivers/video/atmel_lcdfb.c
+++ b/drivers/video/atmel_lcdfb.c
@@ -5,7 +5,6 @@
* Copyright (C) 2007 Atmel Corporation
*/
-#include <common.h>
#include <atmel_lcd.h>
#include <dm.h>
#include <fdtdec.h>
diff --git a/drivers/video/backlight-uclass.c b/drivers/video/backlight-uclass.c
index c14996d..2a09b2d 100644
--- a/drivers/video/backlight-uclass.c
+++ b/drivers/video/backlight-uclass.c
@@ -6,7 +6,6 @@
#define LOG_CATEGORY UCLASS_PANEL_BACKLIGHT
-#include <common.h>
#include <dm.h>
#include <backlight.h>
diff --git a/drivers/video/backlight_gpio.c b/drivers/video/backlight_gpio.c
index eea824a..b26fa9a 100644
--- a/drivers/video/backlight_gpio.c
+++ b/drivers/video/backlight_gpio.c
@@ -4,7 +4,6 @@
* Author: Patrick Delaunay <patrick.delaunay@foss.st.com>
*/
-#include <common.h>
#include <dm.h>
#include <backlight.h>
#include <log.h>
diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c
index 63efa76..0c81e60 100644
--- a/drivers/video/bcm2835.c
+++ b/drivers/video/bcm2835.c
@@ -3,7 +3,6 @@
* (C) Copyright 2012 Stephen Warren
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <video.h>
diff --git a/drivers/video/bmp.c b/drivers/video/bmp.c
index bab6fa7..291ed36 100644
--- a/drivers/video/bmp.c
+++ b/drivers/video/bmp.c
@@ -8,7 +8,6 @@
* BMP handling routines
*/
-#include <common.h>
#include <bmp_layout.h>
#include <command.h>
#include <dm.h>
diff --git a/drivers/video/bochs.c b/drivers/video/bochs.c
index 022ea38..00e673a 100644
--- a/drivers/video/bochs.c
+++ b/drivers/video/bochs.c
@@ -5,7 +5,6 @@
#define LOG_CATEGORY UCLASS_VIDEO
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <pci.h>
diff --git a/drivers/video/bridge/anx6345.c b/drivers/video/bridge/anx6345.c
index 93fa25f..8cee4c95 100644
--- a/drivers/video/bridge/anx6345.c
+++ b/drivers/video/bridge/anx6345.c
@@ -3,7 +3,6 @@
* Copyright (C) 2017 Vasily Khoruzhick <anarsoul@gmail.com>
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <i2c.h>
diff --git a/drivers/video/bridge/ps862x.c b/drivers/video/bridge/ps862x.c
index d1d22a6..efd0375 100644
--- a/drivers/video/bridge/ps862x.c
+++ b/drivers/video/bridge/ps862x.c
@@ -4,7 +4,6 @@
* Written by Simon Glass <sjg@chromium.org>
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <i2c.h>
diff --git a/drivers/video/bridge/ptn3460.c b/drivers/video/bridge/ptn3460.c
index 4760f04..5851e1e 100644
--- a/drivers/video/bridge/ptn3460.c
+++ b/drivers/video/bridge/ptn3460.c
@@ -4,7 +4,6 @@
* Written by Simon Glass <sjg@chromium.org>
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <video_bridge.h>
diff --git a/drivers/video/bridge/ssd2825.c b/drivers/video/bridge/ssd2825.c
index f0ef3da..f978021 100644
--- a/drivers/video/bridge/ssd2825.c
+++ b/drivers/video/bridge/ssd2825.c
@@ -3,7 +3,6 @@
* Copyright (c) 2022 Svyatoslav Ryhel <clamor95@gmail.com>
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/video/bridge/video-bridge-uclass.c b/drivers/video/bridge/video-bridge-uclass.c
index f389bc6..2084a2e 100644
--- a/drivers/video/bridge/video-bridge-uclass.c
+++ b/drivers/video/bridge/video-bridge-uclass.c
@@ -6,7 +6,6 @@
#define LOG_CATEGORY UCLASS_VIDEO_BRIDGE
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <edid.h>
diff --git a/drivers/video/broadwell_igd.c b/drivers/video/broadwell_igd.c
index 83b6c90..a26154a 100644
--- a/drivers/video/broadwell_igd.c
+++ b/drivers/video/broadwell_igd.c
@@ -5,12 +5,12 @@
* Copyright (C) 2016 Google, Inc
*/
-#include <common.h>
#include <bios_emul.h>
#include <bootstage.h>
#include <dm.h>
#include <init.h>
#include <log.h>
+#include <time.h>
#include <vesa.h>
#include <video.h>
#include <asm/cpu.h>
diff --git a/drivers/video/console_normal.c b/drivers/video/console_normal.c
index 34ef5a5..6f4194a 100644
--- a/drivers/video/console_normal.c
+++ b/drivers/video/console_normal.c
@@ -6,7 +6,6 @@
* (C) Copyright 2023 Dzmitry Sankouski <dsankouski@gmail.com>
*/
-#include <common.h>
#include <charset.h>
#include <dm.h>
#include <video.h>
diff --git a/drivers/video/console_rotate.c b/drivers/video/console_rotate.c
index e4303df..dc96983 100644
--- a/drivers/video/console_rotate.c
+++ b/drivers/video/console_rotate.c
@@ -6,7 +6,6 @@
* (C) Copyright 2023 Dzmitry Sankouski <dsankouski@gmail.com>
*/
-#include <common.h>
#include <charset.h>
#include <dm.h>
#include <video.h>
diff --git a/drivers/video/console_truetype.c b/drivers/video/console_truetype.c
index 28665a3..c435162 100644
--- a/drivers/video/console_truetype.c
+++ b/drivers/video/console_truetype.c
@@ -3,7 +3,6 @@
* Copyright (c) 2016 Google, Inc
*/
-#include <common.h>
#include <abuf.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/video/coreboot.c b/drivers/video/coreboot.c
index 5b718ae..9aede26 100644
--- a/drivers/video/coreboot.c
+++ b/drivers/video/coreboot.c
@@ -3,7 +3,6 @@
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*/
-#include <common.h>
#include <dm.h>
#include <init.h>
#include <vesa.h>
diff --git a/drivers/video/display-uclass.c b/drivers/video/display-uclass.c
index 2da3d1d..61a73e1 100644
--- a/drivers/video/display-uclass.c
+++ b/drivers/video/display-uclass.c
@@ -5,7 +5,6 @@
#define LOG_CATEGORY UCLASS_DISPLAY
-#include <common.h>
#include <dm.h>
#include <display.h>
#include <edid.h>
diff --git a/drivers/video/dsi-host-uclass.c b/drivers/video/dsi-host-uclass.c
index 6e5256e..fde275a 100644
--- a/drivers/video/dsi-host-uclass.c
+++ b/drivers/video/dsi-host-uclass.c
@@ -7,7 +7,6 @@
#define LOG_CATEGORY UCLASS_DSI_HOST
-#include <common.h>
#include <dm.h>
#include <dsi_host.h>
diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c
index c217af9..35559ce 100644
--- a/drivers/video/dw_hdmi.c
+++ b/drivers/video/dw_hdmi.c
@@ -5,13 +5,14 @@
* Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
*/
-#include <common.h>
#include <fdtdec.h>
#include <log.h>
#include <asm/io.h>
#include <i2c.h>
#include <media_bus_format.h>
+#include <time.h>
#include <linux/delay.h>
+#include <linux/errno.h>
#include "dw_hdmi.h"
struct tmds_n_cts {
diff --git a/drivers/video/dw_mipi_dsi.c b/drivers/video/dw_mipi_dsi.c
index a7e0784..c74fe67 100644
--- a/drivers/video/dw_mipi_dsi.c
+++ b/drivers/video/dw_mipi_dsi.c
@@ -9,7 +9,6 @@
* the Linux Kernel driver drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c.
*/
-#include <common.h>
#include <clk.h>
#include <dsi_host.h>
#include <dm.h>
diff --git a/drivers/video/efi.c b/drivers/video/efi.c
index 28ac15f..78d123f 100644
--- a/drivers/video/efi.c
+++ b/drivers/video/efi.c
@@ -7,7 +7,6 @@
#define LOG_CATEGORY LOGC_EFI
-#include <common.h>
#include <dm.h>
#include <efi_api.h>
#include <log.h>
diff --git a/drivers/video/endeavoru-panel.c b/drivers/video/endeavoru-panel.c
index 1bff641..d4ba4d8 100644
--- a/drivers/video/endeavoru-panel.c
+++ b/drivers/video/endeavoru-panel.c
@@ -3,7 +3,6 @@
* Copyright (c) 2022 Svyatoslav Ryhel <clamor95@gmail.com>
*/
-#include <common.h>
#include <backlight.h>
#include <dm.h>
#include <panel.h>
diff --git a/drivers/video/exynos/exynos_dp.c b/drivers/video/exynos/exynos_dp.c
index 59838da..b0afb23 100644
--- a/drivers/video/exynos/exynos_dp.c
+++ b/drivers/video/exynos/exynos_dp.c
@@ -5,7 +5,6 @@
* Author: Donghwa Lee <dh09.lee@samsung.com>
*/
-#include <common.h>
#include <dm.h>
#include <display.h>
#include <fdtdec.h>
diff --git a/drivers/video/exynos/exynos_dp_lowlevel.c b/drivers/video/exynos/exynos_dp_lowlevel.c
index ae500a7..f007b31 100644
--- a/drivers/video/exynos/exynos_dp_lowlevel.c
+++ b/drivers/video/exynos/exynos_dp_lowlevel.c
@@ -6,7 +6,6 @@
*/
#include <config.h>
-#include <common.h>
#include <log.h>
#include <linux/delay.h>
#include <linux/err.h>
diff --git a/drivers/video/exynos/exynos_fb.c b/drivers/video/exynos/exynos_fb.c
index 86970a6..0407a3f 100644
--- a/drivers/video/exynos/exynos_fb.c
+++ b/drivers/video/exynos/exynos_fb.c
@@ -7,7 +7,6 @@
*/
#include <config.h>
-#include <common.h>
#include <display.h>
#include <div64.h>
#include <dm.h>
diff --git a/drivers/video/exynos/exynos_mipi_dsi.c b/drivers/video/exynos/exynos_mipi_dsi.c
index 804fcd0..edeb0a8 100644
--- a/drivers/video/exynos/exynos_mipi_dsi.c
+++ b/drivers/video/exynos/exynos_mipi_dsi.c
@@ -6,7 +6,6 @@
* Author: Donghwa Lee <dh09.lee@samsung.com>
*/
-#include <common.h>
#include <log.h>
#include <malloc.h>
#include <fdtdec.h>
diff --git a/drivers/video/exynos/exynos_mipi_dsi_common.c b/drivers/video/exynos/exynos_mipi_dsi_common.c
index be67ceb..fc2767a 100644
--- a/drivers/video/exynos/exynos_mipi_dsi_common.c
+++ b/drivers/video/exynos/exynos_mipi_dsi_common.c
@@ -6,7 +6,6 @@
* Author: Donghwa Lee <dh09.lee@samsung.com>
*/
-#include <common.h>
#include <log.h>
#include <linux/delay.h>
#include <linux/err.h>
diff --git a/drivers/video/exynos/exynos_mipi_dsi_lowlevel.c b/drivers/video/exynos/exynos_mipi_dsi_lowlevel.c
index 8111acd..9f18b5d 100644
--- a/drivers/video/exynos/exynos_mipi_dsi_lowlevel.c
+++ b/drivers/video/exynos/exynos_mipi_dsi_lowlevel.c
@@ -6,7 +6,6 @@
* Author: Donghwa Lee <dh09.lee@samsung.com>
*/
-#include <common.h>
#include <asm/arch/dsim.h>
#include <asm/arch/mipi_dsim.h>
#include <asm/arch/power.h>
diff --git a/drivers/video/himax-hx8394.c b/drivers/video/himax-hx8394.c
index 63637b4..cb7f93e 100644
--- a/drivers/video/himax-hx8394.c
+++ b/drivers/video/himax-hx8394.c
@@ -2,7 +2,6 @@
/*
* Copyright (C) 2022 Ondrej Jirman <megi@xff.cz>
*/
-#include <common.h>
#include <backlight.h>
#include <dm.h>
#include <mipi_dsi.h>
diff --git a/drivers/video/hitachi_tx18d42vm_lcd.c b/drivers/video/hitachi_tx18d42vm_lcd.c
index 95984fe..68f7b75 100644
--- a/drivers/video/hitachi_tx18d42vm_lcd.c
+++ b/drivers/video/hitachi_tx18d42vm_lcd.c
@@ -5,7 +5,6 @@
* (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
*/
-#include <common.h>
#include <malloc.h>
#include <linux/delay.h>
diff --git a/drivers/video/hx8238d.c b/drivers/video/hx8238d.c
index 6ee97cb..2491a32 100644
--- a/drivers/video/hx8238d.c
+++ b/drivers/video/hx8238d.c
@@ -12,7 +12,6 @@
*
*/
-#include <common.h>
#include <dm.h>
#include <panel.h>
#include <spi.h>
diff --git a/drivers/video/ihs_video_out.c b/drivers/video/ihs_video_out.c
index 73b8f4b..bf4d499 100644
--- a/drivers/video/ihs_video_out.c
+++ b/drivers/video/ihs_video_out.c
@@ -9,7 +9,6 @@
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.de
*/
-#include <common.h>
#include <display.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/video/imx/ipu_common.c b/drivers/video/imx/ipu_common.c
index b0a99c9..d582fb8 100644
--- a/drivers/video/imx/ipu_common.c
+++ b/drivers/video/imx/ipu_common.c
@@ -11,7 +11,7 @@
*/
/* #define DEBUG */
-#include <common.h>
+#include <config.h>
#include <log.h>
#include <linux/delay.h>
#include <linux/types.h>
diff --git a/drivers/video/imx/ipu_disp.c b/drivers/video/imx/ipu_disp.c
index 144322e..aaba7d1 100644
--- a/drivers/video/imx/ipu_disp.c
+++ b/drivers/video/imx/ipu_disp.c
@@ -12,7 +12,6 @@
/* #define DEBUG */
-#include <common.h>
#include <log.h>
#include <linux/delay.h>
#include <linux/types.h>
diff --git a/drivers/video/imx/mxc_ipuv3_fb.c b/drivers/video/imx/mxc_ipuv3_fb.c
index 7e60385..039b220 100644
--- a/drivers/video/imx/mxc_ipuv3_fb.c
+++ b/drivers/video/imx/mxc_ipuv3_fb.c
@@ -10,7 +10,6 @@
* (C) Copyright 2004-2010 Freescale Semiconductor, Inc.
*/
-#include <common.h>
#include <log.h>
#include <part.h>
#include <asm/cache.h>
diff --git a/drivers/video/ivybridge_igd.c b/drivers/video/ivybridge_igd.c
index c2cc976..ad68864 100644
--- a/drivers/video/ivybridge_igd.c
+++ b/drivers/video/ivybridge_igd.c
@@ -3,7 +3,6 @@
* Copyright (C) 2016 Google, Inc
*/
-#include <common.h>
#include <bios_emul.h>
#include <dm.h>
#include <errno.h>
diff --git a/drivers/video/lm3533_backlight.c b/drivers/video/lm3533_backlight.c
index 00297a0..6b51fa0 100644
--- a/drivers/video/lm3533_backlight.c
+++ b/drivers/video/lm3533_backlight.c
@@ -6,7 +6,6 @@
#define LOG_CATEGORY UCLASS_PANEL_BACKLIGHT
#include <backlight.h>
-#include <common.h>
#include <dm.h>
#include <i2c.h>
#include <log.h>
diff --git a/drivers/video/logicore_dp_tx.c b/drivers/video/logicore_dp_tx.c
index 624084d..643a77a 100644
--- a/drivers/video/logicore_dp_tx.c
+++ b/drivers/video/logicore_dp_tx.c
@@ -9,7 +9,6 @@
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
*/
-#include <common.h>
#include <clk.h>
#include <display.h>
#include <dm.h>
diff --git a/drivers/video/mali_dp.c b/drivers/video/mali_dp.c
index dbb2f53..c892126 100644
--- a/drivers/video/mali_dp.c
+++ b/drivers/video/mali_dp.c
@@ -5,7 +5,6 @@
*
*/
#define DEBUG
-#include <common.h>
#include <malloc.h>
#include <video.h>
#include <dm.h>
diff --git a/drivers/video/mcde_simple.c b/drivers/video/mcde_simple.c
index 0924cee..2ba5d0d 100644
--- a/drivers/video/mcde_simple.c
+++ b/drivers/video/mcde_simple.c
@@ -1,7 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/* Copyright (C) 2019 Stephan Gerhold */
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <video.h>
diff --git a/drivers/video/meson/meson_canvas.c b/drivers/video/meson/meson_canvas.c
index eccac2f..dd4c546 100644
--- a/drivers/video/meson/meson_canvas.c
+++ b/drivers/video/meson/meson_canvas.c
@@ -6,7 +6,6 @@
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
-#include <common.h>
#include <dm.h>
#include <asm/io.h>
diff --git a/drivers/video/meson/meson_dw_hdmi.c b/drivers/video/meson/meson_dw_hdmi.c
index 259af1b..587df7b 100644
--- a/drivers/video/meson/meson_dw_hdmi.c
+++ b/drivers/video/meson/meson_dw_hdmi.c
@@ -4,7 +4,6 @@
* Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
*/
-#include <common.h>
#include <display.h>
#include <dm.h>
#include <edid.h>
diff --git a/drivers/video/meson/meson_plane.c b/drivers/video/meson/meson_plane.c
index e3f784e..899ce22 100644
--- a/drivers/video/meson/meson_plane.c
+++ b/drivers/video/meson/meson_plane.c
@@ -6,7 +6,6 @@
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
-#include <common.h>
#include <dm.h>
#include <asm/io.h>
#include <linux/bitfield.h>
diff --git a/drivers/video/meson/meson_vclk.c b/drivers/video/meson/meson_vclk.c
index e718a00..4761ff6 100644
--- a/drivers/video/meson/meson_vclk.c
+++ b/drivers/video/meson/meson_vclk.c
@@ -6,7 +6,6 @@
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
-#include <common.h>
#include <dm.h>
#include <edid.h>
#include <linux/bitops.h>
diff --git a/drivers/video/meson/meson_venc.c b/drivers/video/meson/meson_venc.c
index e7366dd..1bc6aaf 100644
--- a/drivers/video/meson/meson_venc.c
+++ b/drivers/video/meson/meson_venc.c
@@ -6,7 +6,6 @@
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
-#include <common.h>
#include <dm.h>
#include <edid.h>
#include <fdtdec.h>
diff --git a/drivers/video/meson/meson_vpu.c b/drivers/video/meson/meson_vpu.c
index 67d4ce7..ca62772 100644
--- a/drivers/video/meson/meson_vpu.c
+++ b/drivers/video/meson/meson_vpu.c
@@ -6,7 +6,6 @@
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
-#include <common.h>
#include <display.h>
#include <dm.h>
#include <efi_loader.h>
diff --git a/drivers/video/meson/meson_vpu_init.c b/drivers/video/meson/meson_vpu_init.c
index c9808e1..0e34cef 100644
--- a/drivers/video/meson/meson_vpu_init.c
+++ b/drivers/video/meson/meson_vpu_init.c
@@ -8,7 +8,6 @@
#define DEBUG
-#include <common.h>
#include <dm.h>
#include <asm/io.h>
#include <linux/bitops.h>
diff --git a/drivers/video/mipi_dsi.c b/drivers/video/mipi_dsi.c
index ecacea1..dc949c8 100644
--- a/drivers/video/mipi_dsi.c
+++ b/drivers/video/mipi_dsi.c
@@ -32,7 +32,6 @@
*
*/
-#include <common.h>
#include <clk.h>
#include <display.h>
#include <dm.h>
diff --git a/drivers/video/mvebu_lcd.c b/drivers/video/mvebu_lcd.c
index d3d07e5..3fc5640 100644
--- a/drivers/video/mvebu_lcd.c
+++ b/drivers/video/mvebu_lcd.c
@@ -5,7 +5,6 @@
* Initialization of LCD interface and setup of SPLASH screen image
*/
-#include <common.h>
#include <dm.h>
#include <part.h>
#include <video.h>
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 515363f..792d631 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -4,7 +4,6 @@
*
* Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <env.h>
diff --git a/drivers/video/nexell/s5pxx18_dp.c b/drivers/video/nexell/s5pxx18_dp.c
index 2248f47..16a489b 100644
--- a/drivers/video/nexell/s5pxx18_dp.c
+++ b/drivers/video/nexell/s5pxx18_dp.c
@@ -6,7 +6,6 @@
*/
#include <config.h>
-#include <common.h>
#include <errno.h>
#include <log.h>
#include <asm/arch/reset.h>
diff --git a/drivers/video/nexell/s5pxx18_dp_hdmi.c b/drivers/video/nexell/s5pxx18_dp_hdmi.c
index 3f1fb8a..109d9f2 100644
--- a/drivers/video/nexell/s5pxx18_dp_hdmi.c
+++ b/drivers/video/nexell/s5pxx18_dp_hdmi.c
@@ -6,7 +6,6 @@
*/
#include <config.h>
-#include <common.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/video/nexell/s5pxx18_dp_lvds.c b/drivers/video/nexell/s5pxx18_dp_lvds.c
index f8ea63f..5db8d2b 100644
--- a/drivers/video/nexell/s5pxx18_dp_lvds.c
+++ b/drivers/video/nexell/s5pxx18_dp_lvds.c
@@ -6,8 +6,8 @@
*/
#include <config.h>
-#include <common.h>
#include <errno.h>
+#include <stdio.h>
#include <asm/arch/nexell.h>
#include <asm/arch/reset.h>
diff --git a/drivers/video/nexell/s5pxx18_dp_mipi.c b/drivers/video/nexell/s5pxx18_dp_mipi.c
index 670272b..58493a8 100644
--- a/drivers/video/nexell/s5pxx18_dp_mipi.c
+++ b/drivers/video/nexell/s5pxx18_dp_mipi.c
@@ -6,7 +6,6 @@
*/
#include <config.h>
-#include <common.h>
#include <errno.h>
#include <asm/arch/nexell.h>
diff --git a/drivers/video/nexell/s5pxx18_dp_rgb.c b/drivers/video/nexell/s5pxx18_dp_rgb.c
index 44e8edb..6abb8b5 100644
--- a/drivers/video/nexell/s5pxx18_dp_rgb.c
+++ b/drivers/video/nexell/s5pxx18_dp_rgb.c
@@ -6,8 +6,8 @@
*/
#include <config.h>
-#include <common.h>
#include <errno.h>
+#include <stdio.h>
#include <asm/arch/display.h>
diff --git a/drivers/video/nexell/soc/s5pxx18_soc_disptop.h b/drivers/video/nexell/soc/s5pxx18_soc_disptop.h
index c7bf504..4ad3532 100644
--- a/drivers/video/nexell/soc/s5pxx18_soc_disptop.h
+++ b/drivers/video/nexell/soc/s5pxx18_soc_disptop.h
@@ -8,6 +8,7 @@
#ifndef _S5PXX18_SOC_DISPTOP_H_
#define _S5PXX18_SOC_DISPTOP_H_
+#include <linux/types.h>
#include "s5pxx18_soc_disptype.h"
#define NUMBER_OF_DISPTOP_MODULE 1
diff --git a/drivers/video/nexell_display.c b/drivers/video/nexell_display.c
index af2698f..7bda33f 100644
--- a/drivers/video/nexell_display.c
+++ b/drivers/video/nexell_display.c
@@ -8,7 +8,6 @@
*/
#include <config.h>
-#include <common.h>
#include <command.h>
#include <dm.h>
#include <mapmem.h>
diff --git a/drivers/video/omap3_dss.c b/drivers/video/omap3_dss.c
index 432b16b..0b7ce34 100644
--- a/drivers/video/omap3_dss.c
+++ b/drivers/video/omap3_dss.c
@@ -25,7 +25,6 @@
* MA 02111-1307 USA
*/
-#include <common.h>
#include <asm/io.h>
#include <asm/arch/dss.h>
diff --git a/drivers/video/orisetech_otm8009a.c b/drivers/video/orisetech_otm8009a.c
index 848f174..a29e909 100644
--- a/drivers/video/orisetech_otm8009a.c
+++ b/drivers/video/orisetech_otm8009a.c
@@ -7,7 +7,6 @@
* This otm8009a panel driver is inspired from the Linux Kernel driver
* drivers/gpu/drm/panel/panel-orisetech-otm8009a.c.
*/
-#include <common.h>
#include <backlight.h>
#include <dm.h>
#include <mipi_dsi.h>
diff --git a/drivers/video/panel-uclass.c b/drivers/video/panel-uclass.c
index 1f7e20e..52a3466 100644
--- a/drivers/video/panel-uclass.c
+++ b/drivers/video/panel-uclass.c
@@ -6,7 +6,6 @@
#define LOG_CATEGORY UCLASS_PANEL
-#include <common.h>
#include <dm.h>
#include <panel.h>
diff --git a/drivers/video/pwm_backlight.c b/drivers/video/pwm_backlight.c
index 1c747d9..a4576c8 100644
--- a/drivers/video/pwm_backlight.c
+++ b/drivers/video/pwm_backlight.c
@@ -6,7 +6,6 @@
#define LOG_CATEGORY UCLASS_PANEL_BACKLIGHT
-#include <common.h>
#include <dm.h>
#include <backlight.h>
#include <log.h>
diff --git a/drivers/video/raydium-rm68200.c b/drivers/video/raydium-rm68200.c
index f1fce55..b8662ca 100644
--- a/drivers/video/raydium-rm68200.c
+++ b/drivers/video/raydium-rm68200.c
@@ -7,7 +7,6 @@
* This rm68200 panel driver is inspired from the Linux Kernel driver
* drivers/gpu/drm/panel/panel-raydium-rm68200.c.
*/
-#include <common.h>
#include <backlight.h>
#include <dm.h>
#include <mipi_dsi.h>
diff --git a/drivers/video/renesas-r61307.c b/drivers/video/renesas-r61307.c
index 3f58590..a3697bc 100644
--- a/drivers/video/renesas-r61307.c
+++ b/drivers/video/renesas-r61307.c
@@ -5,7 +5,6 @@
* Copyright (c) 2022 Svyatoslav Ryhel <clamor95@gmail.com>
*/
-#include <common.h>
#include <backlight.h>
#include <dm.h>
#include <panel.h>
diff --git a/drivers/video/renesas-r69328.c b/drivers/video/renesas-r69328.c
index 082f5bc..9861c3f 100644
--- a/drivers/video/renesas-r69328.c
+++ b/drivers/video/renesas-r69328.c
@@ -5,7 +5,6 @@
* Copyright (c) 2022 Svyatoslav Ryhel <clamor95@gmail.com>
*/
-#include <common.h>
#include <backlight.h>
#include <dm.h>
#include <panel.h>
diff --git a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
index fb78463..fa51217 100644
--- a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
+++ b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
@@ -24,7 +24,6 @@
#include <dm/lists.h>
#include <linux/iopoll.h>
-#include <common.h>
#include <log.h>
#include <video.h>
#include <dm/device-internal.h>
diff --git a/drivers/video/rockchip/rk3288_hdmi.c b/drivers/video/rockchip/rk3288_hdmi.c
index efa8754..3d39f31 100644
--- a/drivers/video/rockchip/rk3288_hdmi.c
+++ b/drivers/video/rockchip/rk3288_hdmi.c
@@ -3,7 +3,6 @@
* Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
*/
-#include <common.h>
#include <clk.h>
#include <display.h>
#include <dm.h>
diff --git a/drivers/video/rockchip/rk3288_mipi.c b/drivers/video/rockchip/rk3288_mipi.c
index 9d42119..850fe31 100644
--- a/drivers/video/rockchip/rk3288_mipi.c
+++ b/drivers/video/rockchip/rk3288_mipi.c
@@ -4,7 +4,6 @@
* Author: Eric Gao <eric.gao@rock-chips.com>
*/
-#include <common.h>
#include <clk.h>
#include <display.h>
#include <dm.h>
diff --git a/drivers/video/rockchip/rk3288_vop.c b/drivers/video/rockchip/rk3288_vop.c
index a468385..282831e 100644
--- a/drivers/video/rockchip/rk3288_vop.c
+++ b/drivers/video/rockchip/rk3288_vop.c
@@ -5,7 +5,6 @@
* Copyright 2014 Rockchip Inc.
*/
-#include <common.h>
#include <display.h>
#include <dm.h>
#include <regmap.h>
diff --git a/drivers/video/rockchip/rk3399_hdmi.c b/drivers/video/rockchip/rk3399_hdmi.c
index 5f3f5d2..c7630cc 100644
--- a/drivers/video/rockchip/rk3399_hdmi.c
+++ b/drivers/video/rockchip/rk3399_hdmi.c
@@ -3,7 +3,6 @@
* Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
*/
-#include <common.h>
#include <clk.h>
#include <display.h>
#include <dm.h>
diff --git a/drivers/video/rockchip/rk3399_mipi.c b/drivers/video/rockchip/rk3399_mipi.c
index b62d808..57e36ee 100644
--- a/drivers/video/rockchip/rk3399_mipi.c
+++ b/drivers/video/rockchip/rk3399_mipi.c
@@ -4,7 +4,6 @@
* Author: Eric Gao <eric.gao@rock-chips.com>
*/
-#include <common.h>
#include <clk.h>
#include <display.h>
#include <dm.h>
diff --git a/drivers/video/rockchip/rk3399_vop.c b/drivers/video/rockchip/rk3399_vop.c
index cb589c7..17e1601 100644
--- a/drivers/video/rockchip/rk3399_vop.c
+++ b/drivers/video/rockchip/rk3399_vop.c
@@ -5,7 +5,6 @@
* Copyright 2014 Rockchip Inc.
*/
-#include <common.h>
#include <display.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c
index 5f68a61..eb881ba 100644
--- a/drivers/video/rockchip/rk_edp.c
+++ b/drivers/video/rockchip/rk_edp.c
@@ -4,7 +4,6 @@
* Copyright 2014 Rockchip Inc.
*/
-#include <common.h>
#include <clk.h>
#include <display.h>
#include <dm.h>
diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c
index d31f6a4..0ac0a3a 100644
--- a/drivers/video/rockchip/rk_hdmi.c
+++ b/drivers/video/rockchip/rk_hdmi.c
@@ -5,7 +5,6 @@
* Copyright 2014 Rockchip Inc.
*/
-#include <common.h>
#include <clk.h>
#include <display.h>
#include <dm.h>
diff --git a/drivers/video/rockchip/rk_lvds.c b/drivers/video/rockchip/rk_lvds.c
index d0a015e..c969dae 100644
--- a/drivers/video/rockchip/rk_lvds.c
+++ b/drivers/video/rockchip/rk_lvds.c
@@ -3,7 +3,6 @@
* Copyright 2016 Rockchip Inc.
*/
-#include <common.h>
#include <display.h>
#include <dm.h>
#include <edid.h>
diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c
index f14cbc6..0a60308 100644
--- a/drivers/video/rockchip/rk_mipi.c
+++ b/drivers/video/rockchip/rk_mipi.c
@@ -4,7 +4,6 @@
* Author: Eric Gao <eric.gao@rock-chips.com>
*/
-#include <common.h>
#include <clk.h>
#include <display.h>
#include <dm.h>
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index acc02e5..17dfe62 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -4,7 +4,6 @@
* Copyright 2014 Rockchip Inc.
*/
-#include <common.h>
#include <clk.h>
#include <display.h>
#include <dm.h>
diff --git a/drivers/video/sandbox_dsi_host.c b/drivers/video/sandbox_dsi_host.c
index c84a27e..7025ac9 100644
--- a/drivers/video/sandbox_dsi_host.c
+++ b/drivers/video/sandbox_dsi_host.c
@@ -3,7 +3,6 @@
* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
*/
-#include <common.h>
#include <display.h>
#include <dm.h>
#include <dsi_host.h>
diff --git a/drivers/video/sandbox_osd.c b/drivers/video/sandbox_osd.c
index 2a854d3..bedc32b 100644
--- a/drivers/video/sandbox_osd.c
+++ b/drivers/video/sandbox_osd.c
@@ -3,7 +3,6 @@
* (C) Copyright 2018
* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
*/
-#include <common.h>
#include <display.h>
#include <dm.h>
#include <malloc.h>
diff --git a/drivers/video/sandbox_sdl.c b/drivers/video/sandbox_sdl.c
index 9081c7d..69dfa93 100644
--- a/drivers/video/sandbox_sdl.c
+++ b/drivers/video/sandbox_sdl.c
@@ -3,7 +3,6 @@
* Copyright (c) 2013 Google, Inc
*/
-#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include <log.h>
diff --git a/drivers/video/seps525.c b/drivers/video/seps525.c
index 74c8721..86cd301 100644
--- a/drivers/video/seps525.c
+++ b/drivers/video/seps525.c
@@ -6,7 +6,6 @@
* Copyright (C) 2020 Xilinx Inc.
*/
-#include <common.h>
#include <command.h>
#include <cpu_func.h>
#include <dm.h>
diff --git a/drivers/video/simple_panel.c b/drivers/video/simple_panel.c
index 76a3042..b6c5b05 100644
--- a/drivers/video/simple_panel.c
+++ b/drivers/video/simple_panel.c
@@ -4,7 +4,6 @@
* Written by Simon Glass <sjg@chromium.org>
*/
-#include <common.h>
#include <backlight.h>
#include <dm.h>
#include <edid.h>
diff --git a/drivers/video/simplefb.c b/drivers/video/simplefb.c
index 33bb78b..cb518b1 100644
--- a/drivers/video/simplefb.c
+++ b/drivers/video/simplefb.c
@@ -3,7 +3,6 @@
* (C) Copyright 2017 Rob Clark
*/
-#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include <fdt_support.h>
diff --git a/drivers/video/ssd2828.c b/drivers/video/ssd2828.c
index 948f5e7..4334bbd 100644
--- a/drivers/video/ssd2828.c
+++ b/drivers/video/ssd2828.c
@@ -9,7 +9,6 @@
* interface for driving a MIPI compatible TFT display.
*/
-#include <common.h>
#include <malloc.h>
#include <mipi_display.h>
#include <asm/gpio.h>
diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c
index a18c1e0..438ed41 100644
--- a/drivers/video/stm32/stm32_dsi.c
+++ b/drivers/video/stm32/stm32_dsi.c
@@ -10,7 +10,6 @@
#define LOG_CATEGORY UCLASS_VIDEO_BRIDGE
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <dsi_host.h>
diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index 4f60ba8..0a062c8 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -7,7 +7,6 @@
#define LOG_CATEGORY UCLASS_VIDEO
-#include <common.h>
#include <clk.h>
#include <display.h>
#include <dm.h>
diff --git a/drivers/video/sunxi/lcdc.c b/drivers/video/sunxi/lcdc.c
index 73033c3..264d775 100644
--- a/drivers/video/sunxi/lcdc.c
+++ b/drivers/video/sunxi/lcdc.c
@@ -7,7 +7,6 @@
* (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
*/
-#include <common.h>
#include <log.h>
#include <linux/delay.h>
diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c
index e02d359..154641b 100644
--- a/drivers/video/sunxi/sunxi_de2.c
+++ b/drivers/video/sunxi/sunxi_de2.c
@@ -5,7 +5,6 @@
* (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
*/
-#include <common.h>
#include <display.h>
#include <dm.h>
#include <edid.h>
diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c
index 8da44a1..4a6a89e 100644
--- a/drivers/video/sunxi/sunxi_display.c
+++ b/drivers/video/sunxi/sunxi_display.c
@@ -6,7 +6,7 @@
* (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
*/
-#include <common.h>
+#include <config.h>
#include <display.h>
#include <dm.h>
#include <cpu_func.h>
diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c
index a5e8d39..b9c03ea 100644
--- a/drivers/video/sunxi/sunxi_dw_hdmi.c
+++ b/drivers/video/sunxi/sunxi_dw_hdmi.c
@@ -6,7 +6,6 @@
*/
#include <clk.h>
-#include <common.h>
#include <display.h>
#include <dm.h>
#include <dw_hdmi.h>
diff --git a/drivers/video/sunxi/sunxi_lcd.c b/drivers/video/sunxi/sunxi_lcd.c
index 7a01cc3..953233f 100644
--- a/drivers/video/sunxi/sunxi_lcd.c
+++ b/drivers/video/sunxi/sunxi_lcd.c
@@ -5,7 +5,6 @@
* (C) Copyright 2017 Vasily Khoruzhick <anarsoul@gmail.com>
*/
-#include <common.h>
#include <display.h>
#include <log.h>
#include <video_bridge.h>
diff --git a/drivers/video/sunxi/tve_common.c b/drivers/video/sunxi/tve_common.c
index 3525137..7bc2b3b 100644
--- a/drivers/video/sunxi/tve_common.c
+++ b/drivers/video/sunxi/tve_common.c
@@ -7,7 +7,6 @@
* (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
*/
-#include <common.h>
#include <asm/arch/tve.h>
#include <asm/io.h>
diff --git a/drivers/video/tda19988.c b/drivers/video/tda19988.c
index 2448743..ebc8521 100644
--- a/drivers/video/tda19988.c
+++ b/drivers/video/tda19988.c
@@ -5,7 +5,6 @@
* Based on the Linux driver, (C) 2012 Texas Instruments
*/
-#include <common.h>
#include <dm.h>
#include <display.h>
#include <i2c.h>
diff --git a/drivers/video/tdo-tl070wsh30.c b/drivers/video/tdo-tl070wsh30.c
index 273672d..d772958 100644
--- a/drivers/video/tdo-tl070wsh30.c
+++ b/drivers/video/tdo-tl070wsh30.c
@@ -3,7 +3,6 @@
* Copyright (C) 2020 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
-#include <common.h>
#include <backlight.h>
#include <dm.h>
#include <mipi_dsi.h>
diff --git a/drivers/video/tegra124/display.c b/drivers/video/tegra124/display.c
index 9261cc9..abe31e2 100644
--- a/drivers/video/tegra124/display.c
+++ b/drivers/video/tegra124/display.c
@@ -5,7 +5,6 @@
* Extracted from Chromium coreboot commit 3f59b13d
*/
-#include <common.h>
#include <bootstage.h>
#include <dm.h>
#include <edid.h>
@@ -14,6 +13,7 @@
#include <edid.h>
#include <log.h>
#include <part.h>
+#include <time.h>
#include <video.h>
#include <asm/gpio.h>
#include <asm/io.h>
diff --git a/drivers/video/tegra124/dp.c b/drivers/video/tegra124/dp.c
index b27b163..763f7ee 100644
--- a/drivers/video/tegra124/dp.c
+++ b/drivers/video/tegra124/dp.c
@@ -4,12 +4,12 @@
* Copyright 2014 Google Inc.
*/
-#include <common.h>
#include <display.h>
#include <dm.h>
#include <div64.h>
#include <errno.h>
#include <log.h>
+#include <time.h>
#include <video_bridge.h>
#include <asm/io.h>
#include <asm/arch-tegra/dc.h>
diff --git a/drivers/video/tegra124/sor.c b/drivers/video/tegra124/sor.c
index 2586851..1ce5330 100644
--- a/drivers/video/tegra124/sor.c
+++ b/drivers/video/tegra124/sor.c
@@ -3,7 +3,6 @@
* Copyright (c) 2011-2013, NVIDIA Corporation.
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/video/tegra20/mipi-phy.c b/drivers/video/tegra20/mipi-phy.c
index c3ebc40..576262e 100644
--- a/drivers/video/tegra20/mipi-phy.c
+++ b/drivers/video/tegra20/mipi-phy.c
@@ -3,7 +3,6 @@
* Copyright (C) 2013 NVIDIA Corporation
*/
-#include <common.h>
#include <linux/err.h>
#include "mipi-phy.h"
diff --git a/drivers/video/tegra20/tegra-dsi.c b/drivers/video/tegra20/tegra-dsi.c
index 13dae37..35a8e6c 100644
--- a/drivers/video/tegra20/tegra-dsi.c
+++ b/drivers/video/tegra20/tegra-dsi.c
@@ -4,7 +4,6 @@
* Copyright (c) 2022 Svyatoslav Ryhel <clamor95@gmail.com>
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <misc.h>
diff --git a/drivers/video/tegra20/tegra-pwm-backlight.c b/drivers/video/tegra20/tegra-pwm-backlight.c
index 5f93f57..79d8a02 100644
--- a/drivers/video/tegra20/tegra-pwm-backlight.c
+++ b/drivers/video/tegra20/tegra-pwm-backlight.c
@@ -6,7 +6,6 @@
#define LOG_CATEGORY UCLASS_PANEL_BACKLIGHT
#include <backlight.h>
-#include <common.h>
#include <dm.h>
#include <i2c.h>
#include <log.h>
diff --git a/drivers/video/ti/tilcdc-panel.c b/drivers/video/ti/tilcdc-panel.c
index df95086..d407652 100644
--- a/drivers/video/ti/tilcdc-panel.c
+++ b/drivers/video/ti/tilcdc-panel.c
@@ -5,7 +5,6 @@
* Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
*/
-#include <common.h>
#include <backlight.h>
#include <clk.h>
#include <display.h>
diff --git a/drivers/video/ti/tilcdc.c b/drivers/video/ti/tilcdc.c
index 2734754..493e2f1 100644
--- a/drivers/video/ti/tilcdc.c
+++ b/drivers/video/ti/tilcdc.c
@@ -3,7 +3,6 @@
* Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <dm/device_compat.h>
diff --git a/drivers/video/tidss/tidss_drv.c b/drivers/video/tidss/tidss_drv.c
index 1380c6b..865d4bd 100644
--- a/drivers/video/tidss/tidss_drv.c
+++ b/drivers/video/tidss/tidss_drv.c
@@ -9,7 +9,6 @@
* Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
*/
-#include <common.h>
#include <dm.h>
#include <clk.h>
#include <log.h>
diff --git a/drivers/video/vesa.c b/drivers/video/vesa.c
index 50912c5..ab756ac 100644
--- a/drivers/video/vesa.c
+++ b/drivers/video/vesa.c
@@ -3,7 +3,6 @@
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <pci.h>
diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c
index 5d06e51..80e7adf 100644
--- a/drivers/video/vidconsole-uclass.c
+++ b/drivers/video/vidconsole-uclass.c
@@ -9,7 +9,6 @@
#define LOG_CATEGORY UCLASS_VIDEO_CONSOLE
-#include <common.h>
#include <abuf.h>
#include <charset.h>
#include <command.h>
diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c
index 7b5d1df..ff1382f 100644
--- a/drivers/video/video-uclass.c
+++ b/drivers/video/video-uclass.c
@@ -5,7 +5,6 @@
#define LOG_CATEGORY UCLASS_VIDEO
-#include <common.h>
#include <bloblist.h>
#include <console.h>
#include <cpu_func.h>
diff --git a/drivers/video/video_bmp.c b/drivers/video/video_bmp.c
index 45f003c..ad512d9 100644
--- a/drivers/video/video_bmp.c
+++ b/drivers/video/video_bmp.c
@@ -3,7 +3,6 @@
* Copyright (c) 2015 Google, Inc
*/
-#include <common.h>
#include <bmp_layout.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/video/video_osd-uclass.c b/drivers/video/video_osd-uclass.c
index 0d3aae4..9236863 100644
--- a/drivers/video/video_osd-uclass.c
+++ b/drivers/video/video_osd-uclass.c
@@ -6,7 +6,6 @@
#define LOG_CATEGORY UCLASS_VIDEO_OSD
-#include <common.h>
#include <dm.h>
#include <video_osd.h>
diff --git a/drivers/video/videomodes.c b/drivers/video/videomodes.c
index 35955a5..d86d867 100644
--- a/drivers/video/videomodes.c
+++ b/drivers/video/videomodes.c
@@ -55,7 +55,6 @@
"myvideo" and setting the variable "videomode=myvideo"..
****************************************************************************/
-#include <common.h>
#include <edid.h>
#include <env.h>
#include <errno.h>
diff --git a/drivers/video/zynqmp/zynqmp_dpsub.c b/drivers/video/zynqmp/zynqmp_dpsub.c
index def4dcf..1405b29 100644
--- a/drivers/video/zynqmp/zynqmp_dpsub.c
+++ b/drivers/video/zynqmp/zynqmp_dpsub.c
@@ -6,7 +6,6 @@
* Xilinx displayport(DP) Tx Subsytem driver
*/
-#include <common.h>
#include <clk.h>
#include <cpu_func.h>
#include <dm.h>
diff --git a/drivers/virtio/virtio-uclass.c b/drivers/virtio/virtio-uclass.c
index c542016..1dbc1a5 100644
--- a/drivers/virtio/virtio-uclass.c
+++ b/drivers/virtio/virtio-uclass.c
@@ -17,7 +17,6 @@
#define LOG_CATEGORY UCLASS_VIRTIO
-#include <common.h>
#include <bootdev.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/virtio/virtio_blk.c b/drivers/virtio/virtio_blk.c
index 9581058..3404f61 100644
--- a/drivers/virtio/virtio_blk.c
+++ b/drivers/virtio/virtio_blk.c
@@ -6,7 +6,6 @@
#define LOG_CATEGORY UCLASS_VIRTIO
-#include <common.h>
#include <blk.h>
#include <dm.h>
#include <part.h>
diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c
index 78c15c8..1cd737a 100644
--- a/drivers/virtio/virtio_mmio.c
+++ b/drivers/virtio/virtio_mmio.c
@@ -7,7 +7,6 @@
* Ported from Linux drivers/virtio/virtio_mmio.c
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <virtio_types.h>
diff --git a/drivers/virtio/virtio_net.c b/drivers/virtio/virtio_net.c
index 1794f73..0e5367a 100644
--- a/drivers/virtio/virtio_net.c
+++ b/drivers/virtio/virtio_net.c
@@ -4,7 +4,6 @@
* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
*/
-#include <common.h>
#include <dm.h>
#include <net.h>
#include <virtio_types.h>
diff --git a/drivers/virtio/virtio_pci_legacy.c b/drivers/virtio/virtio_pci_legacy.c
index aa89604..15f8c6e 100644
--- a/drivers/virtio/virtio_pci_legacy.c
+++ b/drivers/virtio/virtio_pci_legacy.c
@@ -6,7 +6,6 @@
* Ported from Linux drivers/virtio/virtio_pci*.c
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <virtio_types.h>
diff --git a/drivers/virtio/virtio_pci_modern.c b/drivers/virtio/virtio_pci_modern.c
index 3cdc2d2..5850e0c 100644
--- a/drivers/virtio/virtio_pci_modern.c
+++ b/drivers/virtio/virtio_pci_modern.c
@@ -6,7 +6,6 @@
* Ported from Linux drivers/virtio/virtio_pci*.c
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <virtio_types.h>
diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c
index c9adcce..306fa5b 100644
--- a/drivers/virtio/virtio_ring.c
+++ b/drivers/virtio/virtio_ring.c
@@ -7,7 +7,6 @@
*/
#include <bouncebuf.h>
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <malloc.h>
diff --git a/drivers/virtio/virtio_rng.c b/drivers/virtio/virtio_rng.c
index 786359a..90a371a 100644
--- a/drivers/virtio/virtio_rng.c
+++ b/drivers/virtio/virtio_rng.c
@@ -3,7 +3,6 @@
* Copyright (c) 2019, Linaro Limited
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <rng.h>
diff --git a/drivers/virtio/virtio_sandbox.c b/drivers/virtio/virtio_sandbox.c
index b34f1d6..0f1ebef 100644
--- a/drivers/virtio/virtio_sandbox.c
+++ b/drivers/virtio/virtio_sandbox.c
@@ -5,7 +5,6 @@
* VirtIO Sandbox transport driver, for testing purpose only
*/
-#include <common.h>
#include <dm.h>
#include <virtio_types.h>
#include <virtio.h>
diff --git a/drivers/w1-eeprom/ds24xxx.c b/drivers/w1-eeprom/ds24xxx.c
index 4be378b..413d8bc 100644
--- a/drivers/w1-eeprom/ds24xxx.c
+++ b/drivers/w1-eeprom/ds24xxx.c
@@ -7,7 +7,6 @@
*
*/
-#include <common.h>
#include <linux/err.h>
#include <dm.h>
#include <w1-eeprom.h>
diff --git a/drivers/w1-eeprom/ds2502.c b/drivers/w1-eeprom/ds2502.c
index a67f5ed..db9f41e 100644
--- a/drivers/w1-eeprom/ds2502.c
+++ b/drivers/w1-eeprom/ds2502.c
@@ -20,7 +20,6 @@
* Martin Fuzzey <martin.fuzzey@flowbird.group>
*/
-#include <common.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <linux/err.h>
diff --git a/drivers/w1-eeprom/eep_sandbox.c b/drivers/w1-eeprom/eep_sandbox.c
index 27c7f9f..2a69ca2 100644
--- a/drivers/w1-eeprom/eep_sandbox.c
+++ b/drivers/w1-eeprom/eep_sandbox.c
@@ -4,7 +4,6 @@
*
*/
-#include <common.h>
#include <linux/err.h>
#include <dm.h>
#include <w1-eeprom.h>
diff --git a/drivers/w1-eeprom/w1-eeprom-uclass.c b/drivers/w1-eeprom/w1-eeprom-uclass.c
index 70ba537..3919aad 100644
--- a/drivers/w1-eeprom/w1-eeprom-uclass.c
+++ b/drivers/w1-eeprom/w1-eeprom-uclass.c
@@ -12,7 +12,6 @@
#define LOG_CATEGORY UCLASS_W1_EEPROM
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <w1.h>
diff --git a/drivers/w1/mxc_w1.c b/drivers/w1/mxc_w1.c
index b96c1a0..9ebfc13 100644
--- a/drivers/w1/mxc_w1.c
+++ b/drivers/w1/mxc_w1.c
@@ -17,7 +17,6 @@
* Martin Fuzzey <martin.fuzzey@flowbird.group>
*/
-#include <common.h>
#include <asm/arch/clock.h>
#include <dm.h>
#include <dm/device_compat.h>
diff --git a/drivers/w1/w1-gpio.c b/drivers/w1/w1-gpio.c
index 9346f81..759f94e 100644
--- a/drivers/w1/w1-gpio.c
+++ b/drivers/w1/w1-gpio.c
@@ -7,7 +7,6 @@
*
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <w1.h>
diff --git a/drivers/w1/w1-uclass.c b/drivers/w1/w1-uclass.c
index a4247ec..9637ed2 100644
--- a/drivers/w1/w1-uclass.c
+++ b/drivers/w1/w1-uclass.c
@@ -14,7 +14,6 @@
#define LOG_CATEGORY UCLASS_W1
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/watchdog/armada-37xx-wdt.c b/drivers/watchdog/armada-37xx-wdt.c
index e09f5ac..4b51178 100644
--- a/drivers/watchdog/armada-37xx-wdt.c
+++ b/drivers/watchdog/armada-37xx-wdt.c
@@ -5,7 +5,6 @@
* Marek Behún <kabel@kernel.org>
*/
-#include <common.h>
#include <dm.h>
#include <wdt.h>
#include <asm/global_data.h>
diff --git a/drivers/watchdog/ast2600_wdt.c b/drivers/watchdog/ast2600_wdt.c
index bc98420..190490f 100644
--- a/drivers/watchdog/ast2600_wdt.c
+++ b/drivers/watchdog/ast2600_wdt.c
@@ -3,7 +3,6 @@
* Copyright (c) 2020 Aspeed Technology, Inc
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/watchdog/ast_wdt.c b/drivers/watchdog/ast_wdt.c
index f7b5a1a..e61e13f 100644
--- a/drivers/watchdog/ast_wdt.c
+++ b/drivers/watchdog/ast_wdt.c
@@ -3,7 +3,6 @@
* Copyright 2017 Google, Inc
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c
index 647ae32..c809a89 100644
--- a/drivers/watchdog/at91sam9_wdt.c
+++ b/drivers/watchdog/at91sam9_wdt.c
@@ -18,7 +18,6 @@
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/at91_wdt.h>
-#include <common.h>
#include <div64.h>
#include <dm.h>
#include <errno.h>
diff --git a/drivers/watchdog/bcm6345_wdt.c b/drivers/watchdog/bcm6345_wdt.c
index 677b134..6ebe901 100644
--- a/drivers/watchdog/bcm6345_wdt.c
+++ b/drivers/watchdog/bcm6345_wdt.c
@@ -7,7 +7,6 @@
* Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <wdt.h>
diff --git a/drivers/watchdog/cdns_wdt.c b/drivers/watchdog/cdns_wdt.c
index 743ab64..cb5a786 100644
--- a/drivers/watchdog/cdns_wdt.c
+++ b/drivers/watchdog/cdns_wdt.c
@@ -6,7 +6,6 @@
* Author(s): Shreenidhi Shedi <yesshedi@gmail.com>
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <wdt.h>
diff --git a/drivers/watchdog/cortina_wdt.c b/drivers/watchdog/cortina_wdt.c
index 7ab9d7b..9f09ac0 100644
--- a/drivers/watchdog/cortina_wdt.c
+++ b/drivers/watchdog/cortina_wdt.c
@@ -4,7 +4,6 @@
*
*/
-#include <common.h>
#include <dm.h>
#include <hang.h>
#include <asm/io.h>
diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c
index b22e0ee..bd9d710 100644
--- a/drivers/watchdog/designware_wdt.c
+++ b/drivers/watchdog/designware_wdt.c
@@ -4,7 +4,6 @@
*/
#include <clk.h>
-#include <common.h>
#include <dm.h>
#include <reset.h>
#include <wdt.h>
diff --git a/drivers/watchdog/ftwdt010_wdt.c b/drivers/watchdog/ftwdt010_wdt.c
index 1f5f301..4769b96 100644
--- a/drivers/watchdog/ftwdt010_wdt.c
+++ b/drivers/watchdog/ftwdt010_wdt.c
@@ -14,7 +14,6 @@
* 22/08/2022 Port to DM
*/
-#include <common.h>
#include <dm.h>
#include <wdt.h>
#include <log.h>
diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c
index 894158b..ea77021 100644
--- a/drivers/watchdog/imx_watchdog.c
+++ b/drivers/watchdog/imx_watchdog.c
@@ -4,7 +4,6 @@
* Licensed under the GPL-2 or later.
*/
-#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <hang.h>
diff --git a/drivers/watchdog/mcf_wdt.c b/drivers/watchdog/mcf_wdt.c
index b36488b..5092a25 100644
--- a/drivers/watchdog/mcf_wdt.c
+++ b/drivers/watchdog/mcf_wdt.c
@@ -6,7 +6,7 @@
*
*/
-#include <common.h>
+#include <config.h>
#include <dm.h>
#include <hang.h>
#include <asm/io.h>
diff --git a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c
index f28636c..036ff69 100644
--- a/drivers/watchdog/mpc8xxx_wdt.c
+++ b/drivers/watchdog/mpc8xxx_wdt.c
@@ -3,7 +3,6 @@
* Copyright 2017 CS Systemes d'Information
*/
-#include <common.h>
#include <env.h>
#include <dm.h>
#include <wdt.h>
diff --git a/drivers/watchdog/mt7621_wdt.c b/drivers/watchdog/mt7621_wdt.c
index f7d201b..6308d96 100644
--- a/drivers/watchdog/mt7621_wdt.c
+++ b/drivers/watchdog/mt7621_wdt.c
@@ -9,7 +9,6 @@
* Copyright (C) 2013 John Crispin <blogic@openwrt.org>
*/
-#include <common.h>
#include <dm.h>
#include <wdt.h>
#include <asm/global_data.h>
diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
index 368b368..706deb9 100644
--- a/drivers/watchdog/mtk_wdt.c
+++ b/drivers/watchdog/mtk_wdt.c
@@ -6,7 +6,6 @@
* Author: Ryder Lee <ryder.lee@mediatek.com>
*/
-#include <common.h>
#include <dm.h>
#include <hang.h>
#include <wdt.h>
diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c
index f0e57b4..5fd02dd 100644
--- a/drivers/watchdog/omap_wdt.c
+++ b/drivers/watchdog/omap_wdt.c
@@ -36,7 +36,6 @@
* Use the driver model and standard identifiers; handle bigger timeouts.
*/
-#include <common.h>
#include <log.h>
#include <watchdog.h>
#include <asm/ti-common/omap_wdt.h>
diff --git a/drivers/watchdog/orion_wdt.c b/drivers/watchdog/orion_wdt.c
index 127766d..4562b2a 100644
--- a/drivers/watchdog/orion_wdt.c
+++ b/drivers/watchdog/orion_wdt.c
@@ -12,7 +12,6 @@
* warranty of any kind, whether express or implied.
*/
-#include <common.h>
#include <dm.h>
#include <clk.h>
#include <log.h>
diff --git a/drivers/watchdog/rti_wdt.c b/drivers/watchdog/rti_wdt.c
index 8d93f19..99168d0 100644
--- a/drivers/watchdog/rti_wdt.c
+++ b/drivers/watchdog/rti_wdt.c
@@ -8,7 +8,6 @@
* Derived from linux/drivers/watchdog/rti_wdt.c
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <dm/device_compat.h>
diff --git a/drivers/watchdog/s5p_wdt.c b/drivers/watchdog/s5p_wdt.c
index 80524a0..c244f15 100644
--- a/drivers/watchdog/s5p_wdt.c
+++ b/drivers/watchdog/s5p_wdt.c
@@ -4,7 +4,6 @@
* Minkyu Kang <mk7.kang@samsung.com>
*/
-#include <common.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/watchdog.h>
diff --git a/drivers/watchdog/sandbox_alarm-wdt.c b/drivers/watchdog/sandbox_alarm-wdt.c
index 71bb5d9..8dbbfc2 100644
--- a/drivers/watchdog/sandbox_alarm-wdt.c
+++ b/drivers/watchdog/sandbox_alarm-wdt.c
@@ -1,4 +1,3 @@
-#include <common.h>
#include <dm.h>
#include <os.h>
#include <wdt.h>
diff --git a/drivers/watchdog/sandbox_wdt.c b/drivers/watchdog/sandbox_wdt.c
index 535614f..cd5eadb 100644
--- a/drivers/watchdog/sandbox_wdt.c
+++ b/drivers/watchdog/sandbox_wdt.c
@@ -3,7 +3,6 @@
* Copyright 2017 Google, Inc
*/
-#include <common.h>
#include <dm.h>
#include <wdt.h>
#include <asm/state.h>
diff --git a/drivers/watchdog/sbsa_gwdt.c b/drivers/watchdog/sbsa_gwdt.c
index 96d0466..0358552 100644
--- a/drivers/watchdog/sbsa_gwdt.c
+++ b/drivers/watchdog/sbsa_gwdt.c
@@ -7,7 +7,6 @@
#include <asm/global_data.h>
#include <asm/io.h>
-#include <common.h>
#include <dm/device.h>
#include <dm/fdtaddr.h>
#include <dm/read.h>
diff --git a/drivers/watchdog/sl28cpld-wdt.c b/drivers/watchdog/sl28cpld-wdt.c
index af5a6b1..c5b4f8a 100644
--- a/drivers/watchdog/sl28cpld-wdt.c
+++ b/drivers/watchdog/sl28cpld-wdt.c
@@ -5,7 +5,6 @@
* Copyright (c) 2021 Michael Walle <michael@walle.cc>
*/
-#include <common.h>
#include <dm.h>
#include <wdt.h>
#include <sl28cpld.h>
diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c
index 6d58fd3..10fe3e2 100644
--- a/drivers/watchdog/sp805_wdt.c
+++ b/drivers/watchdog/sp805_wdt.c
@@ -8,7 +8,6 @@
#include <log.h>
#include <asm/global_data.h>
#include <asm/io.h>
-#include <common.h>
#include <clk.h>
#include <dm/device.h>
#include <dm/fdtaddr.h>
diff --git a/drivers/watchdog/stm32mp_wdt.c b/drivers/watchdog/stm32mp_wdt.c
index 7ebcd25..97ab8cf 100644
--- a/drivers/watchdog/stm32mp_wdt.c
+++ b/drivers/watchdog/stm32mp_wdt.c
@@ -5,7 +5,6 @@
#define LOG_CATEGORY UCLASS_WDT
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <log.h>
diff --git a/drivers/watchdog/tangier_wdt.c b/drivers/watchdog/tangier_wdt.c
index bdc6559..8fbfac3 100644
--- a/drivers/watchdog/tangier_wdt.c
+++ b/drivers/watchdog/tangier_wdt.c
@@ -2,7 +2,6 @@
/*
* Copyright (c) 2017 Intel Corporation
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <wdt.h>
diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c
index 0eea04e..83f19dc 100644
--- a/drivers/watchdog/ulp_wdog.c
+++ b/drivers/watchdog/ulp_wdog.c
@@ -3,7 +3,6 @@
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*/
-#include <common.h>
#include <cpu_func.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c
index 417e8d7..c88312e 100644
--- a/drivers/watchdog/wdt-uclass.c
+++ b/drivers/watchdog/wdt-uclass.c
@@ -5,7 +5,6 @@
#define LOG_CATEGORY UCLASS_WDT
-#include <common.h>
#include <cyclic.h>
#include <div64.h>
#include <dm.h>
diff --git a/drivers/watchdog/xilinx_tb_wdt.c b/drivers/watchdog/xilinx_tb_wdt.c
index b38c400..8a8e553 100644
--- a/drivers/watchdog/xilinx_tb_wdt.c
+++ b/drivers/watchdog/xilinx_tb_wdt.c
@@ -8,7 +8,6 @@
* Copyright (c) 2011-2018 Xilinx Inc.
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <wdt.h>
diff --git a/drivers/watchdog/xilinx_wwdt.c b/drivers/watchdog/xilinx_wwdt.c
index 963ab22..41eff1a 100644
--- a/drivers/watchdog/xilinx_wwdt.c
+++ b/drivers/watchdog/xilinx_wwdt.c
@@ -9,7 +9,6 @@
*/
#include <clk.h>
-#include <common.h>
#include <dm.h>
#include <regmap.h>
#include <wdt.h>
diff --git a/drivers/xen/events.c b/drivers/xen/events.c
index 2ebe20d..fa8b13d 100644
--- a/drivers/xen/events.c
+++ b/drivers/xen/events.c
@@ -14,7 +14,6 @@
*
* [1] - http://xenbits.xen.org/gitweb/?p=mini-os.git;a=summary
*/
-#include <common.h>
#include <log.h>
#include <asm/io.h>
diff --git a/drivers/xen/gnttab.c b/drivers/xen/gnttab.c
index 31e96e2..005694a 100644
--- a/drivers/xen/gnttab.c
+++ b/drivers/xen/gnttab.c
@@ -14,7 +14,6 @@
*
* [1] - http://xenbits.xen.org/gitweb/?p=mini-os.git;a=summary
*/
-#include <common.h>
#include <asm/global_data.h>
#include <linux/compiler.h>
#include <log.h>
diff --git a/drivers/xen/hypervisor.c b/drivers/xen/hypervisor.c
index 0b2311b..d28df82 100644
--- a/drivers/xen/hypervisor.c
+++ b/drivers/xen/hypervisor.c
@@ -8,7 +8,6 @@
* Copyright (c) 2005, Grzegorz Milos, gm281@cam.ac.uk,Intel Research Cambridge
* Copyright (c) 2020, EPAM Systems Inc.
*/
-#include <common.h>
#include <cpu_func.h>
#include <log.h>
#include <memalign.h>
diff --git a/drivers/xen/pvblock.c b/drivers/xen/pvblock.c
index 9fc51d2..0e47ffb 100644
--- a/drivers/xen/pvblock.c
+++ b/drivers/xen/pvblock.c
@@ -7,7 +7,6 @@
#define LOG_CATEGORY UCLASS_PVBLOCK
#include <blk.h>
-#include <common.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <malloc.h>
diff --git a/drivers/xen/xenbus.c b/drivers/xen/xenbus.c
index 177d144..36de525 100644
--- a/drivers/xen/xenbus.c
+++ b/drivers/xen/xenbus.c
@@ -15,7 +15,6 @@
* [1] - http://xenbits.xen.org/gitweb/?p=mini-os.git;a=summary
*/
-#include <common.h>
#include <log.h>
#include <asm/armv8/mmu.h>
diff --git a/env/ext4.c b/env/ext4.c
index eb16568..d92c844 100644
--- a/env/ext4.c
+++ b/env/ext4.c
@@ -31,6 +31,7 @@
#include <ext4fs.h>
#include <mmc.h>
#include <scsi.h>
+#include <virtio.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -150,6 +151,10 @@
if (!strcmp(ifname, "scsi"))
scsi_scan(true);
#endif
+#if defined(CONFIG_VIRTIO)
+ if (!strcmp(ifname, "virtio"))
+ virtio_init();
+#endif
part = blk_get_device_part_str(ifname, dev_and_part,
&dev_desc, &info, 1);
diff --git a/env/fat.c b/env/fat.c
index 2a40f12..f3f8b73 100644
--- a/env/fat.c
+++ b/env/fat.c
@@ -17,6 +17,7 @@
#include <fat.h>
#include <mmc.h>
#include <scsi.h>
+#include <virtio.h>
#include <asm/cache.h>
#include <asm/global_data.h>
#include <linux/stddef.h>
@@ -133,6 +134,10 @@
if (!strcmp(CONFIG_ENV_FAT_INTERFACE, "scsi"))
scsi_scan(true);
#endif
+#if defined(CONFIG_VIRTIO)
+ if (!strcmp(ifname, "virtio"))
+ virtio_init();
+#endif
#endif
part = blk_get_device_part_str(ifname, dev_and_part,
&dev_desc, &info, 1);
diff --git a/examples/api/demo.c b/examples/api/demo.c
index d586174..677d13b 100644
--- a/examples/api/demo.c
+++ b/examples/api/demo.c
@@ -5,7 +5,7 @@
* Written by: Rafal Jaworowski <raj@semihalf.com>
*/
-#include <common.h>
+#include <stdio.h>
#include <env.h>
#include <linux/types.h>
#include <api_public.h>
diff --git a/examples/api/glue.c b/examples/api/glue.c
index 075d307..08c21a8 100644
--- a/examples/api/glue.c
+++ b/examples/api/glue.c
@@ -3,7 +3,6 @@
* (C) Copyright 2007-2008 Semihalf, Rafal Jaworowski <raj@semihalf.com>
*/
-#include <common.h>
#include <env.h>
#include <linux/types.h>
#include <api_public.h>
diff --git a/examples/api/libgenwrap.c b/examples/api/libgenwrap.c
index 3aa2228..bfd88e1 100644
--- a/examples/api/libgenwrap.c
+++ b/examples/api/libgenwrap.c
@@ -9,7 +9,6 @@
* existing code e.g. operations on strings and similar.
*/
-#include <common.h>
#include <command.h>
#include <hang.h>
#include <linux/delay.h>
diff --git a/examples/standalone/atmel_df_pow2.c b/examples/standalone/atmel_df_pow2.c
index dcb25da..ed0d7ae 100644
--- a/examples/standalone/atmel_df_pow2.c
+++ b/examples/standalone/atmel_df_pow2.c
@@ -6,7 +6,6 @@
* Licensed under the 2-clause BSD.
*/
-#include <common.h>
#include <exports.h>
#include <spi.h>
#include <linux/delay.h>
diff --git a/examples/standalone/sched.c b/examples/standalone/sched.c
index 1c52960..d507163 100644
--- a/examples/standalone/sched.c
+++ b/examples/standalone/sched.c
@@ -1,6 +1,5 @@
// SPDX-License-Identifier: GPL-2.0+
-#include <common.h>
#include <exports.h>
/*
diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c
index 6511557..04e8acb 100644
--- a/examples/standalone/stubs.c
+++ b/examples/standalone/stubs.c
@@ -1,4 +1,3 @@
-#include <common.h>
#include <exports.h>
#include <linux/compiler.h>
diff --git a/fs/zfs/zfs.c b/fs/zfs/zfs.c
index c44e7ec..9906d55 100644
--- a/fs/zfs/zfs.c
+++ b/fs/zfs/zfs.c
@@ -16,6 +16,7 @@
#include <linux/time.h>
#include <linux/ctype.h>
#include <asm/byteorder.h>
+#include <u-boot/zlib.h>
#include "zfs_common.h"
#include "div64.h"
@@ -182,7 +183,8 @@
zlib_decompress(void *s, void *d,
uint32_t slen, uint32_t dlen)
{
- if (zlib_decompress(s, d, slen, dlen) < 0)
+ uLongf z_dest_len = dlen;
+ if (uncompress(d, &z_dest_len, s, slen) != Z_OK)
return ZFS_ERR_BAD_FS;
return ZFS_ERR_NONE;
}
@@ -333,6 +335,12 @@
return 0;
}
+static inline int
+is_supported_spa_version(uint64_t version) {
+ return version == FEATURES_SUPPORTED_SPA_VERSION ||
+ (version > 0 && version <= SPA_VERSION);
+}
+
/*
* Three pieces of information are needed to verify an uberblock: the magic
* number, the version number, and the checksum.
@@ -354,14 +362,12 @@
return ZFS_ERR_BAD_FS;
}
- if (zfs_to_cpu64(uber->ub_magic, LITTLE_ENDIAN) == UBERBLOCK_MAGIC
- && zfs_to_cpu64(uber->ub_version, LITTLE_ENDIAN) > 0
- && zfs_to_cpu64(uber->ub_version, LITTLE_ENDIAN) <= SPA_VERSION)
+ if (zfs_to_cpu64(uber->ub_magic, LITTLE_ENDIAN) == UBERBLOCK_MAGIC &&
+ is_supported_spa_version(zfs_to_cpu64(uber->ub_version, LITTLE_ENDIAN)))
endian = LITTLE_ENDIAN;
- if (zfs_to_cpu64(uber->ub_magic, BIG_ENDIAN) == UBERBLOCK_MAGIC
- && zfs_to_cpu64(uber->ub_version, BIG_ENDIAN) > 0
- && zfs_to_cpu64(uber->ub_version, BIG_ENDIAN) <= SPA_VERSION)
+ if (zfs_to_cpu64(uber->ub_magic, BIG_ENDIAN) == UBERBLOCK_MAGIC &&
+ is_supported_spa_version(zfs_to_cpu64(uber->ub_version, BIG_ENDIAN)))
endian = BIG_ENDIAN;
if (endian == UNKNOWN_ENDIAN) {
@@ -1787,7 +1793,7 @@
return ZFS_ERR_BAD_FS;
}
- if (version > SPA_VERSION) {
+ if (!is_supported_spa_version(version)) {
free(nvlist);
printf("SPA version too new %llu > %llu\n",
(unsigned long long) version,
diff --git a/include/api_public.h b/include/api_public.h
index 5a4465e..e89572c 100644
--- a/include/api_public.h
+++ b/include/api_public.h
@@ -8,6 +8,8 @@
#ifndef _API_PUBLIC_H_
#define _API_PUBLIC_H_
+#include <linux/types.h>
+
#define API_EINVAL 1 /* invalid argument(s) */
#define API_ENODEV 2 /* no device */
#define API_ENOMEM 3 /* no memory */
diff --git a/include/common.h b/include/common.h
deleted file mode 100644
index a79c2bb..0000000
--- a/include/common.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Common header file for U-Boot
- *
- * This file still includes quite a few headers that should be included
- * individually as needed. Patches to remove things are welcome.
- *
- * (C) Copyright 2000-2009
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#ifndef __COMMON_H_
-#define __COMMON_H_ 1
-
-#ifndef __ASSEMBLY__ /* put C only stuff in this section */
-#include <config.h>
-#include <errno.h>
-#include <time.h>
-#include <linux/types.h>
-#include <linux/string.h>
-#include <stdarg.h>
-#include <stdio.h>
-#include <linux/kernel.h>
-#include <asm/u-boot.h> /* boot information for Linux kernel */
-#include <vsprintf.h>
-#endif /* __ASSEMBLY__ */
-
-/* Pull in stuff for the build system */
-#ifdef DO_DEPS_ONLY
-# include <env_internal.h>
-#endif
-
-#endif /* __COMMON_H_ */
diff --git a/include/dt-bindings/clock/adi-sc5xx-clock.h b/include/dt-bindings/clock/adi-sc5xx-clock.h
new file mode 100644
index 0000000..4a5373d
--- /dev/null
+++ b/include/dt-bindings/clock/adi-sc5xx-clock.h
@@ -0,0 +1,271 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ * Contact: Greg Malysa <greg.malysa@timesys.com>
+ *
+ */
+
+#ifndef DT_BINDINGS_CLOCK_ADI_SC5XX_CLOCK_H
+#define DT_BINDINGS_CLOCK_ADI_SC5XX_CLOCK_H
+
+//ADSP-SC594
+#define ADSP_SC594_CLK_DUMMY 0
+#define ADSP_SC594_CLK_SYS_CLKIN0 1
+#define ADSP_SC594_CLK_SYS_CLKIN1 2
+#define ADSP_SC594_CLK_CGU1_IN 3
+#define ADSP_SC594_CLK_CGU0_PLL_IN 4
+#define ADSP_SC594_CLK_CGU1_PLL_IN 5
+#define ADSP_SC594_CLK_CGU0_VCO_OUT 6
+#define ADSP_SC594_CLK_CGU1_VCO_OUT 7
+#define ADSP_SC594_CLK_CGU0_PLLCLK 8
+#define ADSP_SC594_CLK_CGU1_PLLCLK 9
+#define ADSP_SC594_CLK_CGU0_CDIV 10
+#define ADSP_SC594_CLK_CGU0_SYSCLK 11
+#define ADSP_SC594_CLK_CGU0_DDIV 12
+#define ADSP_SC594_CLK_CGU0_ODIV 13
+#define ADSP_SC594_CLK_CGU0_S0SELDIV 14
+#define ADSP_SC594_CLK_CGU0_S1SELDIV 15
+#define ADSP_SC594_CLK_CGU0_S1SELEXDIV 16
+#define ADSP_SC594_CLK_CGU0_S1SEL 17
+#define ADSP_SC594_CLK_CGU1_CDIV 18
+#define ADSP_SC594_CLK_CGU1_SYSCLK 19
+#define ADSP_SC594_CLK_CGU1_DDIV 20
+#define ADSP_SC594_CLK_CGU1_ODIV 21
+#define ADSP_SC594_CLK_CGU1_S0SELDIV 22
+#define ADSP_SC594_CLK_CGU1_S1SELDIV 23
+#define ADSP_SC594_CLK_CGU1_S1SELEXDIV 24
+#define ADSP_SC594_CLK_CGU1_S1SEL 25
+#define ADSP_SC594_CLK_CGU0_CCLK0 26
+#define ADSP_SC594_CLK_CGU0_CCLK1 27
+#define ADSP_SC594_CLK_CGU0_OCLK 28
+#define ADSP_SC594_CLK_CGU0_DCLK 29
+#define ADSP_SC594_CLK_CGU0_SCLK1 30
+#define ADSP_SC594_CLK_CGU0_SCLK0 31
+#define ADSP_SC594_CLK_CGU1_CCLK0 32
+#define ADSP_SC594_CLK_CGU1_CCLK1 33
+#define ADSP_SC594_CLK_CGU1_OCLK 34
+#define ADSP_SC594_CLK_CGU1_DCLK 35
+#define ADSP_SC594_CLK_CGU1_SCLK1 36
+#define ADSP_SC594_CLK_CGU1_SCLK0 37
+#define ADSP_SC594_CLK_SHARC0_SEL 38
+#define ADSP_SC594_CLK_SHARC1_SEL 39
+#define ADSP_SC594_CLK_ARM_SEL 40
+#define ADSP_SC594_CLK_CDU_DDR_SEL 41
+#define ADSP_SC594_CLK_CAN_SEL 42
+#define ADSP_SC594_CLK_SPDIF_SEL 43
+#define ADSP_SC594_CLK_RESERVED_SEL 44
+#define ADSP_SC594_CLK_GIGE_SEL 45
+#define ADSP_SC594_CLK_LP_SEL 46
+#define ADSP_SC594_CLK_LPDDR_SEL 47
+#define ADSP_SC594_CLK_OSPI_SEL 48
+#define ADSP_SC594_CLK_TRACE_SEL 49
+#define ADSP_SC594_CLK_SHARC0 50
+#define ADSP_SC594_CLK_SHARC1 51
+#define ADSP_SC594_CLK_ARM 52
+#define ADSP_SC594_CLK_CDU_DDR 53
+#define ADSP_SC594_CLK_CAN 54
+#define ADSP_SC594_CLK_SPDIF 55
+#define ADSP_SC594_CLK_SPI 56
+#define ADSP_SC594_CLK_GIGE 57
+#define ADSP_SC594_CLK_LP 58
+#define ADSP_SC594_CLK_LPDDR 59
+#define ADSP_SC594_CLK_OSPI 60
+#define ADSP_SC594_CLK_TRACE 61
+#define ADSP_SC594_CLK_END 62
+
+//ADSP-SC598
+#define ADSP_SC598_CLK_DUMMY 0
+#define ADSP_SC598_CLK_SYS_CLKIN0 1
+#define ADSP_SC598_CLK_SYS_CLKIN1 2
+#define ADSP_SC598_CLK_CGU0_PLL_IN 3
+#define ADSP_SC598_CLK_CGU0_VCO_OUT 4
+#define ADSP_SC598_CLK_CGU0_PLLCLK 5
+#define ADSP_SC598_CLK_CGU1_IN 6
+#define ADSP_SC598_CLK_CGU1_PLL_IN 7
+#define ADSP_SC598_CLK_CGU1_VCO_OUT 8
+#define ADSP_SC598_CLK_CGU1_PLLCLK 9
+#define ADSP_SC598_CLK_CGU0_CDIV 10
+#define ADSP_SC598_CLK_CGU0_SYSCLK 11
+#define ADSP_SC598_CLK_CGU0_DDIV 12
+#define ADSP_SC598_CLK_CGU0_ODIV 13
+#define ADSP_SC598_CLK_CGU0_S0SELDIV 14
+#define ADSP_SC598_CLK_CGU0_S1SELDIV 15
+#define ADSP_SC598_CLK_CGU0_S1SELEXDIV 16
+#define ADSP_SC598_CLK_CGU0_S1SEL 17
+#define ADSP_SC598_CLK_CGU1_CDIV 18
+#define ADSP_SC598_CLK_CGU1_SYSCLK 19
+#define ADSP_SC598_CLK_CGU1_DDIV 20
+#define ADSP_SC598_CLK_CGU1_ODIV 21
+#define ADSP_SC598_CLK_CGU1_S0SELDIV 22
+#define ADSP_SC598_CLK_CGU1_S1SELDIV 23
+#define ADSP_SC598_CLK_CGU1_S0SELEXDIV 24
+#define ADSP_SC598_CLK_CGU1_S1SELEXDIV 25
+#define ADSP_SC598_CLK_CGU1_S0SEL 26
+#define ADSP_SC598_CLK_CGU1_S1SEL 27
+#define ADSP_SC598_CLK_CGU0_CCLK2 28
+#define ADSP_SC598_CLK_CGU0_CCLK0 29
+#define ADSP_SC598_CLK_CGU0_OCLK 30
+#define ADSP_SC598_CLK_CGU0_DCLK 31
+#define ADSP_SC598_CLK_CGU0_SCLK1 32
+#define ADSP_SC598_CLK_CGU0_SCLK0 33
+#define ADSP_SC598_CLK_CGU1_CCLK0 34
+#define ADSP_SC598_CLK_CGU1_OCLK 35
+#define ADSP_SC598_CLK_CGU1_DCLK 36
+#define ADSP_SC598_CLK_CGU1_SCLK1 37
+#define ADSP_SC598_CLK_CGU1_SCLK0 38
+#define ADSP_SC598_CLK_CGU1_CCLK2 39
+#define ADSP_SC598_CLK_DCLK0_HALF 40
+#define ADSP_SC598_CLK_DCLK1_HALF 41
+#define ADSP_SC598_CLK_CGU1_SCLK1_HALF 42
+#define ADSP_SC598_CLK_SHARC0_SEL 43
+#define ADSP_SC598_CLK_SHARC1_SEL 44
+#define ADSP_SC598_CLK_ARM_SEL 45
+#define ADSP_SC598_CLK_CDU_DDR_SEL 46
+#define ADSP_SC598_CLK_CAN_SEL 47
+#define ADSP_SC598_CLK_SPDIF_SEL 48
+#define ADSP_SC598_CLK_SPI_SEL 49
+#define ADSP_SC598_CLK_GIGE_SEL 50
+#define ADSP_SC598_CLK_LP_SEL 51
+#define ADSP_SC598_CLK_LP_DDR_SEL 52
+#define ADSP_SC598_CLK_OSPI_REFCLK_SEL 53
+#define ADSP_SC598_CLK_TRACE_SEL 54
+#define ADSP_SC598_CLK_EMMC_SEL 55
+#define ADSP_SC598_CLK_EMMC_TIMER_QMC_SEL 56
+#define ADSP_SC598_CLK_SHARC0 57
+#define ADSP_SC598_CLK_SHARC1 58
+#define ADSP_SC598_CLK_ARM 59
+#define ADSP_SC598_CLK_CDU_DDR 60
+#define ADSP_SC598_CLK_CAN 61
+#define ADSP_SC598_CLK_SPDIF 62
+#define ADSP_SC598_CLK_SPI 63
+#define ADSP_SC598_CLK_GIGE 64
+#define ADSP_SC598_CLK_LP 65
+#define ADSP_SC598_CLK_LP_DDR 66
+#define ADSP_SC598_CLK_OSPI_REFCLK 67
+#define ADSP_SC598_CLK_TRACE 68
+#define ADSP_SC598_CLK_EMMC 69
+#define ADSP_SC598_CLK_EMMC_TIMER_QMC 70
+#define ADSP_SC598_CLK_3PLL_PLL_IN 71
+#define ADSP_SC598_CLK_3PLL_VCO_OUT 72
+#define ADSP_SC598_CLK_3PLL_PLLCLK 73
+#define ADSP_SC598_CLK_3PLL_DDIV 74
+#define ADSP_SC598_CLK_DDR 75
+#define ADSP_SC598_CLK_END 76
+
+//ADSP-SC58X
+#define ADSP_SC58X_CLK_DUMMY 0
+#define ADSP_SC58X_CLK_SYS_CLKIN0 1
+#define ADSP_SC58X_CLK_SYS_CLKIN1 2
+#define ADSP_SC58X_CLK_CGU0_PLL_IN 3
+#define ADSP_SC58X_CLK_CGU0_VCO_OUT 4
+#define ADSP_SC58X_CLK_CGU0_PLLCLK 5
+#define ADSP_SC58X_CLK_CGU1_IN 6
+#define ADSP_SC58X_CLK_CGU1_PLL_IN 7
+#define ADSP_SC58X_CLK_CGU1_VCO_OUT 8
+#define ADSP_SC58X_CLK_CGU1_PLLCLK 9
+#define ADSP_SC58X_CLK_CGU0_CDIV 10
+#define ADSP_SC58X_CLK_CGU0_SYSCLK 11
+#define ADSP_SC58X_CLK_CGU0_DDIV 12
+#define ADSP_SC58X_CLK_CGU0_ODIV 13
+#define ADSP_SC58X_CLK_CGU0_S0SELDIV 14
+#define ADSP_SC58X_CLK_CGU0_S1SELDIV 15
+#define ADSP_SC58X_CLK_CGU1_CDIV 16
+#define ADSP_SC58X_CLK_CGU1_SYSCLK 17
+#define ADSP_SC58X_CLK_CGU1_DDIV 18
+#define ADSP_SC58X_CLK_CGU1_ODIV 19
+#define ADSP_SC58X_CLK_CGU1_S0SELDIV 20
+#define ADSP_SC58X_CLK_CGU1_S1SELDIV 21
+#define ADSP_SC58X_CLK_CGU0_CCLK0 22
+#define ADSP_SC58X_CLK_CGU0_CCLK1 23
+#define ADSP_SC58X_CLK_CGU0_OCLK 24
+#define ADSP_SC58X_CLK_CGU0_DCLK 25
+#define ADSP_SC58X_CLK_CGU0_SCLK1 26
+#define ADSP_SC58X_CLK_CGU0_SCLK0 27
+#define ADSP_SC58X_CLK_CGU1_CCLK0 28
+#define ADSP_SC58X_CLK_CGU1_CCLK1 29
+#define ADSP_SC58X_CLK_CGU1_OCLK 30
+#define ADSP_SC58X_CLK_CGU1_DCLK 31
+#define ADSP_SC58X_CLK_CGU1_SCLK1 32
+#define ADSP_SC58X_CLK_CGU1_SCLK0 33
+#define ADSP_SC58X_CLK_OCLK0_HALF 34
+#define ADSP_SC58X_CLK_CCLK1_1_HALF 35
+#define ADSP_SC58X_CLK_SHARC0_SEL 36
+#define ADSP_SC58X_CLK_SHARC1_SEL 37
+#define ADSP_SC58X_CLK_ARM_SEL 38
+#define ADSP_SC58X_CLK_CDU_DDR_SEL 39
+#define ADSP_SC58X_CLK_CAN_SEL 40
+#define ADSP_SC58X_CLK_SPDIF_SEL 41
+#define ADSP_SC58X_CLK_RESERVED_SEL 42
+#define ADSP_SC58X_CLK_GIGE_SEL 43
+#define ADSP_SC58X_CLK_LP_SEL 44
+#define ADSP_SC58X_CLK_SDIO_SEL 45
+#define ADSP_SC58X_CLK_SHARC0 46
+#define ADSP_SC58X_CLK_SHARC1 47
+#define ADSP_SC58X_CLK_ARM 48
+#define ADSP_SC58X_CLK_CDU_DDR 49
+#define ADSP_SC58X_CLK_CAN 50
+#define ADSP_SC58X_CLK_SPDIF 51
+#define ADSP_SC58X_CLK_RESERVED 52
+#define ADSP_SC58X_CLK_GIGE 53
+#define ADSP_SC58X_CLK_LP 54
+#define ADSP_SC58X_CLK_SDIO 55
+#define ADSP_SC58X_CLK_END 56
+
+//ADSP-SC57X
+#define ADSP_SC57X_CLK_DUMMY 0
+#define ADSP_SC57X_CLK_SYS_CLKIN0 1
+#define ADSP_SC57X_CLK_SYS_CLKIN1 2
+#define ADSP_SC57X_CLK_CGU0_PLL_IN 3
+#define ADSP_SC57X_CLK_CGU0_PLLCLK 4
+#define ADSP_SC57X_CLK_CGU1_IN 5
+#define ADSP_SC57X_CLK_CGU1_PLL_IN 6
+#define ADSP_SC57X_CLK_CGU1_PLLCLK 7
+#define ADSP_SC57X_CLK_CGU0_CDIV 8
+#define ADSP_SC57X_CLK_CGU0_SYSCLK 9
+#define ADSP_SC57X_CLK_CGU0_DDIV 10
+#define ADSP_SC57X_CLK_CGU0_ODIV 11
+#define ADSP_SC57X_CLK_CGU0_S0SELDIV 12
+#define ADSP_SC57X_CLK_CGU0_S1SELDIV 13
+#define ADSP_SC57X_CLK_CGU1_CDIV 14
+#define ADSP_SC57X_CLK_CGU1_SYSCLK 15
+#define ADSP_SC57X_CLK_CGU1_DDIV 16
+#define ADSP_SC57X_CLK_CGU1_ODIV 17
+#define ADSP_SC57X_CLK_CGU1_S0SELDIV 18
+#define ADSP_SC57X_CLK_CGU1_S1SELDIV 19
+#define ADSP_SC57X_CLK_CGU0_CCLK0 20
+#define ADSP_SC57X_CLK_CGU0_CCLK1 21
+#define ADSP_SC57X_CLK_CGU0_OCLK 22
+#define ADSP_SC57X_CLK_CGU0_DCLK 23
+#define ADSP_SC57X_CLK_CGU0_SCLK1 24
+#define ADSP_SC57X_CLK_CGU0_SCLK0 25
+#define ADSP_SC57X_CLK_CGU1_CCLK0 26
+#define ADSP_SC57X_CLK_CGU1_CCLK1 27
+#define ADSP_SC57X_CLK_CGU1_OCLK 28
+#define ADSP_SC57X_CLK_CGU1_DCLK 29
+#define ADSP_SC57X_CLK_CGU1_SCLK1 30
+#define ADSP_SC57X_CLK_CGU1_SCLK0 31
+#define ADSP_SC57X_CLK_OCLK0_HALF 32
+#define ADSP_SC57X_CLK_CCLK1_1_HALF 33
+#define ADSP_SC57X_CLK_SHARC0_SEL 34
+#define ADSP_SC57X_CLK_SHARC1_SEL 35
+#define ADSP_SC57X_CLK_ARM_SEL 36
+#define ADSP_SC57X_CLK_CDU_DDR_SEL 37
+#define ADSP_SC57X_CLK_CAN_SEL 38
+#define ADSP_SC57X_CLK_SPDIF_SEL 39
+#define ADSP_SC57X_CLK_GIGE_SEL 40
+#define ADSP_SC57X_CLK_SDIO_SEL 41
+#define ADSP_SC57X_CLK_SHARC0 42
+#define ADSP_SC57X_CLK_SHARC1 43
+#define ADSP_SC57X_CLK_ARM 44
+#define ADSP_SC57X_CLK_CDU_DDR 45
+#define ADSP_SC57X_CLK_CAN 46
+#define ADSP_SC57X_CLK_SPDIF 47
+#define ADSP_SC57X_CLK_GIGE 48
+#define ADSP_SC57X_CLK_SDIO 49
+#define ADSP_SC57X_CLK_END 50
+
+#endif
diff --git a/include/env/adi/adi_boot.env b/include/env/adi/adi_boot.env
new file mode 100644
index 0000000..d56b14f
--- /dev/null
+++ b/include/env/adi/adi_boot.env
@@ -0,0 +1,122 @@
+/*
+ * A target board needs to set these variables for the commands below to work:
+ *
+ * - adi_stage2_offset, the location of stage2-boot.ldr on the SPI flash
+ * - adi_image_offset, location of the fitImage on the SPI flash
+ * - adi_rfs_offset, location of the RFS on the SPI flash
+ * - loadaddr, where you want to load things
+ * - jffs2file, name of the jffs2 file for update, ex adsp-sc5xx-tiny-adsp-sc573.jffs2
+ */
+
+#ifdef CONFIG_SC59X_64
+#define EARLY_PRINTK earlycon=adi_uart,0x31003000
+#else
+#define EARLY_PRINTK earlyprintk=serial,uart0,CONFIG_BAUDRATE
+#endif
+
+/* Config options */
+imagefile=fitImage
+ethaddr=02:80:ad:20:31:e8
+eth1addr=02:80:ad:20:31:e9
+uart_console=CONFIG_UART_CONSOLE
+#ifdef CONFIG_SC59X_64
+fdt_high=0xffffffffffffffff
+initrd_high=0xffffffffffffffff
+#else
+fdt_high=0xffffffff
+initrd_high=0xffffffff
+#endif
+
+/* Helper routines */
+init_ethernet=mii info;
+ dhcp;
+ setenv serverip ${tftpserverip}
+
+/* Args for each boot mode */
+adi_bootargs=EARLY_PRINTK console=ttySC0,CONFIG_BAUDRATE vmalloc=512M
+ramargs=setenv bootargs ${adi_bootargs}
+
+addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off
+
+/* Boot modes are selectable and should be defined in the board env before including */
+#if defined(USE_NFS)
+// rootpath is set by CONFIG_ROOTPATH
+nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}${rootpath},tcp,nfsvers=3 ${adi_bootargs}
+nfsboot=run init_ethernet;
+ tftp ${loadaddr} ${tftp_dir_prefix}${imagefile};
+ run nfsargs;
+ run addip;
+ bootm ${loadaddr}
+#endif
+
+#if defined(USE_MMC)
+mmcargs=setenv bootargs root=/dev/mmcblk0p1 rw rootfstype=ext4 rootwait ${adi_bootargs}
+mmcboot=mmc rescan;
+ ext4load mmc 0:1 ${loadaddr} /boot/${imagefile};
+ run mmcargs;
+ bootm ${loadaddr}
+#endif
+
+#if defined(USE_SPI) || defined(USE_OSPI)
+spiargs=setenv bootargs root=/dev/mtdblock4 rw rootfstype=jffs2 ${adi_bootargs}
+spiboot=run spiargs;
+ sf probe ${sfdev};
+ sf read ${loadaddr} ${adi_image_offset} ${imagesize};
+ bootm ${loadaddr}
+#endif
+
+#if defined(USE_OSPI)
+ospiboot=run spiboot
+#endif
+
+#if defined(USE_RAM)
+ramboot=run init_ethernet;
+ tftp ${loadaddr} ${tfpt_dir_prefix}${imagefile};
+ run ramargs;
+ bootm ${loadaddr}
+#endif
+
+/* Update commands */
+stage1file=stage1-boot.ldr
+stage2file=stage2-boot.ldr
+
+#if defined(USE_SPI) || defined(USE_OSPI)
+update_spi_uboot_stage1=tftp ${loadaddr} ${tftp_dir_prefix}${stage1file};
+ sf probe ${sfdev};
+ sf update ${loadaddr} 0x0 ${filesize}
+update_spi_uboot_stage2=tftp ${loadaddr} ${tftp_dir_prefix}${stage2file};
+ sf probe ${sfdev};
+ sf update ${loadaddr} ${adi_stage2_offset} ${filesize}
+update_spi_uboot=run update_spi_uboot_stage1;
+ run update_spi_uboot_stage2;
+update_spi_fit=tftp ${loadaddr} ${tftp_dir_prefix}${imagefile};
+ sf probe ${sfdev};
+ sf update ${loadaddr} ${adi_image_offset} ${filesize};
+ setenv imagesize ${filesize}
+update_spi_rfs=tftp ${loadaddr} ${tftp_dir_prefix}${jffs2file};
+ sf probe ${sfdev};
+ sf update ${loadaddr} ${adi_rfs_offset} ${filesize}
+
+start_update_spi=run init_ethernet;
+ run update_spi_uboot;
+ run update_spi_fit;
+ run update_spi_rfs;
+start_update_spi_uboot_only=run init_ethernet;
+ run update_spi_uboot;
+#endif
+
+#if defined(USE_SPI)
+update_spi=setenv sfdev CONFIG_SC_BOOT_SPI_BUS:CONFIG_SC_BOOT_SPI_SSEL;
+ setenv bootcmd run spiboot;
+ setenv argscmd spiargs;
+ run start_update_spi;
+ saveenv
+#endif
+
+#if defined(USE_OSPI)
+update_ospi=setenv sfdev CONFIG_SC_BOOT_OSPI_BUS:CONFIG_SC_BOOT_OSPI_SSEL;
+ setenv bootcmd run ospiboot;
+ setenv argscmd spiargs;
+ run start_update_spi;
+ saveenv
+#endif
diff --git a/include/virtio.h b/include/virtio.h
index 062a246..17f894a 100644
--- a/include/virtio.h
+++ b/include/virtio.h
@@ -21,8 +21,10 @@
#define __VIRTIO_H__
#include <virtio_types.h>
+#include <dm/device.h>
#include <linux/bitops.h>
#include <linux/bug.h>
+#include <linux/typecheck.h>
#define VIRTIO_ID_NET 1 /* virtio net */
#define VIRTIO_ID_BLOCK 2 /* virtio block */
#define VIRTIO_ID_RNG 4 /* virtio rng */
diff --git a/include/xen/events.h b/include/xen/events.h
index 82bd18b..f0a8ef3 100644
--- a/include/xen/events.h
+++ b/include/xen/events.h
@@ -15,6 +15,7 @@
#ifndef _EVENTS_H_
#define _EVENTS_H_
+#include <asm/ptrace.h>
#include <asm/xen/hypercall.h>
#include <xen/interface/event_channel.h>
diff --git a/include/zfs/zfs.h b/include/zfs/zfs.h
index 17b93c1..72d8745 100644
--- a/include/zfs/zfs.h
+++ b/include/zfs/zfs.h
@@ -15,6 +15,7 @@
* On-disk version number.
*/
#define SPA_VERSION 28ULL
+#define FEATURES_SUPPORTED_SPA_VERSION 5000ULL
/*
* The following are configuration names used in the nvlist describing a pool's
diff --git a/scripts/Makefile.autoconf b/scripts/Makefile.autoconf
index 8208ffe..b42f9b5 100644
--- a/scripts/Makefile.autoconf
+++ b/scripts/Makefile.autoconf
@@ -45,7 +45,7 @@
quiet_cmd_autoconf_dep = GEN $@
cmd_autoconf_dep = $(CC) -x c -DDO_DEPS_ONLY -M -MP $(c_flags) \
- -MQ include/config/auto.conf $(srctree)/include/common.h > $@ || { \
+ -MQ include/config/auto.conf include/config.h > $@ || { \
rm $@; false; \
}
include/autoconf.mk.dep: include/config.h FORCE
@@ -70,7 +70,7 @@
quiet_cmd_u_boot_cfg = CFG $@
cmd_u_boot_cfg = \
- $(CPP) $(c_flags) $2 -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && { \
+ $(CPP) $(c_flags) $2 -DDO_DEPS_ONLY -dM include/config.h > $@.tmp && { \
grep 'define CONFIG_' $@.tmp | \
sed '/define CONFIG_IS_ENABLED(/d;/define CONFIG_IF_ENABLED_INT(/d;/define CONFIG_VAL(/d;' > $@; \
rm $@.tmp; \
diff --git a/scripts/gen_compile_commands.py b/scripts/gen_compile_commands.py
index fec513e..e746add 100755
--- a/scripts/gen_compile_commands.py
+++ b/scripts/gen_compile_commands.py
@@ -172,7 +172,7 @@
# escape the pound sign '#', either as '\#' or '$(pound)' (depending on the
# kernel version). The compile_commands.json file is not interepreted
# by Make, so this code replaces the escaped version with '#'.
- prefix = command_prefix.replace('\#', '#').replace('$(pound)', '#')
+ prefix = command_prefix.replace(r'\#', '#').replace('$(pound)', '#')
# Return the canonical path, eliminating any symbolic links encountered in the path.
abs_path = os.path.realpath(os.path.join(root_directory, file_path))
diff --git a/scripts/gen_ll_addressable_symbols.sh b/scripts/gen_ll_addressable_symbols.sh
index d086480..13f670a 100755
--- a/scripts/gen_ll_addressable_symbols.sh
+++ b/scripts/gen_ll_addressable_symbols.sh
@@ -10,6 +10,6 @@
set -e
-echo '#include <common.h>'
+echo '#include <linux/compiler.h>'
$@ 2>/dev/null | grep -oe '_u_boot_list_2_[a-zA-Z0-9_]*_2_[a-zA-Z0-9_]*' | \
sort -u | sed -e 's/^\(.*\)/extern char \1[];\n__ADDRESSABLE(\1);/'
diff --git a/test/py/u_boot_console_base.py b/test/py/u_boot_console_base.py
index 26b6de0..3e01be1 100644
--- a/test/py/u_boot_console_base.py
+++ b/test/py/u_boot_console_base.py
@@ -17,7 +17,6 @@
# Regexes for text we expect U-Boot to send to the console.
pattern_u_boot_spl_signon = re.compile('(U-Boot SPL \\d{4}\\.\\d{2}[^\r\n]*\\))')
-pattern_u_boot_spl2_signon = re.compile('(U-Boot SPL \\d{4}\\.\\d{2}[^\r\n]*\\))')
pattern_u_boot_main_signon = re.compile('(U-Boot \\d{4}\\.\\d{2}[^\r\n]*\\))')
pattern_stop_autoboot_prompt = re.compile('Hit any key to stop autoboot: ')
pattern_unknown_command = re.compile('Unknown command \'.*\' - try \'help\'')
@@ -29,7 +28,6 @@
bad_pattern_defs = (
('spl_signon', pattern_u_boot_spl_signon),
- ('spl2_signon', pattern_u_boot_spl2_signon),
('main_signon', pattern_u_boot_main_signon),
('stop_autoboot_prompt', pattern_stop_autoboot_prompt),
('unknown_command', pattern_unknown_command),
@@ -152,25 +150,20 @@
"""
try:
bcfg = self.config.buildconfig
- config_spl = bcfg.get('config_spl', 'n') == 'y'
config_spl_serial = bcfg.get('config_spl_serial', 'n') == 'y'
env_spl_skipped = self.config.env.get('env__spl_skipped', False)
- env_spl2_skipped = self.config.env.get('env__spl2_skipped', True)
+ env_spl_banner_times = self.config.env.get('env__spl_banner_times', 1)
while loop_num > 0:
loop_num -= 1
- if config_spl and config_spl_serial and not env_spl_skipped:
+ while config_spl_serial and not env_spl_skipped and env_spl_banner_times > 0:
m = self.p.expect([pattern_u_boot_spl_signon] +
self.bad_patterns)
if m != 0:
raise Exception('Bad pattern found on SPL console: ' +
self.bad_pattern_ids[m - 1])
- if not env_spl2_skipped:
- m = self.p.expect([pattern_u_boot_spl2_signon] +
- self.bad_patterns)
- if m != 0:
- raise Exception('Bad pattern found on SPL2 console: ' +
- self.bad_pattern_ids[m - 1])
+ env_spl_banner_times -= 1
+
m = self.p.expect([pattern_u_boot_main_signon] + self.bad_patterns)
if m != 0:
raise Exception('Bad pattern found on console: ' +
diff --git a/tools/dtoc/dtb_platdata.py b/tools/dtoc/dtb_platdata.py
index 39f416c..89066e6 100644
--- a/tools/dtoc/dtb_platdata.py
+++ b/tools/dtoc/dtb_platdata.py
@@ -835,7 +835,6 @@
def generate_uclasses(self):
self.out('\n')
- self.out('#include <common.h>\n')
self.out('#include <dm.h>\n')
self.out('#include <dt-structs.h>\n')
self.out('\n')
@@ -1059,7 +1058,6 @@
self.out('/* Allow use of U_BOOT_DRVINFO() in this file */\n')
self.out('#define DT_PLAT_C\n')
self.out('\n')
- self.out('#include <common.h>\n')
self.out('#include <dm.h>\n')
self.out('#include <dt-structs.h>\n')
self.out('\n')
@@ -1092,7 +1090,6 @@
See the documentation in doc/driver-model/of-plat.rst for more
information.
"""
- self.out('#include <common.h>\n')
self.out('#include <dm.h>\n')
self.out('#include <dt-structs.h>\n')
self.out('\n')
diff --git a/tools/dtoc/test_dtoc.py b/tools/dtoc/test_dtoc.py
index 597c93e..c4a0889 100755
--- a/tools/dtoc/test_dtoc.py
+++ b/tools/dtoc/test_dtoc.py
@@ -63,7 +63,6 @@
/* Allow use of U_BOOT_DRVINFO() in this file */
#define DT_PLAT_C
-#include <common.h>
#include <dm.h>
#include <dt-structs.h>
'''
@@ -417,7 +416,6 @@
'''
uclass_text_inst = '''
-#include <common.h>
#include <dm.h>
#include <dt-structs.h>
@@ -521,7 +519,6 @@
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
-#include <common.h>
#include <dm.h>
#include <dt-structs.h>