diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 4b0c3df..ec651fe 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -179,6 +179,11 @@
 	  The SiFive CLINT block holds memory-mapped control and status registers
 	  associated with software and timer interrupts.
 
+config SIFIVE_CACHE
+	bool
+	help
+	  This enables the operations to configure SiFive cache
+
 config ANDES_PLIC
 	bool
 	depends on RISCV_MMODE || SPL_RISCV_MMODE