diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c
index 5d7aba4..badc569 100644
--- a/arch/arm/cpu/armv7/socfpga/reset_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c
@@ -49,3 +49,20 @@
 {
 	writel(0, &reset_manager_base->per_mod_reset);
 }
+
+/* Change the reset state for EMAC 0 and EMAC 1 */
+void socfpga_emac_reset(int enable)
+{
+	const void *reset = &reset_manager_base->per_mod_reset;
+
+	if (enable) {
+		setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB);
+		setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB);
+	} else {
+#if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS)
+		clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB);
+#elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS)
+		clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB);
+#endif
+	}
+}
diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h
index 18506e6..3c5ab40 100644
--- a/arch/arm/include/asm/arch-socfpga/reset_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h
@@ -10,6 +10,7 @@
 void reset_cpu(ulong addr);
 void reset_deassert_peripherals_handoff(void);
 
+void socfpga_emac_reset(int enable);
 void socfpga_watchdog_reset(void);
 
 struct socfpga_reset_manager {
@@ -29,6 +30,8 @@
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
 #endif
 
+#define RSTMGR_PERMODRST_EMAC0_LSB	0
+#define RSTMGR_PERMODRST_EMAC1_LSB	1
 #define RSTMGR_PERMODRST_L4WD0_LSB	6
 
 #endif /* _RESET_MANAGER_H_ */