| commit | b5c087b4f1f9c73433e49a3c652e88855208d9cf | [log] [tgz] |
|---|---|---|
| author | Marek Vasut <marex@denx.de> | Tue May 08 18:44:43 2018 +0200 |
| committer | Marek Vasut <marex@denx.de> | Sat Mar 09 17:59:14 2019 +0100 |
| tree | 1da56b2c374dbf3a72806923ffcd040b510ca95b | |
| parent | bb6e32a30c925c60201f5ac7964e1c2d82591c92 [diff] |
ARM: socfpga: Fix Arria10 SPI and NAND U-Boot offset The SPL size on Gen5 is 4*64kiB, but on A10 it is 4*256kiB. Handle the difference. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>