diff --git a/.travis.yml b/.travis.yml
index a061f02..ed07d81 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -42,7 +42,7 @@
  - ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
  # prepare buildman environment
  - echo -e "[toolchain]\nroot = /usr" > ~/.buildman
- - echo -e "arc = /tmp/arc_gnu_2017.09_prebuilt_uclibc_le_archs_linux_install" >> ~/.buildman
+ - echo -e "arc = /tmp/arc_gnu_2018.09_prebuilt_uclibc_le_archs_linux_install" >> ~/.buildman
  - echo -e "\n[toolchain-alias]\nsh = sh2\n" >> ~/.buildman
  - cat ~/.buildman
  - virtualenv /tmp/venv
@@ -75,8 +75,8 @@
       echo -e "\n[toolchain-alias]\nx86 = i386" >> ~/.buildman;
     fi
   - if [[ "${TOOLCHAIN}" == arc ]]; then
-       wget https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/download/arc-2017.09-release/arc_gnu_2017.09_prebuilt_uclibc_le_archs_linux_install.tar.gz &&
-       tar -C /tmp -xf arc_gnu_2017.09_prebuilt_uclibc_le_archs_linux_install.tar.gz;
+       wget https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/download/arc-2018.09-release/arc_gnu_2018.09_prebuilt_uclibc_le_archs_linux_install.tar.gz &&
+       tar -C /tmp -xf arc_gnu_2018.09_prebuilt_uclibc_le_archs_linux_install.tar.gz;
     fi
   - if [[ "${TOOLCHAIN}" == *xtensa* ]]; then
        wget https://github.com/foss-xtensa/toolchain/releases/download/2018.02/x86_64-2018.02-${TOOLCHAIN}.tar.gz &&
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bec46ce..cb7ec58 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -932,6 +932,7 @@
 	select DM_SERIAL
 	select OF_CONTROL
 	imply CMD_DM
+	imply DM_USB_GADGET
 
 config ARCH_ZYNQMP
 	bool "Xilinx ZynqMP based platform"
@@ -949,6 +950,7 @@
 	imply CMD_DM
 	imply FAT_WRITE
 	imply MP
+	imply DM_USB_GADGET
 
 config TEGRA
 	bool "NVIDIA Tegra"
diff --git a/arch/arm/dts/am335x-evm.dts b/arch/arm/dts/am335x-evm.dts
index a6f20af..fe27207 100644
--- a/arch/arm/dts/am335x-evm.dts
+++ b/arch/arm/dts/am335x-evm.dts
@@ -80,8 +80,6 @@
 
 	gpio_keys: volume_keys@0 {
 		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
 		autorepeat;
 
 		switch@9 {
@@ -723,8 +721,8 @@
 &mmc3 {
 	/* these are on the crossbar and are outlined in the
 	   xbar-event-map element */
-	dmas = <&edma 12
-		&edma 13>;
+	dmas = <&edma 12 0
+		&edma 13 0>;
 	dma-names = "tx", "rx";
 	status = "okay";
 	vmmc-supply = <&wlan_en_reg>;
diff --git a/arch/arm/dts/am335x-evmsk.dts b/arch/arm/dts/am335x-evmsk.dts
index b3e9b61..0767578 100644
--- a/arch/arm/dts/am335x-evmsk.dts
+++ b/arch/arm/dts/am335x-evmsk.dts
@@ -109,8 +109,6 @@
 
 	gpio_buttons: gpio_buttons@0 {
 		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
 
 		switch@1 {
 			label = "button0";
diff --git a/arch/arm/dts/am335x-pdu001-u-boot.dtsi b/arch/arm/dts/am335x-pdu001-u-boot.dtsi
index fbb6a3f..84a07bd 100644
--- a/arch/arm/dts/am335x-pdu001-u-boot.dtsi
+++ b/arch/arm/dts/am335x-pdu001-u-boot.dtsi
@@ -29,10 +29,18 @@
 	u-boot,dm-pre-reloc;
 };
 
+&mmc1 {
+	u-boot,dm-pre-reloc;
+};
+
 &mmc1_pins {
 	u-boot,dm-pre-reloc;
 };
 
+&mmc2 {
+	u-boot,dm-pre-reloc;
+};
+
 &mmc2_pins {
 	u-boot,dm-pre-reloc;
 };
diff --git a/arch/arm/dts/am335x-pdu001.dts b/arch/arm/dts/am335x-pdu001.dts
index 121e2c6..3a5e9526 100644
--- a/arch/arm/dts/am335x-pdu001.dts
+++ b/arch/arm/dts/am335x-pdu001.dts
@@ -576,7 +576,7 @@
 	bus-width = <4>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc2_pins>;
-	cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+	cd-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
 };
 
 &sham {
diff --git a/arch/arm/dts/am335x-pxm2.dtsi b/arch/arm/dts/am335x-pxm2.dtsi
index 8d58cd4..d9243d5 100644
--- a/arch/arm/dts/am335x-pxm2.dtsi
+++ b/arch/arm/dts/am335x-pxm2.dtsi
@@ -50,8 +50,6 @@
 
 	gpio_keys: restart-keys {
 		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
 		autorepeat;
 
 		restart0 {
diff --git a/arch/arm/dts/am335x-rut.dts b/arch/arm/dts/am335x-rut.dts
index c6cfbb8..a5716a9 100644
--- a/arch/arm/dts/am335x-rut.dts
+++ b/arch/arm/dts/am335x-rut.dts
@@ -36,8 +36,6 @@
 
 	gpio_keys: powerfail-keys {
 		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
 		autorepeat;
 
 		pwr-fail0 {
@@ -190,12 +188,8 @@
 
 &epwmss1 {
 	status = "okay";
-
-	ehrpwm1: ehrpwm@48302200 {
-		status = "okay";
-		pinctrl-names = "default";
-		pinctrl-0 = <&epwmss1_pins>;
-	};
+	pinctrl-names = "default";
+	pinctrl-0 = <&epwmss1_pins>;
 };
 
 &gpmc {
diff --git a/arch/arm/dts/am33xx-clocks.dtsi b/arch/arm/dts/am33xx-clocks.dtsi
index afb4b3a..95d5c9d 100644
--- a/arch/arm/dts/am33xx-clocks.dtsi
+++ b/arch/arm/dts/am33xx-clocks.dtsi
@@ -8,7 +8,7 @@
  * published by the Free Software Foundation.
  */
 &scm_clocks {
-	sys_clkin_ck: sys_clkin_ck {
+	sys_clkin_ck: sys_clkin_ck@40 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
@@ -163,7 +163,7 @@
 		clock-frequency = <12000000>;
 	};
 
-	dpll_core_ck: dpll_core_ck {
+	dpll_core_ck: dpll_core_ck@490 {
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-core-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
@@ -176,7 +176,7 @@
 		clocks = <&dpll_core_ck>;
 	};
 
-	dpll_core_m4_ck: dpll_core_m4_ck {
+	dpll_core_m4_ck: dpll_core_m4_ck@480 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -185,7 +185,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_core_m5_ck: dpll_core_m5_ck {
+	dpll_core_m5_ck: dpll_core_m5_ck@484 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -194,7 +194,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_core_m6_ck: dpll_core_m6_ck {
+	dpll_core_m6_ck: dpll_core_m6_ck@4d8 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -203,14 +203,14 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_mpu_ck: dpll_mpu_ck {
+	dpll_mpu_ck: dpll_mpu_ck@488 {
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 		reg = <0x0488>, <0x0420>, <0x042c>;
 	};
 
-	dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+	dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_mpu_ck>;
@@ -219,14 +219,14 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_ddr_ck: dpll_ddr_ck {
+	dpll_ddr_ck: dpll_ddr_ck@494 {
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-no-gate-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 		reg = <0x0494>, <0x0434>, <0x0440>;
 	};
 
-	dpll_ddr_m2_ck: dpll_ddr_m2_ck {
+	dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_ddr_ck>;
@@ -243,14 +243,14 @@
 		clock-div = <2>;
 	};
 
-	dpll_disp_ck: dpll_disp_ck {
+	dpll_disp_ck: dpll_disp_ck@498 {
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-no-gate-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 		reg = <0x0498>, <0x0448>, <0x0454>;
 	};
 
-	dpll_disp_m2_ck: dpll_disp_m2_ck {
+	dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_disp_ck>;
@@ -260,14 +260,14 @@
 		ti,set-rate-parent;
 	};
 
-	dpll_per_ck: dpll_per_ck {
+	dpll_per_ck: dpll_per_ck@48c {
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-no-gate-j-type-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 		reg = <0x048c>, <0x0470>, <0x049c>;
 	};
 
-	dpll_per_m2_ck: dpll_per_m2_ck {
+	dpll_per_m2_ck: dpll_per_m2_ck@4ac {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_ck>;
@@ -292,14 +292,6 @@
 		clock-div = <4>;
 	};
 
-	cefuse_fck: cefuse_fck {
-		#clock-cells = <0>;
-		compatible = "ti,gate-clock";
-		clocks = <&sys_clkin_ck>;
-		ti,bit-shift = <1>;
-		reg = <0x0a20>;
-	};
-
 	clk_24mhz: clk_24mhz {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
@@ -316,14 +308,6 @@
 		clock-div = <732>;
 	};
 
-	clkdiv32k_ick: clkdiv32k_ick {
-		#clock-cells = <0>;
-		compatible = "ti,gate-clock";
-		clocks = <&clkdiv32k_ck>;
-		ti,bit-shift = <1>;
-		reg = <0x014c>;
-	};
-
 	l3_gclk: l3_gclk {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
@@ -332,14 +316,14 @@
 		clock-div = <1>;
 	};
 
-	pruss_ocp_gclk: pruss_ocp_gclk {
+	pruss_ocp_gclk: pruss_ocp_gclk@530 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
 		reg = <0x0530>;
 	};
 
-	mmu_fck: mmu_fck {
+	mmu_fck: mmu_fck@914 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll_core_m4_ck>;
@@ -347,56 +331,56 @@
 		reg = <0x0914>;
 	};
 
-	timer1_fck: timer1_fck {
+	timer1_fck: timer1_fck@528 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
-		clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
+		clocks = <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
 		reg = <0x0528>;
 	};
 
-	timer2_fck: timer2_fck {
+	timer2_fck: timer2_fck@508 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
-		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
 		reg = <0x0508>;
 	};
 
-	timer3_fck: timer3_fck {
+	timer3_fck: timer3_fck@50c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
-		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
 		reg = <0x050c>;
 	};
 
-	timer4_fck: timer4_fck {
+	timer4_fck: timer4_fck@510 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
-		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
 		reg = <0x0510>;
 	};
 
-	timer5_fck: timer5_fck {
+	timer5_fck: timer5_fck@518 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
-		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
 		reg = <0x0518>;
 	};
 
-	timer6_fck: timer6_fck {
+	timer6_fck: timer6_fck@51c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
-		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
 		reg = <0x051c>;
 	};
 
-	timer7_fck: timer7_fck {
+	timer7_fck: timer7_fck@504 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
-		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
 		reg = <0x0504>;
 	};
 
-	usbotg_fck: usbotg_fck {
+	usbotg_fck: usbotg_fck@47c {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll_per_ck>;
@@ -412,7 +396,7 @@
 		clock-div = <2>;
 	};
 
-	ieee5000_fck: ieee5000_fck {
+	ieee5000_fck: ieee5000_fck@e4 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll_core_m4_div2_ck>;
@@ -420,10 +404,10 @@
 		reg = <0x00e4>;
 	};
 
-	wdt1_fck: wdt1_fck {
+	wdt1_fck: wdt1_fck@538 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
-		clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
+		clocks = <&clk_rc32k_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
 		reg = <0x0538>;
 	};
 
@@ -483,53 +467,21 @@
 		clock-div = <2>;
 	};
 
-	cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
+	cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
 		reg = <0x0520>;
 	};
 
-	gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
+	gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
-		clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
+		clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
 		reg = <0x053c>;
 	};
 
-	gpio0_dbclk: gpio0_dbclk {
-		#clock-cells = <0>;
-		compatible = "ti,gate-clock";
-		clocks = <&gpio0_dbclk_mux_ck>;
-		ti,bit-shift = <18>;
-		reg = <0x0408>;
-	};
-
-	gpio1_dbclk: gpio1_dbclk {
-		#clock-cells = <0>;
-		compatible = "ti,gate-clock";
-		clocks = <&clkdiv32k_ick>;
-		ti,bit-shift = <18>;
-		reg = <0x00ac>;
-	};
-
-	gpio2_dbclk: gpio2_dbclk {
-		#clock-cells = <0>;
-		compatible = "ti,gate-clock";
-		clocks = <&clkdiv32k_ick>;
-		ti,bit-shift = <18>;
-		reg = <0x00b0>;
-	};
-
-	gpio3_dbclk: gpio3_dbclk {
-		#clock-cells = <0>;
-		compatible = "ti,gate-clock";
-		clocks = <&clkdiv32k_ick>;
-		ti,bit-shift = <18>;
-		reg = <0x00b4>;
-	};
-
-	lcd_gclk: lcd_gclk {
+	lcd_gclk: lcd_gclk@534 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
@@ -545,7 +497,7 @@
 		clock-div = <2>;
 	};
 
-	gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
+	gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@52c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
@@ -553,7 +505,7 @@
 		reg = <0x052c>;
 	};
 
-	gfx_fck_div_ck: gfx_fck_div_ck {
+	gfx_fck_div_ck: gfx_fck_div_ck@52c {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&gfx_fclk_clksel_ck>;
@@ -561,14 +513,14 @@
 		ti,max-div = <2>;
 	};
 
-	sysclkout_pre_ck: sysclkout_pre_ck {
+	sysclkout_pre_ck: sysclkout_pre_ck@700 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
 		reg = <0x0700>;
 	};
 
-	clkout2_div_ck: clkout2_div_ck {
+	clkout2_div_ck: clkout2_div_ck@700 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&sysclkout_pre_ck>;
@@ -577,70 +529,97 @@
 		reg = <0x0700>;
 	};
 
-	dbg_sysclk_ck: dbg_sysclk_ck {
+	clkout2_ck: clkout2_ck@700 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
-		clocks = <&sys_clkin_ck>;
-		ti,bit-shift = <19>;
-		reg = <0x0414>;
+		clocks = <&clkout2_div_ck>;
+		ti,bit-shift = <7>;
+		reg = <0x0700>;
 	};
+};
 
-	dbg_clka_ck: dbg_clka_ck {
-		#clock-cells = <0>;
-		compatible = "ti,gate-clock";
-		clocks = <&dpll_core_m4_ck>;
-		ti,bit-shift = <30>;
-		reg = <0x0414>;
-	};
+&prcm {
+	l4_per_cm: l4_per_cm@0 {
+		compatible = "ti,omap4-cm";
+		reg = <0x0 0x200>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x0 0x200>;
 
-	stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
-		ti,bit-shift = <22>;
-		reg = <0x0414>;
+		l4_per_clkctrl: clk@14 {
+			compatible = "ti,clkctrl";
+			reg = <0x14 0x13c>;
+			#clock-cells = <2>;
+		};
 	};
 
-	trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
-		ti,bit-shift = <20>;
-		reg = <0x0414>;
+	l4_wkup_cm: l4_wkup_cm@400 {
+		compatible = "ti,omap4-cm";
+		reg = <0x400 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x400 0x100>;
+
+		l4_wkup_clkctrl: clk@4 {
+			compatible = "ti,clkctrl";
+			reg = <0x4 0xd4>;
+			#clock-cells = <2>;
+		};
 	};
 
-	stm_clk_div_ck: stm_clk_div_ck {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&stm_pmd_clock_mux_ck>;
-		ti,bit-shift = <27>;
-		ti,max-div = <64>;
-		reg = <0x0414>;
-		ti,index-power-of-two;
+	mpu_cm: mpu_cm@600 {
+		compatible = "ti,omap4-cm";
+		reg = <0x600 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x600 0x100>;
+
+		mpu_clkctrl: clk@4 {
+			compatible = "ti,clkctrl";
+			reg = <0x4 0x4>;
+			#clock-cells = <2>;
+		};
 	};
 
-	trace_clk_div_ck: trace_clk_div_ck {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&trace_pmd_clk_mux_ck>;
-		ti,bit-shift = <24>;
-		ti,max-div = <64>;
-		reg = <0x0414>;
-		ti,index-power-of-two;
+	l4_rtc_cm: l4_rtc_cm@800 {
+		compatible = "ti,omap4-cm";
+		reg = <0x800 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x800 0x100>;
+
+		l4_rtc_clkctrl: clk@0 {
+			compatible = "ti,clkctrl";
+			reg = <0x0 0x4>;
+			#clock-cells = <2>;
+		};
 	};
 
-	clkout2_ck: clkout2_ck {
-		#clock-cells = <0>;
-		compatible = "ti,gate-clock";
-		clocks = <&clkout2_div_ck>;
-		ti,bit-shift = <7>;
-		reg = <0x0700>;
+	gfx_l3_cm: gfx_l3_cm@900 {
+		compatible = "ti,omap4-cm";
+		reg = <0x900 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x900 0x100>;
+
+		gfx_l3_clkctrl: clk@4 {
+			compatible = "ti,clkctrl";
+			reg = <0x4 0x4>;
+			#clock-cells = <2>;
+		};
 	};
-};
+
+	l4_cefuse_cm: l4_cefuse_cm@a00 {
+		compatible = "ti,omap4-cm";
+		reg = <0xa00 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xa00 0x100>;
 
-&prcm_clockdomains {
-	clk_24mhz_clkdm: clk_24mhz_clkdm {
-		compatible = "ti,clockdomain";
-		clocks = <&clkdiv32k_ick>;
+		l4_cefuse_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x4>;
+			#clock-cells = <2>;
+		};
 	};
 };
diff --git a/arch/arm/dts/am33xx.dtsi b/arch/arm/dts/am33xx.dtsi
index 4234537..d3dd6a1 100644
--- a/arch/arm/dts/am33xx.dtsi
+++ b/arch/arm/dts/am33xx.dtsi
@@ -10,12 +10,14 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/am33xx.h>
-
-#include "skeleton.dtsi"
+#include <dt-bindings/clock/am3.h>
 
 / {
 	compatible = "ti,am33xx";
 	interrupt-parent = <&intc>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+	chosen { };
 
 	aliases {
 		i2c0 = &i2c0;
@@ -27,14 +29,16 @@
 		serial3 = &uart3;
 		serial4 = &uart4;
 		serial5 = &uart5;
-		d_can0 = &dcan0;
-		d_can1 = &dcan1;
+		d-can0 = &dcan0;
+		d-can1 = &dcan1;
 		usb0 = &usb0;
 		usb1 = &usb1;
 		phy0 = &usb0_phy;
 		phy1 = &usb1_phy;
 		ethernet0 = &cpsw_emac0;
 		ethernet1 = &cpsw_emac1;
+		spi0 = &spi0;
+		spi1 = &spi1;
 	};
 
 	cpus {
@@ -45,19 +49,7 @@
 			device_type = "cpu";
 			reg = <0>;
 
-			/*
-			 * To consider voltage drop between PMIC and SoC,
-			 * tolerance value is reduced to 2% from 4% and
-			 * voltage value is increased as a precaution.
-			 */
-			operating-points = <
-				/* kHz    uV */
-				720000  1285000
-				600000  1225000
-				500000  1125000
-				275000  1125000
-			>;
-			voltage-tolerance = <2>; /* 2 percentage */
+			operating-points-v2 = <&cpu0_opp_table>;
 
 			clocks = <&dpll_mpu_ck>;
 			clock-names = "cpu";
@@ -66,9 +58,84 @@
 		};
 	};
 
+	cpu0_opp_table: opp-table {
+		compatible = "operating-points-v2-ti-cpu";
+		syscon = <&scm_conf>;
+
+		/*
+		 * The three following nodes are marked with opp-suspend
+		 * because the can not be enabled simultaneously on a
+		 * single SoC.
+		 */
+		opp50-300000000 {
+			opp-hz = /bits/ 64 <300000000>;
+			opp-microvolt = <950000 931000 969000>;
+			opp-supported-hw = <0x06 0x0010>;
+			opp-suspend;
+		};
+
+		opp100-275000000 {
+			opp-hz = /bits/ 64 <275000000>;
+			opp-microvolt = <1100000 1078000 1122000>;
+			opp-supported-hw = <0x01 0x00FF>;
+			opp-suspend;
+		};
+
+		opp100-300000000 {
+			opp-hz = /bits/ 64 <300000000>;
+			opp-microvolt = <1100000 1078000 1122000>;
+			opp-supported-hw = <0x06 0x0020>;
+			opp-suspend;
+		};
+
+		opp100-500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <1100000 1078000 1122000>;
+			opp-supported-hw = <0x01 0xFFFF>;
+		};
+
+		opp100-600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <1100000 1078000 1122000>;
+			opp-supported-hw = <0x06 0x0040>;
+		};
+
+		opp120-600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <1200000 1176000 1224000>;
+			opp-supported-hw = <0x01 0xFFFF>;
+		};
+
+		opp120-720000000 {
+			opp-hz = /bits/ 64 <720000000>;
+			opp-microvolt = <1200000 1176000 1224000>;
+			opp-supported-hw = <0x06 0x0080>;
+		};
+
+		oppturbo-720000000 {
+			opp-hz = /bits/ 64 <720000000>;
+			opp-microvolt = <1260000 1234800 1285200>;
+			opp-supported-hw = <0x01 0xFFFF>;
+		};
+
+		oppturbo-800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = <1260000 1234800 1285200>;
+			opp-supported-hw = <0x06 0x0100>;
+		};
+
+		oppnitro-1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <1325000 1298500 1351500>;
+			opp-supported-hw = <0x04 0x0200>;
+		};
+	};
+
-	pmu {
+	pmu@4b000000 {
 		compatible = "arm,cortex-a8-pmu";
 		interrupts = <3>;
+		reg = <0x4b000000 0x1000000>;
+		ti,hwmods = "debugss";
 	};
 
 	/*
@@ -80,6 +147,8 @@
 		mpu {
 			compatible = "ti,omap3-mpu";
 			ti,hwmods = "mpu";
+			pm-sram = <&pm_sram_code
+				   &pm_sram_data>;
 		};
 	};
 
@@ -91,7 +160,6 @@
 	 * the whole bus hierarchy.
 	 */
 	ocp {
-		u-boot,dm-spl;
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -104,9 +172,21 @@
 			#size-cells = <1>;
 			ranges = <0 0x44c00000 0x280000>;
 
+			wkup_m3: wkup_m3@100000 {
+				compatible = "ti,am3352-wkup-m3";
+				reg = <0x100000 0x4000>,
+				      <0x180000	0x2000>;
+				reg-names = "umem", "dmem";
+				ti,hwmods = "wkup_m3";
+				ti,pm-firmware = "am335x-pm-firmware.elf";
+			};
+
 			prcm: prcm@200000 {
-				compatible = "ti,am3-prcm";
+				compatible = "ti,am3-prcm", "simple-bus";
 				reg = <0x200000 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x200000 0x4000>;
 
 				prcm_clocks: clocks {
 					#address-cells = <1>;
@@ -122,6 +202,7 @@
 				reg = <0x210000 0x2000>;
 				#address-cells = <1>;
 				#size-cells = <1>;
+				#pinctrl-cells = <1>;
 				ranges = <0 0x210000 0x2000>;
 
 				am33xx_pinmux: pinmux@800 {
@@ -129,15 +210,17 @@
 					reg = <0x800 0x238>;
 					#address-cells = <1>;
 					#size-cells = <0>;
+					#pinctrl-cells = <1>;
 					pinctrl-single,register-width = <32>;
 					pinctrl-single,function-mask = <0x7f>;
 				};
 
 				scm_conf: scm_conf@0 {
-					compatible = "syscon";
+					compatible = "syscon", "simple-bus";
 					reg = <0x0 0x800>;
 					#address-cells = <1>;
 					#size-cells = <1>;
+					ranges = <0 0 0x800>;
 
 					scm_clocks: clocks {
 						#address-cells = <1>;
@@ -145,6 +228,22 @@
 					};
 				};
 
+				wkup_m3_ipc: wkup_m3_ipc@1324 {
+					compatible = "ti,am3352-wkup-m3-ipc";
+					reg = <0x1324 0x24>;
+					interrupts = <78>;
+					ti,rproc = <&wkup_m3>;
+					mboxes = <&mailbox &mbox_wkupm3>;
+				};
+
+				edma_xbar: dma-router@f90 {
+					compatible = "ti,am335x-edma-crossbar";
+					reg = <0xf90 0x40>;
+					#dma-cells = <3>;
+					dma-requests = <32>;
+					dma-masters = <&edma>;
+				};
+
 				scm_clockdomains: clockdomains {
 				};
 			};
@@ -158,14 +257,46 @@
 		};
 
 		edma: edma@49000000 {
-			compatible = "ti,edma3";
-			ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
-			reg =	<0x49000000 0x10000>,
-				<0x44e10f90 0x40>;
+			compatible = "ti,edma3-tpcc";
+			ti,hwmods = "tpcc";
+			reg =	<0x49000000 0x10000>;
+			reg-names = "edma3_cc";
 			interrupts = <12 13 14>;
-			#dma-cells = <1>;
+			interrupt-names = "edma3_ccint", "edma3_mperr",
+					  "edma3_ccerrint";
+			dma-requests = <64>;
+			#dma-cells = <2>;
+
+			ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
+				   <&edma_tptc2 0>;
+
+			ti,edma-memcpy-channels = <20 21>;
 		};
 
+		edma_tptc0: tptc@49800000 {
+			compatible = "ti,edma3-tptc";
+			ti,hwmods = "tptc0";
+			reg =	<0x49800000 0x100000>;
+			interrupts = <112>;
+			interrupt-names = "edma3_tcerrint";
+		};
+
+		edma_tptc1: tptc@49900000 {
+			compatible = "ti,edma3-tptc";
+			ti,hwmods = "tptc1";
+			reg =	<0x49900000 0x100000>;
+			interrupts = <113>;
+			interrupt-names = "edma3_tcerrint";
+		};
+
+		edma_tptc2: tptc@49a00000 {
+			compatible = "ti,edma3-tptc";
+			ti,hwmods = "tptc2";
+			reg =	<0x49a00000 0x100000>;
+			interrupts = <114>;
+			interrupt-names = "edma3_tcerrint";
+		};
+
 		gpio0: gpio@44e07000 {
 			compatible = "ti,omap4-gpio";
 			ti,hwmods = "gpio1";
@@ -211,67 +342,61 @@
 		};
 
 		uart0: serial@44e09000 {
-			compatible = "ti,omap3-uart";
+			compatible = "ti,am3352-uart", "ti,omap3-uart";
 			ti,hwmods = "uart1";
 			clock-frequency = <48000000>;
 			reg = <0x44e09000 0x2000>;
-			reg-shift = <2>;
 			interrupts = <72>;
 			status = "disabled";
-			dmas = <&edma 26>, <&edma 27>;
+			dmas = <&edma 26 0>, <&edma 27 0>;
 			dma-names = "tx", "rx";
 		};
 
 		uart1: serial@48022000 {
-			compatible = "ti,omap3-uart";
+			compatible = "ti,am3352-uart", "ti,omap3-uart";
 			ti,hwmods = "uart2";
 			clock-frequency = <48000000>;
 			reg = <0x48022000 0x2000>;
-			reg-shift = <2>;
 			interrupts = <73>;
 			status = "disabled";
-			dmas = <&edma 28>, <&edma 29>;
+			dmas = <&edma 28 0>, <&edma 29 0>;
 			dma-names = "tx", "rx";
 		};
 
 		uart2: serial@48024000 {
-			compatible = "ti,omap3-uart";
+			compatible = "ti,am3352-uart", "ti,omap3-uart";
 			ti,hwmods = "uart3";
 			clock-frequency = <48000000>;
 			reg = <0x48024000 0x2000>;
-			reg-shift = <2>;
 			interrupts = <74>;
 			status = "disabled";
-			dmas = <&edma 30>, <&edma 31>;
+			dmas = <&edma 30 0>, <&edma 31 0>;
 			dma-names = "tx", "rx";
 		};
 
 		uart3: serial@481a6000 {
-			compatible = "ti,omap3-uart";
+			compatible = "ti,am3352-uart", "ti,omap3-uart";
 			ti,hwmods = "uart4";
 			clock-frequency = <48000000>;
 			reg = <0x481a6000 0x2000>;
-			reg-shift = <2>;
 			interrupts = <44>;
 			status = "disabled";
 		};
 
 		uart4: serial@481a8000 {
-			compatible = "ti,omap3-uart";
+			compatible = "ti,am3352-uart", "ti,omap3-uart";
 			ti,hwmods = "uart5";
 			clock-frequency = <48000000>;
 			reg = <0x481a8000 0x2000>;
-			reg-shift = <2>;
 			interrupts = <45>;
 			status = "disabled";
 		};
 
 		uart5: serial@481aa000 {
-			compatible = "ti,omap3-uart";
+			compatible = "ti,am3352-uart", "ti,omap3-uart";
 			ti,hwmods = "uart6";
 			clock-frequency = <48000000>;
 			reg = <0x481aa000 0x2000>;
-			reg-shift = <2>;
 			interrupts = <46>;
 			status = "disabled";
 		};
@@ -312,8 +437,8 @@
 			ti,dual-volt;
 			ti,needs-special-reset;
 			ti,needs-special-hs-handling;
-			dmas = <&edma 24
-				&edma 25>;
+			dmas = <&edma_xbar 24 0 0
+				&edma_xbar 25 0 0>;
 			dma-names = "tx", "rx";
 			interrupts = <64>;
 			reg = <0x48060000 0x1000>;
@@ -324,8 +449,8 @@
 			compatible = "ti,omap4-hsmmc";
 			ti,hwmods = "mmc2";
 			ti,needs-special-reset;
-			dmas = <&edma 2
-				&edma 3>;
+			dmas = <&edma 2 0
+				&edma 3 0>;
 			dma-names = "tx", "rx";
 			interrupts = <28>;
 			reg = <0x481d8000 0x1000>;
@@ -377,7 +502,7 @@
 			status = "disabled";
 		};
 
-		mailbox: mailbox@480C8000 {
+		mailbox: mailbox@480c8000 {
 			compatible = "ti,omap4-mailbox";
 			reg = <0x480C8000 0x200>;
 			interrupts = <77>;
@@ -386,6 +511,7 @@
 			ti,mbox-num-users = <4>;
 			ti,mbox-num-fifos = <8>;
 			mbox_wkupm3: wkup_m3 {
+				ti,mbox-send-noirq;
 				ti,mbox-tx = <0 0 0>;
 				ti,mbox-rx = <0 0 3>;
 			};
@@ -397,6 +523,8 @@
 			interrupts = <67>;
 			ti,hwmods = "timer1";
 			ti,timer-alwon;
+			clocks = <&timer1_fck>;
+			clock-names = "fck";
 		};
 
 		timer2: timer@48040000 {
@@ -404,6 +532,8 @@
 			reg = <0x48040000 0x400>;
 			interrupts = <68>;
 			ti,hwmods = "timer2";
+			clocks = <&timer2_fck>;
+			clock-names = "fck";
 		};
 
 		timer3: timer@48042000 {
@@ -451,6 +581,8 @@
 			interrupts = <75
 				      76>;
 			ti,hwmods = "rtc";
+			clocks = <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
+			clock-names = "int-clk";
 		};
 
 		spi0: spi@48030000 {
@@ -461,10 +593,10 @@
 			interrupts = <65>;
 			ti,spi-num-cs = <2>;
 			ti,hwmods = "spi0";
-			dmas = <&edma 16
-				&edma 17
-				&edma 18
-				&edma 19>;
+			dmas = <&edma 16 0
+				&edma 17 0
+				&edma 18 0
+				&edma 19 0>;
 			dma-names = "tx0", "rx0", "tx1", "rx1";
 			status = "disabled";
 		};
@@ -477,10 +609,10 @@
 			interrupts = <125>;
 			ti,spi-num-cs = <2>;
 			ti,hwmods = "spi1";
-			dmas = <&edma 42
-				&edma 43
-				&edma 44
-				&edma 45>;
+			dmas = <&edma 42 0
+				&edma 43 0
+				&edma 44 0
+				&edma 45 0>;
 			dma-names = "tx0", "rx0", "tx1", "rx1";
 			status = "disabled";
 		};
@@ -508,6 +640,7 @@
 				reg-names = "phy";
 				status = "disabled";
 				ti,ctrl_mod = <&usb_ctrl_mod>;
+				#phy-cells = <0>;
 			};
 
 			usb0: usb@47401000 {
@@ -556,6 +689,7 @@
 				reg-names = "phy";
 				status = "disabled";
 				ti,ctrl_mod = <&usb_ctrl_mod>;
+				#phy-cells = <0>;
 			};
 
 			usb1: usb@47401800 {
@@ -625,20 +759,24 @@
 				  0x48300200 0x48300200 0x80>; /* EHRPWM */
 
 			ecap0: ecap@48300100 {
-				compatible = "ti,am33xx-ecap";
+				compatible = "ti,am3352-ecap",
+					     "ti,am33xx-ecap";
 				#pwm-cells = <3>;
 				reg = <0x48300100 0x80>;
+				clocks = <&l4ls_gclk>;
+				clock-names = "fck";
 				interrupts = <31>;
 				interrupt-names = "ecap0";
-				ti,hwmods = "ecap0";
 				status = "disabled";
 			};
 
-			ehrpwm0: ehrpwm@48300200 {
-				compatible = "ti,am33xx-ehrpwm";
+			ehrpwm0: pwm@48300200 {
+				compatible = "ti,am3352-ehrpwm",
+					     "ti,am33xx-ehrpwm";
 				#pwm-cells = <3>;
 				reg = <0x48300200 0x80>;
-				ti,hwmods = "ehrpwm0";
+				clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
+				clock-names = "tbclk", "fck";
 				status = "disabled";
 			};
 		};
@@ -655,20 +793,24 @@
 				  0x48302200 0x48302200 0x80>; /* EHRPWM */
 
 			ecap1: ecap@48302100 {
-				compatible = "ti,am33xx-ecap";
+				compatible = "ti,am3352-ecap",
+					     "ti,am33xx-ecap";
 				#pwm-cells = <3>;
 				reg = <0x48302100 0x80>;
+				clocks = <&l4ls_gclk>;
+				clock-names = "fck";
 				interrupts = <47>;
 				interrupt-names = "ecap1";
-				ti,hwmods = "ecap1";
 				status = "disabled";
 			};
 
-			ehrpwm1: ehrpwm@48302200 {
-				compatible = "ti,am33xx-ehrpwm";
+			ehrpwm1: pwm@48302200 {
+				compatible = "ti,am3352-ehrpwm",
+					     "ti,am33xx-ehrpwm";
 				#pwm-cells = <3>;
 				reg = <0x48302200 0x80>;
-				ti,hwmods = "ehrpwm1";
+				clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
+				clock-names = "tbclk", "fck";
 				status = "disabled";
 			};
 		};
@@ -685,34 +827,36 @@
 				  0x48304200 0x48304200 0x80>; /* EHRPWM */
 
 			ecap2: ecap@48304100 {
-				compatible = "ti,am33xx-ecap";
+				compatible = "ti,am3352-ecap",
+					     "ti,am33xx-ecap";
 				#pwm-cells = <3>;
 				reg = <0x48304100 0x80>;
+				clocks = <&l4ls_gclk>;
+				clock-names = "fck";
 				interrupts = <61>;
 				interrupt-names = "ecap2";
-				ti,hwmods = "ecap2";
 				status = "disabled";
 			};
 
-			ehrpwm2: ehrpwm@48304200 {
-				compatible = "ti,am33xx-ehrpwm";
+			ehrpwm2: pwm@48304200 {
+				compatible = "ti,am3352-ehrpwm",
+					     "ti,am33xx-ehrpwm";
 				#pwm-cells = <3>;
 				reg = <0x48304200 0x80>;
-				ti,hwmods = "ehrpwm2";
+				clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
+				clock-names = "tbclk", "fck";
 				status = "disabled";
 			};
 		};
 
 		mac: ethernet@4a100000 {
-			compatible = "ti,cpsw";
+			compatible = "ti,am335x-cpsw","ti,cpsw";
 			ti,hwmods = "cpgmac0";
 			clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
 			clock-names = "fck", "cpts";
 			cpdma_channels = <8>;
 			ale_entries = <1024>;
 			bd_ram_size = <0x2000>;
-			no_bd_ram = <0>;
-			rx_descs = <64>;
 			mac_control = <0x20>;
 			slaves = <2>;
 			active_slave = <0>;
@@ -734,7 +878,7 @@
 			status = "disabled";
 
 			davinci_mdio: mdio@4a101000 {
-				compatible = "ti,davinci_mdio";
+				compatible = "ti,cpsw-mdio","ti,davinci_mdio";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				ti,hwmods = "davinci_mdio";
@@ -763,14 +907,21 @@
 		ocmcram: ocmcram@40300000 {
 			compatible = "mmio-sram";
 			reg = <0x40300000 0x10000>; /* 64k */
-		};
+			ranges = <0x0 0x40300000 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
 
-		wkup_m3: wkup_m3@44d00000 {
-			compatible = "ti,am3353-wkup-m3";
-			reg = <0x44d00000 0x4000	/* M3 UMEM */
-			       0x44d80000 0x2000>;	/* M3 DMEM */
-			ti,hwmods = "wkup_m3";
-			ti,no-reset-on-init;
+			pm_sram_code: pm-sram-code@0 {
+				compatible = "ti,sram";
+				reg = <0x0 0x1000>;
+				protect-exec;
+			};
+
+			pm_sram_data: pm-sram-data@1000 {
+				compatible = "ti,sram";
+				reg = <0x1000 0x1000>;
+				pool;
+			};
 		};
 
 		elm: elm@48080000 {
@@ -795,6 +946,8 @@
 			interrupts = <16>;
 			ti,hwmods = "adc_tsc";
 			status = "disabled";
+			dmas = <&edma 53 0>, <&edma 57 0>;
+			dma-names = "fifo0", "fifo1";
 
 			tsc {
 				compatible = "ti,am3359-tsc";
@@ -805,16 +958,32 @@
 			};
 		};
 
+		emif: emif@4c000000 {
+			compatible = "ti,emif-am3352";
+			reg = <0x4c000000 0x1000000>;
+			ti,hwmods = "emif";
+			interrupts = <101>;
+			sram = <&pm_sram_code
+				&pm_sram_data>;
+			ti,no-idle;
+		};
+
 		gpmc: gpmc@50000000 {
 			compatible = "ti,am3352-gpmc";
 			ti,hwmods = "gpmc";
 			ti,no-idle-on-init;
 			reg = <0x50000000 0x2000>;
 			interrupts = <100>;
+			dmas = <&edma 52 0>;
+			dma-names = "rxtx";
 			gpmc,num-cs = <7>;
 			gpmc,num-waitpins = <2>;
 			#address-cells = <2>;
 			#size-cells = <1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-controller;
+			#gpio-cells = <2>;
 			status = "disabled";
 		};
 
@@ -823,7 +992,7 @@
 			ti,hwmods = "sham";
 			reg = <0x53100000 0x200>;
 			interrupts = <109>;
-			dmas = <&edma 36>;
+			dmas = <&edma 36 0>;
 			dma-names = "rx";
 		};
 
@@ -832,8 +1001,8 @@
 			ti,hwmods = "aes";
 			reg = <0x53500000 0xa0>;
 			interrupts = <103>;
-			dmas = <&edma 6>,
-			       <&edma 5>;
+			dmas = <&edma 6 0>,
+			       <&edma 5 0>;
 			dma-names = "tx", "rx";
 		};
 
@@ -846,12 +1015,12 @@
 			interrupts = <80>, <81>;
 			interrupt-names = "tx", "rx";
 			status = "disabled";
-			dmas = <&edma 8>,
-				<&edma 9>;
+			dmas = <&edma 8 2>,
+				<&edma 9 2>;
 			dma-names = "tx", "rx";
 		};
 
-		mcasp1: mcasp@4803C000 {
+		mcasp1: mcasp@4803c000 {
 			compatible = "ti,am33xx-mcasp-audio";
 			ti,hwmods = "mcasp1";
 			reg = <0x4803C000 0x2000>,
@@ -860,8 +1029,8 @@
 			interrupts = <82>, <83>;
 			interrupt-names = "tx", "rx";
 			status = "disabled";
-			dmas = <&edma 10>,
-				<&edma 11>;
+			dmas = <&edma 10 2>,
+				<&edma 11 2>;
 			dma-names = "tx", "rx";
 		};
 
@@ -874,4 +1043,4 @@
 	};
 };
 
-/include/ "am33xx-clocks.dtsi"
+#include "am33xx-clocks.dtsi"
diff --git a/arch/arm/dts/am3517-evm-ui.dtsi b/arch/arm/dts/am3517-evm-ui.dtsi
new file mode 100644
index 0000000..e841918
--- /dev/null
+++ b/arch/arm/dts/am3517-evm-ui.dtsi
@@ -0,0 +1,220 @@
+/*
+ * Copyright (C) 2018 Logic PD, Inc - http://www.logicpd.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/input/input.h>
+
+/ {
+	codec1 {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "tlv320aic23-hifi";
+
+		simple-audio-card,widgets =
+			"Microphone", "Mic In",
+			"Line", "Line In",
+			"Line", "Line Out";
+
+		simple-audio-card,routing =
+			"Line Out", "LOUT",
+			"Line Out", "ROUT",
+			"LLINEIN", "Line In",
+			"RLINEIN", "Line In",
+			"MICIN", "Mic In";
+
+		simple-audio-card,format = "i2s";
+		simple-audio-card,bitclock-master = <&sound_master>;
+		simple-audio-card,frame-master = <&sound_master>;
+
+		simple-audio-card,cpu {
+			sound-dai = <&mcbsp1>;
+		};
+
+		sound_master: simple-audio-card,codec {
+			sound-dai = <&tlv320aic23_1>;
+			system-clock-frequency = <12000000>;
+		};
+	};
+
+	codec2 {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "tlv320aic23-hifi";
+
+		simple-audio-card,widgets =
+			"Microphone", "Mic In",
+			"Line", "Line In",
+			"Line", "Line Out";
+
+		simple-audio-card,routing =
+			"Line Out", "LOUT",
+			"Line Out", "ROUT",
+			"LLINEIN", "Line In",
+			"RLINEIN", "Line In",
+			"MICIN", "Mic In";
+
+		simple-audio-card,format = "i2s";
+		simple-audio-card,bitclock-master = <&sound_master2>;
+		simple-audio-card,frame-master = <&sound_master2>;
+
+		simple-audio-card,cpu {
+			sound-dai = <&mcbsp2>;
+		};
+
+		sound_master2: simple-audio-card,codec {
+			sound-dai = <&tlv320aic23_2>;
+			system-clock-frequency = <12000000>;
+		};
+	};
+
+	expander-keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		record {
+			label = "Record";
+			/* linux,code = <BTN_0>; */
+			gpios = <&tca6416_2 15 GPIO_ACTIVE_LOW>;
+		};
+
+		play {
+			label = "Play";
+			linux,code = <KEY_PLAY>;
+			gpios = <&tca6416_2 14 GPIO_ACTIVE_LOW>;
+		};
+
+		Stop {
+			label = "Stop";
+			linux,code = <KEY_STOP>;
+			gpios = <&tca6416_2 13 GPIO_ACTIVE_LOW>;
+		};
+
+		fwd {
+			label = "FWD";
+			linux,code = <KEY_FASTFORWARD>;
+			gpios = <&tca6416_2 12 GPIO_ACTIVE_LOW>;
+		};
+
+		rwd {
+			label = "RWD";
+			linux,code = <KEY_REWIND>;
+			gpios = <&tca6416_2 11 GPIO_ACTIVE_LOW>;
+		};
+
+		shift {
+			label = "Shift";
+			linux,code = <KEY_LEFTSHIFT>;
+			gpios = <&tca6416_2 10 GPIO_ACTIVE_LOW>;
+		};
+
+		Mode {
+			label = "Mode";
+			linux,code = <BTN_MODE>;
+			gpios = <&tca6416_2 9 GPIO_ACTIVE_LOW>;
+		};
+
+		Menu {
+			label = "Menu";
+			linux,code = <KEY_MENU>;
+			gpios = <&tca6416_2 8 GPIO_ACTIVE_LOW>;
+		};
+
+		Up {
+			label = "Up";
+			linux,code = <KEY_UP>;
+			gpios = <&tca6416_2 7 GPIO_ACTIVE_LOW>;
+		};
+
+		Down {
+			label = "Down";
+			linux,code = <KEY_DOWN>;
+			gpios = <&tca6416_2 6 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&i2c2 {
+	/* Audio codecs */
+	tlv320aic23_1: codec@1a {
+		compatible = "ti,tlv320aic23";
+		reg = <0x1a>;
+		#sound-dai-cells= <0>;
+		status = "okay";
+	};
+
+	tlv320aic23_2: codec@1b {
+		compatible = "ti,tlv320aic23";
+		reg = <0x1b>;
+		#sound-dai-cells= <0>;
+		status = "okay";
+	};
+};
+
+&i2c3 {
+	/* Audio codecs */
+	tlv320aic23_3: codec@1a {
+		compatible = "ti,tlv320aic23";
+		reg = <0x1a>;
+		#sound-dai-cells= <0>;
+		status = "okay";
+	};
+
+	/* GPIO Expanders */
+	tca6416_2: gpio@20 {
+		compatible = "ti,tca6416";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		vcc-supply = <&vdd_io_reg>;
+	};
+
+	tca6416_3: gpio@21 {
+		compatible = "ti,tca6416";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		vcc-supply = <&vdd_io_reg>;
+	};
+
+	/* TVP5146 Analog Video decoder input */
+	tvp5146@5c {
+		compatible = "ti,tvp5146m2";
+		reg = <0x5c>;
+	};
+};
+
+&mcbsp1 {
+	status = "ok";
+	#sound-dai-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcbsp1_pins>;
+};
+
+&mcbsp2 {
+	status = "ok";
+	#sound-dai-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcbsp2_pins>;
+};
+
+&omap3_pmx_core {
+	mcbsp1_pins: pinmux_mcbsp1_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE0)	/* mcbsp1_dx.mcbsp1_dx */
+			OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT | MUX_MODE0)	/* mcbsp1_dx.mcbsp1_dr */
+			OMAP3_CORE1_IOPAD(0x2196, PIN_INPUT | MUX_MODE0)	/* mcbsp_clks.mcbsp1_fsx */
+			OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE0)	/* mcbsp1_clkx.mcbsp1_clkx */
+		>;
+	};
+
+	mcbsp2_pins: pinmux_mcbsp2_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0)	/* mcbsp2_fsx.mcbsp2_fsx */
+			OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0)	/* mcbsp2_clkx.mcbsp2_clkx */
+			OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0)	/* mcbsp2_dr.mcbsp2.dr */
+			OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0)	/* mcbsp2_dx.mcbsp2_dx */
+		>;
+	};
+};
diff --git a/arch/arm/dts/am3517-evm.dts b/arch/arm/dts/am3517-evm.dts
index 1d158cf..1e2bb68 100644
--- a/arch/arm/dts/am3517-evm.dts
+++ b/arch/arm/dts/am3517-evm.dts
@@ -9,6 +9,7 @@
 
 #include "am3517.dtsi"
 #include "am3517-som.dtsi"
+#include "am3517-evm-ui.dtsi"
 #include <dt-bindings/input/input.h>
 
 / {
@@ -227,7 +228,7 @@
 	vmmc-supply = <&vmmc_fixed>;
 	bus-width = <4>;
 	wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */
-	cd-gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio_127 */
+	cd-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* gpio_127 */
 };
 
 &mmc3 {
diff --git a/arch/arm/dts/am3517-som.dtsi b/arch/arm/dts/am3517-som.dtsi
index dae6e45..b1c988e 100644
--- a/arch/arm/dts/am3517-som.dtsi
+++ b/arch/arm/dts/am3517-som.dtsi
@@ -163,7 +163,7 @@
 		compatible = "ti,wl1271";
 		reg = <2>;
 		interrupt-parent = <&gpio6>;
-		interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; /* gpio_170 */
+		interrupts = <10 IRQ_TYPE_EDGE_RISING>; /* gpio_170 */
 		ref-clock-frequency = <26000000>;
 		tcxo-clock-frequency = <26000000>;
 	};
diff --git a/arch/arm/dts/am4372.dtsi b/arch/arm/dts/am4372.dtsi
index 3ffa8e0..6f60a32 100644
--- a/arch/arm/dts/am4372.dtsi
+++ b/arch/arm/dts/am4372.dtsi
@@ -108,8 +108,6 @@
 					compatible = "ti,am437-padconf",
 						     "pinctrl-single";
 					reg = <0x800 0x31c>;
-					#address-cells = <1>;
-					#size-cells = <0>;
 					#interrupt-cells = <1>;
 					interrupt-controller;
 					pinctrl-single,register-width = <32>;
@@ -119,8 +117,6 @@
 				scm_conf: scm_conf@0 {
 					compatible = "syscon";
 					reg = <0x0 0x800>;
-					#address-cells = <1>;
-					#size-cells = <1>;
 
 					scm_clocks: clocks {
 						#address-cells = <1>;
@@ -764,7 +760,8 @@
 			reg = <0x48038000 0x2000>,
 			      <0x46000000 0x400000>;
 			reg-names = "mpu", "dat";
-			interrupts = <80>, <81>;
+			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "tx", "rx";
 			status = "disabled";
 			dmas = <&edma 8>,
@@ -778,7 +775,8 @@
 			reg = <0x4803C000 0x2000>,
 			      <0x46400000 0x400000>;
 			reg-names = "mpu", "dat";
-			interrupts = <82>, <83>;
+			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "tx", "rx";
 			status = "disabled";
 			dmas = <&edma 10>,
@@ -807,6 +805,8 @@
 			gpmc,num-waitpins = <2>;
 			#address-cells = <2>;
 			#size-cells = <1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
 			status = "disabled";
 		};
 
diff --git a/arch/arm/dts/am437x-idk-evm.dts b/arch/arm/dts/am437x-idk-evm.dts
index e454647..28e3e1b 100644
--- a/arch/arm/dts/am437x-idk-evm.dts
+++ b/arch/arm/dts/am437x-idk-evm.dts
@@ -106,8 +106,6 @@
 		compatible = "gpio-keys";
 		pinctrl-names = "default";
 		pinctrl-0 = <&gpio_keys_pins_default>;
-		#address-cells = <1>;
-		#size-cells = <0>;
 
 		switch@0 {
 			label = "power-button";
diff --git a/arch/arm/dts/armada-388-helios4-u-boot.dtsi b/arch/arm/dts/armada-388-helios4-u-boot.dtsi
new file mode 100644
index 0000000..4b20610
--- /dev/null
+++ b/arch/arm/dts/armada-388-helios4-u-boot.dtsi
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/ {
+	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		spi1 = &spi1;
+	};
+};
+
+&eth0 {
+	phy-reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
+};
+
+&spi1 {
+	u-boot,dm-spl;
+};
+
+&w25q32 {
+	status = "okay";
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/bcm6858.dtsi b/arch/arm/dts/bcm6858.dtsi
index 9869d72..d78d34d 100644
--- a/arch/arm/dts/bcm6858.dtsi
+++ b/arch/arm/dts/bcm6858.dtsi
@@ -75,7 +75,7 @@
 		u-boot,dm-pre-reloc;
 
 		uart0: serial@ff800640 {
-			compatible = "brcm,bcm6858-uart";
+			compatible = "brcm,bcm6345-uart";
 			reg = <0x0 0xff800640 0x0 0x18>;
 			clocks = <&periph_osc>;
 
diff --git a/arch/arm/dts/da850-evm.dts b/arch/arm/dts/da850-evm.dts
index 0e82bb9..a3c9b34 100644
--- a/arch/arm/dts/da850-evm.dts
+++ b/arch/arm/dts/da850-evm.dts
@@ -27,6 +27,65 @@
 		spi0 = &spi1;
 	};
 
+	backlight: backlight-pwm {
+		pinctrl-names = "default";
+		pinctrl-0 = <&ecap2_pins>;
+		power-supply = <&backlight_lcd>;
+		compatible = "pwm-backlight";
+		/*
+		 * The PWM here corresponds to production hardware. The
+		 * schematic needs to be 1015171 (15 March 2010), Rev A
+		 * or newer.
+		 */
+		pwms = <&ecap2 0 50000 0>;
+		brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>;
+		default-brightness-level = <7>;
+	};
+
+	panel {
+		compatible = "ti,tilcdc,panel";
+		pinctrl-names = "default";
+		pinctrl-0 = <&lcd_pins>;
+		/*
+		 * The vpif and the LCD are mutually exclusive.
+		 * To enable VPIF, change the status below to 'disabled' then
+		 * then change the status of the vpif below to 'okay'
+		 */
+		status = "okay";
+		enable-gpios = <&gpio 40 GPIO_ACTIVE_HIGH>; /* lcd_panel_pwr */
+
+		panel-info {
+			ac-bias		= <255>;
+			ac-bias-intrpt	= <0>;
+			dma-burst-sz	= <16>;
+			bpp		= <16>;
+			fdd		= <0x80>;
+			sync-edge	= <0>;
+			sync-ctrl	= <1>;
+			raster-order	= <0>;
+			fifo-th		= <0>;
+		};
+
+		display-timings {
+			native-mode = <&timing0>;
+			timing0: 480x272 {
+				clock-frequency = <9000000>;
+				hactive = <480>;
+				vactive = <272>;
+				hfront-porch = <3>;
+				hback-porch = <2>;
+				hsync-len = <42>;
+				vback-porch = <3>;
+				vfront-porch = <4>;
+				vsync-len = <11>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <1>;
+			};
+		};
+	};
+
 	vbat: fixedregulator0 {
 		compatible = "regulator-fixed";
 		regulator-name = "vbat";
@@ -35,6 +94,15 @@
 		regulator-boot-on;
 	};
 
+	backlight_lcd: backlight-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "lcd_backlight_pwr";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio 47 GPIO_ACTIVE_HIGH>; /* lcd_backlight_pwr */
+		enable-active-high;
+	};
+
 	sound {
 		compatible = "simple-audio-card";
 		simple-audio-card,name = "DA850/OMAP-L138 EVM";
@@ -63,6 +131,14 @@
 	};
 };
 
+&ecap2 {
+	status = "okay";
+};
+
+&ref_clk {
+	clock-frequency = <24000000>;
+};
+
 &pmx_core {
 	status = "okay";
 
@@ -93,6 +169,10 @@
 	};
 };
 
+&sata {
+	status = "okay";
+};
+
 &serial0 {
 	status = "okay";
 };
@@ -109,6 +189,10 @@
 	status = "okay";
 };
 
+&lcdc {
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 	clock-frequency = <100000>;
@@ -137,6 +221,12 @@
 		gpio-controller;
 		#gpio-cells = <2>;
 	};
+	tca6416_bb: gpio@21 {
+		compatible = "ti,tca6416";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
 };
 
 &wdt {
@@ -336,5 +426,10 @@
 &vpif {
 	pinctrl-names = "default";
 	pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>;
-	status = "okay";
+	/*
+	 * The vpif and the LCD are mutually exclusive.
+	 * To enable VPIF, disable the ti,tilcdc,panel then
+	 * change the status below to 'okay'
+	 */
+	status = "disabled";
 };
diff --git a/arch/arm/dts/da850-lcdk.dts b/arch/arm/dts/da850-lcdk.dts
index a1f4d6d..0177e3e 100644
--- a/arch/arm/dts/da850-lcdk.dts
+++ b/arch/arm/dts/da850-lcdk.dts
@@ -21,8 +21,8 @@
 		stdout-path = "serial2:115200n8";
 	};
 
-	memory {
-		device_type = "memory";
+	memory@c0000000 {
+		/* 128 MB DDR2 SDRAM @ 0xc0000000 */
 		reg = <0xc0000000 0x08000000>;
 	};
 
@@ -123,6 +123,10 @@
 	};
 };
 
+&ref_clk {
+	clock-frequency = <24000000>;
+};
+
 &pmx_core {
 	status = "okay";
 
@@ -173,6 +177,11 @@
 
 &gpio {
 	status = "okay";
+};
+
+&sata_refclk {
+	status = "okay";
+	clock-frequency = <100000000>;
 };
 
 &sata {
diff --git a/arch/arm/dts/da850.dtsi b/arch/arm/dts/da850.dtsi
index c66cf78..47aa53b 100644
--- a/arch/arm/dts/da850.dtsi
+++ b/arch/arm/dts/da850.dtsi
@@ -7,10 +7,19 @@
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
-#include "skeleton.dtsi"
 #include <dt-bindings/interrupt-controller/irq.h>
 
 / {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	chosen { };
+	aliases { };
+
+	memory@c0000000 {
+		device_type = "memory";
+		reg = <0xc0000000 0x0>;
+	};
+
 	arm {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -23,6 +32,25 @@
 			reg = <0xfffee000 0x2000>;
 		};
 	};
+	clocks: clocks {
+		ref_clk: ref_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-output-names = "ref_clk";
+		};
+		sata_refclk: sata_refclk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-output-names = "sata_refclk";
+			status = "disabled";
+		};
+		usb_refclkin: usb_refclkin {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-output-names = "usb_refclkin";
+			status = "disabled";
+		};
+	};
 	dsp: dsp@11800000 {
 		compatible = "ti,da850-dsp";
 		reg = <0x11800000 0x40000>,
@@ -33,6 +61,8 @@
 		reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig";
 		interrupt-parent = <&intc>;
 		interrupts = <28>;
+		clocks = <&psc0 15>;
+		resets = <&psc0 15>;
 		status = "disabled";
 	};
 	soc@1c00000 {
@@ -43,17 +73,57 @@
 		ranges = <0x0 0x01c00000 0x400000>;
 		interrupt-parent = <&intc>;
 
+		psc0: clock-controller@10000 {
+			compatible = "ti,da850-psc0";
+			reg = <0x10000 0x1000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+			clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>,
+				 <&pll0_sysclk 4>, <&pll0_sysclk 6>,
+				 <&async1_clk>;
+			clock-names = "pll0_sysclk1", "pll0_sysclk2",
+				      "pll0_sysclk4", "pll0_sysclk6",
+				      "async1";
+		};
+		pll0: clock-controller@11000 {
+			compatible = "ti,da850-pll0";
+			reg = <0x11000 0x1000>;
+			clocks = <&ref_clk>, <&pll1_sysclk 3>;
+			clock-names = "clksrc", "extclksrc";
+
+			pll0_pllout: pllout {
+				#clock-cells = <0>;
+			};
+			pll0_sysclk: sysclk {
+				#clock-cells = <1>;
+			};
+			pll0_auxclk: auxclk {
+				#clock-cells = <0>;
+			};
+			pll0_obsclk: obsclk {
+				#clock-cells = <0>;
+			};
+		};
 		pmx_core: pinmux@14120 {
 			compatible = "pinctrl-single";
 			reg = <0x14120 0x50>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			#pinctrl-cells = <2>;
 			pinctrl-single,bit-per-mux;
 			pinctrl-single,register-width = <32>;
 			pinctrl-single,function-mask = <0xf>;
+			/* pin base, nr pins & gpio function */
+			pinctrl-single,gpio-range = <&range   0 17 0x8>,
+						    <&range  17  8 0x4>,
+						    <&range  26  8 0x4>,
+						    <&range  34 80 0x8>,
+						    <&range 129 31 0x8>;
 			status = "disabled";
 
+			range: gpio-range {
+				#pinctrl-single,gpio-range-cells = <3>;
+			};
+
 			serial0_rtscts_pins: pinmux_serial0_rtscts_pins {
 				pinctrl-single,bits = <
 					/* UART0_RTS UART0_CTS */
@@ -264,8 +334,41 @@
 			usb_phy: usb-phy {
 				compatible = "ti,da830-usb-phy";
 				#phy-cells = <1>;
+				clocks = <&usb_phy_clk 0>, <&usb_phy_clk 1>;
+				clock-names = "usb0_clk48", "usb1_clk48";
 				status = "disabled";
 			};
+			usb_phy_clk: usb-phy-clocks {
+				compatible = "ti,da830-usb-phy-clocks";
+				#clock-cells = <1>;
+				clocks = <&psc1 1>, <&usb_refclkin>,
+					 <&pll0_auxclk>;
+				clock-names = "fck", "usb_refclkin", "auxclk";
+			};
+			ehrpwm_tbclk: ehrpwm_tbclk {
+				compatible = "ti,da830-tbclksync";
+				#clock-cells = <0>;
+				clocks = <&psc1 17>;
+				clock-names = "fck";
+			};
+			div4p5_clk: div4.5 {
+				compatible = "ti,da830-div4p5ena";
+				#clock-cells = <0>;
+				clocks = <&pll0_pllout>;
+				clock-names = "pll0_pllout";
+			};
+			async1_clk: async1 {
+				compatible = "ti,da850-async1-clksrc";
+				#clock-cells = <0>;
+				clocks = <&pll0_sysclk 3>, <&div4p5_clk>;
+				clock-names = "pll0_sysclk3", "div4.5";
+			};
+			async3_clk: async3 {
+				compatible = "ti,da850-async3-clksrc";
+				#clock-cells = <0>;
+				clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>;
+				clock-names = "pll0_sysclk2", "pll1_sysclk2";
+			};
 		};
 		edma0: edma@0 {
 			compatible = "ti,edma3-tpcc";
@@ -277,18 +380,21 @@
 			#dma-cells = <2>;
 
 			ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>;
+			power-domains = <&psc0 0>;
 		};
 		edma0_tptc0: tptc@8000 {
 			compatible = "ti,edma3-tptc";
 			reg =	<0x8000 0x400>;
 			interrupts = <13>;
 			interrupt-names = "edm3_tcerrint";
+			power-domains = <&psc0 1>;
 		};
 		edma0_tptc1: tptc@8400 {
 			compatible = "ti,edma3-tptc";
 			reg =	<0x8400 0x400>;
 			interrupts = <32>;
 			interrupt-names = "edm3_tcerrint";
+			power-domains = <&psc0 2>;
 		};
 		edma1: edma@230000 {
 			compatible = "ti,edma3-tpcc";
@@ -300,12 +406,14 @@
 			#dma-cells = <2>;
 
 			ti,tptcs = <&edma1_tptc0 7>;
+			power-domains = <&psc1 0>;
 		};
 		edma1_tptc0: tptc@238000 {
 			compatible = "ti,edma3-tptc";
 			reg =	<0x238000 0x400>;
 			interrupts = <95>;
 			interrupt-names = "edm3_tcerrint";
+			power-domains = <&psc1 21>;
 		};
 		serial0: serial@42000 {
 			compatible = "ti,da830-uart", "ns16550a";
@@ -313,6 +421,8 @@
 			reg-io-width = <4>;
 			reg-shift = <2>;
 			interrupts = <25>;
+			clocks = <&psc0 9>;
+			power-domains = <&psc0 9>;
 			status = "disabled";
 		};
 		serial1: serial@10c000 {
@@ -321,6 +431,8 @@
 			reg-io-width = <4>;
 			reg-shift = <2>;
 			interrupts = <53>;
+			clocks = <&psc1 12>;
+			power-domains = <&psc1 12>;
 			status = "disabled";
 		};
 		serial2: serial@10d000 {
@@ -329,6 +441,8 @@
 			reg-io-width = <4>;
 			reg-shift = <2>;
 			interrupts = <61>;
+			clocks = <&psc1 13>;
+			power-domains = <&psc1 13>;
 			status = "disabled";
 		};
 		rtc0: rtc@23000 {
@@ -336,6 +450,8 @@
 			reg = <0x23000 0x1000>;
 			interrupts = <19
 				      19>;
+			clocks = <&pll0_auxclk>;
+			clock-names = "int-clk";
 			status = "disabled";
 		};
 		i2c0: i2c@22000 {
@@ -344,6 +460,7 @@
 			interrupts = <15>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			clocks = <&pll0_auxclk>;
 			status = "disabled";
 		};
 		i2c1: i2c@228000 {
@@ -352,11 +469,21 @@
 			interrupts = <51>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			clocks = <&psc1 11>;
+			power-domains = <&psc1 11>;
 			status = "disabled";
 		};
+		clocksource: timer@20000 {
+			compatible = "ti,da830-timer";
+			reg = <0x20000 0x1000>;
+			interrupts = <12>, <13>;
+			interrupt-names = "tint12", "tint34";
+			clocks = <&pll0_auxclk>;
+		};
 		wdt: wdt@21000 {
 			compatible = "ti,davinci-wdt";
 			reg = <0x21000 0x1000>;
+			clocks = <&pll0_auxclk>;
 			status = "disabled";
 		};
 		mmc0: mmc@40000 {
@@ -367,12 +494,14 @@
 			interrupts = <16>;
 			dmas = <&edma0 16 0>, <&edma0 17 0>;
 			dma-names = "rx", "tx";
+			clocks = <&psc0 5>;
 			status = "disabled";
 		};
 		vpif: video@217000 {
 			compatible = "ti,da850-vpif";
 			reg = <0x217000 0x1000>;
 			interrupts = <92>;
+			power-domains = <&psc1 9>;
 			status = "disabled";
 
 			/* VPIF capture port */
@@ -395,6 +524,7 @@
 			interrupts = <72>;
 			dmas = <&edma1 28 0>, <&edma1 29 0>;
 			dma-names = "rx", "tx";
+			clocks = <&psc1 18>;
 			status = "disabled";
 		};
 		ehrpwm0: pwm@300000 {
@@ -402,6 +532,9 @@
 				     "ti,am33xx-ehrpwm";
 			#pwm-cells = <3>;
 			reg = <0x300000 0x2000>;
+			clocks = <&psc1 17>, <&ehrpwm_tbclk>;
+			clock-names = "fck", "tbclk";
+			power-domains = <&psc1 17>;
 			status = "disabled";
 		};
 		ehrpwm1: pwm@302000 {
@@ -409,6 +542,9 @@
 				     "ti,am33xx-ehrpwm";
 			#pwm-cells = <3>;
 			reg = <0x302000 0x2000>;
+			clocks = <&psc1 17>, <&ehrpwm_tbclk>;
+			clock-names = "fck", "tbclk";
+			power-domains = <&psc1 17>;
 			status = "disabled";
 		};
 		ecap0: ecap@306000 {
@@ -416,6 +552,9 @@
 				     "ti,am33xx-ecap";
 			#pwm-cells = <3>;
 			reg = <0x306000 0x80>;
+			clocks = <&psc1 20>;
+			clock-names = "fck";
+			power-domains = <&psc1 20>;
 			status = "disabled";
 		};
 		ecap1: ecap@307000 {
@@ -423,6 +562,9 @@
 				     "ti,am33xx-ecap";
 			#pwm-cells = <3>;
 			reg = <0x307000 0x80>;
+			clocks = <&psc1 20>;
+			clock-names = "fck";
+			power-domains = <&psc1 20>;
 			status = "disabled";
 		};
 		ecap2: ecap@308000 {
@@ -430,6 +572,9 @@
 				     "ti,am33xx-ecap";
 			#pwm-cells = <3>;
 			reg = <0x308000 0x80>;
+			clocks = <&psc1 20>;
+			clock-names = "fck";
+			power-domains = <&psc1 20>;
 			status = "disabled";
 		};
 		spi0: spi@41000 {
@@ -442,6 +587,8 @@
 			interrupts = <20>;
 			dmas = <&edma0 14 0>, <&edma0 15 0>;
 			dma-names = "rx", "tx";
+			clocks = <&psc0 4>;
+			power-domains = <&psc0 4>;
 			status = "disabled";
 		};
 		spi1: spi@30e000 {
@@ -454,6 +601,8 @@
 			interrupts = <56>;
 			dmas = <&edma0 18 0>, <&edma0 19 0>;
 			dma-names = "rx", "tx";
+			clocks = <&psc1 10>;
+			power-domains = <&psc1 10>;
 			status = "disabled";
 		};
 		usb0: usb@200000 {
@@ -465,6 +614,8 @@
 			dr_mode = "otg";
 			phys = <&usb_phy 0>;
 			phy-names = "usb-phy";
+			clocks = <&psc1 1>;
+			clock-ranges;
 			status = "disabled";
 
 			#address-cells = <1>;
@@ -488,6 +639,7 @@
 				interrupts = <58>;
 				#dma-cells = <2>;
 				#dma-channels = <4>;
+				power-domains = <&psc1 1>;
 				status = "okay";
 			};
 		};
@@ -495,13 +647,31 @@
 			compatible = "ti,da850-ahci";
 			reg = <0x218000 0x2000>, <0x22c018 0x4>;
 			interrupts = <67>;
+			clocks = <&psc1 8>, <&sata_refclk>;
+			clock-names = "fck", "refclk";
 			status = "disabled";
 		};
+		pll1: clock-controller@21a000 {
+			compatible = "ti,da850-pll1";
+			reg = <0x21a000 0x1000>;
+			clocks = <&ref_clk>;
+			clock-names = "clksrc";
+
+			pll1_sysclk: sysclk {
+				#clock-cells = <1>;
+			};
+			pll1_obsclk: obsclk {
+				#clock-cells = <0>;
+			};
+		};
 		mdio: mdio@224000 {
 			compatible = "ti,davinci_mdio";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x224000 0x1000>;
+			clocks = <&psc1 5>;
+			clock-names = "fck";
+			power-domains = <&psc1 5>;
 			status = "disabled";
 		};
 		eth0: ethernet@220000 {
@@ -517,6 +687,8 @@
 					35
 					36
 					>;
+			clocks = <&psc1 5>;
+			power-domains = <&psc1 5>;
 			status = "disabled";
 		};
 		usb1: usb@225000 {
@@ -525,6 +697,7 @@
 			interrupts = <59>;
 			phys = <&usb_phy 1>;
 			phy-names = "usb-phy";
+			clocks = <&psc1 2>;
 			status = "disabled";
 		};
 		gpio: gpio@226000 {
@@ -532,16 +705,169 @@
 			gpio-controller;
 			#gpio-cells = <2>;
 			reg = <0x226000 0x1000>;
-			interrupts = <42 IRQ_TYPE_EDGE_BOTH
-				43 IRQ_TYPE_EDGE_BOTH 44 IRQ_TYPE_EDGE_BOTH
-				45 IRQ_TYPE_EDGE_BOTH 46 IRQ_TYPE_EDGE_BOTH
-				47 IRQ_TYPE_EDGE_BOTH 48 IRQ_TYPE_EDGE_BOTH
-				49 IRQ_TYPE_EDGE_BOTH 50 IRQ_TYPE_EDGE_BOTH>;
+			interrupts = <42 43 44 45 46 47 48 49 50>;
 			ti,ngpio = <144>;
 			ti,davinci-gpio-unbanked = <0>;
+			clocks = <&psc1 3>;
+			clock-names = "gpio";
 			status = "disabled";
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			gpio-ranges = <&pmx_core   0  15 1>,
+				      <&pmx_core   1  14 1>,
+				      <&pmx_core   2  13 1>,
+				      <&pmx_core   3  12 1>,
+				      <&pmx_core   4  11 1>,
+				      <&pmx_core   5  10 1>,
+				      <&pmx_core   6   9 1>,
+				      <&pmx_core   7   8 1>,
+				      <&pmx_core   8   7 1>,
+				      <&pmx_core   9   6 1>,
+				      <&pmx_core  10   5 1>,
+				      <&pmx_core  11   4 1>,
+				      <&pmx_core  12   3 1>,
+				      <&pmx_core  13   2 1>,
+				      <&pmx_core  14   1 1>,
+				      <&pmx_core  15   0 1>,
+				      <&pmx_core  16  39 1>,
+				      <&pmx_core  17  38 1>,
+				      <&pmx_core  18  37 1>,
+				      <&pmx_core  19  36 1>,
+				      <&pmx_core  20  35 1>,
+				      <&pmx_core  21  34 1>,
+				      <&pmx_core  22  33 1>,
+				      <&pmx_core  23  32 1>,
+				      <&pmx_core  24  24 1>,
+				      <&pmx_core  25  22 1>,
+				      <&pmx_core  26  21 1>,
+				      <&pmx_core  27  20 1>,
+				      <&pmx_core  28  19 1>,
+				      <&pmx_core  29  18 1>,
+				      <&pmx_core  30  17 1>,
+				      <&pmx_core  31  16 1>,
+				      <&pmx_core  32  55 1>,
+				      <&pmx_core  33  54 1>,
+				      <&pmx_core  34  53 1>,
+				      <&pmx_core  35  52 1>,
+				      <&pmx_core  36  51 1>,
+				      <&pmx_core  37  50 1>,
+				      <&pmx_core  38  49 1>,
+				      <&pmx_core  39  48 1>,
+				      <&pmx_core  40  47 1>,
+				      <&pmx_core  41  46 1>,
+				      <&pmx_core  42  45 1>,
+				      <&pmx_core  43  44 1>,
+				      <&pmx_core  44  43 1>,
+				      <&pmx_core  45  42 1>,
+				      <&pmx_core  46  41 1>,
+				      <&pmx_core  47  40 1>,
+				      <&pmx_core  48  71 1>,
+				      <&pmx_core  49  70 1>,
+				      <&pmx_core  50  69 1>,
+				      <&pmx_core  51  68 1>,
+				      <&pmx_core  52  67 1>,
+				      <&pmx_core  53  66 1>,
+				      <&pmx_core  54  65 1>,
+				      <&pmx_core  55  64 1>,
+				      <&pmx_core  56  63 1>,
+				      <&pmx_core  57  62 1>,
+				      <&pmx_core  58  61 1>,
+				      <&pmx_core  59  60 1>,
+				      <&pmx_core  60  59 1>,
+				      <&pmx_core  61  58 1>,
+				      <&pmx_core  62  57 1>,
+				      <&pmx_core  63  56 1>,
+				      <&pmx_core  64  87 1>,
+				      <&pmx_core  65  86 1>,
+				      <&pmx_core  66  85 1>,
+				      <&pmx_core  67  84 1>,
+				      <&pmx_core  68  83 1>,
+				      <&pmx_core  69  82 1>,
+				      <&pmx_core  70  81 1>,
+				      <&pmx_core  71  80 1>,
+				      <&pmx_core  72  70 1>,
+				      <&pmx_core  73  78 1>,
+				      <&pmx_core  74  77 1>,
+				      <&pmx_core  75  76 1>,
+				      <&pmx_core  76  75 1>,
+				      <&pmx_core  77  74 1>,
+				      <&pmx_core  78  73 1>,
+				      <&pmx_core  79  72 1>,
+				      <&pmx_core  80 103 1>,
+				      <&pmx_core  81 102 1>,
+				      <&pmx_core  82 101 1>,
+				      <&pmx_core  83 100 1>,
+				      <&pmx_core  84  99 1>,
+				      <&pmx_core  85  98 1>,
+				      <&pmx_core  86  97 1>,
+				      <&pmx_core  87  96 1>,
+				      <&pmx_core  88  95 1>,
+				      <&pmx_core  89  94 1>,
+				      <&pmx_core  90  93 1>,
+				      <&pmx_core  91  92 1>,
+				      <&pmx_core  92  91 1>,
+				      <&pmx_core  93  90 1>,
+				      <&pmx_core  94  89 1>,
+				      <&pmx_core  95  88 1>,
+				      <&pmx_core  96 158 1>,
+				      <&pmx_core  97 157 1>,
+				      <&pmx_core  98 156 1>,
+				      <&pmx_core  99 155 1>,
+				      <&pmx_core 100 154 1>,
+				      <&pmx_core 101 129 1>,
+				      <&pmx_core 102 113 1>,
+				      <&pmx_core 103 112 1>,
+				      <&pmx_core 104 111 1>,
+				      <&pmx_core 105 110 1>,
+				      <&pmx_core 106 109 1>,
+				      <&pmx_core 107 108 1>,
+				      <&pmx_core 108 107 1>,
+				      <&pmx_core 109 106 1>,
+				      <&pmx_core 110 105 1>,
+				      <&pmx_core 111 104 1>,
+				      <&pmx_core 112 145 1>,
+				      <&pmx_core 113 144 1>,
+				      <&pmx_core 114 143 1>,
+				      <&pmx_core 115 142 1>,
+				      <&pmx_core 116 141 1>,
+				      <&pmx_core 117 140 1>,
+				      <&pmx_core 118 139 1>,
+				      <&pmx_core 119 138 1>,
+				      <&pmx_core 120 137 1>,
+				      <&pmx_core 121 136 1>,
+				      <&pmx_core 122 135 1>,
+				      <&pmx_core 123 134 1>,
+				      <&pmx_core 124 133 1>,
+				      <&pmx_core 125 132 1>,
+				      <&pmx_core 126 131 1>,
+				      <&pmx_core 127 130 1>,
+				      <&pmx_core 128 159 1>,
+				      <&pmx_core 129  31 1>,
+				      <&pmx_core 130  30 1>,
+				      <&pmx_core 131  20 1>,
+				      <&pmx_core 132  28 1>,
+				      <&pmx_core 133  27 1>,
+				      <&pmx_core 134  26 1>,
+				      <&pmx_core 135  23 1>,
+				      <&pmx_core 136 153 1>,
+				      <&pmx_core 137 152 1>,
+				      <&pmx_core 138 151 1>,
+				      <&pmx_core 139 150 1>,
+				      <&pmx_core 140 149 1>,
+				      <&pmx_core 141 148 1>,
+				      <&pmx_core 142 147 1>,
+				      <&pmx_core 143 146 1>;
+		};
+		psc1: clock-controller@227000 {
+			compatible = "ti,da850-psc1";
+			reg = <0x227000 0x1000>;
+			#clock-cells = <1>;
+			#power-domain-cells = <1>;
+			clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>,
+				 <&async3_clk>;
+			clock-names = "pll0_sysclk2", "pll0_sysclk4", "async3";
+			assigned-clocks = <&async3_clk>;
+			assigned-clock-parents = <&pll1_sysclk 2>;
 		};
 		pinconf: pin-controller@22c00c {
 			compatible = "ti,da850-pupd";
@@ -556,6 +882,7 @@
 			reg-names = "mpu", "dat";
 			interrupts = <54>;
 			interrupt-names = "common";
+			power-domains = <&psc1 7>;
 			status = "disabled";
 			dmas = <&edma0 1 1>,
 				<&edma0 0 1>;
@@ -567,6 +894,9 @@
 			reg = <0x213000 0x1000>;
 			interrupts = <52>;
 			max-pixelclock = <37500>;
+			clocks = <&psc1 16>;
+			clock-names = "fck";
+			power-domains = <&psc1 16>;
 			status = "disabled";
 		};
 	};
@@ -578,6 +908,9 @@
 		reg = <0x68000000 0x00008000>;
 		ranges = <0 0 0x60000000 0x08000000
 			  1 0 0x68000000 0x00008000>;
+		clocks = <&psc0 3>;
+		clock-names = "aemif";
+		clock-ranges;
 		status = "disabled";
 	};
 	memctrl: memory-controller@b0000000 {
diff --git a/arch/arm/dts/dm816x.dtsi b/arch/arm/dts/dm816x.dtsi
index 276211e..fe58faf 100644
--- a/arch/arm/dts/dm816x.dtsi
+++ b/arch/arm/dts/dm816x.dtsi
@@ -90,8 +90,6 @@
 			dm816x_pinmux: pinmux@800 {
 				compatible = "pinctrl-single";
 				reg = <0x800 0x50a>;
-				#address-cells = <1>;
-				#size-cells = <0>;
 				#pinctrl-cells = <1>;
 				pinctrl-single,register-width = <16>;
 				pinctrl-single,function-mask = <0xf>;
@@ -127,8 +125,6 @@
 			};
 
 			scrm_clocks: clocks {
-				#address-cells = <1>;
-				#size-cells = <0>;
 			};
 
 			scrm_clockdomains: clockdomains {
diff --git a/arch/arm/dts/logicpd-som-lv-35xx-devkit.dts b/arch/arm/dts/logicpd-som-lv-35xx-devkit.dts
index 4cd72b5..32d0dc3 100644
--- a/arch/arm/dts/logicpd-som-lv-35xx-devkit.dts
+++ b/arch/arm/dts/logicpd-som-lv-35xx-devkit.dts
@@ -15,18 +15,3 @@
 	model = "LogicPD Zoom OMAP35xx SOM-LV Development Kit";
 	compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3";
 };
-
-&omap3_pmx_core2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&hsusb2_2_pins>;
-	hsusb2_2_pins: pinmux_hsusb2_2_pins {
-		pinctrl-single,pins = <
-			OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)            /* etk_d10.hsusb2_clk */
-			OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)            /* etk_d11.hsusb2_stp */
-			OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d12.hsusb2_dir */
-			OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d13.hsusb2_nxt */
-			OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d14.hsusb2_data0 */
-			OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d15.hsusb2_data1 */
-		>;
-	};
-};
diff --git a/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts b/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts
index 2aca911..2428373 100644
--- a/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts
+++ b/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts
@@ -15,18 +15,3 @@
 	model = "LogicPD Zoom DM3730 SOM-LV Development Kit";
 	compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3";
 };
-
-&omap3_pmx_core2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&hsusb2_2_pins>;
-	hsusb2_2_pins: pinmux_hsusb2_2_pins {
-		pinctrl-single,pins = <
-			OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)            /* etk_d10.hsusb2_clk */
-			OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)            /* etk_d11.hsusb2_stp */
-			OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d12.hsusb2_dir */
-			OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d13.hsusb2_nxt */
-			OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d14.hsusb2_data0 */
-			OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d15.hsusb2_data1 */
-		>;
-	};
-};
diff --git a/arch/arm/dts/logicpd-som-lv.dtsi b/arch/arm/dts/logicpd-som-lv.dtsi
index 0348550..98b682a 100644
--- a/arch/arm/dts/logicpd-som-lv.dtsi
+++ b/arch/arm/dts/logicpd-som-lv.dtsi
@@ -129,7 +129,7 @@
 };
 
 &mmc3 {
-	interrupts-extended = <&intc 94>;
+	interrupts-extended = <&intc 94 &omap3_pmx_core 0x136>;
 	pinctrl-0 = <&mmc3_pins &wl127x_gpio>;
 	pinctrl-names = "default";
 	vmmc-supply = <&wl12xx_vmmc>;
@@ -232,20 +232,6 @@
 		>;
 	};
 
-	i2c2_pins: pinmux_i2c2_pins {
-		pinctrl-single,pins = <
-			OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0)	/* i2c2_scl */
-			OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0)	/* i2c2_sda */
-		>;
-	};
-
-	i2c3_pins: pinmux_i2c3_pins {
-		pinctrl-single,pins = <
-			OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0)	/* i2c3_scl */
-			OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0)	/* i2c3_sda */
-		>;
-	};
-
 	tsc2004_pins: pinmux_tsc2004_pins {
 		pinctrl-single,pins = <
 			OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4)	/* mcbsp4_dr.gpio_153 */
@@ -267,6 +253,33 @@
 			OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4)	/* sys_boot1.gpio_3 */
 		>;
 	};
+	i2c2_pins: pinmux_i2c2_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0)	/* i2c2_scl */
+			OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0)	/* i2c2_sda */
+		>;
+	};
+	i2c3_pins: pinmux_i2c3_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0)	/* i2c3_scl */
+			OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0)	/* i2c3_sda */
+		>;
+	};
+};
+
+&omap3_pmx_core2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hsusb2_2_pins>;
+	hsusb2_2_pins: pinmux_hsusb2_2_pins {
+		pinctrl-single,pins = <
+			OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)            /* etk_d10.hsusb2_clk */
+			OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)            /* etk_d11.hsusb2_stp */
+			OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d12.hsusb2_dir */
+			OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d13.hsusb2_nxt */
+			OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d14.hsusb2_data0 */
+			OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d15.hsusb2_data1 */
+		>;
+	};
 };
 
 &uart2 {
diff --git a/arch/arm/dts/logicpd-torpedo-37xx-devkit.dts b/arch/arm/dts/logicpd-torpedo-37xx-devkit.dts
index 9d5d53f..c39cf2c 100644
--- a/arch/arm/dts/logicpd-torpedo-37xx-devkit.dts
+++ b/arch/arm/dts/logicpd-torpedo-37xx-devkit.dts
@@ -35,7 +35,7 @@
  * jumpering combinations for the long run.
  */
 &mmc3 {
-	interrupts-extended = <&intc 94 &omap3_pmx_core2 0x46>;
+	interrupts-extended = <&intc 94 &omap3_pmx_core 0x136>;
 	pinctrl-0 = <&mmc3_pins &mmc3_core2_pins>;
 	pinctrl-names = "default";
 	vmmc-supply = <&wl12xx_vmmc>;
diff --git a/arch/arm/dts/omap5-u-boot.dtsi b/arch/arm/dts/omap5-u-boot.dtsi
index bf2684c..a6a7801 100644
--- a/arch/arm/dts/omap5-u-boot.dtsi
+++ b/arch/arm/dts/omap5-u-boot.dtsi
@@ -15,6 +15,10 @@
 	ocp {
 		u-boot,dm-spl;
 
+		ocp2scp@4a080000 {
+			compatible = "ti,omap-ocp2scp", "simple-bus";
+		};
+
 		ocp2scp@4a090000 {
 			compatible = "ti,omap-ocp2scp", "simple-bus";
 		};
diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
index f8b7701..7a9b742 100644
--- a/arch/arm/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/dts/stm32mp157c-ed1.dts
@@ -365,6 +365,14 @@
 	usb33d-supply = <&usb33>;
 };
 
+&hwspinlock {
+	status = "okay";
+};
+
+&pinctrl {
+	hwlocks = <&hwspinlock 0>;
+};
+
 &usbphyc_port0 {
 	phy-supply = <&vdd_usb>;
 	vdda1v1-supply = <&reg11>;
diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi
index 33c5981..37cadfa 100644
--- a/arch/arm/dts/stm32mp157c.dtsi
+++ b/arch/arm/dts/stm32mp157c.dtsi
@@ -690,6 +690,15 @@
 			status = "disabled";
 		};
 
+		hwspinlock: hwspinlock@4c000000 {
+			compatible = "st,stm32-hwspinlock";
+			#hwlock-cells = <1>;
+			reg = <0x4c000000 0x400>;
+			clocks = <&rcc HSEM>;
+			clock-names = "hwspinlock";
+			status = "disabled";
+		};
+
 		rcc: rcc@50000000 {
 			compatible = "st,stm32mp1-rcc", "syscon";
 			reg = <0x50000000 0x1000>;
diff --git a/arch/arm/include/asm/arch-stm32/gpio.h b/arch/arm/include/asm/arch-stm32/gpio.h
index 84859b1..570e80a 100644
--- a/arch/arm/include/asm/arch-stm32/gpio.h
+++ b/arch/arm/include/asm/arch-stm32/gpio.h
@@ -7,6 +7,8 @@
 #ifndef _GPIO_H_
 #define _GPIO_H_
 
+#define STM32_GPIOS_PER_BANK		16
+
 enum stm32_gpio_port {
 	STM32_GPIO_PORT_A = 0,
 	STM32_GPIO_PORT_B,
@@ -109,6 +111,9 @@
 
 struct stm32_gpio_priv {
 	struct stm32_gpio_regs *regs;
+	unsigned int gpio_range;
 };
 
+int stm32_offset_to_index(struct udevice *dev, unsigned int offset);
+
 #endif /* _GPIO_H_ */
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 5df7472..12bc7fb 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -160,7 +160,12 @@
 #define in_be32(a)	in_arch(l,be32,a)
 #define in_be16(a)	in_arch(w,be16,a)
 
+#define out_32(a,v)	__raw_writel(v,a)
+#define out_16(a,v)	__raw_writew(v,a)
 #define out_8(a,v)	__raw_writeb(v,a)
+
+#define in_32(a)	__raw_readl(a)
+#define in_16(a)	__raw_readw(a)
 #define in_8(a)		__raw_readb(a)
 
 #define clrbits(type, addr, clear) \
@@ -180,6 +185,10 @@
 #define setbits_le32(addr, set) setbits(le32, addr, set)
 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
 
+#define clrbits_32(addr, clear) clrbits(32, addr, clear)
+#define setbits_32(addr, set) setbits(32, addr, set)
+#define clrsetbits_32(addr, clear, set) clrsetbits(32, addr, clear, set)
+
 #define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
 #define setbits_be16(addr, set) setbits(be16, addr, set)
 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
@@ -188,6 +197,10 @@
 #define setbits_le16(addr, set) setbits(le16, addr, set)
 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
 
+#define clrbits_16(addr, clear) clrbits(16, addr, clear)
+#define setbits_16(addr, set) setbits(16, addr, set)
+#define clrsetbits_16(addr, clear, set) clrsetbits(16, addr, clear, set)
+
 #define clrbits_8(addr, clear) clrbits(8, addr, clear)
 #define setbits_8(addr, set) setbits(8, addr, set)
 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
diff --git a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
index eca78f8..b714e93 100644
--- a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
+++ b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
@@ -48,3 +48,13 @@
 		__bss_end = .;
 	} >.sdram
 }
+
+#if defined(CONFIG_SPL_MAX_SIZE)
+ASSERT(__image_copy_end - __start < (CONFIG_SPL_MAX_SIZE), \
+	"SPL image too big");
+#endif
+
+#if defined(CONFIG_SPL_BSS_MAX_SIZE)
+ASSERT(__bss_end - __bss_start < (CONFIG_SPL_BSS_MAX_SIZE), \
+	"SPL image BSS too big");
+#endif
diff --git a/arch/arm/mach-stm32mp/include/mach/gpio.h b/arch/arm/mach-stm32mp/include/mach/gpio.h
index 5151150..5ca76d2 100644
--- a/arch/arm/mach-stm32mp/include/mach/gpio.h
+++ b/arch/arm/mach-stm32mp/include/mach/gpio.h
@@ -8,6 +8,8 @@
 #define _STM32_GPIO_H_
 #include <asm/gpio.h>
 
+#define STM32_GPIOS_PER_BANK		16
+
 enum stm32_gpio_port {
 	STM32_GPIO_PORT_A = 0,
 	STM32_GPIO_PORT_B,
@@ -110,5 +112,9 @@
 
 struct stm32_gpio_priv {
 	struct stm32_gpio_regs *regs;
+	unsigned int gpio_range;
 };
+
+int stm32_offset_to_index(struct udevice *dev, unsigned int offset);
+
 #endif /* _STM32_GPIO_H_ */
diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c
index 5d91d7e..dea42de 100644
--- a/arch/arm/mach-sunxi/pmic_bus.c
+++ b/arch/arm/mach-sunxi/pmic_bus.c
@@ -101,6 +101,9 @@
 	if (ret)
 		return ret;
 
+	if ((val & bits) == bits)
+		return 0;
+
 	val |= bits;
 	return pmic_bus_write(reg, val);
 }
@@ -114,6 +117,9 @@
 	if (ret)
 		return ret;
 
+	if (!(val & bits))
+		return 0;
+
 	val &= ~bits;
 	return pmic_bus_write(reg, val);
 }
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 6722e18..6b1c269 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -460,6 +460,8 @@
 
 		test4 {
 			compatible = "denx,u-boot-probe-test";
+			first-syscon = <&syscon0>;
+			second-sys-ctrl = <&another_system_controller>;
 		};
 	};
 
@@ -540,12 +542,12 @@
 		};
 	};
 
-	syscon@0 {
+	syscon0: syscon@0 {
 		compatible = "sandbox,syscon0";
 		reg = <0x10 16>;
 	};
 
-	syscon@1 {
+	another_system_controller: syscon@1 {
 		compatible = "sandbox,syscon1";
 		reg = <0x20 5
 			0x28 6
@@ -742,6 +744,18 @@
 	pinctrl {
 		compatible = "sandbox,pinctrl";
 	};
+
+	hwspinlock@0 {
+		compatible = "sandbox,hwspinlock";
+	};
+
+	dma: dma {
+		compatible = "sandbox,dma";
+		#dma-cells = <1>;
+
+		dmas = <&dma 0>, <&dma 1>, <&dma 2>;
+		dma-names = "m2m", "tx0", "rx0";
+	};
 };
 
 #include "sandbox_pmic.dtsi"
diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h
index 5a14485..c724827 100644
--- a/arch/sandbox/include/asm/state.h
+++ b/arch/sandbox/include/asm/state.h
@@ -101,6 +101,7 @@
 
 	ulong next_tag;			/* Next address tag to allocate */
 	struct list_head mapmem_head;	/* struct sandbox_mapmem_entry */
+	bool hwspinlock;		/* Hardware Spinlock status */
 };
 
 /* Minimum space we guarantee in the state FDT when calling read/write*/
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index a1c18d2..e052093 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -729,13 +729,22 @@
 	  maximum number of PCI buses as defined by the PCI specification.
 
 config I8259_PIC
-	bool
+	bool "Enable Intel 8259 compatible interrupt controller"
 	default y
 	help
 	  Intel 8259 ISA compatible chipset incorporates two 8259 (master and
 	  slave) interrupt controllers. Include this to have U-Boot set up
 	  the interrupt correctly.
 
+config APIC
+	bool "Enable Intel Advanced Programmable Interrupt Controller"
+	default y
+	help
+	  The (A)dvanced (P)rogrammable (I)nterrupt (C)ontroller is responsible
+	  for catching interrupts and distributing them to one or more CPU
+	  cores. In most cases there are some LAPICs (local) for each core and
+	  one I/O APIC. This conjunction is found on most modern x86 systems.
+
 config PINCTRL_ICH6
 	bool
 	help
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index f862d8c..54668aa 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -35,7 +35,7 @@
 obj-$(CONFIG_INTEL_QUARK) += quark/
 obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/
 obj-$(CONFIG_INTEL_TANGIER) += tangier/
-obj-y += lapic.o ioapic.o
+obj-$(CONFIG_APIC) += lapic.o ioapic.o
 obj-y += irq.o
 ifndef CONFIG_$(SPL_)X86_64
 obj-$(CONFIG_SMP) += mp_init.o
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index aaf0d07..4c6ed0b 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -77,7 +77,8 @@
 		timestamp_add_to_bootstage();
 
 	/* start usb so that usb keyboard can be used as input device */
-	usb_init();
+	if (CONFIG_IS_ENABLED(USB_KEYBOARD))
+		usb_init();
 
 	board_final_cleanup();
 
diff --git a/arch/x86/cpu/efi/payload.c b/arch/x86/cpu/efi/payload.c
index c323c7b..225aef7 100644
--- a/arch/x86/cpu/efi/payload.c
+++ b/arch/x86/cpu/efi/payload.c
@@ -166,7 +166,8 @@
 int last_stage_init(void)
 {
 	/* start usb so that usb keyboard can be used as input device */
-	usb_init();
+	if (CONFIG_IS_ENABLED(USB_KEYBOARD))
+		usb_init();
 
 	return 0;
 }
diff --git a/arch/x86/cpu/i386/interrupt.c b/arch/x86/cpu/i386/interrupt.c
index ed8423e..1ea415b 100644
--- a/arch/x86/cpu/i386/interrupt.c
+++ b/arch/x86/cpu/i386/interrupt.c
@@ -264,7 +264,9 @@
 	i8259_init();
 #endif
 
+#ifdef CONFIG_APIC
 	lapic_setup();
+#endif
 
 	/* Initialize core interrupt and exception functionality of CPU */
 	cpu_init_interrupts();
diff --git a/arch/x86/include/asm/arch-tangier/acpi/platform.asl b/arch/x86/include/asm/arch-tangier/acpi/platform.asl
index 7abea4b..353b879 100644
--- a/arch/x86/include/asm/arch-tangier/acpi/platform.asl
+++ b/arch/x86/include/asm/arch-tangier/acpi/platform.asl
@@ -21,6 +21,19 @@
     Return (Package() {0, 0})
 }
 
+Scope (_SB)
+{
+    /* Real Time Clock */
+    Device (RTC0)
+    {
+        Name (_HID, EisaId ("PNP0B00"))
+        Name (_CRS, ResourceTemplate()
+        {
+            IO(Decode16, 0x70, 0x70, 0x01, 0x08)
+        })
+    }
+}
+
 /* ACPI global NVS */
 #include "global_nvs.asl"
 
diff --git a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
index 48193ba..e166e51 100644
--- a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
+++ b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
@@ -295,16 +295,16 @@
 
             Method (_CRS, 0, Serialized)
             {
-                Name (RBUF, ResourceTemplate ()
+                Name (RBUF, ResourceTemplate()
                 {
-                    UartSerialBus (0x0001C200, DataBitsEight, StopBitsOne,
+                    UartSerialBus(0x0001C200, DataBitsEight, StopBitsOne,
                         0xFC, LittleEndian, ParityTypeNone, FlowControlHardware,
                         0x20, 0x20, "\\_SB.PCI0.HSU0", 0, ResourceConsumer, , )
-                    GpioInt (Level, ActiveHigh, Exclusive, PullNone, 0,
+                    GpioInt(Level, ActiveHigh, Exclusive, PullNone, 0,
                         "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 185 }
-                    GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly,
+                    GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly,
                         "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 184 }
-                    GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly,
+                    GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly,
                         "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 71 }
                 })
                 Return (RBUF)
@@ -328,7 +328,7 @@
     Name (_DDN, "Intel Merrifield Family-Level Interface Shim")
     Name (RBUF, ResourceTemplate()
     {
-        Memory32Fixed(ReadWrite, 0xFF0C0000, 0x00008000, )
+        Memory32Fixed(ReadWrite, 0xFF0C0000, 0x00008000)
         PinGroup("spi5", ResourceProducer, ) { 90, 91, 92, 93, 94, 95, 96 }
         PinGroup("uart0", ResourceProducer, ) { 115, 116, 117, 118 }
         PinGroup("uart1", ResourceProducer, ) { 119, 120, 121, 122 }
diff --git a/arch/x86/lib/interrupts.c b/arch/x86/lib/interrupts.c
index 297067d..39f8dea 100644
--- a/arch/x86/lib/interrupts.c
+++ b/arch/x86/lib/interrupts.c
@@ -64,7 +64,8 @@
 	irq_handlers[irq].arg = arg;
 	irq_handlers[irq].count = 0;
 
-	unmask_irq(irq);
+	if (CONFIG_IS_ENABLED(I8259_PIC))
+		unmask_irq(irq);
 
 	if (status)
 		enable_interrupts();
@@ -83,7 +84,8 @@
 
 	status = disable_interrupts();
 
-	mask_irq(irq);
+	if (CONFIG_IS_ENABLED(I8259_PIC))
+		mask_irq(irq);
 
 	irq_handlers[irq].handler = NULL;
 	irq_handlers[irq].arg = NULL;
@@ -104,14 +106,16 @@
 	}
 
 	if (irq_handlers[irq].handler) {
-		mask_irq(irq);
+		if (CONFIG_IS_ENABLED(I8259_PIC))
+			mask_irq(irq);
 
 		irq_handlers[irq].handler(irq_handlers[irq].arg);
 		irq_handlers[irq].count++;
 
-		unmask_irq(irq);
-		specific_eoi(irq);
-
+		if (CONFIG_IS_ENABLED(I8259_PIC)) {
+			unmask_irq(irq);
+			specific_eoi(irq);
+		}
 	} else {
 		if ((irq & 7) != 7) {
 			spurious_irq_cnt++;
diff --git a/board/8dtech/eco5pk/eco5pk.c b/board/8dtech/eco5pk/eco5pk.c
index e05928f..dcbd483 100644
--- a/board/8dtech/eco5pk/eco5pk.c
+++ b/board/8dtech/eco5pk/eco5pk.c
@@ -16,7 +16,7 @@
 #include <asm/arch/emac_defs.h>
 #include <asm/gpio.h>
 #include <i2c.h>
-#include <crc.h>
+#include <u-boot/crc.h>
 #include <asm/mach-types.h>
 #include "eco5pk.h"
 
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c
index 160d30c..1f7650c 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -212,7 +212,7 @@
 	    SPEED_BIN_DDR_1600K,	/* speed_bin */
 	    MV_DDR_DEV_WIDTH_16BIT,	/* memory_width */
 	    MV_DDR_DIE_CAP_4GBIT,			/* mem_size */
-	    DDR_FREQ_800,		/* frequency */
+	    MV_DDR_FREQ_800,		/* frequency */
 	    0, 0,			/* cas_wl cas_l */
 	    MV_DDR_TEMP_NORMAL,		/* temperature */
 	    MV_DDR_TIM_2T} },		/* timing */
@@ -234,7 +234,7 @@
 	    SPEED_BIN_DDR_1600K,	/* speed_bin */
 	    MV_DDR_DEV_WIDTH_16BIT,	/* memory_width */
 	    MV_DDR_DIE_CAP_8GBIT,			/* mem_size */
-	    DDR_FREQ_800,		/* frequency */
+	    MV_DDR_FREQ_800,		/* frequency */
 	    0, 0,			/* cas_wl cas_l */
 	    MV_DDR_TEMP_NORMAL,		/* temperature */
 	    MV_DDR_TIM_2T} },		/* timing */
diff --git a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
index 92d7ae7..bc18fe6 100644
--- a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
+++ b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
@@ -67,7 +67,7 @@
 	    SPEED_BIN_DDR_1866L,	/* speed_bin */
 	    MV_DDR_DEV_WIDTH_8BIT,	/* memory_width */
 	    MV_DDR_DIE_CAP_2GBIT,	/* mem_size */
-	    DDR_FREQ_800,		/* frequency */
+	    MV_DDR_FREQ_800,		/* frequency */
 	    0, 0,			/* cas_wl cas_l */
 	    MV_DDR_TEMP_LOW,		/* temperature */
 	    MV_DDR_TIM_DEFAULT} },	/* timing */
diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
index a8cfe8a..9368bce 100644
--- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
+++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
@@ -88,7 +88,7 @@
 	    SPEED_BIN_DDR_1866L,	/* speed_bin */
 	    MV_DDR_DEV_WIDTH_8BIT,	/* memory_width */
 	    MV_DDR_DIE_CAP_4GBIT,	/* mem_size */
-	    DDR_FREQ_800,		/* frequency */
+	    MV_DDR_FREQ_800,		/* frequency */
 	    0, 0,			/* cas_wl cas_l */
 	    MV_DDR_TEMP_LOW,		/* temperature */
 	    MV_DDR_TIM_DEFAULT} },	/* timing */
diff --git a/board/armadeus/apf27/apf27.c b/board/armadeus/apf27/apf27.c
index 0f0c8a4..bf2586d 100644
--- a/board/armadeus/apf27/apf27.c
+++ b/board/armadeus/apf27/apf27.c
@@ -16,8 +16,8 @@
 #include <asm/arch/gpio.h>
 #include <asm/gpio.h>
 #include <linux/errno.h>
+#include <u-boot/crc.h>
 #include "apf27.h"
-#include "crc.h"
 #include "fpga.h"
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c
index dd4c083..86051ae 100644
--- a/board/gdsys/a38x/controlcenterdc.c
+++ b/board/gdsys/a38x/controlcenterdc.c
@@ -64,7 +64,7 @@
 	    SPEED_BIN_DDR_1600K,	/* speed_bin */
 	    MV_DDR_DEV_WIDTH_16BIT,	/* memory_width */
 	    MV_DDR_DIE_CAP_4GBIT,	/* mem_size */
-	    DDR_FREQ_533,		/* frequency */
+	    MV_DDR_FREQ_533,		/* frequency */
 	    0, 0,			/* cas_wl cas_l */
 	    MV_DDR_TEMP_LOW,		/* temperature */
 	    MV_DDR_TIM_DEFAULT} },	/* timing */
diff --git a/board/kobol/helios4/helios4.c b/board/kobol/helios4/helios4.c
index 3416783..8c0864b 100644
--- a/board/kobol/helios4/helios4.c
+++ b/board/kobol/helios4/helios4.c
@@ -33,18 +33,6 @@
 #define BOARD_GPP_POL_LOW	0x0
 #define BOARD_GPP_POL_MID	0x0
 
-/* IO expander on Marvell GP board includes e.g. fan enabling */
-struct marvell_io_exp {
-	u8 addr;
-	u8 val;
-};
-
-static struct marvell_io_exp io_exp[] = {
-	{6, 0xf9},
-	{2, 0x46}, /* Assert reset signals and enable USB3 current limiter */
-	{6, 0xb9}
-};
-
 static struct serdes_map board_serdes_map[] = {
 	{SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
 	{USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
@@ -78,7 +66,7 @@
 	    SPEED_BIN_DDR_1600K,	/* speed_bin */
 	    MV_DDR_DEV_WIDTH_16BIT,	/* memory_width */
 	    MV_DDR_DIE_CAP_8GBIT,	/* mem_size */
-	    DDR_FREQ_800,		/* frequency */
+	    MV_DDR_FREQ_800,		/* frequency */
 	    0, 0,			/* cas_wl cas_l */
 	    MV_DDR_TEMP_LOW,		/* temperature */
 	    MV_DDR_TIM_DEFAULT} },	/* timing */
@@ -123,29 +111,9 @@
 
 int board_init(void)
 {
-	int i;
-
 	/* Address of boot parameters */
 	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 
-	/* Init I2C IO expanders */
-	for (i = 0; i < ARRAY_SIZE(io_exp); i++) {
-		struct udevice *dev;
-		int ret;
-
-		ret = i2c_get_chip_for_busnum(0, io_exp[i].addr, 1, &dev);
-		if (ret) {
-			printf("Cannot find I2C: %d\n", ret);
-			return 0;
-		}
-
-		ret = dm_i2c_write(dev, io_exp[i].val, &io_exp[i].val, 1);
-		if (ret) {
-			printf("Failed to set IO expander via I2C\n");
-			return -EIO;
-		}
-	}
-
 	return 0;
 }
 
diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c
index 4e1386c..1742aa8 100644
--- a/board/solidrun/clearfog/clearfog.c
+++ b/board/solidrun/clearfog/clearfog.c
@@ -65,7 +65,7 @@
 	    SPEED_BIN_DDR_1600K,	/* speed_bin */
 	    MV_DDR_DEV_WIDTH_16BIT,	/* memory_width */
 	    MV_DDR_DIE_CAP_4GBIT,	/* mem_size */
-	    DDR_FREQ_800,		/* frequency */
+	    MV_DDR_FREQ_800,		/* frequency */
 	    0, 0,			/* cas_wl cas_l */
 	    MV_DDR_TEMP_LOW,		/* temperature */
 	    MV_DDR_TIM_DEFAULT} },	/* timing */
diff --git a/board/sunxi/README.sunxi64 b/board/sunxi/README.sunxi64
index bba2e01..258921a 100644
--- a/board/sunxi/README.sunxi64
+++ b/board/sunxi/README.sunxi64
@@ -12,8 +12,13 @@
 Quick Start / Overview
 ======================
 - Build the ARM Trusted Firmware binary (see "ARM Trusted Firmware (ATF)" below)
+  $ cd /src/arm-trusted-firmware
+  $ make PLAT=sun50i_a64 DEBUG=1 bl31
 - Build U-Boot (see "SPL/U-Boot" below)
+  $ export BL31=/path/to/bl31.bin
+  $ make pine64_plus_defconfig && make -j5
 - Transfer to an uSD card (see "microSD card" below)
+  $ dd if=u-boot-sunxi-with-spl.bin of=/dev/sdx bs=8k seek=1
 - Boot and enjoy!
 
 Building the firmware
@@ -29,14 +34,18 @@
 
  ARM Trusted Firmware (ATF)
 ----------------------------
-Checkout the "allwinner" branch from the github repository [1] and build it:
+Checkout the latest master branch from the official ATF repository [1] and
+build it:
 $ export CROSS_COMPILE=aarch64-linux-gnu-
-$ make PLAT=sun50iw1p1 DEBUG=1 bl31
-The resulting binary is build/sun50iw1p1/debug/bl31.bin. Either put the
+$ make PLAT=sun50i_a64 DEBUG=1 bl31
+The resulting binary is build/sun50i_a64/debug/bl31.bin. Either put the
 location of this file into the BL31 environment variable or copy this to
 the root of your U-Boot build directory (or create a symbolic link).
-$ export BL31=/src/arm-trusted-firmware/build/sun50iw1p1/debug/bl31.bin
+$ export BL31=/src/arm-trusted-firmware/build/sun50i_a64/debug/bl31.bin
   (adjust the actual path accordingly)
+The platform target "sun50i_a64" covers all boards with either an Allwinner
+A64 or H5 SoC (since they are very similar). For boards with an Allwinner H6
+SoC use "sun50i_h6".
 
 If you run into size issues with the resulting U-Boot image file, it might
 help to use a release build, by using "DEBUG=0" when building bl31.bin.
@@ -59,7 +68,8 @@
 $ make
 
 This will build the SPL in spl/sunxi-spl.bin and a FIT image called u-boot.itb,
-which contains the rest of the firmware.
+which contains the rest of the firmware. u-boot-sunxi-with-spl.bin joins those
+two components in one convenient image file.
 
 
 Boot process
@@ -91,6 +101,9 @@
 As the FEL mode is controlled by the boot ROM, it expects to be running in
 AArch32. For now the AArch64 SPL cannot properly return into FEL mode, so the
 feature is disabled in the configuration at the moment.
+The repository in [3] contains FEL capable SPL binaries, built using an
+off-tree branch to generate 32-bit ARM code (along with instructions
+how to re-create them).
 
 microSD card
 ------------
@@ -165,6 +178,6 @@
 device file (see above):
 $ dd if=firmware.img of=/dev/sdx bs=8k seek=1
 
-[1] https://github.com/apritzel/arm-trusted-firmware.git
+[1] https://github.com/ARM-software/arm-trusted-firmware.git
 [2] git://github.com/linux-sunxi/sunxi-tools.git
 [3] https://github.com/apritzel/pine64/
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 64ccbc7..917f5b1 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -28,7 +28,7 @@
 #endif
 #include <asm/gpio.h>
 #include <asm/io.h>
-#include <crc.h>
+#include <u-boot/crc.h>
 #include <environment.h>
 #include <linux/libfdt.h>
 #include <nand.h>
@@ -637,13 +637,6 @@
 	power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
 #endif
 #endif
-	printf("DRAM:");
-	gd->ram_size = sunxi_dram_init();
-	printf(" %d MiB\n", (int)(gd->ram_size >> 20));
-	if (!gd->ram_size)
-		hang();
-
-	sunxi_spl_store_dram_size(gd->ram_size);
 
 	/*
 	 * Only clock up the CPU to full speed if we are reasonably
@@ -652,7 +645,16 @@
 	if (!power_failed)
 		clock_set_pll1(CONFIG_SYS_CLK_FREQ);
 	else
-		printf("Failed to set core voltage! Can't set CPU frequency\n");
+		printf("Error setting up the power controller.\n"
+		       "CPU frequency not set.\n");
+
+	printf("DRAM:");
+	gd->ram_size = sunxi_dram_init();
+	printf(" %d MiB\n", (int)(gd->ram_size >> 20));
+	if (!gd->ram_size)
+		hang();
+
+	sunxi_spl_store_dram_size(gd->ram_size);
 }
 #endif
 
@@ -663,7 +665,7 @@
 	struct phy phy;
 	int ret;
 
-	ret = uclass_get_device(UCLASS_USB_DEV_GENERIC, 0, &dev);
+	ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
 	if (ret) {
 		pr_err("%s: Cannot find USB device\n", __func__);
 		return ret;
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 177a324..8dfb2ee 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -675,6 +675,19 @@
 	return;
 }
 
+#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
+static int device_okay(const char *path)
+{
+	int node;
+
+	node = fdt_path_offset(gd->fdt_blob, path);
+	if (node < 0)
+		return 0;
+
+	return fdtdec_get_is_enabled(gd->fdt_blob, node);
+}
+#endif
+
 int board_late_init(void)
 {
 	setup_board_eeprom_env();
@@ -714,6 +727,12 @@
 	board_ti_set_ethaddr(2);
 #endif
 
+#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
+	if (device_okay("/ocp/omap_dwc3_1@48880000"))
+		enable_usb_clocks(0);
+	if (device_okay("/ocp/omap_dwc3_2@488c0000"))
+		enable_usb_clocks(1);
+#endif
 	return 0;
 }
 
@@ -864,93 +883,6 @@
 }
 #endif
 
-#ifdef CONFIG_USB_DWC3
-static struct dwc3_device usb_otg_ss2 = {
-	.maximum_speed = USB_SPEED_HIGH,
-	.base = DRA7_USB_OTG_SS2_BASE,
-	.tx_fifo_resize = false,
-	.index = 1,
-};
-
-static struct dwc3_omap_device usb_otg_ss2_glue = {
-	.base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
-	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
-	.index = 1,
-};
-
-static struct ti_usb_phy_device usb_phy2_device = {
-	.usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
-	.index = 1,
-};
-
-int usb_gadget_handle_interrupts(int index)
-{
-	u32 status;
-
-	status = dwc3_omap_uboot_interrupt_status(index);
-	if (status)
-		dwc3_uboot_handle_interrupt(index);
-
-	return 0;
-}
-#endif /* CONFIG_USB_DWC3 */
-
-#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
-int board_usb_init(int index, enum usb_init_type init)
-{
-	enable_usb_clocks(index);
-	switch (index) {
-	case 0:
-		if (init == USB_INIT_DEVICE) {
-			printf("port %d can't be used as device\n", index);
-			disable_usb_clocks(index);
-			return -EINVAL;
-		}
-		break;
-	case 1:
-		if (init == USB_INIT_DEVICE) {
-#ifdef CONFIG_USB_DWC3
-			usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
-			usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
-			ti_usb_phy_uboot_init(&usb_phy2_device);
-			dwc3_omap_uboot_init(&usb_otg_ss2_glue);
-			dwc3_uboot_init(&usb_otg_ss2);
-#endif
-		} else {
-			printf("port %d can't be used as host\n", index);
-			disable_usb_clocks(index);
-			return -EINVAL;
-		}
-
-		break;
-	default:
-		printf("Invalid Controller Index\n");
-	}
-
-	return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-#ifdef CONFIG_USB_DWC3
-	switch (index) {
-	case 0:
-	case 1:
-		if (init == USB_INIT_DEVICE) {
-			ti_usb_phy_uboot_exit(index);
-			dwc3_uboot_exit(index);
-			dwc3_omap_uboot_exit(index);
-		}
-		break;
-	default:
-		printf("Invalid Controller Index\n");
-	}
-#endif
-	disable_usb_clocks(index);
-	return 0;
-}
-#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
-
 #ifdef CONFIG_DRIVER_TI_CPSW
 
 /* Delay value to add to calibrated value */
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index bbe5445..d69641e 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -646,6 +646,19 @@
 	return 0;
 }
 
+#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
+static int device_okay(const char *path)
+{
+	int node;
+
+	node = fdt_path_offset(gd->fdt_blob, path);
+	if (node < 0)
+		return 0;
+
+	return fdtdec_get_is_enabled(gd->fdt_blob, node);
+}
+#endif
+
 int board_late_init(void)
 {
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
@@ -685,6 +698,12 @@
 	if (board_is_dra71x_evm())
 		palmas_i2c_write_u8(LP873X_I2C_SLAVE_ADDR, 0x9, 0x7);
 #endif
+#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
+	if (device_okay("/ocp/omap_dwc3_1@48880000"))
+		enable_usb_clocks(0);
+	if (device_okay("/ocp/omap_dwc3_2@488c0000"))
+		enable_usb_clocks(1);
+#endif
 	return 0;
 }
 
@@ -893,110 +912,6 @@
 	default:
 		return NULL;
 	}
-}
-#endif
-
-#ifdef CONFIG_USB_DWC3
-static struct dwc3_device usb_otg_ss1 = {
-	.maximum_speed = USB_SPEED_SUPER,
-	.base = DRA7_USB_OTG_SS1_BASE,
-	.tx_fifo_resize = false,
-	.index = 0,
-};
-
-static struct dwc3_omap_device usb_otg_ss1_glue = {
-	.base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
-	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
-	.index = 0,
-};
-
-static struct ti_usb_phy_device usb_phy1_device = {
-	.pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
-	.usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
-	.usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
-	.index = 0,
-};
-
-static struct dwc3_device usb_otg_ss2 = {
-	.maximum_speed = USB_SPEED_SUPER,
-	.base = DRA7_USB_OTG_SS2_BASE,
-	.tx_fifo_resize = false,
-	.index = 1,
-};
-
-static struct dwc3_omap_device usb_otg_ss2_glue = {
-	.base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
-	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
-	.index = 1,
-};
-
-static struct ti_usb_phy_device usb_phy2_device = {
-	.usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
-	.index = 1,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-	enable_usb_clocks(index);
-	switch (index) {
-	case 0:
-		if (init == USB_INIT_DEVICE) {
-			usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
-			usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
-		} else {
-			usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
-			usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
-		}
-
-		ti_usb_phy_uboot_init(&usb_phy1_device);
-		dwc3_omap_uboot_init(&usb_otg_ss1_glue);
-		dwc3_uboot_init(&usb_otg_ss1);
-		break;
-	case 1:
-		if (init == USB_INIT_DEVICE) {
-			usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
-			usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
-		} else {
-			usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
-			usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
-		}
-
-		ti_usb_phy_uboot_init(&usb_phy2_device);
-		dwc3_omap_uboot_init(&usb_otg_ss2_glue);
-		dwc3_uboot_init(&usb_otg_ss2);
-		break;
-	default:
-		printf("Invalid Controller Index\n");
-	}
-
-	return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-	switch (index) {
-	case 0:
-	case 1:
-		ti_usb_phy_uboot_exit(index);
-		dwc3_uboot_exit(index);
-		dwc3_omap_uboot_exit(index);
-		break;
-	default:
-		printf("Invalid Controller Index\n");
-	}
-	disable_usb_clocks(index);
-	return 0;
-}
-
-int usb_gadget_handle_interrupts(int index)
-{
-	u32 status;
-
-	status = dwc3_omap_uboot_interrupt_status(index);
-	if (status)
-		dwc3_uboot_handle_interrupt(index);
-
-	return 0;
 }
 #endif
 
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index 72709c0..3e06800 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -59,6 +59,11 @@
 	return 0;
 }
 
+struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
+{
+	return (struct image_header *)(CONFIG_SYS_TEXT_BASE);
+}
+
 int board_init(void)
 {
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c
index 979ac4a..7f88c1e 100644
--- a/cmd/bootmenu.c
+++ b/cmd/bootmenu.c
@@ -351,6 +351,12 @@
 	}
 
 	menu->count = i;
+
+	if ((menu->active >= menu->count)||(menu->active < 0)) { //ensure active menuitem is inside menu
+		printf("active menuitem (%d) is outside menu (0..%d)\n",menu->active,menu->count-1);
+		menu->active=0;
+	}
+
 	return menu;
 
 cleanup:
diff --git a/cmd/fastboot.c b/cmd/fastboot.c
index ae3a5f6..0be83b7 100644
--- a/cmd/fastboot.c
+++ b/cmd/fastboot.c
@@ -51,7 +51,7 @@
 		return CMD_RET_FAILURE;
 	}
 
-	ret = board_usb_init(controller_index, USB_INIT_DEVICE);
+	ret = usb_gadget_initialize(controller_index);
 	if (ret) {
 		pr_err("USB init failed: %d\n", ret);
 		return CMD_RET_FAILURE;
@@ -82,7 +82,7 @@
 exit:
 	g_dnl_unregister();
 	g_dnl_clear_detach();
-	board_usb_cleanup(controller_index, USB_INIT_DEVICE);
+	usb_gadget_release(controller_index);
 
 	return ret;
 #else
diff --git a/cmd/rockusb.c b/cmd/rockusb.c
index 8206643..e0c1480 100644
--- a/cmd/rockusb.c
+++ b/cmd/rockusb.c
@@ -33,7 +33,7 @@
 	dev_index = simple_strtoul(devnum, NULL, 0);
 	rockusb_dev_init(devtype, dev_index);
 
-	ret = board_usb_init(controller_index, USB_INIT_DEVICE);
+	ret = usb_gadget_initialize(controller_index);
 	if (ret) {
 		printf("USB init failed: %d\n", ret);
 		return CMD_RET_FAILURE;
@@ -62,7 +62,7 @@
 exit:
 	g_dnl_unregister();
 	g_dnl_clear_detach();
-	board_usb_cleanup(controller_index, USB_INIT_DEVICE);
+	usb_gadget_release(controller_index);
 
 	return ret;
 }
diff --git a/cmd/thordown.c b/cmd/thordown.c
index 2615ada..ce3660d 100644
--- a/cmd/thordown.c
+++ b/cmd/thordown.c
@@ -30,7 +30,7 @@
 		goto done;
 
 	int controller_index = simple_strtoul(usb_controller, NULL, 0);
-	ret = board_usb_init(controller_index, USB_INIT_DEVICE);
+	ret = usb_gadget_initialize(controller_index);
 	if (ret) {
 		pr_err("USB init failed: %d\n", ret);
 		ret = CMD_RET_FAILURE;
@@ -55,7 +55,7 @@
 
 exit:
 	g_dnl_unregister();
-	board_usb_cleanup(controller_index, USB_INIT_DEVICE);
+	usb_gadget_release(controller_index);
 done:
 	dfu_free_entities();
 
diff --git a/cmd/usb_gadget_sdp.c b/cmd/usb_gadget_sdp.c
index ba1f66a..808ed97 100644
--- a/cmd/usb_gadget_sdp.c
+++ b/cmd/usb_gadget_sdp.c
@@ -20,7 +20,7 @@
 
 	char *usb_controller = argv[1];
 	int controller_index = simple_strtoul(usb_controller, NULL, 0);
-	board_usb_init(controller_index, USB_INIT_DEVICE);
+	usb_gadget_initialize(controller_index);
 
 	g_dnl_clear_detach();
 	g_dnl_register("usb_dnl_sdp");
@@ -37,7 +37,7 @@
 
 exit:
 	g_dnl_unregister();
-	board_usb_cleanup(controller_index, USB_INIT_DEVICE);
+	usb_gadget_release(controller_index);
 
 	return ret;
 }
diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c
index 0d55114..753ae4f 100644
--- a/cmd/usb_mass_storage.c
+++ b/cmd/usb_mass_storage.c
@@ -160,7 +160,7 @@
 
 	controller_index = (unsigned int)(simple_strtoul(
 				usb_controller,	NULL, 0));
-	if (board_usb_init(controller_index, USB_INIT_DEVICE)) {
+	if (usb_gadget_initialize(controller_index)) {
 		pr_err("Couldn't init USB controller.\n");
 		rc = CMD_RET_FAILURE;
 		goto cleanup_ums_init;
@@ -231,7 +231,7 @@
 cleanup_register:
 	g_dnl_unregister();
 cleanup_board:
-	board_usb_cleanup(controller_index, USB_INIT_DEVICE);
+	usb_gadget_release(controller_index);
 cleanup_ums_init:
 	ums_fini();
 
diff --git a/common/dfu.c b/common/dfu.c
index 2620d32..44d1484 100644
--- a/common/dfu.c
+++ b/common/dfu.c
@@ -23,9 +23,9 @@
 	bool dfu_reset = false;
 	int ret, i = 0;
 
-	ret = board_usb_init(usbctrl_index, USB_INIT_DEVICE);
+	ret = usb_gadget_initialize(usbctrl_index);
 	if (ret) {
-		pr_err("board usb init failed\n");
+		pr_err("usb_gadget_initialize failed\n");
 		return CMD_RET_FAILURE;
 	}
 	g_dnl_clear_detach();
@@ -84,7 +84,7 @@
 	}
 exit:
 	g_dnl_unregister();
-	board_usb_cleanup(usbctrl_index, USB_INIT_DEVICE);
+	usb_gadget_release(usbctrl_index);
 
 	if (dfu_reset)
 		do_reset(NULL, 0, 0, NULL);
diff --git a/common/hash.c b/common/hash.c
index ef14651..413a5bf 100644
--- a/common/hash.c
+++ b/common/hash.c
@@ -85,6 +85,33 @@
 }
 #endif
 
+static int hash_init_crc16_ccitt(struct hash_algo *algo, void **ctxp)
+{
+	uint16_t *ctx = malloc(sizeof(uint16_t));
+	*ctx = 0;
+	*ctxp = ctx;
+	return 0;
+}
+
+static int hash_update_crc16_ccitt(struct hash_algo *algo, void *ctx,
+				   const void *buf, unsigned int size,
+				   int is_last)
+{
+	*((uint16_t *)ctx) = crc16_ccitt(*((uint16_t *)ctx), buf, size);
+	return 0;
+}
+
+static int hash_finish_crc16_ccitt(struct hash_algo *algo, void *ctx,
+				   void *dest_buf, int size)
+{
+	if (size < algo->digest_size)
+		return -1;
+
+	*((uint16_t *)dest_buf) = *((uint16_t *)ctx);
+	free(ctx);
+	return 0;
+}
+
 static int hash_init_crc32(struct hash_algo *algo, void **ctxp)
 {
 	uint32_t *ctx = malloc(sizeof(uint32_t));
@@ -160,6 +187,15 @@
 	},
 #endif
 	{
+		.name		= "crc16-ccitt",
+		.digest_size	= 2,
+		.chunk_size	= CHUNKSZ,
+		.hash_func_ws	= crc16_ccitt_wd_buf,
+		.hash_init	= hash_init_crc16_ccitt,
+		.hash_update	= hash_update_crc16_ccitt,
+		.hash_finish	= hash_finish_crc16_ccitt,
+	},
+	{
 		.name		= "crc32",
 		.digest_size	= 4,
 		.chunk_size	= CHUNKSZ_CRC32,
diff --git a/common/main.c b/common/main.c
index 9802bed..07b34bf 100644
--- a/common/main.c
+++ b/common/main.c
@@ -24,15 +24,15 @@
 
 	p = env_get("preboot");
 	if (p != NULL) {
-# ifdef CONFIG_AUTOBOOT_KEYED
-		int prev = disable_ctrlc(1);	/* disable Control C checking */
-# endif
+		int prev = 0;
+
+		if (IS_ENABLED(CONFIG_AUTOBOOT_KEYED))
+			prev = disable_ctrlc(1); /* disable Ctrl-C checking */
 
 		run_command_list(p, -1, 0);
 
-# ifdef CONFIG_AUTOBOOT_KEYED
-		disable_ctrlc(prev);	/* restore Control C checking */
-# endif
+		if (IS_ENABLED(CONFIG_AUTOBOOT_KEYED))
+			disable_ctrlc(prev);	/* restore Ctrl-C checking */
 	}
 #endif /* CONFIG_PREBOOT */
 }
@@ -44,17 +44,15 @@
 
 	bootstage_mark_name(BOOTSTAGE_ID_MAIN_LOOP, "main_loop");
 
-#ifdef CONFIG_VERSION_VARIABLE
-	env_set("ver", version_string);  /* set version variable */
-#endif /* CONFIG_VERSION_VARIABLE */
+	if (IS_ENABLED(CONFIG_VERSION_VARIABLE))
+		env_set("ver", version_string);  /* set version variable */
 
 	cli_init();
 
 	run_preboot_environment_command();
 
-#if defined(CONFIG_UPDATE_TFTP)
-	update_tftp(0UL, NULL, NULL);
-#endif /* CONFIG_UPDATE_TFTP */
+	if (IS_ENABLED(CONFIG_UPDATE_TFTP))
+		update_tftp(0UL, NULL, NULL);
 
 	s = bootdelay_process();
 	if (cli_process_fdt(&s))
diff --git a/common/xyzModem.c b/common/xyzModem.c
index 830fca8..e5c65b4 100644
--- a/common/xyzModem.c
+++ b/common/xyzModem.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <xyzModem.h>
 #include <stdarg.h>
-#include <crc.h>
+#include <u-boot/crc.h>
 
 /* Assumption - run xyzModem protocol over the console port */
 
diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
index 467ca4e..dee8d02 100644
--- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
+++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
@@ -26,7 +26,9 @@
 CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_AXP_ALDO3_INRUSH_QUIRK=y
 CONFIG_AXP_ALDO3_VOLT=2800
+CONFIG_AXP_ALDO3_VOLT_SLOPE_08=y
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig
index fa58a6d..0c04ae6 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -25,7 +25,9 @@
 CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_AXP_ALDO3_INRUSH_QUIRK=y
 CONFIG_AXP_ALDO3_VOLT=2800
+CONFIG_AXP_ALDO3_VOLT_SLOPE_08=y
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig
index 379b958..419b41c 100644
--- a/configs/am335x_hs_evm_uart_defconfig
+++ b/configs/am335x_hs_evm_uart_defconfig
@@ -19,7 +19,6 @@
 # CONFIG_SPL_EXT_SUPPORT is not set
 CONFIG_SPL_MTD_SUPPORT=y
 # CONFIG_SPL_NAND_SUPPORT is not set
-# CONFIG_SPL_YMODEM_SUPPORT is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/am335x_pdu001_defconfig b/configs/am335x_pdu001_defconfig
index 065efca..3cb38af 100644
--- a/configs/am335x_pdu001_defconfig
+++ b/configs/am335x_pdu001_defconfig
@@ -18,6 +18,7 @@
 # CONFIG_SPL_NAND_SUPPORT is not set
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
@@ -37,6 +38,10 @@
 CONFIG_SPL_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
+CONFIG_BLK=y
+CONFIG_SPL_BLK=y
+CONFIG_DM_MMC=y
+CONFIG_SPL_DM_MMC=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_MMC_SDHCI=y
 CONFIG_PINCTRL=y
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index 5242ab6..32a95ea 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -50,6 +50,7 @@
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
+CONFIG_MISC=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_DM_SPI_FLASH=y
@@ -61,6 +62,9 @@
 CONFIG_DM_ETH=y
 CONFIG_DRIVER_TI_CPSW=y
 CONFIG_MII=y
+CONFIG_PHY=y
+CONFIG_PIPE3_PHY=y
+CONFIG_OMAP_USB2_PHY=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_PALMAS=y
 CONFIG_DM_REGULATOR=y
@@ -70,13 +74,15 @@
 CONFIG_DM_SPI=y
 CONFIG_TI_QSPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_SPL_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_OMAP_USB_PHY=y
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index be4aa0f..6a05738 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -53,6 +53,7 @@
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
+CONFIG_MISC=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_DM_SPI_FLASH=y
@@ -64,6 +65,9 @@
 CONFIG_DM_ETH=y
 CONFIG_DRIVER_TI_CPSW=y
 CONFIG_MII=y
+CONFIG_PHY=y
+CONFIG_PIPE3_PHY=y
+CONFIG_OMAP_USB2_PHY=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_PALMAS=y
 CONFIG_DM_REGULATOR=y
@@ -73,13 +77,15 @@
 CONFIG_DM_SPI=y
 CONFIG_TI_QSPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_SPL_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_OMAP_USB_PHY=y
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
diff --git a/configs/bcm968580_ram_defconfig b/configs/bcm968580_ram_defconfig
index abe90ee..4e10175 100644
--- a/configs/bcm968580_ram_defconfig
+++ b/configs/bcm968580_ram_defconfig
@@ -30,7 +30,7 @@
 CONFIG_CONS_INDEX=0
 CONFIG_DM_SERIAL=y
 CONFIG_SERIAL_SEARCH_ALL=y
-CONFIG_BCM6858_SERIAL=y
+CONFIG_BCM6345_SERIAL=y
 CONFIG_SYSRESET=y
 CONFIG_REGEX=y
 # CONFIG_GENERATE_SMBIOS_TABLE is not set
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 27f6b5d..1d9509c 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -56,6 +56,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_PCF8575_GPIO=y
 CONFIG_DM_I2C=y
+CONFIG_MISC=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_IO_VOLTAGE=y
 CONFIG_MMC_UHS_SUPPORT=y
@@ -72,6 +73,7 @@
 CONFIG_MII=y
 CONFIG_SPL_PHY=y
 CONFIG_PIPE3_PHY=y
+CONFIG_OMAP_USB2_PHY=y
 CONFIG_PMIC_PALMAS=y
 CONFIG_PMIC_LP873X=y
 CONFIG_DM_REGULATOR_FIXED=y
@@ -87,14 +89,14 @@
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_SPL_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_XHCI_DRA7XX_INDEX=1
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_OMAP_USB_PHY=y
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index 651fc4f..f3be339 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -56,6 +56,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_PCF8575_GPIO=y
 CONFIG_DM_I2C=y
+CONFIG_MISC=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_IO_VOLTAGE=y
 CONFIG_MMC_UHS_SUPPORT=y
@@ -71,6 +72,7 @@
 CONFIG_MII=y
 CONFIG_SPL_PHY=y
 CONFIG_PIPE3_PHY=y
+CONFIG_OMAP_USB2_PHY=y
 CONFIG_PMIC_PALMAS=y
 CONFIG_PMIC_LP873X=y
 CONFIG_DM_REGULATOR_FIXED=y
@@ -86,14 +88,14 @@
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_SPL_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_XHCI_DRA7XX_INDEX=1
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_OMAP_USB_PHY=y
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
index 5b3bb8e..f022163 100644
--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
@@ -49,6 +49,7 @@
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYSRESET=y
 CONFIG_USB=y
+CONFIG_USB_DWC3=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig
index e30eb3d..3bb4622 100644
--- a/configs/helios4_defconfig
+++ b/configs/helios4_defconfig
@@ -6,8 +6,8 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_HELIOS4=y
 CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC=y
-CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BASE=0xd0012000
 CONFIG_DEBUG_UART_CLOCK=250000000
@@ -20,11 +20,10 @@
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x141
-CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
@@ -38,18 +37,22 @@
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_SCSI_AHCI=y
+CONFIG_DM_GPIO=y
+CONFIG_MVEBU_GPIO=y
+CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_MV=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_SPI_FLASH_MTD=y
 CONFIG_PHY_GIGE=y
 CONFIG_MVNETA=y
 CONFIG_MII=y
-CONFIG_PCI=y
 CONFIG_SCSI=y
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 1a76785..5b65c61 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -96,6 +96,8 @@
 CONFIG_BOARD_SANDBOX=y
 CONFIG_PM8916_GPIO=y
 CONFIG_SANDBOX_GPIO=y
+CONFIG_DM_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_SANDBOX=y
 CONFIG_DM_I2C_COMPAT=y
 CONFIG_I2C_CROS_EC_TUNNEL=y
 CONFIG_I2C_CROS_EC_LDO=y
@@ -216,3 +218,6 @@
 CONFIG_UT_DM=y
 CONFIG_UT_ENV=y
 CONFIG_UT_OVERLAY=y
+CONFIG_DMA=y
+CONFIG_DMA_CHANNELS=y
+CONFIG_SANDBOX_DMA=y
diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
index 1bf3a7c..121e962 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_STM32=y
 CONFIG_SYS_TEXT_BASE=0x08008000
-CONFIG_SYS_MALLOC_F_LEN=0xC00
+CONFIG_SYS_MALLOC_F_LEN=0xE00
 CONFIG_STM32F7=y
 CONFIG_TARGET_STM32F746_DISCO=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
index 3bf7538..c8409fd 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -32,6 +32,8 @@
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
 CONFIG_STM32_ADC=y
+CONFIG_DM_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_STM32=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_STM32F7=y
 CONFIG_LED=y
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 4ac823d..e9fbadd 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -40,6 +40,8 @@
 
 source "drivers/gpio/Kconfig"
 
+source "drivers/hwspinlock/Kconfig"
+
 source "drivers/i2c/Kconfig"
 
 source "drivers/input/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 55de109..c425831 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -113,4 +113,5 @@
 obj-$(CONFIG_W1_EEPROM) += w1-eeprom/
 
 obj-$(CONFIG_MACH_PIC32) += ddr/microchip/
+obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock/
 endif
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 04b369a..6d7a514 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -243,6 +243,10 @@
 {
 	int ret;
 
+	/* If this not in SPL and pre-reloc state, don't take any action. */
+	if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC)))
+		return 0;
+
 	debug("%s(%s)\n", __func__, dev_read_name(dev));
 
 	ret = clk_set_default_parents(dev);
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index 6a8c7b7..b7c5d34 100644
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -104,6 +104,7 @@
 #define RCC_MP_APB2ENSETR	0XA08
 #define RCC_MP_APB3ENSETR	0xA10
 #define RCC_MP_AHB2ENSETR	0xA18
+#define RCC_MP_AHB3ENSETR	0xA20
 #define RCC_MP_AHB4ENSETR	0xA28
 
 /* used for most of SELR register */
@@ -534,6 +535,8 @@
 	STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
 	STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
 
+	STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL),
+
 	STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
 	STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
 	STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
diff --git a/drivers/core/syscon-uclass.c b/drivers/core/syscon-uclass.c
index 303e166..661cf61 100644
--- a/drivers/core/syscon-uclass.c
+++ b/drivers/core/syscon-uclass.c
@@ -53,6 +53,29 @@
 #endif
 }
 
+struct regmap *syscon_regmap_lookup_by_phandle(struct udevice *dev,
+					       const char *name)
+{
+	struct udevice *syscon;
+	struct regmap *r;
+	int err;
+
+	err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
+					   name, &syscon);
+	if (err) {
+		dev_dbg(dev, "unable to find syscon device\n");
+		return ERR_PTR(err);
+	}
+
+	r = syscon_get_regmap(syscon);
+	if (!r) {
+		dev_dbg(dev, "unable to find regmap\n");
+		return ERR_PTR(-ENODEV);
+	}
+
+	return r;
+}
+
 int syscon_get_by_driver_data(ulong driver_data, struct udevice **devp)
 {
 	struct udevice *dev;
diff --git a/drivers/ddr/marvell/a38x/ddr3_debug.c b/drivers/ddr/marvell/a38x/ddr3_debug.c
index 1eac0bc..f5fc964 100644
--- a/drivers/ddr/marvell/a38x/ddr3_debug.c
+++ b/drivers/ddr/marvell/a38x/ddr3_debug.c
@@ -4,6 +4,8 @@
  */
 
 #include "ddr3_init.h"
+#include "mv_ddr_training_db.h"
+#include "mv_ddr_regs.h"
 
 u8 is_reg_dump = 0;
 u8 debug_pbs = DEBUG_LEVEL_ERROR;
@@ -83,7 +85,7 @@
 #endif /* SILENT_LIB */
 
 #if defined(DDR_VIEWER_TOOL)
-static char *convert_freq(enum hws_ddr_freq freq);
+static char *convert_freq(enum mv_ddr_freq freq);
 #if defined(EXCLUDE_SWITCH_DEBUG)
 u32 ctrl_sweepres[ADLL_LENGTH][MAX_INTERFACE_NUM][MAX_BUS_NUM];
 u32 ctrl_adll[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
@@ -177,23 +179,6 @@
 }
 
 /*
- * Read training result table
- */
-int hws_ddr3_tip_read_training_result(
-	u32 dev_num, enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM])
-{
-	if (result == NULL)
-		return MV_BAD_PARAM;
-
-	memcpy(result, training_result,
-	       sizeof(enum hws_result) *
-	       MAX_STAGE_LIMIT *
-	       MAX_INTERFACE_NUM);
-
-	return MV_OK;
-}
-
-/*
  * Get training result info pointer
  */
 enum hws_result *ddr3_tip_get_result_ptr(u32 stage)
@@ -218,50 +203,50 @@
 /*
  * Convert freq to character string
  */
-static char *convert_freq(enum hws_ddr_freq freq)
+static char *convert_freq(enum mv_ddr_freq freq)
 {
 	switch (freq) {
-	case DDR_FREQ_LOW_FREQ:
-		return "DDR_FREQ_LOW_FREQ";
+	case MV_DDR_FREQ_LOW_FREQ:
+		return "MV_DDR_FREQ_LOW_FREQ";
 
-	case DDR_FREQ_400:
+	case MV_DDR_FREQ_400:
 		return "400";
 
-	case DDR_FREQ_533:
+	case MV_DDR_FREQ_533:
 		return "533";
 
-	case DDR_FREQ_667:
+	case MV_DDR_FREQ_667:
 		return "667";
 
-	case DDR_FREQ_800:
+	case MV_DDR_FREQ_800:
 		return "800";
 
-	case DDR_FREQ_933:
+	case MV_DDR_FREQ_933:
 		return "933";
 
-	case DDR_FREQ_1066:
+	case MV_DDR_FREQ_1066:
 		return "1066";
 
-	case DDR_FREQ_311:
+	case MV_DDR_FREQ_311:
 		return "311";
 
-	case DDR_FREQ_333:
+	case MV_DDR_FREQ_333:
 		return "333";
 
-	case DDR_FREQ_467:
+	case MV_DDR_FREQ_467:
 		return "467";
 
-	case DDR_FREQ_850:
+	case MV_DDR_FREQ_850:
 		return "850";
 
-	case DDR_FREQ_900:
+	case MV_DDR_FREQ_900:
 		return "900";
 
-	case DDR_FREQ_360:
-		return "DDR_FREQ_360";
+	case MV_DDR_FREQ_360:
+		return "MV_DDR_FREQ_360";
 
-	case DDR_FREQ_1000:
-		return "DDR_FREQ_1000";
+	case MV_DDR_FREQ_1000:
+		return "MV_DDR_FREQ_1000";
 
 	default:
 		return "Unknown Frequency";
@@ -364,7 +349,7 @@
 	if ((is_validate_window_per_if != 0) ||
 	    (is_validate_window_per_pup != 0)) {
 		u32 is_pup_log = 0;
-		enum hws_ddr_freq freq;
+		enum mv_ddr_freq freq;
 
 		freq = tm->interface_params[first_active_if].memory_freq;
 
@@ -528,7 +513,7 @@
 	u8 if_id = 0, csindex = 0, bus_id = 0, idx = 0;
 	u32 reg_data;
 	u32 read_data[MAX_INTERFACE_NUM];
-	u32 max_cs = ddr3_tip_max_cs_get(dev_num);
+	unsigned int max_cs = mv_ddr_cs_num_get();
 	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
 
 	/* Title print */
@@ -844,8 +829,6 @@
 	 0xffffffff, 0xffffffff}
 };
 
-static int ddr3_tip_access_atr(u32 dev_num, u32 flag_id, u32 value, u32 **ptr);
-
 int ddr3_tip_print_adll(void)
 {
 	u32 bus_cnt = 0, if_id, data_p1, data_p2, ui_data3, dev_num = 0;
@@ -877,353 +860,6 @@
 	return MV_OK;
 }
 
-/*
- * Set attribute value
- */
-int ddr3_tip_set_atr(u32 dev_num, u32 flag_id, u32 value)
-{
-	int ret;
-	u32 *ptr_flag = NULL;
-
-	ret = ddr3_tip_access_atr(dev_num, flag_id, value, &ptr_flag);
-	if (ptr_flag != NULL) {
-		printf("ddr3_tip_set_atr Flag ID 0x%x value is set to 0x%x (was 0x%x)\n",
-		       flag_id, value, *ptr_flag);
-		*ptr_flag = value;
-	} else {
-		printf("ddr3_tip_set_atr Flag ID 0x%x value is set to 0x%x\n",
-		       flag_id, value);
-	}
-
-	return ret;
-}
-
-/*
- * Access attribute
- */
-static int ddr3_tip_access_atr(u32 dev_num, u32 flag_id, u32 value, u32 **ptr)
-{
-	u32 tmp_val = 0, if_id = 0, pup_id = 0;
-	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
-
-	*ptr = NULL;
-
-	switch (flag_id) {
-	case 0:
-		*ptr = (u32 *)&(tm->if_act_mask);
-		break;
-
-	case 0x1:
-		*ptr = (u32 *)&mask_tune_func;
-		break;
-
-	case 0x2:
-		low_freq = (enum hws_ddr_freq)value;
-		break;
-
-	case 0x3:
-		medium_freq = (enum hws_ddr_freq)value;
-		break;
-
-	case 0x4:
-		*ptr = (u32 *)&generic_init_controller;
-		break;
-
-	case 0x8:
-		*ptr = (u32 *)&start_xsb_offset;
-		break;
-
-	case 0x20:
-		*ptr = (u32 *)&is_rl_old;
-		break;
-
-	case 0x21:
-		*ptr = (u32 *)&is_freq_old;
-		break;
-
-	case 0x23:
-		*ptr = (u32 *)&is_dfs_disabled;
-		break;
-
-	case 0x24:
-		*ptr = (u32 *)&is_pll_before_init;
-		break;
-
-	case 0x25:
-		*ptr = (u32 *)&is_adll_calib_before_init;
-		break;
-	case 0x28:
-		*ptr = (u32 *)&is_tune_result;
-		break;
-
-	case 0x29:
-		*ptr = (u32 *)&is_validate_window_per_if;
-		break;
-
-	case 0x2a:
-		*ptr = (u32 *)&is_validate_window_per_pup;
-		break;
-
-	case 0x30:
-		*ptr = (u32 *)&sweep_cnt;
-		break;
-
-	case 0x31:
-		*ptr = (u32 *)&is_bist_reset_bit;
-		break;
-
-	case 0x32:
-		*ptr = (u32 *)&is_dfs_in_init;
-		break;
-
-	case 0x33:
-		*ptr = (u32 *)&g_zpodt_data;
-		break;
-
-	case 0x34:
-		*ptr = (u32 *)&g_znodt_data;
-		break;
-
-	case 0x35:
-		break;
-
-	case 0x36:
-		*ptr = (u32 *)&(freq_val[DDR_FREQ_LOW_FREQ]);
-		break;
-
-	case 0x37:
-		*ptr = (u32 *)&start_pattern;
-		break;
-
-	case 0x38:
-		*ptr = (u32 *)&end_pattern;
-		break;
-
-	case 0x39:
-		*ptr = (u32 *)&phy_reg0_val;
-		break;
-
-	case 0x4a:
-		*ptr = (u32 *)&phy_reg1_val;
-		break;
-
-	case 0x4b:
-		*ptr = (u32 *)&phy_reg2_val;
-		break;
-
-	case 0x4c:
-		*ptr = (u32 *)&phy_reg3_val;
-		break;
-
-	case 0x4e:
-		sweep_pattern = (enum hws_pattern)value;
-		break;
-
-	case 0x51:
-		*ptr = (u32 *)&g_znri_data;
-		break;
-
-	case 0x52:
-		*ptr = (u32 *)&g_zpri_data;
-		break;
-
-	case 0x53:
-		*ptr = (u32 *)&finger_test;
-		break;
-
-	case 0x54:
-		*ptr = (u32 *)&n_finger_start;
-		break;
-
-	case 0x55:
-		*ptr = (u32 *)&n_finger_end;
-		break;
-
-	case 0x56:
-		*ptr = (u32 *)&p_finger_start;
-		break;
-
-	case 0x57:
-		*ptr = (u32 *)&p_finger_end;
-		break;
-
-	case 0x58:
-		*ptr = (u32 *)&p_finger_step;
-		break;
-
-	case 0x59:
-		*ptr = (u32 *)&n_finger_step;
-		break;
-
-	case 0x5a:
-		*ptr = (u32 *)&g_znri_ctrl;
-		break;
-
-	case 0x5b:
-		*ptr = (u32 *)&g_zpri_ctrl;
-		break;
-
-	case 0x5c:
-		*ptr = (u32 *)&is_reg_dump;
-		break;
-
-	case 0x5d:
-		*ptr = (u32 *)&vref_init_val;
-		break;
-
-	case 0x5e:
-		*ptr = (u32 *)&mode_2t;
-		break;
-
-	case 0x5f:
-		*ptr = (u32 *)&xsb_validate_type;
-		break;
-
-	case 0x60:
-		*ptr = (u32 *)&xsb_validation_base_address;
-		break;
-
-	case 0x67:
-		*ptr = (u32 *)&activate_select_before_run_alg;
-		break;
-
-	case 0x68:
-		*ptr = (u32 *)&activate_deselect_after_run_alg;
-		break;
-
-	case 0x69:
-		*ptr = (u32 *)&odt_additional;
-		break;
-
-	case 0x70:
-		*ptr = (u32 *)&debug_mode;
-		break;
-
-	case 0x71:
-		pbs_pattern = (enum hws_pattern)value;
-		break;
-
-	case 0x72:
-		*ptr = (u32 *)&delay_enable;
-		break;
-
-	case 0x73:
-		*ptr = (u32 *)&ck_delay;
-		break;
-
-	case 0x75:
-		*ptr = (u32 *)&ca_delay;
-		break;
-
-	case 0x100:
-		*ptr = (u32 *)&debug_dunit;
-		break;
-
-	case 0x101:
-		debug_acc = (int)value;
-		break;
-
-	case 0x102:
-		debug_training = (u8)value;
-		break;
-
-	case 0x103:
-		debug_training_bist = (u8)value;
-		break;
-
-	case 0x104:
-		debug_centralization = (u8)value;
-		break;
-
-	case 0x105:
-		debug_training_ip = (u8)value;
-		break;
-
-	case 0x106:
-		debug_leveling = (u8)value;
-		break;
-
-	case 0x107:
-		debug_pbs = (u8)value;
-		break;
-
-	case 0x108:
-		debug_training_static = (u8)value;
-		break;
-
-	case 0x109:
-		debug_training_access = (u8)value;
-		break;
-
-
-	case 0x112:
-		*ptr = &start_pattern;
-		break;
-
-	case 0x113:
-		*ptr = &end_pattern;
-		break;
-
-	default:
-		if ((flag_id >= 0x200) && (flag_id < 0x210)) {
-			if_id = flag_id - 0x200;
-			*ptr = (u32 *)&(tm->interface_params
-					[if_id].memory_freq);
-		} else if ((flag_id >= 0x210) && (flag_id < 0x220)) {
-			if_id = flag_id - 0x210;
-			*ptr = (u32 *)&(tm->interface_params
-					[if_id].speed_bin_index);
-		} else if ((flag_id >= 0x220) && (flag_id < 0x230)) {
-			if_id = flag_id - 0x220;
-			*ptr = (u32 *)&(tm->interface_params
-					[if_id].bus_width);
-		} else if ((flag_id >= 0x230) && (flag_id < 0x240)) {
-			if_id = flag_id - 0x230;
-			*ptr = (u32 *)&(tm->interface_params
-					[if_id].memory_size);
-		} else if ((flag_id >= 0x240) && (flag_id < 0x250)) {
-			if_id = flag_id - 0x240;
-			*ptr = (u32 *)&(tm->interface_params
-					[if_id].cas_l);
-		} else if ((flag_id >= 0x250) && (flag_id < 0x260)) {
-			if_id = flag_id - 0x250;
-			*ptr = (u32 *)&(tm->interface_params
-					[if_id].cas_wl);
-		} else if ((flag_id >= 0x270) && (flag_id < 0x2cf)) {
-			if_id = (flag_id - 0x270) / MAX_BUS_NUM;
-			pup_id = (flag_id - 0x270) % MAX_BUS_NUM;
-			*ptr = (u32 *)&(tm->interface_params[if_id].
-					as_bus_params[pup_id].is_ck_swap);
-		} else if ((flag_id >= 0x2d0) && (flag_id < 0x32f)) {
-			if_id = (flag_id - 0x2d0) / MAX_BUS_NUM;
-			pup_id = (flag_id - 0x2d0) % MAX_BUS_NUM;
-			*ptr = (u32 *)&(tm->interface_params[if_id].
-					as_bus_params[pup_id].is_dqs_swap);
-		} else if ((flag_id >= 0x330) && (flag_id < 0x38f)) {
-			if_id = (flag_id - 0x330) / MAX_BUS_NUM;
-			pup_id = (flag_id - 0x330) % MAX_BUS_NUM;
-			*ptr = (u32 *)&(tm->interface_params[if_id].
-					as_bus_params[pup_id].cs_bitmask);
-		} else if ((flag_id >= 0x390) && (flag_id < 0x3ef)) {
-			if_id = (flag_id - 0x390) / MAX_BUS_NUM;
-			pup_id = (flag_id - 0x390) % MAX_BUS_NUM;
-			*ptr = (u32 *)&(tm->interface_params
-					[if_id].as_bus_params
-					[pup_id].mirror_enable_bitmask);
-		} else if ((flag_id >= 0x500) && (flag_id <= 0x50f)) {
-			tmp_val = flag_id - 0x320;
-			*ptr = (u32 *)&(clamp_tbl[tmp_val]);
-		} else {
-			DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
-					  ("flag_id out of boundary %d\n",
-					   flag_id));
-			return MV_BAD_PARAM;
-		}
-	}
-
-	return MV_OK;
-}
-
 #endif /* EXCLUDE_SWITCH_DEBUG */
 
 #if defined(DDR_VIEWER_TOOL)
@@ -1315,7 +951,7 @@
 	u32 reg;
 	enum hws_access_type pup_access;
 	u32 cs;
-	u32 max_cs = ddr3_tip_max_cs_get(dev_num);
+	unsigned int max_cs = mv_ddr_cs_num_get();
 	u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
 	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
 
@@ -1462,7 +1098,7 @@
 	u32 reg;
 	enum hws_access_type pup_access;
 	u32 cs;
-	u32 max_cs = ddr3_tip_max_cs_get(dev_num);
+	unsigned int max_cs = mv_ddr_cs_num_get();
 	u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
 	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
 
diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c b/drivers/ddr/marvell/a38x/ddr3_init.c
index 27dbf4f..22c8f9c 100644
--- a/drivers/ddr/marvell/a38x/ddr3_init.c
+++ b/drivers/ddr/marvell/a38x/ddr3_init.c
@@ -6,18 +6,6 @@
 #include "ddr3_init.h"
 #include "mv_ddr_common.h"
 
-/*
- * Translates topology map definitions to real memory size in bits
-  * (per values in ddr3_training_ip_def.h)
- */
-u32 mem_size[] = {
-	ADDR_SIZE_512MB,
-	ADDR_SIZE_1GB,
-	ADDR_SIZE_2GB,
-	ADDR_SIZE_4GB,
-	ADDR_SIZE_8GB
-};
-
 static char *ddr_type = "DDR3";
 
 /*
@@ -37,8 +25,6 @@
  */
 int ddr3_init(void)
 {
-	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
-	u32 octets_per_if_num;
 	int status;
 	int is_manual_cal_done;
 
@@ -55,7 +41,7 @@
 
 	mv_ddr_early_init();
 
-	if (mv_ddr_topology_map_update() == NULL) {
+	if (mv_ddr_topology_map_update()) {
 		printf("mv_ddr: failed to update topology\n");
 		return MV_FAIL;
 	}
@@ -68,7 +54,6 @@
 	if (MV_OK != status)
 		return status;
 
-
 	mv_ddr_mc_config();
 
 	is_manual_cal_done = mv_ddr_manual_cal_do();
@@ -101,76 +86,14 @@
 
 	mv_ddr_post_training_fixup();
 
-	octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
-	if (ddr3_if_ecc_enabled()) {
-		if (MV_DDR_IS_64BIT_DRAM_MODE(tm->bus_act_mask) ||
-		    MV_DDR_IS_32BIT_IN_64BIT_DRAM_MODE(tm->bus_act_mask, octets_per_if_num))
-			mv_ddr_mem_scrubbing();
-		else
-			ddr3_new_tip_ecc_scrub();
-	}
+	if (mv_ddr_is_ecc_ena())
+		mv_ddr_mem_scrubbing();
 
 	printf("mv_ddr: completed successfully\n");
 
 	return MV_OK;
 }
 
-uint64_t mv_ddr_get_memory_size_per_cs_in_bits(void)
-{
-	uint64_t memory_size_per_cs;
-
-	u32 bus_cnt, num_of_active_bus = 0;
-	u32 num_of_sub_phys_per_ddr_unit = 0;
-
-	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
-
-	u32 octets_per_if_num = ddr3_tip_dev_attr_get(DEV_NUM_0, MV_ATTR_OCTET_PER_INTERFACE);
-
-	/* count the number of active bus */
-	for (bus_cnt = 0; bus_cnt < octets_per_if_num - 1/* ignore ecc octet */; bus_cnt++) {
-		VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt);
-		num_of_active_bus++;
-	}
-
-	/* calculate number of sub-phys per ddr unit */
-	if (tm->interface_params[0].bus_width/* supports only single interface */ == MV_DDR_DEV_WIDTH_16BIT)
-		num_of_sub_phys_per_ddr_unit = TWO_SUB_PHYS;
-	if (tm->interface_params[0].bus_width/* supports only single interface */ == MV_DDR_DEV_WIDTH_8BIT)
-		num_of_sub_phys_per_ddr_unit = SINGLE_SUB_PHY;
-
-	/* calculate dram size per cs */
-	memory_size_per_cs = (uint64_t)mem_size[tm->interface_params[0].memory_size] * (uint64_t)num_of_active_bus
-		/ (uint64_t)num_of_sub_phys_per_ddr_unit * (uint64_t)MV_DDR_NUM_BITS_IN_BYTE;
-
-	return memory_size_per_cs;
-}
-
-uint64_t mv_ddr_get_total_memory_size_in_bits(void)
-{
-	uint64_t total_memory_size = 0;
-	uint64_t memory_size_per_cs = 0;
-
-	/* get the number of cs */
-	u32 max_cs = ddr3_tip_max_cs_get(DEV_NUM_0);
-
-	memory_size_per_cs = mv_ddr_get_memory_size_per_cs_in_bits();
-	total_memory_size = (uint64_t)max_cs * memory_size_per_cs;
-
-	return total_memory_size;
-}
-
-int ddr3_if_ecc_enabled(void)
-{
-	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
-
-	if (DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask) ||
-	    DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask) ||
-	    DDR3_IS_ECC_PUP8_MODE(tm->bus_act_mask))
-		return 1;
-	else
-		return 0;
-}
-
 /*
  * Name:	mv_ddr_training_params_set
  * Desc:
@@ -182,15 +105,9 @@
 {
 	struct tune_train_params params;
 	int status;
-	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
-	u32 if_id;
 	u32 cs_num;
 
-	CHECK_STATUS(ddr3_tip_get_first_active_if
-		     (dev_num, tm->if_act_mask,
-		      &if_id));
-
-	CHECK_STATUS(calc_cs_num(dev_num, if_id, &cs_num));
+	cs_num = mv_ddr_cs_num_get();
 
 	/* NOTE: do not remove any field initilization */
 	params.ck_delay = TUNE_TRAINING_PARAMS_CK_DELAY;
diff --git a/drivers/ddr/marvell/a38x/ddr3_init.h b/drivers/ddr/marvell/a38x/ddr3_init.h
index 382bd92..055516b 100644
--- a/drivers/ddr/marvell/a38x/ddr3_init.h
+++ b/drivers/ddr/marvell/a38x/ddr3_init.h
@@ -7,9 +7,7 @@
 #define _DDR3_INIT_H
 
 #include "ddr_ml_wrapper.h"
-#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
 #include "mv_ddr_plat.h"
-#endif
 
 #include "seq_exec.h"
 #include "ddr3_logging_def.h"
@@ -32,14 +30,8 @@
 			return status;	\
 	}
 
-#define GET_MAX_VALUE(x, y)			\
-	((x) > (y)) ? (x) : (y)
-
 #define SUB_VERSION	0
 
-/* max number of devices supported by driver */
-#define MAX_DEVICE_NUM	1
-
 enum log_level  {
 	MV_LOG_LEVEL_0,
 	MV_LOG_LEVEL_1,
@@ -47,24 +39,26 @@
 	MV_LOG_LEVEL_3
 };
 
+/* TODO: consider to move to misl phy driver */
+#define MISL_PHY_DRV_P_OFFS	0x7
+#define MISL_PHY_DRV_N_OFFS	0x0
+#define MISL_PHY_ODT_P_OFFS	0x6
+#define MISL_PHY_ODT_N_OFFS	0x0
+
 /* Globals */
 extern u8 debug_training, debug_calibration, debug_ddr4_centralization,
 	debug_tap_tuning, debug_dm_tuning;
 extern u8 is_reg_dump;
 extern u8 generic_init_controller;
-/* list of allowed frequency listed in order of enum hws_ddr_freq */
-extern u32 freq_val[DDR_FREQ_LAST];
+/* list of allowed frequency listed in order of enum mv_ddr_freq */
 extern u32 is_pll_old;
-extern struct cl_val_per_freq cas_latency_table[];
 extern struct pattern_info pattern_table[];
-extern struct cl_val_per_freq cas_write_latency_table[];
 extern u8 debug_centralization, debug_training_ip, debug_training_bist,
 	debug_pbs, debug_training_static, debug_leveling;
 extern struct hws_tip_config_func_db config_func_info[];
 extern u8 twr_mask_table[];
 extern u8 cl_mask_table[];
 extern u8 cwl_mask_table[];
-extern u16 rfc_table[];
 extern u32 speed_bin_table_t_rc[];
 extern u32 speed_bin_table_t_rcd_t_rp[];
 
@@ -90,10 +84,10 @@
 extern u32 rl_version;
 extern int rl_mid_freq_wa;
 extern u8 calibration_update_control; /* 2 external only, 1 is internal only */
-extern enum hws_ddr_freq medium_freq;
+extern enum mv_ddr_freq medium_freq;
 
 extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
-extern enum hws_ddr_freq low_freq;
+extern enum mv_ddr_freq low_freq;
 extern enum auto_tune_stage training_stage;
 extern u32 is_pll_before_init;
 extern u32 is_adll_calib_before_init;
@@ -120,7 +114,7 @@
 extern u32 debug_mode;
 extern u32 debug_dunit;
 extern u32 clamp_tbl[];
-extern u32 freq_mask[MAX_DEVICE_NUM][DDR_FREQ_LAST];
+extern u32 freq_mask[MAX_DEVICE_NUM][MV_DDR_FREQ_LAST];
 
 extern u32 maxt_poll_tries;
 extern u32 is_bist_reset_bit;
@@ -139,7 +133,6 @@
 
 extern u32 target_freq;
 extern u32 dfs_low_freq;
-extern u32 mem_size[];
 
 extern u32 nominal_avs;
 extern u32 extension_avs;
@@ -154,13 +147,8 @@
 int mv_ddr_early_init2(void);
 int ddr3_silicon_post_init(void);
 int ddr3_post_run_alg(void);
-int ddr3_if_ecc_enabled(void);
 void ddr3_new_tip_ecc_scrub(void);
 
-void mv_ddr_ver_print(void);
-struct mv_ddr_topology_map *mv_ddr_topology_map_get(void);
-
-int ddr3_if_ecc_enabled(void);
 int ddr3_tip_reg_write(u32 dev_num, u32 reg_addr, u32 data);
 int ddr3_tip_reg_read(u32 dev_num, u32 reg_addr, u32 *data, u32 reg_mask);
 int ddr3_silicon_get_ddr_target_freq(u32 *ddr_freq);
@@ -185,15 +173,20 @@
 void ddr3_fast_path_static_cs_size_config(u32 cs_ena);
 u32 mv_board_id_index_get(u32 board_id);
 void ddr3_set_log_level(u32 n_log_level);
-int calc_cs_num(u32 dev_num, u32 if_id, u32 *cs_num);
 
 int hws_ddr3_cs_base_adr_calc(u32 if_id, u32 cs, u32 *cs_base_addr);
 
 int ddr3_tip_print_pbs_result(u32 dev_num, u32 cs_num, enum pbs_dir pbs_mode);
 int ddr3_tip_clean_pbs_result(u32 dev_num, enum pbs_dir pbs_mode);
-
-u32 mv_ddr_init_freq_get(void);
 void mv_ddr_mc_config(void);
 int mv_ddr_mc_init(void);
 void mv_ddr_set_calib_controller(void);
+/* TODO: consider to move to misl phy driver */
+unsigned int mv_ddr_misl_phy_drv_data_p_get(void);
+unsigned int mv_ddr_misl_phy_drv_data_n_get(void);
+unsigned int mv_ddr_misl_phy_drv_ctrl_p_get(void);
+unsigned int mv_ddr_misl_phy_drv_ctrl_n_get(void);
+unsigned int mv_ddr_misl_phy_odt_p_get(void);
+unsigned int mv_ddr_misl_phy_odt_n_get(void);
+
 #endif /* _DDR3_INIT_H */
diff --git a/drivers/ddr/marvell/a38x/ddr3_topology_def.h b/drivers/ddr/marvell/a38x/ddr3_topology_def.h
deleted file mode 100644
index 1963bae..0000000
--- a/drivers/ddr/marvell/a38x/ddr3_topology_def.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) Marvell International Ltd. and its affiliates
- */
-
-#ifndef _DDR3_TOPOLOGY_DEF_H
-#define _DDR3_TOPOLOGY_DEF_H
-
-#define DEV_NUM_0	0
-
-/* TOPOLOGY */
-enum hws_speed_bin {
-	SPEED_BIN_DDR_800D,
-	SPEED_BIN_DDR_800E,
-	SPEED_BIN_DDR_1066E,
-	SPEED_BIN_DDR_1066F,
-	SPEED_BIN_DDR_1066G,
-	SPEED_BIN_DDR_1333F,
-	SPEED_BIN_DDR_1333G,
-	SPEED_BIN_DDR_1333H,
-	SPEED_BIN_DDR_1333J,
-	SPEED_BIN_DDR_1600G,
-	SPEED_BIN_DDR_1600H,
-	SPEED_BIN_DDR_1600J,
-	SPEED_BIN_DDR_1600K,
-	SPEED_BIN_DDR_1866J,
-	SPEED_BIN_DDR_1866K,
-	SPEED_BIN_DDR_1866L,
-	SPEED_BIN_DDR_1866M,
-	SPEED_BIN_DDR_2133K,
-	SPEED_BIN_DDR_2133L,
-	SPEED_BIN_DDR_2133M,
-	SPEED_BIN_DDR_2133N,
-
-	SPEED_BIN_DDR_1333H_EXT,
-	SPEED_BIN_DDR_1600K_EXT,
-	SPEED_BIN_DDR_1866M_EXT
-};
-
-enum hws_ddr_freq {
-	DDR_FREQ_LOW_FREQ,
-	DDR_FREQ_400,
-	DDR_FREQ_533,
-	DDR_FREQ_667,
-	DDR_FREQ_800,
-	DDR_FREQ_933,
-	DDR_FREQ_1066,
-	DDR_FREQ_311,
-	DDR_FREQ_333,
-	DDR_FREQ_467,
-	DDR_FREQ_850,
-	DDR_FREQ_600,
-	DDR_FREQ_300,
-	DDR_FREQ_900,
-	DDR_FREQ_360,
-	DDR_FREQ_1000,
-	DDR_FREQ_LAST,
-	DDR_FREQ_SAR
-};
-
-enum speed_bin_table_elements {
-	SPEED_BIN_TRCD,
-	SPEED_BIN_TRP,
-	SPEED_BIN_TRAS,
-	SPEED_BIN_TRC,
-	SPEED_BIN_TRRD1K,
-	SPEED_BIN_TRRD2K,
-	SPEED_BIN_TPD,
-	SPEED_BIN_TFAW1K,
-	SPEED_BIN_TFAW2K,
-	SPEED_BIN_TWTR,
-	SPEED_BIN_TRTP,
-	SPEED_BIN_TWR,
-	SPEED_BIN_TMOD,
-	SPEED_BIN_TXPDLL
-};
-
-#endif /* _DDR3_TOPOLOGY_DEF_H */
diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c
index 799c5ba..c7be700 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training.c
@@ -5,6 +5,8 @@
 
 #include "ddr3_init.h"
 #include "mv_ddr_common.h"
+#include "mv_ddr_training_db.h"
+#include "mv_ddr_regs.h"
 
 #define GET_CS_FROM_MASK(mask)	(cs_mask2_num[mask])
 #define CS_CBE_VALUE(cs_num)	(cs_cbe_reg[cs_num])
@@ -14,8 +16,8 @@
 u32 phy_reg1_val = 8;
 u32 phy_reg2_val = 0;
 u32 phy_reg3_val = PARAM_UNDEFINED;
-enum hws_ddr_freq low_freq = DDR_FREQ_LOW_FREQ;
-enum hws_ddr_freq medium_freq;
+enum mv_ddr_freq low_freq = MV_DDR_FREQ_LOW_FREQ;
+enum mv_ddr_freq medium_freq;
 u32 debug_dunit = 0;
 u32 odt_additional = 1;
 u32 *dq_map_table = NULL;
@@ -97,36 +99,9 @@
 #endif
 
 int adll_calibration(u32 dev_num, enum hws_access_type access_type,
-		     u32 if_id, enum hws_ddr_freq frequency);
+		     u32 if_id, enum mv_ddr_freq frequency);
 static int ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type,
-			       u32 if_id, enum hws_ddr_freq frequency);
-
-static struct page_element page_tbl[] = {
-	/*
-	 * 8bits	16 bits
-	 * page-size(K)	page-size(K)	mask
-	 */
-	{ 1,		2,		2},
-	/* 512M */
-	{ 1,		2,		3},
-	/* 1G */
-	{ 1,		2,		0},
-	/* 2G */
-	{ 1,		2,		4},
-	/* 4G */
-	{ 2,		2,		5},
-	/* 8G */
-	{0, 0, 0}, /* TODO: placeholder for 16-Mbit die capacity */
-	{0, 0, 0}, /* TODO: placeholder for 32-Mbit die capacity */
-	{0, 0, 0}, /* TODO: placeholder for 12-Mbit die capacity */
-	{0, 0, 0}  /* TODO: placeholder for 24-Mbit die capacity */
-
-};
-
-struct page_element *mv_ddr_page_tbl_get(void)
-{
-	return &page_tbl[0];
-}
+			       u32 if_id, enum mv_ddr_freq frequency);
 
 static u8 mem_size_config[MV_DDR_DIE_CAP_LAST] = {
 	0x2,			/* 512Mbit  */
@@ -204,7 +179,52 @@
 	{MRS3_CMD, MR3_REG}
 };
 
+/* inverse pads */
+static int ddr3_tip_pad_inv(void)
+{
+	u32 sphy, data;
+	u32 sphy_max = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
+	u32 ck_swap_ctrl_sphy;
+	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
+
+	for (sphy = 0; sphy < sphy_max; sphy++) {
+		VALIDATE_BUS_ACTIVE(tm->bus_act_mask, sphy);
+		if (tm->interface_params[0].
+		    as_bus_params[sphy].is_dqs_swap == 1) {
+			data = (INVERT_PAD << INV_PAD4_OFFS |
+				INVERT_PAD << INV_PAD5_OFFS);
+			/* dqs swap */
+			ddr3_tip_bus_read_modify_write(0, ACCESS_TYPE_UNICAST,
+						       0, sphy,
+						       DDR_PHY_DATA,
+						       PHY_CTRL_PHY_REG,
+						       data, data);
+		}
+
+		if (tm->interface_params[0].as_bus_params[sphy].
+		    is_ck_swap == 1 && sphy == 0) {
+/* TODO: move this code to per platform one */
+#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
+			/* clock swap for both cs0 and cs1 */
+			data = (INVERT_PAD << INV_PAD2_OFFS |
+				INVERT_PAD << INV_PAD6_OFFS |
+				INVERT_PAD << INV_PAD4_OFFS |
+				INVERT_PAD << INV_PAD5_OFFS);
+			ck_swap_ctrl_sphy = CK_SWAP_CTRL_PHY_NUM;
+			ddr3_tip_bus_read_modify_write(0, ACCESS_TYPE_UNICAST,
+						       0, ck_swap_ctrl_sphy,
+						       DDR_PHY_CONTROL,
+						       PHY_CTRL_PHY_REG,
+						       data, data);
+#else /* !CONFIG_ARMADA_38X && !CONFIG_ARMADA_39X && !A70X0 && !A80X0 && !A3900 */
+#pragma message "unknown platform to configure ddr clock swap"
+#endif
+		}
+	}
+
+	return MV_OK;
+}
+
-static int ddr3_tip_pad_inv(u32 dev_num, u32 if_id);
 static int ddr3_tip_rank_control(u32 dev_num, u32 if_id);
 
 /*
@@ -244,6 +264,7 @@
 	if (params->g_rtt_park != PARAM_UNDEFINED)
 		g_rtt_park = params->g_rtt_park;
 
+
 	DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
 			  ("DGL parameters: 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n",
 			   g_zpri_data, g_znri_data, g_zpri_ctrl, g_znri_ctrl, g_zpodt_data, g_znodt_data,
@@ -304,44 +325,6 @@
 			      DUNIT_CTRL_LOW_REG, (enable << 15), 1 << 15));
 		break;
 	}
-
-	return MV_OK;
-}
-
-/*
- * Calculate number of CS
- */
-int calc_cs_num(u32 dev_num, u32 if_id, u32 *cs_num)
-{
-	u32 cs;
-	u32 bus_cnt;
-	u32 cs_count;
-	u32 cs_bitmask;
-	u32 curr_cs_num = 0;
-	u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
-	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
-
-	for (bus_cnt = 0; bus_cnt < octets_per_if_num; bus_cnt++) {
-		VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt);
-		cs_count = 0;
-		cs_bitmask = tm->interface_params[if_id].
-			as_bus_params[bus_cnt].cs_bitmask;
-		for (cs = 0; cs < MAX_CS_NUM; cs++) {
-			if ((cs_bitmask >> cs) & 1)
-				cs_count++;
-		}
-
-		if (curr_cs_num == 0) {
-			curr_cs_num = cs_count;
-		} else if (cs_count != curr_cs_num) {
-			DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
-					  ("CS number is different per bus (IF %d BUS %d cs_num %d curr_cs_num %d)\n",
-					   if_id, bus_cnt, cs_count,
-					   curr_cs_num));
-			return MV_NOT_SUPPORTED;
-		}
-	}
-	*cs_num = curr_cs_num;
 
 	return MV_OK;
 }
@@ -356,7 +339,7 @@
 	u32 t_ckclk = 0, t_wr = 0, t2t = 0;
 	u32 data_value = 0, cs_cnt = 0,
 		mem_mask = 0, bus_index = 0;
-	enum hws_speed_bin speed_bin_index = SPEED_BIN_DDR_2133N;
+	enum mv_ddr_speed_bin speed_bin_index = SPEED_BIN_DDR_2133N;
 	u32 cs_mask = 0;
 	u32 cl_value = 0, cwl_val = 0;
 	u32 bus_cnt = 0, adll_tap = 0;
@@ -364,8 +347,8 @@
 	u32 data_read[MAX_INTERFACE_NUM];
 	u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
 	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
-	enum hws_ddr_freq freq = tm->interface_params[0].memory_freq;
 	enum mv_ddr_timing timing;
+	enum mv_ddr_freq freq = tm->interface_params[0].memory_freq;
 
 	DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
 			  ("Init_controller, do_mrs_phy=%d, is_ctrl64_bit=%d\n",
@@ -403,7 +386,7 @@
 				speed_bin_index;
 
 			/* t_ckclk is external clock */
-			t_ckclk = (MEGA / freq_val[freq]);
+			t_ckclk = (MEGA / mv_ddr_freq_get(freq));
 
 			if (MV_DDR_IS_HALF_BUS_DRAM_MODE(tm->bus_act_mask, octets_per_if_num))
 				data_value = (0x4000 | 0 | 0x1000000) & ~(1 << 26);
@@ -508,7 +491,7 @@
 			 * configure them both:  The Bust_width it\92s the
 			 * Memory Bus width \96 x8 or x16
 			 */
-			for (cs_cnt = 0; cs_cnt < NUM_OF_CS; cs_cnt++) {
+			for (cs_cnt = 0; cs_cnt < MAX_CS_NUM; cs_cnt++) {
 				ddr3_tip_configure_cs(dev_num, if_id, cs_cnt,
 						      ((cs_mask & (1 << cs_cnt)) ? 1
 						       : 0));
@@ -534,7 +517,7 @@
 						  ("cl_value 0x%x cwl_val 0x%x\n",
 						   cl_value, cwl_val));
 
-				t_wr = time_to_nclk(speed_bin_table
+				t_wr = time_to_nclk(mv_ddr_speed_bin_timing_get
 							   (speed_bin_index,
 							    SPEED_BIN_TWR), t_ckclk);
 
@@ -612,8 +595,7 @@
 				t2t = (timing == MV_DDR_TIM_2T) ? 1 : 0;
 			} else {
 				/* calculate number of CS (per interface) */
-				CHECK_STATUS(calc_cs_num
-					     (dev_num, if_id, &cs_num));
+				cs_num = mv_ddr_cs_num_get();
 				t2t = (cs_num == 1) ? 0 : 1;
 			}
 
@@ -666,9 +648,8 @@
 		VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
 		CHECK_STATUS(ddr3_tip_rank_control(dev_num, if_id));
 
-		if (init_cntr_prm->do_mrs_phy) {
-			CHECK_STATUS(ddr3_tip_pad_inv(dev_num, if_id));
-		}
+		if (init_cntr_prm->do_mrs_phy)
+			ddr3_tip_pad_inv();
 
 		/* Pad calibration control - disable */
 		CHECK_STATUS(ddr3_tip_if_write
@@ -682,7 +663,7 @@
 
 
 	if (delay_enable != 0) {
-		adll_tap = MEGA / (freq_val[freq] * 64);
+		adll_tap = MEGA / (mv_ddr_freq_get(freq) * 64);
 		ddr3_tip_cmd_addr_init_delay(dev_num, adll_tap);
 	}
 
@@ -788,48 +769,6 @@
 }
 
 /*
- * PAD Inverse Flow
- */
-static int ddr3_tip_pad_inv(u32 dev_num, u32 if_id)
-{
-	u32 bus_cnt, data_value, ck_swap_pup_ctrl;
-	u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
-	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
-
-	for (bus_cnt = 0; bus_cnt < octets_per_if_num; bus_cnt++) {
-		VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt);
-		if (tm->interface_params[if_id].
-		    as_bus_params[bus_cnt].is_dqs_swap == 1) {
-			/* dqs swap */
-			ddr3_tip_bus_read_modify_write(dev_num, ACCESS_TYPE_UNICAST,
-						       if_id, bus_cnt,
-						       DDR_PHY_DATA,
-						       PHY_CTRL_PHY_REG, 0xc0,
-						       0xc0);
-		}
-
-		if (tm->interface_params[if_id].
-		    as_bus_params[bus_cnt].is_ck_swap == 1) {
-			if (bus_cnt <= 1)
-				data_value = 0x5 << 2;
-			else
-				data_value = 0xa << 2;
-
-			/* mask equals data */
-			/* ck swap pup is only control pup #0 ! */
-			ck_swap_pup_ctrl = 0;
-			ddr3_tip_bus_read_modify_write(dev_num, ACCESS_TYPE_UNICAST,
-						       if_id, ck_swap_pup_ctrl,
-						       DDR_PHY_CONTROL,
-						       PHY_CTRL_PHY_REG,
-						       data_value, data_value);
-		}
-	}
-
-	return MV_OK;
-}
-
-/*
  * Algorithm Parameters Validation
  */
 int ddr3_tip_validate_algo_var(u32 value, u32 fail_value, char *var_name)
@@ -1182,7 +1121,7 @@
  * ADLL Calibration
  */
 int adll_calibration(u32 dev_num, enum hws_access_type access_type,
-		     u32 if_id, enum hws_ddr_freq frequency)
+		     u32 if_id, enum mv_ddr_freq frequency)
 {
 	struct hws_tip_freq_config_info freq_config_info;
 	u32 bus_cnt = 0;
@@ -1229,7 +1168,7 @@
 	CHECK_STATUS(ddr3_tip_if_write
 		     (dev_num, access_type, if_id, DRAM_PHY_CFG_REG,
 		      0, (0x80000000 | 0x40000000)));
-	mdelay(100 / (freq_val[frequency] / freq_val[DDR_FREQ_LOW_FREQ]));
+	mdelay(100 / (mv_ddr_freq_get(frequency)) / mv_ddr_freq_get(MV_DDR_FREQ_LOW_FREQ));
 	CHECK_STATUS(ddr3_tip_if_write
 		     (dev_num, access_type, if_id, DRAM_PHY_CFG_REG,
 		      (0x80000000 | 0x40000000), (0x80000000 | 0x40000000)));
@@ -1255,7 +1194,7 @@
 }
 
 int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type,
-		      u32 if_id, enum hws_ddr_freq frequency)
+		      u32 if_id, enum mv_ddr_freq frequency)
 {
 	u32 cl_value = 0, cwl_value = 0, mem_mask = 0, val = 0,
 		bus_cnt = 0, t_wr = 0, t_ckclk = 0,
@@ -1263,7 +1202,7 @@
 	u32 end_if, start_if;
 	u32 bus_index = 0;
 	int is_dll_off = 0;
-	enum hws_speed_bin speed_bin_index = 0;
+	enum mv_ddr_speed_bin speed_bin_index = 0;
 	struct hws_tip_freq_config_info freq_config_info;
 	enum hws_result *flow_result = training_result[training_stage];
 	u32 adll_tap = 0;
@@ -1274,12 +1213,13 @@
 	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
 	unsigned int tclk;
 	enum mv_ddr_timing timing = tm->interface_params[if_id].timing;
+	u32 freq = mv_ddr_freq_get(frequency);
 
 	DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
 			  ("dev %d access %d IF %d freq %d\n", dev_num,
 			   access_type, if_id, frequency));
 
-	if (frequency == DDR_FREQ_LOW_FREQ)
+	if (frequency == MV_DDR_FREQ_LOW_FREQ)
 		is_dll_off = 1;
 	if (access_type == ACCESS_TYPE_MULTICAST) {
 		start_if = 0;
@@ -1318,7 +1258,7 @@
 			cwl_value =
 				tm->interface_params[if_id].cas_wl;
 		} else if (tm->cfg_src == MV_DDR_CFG_SPD) {
-			tclk = 1000000 / freq_val[frequency];
+			tclk = 1000000 / freq;
 			cl_value = mv_ddr_cl_calc(tm->timing_data[MV_DDR_TAA_MIN], tclk);
 			if (cl_value == 0) {
 				printf("mv_ddr: unsupported cas latency value found\n");
@@ -1330,11 +1270,8 @@
 				return MV_FAIL;
 			}
 		} else {
-			cl_value =
-				cas_latency_table[speed_bin_index].cl_val[frequency];
-			cwl_value =
-				cas_write_latency_table[speed_bin_index].
-				cl_val[frequency];
+			cl_value = mv_ddr_cl_val_get(speed_bin_index, frequency);
+			cwl_value = mv_ddr_cwl_val_get(speed_bin_index, frequency);
 		}
 
 		DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
@@ -1342,11 +1279,9 @@
 				   dev_num, access_type, if_id,
 				   frequency, speed_bin_index));
 
-		for (cnt_id = 0; cnt_id < DDR_FREQ_LAST; cnt_id++) {
+		for (cnt_id = 0; cnt_id < MV_DDR_FREQ_LAST; cnt_id++) {
 			DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
-					  ("%d ",
-					   cas_latency_table[speed_bin_index].
-					   cl_val[cnt_id]));
+					  ("%d ", mv_ddr_cl_val_get(speed_bin_index, cnt_id)));
 		}
 
 		DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE, ("\n"));
@@ -1420,7 +1355,7 @@
 			t2t = (timing == MV_DDR_TIM_2T) ? 1 : 0;
 		} else {
 			/* Calculate number of CS per interface */
-			CHECK_STATUS(calc_cs_num(dev_num, if_id, &cs_num));
+			cs_num = mv_ddr_cs_num_get();
 			t2t = (cs_num == 1) ? 0 : 1;
 		}
 
@@ -1455,8 +1390,8 @@
 			     (dev_num, access_type, if_id, DFS_REG,
 			      (cwl_mask_table[cwl_value] << 12), 0x7000));
 
-		t_ckclk = (MEGA / freq_val[frequency]);
-		t_wr = time_to_nclk(speed_bin_table
+		t_ckclk = (MEGA / freq);
+		t_wr = time_to_nclk(mv_ddr_speed_bin_timing_get
 					   (speed_bin_index,
 					    SPEED_BIN_TWR), t_ckclk);
 
@@ -1517,7 +1452,7 @@
 			     (dev_num, access_type, if_id,
 			      DRAM_PHY_CFG_REG, 0,
 			      (0x80000000 | 0x40000000)));
-		mdelay(100 / (freq_val[frequency] / freq_val[DDR_FREQ_LOW_FREQ]));
+		mdelay(100 / (freq / mv_ddr_freq_get(MV_DDR_FREQ_LOW_FREQ)));
 		CHECK_STATUS(ddr3_tip_if_write
 			     (dev_num, access_type, if_id,
 			      DRAM_PHY_CFG_REG, (0x80000000 | 0x40000000),
@@ -1544,7 +1479,7 @@
 		/* Set proper timing params before existing Self-Refresh */
 		ddr3_tip_set_timing(dev_num, access_type, if_id, frequency);
 		if (delay_enable != 0) {
-			adll_tap = (is_dll_off == 1) ? 1000 : (MEGA / (freq_val[frequency] * 64));
+			adll_tap = (is_dll_off == 1) ? 1000 : (MEGA / (freq * 64));
 			ddr3_tip_cmd_addr_init_delay(dev_num, adll_tap);
 		}
 
@@ -1682,7 +1617,7 @@
  * Set Timing values for training
  */
 static int ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type,
-			       u32 if_id, enum hws_ddr_freq frequency)
+			       u32 if_id, enum mv_ddr_freq frequency)
 {
 	u32 t_ckclk = 0, t_ras = 0;
 	u32 t_rcd = 0, t_rp = 0, t_wr = 0, t_wtr = 0, t_rrd = 0, t_rtp = 0,
@@ -1690,66 +1625,63 @@
 		t_r2w_w2r = 0x3, t_r2w_w2r_high = 0x1, t_w2w = 0x3;
 	u32 refresh_interval_cnt, t_hclk, t_refi, t_faw, t_pd, t_xpdll;
 	u32 val = 0, page_size = 0, mask = 0;
-	enum hws_speed_bin speed_bin_index;
+	enum mv_ddr_speed_bin speed_bin_index;
 	enum mv_ddr_die_capacity memory_size = MV_DDR_DIE_CAP_2GBIT;
 	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
-	struct page_element *page_param = mv_ddr_page_tbl_get();
+	u32 freq = mv_ddr_freq_get(frequency);
 
 	speed_bin_index = tm->interface_params[if_id].speed_bin_index;
 	memory_size = tm->interface_params[if_id].memory_size;
-	page_size =
-		(tm->interface_params[if_id].bus_width ==
-		 MV_DDR_DEV_WIDTH_8BIT) ? page_param[memory_size].
-		page_size_8bit : page_param[memory_size].page_size_16bit;
-	t_ckclk = (MEGA / freq_val[frequency]);
+	page_size = mv_ddr_page_size_get(tm->interface_params[if_id].bus_width, memory_size);
+	t_ckclk = (MEGA / freq);
 	/* HCLK in[ps] */
-	t_hclk = MEGA / (freq_val[frequency] / config_func_info[dev_num].tip_get_clock_ratio(frequency));
+	t_hclk = MEGA / (freq / config_func_info[dev_num].tip_get_clock_ratio(frequency));
 
 	t_refi = (tm->interface_params[if_id].interface_temp == MV_DDR_TEMP_HIGH) ? TREFI_HIGH : TREFI_LOW;
 	t_refi *= 1000;	/* psec */
 	refresh_interval_cnt = t_refi / t_hclk;	/* no units */
 
 	if (page_size == 1) {
-		t_faw = speed_bin_table(speed_bin_index, SPEED_BIN_TFAW1K);
+		t_faw = mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TFAW1K);
 		t_faw = time_to_nclk(t_faw, t_ckclk);
 		t_faw = GET_MAX_VALUE(20, t_faw);
 	} else {	/* page size =2, we do not support page size 0.5k */
-		t_faw = speed_bin_table(speed_bin_index, SPEED_BIN_TFAW2K);
+		t_faw = mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TFAW2K);
 		t_faw = time_to_nclk(t_faw, t_ckclk);
 		t_faw = GET_MAX_VALUE(28, t_faw);
 	}
 
-	t_pd = GET_MAX_VALUE(t_ckclk * 3, speed_bin_table(speed_bin_index, SPEED_BIN_TPD));
+	t_pd = GET_MAX_VALUE(t_ckclk * 3, mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TPD));
 	t_pd = time_to_nclk(t_pd, t_ckclk);
 
-	t_xpdll = GET_MAX_VALUE(t_ckclk * 10, speed_bin_table(speed_bin_index, SPEED_BIN_TXPDLL));
+	t_xpdll = GET_MAX_VALUE(t_ckclk * 10, mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TXPDLL));
 	t_xpdll = time_to_nclk(t_xpdll, t_ckclk);
 
-	t_rrd =	(page_size == 1) ? speed_bin_table(speed_bin_index,
+	t_rrd =	(page_size == 1) ? mv_ddr_speed_bin_timing_get(speed_bin_index,
 						   SPEED_BIN_TRRD1K) :
-		speed_bin_table(speed_bin_index, SPEED_BIN_TRRD2K);
+		mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TRRD2K);
 	t_rrd = GET_MAX_VALUE(t_ckclk * 4, t_rrd);
-	t_rtp =	GET_MAX_VALUE(t_ckclk * 4, speed_bin_table(speed_bin_index,
+	t_rtp =	GET_MAX_VALUE(t_ckclk * 4, mv_ddr_speed_bin_timing_get(speed_bin_index,
 							   SPEED_BIN_TRTP));
 	t_mod = GET_MAX_VALUE(t_ckclk * 12, 15000);
-	t_wtr = GET_MAX_VALUE(t_ckclk * 4, speed_bin_table(speed_bin_index,
+	t_wtr = GET_MAX_VALUE(t_ckclk * 4, mv_ddr_speed_bin_timing_get(speed_bin_index,
 							   SPEED_BIN_TWTR));
-	t_ras = time_to_nclk(speed_bin_table(speed_bin_index,
+	t_ras = time_to_nclk(mv_ddr_speed_bin_timing_get(speed_bin_index,
 						    SPEED_BIN_TRAS),
 				    t_ckclk);
-	t_rcd = time_to_nclk(speed_bin_table(speed_bin_index,
+	t_rcd = time_to_nclk(mv_ddr_speed_bin_timing_get(speed_bin_index,
 						    SPEED_BIN_TRCD),
 				    t_ckclk);
-	t_rp = time_to_nclk(speed_bin_table(speed_bin_index,
+	t_rp = time_to_nclk(mv_ddr_speed_bin_timing_get(speed_bin_index,
 						   SPEED_BIN_TRP),
 				   t_ckclk);
-	t_wr = time_to_nclk(speed_bin_table(speed_bin_index,
+	t_wr = time_to_nclk(mv_ddr_speed_bin_timing_get(speed_bin_index,
 						   SPEED_BIN_TWR),
 				   t_ckclk);
 	t_wtr = time_to_nclk(t_wtr, t_ckclk);
 	t_rrd = time_to_nclk(t_rrd, t_ckclk);
 	t_rtp = time_to_nclk(t_rtp, t_ckclk);
-	t_rfc = time_to_nclk(rfc_table[memory_size] * 1000, t_ckclk);
+	t_rfc = time_to_nclk(mv_ddr_rfc_get(memory_size) * 1000, t_ckclk);
 	t_mod = time_to_nclk(t_mod, t_ckclk);
 
 	/* SDRAM Timing Low */
@@ -1827,68 +1759,6 @@
 
 
 /*
- * Mode Read
- */
-int hws_ddr3_tip_mode_read(u32 dev_num, struct mode_info *mode_info)
-{
-	u32 ret;
-
-	ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
-			       MR0_REG, mode_info->reg_mr0, MASK_ALL_BITS);
-	if (ret != MV_OK)
-		return ret;
-
-	ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
-			       MR1_REG, mode_info->reg_mr1, MASK_ALL_BITS);
-	if (ret != MV_OK)
-		return ret;
-
-	ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
-			       MR2_REG, mode_info->reg_mr2, MASK_ALL_BITS);
-	if (ret != MV_OK)
-		return ret;
-
-	ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
-			       MR3_REG, mode_info->reg_mr2, MASK_ALL_BITS);
-	if (ret != MV_OK)
-		return ret;
-
-	ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
-			       RD_DATA_SMPL_DLYS_REG, mode_info->read_data_sample,
-			       MASK_ALL_BITS);
-	if (ret != MV_OK)
-		return ret;
-
-	ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
-			       RD_DATA_RDY_DLYS_REG, mode_info->read_data_ready,
-			       MASK_ALL_BITS);
-	if (ret != MV_OK)
-		return ret;
-
-	return MV_OK;
-}
-
-/*
- * Get first active IF
- */
-int ddr3_tip_get_first_active_if(u8 dev_num, u32 interface_mask,
-				 u32 *interface_id)
-{
-	u32 if_id;
-	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
-
-	for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
-		VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
-		if (interface_mask & (1 << if_id)) {
-			*interface_id = if_id;
-			break;
-		}
-	}
-
-	return MV_OK;
-}
-
-/*
  * Write CS Result
  */
 int ddr3_tip_write_cs_result(u32 dev_num, u32 offset)
@@ -2139,9 +2009,10 @@
 	int ret = MV_OK;
 	int adll_bypass_flag = 0;
 	u32 if_id;
-	u32 max_cs = ddr3_tip_max_cs_get(dev_num);
+	unsigned int max_cs = mv_ddr_cs_num_get();
 	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
-	enum hws_ddr_freq freq = tm->interface_params[0].memory_freq;
+	enum mv_ddr_freq freq = tm->interface_params[0].memory_freq;
+	unsigned int *freq_tbl = mv_ddr_freq_tbl_get();
 
 #ifdef DDR_VIEWER_TOOL
 	if (debug_training == DEBUG_LEVEL_TRACE) {
@@ -2157,7 +2028,7 @@
 	/* Set to 0 after each loop to avoid illegal value may be used */
 	effective_cs = 0;
 
-	freq_val[DDR_FREQ_LOW_FREQ] = dfs_low_freq;
+	freq_tbl[MV_DDR_FREQ_LOW_FREQ] = dfs_low_freq;
 
 	if (is_pll_before_init != 0) {
 		for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
@@ -2220,7 +2091,7 @@
 
 		DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
 				  ("SET_LOW_FREQ_MASK_BIT %d\n",
-				   freq_val[low_freq]));
+				   freq_tbl[low_freq]));
 		ret = ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST,
 					PARAM_NOT_CARE, low_freq);
 		if (is_reg_dump != 0)
@@ -2281,7 +2152,7 @@
 		training_stage = SET_MEDIUM_FREQ;
 		DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
 				  ("SET_MEDIUM_FREQ_MASK_BIT %d\n",
-				   freq_val[medium_freq]));
+				   freq_tbl[medium_freq]));
 		ret =
 			ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST,
 					  PARAM_NOT_CARE, medium_freq);
@@ -2299,7 +2170,7 @@
 		training_stage = WRITE_LEVELING;
 		DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
 				  ("WRITE_LEVELING_MASK_BIT\n"));
-		if ((rl_mid_freq_wa == 0) || (freq_val[medium_freq] == 533)) {
+		if ((rl_mid_freq_wa == 0) || (freq_tbl[medium_freq] == 533)) {
 			ret = ddr3_tip_dynamic_write_leveling(dev_num, 0);
 		} else {
 			/* Use old WL */
@@ -2341,7 +2212,7 @@
 		training_stage = READ_LEVELING;
 		DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
 				  ("READ_LEVELING_MASK_BIT\n"));
-		if ((rl_mid_freq_wa == 0) || (freq_val[medium_freq] == 533)) {
+		if ((rl_mid_freq_wa == 0) || (freq_tbl[medium_freq] == 533)) {
 			ret = ddr3_tip_dynamic_read_leveling(dev_num, medium_freq);
 		} else {
 			/* Use old RL */
@@ -2417,19 +2288,13 @@
 		training_stage = SET_TARGET_FREQ;
 		DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
 				  ("SET_TARGET_FREQ_MASK_BIT %d\n",
-				   freq_val[tm->
+				   freq_tbl[tm->
 					    interface_params[first_active_if].
 					    memory_freq]));
 		ret = ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST,
 					PARAM_NOT_CARE,
 					tm->interface_params[first_active_if].
 					memory_freq);
-#if defined(A70X0) || defined(A80X0)
-	if (apn806_rev_id_get() == APN806_REV_ID_A0) {
-		reg_write(0x6f812c, extension_avs);
-		reg_write(0x6f8130, nominal_avs);
-	}
-#endif /* #if defined(A70X0) || defined(A80X0) */
 		if (is_reg_dump != 0)
 			ddr3_tip_reg_dump(dev_num);
 		if (ret != MV_OK) {
@@ -2892,3 +2757,140 @@
 
 	return MV_OK;
 }
+
+/* TODO: consider to move to misl phy driver */
+enum {
+	MISL_PHY_DRV_OHM_30 = 0xf,
+	MISL_PHY_DRV_OHM_48 = 0xa,
+	MISL_PHY_DRV_OHM_80 = 0x6,
+	MISL_PHY_DRV_OHM_120 = 0x4
+};
+
+enum {
+	MISL_PHY_ODT_OHM_60 = 0x8,
+	MISL_PHY_ODT_OHM_80 = 0x6,
+	MISL_PHY_ODT_OHM_120 = 0x4,
+	MISL_PHY_ODT_OHM_240 = 0x2
+};
+
+static unsigned int mv_ddr_misl_phy_drv_calc(unsigned int cfg)
+{
+	unsigned int val;
+
+	switch (cfg) {
+	case MV_DDR_OHM_30:
+		val = MISL_PHY_DRV_OHM_30;
+		break;
+	case MV_DDR_OHM_48:
+		val = MISL_PHY_DRV_OHM_48;
+		break;
+	case MV_DDR_OHM_80:
+		val = MISL_PHY_DRV_OHM_80;
+		break;
+	case MV_DDR_OHM_120:
+		val = MISL_PHY_DRV_OHM_120;
+		break;
+	default:
+		val = PARAM_UNDEFINED;
+	}
+
+	return val;
+}
+
+static unsigned int mv_ddr_misl_phy_odt_calc(unsigned int cfg)
+{
+	unsigned int val;
+
+	switch (cfg) {
+	case MV_DDR_OHM_60:
+		val = MISL_PHY_ODT_OHM_60;
+		break;
+	case MV_DDR_OHM_80:
+		val = MISL_PHY_ODT_OHM_80;
+		break;
+	case MV_DDR_OHM_120:
+		val = MISL_PHY_ODT_OHM_120;
+		break;
+	case MV_DDR_OHM_240:
+		val = MISL_PHY_ODT_OHM_240;
+		break;
+	default:
+		val = PARAM_UNDEFINED;
+	}
+
+	return val;
+}
+
+unsigned int mv_ddr_misl_phy_drv_data_p_get(void)
+{
+	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
+	unsigned int drv_data_p = mv_ddr_misl_phy_drv_calc(tm->edata.phy_edata.drv_data_p);
+
+	if (drv_data_p == PARAM_UNDEFINED)
+		printf("error: %s: unsupported drv_data_p parameter found\n", __func__);
+
+	return drv_data_p;
+}
+
+unsigned int mv_ddr_misl_phy_drv_data_n_get(void)
+{
+	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
+	unsigned int drv_data_n = mv_ddr_misl_phy_drv_calc(tm->edata.phy_edata.drv_data_n);
+
+	if (drv_data_n == PARAM_UNDEFINED)
+		printf("error: %s: unsupported drv_data_n parameter found\n", __func__);
+
+	return drv_data_n;
+}
+
+unsigned int mv_ddr_misl_phy_drv_ctrl_p_get(void)
+{
+	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
+	unsigned int drv_ctrl_p = mv_ddr_misl_phy_drv_calc(tm->edata.phy_edata.drv_ctrl_p);
+
+	if (drv_ctrl_p == PARAM_UNDEFINED)
+		printf("error: %s: unsupported drv_ctrl_p parameter found\n", __func__);
+
+	return drv_ctrl_p;
+}
+
+unsigned int mv_ddr_misl_phy_drv_ctrl_n_get(void)
+{
+	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
+	unsigned int drv_ctrl_n = mv_ddr_misl_phy_drv_calc(tm->edata.phy_edata.drv_ctrl_n);
+
+	if (drv_ctrl_n == PARAM_UNDEFINED)
+		printf("error: %s: unsupported drv_ctrl_n parameter found\n", __func__);
+
+	return drv_ctrl_n;
+}
+
+unsigned int mv_ddr_misl_phy_odt_p_get(void)
+{
+	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
+	unsigned int cs_num = mv_ddr_cs_num_get();
+	unsigned int odt_p = PARAM_UNDEFINED;
+
+	if (cs_num > 0 && cs_num <= MAX_CS_NUM)
+		odt_p = mv_ddr_misl_phy_odt_calc(tm->edata.phy_edata.odt_p[cs_num - 1]);
+
+	if (odt_p == PARAM_UNDEFINED)
+		printf("error: %s: unsupported odt_p parameter found\n", __func__);
+
+	return odt_p;
+}
+
+unsigned int mv_ddr_misl_phy_odt_n_get(void)
+{
+	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
+	unsigned int cs_num = mv_ddr_cs_num_get();
+	unsigned int odt_n = PARAM_UNDEFINED;
+
+	if (cs_num > 0 && cs_num <= MAX_CS_NUM)
+		odt_n = mv_ddr_misl_phy_odt_calc(tm->edata.phy_edata.odt_n[cs_num - 1]);
+
+	if (odt_n == PARAM_UNDEFINED)
+		printf("error: %s: unsupported odt_n parameter found\n", __func__);
+
+	return odt_n;
+}
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_bist.c b/drivers/ddr/marvell/a38x/ddr3_training_bist.c
index e29b171..d388a17 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_bist.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_bist.c
@@ -4,6 +4,7 @@
  */
 
 #include "ddr3_init.h"
+#include "mv_ddr_regs.h"
 
 static u32 bist_offset = 32;
 enum hws_pattern sweep_pattern = PATTERN_KILLER_DQ0;
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_centralization.c b/drivers/ddr/marvell/a38x/ddr3_training_centralization.c
index 03e5c9f..648b37e 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_centralization.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_centralization.c
@@ -4,6 +4,7 @@
  */
 
 #include "ddr3_init.h"
+#include "mv_ddr_regs.h"
 
 #define VALIDATE_WIN_LENGTH(e1, e2, maxsize)		\
 	(((e2) + 1 > (e1) + (u8)MIN_WINDOW_SIZE) &&	\
@@ -698,6 +699,8 @@
 	u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
 	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
 
+	dev_num = dev_num;
+
 	printf("Centralization Results\n");
 	printf("I/F0 Result[0 - success 1-fail 2 - state_2 3 - state_3] ...\n");
 	for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_db.c b/drivers/ddr/marvell/a38x/ddr3_training_db.c
index c0089f6..111a858 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_db.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_db.c
@@ -3,11 +3,16 @@
  * Copyright (C) Marvell International Ltd. and its affiliates
  */
 
-#include "ddr3_init.h"
+#include "ddr_ml_wrapper.h"
+
+#include "ddr3_training_ip_flow.h"
+#include "mv_ddr_topology.h"
+#include "mv_ddr_training_db.h"
+#include "ddr3_training_ip_db.h"
 
 /* Device attributes structures */
-enum mv_ddr_dev_attribute ddr_dev_attributes[MAX_DEVICE_NUM][MV_ATTR_LAST];
-int ddr_dev_attr_init_done[MAX_DEVICE_NUM] = { 0 };
+enum mv_ddr_dev_attribute ddr_dev_attributes[MV_ATTR_LAST];
+int ddr_dev_attr_init_done = 0;
 
 static inline u32 pattern_table_get_killer_word16(u8 dqs, u8 index);
 static inline u32 pattern_table_get_sso_word(u8 sso, u8 index);
@@ -20,28 +25,38 @@
 static inline u32 pattern_table_get_isi_word(u8 index);
 static inline u32 pattern_table_get_isi_word16(u8 index);
 
-/* List of allowed frequency listed in order of enum hws_ddr_freq */
-u32 freq_val[DDR_FREQ_LAST] = {
-	0,			/*DDR_FREQ_LOW_FREQ */
-	400,			/*DDR_FREQ_400, */
-	533,			/*DDR_FREQ_533, */
-	666,			/*DDR_FREQ_667, */
-	800,			/*DDR_FREQ_800, */
-	933,			/*DDR_FREQ_933, */
-	1066,			/*DDR_FREQ_1066, */
-	311,			/*DDR_FREQ_311, */
-	333,			/*DDR_FREQ_333, */
-	467,			/*DDR_FREQ_467, */
-	850,			/*DDR_FREQ_850, */
-	600,			/*DDR_FREQ_600 */
-	300,			/*DDR_FREQ_300 */
-	900,			/*DDR_FREQ_900 */
-	360,			/*DDR_FREQ_360 */
-	1000			/*DDR_FREQ_1000 */
+/* List of allowed frequency listed in order of enum mv_ddr_freq */
+static unsigned int freq_val[MV_DDR_FREQ_LAST] = {
+	0,			/*MV_DDR_FREQ_LOW_FREQ */
+	400,			/*MV_DDR_FREQ_400, */
+	533,			/*MV_DDR_FREQ_533, */
+	666,			/*MV_DDR_FREQ_667, */
+	800,			/*MV_DDR_FREQ_800, */
+	933,			/*MV_DDR_FREQ_933, */
+	1066,			/*MV_DDR_FREQ_1066, */
+	311,			/*MV_DDR_FREQ_311, */
+	333,			/*MV_DDR_FREQ_333, */
+	467,			/*MV_DDR_FREQ_467, */
+	850,			/*MV_DDR_FREQ_850, */
+	600,			/*MV_DDR_FREQ_600 */
+	300,			/*MV_DDR_FREQ_300 */
+	900,			/*MV_DDR_FREQ_900 */
+	360,			/*MV_DDR_FREQ_360 */
+	1000			/*MV_DDR_FREQ_1000 */
 };
 
-/* Table for CL values per frequency for each speed bin index */
-struct cl_val_per_freq cas_latency_table[] = {
+unsigned int *mv_ddr_freq_tbl_get(void)
+{
+	return &freq_val[0];
+}
+
+u32 mv_ddr_freq_get(enum mv_ddr_freq freq)
+{
+	return freq_val[freq];
+}
+
+/* cas latency values per frequency for each speed bin index */
+static struct mv_ddr_cl_val_per_freq cl_table[] = {
 	/*
 	 * 400M   667M     933M   311M     467M  600M    360
 	 * 100M    533M    800M    1066M   333M    850M      900
@@ -97,8 +112,13 @@
 	{ {6, 6, 7, 9, 11, 13, 0, 6, 6, 7, 13, 9, 6, 13, 6, 13} },
 };
 
-/* Table for CWL values per speedbin index */
-struct cl_val_per_freq cas_write_latency_table[] = {
+u32 mv_ddr_cl_val_get(u32 index, u32 freq)
+{
+	return cl_table[index].cl_val[freq];
+}
+
+/* cas write latency values per frequency for each speed bin index */
+static struct mv_ddr_cl_val_per_freq cwl_table[] = {
 	/*
 	 * 400M   667M     933M   311M     467M  600M    360
 	 * 100M    533M    800M    1066M   333M    850M      900
@@ -154,6 +174,11 @@
 	{ {5, 5, 6, 7, 8, 9, 0, 5, 5, 6, 9, 7, 5, 9, 5, 9} },
 };
 
+u32 mv_ddr_cwl_val_get(u32 index, u32 freq)
+{
+	return cwl_table[index].cl_val[freq];
+}
+
 u8 twr_mask_table[] = {
 	10,
 	10,
@@ -213,18 +238,23 @@
 };
 
 /* RFC values (in ns) */
-u16 rfc_table[] = {
-	90,			/* 512M */
-	110,			/* 1G */
-	160,			/* 2G */
-	260,			/* 4G */
-	350,			/* 8G */
-	0,			/* TODO: placeholder for 16-Mbit dev width */
-	0,			/* TODO: placeholder for 32-Mbit dev width */
-	0,			/* TODO: placeholder for 12-Mbit dev width */
-	0			/* TODO: placeholder for 24-Mbit dev width */
+static unsigned int rfc_table[] = {
+	90,	/* 512M */
+	110,	/* 1G */
+	160,	/* 2G */
+	260,	/* 4G */
+	350,	/* 8G */
+	0,	/* TODO: placeholder for 16-Mbit dev width */
+	0,	/* TODO: placeholder for 32-Mbit dev width */
+	0,	/* TODO: placeholder for 12-Mbit dev width */
+	0	/* TODO: placeholder for 24-Mbit dev width */
 };
 
+u32 mv_ddr_rfc_get(u32 mem)
+{
+	return rfc_table[mem];
+}
+
 u32 speed_bin_table_t_rc[] = {
 	50000,
 	52500,
@@ -358,8 +388,29 @@
 	0xfe
 };
 
+static struct mv_ddr_page_element page_tbl[] = {
+	/* 8-bit, 16-bit page size */
+	{MV_DDR_PAGE_SIZE_1K, MV_DDR_PAGE_SIZE_2K}, /* 512M */
+	{MV_DDR_PAGE_SIZE_1K, MV_DDR_PAGE_SIZE_2K}, /* 1G */
+	{MV_DDR_PAGE_SIZE_1K, MV_DDR_PAGE_SIZE_2K}, /* 2G */
+	{MV_DDR_PAGE_SIZE_1K, MV_DDR_PAGE_SIZE_2K}, /* 4G */
+	{MV_DDR_PAGE_SIZE_2K, MV_DDR_PAGE_SIZE_2K}, /* 8G */
+	{0, 0}, /* TODO: placeholder for 16-Mbit die capacity */
+	{0, 0}, /* TODO: placeholder for 32-Mbit die capacity */
+	{0, 0}, /* TODO: placeholder for 12-Mbit die capacity */
+	{0, 0}  /* TODO: placeholder for 24-Mbit die capacity */
+};
+
+u32 mv_ddr_page_size_get(enum mv_ddr_dev_width bus_width, enum mv_ddr_die_capacity mem_size)
+{
+	if (bus_width == MV_DDR_DEV_WIDTH_8BIT)
+		return page_tbl[mem_size].page_size_8bit;
+	else
+		return page_tbl[mem_size].page_size_16bit;
+}
+
 /* Return speed Bin value for selected index and t* element */
-u32 speed_bin_table(u8 index, enum speed_bin_table_elements element)
+unsigned int mv_ddr_speed_bin_timing_get(enum mv_ddr_speed_bin index, enum mv_ddr_speed_bin_timing element)
 {
 	u32 result = 0;
 
@@ -384,19 +435,19 @@
 		result = speed_bin_table_t_rc[index];
 		break;
 	case SPEED_BIN_TRRD1K:
-		if (index < SPEED_BIN_DDR_800E)
+		if (index <= SPEED_BIN_DDR_800E)
 			result = 10000;
-		else if (index < SPEED_BIN_DDR_1066G)
+		else if (index <= SPEED_BIN_DDR_1066G)
 			result = 7500;
-		else if (index < SPEED_BIN_DDR_1600K)
+		else if (index <= SPEED_BIN_DDR_1600K)
 			result = 6000;
 		else
 			result = 5000;
 		break;
 	case SPEED_BIN_TRRD2K:
-		if (index < SPEED_BIN_DDR_1066G)
+		if (index <= SPEED_BIN_DDR_1066G)
 			result = 10000;
-		else if (index < SPEED_BIN_DDR_1600K)
+		else if (index <= SPEED_BIN_DDR_1600K)
 			result = 7500;
 		else
 			result = 6000;
@@ -410,23 +461,23 @@
 			result = 5000;
 		break;
 	case SPEED_BIN_TFAW1K:
-		if (index < SPEED_BIN_DDR_800E)
+		if (index <= SPEED_BIN_DDR_800E)
 			result = 40000;
-		else if (index < SPEED_BIN_DDR_1066G)
+		else if (index <= SPEED_BIN_DDR_1066G)
 			result = 37500;
-		else if (index < SPEED_BIN_DDR_1600K)
+		else if (index <= SPEED_BIN_DDR_1600K)
 			result = 30000;
-		else if (index < SPEED_BIN_DDR_1866M)
+		else if (index <= SPEED_BIN_DDR_1866M)
 			result = 27000;
 		else
 			result = 25000;
 		break;
 	case SPEED_BIN_TFAW2K:
-		if (index < SPEED_BIN_DDR_1066G)
+		if (index <= SPEED_BIN_DDR_1066G)
 			result = 50000;
-		else if (index < SPEED_BIN_DDR_1333J)
+		else if (index <= SPEED_BIN_DDR_1333J)
 			result = 45000;
-		else if (index < SPEED_BIN_DDR_1600K)
+		else if (index <= SPEED_BIN_DDR_1600K)
 			result = 40000;
 		else
 			result = 35000;
@@ -446,6 +497,9 @@
 	case SPEED_BIN_TXPDLL:
 		result = 24000;
 		break;
+	case SPEED_BIN_TXSDLL:
+		result = 512;
+		break;
 	default:
 		break;
 	}
@@ -608,7 +662,7 @@
 
 u32 pattern_table_get_word(u32 dev_num, enum hws_pattern type, u8 index)
 {
-	u32 pattern;
+	u32 pattern = 0;
 	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
 
 	if (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask) == 0) {
@@ -696,8 +750,8 @@
 			pattern = pattern_table_get_isi_word(index);
 			break;
 		default:
-			DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR, ("Error: %s: pattern type [%d] not supported\n",
-							      __func__, (int)type));
+			printf("error: %s: unsupported pattern type [%d] found\n",
+			       __func__, (int)type);
 			pattern = 0;
 			break;
 		}
@@ -779,8 +833,8 @@
 			pattern = pattern_table_get_isi_word16(index);
 			break;
 		default:
-			DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR, ("Error: %s: pattern type [%d] not supported\n",
-							      __func__, (int)type));
+			printf("error: %s: unsupported pattern type [%d] found\n",
+			       __func__, (int)type);
 			pattern = 0;
 			break;
 		}
@@ -795,23 +849,23 @@
 	u32 attr_id;
 
 	for (attr_id = 0; attr_id < MV_ATTR_LAST; attr_id++)
-		ddr_dev_attributes[dev_num][attr_id] = 0xFF;
+		ddr_dev_attributes[attr_id] = 0xFF;
 
-	ddr_dev_attr_init_done[dev_num] = 1;
+	ddr_dev_attr_init_done = 1;
 }
 
 u32 ddr3_tip_dev_attr_get(u32 dev_num, enum mv_ddr_dev_attribute attr_id)
 {
-	if (ddr_dev_attr_init_done[dev_num] == 0)
+	if (ddr_dev_attr_init_done == 0)
 		ddr3_tip_dev_attr_init(dev_num);
 
-	return ddr_dev_attributes[dev_num][attr_id];
+	return ddr_dev_attributes[attr_id];
 }
 
 void ddr3_tip_dev_attr_set(u32 dev_num, enum mv_ddr_dev_attribute attr_id, u32 value)
 {
-	if (ddr_dev_attr_init_done[dev_num] == 0)
+	if (ddr_dev_attr_init_done == 0)
 		ddr3_tip_dev_attr_init(dev_num);
 
-	ddr_dev_attributes[dev_num][attr_id] = value;
+	ddr_dev_attributes[attr_id] = value;
 }
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
index 6b8aae8..db0f8ad 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
@@ -4,6 +4,7 @@
  */
 
 #include "ddr3_init.h"
+#include "mv_ddr_regs.h"
 
 #define VREF_INITIAL_STEP		3
 #define VREF_SECOND_STEP		1
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip.h b/drivers/ddr/marvell/a38x/ddr3_training_ip.h
index 531103c..056c214 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip.h
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip.h
@@ -6,12 +6,8 @@
 #ifndef _DDR3_TRAINING_IP_H_
 #define _DDR3_TRAINING_IP_H_
 
-#include "ddr3_training_ip_def.h"
 #include "ddr_topology_def.h"
-#include "ddr_training_ip_db.h"
 
-#define MAX_CS_NUM		4
-#define MAX_TOTAL_BUS_NUM	(MAX_INTERFACE_NUM * MAX_BUS_NUM)
 #define TIP_ENG_LOCK	0x02000000
 #define TIP_TX_DLL_RANGE_MAX	64
 
@@ -112,40 +108,11 @@
 	u8 pattern_len;
 };
 
-/* CL value for each frequency */
-struct cl_val_per_freq {
-	u8 cl_val[DDR_FREQ_LAST];
-};
-
 struct cs_element {
 	u8 cs_num;
 	u8 num_of_cs;
 };
 
-struct mode_info {
-	/* 32 bits representing MRS bits */
-	u32 reg_mr0[MAX_INTERFACE_NUM];
-	u32 reg_mr1[MAX_INTERFACE_NUM];
-	u32 reg_mr2[MAX_INTERFACE_NUM];
-	u32 reg_m_r3[MAX_INTERFACE_NUM];
-	/*
-	 * Each element in array represent read_data_sample register delay for
-	 * a specific interface.
-	 * Each register, 4 bits[0+CS*8 to 4+CS*8] represent Number of DDR
-	 * cycles from read command until data is ready to be fetched from
-	 * the PHY, when accessing CS.
-	 */
-	u32 read_data_sample[MAX_INTERFACE_NUM];
-	/*
-	 * Each element in array represent read_data_sample register delay for
-	 * a specific interface.
-	 * Each register, 4 bits[0+CS*8 to 4+CS*8] represent the total delay
-	 * from read command until opening the read mask, when accessing CS.
-	 * This field defines the delay in DDR cycles granularity.
-	 */
-	u32 read_data_ready[MAX_INTERFACE_NUM];
-};
-
 struct hws_tip_freq_config_info {
 	u8 is_supported;
 	u8 bw_per_freq;
@@ -173,12 +140,7 @@
 int hws_ddr3_tip_load_topology_map(u32 dev_num,
 				   struct mv_ddr_topology_map *topology);
 int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type);
-int hws_ddr3_tip_mode_read(u32 dev_num, struct mode_info *mode_info);
-int hws_ddr3_tip_read_training_result(u32 dev_num,
-		enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM]);
 int ddr3_tip_is_pup_lock(u32 *pup_buf, enum hws_training_result read_mode);
 u8 ddr3_tip_get_buf_min(u8 *buf_ptr);
 u8 ddr3_tip_get_buf_max(u8 *buf_ptr);
-uint64_t mv_ddr_get_memory_size_per_cs_in_bits(void);
-uint64_t mv_ddr_get_total_memory_size_in_bits(void);
 #endif /* _DDR3_TRAINING_IP_H_ */
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h b/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
index 2318ceb..2a68669 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
@@ -75,32 +75,6 @@
 #define GET_RESULT_STATE(res)		(res)
 #define SET_RESULT_STATE(res, state)	(res = state)
 
-#define _1K				0x00000400
-#define _4K				0x00001000
-#define _8K				0x00002000
-#define _16K				0x00004000
-#define _32K				0x00008000
-#define _64K				0x00010000
-#define _128K				0x00020000
-#define _256K				0x00040000
-#define _512K				0x00080000
-
-#define _1M				0x00100000
-#define _2M				0x00200000
-#define _4M				0x00400000
-#define _8M				0x00800000
-#define _16M				0x01000000
-#define _32M				0x02000000
-#define _64M				0x04000000
-#define _128M				0x08000000
-#define _256M				0x10000000
-#define _512M				0x20000000
-
-#define _1G				0x40000000
-#define _2G				0x80000000
-#define _4G				0x100000000
-#define _8G				0x200000000
-
 #define ADDR_SIZE_512MB			0x04000000
 #define ADDR_SIZE_1GB			0x08000000
 #define ADDR_SIZE_2GB			0x10000000
@@ -126,11 +100,6 @@
 	HWS_SEARCH_DIR_LIMIT
 };
 
-enum hws_page_size {
-	PAGE_SIZE_1K,
-	PAGE_SIZE_2K
-};
-
 enum hws_operation {
 	OPERATION_READ = 0,
 	OPERATION_WRITE = 1
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
index 334c290..74417d6 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
@@ -4,6 +4,8 @@
  */
 
 #include "ddr3_init.h"
+#include "mv_ddr_regs.h"
+#include "ddr_training_ip_db.h"
 
 #define PATTERN_1	0x55555555
 #define PATTERN_2	0xaaaaaaaa
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.h b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.h
index 8fbcff5..2d40e68 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.h
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.h
@@ -8,6 +8,7 @@
 
 #include "ddr3_training_ip_def.h"
 #include "ddr3_training_ip_flow.h"
+#include "ddr3_training_ip_pbs.h"
 
 #define EDGE_1				0
 #define EDGE_2				1
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h b/drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h
index 6a9ef35..ab152cb 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h
@@ -7,71 +7,17 @@
 #define _DDR3_TRAINING_IP_FLOW_H_
 
 #include "ddr3_training_ip.h"
-#include "ddr3_training_ip_pbs.h"
-#include "mv_ddr_regs.h"
+#include "ddr3_training_ip_db.h"
 
 #define KILLER_PATTERN_LENGTH		32
 #define EXT_ACCESS_BURST_LENGTH		8
 
-#define IS_ACTIVE(mask, id) \
-	((mask) & (1 << (id)))
-
-#define VALIDATE_ACTIVE(mask, id)		\
-	{					\
-	if (IS_ACTIVE(mask, id) == 0)		\
-		continue;			\
-	}
-
-#define IS_IF_ACTIVE(if_mask, if_id) \
-	((if_mask) & (1 << (if_id)))
-
-#define VALIDATE_IF_ACTIVE(mask, id)		\
-	{					\
-	if (IS_IF_ACTIVE(mask, id) == 0)	\
-		continue;			\
-	}
-
-#define IS_BUS_ACTIVE(if_mask , if_id) \
-	(((if_mask) >> (if_id)) & 1)
-
-#define VALIDATE_BUS_ACTIVE(mask, id)		\
-	{					\
-	if (IS_BUS_ACTIVE(mask, id) == 0)	\
-		continue;			\
-	}
-
-#define DDR3_IS_ECC_PUP3_MODE(if_mask) \
-	(((if_mask) == BUS_MASK_16BIT_ECC_PUP3) ? 1 : 0)
-
-#define DDR3_IS_ECC_PUP4_MODE(if_mask) \
-	((if_mask == BUS_MASK_32BIT_ECC || if_mask == BUS_MASK_16BIT_ECC) ? 1 : 0)
-
-#define DDR3_IS_16BIT_DRAM_MODE(mask) \
-	((mask == BUS_MASK_16BIT || mask == BUS_MASK_16BIT_ECC || mask == BUS_MASK_16BIT_ECC_PUP3) ? 1 : 0)
-
-#define DDR3_IS_ECC_PUP8_MODE(if_mask) \
-	((if_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK || if_mask == MV_DDR_64BIT_ECC_PUP8_BUS_MASK) ? 1 : 0)
-
-#define MV_DDR_IS_64BIT_DRAM_MODE(mask) \
-	((((mask) & MV_DDR_64BIT_BUS_MASK) == MV_DDR_64BIT_BUS_MASK) || \
-	(((mask) & MV_DDR_64BIT_ECC_PUP8_BUS_MASK) == MV_DDR_64BIT_ECC_PUP8_BUS_MASK) ? 1 : 0)
-
-#define MV_DDR_IS_32BIT_IN_64BIT_DRAM_MODE(mask, octets_per_if_num/* FIXME: get from ATF */) \
-	((octets_per_if_num == 9/* FIXME: get from ATF */) && \
-	((mask == BUS_MASK_32BIT) || \
-	(mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK)) ? 1 : 0)
-
-#define MV_DDR_IS_HALF_BUS_DRAM_MODE(mask, octets_per_if_num/* FIXME: get from ATF */) \
-	(MV_DDR_IS_32BIT_IN_64BIT_DRAM_MODE(mask, octets_per_if_num) || DDR3_IS_16BIT_DRAM_MODE(mask))
-
 #define ECC_READ_BUS_0			0
 #define ECC_PHY_ACCESS_3		3
 #define ECC_PHY_ACCESS_4		4
 #define ECC_PHY_ACCESS_8		8
-#define MEGA				1000000
 #define BUS_WIDTH_IN_BITS		8
 #define MAX_POLLING_ITERATIONS		1000000
-#define NUM_OF_CS			4
 #define ADLL_LENGTH			32
 
 #define GP_RSVD0_REG			0x182e0
@@ -92,8 +38,6 @@
  */
 
 /* nsec */
-#define  TREFI_LOW				7800
-#define  TREFI_HIGH				3900
 #define AUTO_ZQC_TIMING				15384
 
 enum mr_number {
@@ -114,20 +58,11 @@
 	int is_pup_fail;
 };
 
-struct page_element {
-	enum hws_page_size page_size_8bit;
-	/* page size in 8 bits bus width */
-	enum hws_page_size page_size_16bit;
-	/* page size in 16 bits bus width */
-	u32 ui_page_mask;
-	/* Mask used in register */
-};
-
 int ddr3_tip_write_leveling_static_config(u32 dev_num, u32 if_id,
-					  enum hws_ddr_freq frequency,
+					  enum mv_ddr_freq frequency,
 					  u32 *round_trip_delay_arr);
 int ddr3_tip_read_leveling_static_config(u32 dev_num, u32 if_id,
-					 enum hws_ddr_freq frequency,
+					 enum mv_ddr_freq frequency,
 					 u32 *total_round_trip_delay_arr);
 int ddr3_tip_if_write(u32 dev_num, enum hws_access_type interface_access,
 		      u32 if_id, u32 reg_addr, u32 data_value, u32 mask);
@@ -149,7 +84,7 @@
 		       enum hws_ddr_phy e_phy_type, u32 reg_addr,
 		       u32 data_value);
 int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type e_access, u32 if_id,
-		      enum hws_ddr_freq memory_freq);
+		      enum mv_ddr_freq memory_freq);
 int ddr3_tip_adjust_dqs(u32 dev_num);
 int ddr3_tip_init_controller(u32 dev_num);
 int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u32 reg_addr,
@@ -174,22 +109,12 @@
 			    u32 tx_burst_size, u32 rx_phases,
 			    u32 delay_between_burst, u32 rd_mode, u32 cs_num,
 			    u32 addr_stress_jump, u32 single_pattern);
-int ddr3_tip_set_atr(u32 dev_num, u32 flag_id, u32 value);
 int ddr3_tip_write_mrs_cmd(u32 dev_num, u32 *cs_mask_arr, enum mr_number mr_num, u32 data, u32 mask);
 int ddr3_tip_write_cs_result(u32 dev_num, u32 offset);
-int ddr3_tip_get_first_active_if(u8 dev_num, u32 interface_mask, u32 *if_id);
 int ddr3_tip_reset_fifo_ptr(u32 dev_num);
-int ddr3_tip_read_pup_value(u32 dev_num,
-			    u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
-			    int reg_addr, u32 mask);
-int ddr3_tip_read_adll_value(u32 dev_num,
-			     u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
-			     u32 reg_addr, u32 mask);
-int ddr3_tip_write_adll_value(u32 dev_num,
-			      u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
-			      u32 reg_addr);
-int ddr3_tip_tune_training_params(u32 dev_num,
-				  struct tune_train_params *params);
-struct page_element *mv_ddr_page_tbl_get(void);
+int ddr3_tip_read_pup_value(u32 dev_num, u32 pup_values[], int reg_addr, u32 mask);
+int ddr3_tip_read_adll_value(u32 dev_num, u32 pup_values[], u32 reg_addr, u32 mask);
+int ddr3_tip_write_adll_value(u32 dev_num, u32 pup_values[], u32 reg_addr);
+int ddr3_tip_tune_training_params(u32 dev_num, struct tune_train_params *params);
 
 #endif /* _DDR3_TRAINING_IP_FLOW_H_ */
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_prv_if.h b/drivers/ddr/marvell/a38x/ddr3_training_ip_prv_if.h
index f614d68..2df592e 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip_prv_if.h
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_prv_if.h
@@ -28,15 +28,15 @@
 	u8 dev_num, enum hws_access_type interface_access, u32 if_id,
 	u32 offset, u32 data, u32 mask);
 typedef int (*HWS_TIP_GET_FREQ_CONFIG_INFO)(
-	u8 dev_num, enum hws_ddr_freq freq,
+	u8 dev_num, enum mv_ddr_freq freq,
 	struct hws_tip_freq_config_info *freq_config_info);
 typedef int (*HWS_TIP_GET_DEVICE_INFO)(
 	u8 dev_num, struct ddr3_device_info *info_ptr);
 typedef int (*HWS_GET_CS_CONFIG_FUNC_PTR)(
 	u8 dev_num, u32 cs_mask, struct hws_cs_config_info *cs_info);
 typedef int (*HWS_SET_FREQ_DIVIDER_FUNC_PTR)(
-	u8 dev_num, u32 if_id, enum hws_ddr_freq freq);
-typedef int (*HWS_GET_INIT_FREQ)(u8 dev_num, enum hws_ddr_freq *freq);
+	u8 dev_num, u32 if_id, enum mv_ddr_freq freq);
+typedef int (*HWS_GET_INIT_FREQ)(u8 dev_num, enum mv_ddr_freq *freq);
 typedef int (*HWS_TRAINING_IP_IF_WRITE_FUNC_PTR)(
 	u32 dev_num, enum hws_access_type access_type, u32 dunit_id,
 	u32 reg_addr, u32 data, u32 mask);
@@ -54,7 +54,7 @@
 	u32 dev_num, enum hws_algo_type algo_type);
 typedef int (*HWS_TRAINING_IP_SET_FREQ_FUNC_PTR)(
 	u32 dev_num, enum hws_access_type access_type, u32 if_id,
-	enum hws_ddr_freq frequency);
+	enum mv_ddr_freq frequency);
 typedef int (*HWS_TRAINING_IP_INIT_CONTROLLER_FUNC_PTR)(
 	u32 dev_num, struct init_cntr_param *init_cntr_prm);
 typedef int (*HWS_TRAINING_IP_PBS_RX_FUNC_PTR)(u32 dev_num);
@@ -64,7 +64,7 @@
 typedef int (*HWS_TRAINING_IP_TOPOLOGY_MAP_LOAD_FUNC_PTR)(
 	u32 dev_num, struct mv_ddr_topology_map *tm);
 typedef int (*HWS_TRAINING_IP_STATIC_CONFIG_FUNC_PTR)(
-	u32 dev_num, enum hws_ddr_freq frequency,
+	u32 dev_num, enum mv_ddr_freq frequency,
 	enum hws_static_config_type static_config_type, u32 if_id);
 typedef int (*HWS_TRAINING_IP_EXTERNAL_READ_PTR)(
 	u32 dev_num, u32 if_id, u32 ddr_addr, u32 num_bursts, u32 *data);
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_leveling.c b/drivers/ddr/marvell/a38x/ddr3_training_leveling.c
index 6248ffc..7f7df67 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_leveling.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_leveling.c
@@ -4,6 +4,9 @@
  */
 
 #include "ddr3_init.h"
+#include "mv_ddr_training_db.h"
+#include "ddr_training_ip_db.h"
+#include "mv_ddr_regs.h"
 
 #define WL_ITERATION_NUM	10
 
@@ -24,33 +27,6 @@
 static int ddr3_tip_xsb_compare_test(u32 dev_num, u32 if_id, u32 bus_id,
 				     u32 edge_offset);
 
-u32 ddr3_tip_max_cs_get(u32 dev_num)
-{
-	u32 c_cs, if_id, bus_id;
-	static u32 max_cs;
-	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
-	u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
-
-	if (!max_cs) {
-		CHECK_STATUS(ddr3_tip_get_first_active_if((u8)dev_num,
-							  tm->if_act_mask,
-							  &if_id));
-		for (bus_id = 0; bus_id < octets_per_if_num; bus_id++) {
-			VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);
-			break;
-		}
-
-		for (c_cs = 0; c_cs < NUM_OF_CS; c_cs++) {
-			VALIDATE_ACTIVE(tm->
-					interface_params[if_id].as_bus_params[bus_id].
-					cs_bitmask, c_cs);
-			max_cs++;
-		}
-	}
-
-	return max_cs;
-}
-
 enum {
 	PASS,
 	FAIL
@@ -61,20 +37,20 @@
 int ddr3_tip_dynamic_read_leveling(u32 dev_num, u32 freq)
 {
 	u32 data, mask;
-	u32 max_cs = ddr3_tip_max_cs_get(dev_num);
+	unsigned int max_cs = mv_ddr_cs_num_get();
 	u32 bus_num, if_id, cl_val;
-	enum hws_speed_bin speed_bin_index;
+	enum mv_ddr_speed_bin speed_bin_index;
 	/* save current CS value */
 	u32 cs_enable_reg_val[MAX_INTERFACE_NUM] = { 0 };
 	int is_any_pup_fail = 0;
 	u32 data_read[MAX_INTERFACE_NUM + 1] = { 0 };
-	u8 rl_values[NUM_OF_CS][MAX_BUS_NUM][MAX_INTERFACE_NUM];
+	u8 rl_values[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM];
 	struct pattern_info *pattern_table = ddr3_tip_get_pattern_table();
 	u16 *mask_results_pup_reg_map = ddr3_tip_get_mask_results_pup_reg_map();
 	u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
 	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
 
-	for (effective_cs = 0; effective_cs < NUM_OF_CS; effective_cs++)
+	for (effective_cs = 0; effective_cs < MAX_CS_NUM; effective_cs++)
 		for (bus_num = 0; bus_num < MAX_BUS_NUM; bus_num++)
 			for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++)
 				rl_values[effective_cs][bus_num][if_id] = 0;
@@ -143,8 +119,7 @@
 			VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
 			speed_bin_index =
 				tm->interface_params[if_id].speed_bin_index;
-			cl_val =
-				cas_latency_table[speed_bin_index].cl_val[freq];
+			cl_val = mv_ddr_cl_val_get(speed_bin_index, freq);
 			data = (cl_val << 17) | (0x3 << 25);
 			mask = (0xff << 9) | (0x1f << 17) | (0x3 << 25);
 			CHECK_STATUS(ddr3_tip_if_write
@@ -340,7 +315,7 @@
 int ddr3_tip_legacy_dynamic_write_leveling(u32 dev_num)
 {
 	u32 c_cs, if_id, cs_mask = 0;
-	u32 max_cs = ddr3_tip_max_cs_get(dev_num);
+	unsigned int max_cs = mv_ddr_cs_num_get();
 	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
 
 	/*
@@ -381,7 +356,7 @@
 int ddr3_tip_legacy_dynamic_read_leveling(u32 dev_num)
 {
 	u32 c_cs, if_id, cs_mask = 0;
-	u32 max_cs = ddr3_tip_max_cs_get(dev_num);
+	unsigned int max_cs = mv_ddr_cs_num_get();
 	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
 
 	/*
@@ -426,7 +401,7 @@
 	u32 curr_numb, curr_min_delay;
 	int adll_array[3] = { 0, -0xa, 0x14 };
 	u32 phyreg3_arr[MAX_INTERFACE_NUM][MAX_BUS_NUM];
-	enum hws_speed_bin speed_bin_index;
+	enum mv_ddr_speed_bin speed_bin_index;
 	int is_any_pup_fail = 0;
 	int break_loop = 0;
 	u32 cs_enable_reg_val[MAX_INTERFACE_NUM]; /* save current CS value */
@@ -516,8 +491,7 @@
 			VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
 			speed_bin_index =
 				tm->interface_params[if_id].speed_bin_index;
-			cl_val =
-				cas_latency_table[speed_bin_index].cl_val[freq];
+			cl_val = mv_ddr_cl_val_get(speed_bin_index, freq);
 			data = (cl_val << 17) | (0x3 << 25);
 			mask = (0xff << 9) | (0x1f << 17) | (0x3 << 25);
 			CHECK_STATUS(ddr3_tip_if_write
@@ -839,10 +813,10 @@
 	u32 res_values[MAX_INTERFACE_NUM * MAX_BUS_NUM] = { 0 };
 	u32 test_res = 0;	/* 0 - success for all pup */
 	u32 data_read[MAX_INTERFACE_NUM];
-	u8 wl_values[NUM_OF_CS][MAX_BUS_NUM][MAX_INTERFACE_NUM];
+	u8 wl_values[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM];
 	u16 *mask_results_pup_reg_map = ddr3_tip_get_mask_results_pup_reg_map();
 	u32 cs_mask0[MAX_INTERFACE_NUM] = { 0 };
-	u32 max_cs = ddr3_tip_max_cs_get(dev_num);
+	unsigned int max_cs = mv_ddr_cs_num_get();
 	u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
 	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
 
@@ -1694,9 +1668,11 @@
 	RL_INSIDE,
 	RL_BEHIND
 };
+
+
 int mv_ddr_rl_dqs_burst(u32 dev_num, u32 if_id, u32 freq)
 {
-	enum rl_dqs_burst_state rl_state[NUM_OF_CS][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } };
+	enum rl_dqs_burst_state rl_state[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } };
 	enum hws_ddr_phy subphy_type = DDR_PHY_DATA;
 	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
 	int cl_val = tm->interface_params[0].cas_l;
@@ -1707,17 +1683,18 @@
 	int init_pass_lock_num;
 	int phase_delta;
 	int min_phase, max_phase;
-	u32 max_cs = ddr3_tip_max_cs_get(dev_num);
-	u32 rl_values[NUM_OF_CS][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } };
-	u32 rl_min_values[NUM_OF_CS][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } };
-	u32 rl_max_values[NUM_OF_CS][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } };
-	u32 rl_val, rl_min_val[NUM_OF_CS], rl_max_val[NUM_OF_CS];
+	unsigned int max_cs = mv_ddr_cs_num_get();
+	u32 rl_values[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } };
+	u32 rl_min_values[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } };
+	u32 rl_max_values[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } };
+	u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM];
 	u32 reg_val_low, reg_val_high;
-	u32 reg_val,  reg_mask;
+	u32 reg_val, reg_mask;
 	uintptr_t test_addr = TEST_ADDR;
 
+
 	/* initialization */
-	if (ddr3_if_ecc_enabled()) {
+	if (mv_ddr_is_ecc_ena()) {
 		ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, TRAINING_SW_2_REG,
 				 &reg_val, MASK_ALL_BITS);
 		reg_mask = (TRAINING_ECC_MUX_MASK << TRAINING_ECC_MUX_OFFS) |
@@ -1753,6 +1730,7 @@
 	/* search for dqs edges per subphy */
 	if_id = 0;
 	for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
+
 		pass_lock_num = init_pass_lock_num;
 		ddr3_tip_if_write(0, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_DATA_CTRL_REG,
 				  effective_cs << ODPG_DATA_CS_OFFS,
@@ -1972,6 +1950,7 @@
 			CHECK_STATUS(ddr3_tip_write_additional_odt_setting(dev_num, if_id));
 	}
 
+
 	/* reset read fifo assertion */
 	ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, if_id, SDRAM_CFG_REG,
 			  DATA_PUP_RD_RESET_ENA << DATA_PUP_RD_RESET_OFFS,
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_leveling.h b/drivers/ddr/marvell/a38x/ddr3_training_leveling.h
index 96d945a..6719fb8 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_leveling.h
+++ b/drivers/ddr/marvell/a38x/ddr3_training_leveling.h
@@ -11,6 +11,5 @@
 int ddr3_tip_print_wl_supp_result(u32 dev_num);
 int ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs,
 			  u32 *cs_mask);
-u32 ddr3_tip_max_cs_get(u32 dev_num);
 
 #endif /* _DDR3_TRAINING_LEVELING_H_ */
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_pbs.c b/drivers/ddr/marvell/a38x/ddr3_training_pbs.c
index 0511026..b7dfebd 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_pbs.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_pbs.c
@@ -4,6 +4,9 @@
  */
 
 #include "ddr3_init.h"
+#include "mv_ddr_training_db.h"
+#include "mv_ddr_common.h"
+#include "mv_ddr_regs.h"
 
 #define TYPICAL_PBS_VALUE	12
 
@@ -33,7 +36,7 @@
 int ddr3_tip_pbs(u32 dev_num, enum pbs_dir pbs_mode)
 {
 	u32 res0[MAX_INTERFACE_NUM];
-	int adll_tap = MEGA / freq_val[medium_freq] / 64;
+	int adll_tap = MEGA / mv_ddr_freq_get(medium_freq) / 64;
 	int pad_num = 0;
 	enum hws_search_dir search_dir =
 		(pbs_mode == PBS_RX_MODE) ? HWS_HIGH2LOW : HWS_LOW2HIGH;
@@ -921,7 +924,7 @@
 int ddr3_tip_print_all_pbs_result(u32 dev_num)
 {
 	u32 curr_cs;
-	u32 max_cs = ddr3_tip_max_cs_get(dev_num);
+	unsigned int max_cs = mv_ddr_cs_num_get();
 
 	for (curr_cs = 0; curr_cs < max_cs; curr_cs++) {
 		ddr3_tip_print_pbs_result(dev_num, curr_cs, PBS_RX_MODE);
diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h
index 8122249..e6fe8a0 100644
--- a/drivers/ddr/marvell/a38x/ddr_topology_def.h
+++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h
@@ -7,16 +7,13 @@
 #define _DDR_TOPOLOGY_DEF_H
 
 #include "ddr3_training_ip_def.h"
-#include "ddr3_topology_def.h"
-
-#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
-#include "mv_ddr_plat.h"
-#endif
-
 #include "mv_ddr_topology.h"
 #include "mv_ddr_spd.h"
 #include "ddr3_logging_def.h"
 
+#define MV_DDR_MAX_BUS_NUM	9
+#define MV_DDR_MAX_IFACE_NUM	1
+
 struct bus_params {
 	/* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */
 	u8 cs_bitmask;
@@ -36,10 +33,10 @@
 
 struct if_params {
 	/* bus configuration */
-	struct bus_params as_bus_params[MAX_BUS_NUM];
+	struct bus_params as_bus_params[MV_DDR_MAX_BUS_NUM];
 
 	/* Speed Bin Table */
-	enum hws_speed_bin speed_bin_index;
+	enum mv_ddr_speed_bin speed_bin_index;
 
 	/* sdram device width */
 	enum mv_ddr_dev_width bus_width;
@@ -48,7 +45,7 @@
 	enum mv_ddr_die_capacity memory_size;
 
 	/* The DDR frequency for each interfaces */
-	enum hws_ddr_freq memory_freq;
+	enum mv_ddr_freq memory_freq;
 
 	/*
 	 * delay CAS Write Latency
@@ -69,6 +66,37 @@
 	enum mv_ddr_timing timing;
 };
 
+/* memory electrical configuration */
+struct mv_ddr_mem_edata {
+	enum mv_ddr_rtt_nom_park_evalue rtt_nom;
+	enum mv_ddr_rtt_nom_park_evalue rtt_park[MAX_CS_NUM];
+	enum mv_ddr_rtt_wr_evalue rtt_wr[MAX_CS_NUM];
+	enum mv_ddr_dic_evalue dic;
+};
+
+/* phy electrical configuration */
+struct mv_ddr_phy_edata {
+	enum mv_ddr_ohm_evalue drv_data_p;
+	enum mv_ddr_ohm_evalue drv_data_n;
+	enum mv_ddr_ohm_evalue drv_ctrl_p;
+	enum mv_ddr_ohm_evalue drv_ctrl_n;
+	enum mv_ddr_ohm_evalue odt_p[MAX_CS_NUM];
+	enum mv_ddr_ohm_evalue odt_n[MAX_CS_NUM];
+};
+
+/* mac electrical configuration */
+struct mv_ddr_mac_edata {
+	enum mv_ddr_odt_cfg_evalue odt_cfg_pat;
+	enum mv_ddr_odt_cfg_evalue odt_cfg_wr;
+	enum mv_ddr_odt_cfg_evalue odt_cfg_rd;
+};
+
+struct mv_ddr_edata {
+	struct mv_ddr_mem_edata mem_edata;
+	struct mv_ddr_phy_edata phy_edata;
+	struct mv_ddr_mac_edata mac_edata;
+};
+
 struct mv_ddr_topology_map {
 	/* debug level configuration */
 	enum mv_ddr_debug_level debug_level;
@@ -77,7 +105,7 @@
 	u8 if_act_mask;
 
 	/* Controller configuration per interface */
-	struct if_params interface_params[MAX_INTERFACE_NUM];
+	struct if_params interface_params[MV_DDR_MAX_IFACE_NUM];
 
 	/* Bit mask for active buses */
 	u16 bus_act_mask;
@@ -90,8 +118,67 @@
 
 	/* timing parameters */
 	unsigned int timing_data[MV_DDR_TDATA_LAST];
+
+	/* electrical configuration */
+	struct mv_ddr_edata edata;
+
+	/* electrical parameters */
+	unsigned int electrical_data[MV_DDR_EDATA_LAST];
+};
+
+enum mv_ddr_iface_mode {
+	MV_DDR_RAR_ENA,
+	MV_DDR_RAR_DIS,
 };
 
+enum mv_ddr_iface_state {
+	MV_DDR_IFACE_NRDY,	/* not ready */
+	MV_DDR_IFACE_INIT,	/* init'd */
+	MV_DDR_IFACE_RDY,	/* ready */
+	MV_DDR_IFACE_DNE	/* does not exist */
+};
+
+enum mv_ddr_validation {
+	MV_DDR_VAL_DIS,
+	MV_DDR_VAL_RX,
+	MV_DDR_VAL_TX,
+	MV_DDR_VAL_RX_TX
+};
+
+struct mv_ddr_iface {
+	/* base addr of ap ddr interface belongs to */
+	unsigned int ap_base;
+
+	/* ddr interface id */
+	unsigned int id;
+
+	/* ddr interface state */
+	enum mv_ddr_iface_state state;
+
+	/* ddr interface mode (rar enabled/disabled) */
+	enum mv_ddr_iface_mode iface_mode;
+
+	/* ddr interface base address */
+	unsigned long long iface_base_addr;
+
+	/* ddr interface size - ddr flow will update this parameter */
+	unsigned long long iface_byte_size;
+
+	/* ddr i2c spd data address */
+	unsigned int spd_data_addr;
+
+	/* ddr i2c spd page 0 select address */
+	unsigned int spd_page_sel_addr;
+
+	/* ddr interface validation mode */
+	enum mv_ddr_validation validation;
+
+	/* ddr interface topology map */
+	struct mv_ddr_topology_map tm;
+};
+
+struct mv_ddr_iface *mv_ddr_iface_get(void);
+
 /* DDR3 training global configuration parameters */
 struct tune_train_params {
 	u32 ck_delay;
diff --git a/drivers/ddr/marvell/a38x/ddr_training_ip_db.h b/drivers/ddr/marvell/a38x/ddr_training_ip_db.h
index e7de5ae..f1b4d8e 100644
--- a/drivers/ddr/marvell/a38x/ddr_training_ip_db.h
+++ b/drivers/ddr/marvell/a38x/ddr_training_ip_db.h
@@ -6,10 +6,8 @@
 #ifndef _DDR_TRAINING_IP_DB_H_
 #define _DDR_TRAINING_IP_DB_H_
 
-#include "ddr_topology_def.h"
 #include "ddr3_training_ip_db.h"
 
-u32 speed_bin_table(u8 index, enum speed_bin_table_elements element);
 u32 pattern_table_get_word(u32 dev_num, enum hws_pattern type, u8 index);
 
 #endif /* _DDR3_TRAINING_IP_DB_H_ */
diff --git a/drivers/ddr/marvell/a38x/dram_if.h b/drivers/ddr/marvell/a38x/dram_if.h
new file mode 100644
index 0000000..4d08464
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/dram_if.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Marvell International Ltd.
+ */
+
+#ifndef _DRAM_IF_H_
+#define _DRAM_IF_H_
+
+/* TODO: update atf to this new prototype */
+int dram_init(void);
+void dram_mmap_config(void);
+unsigned long long dram_iface_mem_sz_get(void);
+#endif /* _DRAM_IF_H_ */
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_build_message.c b/drivers/ddr/marvell/a38x/mv_ddr_build_message.c
index 2b49b77..cc6234f 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_build_message.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_build_message.c
@@ -1,3 +1,3 @@
 // SPDX-License-Identifier: GPL-2.0
 const char mv_ddr_build_message[] = "";
-const char mv_ddr_version_string[] = "mv_ddr: mv_ddr-armada-17.10.4";
+const char mv_ddr_version_string[] = "mv_ddr: mv_ddr-armada-18.09.2";
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_common.h b/drivers/ddr/marvell/a38x/mv_ddr_common.h
index c71ff44..321a390 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_common.h
+++ b/drivers/ddr/marvell/a38x/mv_ddr_common.h
@@ -9,10 +9,44 @@
 extern const char mv_ddr_build_message[];
 extern const char mv_ddr_version_string[];
 
-#define MV_DDR_NUM_BITS_IN_BYTE	8
-#define MV_DDR_MEGA_BITS	(1024 * 1024)
+#define _1K	0x00000400
+#define _4K	0x00001000
+#define _8K	0x00002000
+#define _16K	0x00004000
+#define _32K	0x00008000
+#define _64K	0x00010000
+#define _128K	0x00020000
+#define _256K	0x00040000
+#define _512K	0x00080000
+
+#define _1M	0x00100000
+#define _2M	0x00200000
+#define _4M	0x00400000
+#define _8M	0x00800000
+#define _16M	0x01000000
+#define _32M	0x02000000
+#define _64M	0x04000000
+#define _128M	0x08000000
+#define _256M	0x10000000
+#define _512M	0x20000000
+
+#define _1G	0x40000000
+#define _2G	0x80000000
+#define _4G	0x100000000
+#define _8G	0x200000000
+#define _16G	0x400000000
+#define _32G	0x800000000
+#define _64G	0x1000000000
+#define _128G	0x2000000000
+
+#define MEGA			1000000
+#define MV_DDR_MEGABYTE		(1024 * 1024)
 #define MV_DDR_32_BITS_MASK	0xffffffff
 
+#define GET_MAX_VALUE(x, y) \
+	(((x) > (y)) ? (x) : (y))
+
+void mv_ddr_ver_print(void);
 unsigned int ceil_div(unsigned int x, unsigned int y);
 unsigned int time_to_nclk(unsigned int t, unsigned int tclk);
 int round_div(unsigned int dividend, unsigned int divisor, unsigned int *quotient);
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.c b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
index 2f318cb..cc7942d 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
@@ -4,7 +4,8 @@
  */
 
 #include "ddr3_init.h"
-
+#include "mv_ddr_training_db.h"
+#include "mv_ddr_regs.h"
 #include "mv_ddr_sys_env_lib.h"
 
 #define DDR_INTERFACES_NUM		1
@@ -58,42 +59,42 @@
 	return &ddr3_dlb_config_table[0];
 }
 
-static u8 a38x_bw_per_freq[DDR_FREQ_LAST] = {
-	0x3,			/* DDR_FREQ_100 */
-	0x4,			/* DDR_FREQ_400 */
-	0x4,			/* DDR_FREQ_533 */
-	0x5,			/* DDR_FREQ_667 */
-	0x5,			/* DDR_FREQ_800 */
-	0x5,			/* DDR_FREQ_933 */
-	0x5,			/* DDR_FREQ_1066 */
-	0x3,			/* DDR_FREQ_311 */
-	0x3,			/* DDR_FREQ_333 */
-	0x4,			/* DDR_FREQ_467 */
-	0x5,			/* DDR_FREQ_850 */
-	0x5,			/* DDR_FREQ_600 */
-	0x3,			/* DDR_FREQ_300 */
-	0x5,			/* DDR_FREQ_900 */
-	0x3,			/* DDR_FREQ_360 */
-	0x5			/* DDR_FREQ_1000 */
+static u8 a38x_bw_per_freq[MV_DDR_FREQ_LAST] = {
+	0x3,			/* MV_DDR_FREQ_100 */
+	0x4,			/* MV_DDR_FREQ_400 */
+	0x4,			/* MV_DDR_FREQ_533 */
+	0x5,			/* MV_DDR_FREQ_667 */
+	0x5,			/* MV_DDR_FREQ_800 */
+	0x5,			/* MV_DDR_FREQ_933 */
+	0x5,			/* MV_DDR_FREQ_1066 */
+	0x3,			/* MV_DDR_FREQ_311 */
+	0x3,			/* MV_DDR_FREQ_333 */
+	0x4,			/* MV_DDR_FREQ_467 */
+	0x5,			/* MV_DDR_FREQ_850 */
+	0x5,			/* MV_DDR_FREQ_600 */
+	0x3,			/* MV_DDR_FREQ_300 */
+	0x5,			/* MV_DDR_FREQ_900 */
+	0x3,			/* MV_DDR_FREQ_360 */
+	0x5			/* MV_DDR_FREQ_1000 */
 };
 
-static u8 a38x_rate_per_freq[DDR_FREQ_LAST] = {
-	0x1,			/* DDR_FREQ_100 */
-	0x2,			/* DDR_FREQ_400 */
-	0x2,			/* DDR_FREQ_533 */
-	0x2,			/* DDR_FREQ_667 */
-	0x2,			/* DDR_FREQ_800 */
-	0x3,			/* DDR_FREQ_933 */
-	0x3,			/* DDR_FREQ_1066 */
-	0x1,			/* DDR_FREQ_311 */
-	0x1,			/* DDR_FREQ_333 */
-	0x2,			/* DDR_FREQ_467 */
-	0x2,			/* DDR_FREQ_850 */
-	0x2,			/* DDR_FREQ_600 */
-	0x1,			/* DDR_FREQ_300 */
-	0x2,			/* DDR_FREQ_900 */
-	0x1,			/* DDR_FREQ_360 */
-	0x2			/* DDR_FREQ_1000 */
+static u8 a38x_rate_per_freq[MV_DDR_FREQ_LAST] = {
+	0x1,			/* MV_DDR_FREQ_100 */
+	0x2,			/* MV_DDR_FREQ_400 */
+	0x2,			/* MV_DDR_FREQ_533 */
+	0x2,			/* MV_DDR_FREQ_667 */
+	0x2,			/* MV_DDR_FREQ_800 */
+	0x3,			/* MV_DDR_FREQ_933 */
+	0x3,			/* MV_DDR_FREQ_1066 */
+	0x1,			/* MV_DDR_FREQ_311 */
+	0x1,			/* MV_DDR_FREQ_333 */
+	0x2,			/* MV_DDR_FREQ_467 */
+	0x2,			/* MV_DDR_FREQ_850 */
+	0x2,			/* MV_DDR_FREQ_600 */
+	0x1,			/* MV_DDR_FREQ_300 */
+	0x2,			/* MV_DDR_FREQ_900 */
+	0x1,			/* MV_DDR_FREQ_360 */
+	0x2			/* MV_DDR_FREQ_1000 */
 };
 
 static u16 a38x_vco_freq_per_sar_ref_clk_25_mhz[] = {
@@ -177,10 +178,11 @@
 
 void mv_ddr_mem_scrubbing(void)
 {
+	ddr3_new_tip_ecc_scrub();
 }
 
 static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id,
-				     enum hws_ddr_freq freq);
+				     enum mv_ddr_freq freq);
 
 /*
  * Read temperature TJ value
@@ -219,7 +221,7 @@
  * Notes:
  * Returns:  MV_OK if success, other error code if fail.
  */
-static int ddr3_tip_a38x_get_freq_config(u8 dev_num, enum hws_ddr_freq freq,
+static int ddr3_tip_a38x_get_freq_config(u8 dev_num, enum mv_ddr_freq freq,
 				  struct hws_tip_freq_config_info
 				  *freq_config_info)
 {
@@ -377,13 +379,13 @@
 
 static u8 ddr3_tip_clock_mode(u32 frequency)
 {
-	if ((frequency == DDR_FREQ_LOW_FREQ) || (freq_val[frequency] <= 400))
+	if ((frequency == MV_DDR_FREQ_LOW_FREQ) || (mv_ddr_freq_get(frequency) <= 400))
 		return 1;
 
 	return 2;
 }
 
-static int mv_ddr_sar_freq_get(int dev_num, enum hws_ddr_freq *freq)
+static int mv_ddr_sar_freq_get(int dev_num, enum mv_ddr_freq *freq)
 {
 	u32 reg, ref_clk_satr;
 
@@ -402,7 +404,7 @@
 					      reg));
 			/* fallthrough */
 		case 0x0:
-			*freq = DDR_FREQ_333;
+			*freq = MV_DDR_FREQ_333;
 			break;
 		case 0x3:
 			DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR,
@@ -410,7 +412,7 @@
 					      reg));
 			/* fallthrough */
 		case 0x2:
-			*freq = DDR_FREQ_400;
+			*freq = MV_DDR_FREQ_400;
 			break;
 		case 0xd:
 			DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR,
@@ -418,10 +420,10 @@
 					      reg));
 			/* fallthrough */
 		case 0x4:
-			*freq = DDR_FREQ_533;
+			*freq = MV_DDR_FREQ_533;
 			break;
 		case 0x6:
-			*freq = DDR_FREQ_600;
+			*freq = MV_DDR_FREQ_600;
 			break;
 		case 0x11:
 		case 0x14:
@@ -430,7 +432,7 @@
 					      reg));
 			/* fallthrough */
 		case 0x8:
-			*freq = DDR_FREQ_667;
+			*freq = MV_DDR_FREQ_667;
 			break;
 		case 0x15:
 		case 0x1b:
@@ -439,16 +441,16 @@
 					      reg));
 			/* fallthrough */
 		case 0xc:
-			*freq = DDR_FREQ_800;
+			*freq = MV_DDR_FREQ_800;
 			break;
 		case 0x10:
-			*freq = DDR_FREQ_933;
+			*freq = MV_DDR_FREQ_933;
 			break;
 		case 0x12:
-			*freq = DDR_FREQ_900;
+			*freq = MV_DDR_FREQ_900;
 			break;
 		case 0x13:
-			*freq = DDR_FREQ_933;
+			*freq = MV_DDR_FREQ_933;
 			break;
 		default:
 			*freq = 0;
@@ -457,16 +459,16 @@
 	} else { /* REFCLK 40MHz case */
 		switch (reg) {
 		case 0x3:
-			*freq = DDR_FREQ_400;
+			*freq = MV_DDR_FREQ_400;
 			break;
 		case 0x5:
-			*freq = DDR_FREQ_533;
+			*freq = MV_DDR_FREQ_533;
 			break;
 		case 0xb:
-			*freq = DDR_FREQ_800;
+			*freq = MV_DDR_FREQ_800;
 			break;
 		case 0x1e:
-			*freq = DDR_FREQ_900;
+			*freq = MV_DDR_FREQ_900;
 			break;
 		default:
 			*freq = 0;
@@ -477,7 +479,7 @@
 	return MV_OK;
 }
 
-static int ddr3_tip_a38x_get_medium_freq(int dev_num, enum hws_ddr_freq *freq)
+static int ddr3_tip_a38x_get_medium_freq(int dev_num, enum mv_ddr_freq *freq)
 {
 	u32 reg, ref_clk_satr;
 
@@ -493,37 +495,37 @@
 		case 0x0:
 		case 0x1:
 			/* Medium is same as TF to run PBS in this freq */
-			*freq = DDR_FREQ_333;
+			*freq = MV_DDR_FREQ_333;
 			break;
 		case 0x2:
 		case 0x3:
 			/* Medium is same as TF to run PBS in this freq */
-			*freq = DDR_FREQ_400;
+			*freq = MV_DDR_FREQ_400;
 			break;
 		case 0x4:
 		case 0xd:
 			/* Medium is same as TF to run PBS in this freq */
-			*freq = DDR_FREQ_533;
+			*freq = MV_DDR_FREQ_533;
 			break;
 		case 0x8:
 		case 0x10:
 		case 0x11:
 		case 0x14:
-			*freq = DDR_FREQ_333;
+			*freq = MV_DDR_FREQ_333;
 			break;
 		case 0xc:
 		case 0x15:
 		case 0x1b:
-			*freq = DDR_FREQ_400;
+			*freq = MV_DDR_FREQ_400;
 			break;
 		case 0x6:
-			*freq = DDR_FREQ_300;
+			*freq = MV_DDR_FREQ_300;
 			break;
 		case 0x12:
-			*freq = DDR_FREQ_360;
+			*freq = MV_DDR_FREQ_360;
 			break;
 		case 0x13:
-			*freq = DDR_FREQ_400;
+			*freq = MV_DDR_FREQ_400;
 			break;
 		default:
 			*freq = 0;
@@ -533,17 +535,17 @@
 		switch (reg) {
 		case 0x3:
 			/* Medium is same as TF to run PBS in this freq */
-			*freq = DDR_FREQ_400;
+			*freq = MV_DDR_FREQ_400;
 			break;
 		case 0x5:
 			/* Medium is same as TF to run PBS in this freq */
-			*freq = DDR_FREQ_533;
+			*freq = MV_DDR_FREQ_533;
 			break;
 		case 0xb:
-			*freq = DDR_FREQ_400;
+			*freq = MV_DDR_FREQ_400;
 			break;
 		case 0x1e:
-			*freq = DDR_FREQ_360;
+			*freq = MV_DDR_FREQ_360;
 			break;
 		default:
 			*freq = 0;
@@ -682,7 +684,7 @@
 static int mv_ddr_training_mask_set(void)
 {
 	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
-	enum hws_ddr_freq ddr_freq = tm->interface_params[0].memory_freq;
+	enum mv_ddr_freq ddr_freq = tm->interface_params[0].memory_freq;
 
 	mask_tune_func = (SET_LOW_FREQ_MASK_BIT |
 			  LOAD_PATTERN_MASK_BIT |
@@ -699,7 +701,7 @@
 			  CENTRALIZATION_TX_MASK_BIT);
 	rl_mid_freq_wa = 1;
 
-	if ((ddr_freq == DDR_FREQ_333) || (ddr_freq == DDR_FREQ_400)) {
+	if ((ddr_freq == MV_DDR_FREQ_333) || (ddr_freq == MV_DDR_FREQ_400)) {
 		mask_tune_func = (WRITE_LEVELING_MASK_BIT |
 				  LOAD_PATTERN_2_MASK_BIT |
 				  WRITE_LEVELING_SUPP_MASK_BIT |
@@ -712,7 +714,7 @@
 	}
 
 	/* Supplementary not supported for ECC modes */
-	if (1 == ddr3_if_ecc_enabled()) {
+	if (mv_ddr_is_ecc_ena()) {
 		mask_tune_func &= ~WRITE_LEVELING_SUPP_TF_MASK_BIT;
 		mask_tune_func &= ~WRITE_LEVELING_SUPP_MASK_BIT;
 		mask_tune_func &= ~PBS_TX_MASK_BIT;
@@ -734,11 +736,12 @@
 }
 
 static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id,
-				     enum hws_ddr_freq frequency)
+				     enum mv_ddr_freq frequency)
 {
 	u32 divider = 0;
 	u32 sar_val, ref_clk_satr;
 	u32 async_val;
+	u32 freq = mv_ddr_freq_get(frequency);
 
 	if (if_id != 0) {
 		DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR,
@@ -755,11 +758,11 @@
 	ref_clk_satr = reg_read(DEVICE_SAMPLE_AT_RESET2_REG);
 	if (((ref_clk_satr >> DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_OFFSET) & 0x1) ==
 	    DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_25MHZ)
-		divider = a38x_vco_freq_per_sar_ref_clk_25_mhz[sar_val] / freq_val[frequency];
+		divider = a38x_vco_freq_per_sar_ref_clk_25_mhz[sar_val] / freq;
 	else
-		divider = a38x_vco_freq_per_sar_ref_clk_40_mhz[sar_val] / freq_val[frequency];
+		divider = a38x_vco_freq_per_sar_ref_clk_40_mhz[sar_val] / freq;
 
-	if ((async_mode_at_tf == 1) && (freq_val[frequency] > 400)) {
+	if ((async_mode_at_tf == 1) && (freq > 400)) {
 		/* Set async mode */
 		dunit_write(0x20220, 0x1000, 0x1000);
 		dunit_write(0xe42f4, 0x200, 0x200);
@@ -769,42 +772,38 @@
 
 		/* Set KNL values */
 		switch (frequency) {
-#ifdef CONFIG_DDR3
-		case DDR_FREQ_467:
+		case MV_DDR_FREQ_467:
 			async_val = 0x806f012;
 			break;
-		case DDR_FREQ_533:
+		case MV_DDR_FREQ_533:
 			async_val = 0x807f012;
 			break;
-		case DDR_FREQ_600:
+		case MV_DDR_FREQ_600:
 			async_val = 0x805f00a;
 			break;
-#endif
-		case DDR_FREQ_667:
+		case MV_DDR_FREQ_667:
 			async_val = 0x809f012;
 			break;
-		case DDR_FREQ_800:
+		case MV_DDR_FREQ_800:
 			async_val = 0x807f00a;
 			break;
-#ifdef CONFIG_DDR3
-		case DDR_FREQ_850:
+		case MV_DDR_FREQ_850:
 			async_val = 0x80cb012;
 			break;
-#endif
-		case DDR_FREQ_900:
+		case MV_DDR_FREQ_900:
 			async_val = 0x80d7012;
 			break;
-		case DDR_FREQ_933:
+		case MV_DDR_FREQ_933:
 			async_val = 0x80df012;
 			break;
-		case DDR_FREQ_1000:
+		case MV_DDR_FREQ_1000:
 			async_val = 0x80ef012;
 			break;
-		case DDR_FREQ_1066:
+		case MV_DDR_FREQ_1066:
 			async_val = 0x80ff012;
 			break;
 		default:
-			/* set DDR_FREQ_667 as default */
+			/* set MV_DDR_FREQ_667 as default */
 			async_val = 0x809f012;
 		}
 		dunit_write(0xe42f0, 0xffffffff, async_val);
@@ -890,7 +889,7 @@
 
 	mv_ddr_sw_db_init(0, 0);
 
-	if (tm->interface_params[0].memory_freq != DDR_FREQ_SAR)
+	if (tm->interface_params[0].memory_freq != MV_DDR_FREQ_SAR)
 		async_mode_at_tf = 1;
 
 	return MV_OK;
@@ -934,7 +933,7 @@
 
 u32 mv_ddr_init_freq_get(void)
 {
-	enum hws_ddr_freq freq;
+	enum mv_ddr_freq freq;
 
 	mv_ddr_sar_freq_get(0, &freq);
 
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.h b/drivers/ddr/marvell/a38x/mv_ddr_plat.h
index 9c5fdec..281d4c2 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_plat.h
+++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.h
@@ -6,6 +6,7 @@
 #ifndef _MV_DDR_PLAT_H
 #define _MV_DDR_PLAT_H
 
+#define MAX_DEVICE_NUM			1
 #define MAX_INTERFACE_NUM		1
 #define MAX_BUS_NUM			5
 #define DDR_IF_CTRL_SUBPHYS_NUM		3
@@ -121,6 +122,9 @@
 #define DLB_QUEUE_MAP_REG		0x1784
 #define DLB_SPLIT_REG			0x1788
 
+/* ck swap control subphy number */
+#define CK_SWAP_CTRL_PHY_NUM	2
+
 /* Subphy result control per byte registers */
 #define RESULT_CONTROL_BYTE_PUP_0_REG		0x1830
 #define RESULT_CONTROL_BYTE_PUP_1_REG		0x1834
@@ -221,7 +225,7 @@
 int mv_ddr_pre_training_soc_config(const char *ddr_type);
 int mv_ddr_post_training_soc_config(const char *ddr_type);
 void mv_ddr_mem_scrubbing(void);
-
+u32 mv_ddr_init_freq_get(void);
 void mv_ddr_odpg_enable(void);
 void mv_ddr_odpg_disable(void);
 void mv_ddr_odpg_done_clr(void);
@@ -233,4 +237,5 @@
 int mv_ddr_post_training_fixup(void);
 int mv_ddr_manual_cal_do(void);
 int ddr3_calc_mem_cs_size(u32 cs, uint64_t *cs_size);
+
 #endif /* _MV_DDR_PLAT_H */
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_regs.h b/drivers/ddr/marvell/a38x/mv_ddr_regs.h
index ceda204..cf2a6c9 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_regs.h
+++ b/drivers/ddr/marvell/a38x/mv_ddr_regs.h
@@ -134,6 +134,7 @@
 #define SDRAM_OP_CMD_CS_BASE			8
 #define SDRAM_OP_CMD_CS_OFFS(cs)		(SDRAM_OP_CMD_CS_BASE + (cs))
 #define SDRAM_OP_CMD_CS_MASK			0x1
+#define SDRAM_OP_CMD_ALL_CS_MASK		0xf
 enum {
 	CMD_NORMAL,
 	CMD_PRECHARGE,
@@ -270,6 +271,10 @@
 #define ZQC_CFG_REG				0x15e4
 #define DRAM_PHY_CFG_REG			0x15ec
 #define ODPG_CTRL_CTRL_REG			0x1600
+#define ODPG_CTRL_AUTO_REFRESH_OFFS		21
+#define ODPG_CTRL_AUTO_REFRESH_MASK		0x1
+#define ODPG_CTRL_AUTO_REFRESH_DIS		1
+#define ODPG_CTRL_AUTO_REFRESH_ENA		0
 
 #define ODPG_DATA_CTRL_REG			0x1630
 #define ODPG_WRBUF_WR_CTRL_OFFS			0
@@ -406,6 +411,20 @@
 #define CRX_PHY_REG(cs)				(CRX_PHY_BASE + (cs) * 0x4)
 
 #define PHY_CTRL_PHY_REG			0x90
+#define INV_PAD0_OFFS				2
+#define INV_PAD1_OFFS				3
+#define INV_PAD2_OFFS				4
+#define INV_PAD3_OFFS				5
+#define INV_PAD4_OFFS				6
+#define INV_PAD5_OFFS				7
+#define INV_PAD6_OFFS				8
+#define INV_PAD7_OFFS				9
+#define INV_PAD8_OFFS				10
+#define INV_PAD9_OFFS				11
+#define INV_PAD10_OFFS				12
+#define INV_PAD_MASK				0x1
+#define INVERT_PAD				1
+
 #define ADLL_CFG0_PHY_REG			0x92
 #define ADLL_CFG1_PHY_REG			0x93
 #define ADLL_CFG2_PHY_REG			0x94
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_spd.c b/drivers/ddr/marvell/a38x/mv_ddr_spd.c
index e9e7f18..04dbfe9 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_spd.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_spd.c
@@ -81,9 +81,6 @@
 	timing_data[MV_DDR_TWR_MIN] = (spd_data->byte_fields.byte_42 +
 		(spd_data->byte_fields.byte_41.bit_fields.t_wr_min_msn << MV_DDR_SPD_MSB_OFFS)) *
 		MV_DDR_SPD_DATA_MTB;
-	/* FIXME: wa: set twr to a default value, if it's unset on spd */
-	if (timing_data[MV_DDR_TWR_MIN] == 0)
-		timing_data[MV_DDR_TWR_MIN] = 15000;
 
 	/* t rcd min, ps */
 	calc_val = spd_data->byte_fields.byte_25 * MV_DDR_SPD_DATA_MTB +
@@ -127,6 +124,13 @@
 		return 1;
 	timing_data[MV_DDR_TRRD_L_MIN] = calc_val;
 
+	/* t ccd l min, ps */
+	calc_val = spd_data->byte_fields.byte_40 * MV_DDR_SPD_DATA_MTB +
+		(signed char)spd_data->byte_fields.byte_117 * MV_DDR_SPD_DATA_FTB;
+	if (calc_val < 0)
+		return 1;
+	timing_data[MV_DDR_TCCD_L_MIN] = calc_val;
+
 	/* t faw min, ps */
 	timing_data[MV_DDR_TFAW_MIN] = (spd_data->byte_fields.byte_37 +
 		(spd_data->byte_fields.byte_36.bit_fields.t_faw_min_msn << MV_DDR_SPD_MSB_OFFS)) *
@@ -136,17 +140,11 @@
 	timing_data[MV_DDR_TWTR_S_MIN] = (spd_data->byte_fields.byte_44 +
 		(spd_data->byte_fields.byte_43.bit_fields.t_wtr_s_min_msn << MV_DDR_SPD_MSB_OFFS)) *
 		MV_DDR_SPD_DATA_MTB;
-	/* FIXME: wa: set twtr_s to a default value, if it's unset on spd */
-	if (timing_data[MV_DDR_TWTR_S_MIN] == 0)
-		timing_data[MV_DDR_TWTR_S_MIN] = 2500;
 
 	/* t wtr l min, ps */
 	timing_data[MV_DDR_TWTR_L_MIN] = (spd_data->byte_fields.byte_45 +
 		(spd_data->byte_fields.byte_43.bit_fields.t_wtr_l_min_msn << MV_DDR_SPD_MSB_OFFS)) *
 		MV_DDR_SPD_DATA_MTB;
-	/* FIXME: wa: set twtr_l to a default value, if it's unset on spd */
-	if (timing_data[MV_DDR_TWTR_L_MIN] == 0)
-		timing_data[MV_DDR_TWTR_L_MIN] = 7500;
 
 	return 0;
 }
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
index f56ce06..ef3b658 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
@@ -2,15 +2,16 @@
 /*
  * Copyright (C) Marvell International Ltd. and its affiliates
  */
+#include "ddr_ml_wrapper.h"
+#include "mv_ddr_plat.h"
 
 #include "mv_ddr_topology.h"
 #include "mv_ddr_common.h"
 #include "mv_ddr_spd.h"
-#include "ddr3_init.h"
 #include "ddr_topology_def.h"
 #include "ddr3_training_ip_db.h"
 #include "ddr3_training_ip.h"
-
+#include "mv_ddr_training_db.h"
 
 unsigned int mv_ddr_cl_calc(unsigned int taa_min, unsigned int tclk)
 {
@@ -32,54 +33,57 @@
 		cwl = 11;
 	else if (tclk >= 833)
 		cwl = 12;
+	else if (tclk >= 750)
+		cwl = 14;
+	else if (tclk >= 625)
+		cwl = 16;
 	else
 		cwl = 0;
 
 	return cwl;
 }
 
-struct mv_ddr_topology_map *mv_ddr_topology_map_update(void)
+int mv_ddr_topology_map_update(void)
 {
 	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
+	struct if_params *iface_params = &(tm->interface_params[0]);
 	unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
-	enum hws_speed_bin speed_bin_index;
-	enum hws_ddr_freq freq = DDR_FREQ_LAST;
+	enum mv_ddr_speed_bin speed_bin_index;
+	enum mv_ddr_freq freq = MV_DDR_FREQ_LAST;
 	unsigned int tclk;
 	unsigned char val = 0;
 	int i;
 
-
-	if (tm->interface_params[0].memory_freq == DDR_FREQ_SAR)
-		tm->interface_params[0].memory_freq = mv_ddr_init_freq_get();
+	if (iface_params->memory_freq == MV_DDR_FREQ_SAR)
+		iface_params->memory_freq = mv_ddr_init_freq_get();
 
 	if (tm->cfg_src == MV_DDR_CFG_SPD) {
 		/* check dram device type */
 		val = mv_ddr_spd_dev_type_get(&tm->spd_data);
 		if (val != MV_DDR_SPD_DEV_TYPE_DDR4) {
 			printf("mv_ddr: unsupported dram device type found\n");
-			return NULL;
+			return -1;
 		}
 
 		/* update topology map with timing data */
 		if (mv_ddr_spd_timing_calc(&tm->spd_data, tm->timing_data) > 0) {
 			printf("mv_ddr: negative timing data found\n");
-			return NULL;
+			return -1;
 		}
 
 		/* update device width in topology map */
-		tm->interface_params[0].bus_width = mv_ddr_spd_dev_width_get(&tm->spd_data);
+		iface_params->bus_width = mv_ddr_spd_dev_width_get(&tm->spd_data);
 
 		/* update die capacity in topology map */
-		tm->interface_params[0].memory_size = mv_ddr_spd_die_capacity_get(&tm->spd_data);
+		iface_params->memory_size = mv_ddr_spd_die_capacity_get(&tm->spd_data);
 
 		/* update bus bit mask in topology map */
 		tm->bus_act_mask = mv_ddr_bus_bit_mask_get();
 
 		/* update cs bit mask in topology map */
 		val = mv_ddr_spd_cs_bit_mask_get(&tm->spd_data);
-		for (i = 0; i < octets_per_if_num; i++) {
-				tm->interface_params[0].as_bus_params[i].cs_bitmask = val;
-		}
+		for (i = 0; i < octets_per_if_num; i++)
+			iface_params->as_bus_params[i].cs_bitmask = val;
 
 		/* check dram module type */
 		val = mv_ddr_spd_module_type_get(&tm->spd_data);
@@ -93,48 +97,44 @@
 			break;
 		default:
 			printf("mv_ddr: unsupported dram module type found\n");
-			return NULL;
+			return -1;
 		}
 
 		/* update mirror bit mask in topology map */
 		val = mv_ddr_spd_mem_mirror_get(&tm->spd_data);
-		for (i = 0; i < octets_per_if_num; i++) {
-				tm->interface_params[0].as_bus_params[i].mirror_enable_bitmask = val << 1;
-		}
+		for (i = 0; i < octets_per_if_num; i++)
+			iface_params->as_bus_params[i].mirror_enable_bitmask = val << 1;
 
-		tclk = 1000000 / freq_val[tm->interface_params[0].memory_freq];
+		tclk = 1000000 / mv_ddr_freq_get(iface_params->memory_freq);
 		/* update cas write latency (cwl) */
 		val = mv_ddr_cwl_calc(tclk);
 		if (val == 0) {
 			printf("mv_ddr: unsupported cas write latency value found\n");
-			return NULL;
+			return -1;
 		}
-		tm->interface_params[0].cas_wl = val;
+		iface_params->cas_wl = val;
 
 		/* update cas latency (cl) */
 		mv_ddr_spd_supported_cls_calc(&tm->spd_data);
 		val = mv_ddr_cl_calc(tm->timing_data[MV_DDR_TAA_MIN], tclk);
 		if (val == 0) {
 			printf("mv_ddr: unsupported cas latency value found\n");
-			return NULL;
+			return -1;
 		}
-		tm->interface_params[0].cas_l = val;
+		iface_params->cas_l = val;
 	} else if (tm->cfg_src == MV_DDR_CFG_DEFAULT) {
 		/* set cas and cas-write latencies per speed bin, if they unset */
-		speed_bin_index = tm->interface_params[0].speed_bin_index;
-		freq = tm->interface_params[0].memory_freq;
+		speed_bin_index = iface_params->speed_bin_index;
+		freq = iface_params->memory_freq;
 
-		if (tm->interface_params[0].cas_l == 0)
-			tm->interface_params[0].cas_l =
-				cas_latency_table[speed_bin_index].cl_val[freq];
+		if (iface_params->cas_l == 0)
+			iface_params->cas_l = mv_ddr_cl_val_get(speed_bin_index, freq);
 
-		if (tm->interface_params[0].cas_wl == 0)
-			tm->interface_params[0].cas_wl =
-				cas_write_latency_table[speed_bin_index].cl_val[freq];
+		if (iface_params->cas_wl == 0)
+			iface_params->cas_wl = mv_ddr_cwl_val_get(speed_bin_index, freq);
 	}
 
-
-	return tm;
+	return 0;
 }
 
 unsigned short mv_ddr_bus_bit_mask_get(void)
@@ -195,3 +195,150 @@
 
 	return bus_width;
 }
+
+unsigned int mv_ddr_cs_num_get(void)
+{
+	unsigned int cs_num = 0;
+	unsigned int cs, sphy;
+	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
+	struct if_params *iface_params = &(tm->interface_params[0]);
+	unsigned int sphy_max = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
+
+	for (sphy = 0; sphy < sphy_max; sphy++) {
+		VALIDATE_BUS_ACTIVE(tm->bus_act_mask, sphy);
+		break;
+	}
+
+	for (cs = 0; cs < MAX_CS_NUM; cs++) {
+		VALIDATE_ACTIVE(iface_params->as_bus_params[sphy].cs_bitmask, cs);
+		cs_num++;
+	}
+
+	return cs_num;
+}
+
+int mv_ddr_is_ecc_ena(void)
+{
+	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
+
+	if (DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask) ||
+	    DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask) ||
+	    DDR3_IS_ECC_PUP8_MODE(tm->bus_act_mask))
+		return 1;
+	else
+		return 0;
+}
+
+/* translate topology map definition to real memory size in bits */
+static unsigned int mem_size[] = {
+	ADDR_SIZE_512MB,
+	ADDR_SIZE_1GB,
+	ADDR_SIZE_2GB,
+	ADDR_SIZE_4GB,
+	ADDR_SIZE_8GB
+	/* TODO: add capacity up to 256GB */
+};
+
+unsigned long long mv_ddr_mem_sz_per_cs_get(void)
+{
+	unsigned long long mem_sz_per_cs;
+	unsigned int i, sphys, sphys_per_dunit;
+	unsigned int sphy_max = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
+	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
+	struct if_params *iface_params = &(tm->interface_params[0]);
+
+	/* calc number of active subphys excl. ecc one */
+	for (i = 0, sphys = 0; i < sphy_max - 1; i++) {
+		VALIDATE_BUS_ACTIVE(tm->bus_act_mask, i);
+		sphys++;
+	}
+
+	/* calc number of subphys per ddr unit */
+	if (iface_params->bus_width == MV_DDR_DEV_WIDTH_8BIT)
+		sphys_per_dunit = MV_DDR_ONE_SPHY_PER_DUNIT;
+	else if (iface_params->bus_width == MV_DDR_DEV_WIDTH_16BIT)
+		sphys_per_dunit = MV_DDR_TWO_SPHY_PER_DUNIT;
+	else {
+		printf("mv_ddr: unsupported bus width type found\n");
+		return 0;
+	}
+
+	/* calc dram size per cs */
+	mem_sz_per_cs = (unsigned long long)mem_size[iface_params->memory_size] *
+			(unsigned long long)sphys /
+			(unsigned long long)sphys_per_dunit;
+
+	return mem_sz_per_cs;
+}
+
+unsigned long long mv_ddr_mem_sz_get(void)
+{
+	unsigned long long tot_mem_sz = 0;
+	unsigned long long mem_sz_per_cs = 0;
+	unsigned long long max_cs = mv_ddr_cs_num_get();
+
+	mem_sz_per_cs = mv_ddr_mem_sz_per_cs_get();
+	tot_mem_sz = max_cs * mem_sz_per_cs;
+
+	return tot_mem_sz;
+}
+
+unsigned int mv_ddr_rtt_nom_get(void)
+{
+	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
+	unsigned int rtt_nom = tm->edata.mem_edata.rtt_nom;
+
+	if (rtt_nom >= MV_DDR_RTT_NOM_PARK_RZQ_LAST) {
+		printf("error: %s: unsupported rtt_nom parameter found\n", __func__);
+		rtt_nom = PARAM_UNDEFINED;
+	}
+
+	return rtt_nom;
+}
+
+unsigned int mv_ddr_rtt_park_get(void)
+{
+	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
+	unsigned int cs_num = mv_ddr_cs_num_get();
+	unsigned int rtt_park = MV_DDR_RTT_NOM_PARK_RZQ_LAST;
+
+	if (cs_num > 0 && cs_num <= MAX_CS_NUM)
+		rtt_park = tm->edata.mem_edata.rtt_park[cs_num - 1];
+
+	if (rtt_park >= MV_DDR_RTT_NOM_PARK_RZQ_LAST) {
+		printf("error: %s: unsupported rtt_park parameter found\n", __func__);
+		rtt_park = PARAM_UNDEFINED;
+	}
+
+	return rtt_park;
+}
+
+unsigned int mv_ddr_rtt_wr_get(void)
+{
+	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
+	unsigned int cs_num = mv_ddr_cs_num_get();
+	unsigned int rtt_wr = MV_DDR_RTT_WR_RZQ_LAST;
+
+	if (cs_num > 0 && cs_num <= MAX_CS_NUM)
+		rtt_wr = tm->edata.mem_edata.rtt_wr[cs_num - 1];
+
+	if (rtt_wr >= MV_DDR_RTT_WR_RZQ_LAST) {
+		printf("error: %s: unsupported rtt_wr parameter found\n", __func__);
+		rtt_wr = PARAM_UNDEFINED;
+	}
+
+	return rtt_wr;
+}
+
+unsigned int mv_ddr_dic_get(void)
+{
+	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
+	unsigned int dic = tm->edata.mem_edata.dic;
+
+	if (dic >= MV_DDR_DIC_RZQ_LAST) {
+		printf("error: %s: unsupported dic parameter found\n", __func__);
+		dic = PARAM_UNDEFINED;
+	}
+
+	return dic;
+}
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.h b/drivers/ddr/marvell/a38x/mv_ddr_topology.h
index 7bef2d1..766f25d 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_topology.h
+++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.h
@@ -6,6 +6,75 @@
 #ifndef _MV_DDR_TOPOLOGY_H
 #define _MV_DDR_TOPOLOGY_H
 
+#define MAX_CS_NUM	4
+
+enum mv_ddr_speed_bin {
+	SPEED_BIN_DDR_800D,
+	SPEED_BIN_DDR_800E,
+	SPEED_BIN_DDR_1066E,
+	SPEED_BIN_DDR_1066F,
+	SPEED_BIN_DDR_1066G,
+	SPEED_BIN_DDR_1333F,
+	SPEED_BIN_DDR_1333G,
+	SPEED_BIN_DDR_1333H,
+	SPEED_BIN_DDR_1333J,
+	SPEED_BIN_DDR_1600G,
+	SPEED_BIN_DDR_1600H,
+	SPEED_BIN_DDR_1600J,
+	SPEED_BIN_DDR_1600K,
+	SPEED_BIN_DDR_1866J,
+	SPEED_BIN_DDR_1866K,
+	SPEED_BIN_DDR_1866L,
+	SPEED_BIN_DDR_1866M,
+	SPEED_BIN_DDR_2133K,
+	SPEED_BIN_DDR_2133L,
+	SPEED_BIN_DDR_2133M,
+	SPEED_BIN_DDR_2133N,
+
+	SPEED_BIN_DDR_1333H_EXT,
+	SPEED_BIN_DDR_1600K_EXT,
+	SPEED_BIN_DDR_1866M_EXT
+};
+
+enum mv_ddr_freq {
+	MV_DDR_FREQ_LOW_FREQ,
+	MV_DDR_FREQ_400,
+	MV_DDR_FREQ_533,
+	MV_DDR_FREQ_667,
+	MV_DDR_FREQ_800,
+	MV_DDR_FREQ_933,
+	MV_DDR_FREQ_1066,
+	MV_DDR_FREQ_311,
+	MV_DDR_FREQ_333,
+	MV_DDR_FREQ_467,
+	MV_DDR_FREQ_850,
+	MV_DDR_FREQ_600,
+	MV_DDR_FREQ_300,
+	MV_DDR_FREQ_900,
+	MV_DDR_FREQ_360,
+	MV_DDR_FREQ_1000,
+	MV_DDR_FREQ_LAST,
+	MV_DDR_FREQ_SAR
+};
+
+enum mv_ddr_speed_bin_timing {
+	SPEED_BIN_TRCD,
+	SPEED_BIN_TRP,
+	SPEED_BIN_TRAS,
+	SPEED_BIN_TRC,
+	SPEED_BIN_TRRD1K,
+	SPEED_BIN_TRRD2K,
+	SPEED_BIN_TPD,
+	SPEED_BIN_TFAW1K,
+	SPEED_BIN_TFAW2K,
+	SPEED_BIN_TWTR,
+	SPEED_BIN_TRTP,
+	SPEED_BIN_TWR,
+	SPEED_BIN_TMOD,
+	SPEED_BIN_TXPDLL,
+	SPEED_BIN_TXSDLL
+};
+
 /* ddr bus masks */
 #define BUS_MASK_32BIT			0xf
 #define BUS_MASK_32BIT_ECC		0x1f
@@ -16,6 +85,12 @@
 #define MV_DDR_64BIT_ECC_PUP8_BUS_MASK	0x1ff
 #define MV_DDR_32BIT_ECC_PUP8_BUS_MASK	0x10f
 
+#define MV_DDR_CS_BITMASK_1CS		0x1
+#define MV_DDR_CS_BITMASK_2CS		0x3
+
+#define MV_DDR_ONE_SPHY_PER_DUNIT	1
+#define MV_DDR_TWO_SPHY_PER_DUNIT	2
+
 /* source of ddr configuration data */
 enum mv_ddr_cfg_src {
 	MV_DDR_CFG_DEFAULT,	/* based on data in mv_ddr_topology_map structure */
@@ -25,11 +100,6 @@
 	MV_DDR_CFG_LAST
 };
 
-enum mv_ddr_num_of_sub_phys_per_ddr_unit {
-	SINGLE_SUB_PHY = 1,
-	TWO_SUB_PHYS = 2
-};
-
 enum mv_ddr_temperature {
 	MV_DDR_TEMP_LOW,
 	MV_DDR_TEMP_NORMAL,
@@ -53,12 +123,78 @@
 	MV_DDR_TRAS_MIN, /* min active to precharge delay time (t ras min) */
 	MV_DDR_TRRD_S_MIN, /* min activate to activate delay time (t rrd_s min), diff bank group */
 	MV_DDR_TRRD_L_MIN, /* min activate to activate delay time (t rrd_l min), same bank group */
+	MV_DDR_TCCD_L_MIN, /* min cas to cas delay time (t ccd_l min), same bank group */
 	MV_DDR_TFAW_MIN, /* min four activate window delay time (t faw min) */
 	MV_DDR_TWTR_S_MIN, /* min write to read time (t wtr s min), diff bank group */
 	MV_DDR_TWTR_L_MIN, /* min write to read time (t wtr l min), same bank group */
 	MV_DDR_TDATA_LAST
 };
 
+enum mv_ddr_electrical_data {
+	MV_DDR_CK_DLY,
+	MV_DDR_PHY_REG3,
+	MV_DDR_ZPRI_DATA,
+	MV_DDR_ZNRI_DATA,
+	MV_DDR_ZPRI_CTRL,
+	MV_DDR_ZNRI_CTRL,
+	MV_DDR_ZPODT_DATA,
+	MV_DDR_ZNODT_DATA,
+	MV_DDR_ZPODT_CTRL,
+	MV_DDR_ZNODT_CTRL,
+	MV_DDR_DIC,
+	MV_DDR_ODT_CFG,
+	MV_DDR_RTT_NOM,
+	MV_DDR_RTT_WR,
+	MV_DDR_RTT_PARK,
+	MV_DDR_EDATA_LAST
+};
+
+/* memory electrical configuration values */
+enum mv_ddr_rtt_nom_park_evalue {
+	MV_DDR_RTT_NOM_PARK_RZQ_DISABLE,
+	MV_DDR_RTT_NOM_PARK_RZQ_DIV4,	/* 60-Ohm; RZQ = 240-Ohm */
+	MV_DDR_RTT_NOM_PARK_RZQ_DIV2,	/* 120-Ohm; RZQ = 240-Ohm */
+	MV_DDR_RTT_NOM_PARK_RZQ_DIV6,	/* 40-Ohm; RZQ = 240-Ohm */
+	MV_DDR_RTT_NOM_PARK_RZQ_DIV1,	/* 240-Ohm; RZQ = 240-Ohm */
+	MV_DDR_RTT_NOM_PARK_RZQ_DIV5,	/* 48-Ohm; RZQ = 240-Ohm */
+	MV_DDR_RTT_NOM_PARK_RZQ_DIV3,	/* 80-Ohm; RZQ = 240-Ohm */
+	MV_DDR_RTT_NOM_PARK_RZQ_DIV7,	/* 34-Ohm; RZQ = 240-Ohm */
+	MV_DDR_RTT_NOM_PARK_RZQ_LAST
+};
+
+enum mv_ddr_rtt_wr_evalue {
+	MV_DDR_RTT_WR_DYN_ODT_OFF,
+	MV_DDR_RTT_WR_RZQ_DIV2,	/* 120-Ohm; RZQ = 240-Ohm */
+	MV_DDR_RTT_WR_RZQ_DIV1,	/* 240-Ohm; RZQ = 240-Ohm */
+	MV_DDR_RTT_WR_HIZ,
+	MV_DDR_RTT_WR_RZQ_DIV3,	/* 80-Ohm; RZQ = 240-Ohm */
+	MV_DDR_RTT_WR_RZQ_LAST
+};
+
+enum mv_ddr_dic_evalue {
+	MV_DDR_DIC_RZQ_DIV7,	/* 34-Ohm; RZQ = 240-Ohm */
+	MV_DDR_DIC_RZQ_DIV5,	/* 48-Ohm; RZQ = 240-Ohm */
+	MV_DDR_DIC_RZQ_LAST
+};
+
+/* phy electrical configuration values */
+enum mv_ddr_ohm_evalue {
+	MV_DDR_OHM_30 = 30,
+	MV_DDR_OHM_48 = 48,
+	MV_DDR_OHM_60 = 60,
+	MV_DDR_OHM_80 = 80,
+	MV_DDR_OHM_120 = 120,
+	MV_DDR_OHM_240 = 240,
+	MV_DDR_OHM_LAST
+};
+
+/* mac electrical configuration values */
+enum mv_ddr_odt_cfg_evalue {
+	MV_DDR_ODT_CFG_NORMAL,
+	MV_DDR_ODT_CFG_ALWAYS_ON,
+	MV_DDR_ODT_CFG_LAST
+};
+
 enum mv_ddr_dev_width { /* sdram device width */
 	MV_DDR_DEV_WIDTH_4BIT,
 	MV_DDR_DEV_WIDTH_8BIT,
@@ -119,11 +255,75 @@
 	MV_DDR_DIE_CNT_LAST
 };
 
+#define IS_ACTIVE(mask, id) \
+	((mask) & (1 << (id)))
+
+#define VALIDATE_ACTIVE(mask, id)		\
+	{					\
+	if (IS_ACTIVE(mask, id) == 0)		\
+		continue;			\
+	}
+
+#define IS_IF_ACTIVE(if_mask, if_id) \
+	((if_mask) & (1 << (if_id)))
+
+#define VALIDATE_IF_ACTIVE(mask, id)		\
+	{					\
+	if (IS_IF_ACTIVE(mask, id) == 0)	\
+		continue;			\
+	}
+
+#define IS_BUS_ACTIVE(if_mask , if_id) \
+	(((if_mask) >> (if_id)) & 1)
+
+#define VALIDATE_BUS_ACTIVE(mask, id)		\
+	{					\
+	if (IS_BUS_ACTIVE(mask, id) == 0)	\
+		continue;			\
+	}
+
+#define DDR3_IS_ECC_PUP3_MODE(if_mask)		\
+	(((if_mask) == BUS_MASK_16BIT_ECC_PUP3) ? 1 : 0)
+
+#define DDR3_IS_ECC_PUP4_MODE(if_mask)		\
+	(((if_mask) == BUS_MASK_32BIT_ECC ||	\
+	  (if_mask) == BUS_MASK_16BIT_ECC) ? 1 : 0)
+
+#define DDR3_IS_16BIT_DRAM_MODE(mask)		\
+	(((mask) == BUS_MASK_16BIT ||		\
+	  (mask) == BUS_MASK_16BIT_ECC ||	\
+	  (mask) == BUS_MASK_16BIT_ECC_PUP3) ? 1 : 0)
+
+#define DDR3_IS_ECC_PUP8_MODE(if_mask)				\
+	(((if_mask) == MV_DDR_32BIT_ECC_PUP8_BUS_MASK ||	\
+	  (if_mask) == MV_DDR_64BIT_ECC_PUP8_BUS_MASK) ? 1 : 0)
+
+#define MV_DDR_IS_64BIT_DRAM_MODE(mask)					\
+	((((mask) & MV_DDR_64BIT_BUS_MASK) == MV_DDR_64BIT_BUS_MASK) ||	\
+	 (((mask) & MV_DDR_64BIT_ECC_PUP8_BUS_MASK) == MV_DDR_64BIT_ECC_PUP8_BUS_MASK) ? 1 : 0)
+
+#define MV_DDR_IS_32BIT_IN_64BIT_DRAM_MODE(mask, sphys)		\
+	(((sphys) == 9) &&					\
+	(((mask) == BUS_MASK_32BIT) ||				\
+	 ((mask) == MV_DDR_32BIT_ECC_PUP8_BUS_MASK)) ? 1 : 0)
+
+#define MV_DDR_IS_HALF_BUS_DRAM_MODE(mask, sphys)		\
+	(MV_DDR_IS_32BIT_IN_64BIT_DRAM_MODE(mask, sphys) ||	\
+	 DDR3_IS_16BIT_DRAM_MODE(mask))
+
+struct mv_ddr_topology_map *mv_ddr_topology_map_get(void);
 unsigned int mv_ddr_cl_calc(unsigned int taa_min, unsigned int tclk);
 unsigned int mv_ddr_cwl_calc(unsigned int tclk);
-struct mv_ddr_topology_map *mv_ddr_topology_map_update(void);
-struct dram_config *mv_ddr_dram_config_update(void);
+int mv_ddr_topology_map_update(void);
 unsigned short mv_ddr_bus_bit_mask_get(void);
 unsigned int mv_ddr_if_bus_width_get(void);
+unsigned int mv_ddr_cs_num_get(void);
+int mv_ddr_is_ecc_ena(void);
+unsigned long long mv_ddr_mem_sz_per_cs_get(void);
+unsigned long long mv_ddr_mem_sz_get(void);
+unsigned int mv_ddr_rtt_nom_get(void);
+unsigned int mv_ddr_rtt_park_get(void);
+unsigned int mv_ddr_rtt_wr_get(void);
+unsigned int mv_ddr_dic_get(void);
 
 #endif /* _MV_DDR_TOPOLOGY_H */
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_training_db.h b/drivers/ddr/marvell/a38x/mv_ddr_training_db.h
new file mode 100644
index 0000000..838be45
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/mv_ddr_training_db.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ */
+
+#ifndef _MV_DDR_TRAINING_DB_H
+#define _MV_DDR_TRAINING_DB_H
+
+#include "mv_ddr_topology.h"
+
+/* in ns */
+#define TREFI_LOW	7800
+#define TREFI_HIGH	3900
+
+enum mv_ddr_page_size {
+	MV_DDR_PAGE_SIZE_1K = 1,
+	MV_DDR_PAGE_SIZE_2K
+};
+
+struct mv_ddr_page_element {
+	/* 8-bit bus width page size */
+	enum mv_ddr_page_size page_size_8bit;
+	/* 16-bit bus width page size */
+	enum mv_ddr_page_size page_size_16bit;
+};
+
+/* cas latency value per frequency */
+struct mv_ddr_cl_val_per_freq {
+	unsigned int cl_val[MV_DDR_FREQ_LAST];
+};
+
+u32 mv_ddr_rfc_get(u32 mem);
+unsigned int *mv_ddr_freq_tbl_get(void);
+u32 mv_ddr_freq_get(enum mv_ddr_freq freq);
+u32 mv_ddr_page_size_get(enum mv_ddr_dev_width bus_width, enum mv_ddr_die_capacity mem_size);
+unsigned int mv_ddr_speed_bin_timing_get(enum mv_ddr_speed_bin index, enum mv_ddr_speed_bin_timing element);
+u32 mv_ddr_cl_val_get(u32 index, u32 freq);
+u32 mv_ddr_cwl_val_get(u32 index, u32 freq);
+
+#endif /* _MV_DDR_TRAINING_DB_H */
diff --git a/drivers/ddr/marvell/a38x/xor.c b/drivers/ddr/marvell/a38x/xor.c
index f859596..5fb9e21 100644
--- a/drivers/ddr/marvell/a38x/xor.c
+++ b/drivers/ddr/marvell/a38x/xor.c
@@ -4,6 +4,7 @@
  */
 
 #include "ddr3_init.h"
+#include "mv_ddr_common.h"
 #include "xor_regs.h"
 
 /* defines  */
@@ -339,16 +340,17 @@
 {
 	u32 cs_c, max_cs;
 	u32 cs_ena = 0;
-	u32 dev_num = 0;
 	uint64_t total_mem_size, cs_mem_size = 0;
 
 	printf("DDR Training Sequence - Start scrubbing\n");
-	max_cs = ddr3_tip_max_cs_get(dev_num);
+	max_cs = mv_ddr_cs_num_get();
 	for (cs_c = 0; cs_c < max_cs; cs_c++)
 		cs_ena |= 1 << cs_c;
 
-	/* assume that all CS have same size */
+#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
+	/* all chip-selects are of same size */
 	ddr3_calc_mem_cs_size(0, &cs_mem_size);
+#endif
 
 	mv_sys_xor_init(max_cs, cs_ena, cs_mem_size, 0);
 	total_mem_size = max_cs * cs_mem_size;
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 4ee6afa..8a4162e 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -12,6 +12,20 @@
 	  buses that is used to transfer data to and from memory.
 	  The uclass interface is defined in include/dma.h.
 
+config DMA_CHANNELS
+	bool "Enable DMA channels support"
+	depends on DMA
+	help
+	  Enable channels support for DMA. Some DMA controllers have multiple
+	  channels which can either transfer data to/from different devices.
+
+config SANDBOX_DMA
+	bool "Enable the sandbox DMA test driver"
+	depends on DMA && DMA_CHANNELS && SANDBOX
+	help
+	  Enable support for a test DMA uclass implementation. It stimulates
+	  DMA transfer by simple copying data between channels.
+
 config TI_EDMA3
 	bool "TI EDMA3 driver"
 	help
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 4eaef8a..aff31f9 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -8,6 +8,7 @@
 obj-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
 obj-$(CONFIG_APBH_DMA) += apbh_dma.o
 obj-$(CONFIG_FSL_DMA) += fsl_dma.o
+obj-$(CONFIG_SANDBOX_DMA) += sandbox-dma-test.o
 obj-$(CONFIG_TI_KSNAV) += keystone_nav.o keystone_nav_cfg.o
 obj-$(CONFIG_TI_EDMA3) += ti-edma3.o
 obj-$(CONFIG_DMA_LPC32XX) += lpc32xx_dma.o
diff --git a/drivers/dma/dma-uclass.c b/drivers/dma/dma-uclass.c
index a33f7d5..9c961cf 100644
--- a/drivers/dma/dma-uclass.c
+++ b/drivers/dma/dma-uclass.c
@@ -2,19 +2,192 @@
 /*
  * Direct Memory Access U-Class driver
  *
- * (C) Copyright 2015
- *     Texas Instruments Incorporated, <www.ti.com>
+ * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
+ * Copyright (C) 2015 - 2018 Texas Instruments Incorporated <www.ti.com>
+ * Written by Mugunthan V N <mugunthanvnm@ti.com>
  *
  * Author: Mugunthan V N <mugunthanvnm@ti.com>
  */
 
 #include <common.h>
-#include <dma.h>
 #include <dm.h>
-#include <dm/uclass-internal.h>
-#include <dm/device-internal.h>
+#include <dm/read.h>
+#include <dma-uclass.h>
+#include <dt-structs.h>
 #include <errno.h>
 
+#ifdef CONFIG_DMA_CHANNELS
+static inline struct dma_ops *dma_dev_ops(struct udevice *dev)
+{
+	return (struct dma_ops *)dev->driver->ops;
+}
+
+# if CONFIG_IS_ENABLED(OF_CONTROL)
+static int dma_of_xlate_default(struct dma *dma,
+				struct ofnode_phandle_args *args)
+{
+	debug("%s(dma=%p)\n", __func__, dma);
+
+	if (args->args_count > 1) {
+		pr_err("Invaild args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	if (args->args_count)
+		dma->id = args->args[0];
+	else
+		dma->id = 0;
+
+	return 0;
+}
+
+int dma_get_by_index(struct udevice *dev, int index, struct dma *dma)
+{
+	int ret;
+	struct ofnode_phandle_args args;
+	struct udevice *dev_dma;
+	const struct dma_ops *ops;
+
+	debug("%s(dev=%p, index=%d, dma=%p)\n", __func__, dev, index, dma);
+
+	assert(dma);
+	dma->dev = NULL;
+
+	ret = dev_read_phandle_with_args(dev, "dmas", "#dma-cells", 0, index,
+					 &args);
+	if (ret) {
+		pr_err("%s: dev_read_phandle_with_args failed: err=%d\n",
+		       __func__, ret);
+		return ret;
+	}
+
+	ret = uclass_get_device_by_ofnode(UCLASS_DMA, args.node, &dev_dma);
+	if (ret) {
+		pr_err("%s: uclass_get_device_by_ofnode failed: err=%d\n",
+		       __func__, ret);
+		return ret;
+	}
+
+	dma->dev = dev_dma;
+
+	ops = dma_dev_ops(dev_dma);
+
+	if (ops->of_xlate)
+		ret = ops->of_xlate(dma, &args);
+	else
+		ret = dma_of_xlate_default(dma, &args);
+	if (ret) {
+		pr_err("of_xlate() failed: %d\n", ret);
+		return ret;
+	}
+
+	return dma_request(dev_dma, dma);
+}
+
+int dma_get_by_name(struct udevice *dev, const char *name, struct dma *dma)
+{
+	int index;
+
+	debug("%s(dev=%p, name=%s, dma=%p)\n", __func__, dev, name, dma);
+	dma->dev = NULL;
+
+	index = dev_read_stringlist_search(dev, "dma-names", name);
+	if (index < 0) {
+		pr_err("dev_read_stringlist_search() failed: %d\n", index);
+		return index;
+	}
+
+	return dma_get_by_index(dev, index, dma);
+}
+# endif /* OF_CONTROL */
+
+int dma_request(struct udevice *dev, struct dma *dma)
+{
+	struct dma_ops *ops = dma_dev_ops(dev);
+
+	debug("%s(dev=%p, dma=%p)\n", __func__, dev, dma);
+
+	dma->dev = dev;
+
+	if (!ops->request)
+		return 0;
+
+	return ops->request(dma);
+}
+
+int dma_free(struct dma *dma)
+{
+	struct dma_ops *ops = dma_dev_ops(dma->dev);
+
+	debug("%s(dma=%p)\n", __func__, dma);
+
+	if (!ops->free)
+		return 0;
+
+	return ops->free(dma);
+}
+
+int dma_enable(struct dma *dma)
+{
+	struct dma_ops *ops = dma_dev_ops(dma->dev);
+
+	debug("%s(dma=%p)\n", __func__, dma);
+
+	if (!ops->enable)
+		return -ENOSYS;
+
+	return ops->enable(dma);
+}
+
+int dma_disable(struct dma *dma)
+{
+	struct dma_ops *ops = dma_dev_ops(dma->dev);
+
+	debug("%s(dma=%p)\n", __func__, dma);
+
+	if (!ops->disable)
+		return -ENOSYS;
+
+	return ops->disable(dma);
+}
+
+int dma_prepare_rcv_buf(struct dma *dma, void *dst, size_t size)
+{
+	struct dma_ops *ops = dma_dev_ops(dma->dev);
+
+	debug("%s(dma=%p)\n", __func__, dma);
+
+	if (!ops->prepare_rcv_buf)
+		return -1;
+
+	return ops->prepare_rcv_buf(dma, dst, size);
+}
+
+int dma_receive(struct dma *dma, void **dst, void *metadata)
+{
+	struct dma_ops *ops = dma_dev_ops(dma->dev);
+
+	debug("%s(dma=%p)\n", __func__, dma);
+
+	if (!ops->receive)
+		return -ENOSYS;
+
+	return ops->receive(dma, dst, metadata);
+}
+
+int dma_send(struct dma *dma, void *src, size_t len, void *metadata)
+{
+	struct dma_ops *ops = dma_dev_ops(dma->dev);
+
+	debug("%s(dma=%p)\n", __func__, dma);
+
+	if (!ops->send)
+		return -ENOSYS;
+
+	return ops->send(dma, src, len, metadata);
+}
+#endif /* CONFIG_DMA_CHANNELS */
+
 int dma_get_device(u32 transfer_type, struct udevice **devp)
 {
 	struct udevice *dev;
diff --git a/drivers/dma/sandbox-dma-test.c b/drivers/dma/sandbox-dma-test.c
new file mode 100644
index 0000000..8fcef18
--- /dev/null
+++ b/drivers/dma/sandbox-dma-test.c
@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Direct Memory Access U-Class Simulation driver
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated <www.ti.com>
+ *
+ * Author: Grygorii Strashko <grygorii.strashko@ti.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/read.h>
+#include <dma-uclass.h>
+#include <dt-structs.h>
+#include <errno.h>
+
+#define SANDBOX_DMA_CH_CNT 3
+#define SANDBOX_DMA_BUF_SIZE 1024
+
+struct sandbox_dma_chan {
+	struct sandbox_dma_dev *ud;
+	char name[20];
+	u32 id;
+	enum dma_direction dir;
+	bool in_use;
+	bool enabled;
+};
+
+struct sandbox_dma_dev {
+	struct device *dev;
+	u32 ch_count;
+	struct sandbox_dma_chan channels[SANDBOX_DMA_CH_CNT];
+	uchar   buf[SANDBOX_DMA_BUF_SIZE];
+	uchar	*buf_rx;
+	size_t	data_len;
+	u32	meta;
+};
+
+static int sandbox_dma_transfer(struct udevice *dev, int direction,
+				void *dst, void *src, size_t len)
+{
+	memcpy(dst, src, len);
+
+	return 0;
+}
+
+static int sandbox_dma_of_xlate(struct dma *dma,
+				struct ofnode_phandle_args *args)
+{
+	struct sandbox_dma_dev *ud = dev_get_priv(dma->dev);
+	struct sandbox_dma_chan *uc;
+
+	debug("%s(dma id=%u)\n", __func__, args->args[0]);
+
+	if (args->args[0] >= SANDBOX_DMA_CH_CNT)
+		return -EINVAL;
+
+	dma->id = args->args[0];
+
+	uc = &ud->channels[dma->id];
+
+	if (dma->id == 1)
+		uc->dir = DMA_MEM_TO_DEV;
+	else if (dma->id == 2)
+		uc->dir = DMA_DEV_TO_MEM;
+	else
+		uc->dir = DMA_MEM_TO_MEM;
+	debug("%s(dma id=%lu dir=%d)\n", __func__, dma->id, uc->dir);
+
+	return 0;
+}
+
+static int sandbox_dma_request(struct dma *dma)
+{
+	struct sandbox_dma_dev *ud = dev_get_priv(dma->dev);
+	struct sandbox_dma_chan *uc;
+
+	if (dma->id >= SANDBOX_DMA_CH_CNT)
+		return -EINVAL;
+
+	uc = &ud->channels[dma->id];
+	if (uc->in_use)
+		return -EBUSY;
+
+	uc->in_use = true;
+	debug("%s(dma id=%lu in_use=%d)\n", __func__, dma->id, uc->in_use);
+
+	return 0;
+}
+
+static int sandbox_dma_free(struct dma *dma)
+{
+	struct sandbox_dma_dev *ud = dev_get_priv(dma->dev);
+	struct sandbox_dma_chan *uc;
+
+	if (dma->id >= SANDBOX_DMA_CH_CNT)
+		return -EINVAL;
+
+	uc = &ud->channels[dma->id];
+	if (!uc->in_use)
+		return -EINVAL;
+
+	uc->in_use = false;
+	ud->buf_rx = NULL;
+	ud->data_len = 0;
+	debug("%s(dma id=%lu in_use=%d)\n", __func__, dma->id, uc->in_use);
+
+	return 0;
+}
+
+static int sandbox_dma_enable(struct dma *dma)
+{
+	struct sandbox_dma_dev *ud = dev_get_priv(dma->dev);
+	struct sandbox_dma_chan *uc;
+
+	if (dma->id >= SANDBOX_DMA_CH_CNT)
+		return -EINVAL;
+
+	uc = &ud->channels[dma->id];
+	if (!uc->in_use)
+		return -EINVAL;
+	if (uc->enabled)
+		return -EINVAL;
+
+	uc->enabled = true;
+	debug("%s(dma id=%lu enabled=%d)\n", __func__, dma->id, uc->enabled);
+
+	return 0;
+}
+
+static int sandbox_dma_disable(struct dma *dma)
+{
+	struct sandbox_dma_dev *ud = dev_get_priv(dma->dev);
+	struct sandbox_dma_chan *uc;
+
+	if (dma->id >= SANDBOX_DMA_CH_CNT)
+		return -EINVAL;
+
+	uc = &ud->channels[dma->id];
+	if (!uc->in_use)
+		return -EINVAL;
+	if (!uc->enabled)
+		return -EINVAL;
+
+	uc->enabled = false;
+	debug("%s(dma id=%lu enabled=%d)\n", __func__, dma->id, uc->enabled);
+
+	return 0;
+}
+
+static int sandbox_dma_send(struct dma *dma,
+			    void *src, size_t len, void *metadata)
+{
+	struct sandbox_dma_dev *ud = dev_get_priv(dma->dev);
+	struct sandbox_dma_chan *uc;
+
+	if (dma->id >= SANDBOX_DMA_CH_CNT)
+		return -EINVAL;
+	if (!src || !metadata)
+		return -EINVAL;
+
+	debug("%s(dma id=%lu)\n", __func__, dma->id);
+
+	uc = &ud->channels[dma->id];
+	if (uc->dir != DMA_MEM_TO_DEV)
+		return -EINVAL;
+	if (!uc->in_use)
+		return -EINVAL;
+	if (!uc->enabled)
+		return -EINVAL;
+	if (len >= SANDBOX_DMA_BUF_SIZE)
+		return -EINVAL;
+
+	memcpy(ud->buf, src, len);
+	ud->data_len = len;
+	ud->meta = *((u32 *)metadata);
+
+	debug("%s(dma id=%lu len=%zu meta=%08x)\n",
+	      __func__, dma->id, len, ud->meta);
+
+	return 0;
+}
+
+static int sandbox_dma_receive(struct dma *dma, void **dst, void *metadata)
+{
+	struct sandbox_dma_dev *ud = dev_get_priv(dma->dev);
+	struct sandbox_dma_chan *uc;
+
+	if (dma->id >= SANDBOX_DMA_CH_CNT)
+		return -EINVAL;
+	if (!dst || !metadata)
+		return -EINVAL;
+
+	uc = &ud->channels[dma->id];
+	if (uc->dir != DMA_DEV_TO_MEM)
+		return -EINVAL;
+	if (!uc->in_use)
+		return -EINVAL;
+	if (!uc->enabled)
+		return -EINVAL;
+	if (!ud->data_len)
+		return 0;
+
+	if (ud->buf_rx) {
+		memcpy(ud->buf_rx, ud->buf, ud->data_len);
+		*dst = ud->buf_rx;
+	} else {
+		memcpy(*dst, ud->buf, ud->data_len);
+	}
+
+	*((u32 *)metadata) = ud->meta;
+
+	debug("%s(dma id=%lu len=%zu meta=%08x %p)\n",
+	      __func__, dma->id, ud->data_len, ud->meta, *dst);
+
+	return ud->data_len;
+}
+
+static int sandbox_dma_prepare_rcv_buf(struct dma *dma, void *dst, size_t size)
+{
+	struct sandbox_dma_dev *ud = dev_get_priv(dma->dev);
+
+	ud->buf_rx = dst;
+
+	return 0;
+}
+
+static const struct dma_ops sandbox_dma_ops = {
+	.transfer	= sandbox_dma_transfer,
+	.of_xlate	= sandbox_dma_of_xlate,
+	.request	= sandbox_dma_request,
+	.free		= sandbox_dma_free,
+	.enable		= sandbox_dma_enable,
+	.disable	= sandbox_dma_disable,
+	.send		= sandbox_dma_send,
+	.receive	= sandbox_dma_receive,
+	.prepare_rcv_buf = sandbox_dma_prepare_rcv_buf,
+};
+
+static int sandbox_dma_probe(struct udevice *dev)
+{
+	struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct sandbox_dma_dev *ud = dev_get_priv(dev);
+	int i, ret = 0;
+
+	uc_priv->supported = DMA_SUPPORTS_MEM_TO_MEM |
+			     DMA_SUPPORTS_MEM_TO_DEV |
+			     DMA_SUPPORTS_DEV_TO_MEM;
+
+	ud->ch_count = SANDBOX_DMA_CH_CNT;
+	ud->buf_rx = NULL;
+	ud->meta = 0;
+	ud->data_len = 0;
+
+	pr_err("Number of channels: %u\n", ud->ch_count);
+
+	for (i = 0; i < ud->ch_count; i++) {
+		struct sandbox_dma_chan *uc = &ud->channels[i];
+
+		uc->ud = ud;
+		uc->id = i;
+		sprintf(uc->name, "DMA chan%d\n", i);
+		uc->in_use = false;
+		uc->enabled = false;
+	}
+
+	return ret;
+}
+
+static const struct udevice_id sandbox_dma_ids[] = {
+	{ .compatible = "sandbox,dma" },
+	{ }
+};
+
+U_BOOT_DRIVER(sandbox_dma) = {
+	.name	= "sandbox-dma",
+	.id	= UCLASS_DMA,
+	.of_match = sandbox_dma_ids,
+	.ops	= &sandbox_dma_ops,
+	.probe = sandbox_dma_probe,
+	.priv_auto_alloc_size = sizeof(struct sandbox_dma_dev),
+};
diff --git a/drivers/dma/ti-edma3.c b/drivers/dma/ti-edma3.c
index 2131e10..7e11b13 100644
--- a/drivers/dma/ti-edma3.c
+++ b/drivers/dma/ti-edma3.c
@@ -11,7 +11,7 @@
 #include <asm/io.h>
 #include <common.h>
 #include <dm.h>
-#include <dma.h>
+#include <dma-uclass.h>
 #include <asm/omap_common.h>
 #include <asm/ti-common/ti-edma3.h>
 
diff --git a/drivers/gpio/stm32f7_gpio.c b/drivers/gpio/stm32f7_gpio.c
index a690c43..f160b4e 100644
--- a/drivers/gpio/stm32f7_gpio.c
+++ b/drivers/gpio/stm32f7_gpio.c
@@ -15,17 +15,45 @@
 #include <linux/errno.h>
 #include <linux/io.h>
 
-#define STM32_GPIOS_PER_BANK		16
 #define MODE_BITS(gpio_pin)		(gpio_pin * 2)
 #define MODE_BITS_MASK			3
 #define BSRR_BIT(gpio_pin, value)	BIT(gpio_pin + (value ? 0 : 16))
 
+/*
+ * convert gpio offset to gpio index taking into account gpio holes
+ * into gpio bank
+ */
+int stm32_offset_to_index(struct udevice *dev, unsigned int offset)
+{
+	struct stm32_gpio_priv *priv = dev_get_priv(dev);
+	int idx = 0;
+	int i;
+
+	for (i = 0; i < STM32_GPIOS_PER_BANK; i++) {
+		if (priv->gpio_range & BIT(i)) {
+			if (idx == offset)
+				return idx;
+			idx++;
+		}
+	}
+	/* shouldn't happen */
+	return -EINVAL;
+}
+
 static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
 {
 	struct stm32_gpio_priv *priv = dev_get_priv(dev);
 	struct stm32_gpio_regs *regs = priv->regs;
-	int bits_index = MODE_BITS(offset);
-	int mask = MODE_BITS_MASK << bits_index;
+	int bits_index;
+	int mask;
+	int idx;
+
+	idx = stm32_offset_to_index(dev, offset);
+	if (idx < 0)
+		return idx;
+
+	bits_index = MODE_BITS(idx);
+	mask = MODE_BITS_MASK << bits_index;
 
 	clrsetbits_le32(&regs->moder, mask, STM32_GPIO_MODE_IN << bits_index);
 
@@ -37,12 +65,20 @@
 {
 	struct stm32_gpio_priv *priv = dev_get_priv(dev);
 	struct stm32_gpio_regs *regs = priv->regs;
-	int bits_index = MODE_BITS(offset);
-	int mask = MODE_BITS_MASK << bits_index;
+	int bits_index;
+	int mask;
+	int idx;
+
+	idx = stm32_offset_to_index(dev, offset);
+	if (idx < 0)
+		return idx;
+
+	bits_index = MODE_BITS(idx);
+	mask = MODE_BITS_MASK << bits_index;
 
 	clrsetbits_le32(&regs->moder, mask, STM32_GPIO_MODE_OUT << bits_index);
 
-	writel(BSRR_BIT(offset, value), &regs->bsrr);
+	writel(BSRR_BIT(idx, value), &regs->bsrr);
 
 	return 0;
 }
@@ -51,16 +87,26 @@
 {
 	struct stm32_gpio_priv *priv = dev_get_priv(dev);
 	struct stm32_gpio_regs *regs = priv->regs;
+	int idx;
 
-	return readl(&regs->idr) & BIT(offset) ? 1 : 0;
+	idx = stm32_offset_to_index(dev, offset);
+	if (idx < 0)
+		return idx;
+
+	return readl(&regs->idr) & BIT(idx) ? 1 : 0;
 }
 
 static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
 {
 	struct stm32_gpio_priv *priv = dev_get_priv(dev);
 	struct stm32_gpio_regs *regs = priv->regs;
+	int idx;
+
+	idx = stm32_offset_to_index(dev, offset);
+	if (idx < 0)
+		return idx;
 
-	writel(BSRR_BIT(offset, value), &regs->bsrr);
+	writel(BSRR_BIT(idx, value), &regs->bsrr);
 
 	return 0;
 }
@@ -69,10 +115,18 @@
 {
 	struct stm32_gpio_priv *priv = dev_get_priv(dev);
 	struct stm32_gpio_regs *regs = priv->regs;
-	int bits_index = MODE_BITS(offset);
-	int mask = MODE_BITS_MASK << bits_index;
+	int bits_index;
+	int mask;
+	int idx;
 	u32 mode;
 
+	idx = stm32_offset_to_index(dev, offset);
+	if (idx < 0)
+		return idx;
+
+	bits_index = MODE_BITS(idx);
+	mask = MODE_BITS_MASK << bits_index;
+
 	mode = (readl(&regs->moder) & mask) >> bits_index;
 	if (mode == STM32_GPIO_MODE_OUT)
 		return GPIOF_OUTPUT;
@@ -96,8 +150,12 @@
 {
 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 	struct stm32_gpio_priv *priv = dev_get_priv(dev);
+	struct ofnode_phandle_args args;
+	struct clk clk;
 	fdt_addr_t addr;
 	const char *name;
+	int ret;
+	int i;
 
 	addr = dev_read_addr(dev);
 	if (addr == FDT_ADDR_T_NONE)
@@ -108,14 +166,25 @@
 	if (!name)
 		return -EINVAL;
 	uc_priv->bank_name = name;
-	uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios",
-						   STM32_GPIOS_PER_BANK);
-	debug("%s, addr = 0x%p, bank_name = %s\n", __func__, (u32 *)priv->regs,
-	      uc_priv->bank_name);
 
-#ifdef CONFIG_CLK
-	struct clk clk;
-	int ret;
+	i = 0;
+	ret = dev_read_phandle_with_args(dev, "gpio-ranges",
+					 NULL, 3, i, &args);
+
+	while (ret != -ENOENT) {
+		priv->gpio_range |= GENMASK(args.args[2] + args.args[0] - 1,
+				    args.args[0]);
+
+		uc_priv->gpio_count += args.args[2];
+
+		ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
+						 ++i, &args);
+	}
+
+	dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
+		(u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count,
+		priv->gpio_range);
+
 	ret = clk_get_by_index(dev, 0, &clk);
 	if (ret < 0)
 		return ret;
@@ -127,7 +196,6 @@
 		return ret;
 	}
 	debug("clock enabled for device %s\n", dev->name);
-#endif
 
 	return 0;
 }
diff --git a/drivers/hwspinlock/Kconfig b/drivers/hwspinlock/Kconfig
new file mode 100644
index 0000000..96d4f5d
--- /dev/null
+++ b/drivers/hwspinlock/Kconfig
@@ -0,0 +1,24 @@
+menu "Hardware Spinlock Support"
+
+config DM_HWSPINLOCK
+	bool "Enable U-Boot hardware spinlock support"
+	help
+	  This option enables U-Boot hardware spinlock support
+
+config HWSPINLOCK_SANDBOX
+	bool "Enable Hardware Spinlock support for Sandbox"
+	depends on SANDBOX && DM_HWSPINLOCK
+	help
+	  Enable hardware spinlock support in Sandbox. This is a dummy device that
+	  can be probed and support all the methods of HWSPINLOCK, but does not
+	  really do anything.
+
+config HWSPINLOCK_STM32
+	bool "Enable Hardware Spinlock support for STM32"
+	depends on ARCH_STM32MP && DM_HWSPINLOCK
+	help
+	  Enable hardware spinlock support in STM32MP. Hardware spinlocks are
+	  hardware mutex which provide a synchronisation mechanism for the
+	  various processors on the SoC.
+
+endmenu
diff --git a/drivers/hwspinlock/Makefile b/drivers/hwspinlock/Makefile
new file mode 100644
index 0000000..289b12a
--- /dev/null
+++ b/drivers/hwspinlock/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+#
+# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+
+obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock-uclass.o
+obj-$(CONFIG_HWSPINLOCK_SANDBOX) += sandbox_hwspinlock.o
+obj-$(CONFIG_HWSPINLOCK_STM32) += stm32_hwspinlock.o
diff --git a/drivers/hwspinlock/hwspinlock-uclass.c b/drivers/hwspinlock/hwspinlock-uclass.c
new file mode 100644
index 0000000..195f079
--- /dev/null
+++ b/drivers/hwspinlock/hwspinlock-uclass.c
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <hwspinlock.h>
+#include <dm/device-internal.h>
+
+static inline const struct hwspinlock_ops *
+hwspinlock_dev_ops(struct udevice *dev)
+{
+	return (const struct hwspinlock_ops *)dev->driver->ops;
+}
+
+static int hwspinlock_of_xlate_default(struct hwspinlock *hws,
+				       struct ofnode_phandle_args *args)
+{
+	if (args->args_count > 1) {
+		debug("Invaild args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	if (args->args_count)
+		hws->id = args->args[0];
+	else
+		hws->id = 0;
+
+	return 0;
+}
+
+int hwspinlock_get_by_index(struct udevice *dev, int index,
+			    struct hwspinlock *hws)
+{
+	int ret;
+	struct ofnode_phandle_args args;
+	struct udevice *dev_hws;
+	const struct hwspinlock_ops *ops;
+
+	assert(hws);
+	hws->dev = NULL;
+
+	ret = dev_read_phandle_with_args(dev, "hwlocks", "#hwlock-cells", 1,
+					 index, &args);
+	if (ret) {
+		dev_dbg(dev, "%s: dev_read_phandle_with_args: err=%d\n",
+			__func__, ret);
+		return ret;
+	}
+
+	ret = uclass_get_device_by_ofnode(UCLASS_HWSPINLOCK,
+					  args.node, &dev_hws);
+	if (ret) {
+		dev_dbg(dev,
+			"%s: uclass_get_device_by_of_offset failed: err=%d\n",
+			__func__, ret);
+		return ret;
+	}
+
+	hws->dev = dev_hws;
+
+	ops = hwspinlock_dev_ops(dev_hws);
+
+	if (ops->of_xlate)
+		ret = ops->of_xlate(hws, &args);
+	else
+		ret = hwspinlock_of_xlate_default(hws, &args);
+	if (ret)
+		dev_dbg(dev, "of_xlate() failed: %d\n", ret);
+
+	return ret;
+}
+
+int hwspinlock_lock_timeout(struct hwspinlock *hws, unsigned int timeout)
+{
+	const struct hwspinlock_ops *ops;
+	ulong start;
+	int ret;
+
+	assert(hws);
+
+	if (!hws->dev)
+		return -EINVAL;
+
+	ops = hwspinlock_dev_ops(hws->dev);
+	if (!ops->lock)
+		return -ENOSYS;
+
+	start = get_timer(0);
+	do {
+		ret = ops->lock(hws->dev, hws->id);
+		if (!ret)
+			return ret;
+
+		if (ops->relax)
+			ops->relax(hws->dev);
+	} while (get_timer(start) < timeout);
+
+	return -ETIMEDOUT;
+}
+
+int hwspinlock_unlock(struct hwspinlock *hws)
+{
+	const struct hwspinlock_ops *ops;
+
+	assert(hws);
+
+	if (!hws->dev)
+		return -EINVAL;
+
+	ops = hwspinlock_dev_ops(hws->dev);
+	if (!ops->unlock)
+		return -ENOSYS;
+
+	return ops->unlock(hws->dev, hws->id);
+}
+
+static int hwspinlock_post_bind(struct udevice *dev)
+{
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
+	struct hwspinlock_ops *ops = device_get_ops(dev);
+	static int reloc_done;
+
+	if (!reloc_done) {
+		if (ops->lock)
+			ops->lock += gd->reloc_off;
+		if (ops->unlock)
+			ops->unlock += gd->reloc_off;
+		if (ops->relax)
+			ops->relax += gd->reloc_off;
+
+		reloc_done++;
+	}
+#endif
+	return 0;
+}
+
+UCLASS_DRIVER(hwspinlock) = {
+	.id		= UCLASS_HWSPINLOCK,
+	.name		= "hwspinlock",
+	.post_bind	= hwspinlock_post_bind,
+};
diff --git a/drivers/hwspinlock/sandbox_hwspinlock.c b/drivers/hwspinlock/sandbox_hwspinlock.c
new file mode 100644
index 0000000..be920f5
--- /dev/null
+++ b/drivers/hwspinlock/sandbox_hwspinlock.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <hwspinlock.h>
+#include <asm/state.h>
+
+static int sandbox_lock(struct udevice *dev, int index)
+{
+	struct sandbox_state *state = state_get_current();
+
+	if (index != 0)
+		return -1;
+
+	if (state->hwspinlock)
+		return -1;
+
+	state->hwspinlock = true;
+
+	return 0;
+}
+
+static int sandbox_unlock(struct udevice *dev, int index)
+{
+	struct sandbox_state *state = state_get_current();
+
+	if (index != 0)
+		return -1;
+
+	if (!state->hwspinlock)
+		return -1;
+
+	state->hwspinlock = false;
+
+	return 0;
+}
+
+static const struct hwspinlock_ops sandbox_hwspinlock_ops = {
+	.lock = sandbox_lock,
+	.unlock = sandbox_unlock,
+};
+
+static const struct udevice_id sandbox_hwspinlock_ids[] = {
+	{ .compatible = "sandbox,hwspinlock" },
+	{}
+};
+
+U_BOOT_DRIVER(hwspinlock_sandbox) = {
+	.name = "hwspinlock_sandbox",
+	.id = UCLASS_HWSPINLOCK,
+	.of_match = sandbox_hwspinlock_ids,
+	.ops = &sandbox_hwspinlock_ops,
+};
diff --git a/drivers/hwspinlock/stm32_hwspinlock.c b/drivers/hwspinlock/stm32_hwspinlock.c
new file mode 100644
index 0000000..a32bde4
--- /dev/null
+++ b/drivers/hwspinlock/stm32_hwspinlock.c
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <hwspinlock.h>
+#include <asm/io.h>
+
+#define STM32_MUTEX_COREID	BIT(8)
+#define STM32_MUTEX_LOCK_BIT	BIT(31)
+#define STM32_MUTEX_NUM_LOCKS	32
+
+struct stm32mp1_hws_priv {
+	fdt_addr_t base;
+};
+
+static int stm32mp1_lock(struct udevice *dev, int index)
+{
+	struct stm32mp1_hws_priv *priv = dev_get_priv(dev);
+	u32 status;
+
+	if (index >= STM32_MUTEX_NUM_LOCKS)
+		return -EINVAL;
+
+	status = readl(priv->base + index * sizeof(u32));
+	if (status == (STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID))
+		return -EBUSY;
+
+	writel(STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID,
+	       priv->base + index * sizeof(u32));
+
+	status = readl(priv->base + index * sizeof(u32));
+	if (status != (STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID))
+		return -EINVAL;
+
+	return 0;
+}
+
+static int stm32mp1_unlock(struct udevice *dev, int index)
+{
+	struct stm32mp1_hws_priv *priv = dev_get_priv(dev);
+
+	if (index >= STM32_MUTEX_NUM_LOCKS)
+		return -EINVAL;
+
+	writel(STM32_MUTEX_COREID, priv->base + index * sizeof(u32));
+
+	return 0;
+}
+
+static int stm32mp1_hwspinlock_probe(struct udevice *dev)
+{
+	struct stm32mp1_hws_priv *priv = dev_get_priv(dev);
+	struct clk clk;
+	int ret;
+
+	priv->base = dev_read_addr(dev);
+	if (priv->base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	ret = clk_get_by_index(dev, 0, &clk);
+	if (ret)
+		return ret;
+
+	ret = clk_enable(&clk);
+	if (ret)
+		clk_free(&clk);
+
+	return ret;
+}
+
+static const struct hwspinlock_ops stm32mp1_hwspinlock_ops = {
+	.lock = stm32mp1_lock,
+	.unlock = stm32mp1_unlock,
+};
+
+static const struct udevice_id stm32mp1_hwspinlock_ids[] = {
+	{ .compatible = "st,stm32-hwspinlock" },
+	{}
+};
+
+U_BOOT_DRIVER(hwspinlock_stm32mp1) = {
+	.name = "hwspinlock_stm32mp1",
+	.id = UCLASS_HWSPINLOCK,
+	.of_match = stm32mp1_hwspinlock_ids,
+	.ops = &stm32mp1_hwspinlock_ops,
+	.probe = stm32mp1_hwspinlock_probe,
+	.priv_auto_alloc_size = sizeof(struct stm32mp1_hws_priv),
+};
diff --git a/drivers/mmc/mmc_spi.c b/drivers/mmc/mmc_spi.c
index a9d95fb..4f57990 100644
--- a/drivers/mmc/mmc_spi.c
+++ b/drivers/mmc/mmc_spi.c
@@ -10,7 +10,7 @@
 #include <part.h>
 #include <mmc.h>
 #include <spi.h>
-#include <crc.h>
+#include <u-boot/crc.h>
 #include <linux/crc7.h>
 #include <asm/byteorder.h>
 
diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index 37749e0..a0abb23 100644
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -8,7 +8,7 @@
 #include <common.h>
 #include <dm.h>
 #include <phy.h>
-#include <crc.h>
+#include <u-boot/crc.h>
 #include <malloc.h>
 #include <asm/byteorder.h>
 #include <fs.h>
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 14d82b9..3921e39 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -155,4 +155,13 @@
 
 	  This PHY is found on qualcomm dragonboard410c development board.
 
+config OMAP_USB2_PHY
+	bool "Support OMAP's USB2 PHY"
+	depends on PHY
+	depends on SYSCON
+	help
+	  Support for the OMAP's USB2 PHY.
+
+	  This PHY is found on OMAP devices supporting USB2.
+
 endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 8030d59..53dd5bd 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -17,3 +17,4 @@
 obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o
 obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o meson-gxl-usb3.o
 obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o
+obj-$(CONFIG_OMAP_USB2_PHY) += omap-usb2-phy.o
diff --git a/drivers/phy/omap-usb2-phy.c b/drivers/phy/omap-usb2-phy.c
new file mode 100644
index 0000000..fd20e8c
--- /dev/null
+++ b/drivers/phy/omap-usb2-phy.c
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * OMAP USB2 PHY LAYER
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
+ * Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <syscon.h>
+
+#define OMAP_USB2_CALIBRATE_FALSE_DISCONNECT	BIT(0)
+
+#define OMAP_DEV_PHY_PD		BIT(0)
+#define OMAP_USB2_PHY_PD	BIT(28)
+
+#define USB2PHY_DISCON_BYP_LATCH	BIT(31)
+#define USB2PHY_ANA_CONFIG1		(0x4c)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct omap_usb2_phy {
+	struct regmap *pwr_regmap;
+	ulong flags;
+	void *phy_base;
+	u32 pwr_reg_offset;
+};
+
+struct usb_phy_data {
+	const char *label;
+	u8 flags;
+	u32 mask;
+	u32 power_on;
+	u32 power_off;
+};
+
+static const struct usb_phy_data omap5_usb2_data = {
+	.label = "omap5_usb2",
+	.flags = 0,
+	.mask = OMAP_DEV_PHY_PD,
+	.power_off = OMAP_DEV_PHY_PD,
+};
+
+static const struct usb_phy_data dra7x_usb2_data = {
+	.label = "dra7x_usb2",
+	.flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
+	.mask = OMAP_DEV_PHY_PD,
+	.power_off = OMAP_DEV_PHY_PD,
+};
+
+static const struct usb_phy_data dra7x_usb2_phy2_data = {
+	.label = "dra7x_usb2_phy2",
+	.flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
+	.mask = OMAP_USB2_PHY_PD,
+	.power_off = OMAP_USB2_PHY_PD,
+};
+
+static const struct udevice_id omap_usb2_id_table[] = {
+	{
+		.compatible = "ti,omap5-usb2",
+		.data = (ulong)&omap5_usb2_data,
+	},
+	{
+		.compatible = "ti,dra7x-usb2",
+		.data = (ulong)&dra7x_usb2_data,
+	},
+	{
+		.compatible = "ti,dra7x-usb2-phy2",
+		.data = (ulong)&dra7x_usb2_phy2_data,
+	},
+	{},
+};
+
+static int omap_usb_phy_power(struct phy *usb_phy, bool on)
+{
+	struct udevice *dev = usb_phy->dev;
+	const struct usb_phy_data *data;
+	const struct omap_usb2_phy *phy = dev_get_priv(dev);
+	u32 val;
+	int rc;
+
+	data = (const struct usb_phy_data *)dev_get_driver_data(dev);
+	if (!data)
+		return -EINVAL;
+
+	rc = regmap_read(phy->pwr_regmap, phy->pwr_reg_offset, &val);
+	if (rc)
+		return rc;
+	val &= ~data->mask;
+	if (on)
+		val |= data->power_on;
+	else
+		val |= data->power_off;
+	rc = regmap_write(phy->pwr_regmap, phy->pwr_reg_offset, val);
+	if (rc)
+		return rc;
+
+	return 0;
+}
+
+static int omap_usb2_phy_init(struct phy *usb_phy)
+{
+	struct udevice *dev = usb_phy->dev;
+	struct omap_usb2_phy *priv = dev_get_priv(dev);
+	u32 val;
+
+	if (priv->flags & OMAP_USB2_CALIBRATE_FALSE_DISCONNECT) {
+		/*
+		 *
+		 * Reduce the sensitivity of internal PHY by enabling the
+		 * DISCON_BYP_LATCH of the USB2PHY_ANA_CONFIG1 register. This
+		 * resolves issues with certain devices which can otherwise
+		 * be prone to false disconnects.
+		 *
+		 */
+		val = readl(priv->phy_base + USB2PHY_ANA_CONFIG1);
+		val |= USB2PHY_DISCON_BYP_LATCH;
+		writel(val, priv->phy_base + USB2PHY_ANA_CONFIG1);
+	}
+
+	return 0;
+}
+
+static int omap_usb2_phy_power_on(struct phy *usb_phy)
+{
+	return omap_usb_phy_power(usb_phy, true);
+}
+
+static int omap_usb2_phy_power_off(struct phy *usb_phy)
+{
+	return omap_usb_phy_power(usb_phy, false);
+}
+
+static int omap_usb2_phy_exit(struct phy *usb_phy)
+{
+	return omap_usb_phy_power(usb_phy, false);
+}
+
+struct phy_ops omap_usb2_phy_ops = {
+	.init = omap_usb2_phy_init,
+	.power_on = omap_usb2_phy_power_on,
+	.power_off = omap_usb2_phy_power_off,
+	.exit = omap_usb2_phy_exit,
+};
+
+int omap_usb2_phy_probe(struct udevice *dev)
+{
+	int rc;
+	struct regmap *regmap;
+	struct omap_usb2_phy *priv = dev_get_priv(dev);
+	const struct usb_phy_data *data;
+	u32 tmp[2];
+
+	data = (const struct usb_phy_data *)dev_get_driver_data(dev);
+	if (!data)
+		return -EINVAL;
+
+	if (data->flags & OMAP_USB2_CALIBRATE_FALSE_DISCONNECT) {
+		u32 base = dev_read_addr(dev);
+
+		if (base == FDT_ADDR_T_NONE)
+			return -EINVAL;
+		priv->phy_base = (void *)base;
+		priv->flags |= OMAP_USB2_CALIBRATE_FALSE_DISCONNECT;
+	}
+
+	regmap = syscon_regmap_lookup_by_phandle(dev, "syscon-phy-power");
+	if (IS_ERR(regmap)) {
+		printf("can't get regmap (err %ld)\n", PTR_ERR(regmap));
+		return PTR_ERR(regmap);
+	}
+	priv->pwr_regmap = regmap;
+
+	rc =  dev_read_u32_array(dev, "syscon-phy-power", tmp, 2);
+	if (rc) {
+		printf("couldn't get power reg. offset (err %d)\n", rc);
+		return rc;
+	}
+	priv->pwr_reg_offset = tmp[1];
+
+	return 0;
+}
+
+U_BOOT_DRIVER(omap_usb2_phy) = {
+	.name = "omap_usb2_phy",
+	.id = UCLASS_PHY,
+	.of_match = omap_usb2_id_table,
+	.probe = omap_usb2_phy_probe,
+	.ops = &omap_usb2_phy_ops,
+	.priv_auto_alloc_size = sizeof(struct omap_usb2_phy),
+};
diff --git a/drivers/phy/ti-pipe3-phy.c b/drivers/phy/ti-pipe3-phy.c
index b22bbaf..e7e78e3 100644
--- a/drivers/phy/ti-pipe3-phy.c
+++ b/drivers/phy/ti-pipe3-phy.c
@@ -141,7 +141,7 @@
 	omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);
 
 	val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);
-	val &= ~PLL_SELFREQDCO_MASK;
+	val &= ~(PLL_SELFREQDCO_MASK | PLL_IDLE);
 	val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
 	omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);
 
@@ -265,10 +265,13 @@
 		return -EBUSY;
 	}
 
-	val = readl(pipe3->pll_reset_reg);
-	writel(val | SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
-	mdelay(1);
-	writel(val & ~SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
+	if (pipe3->pll_reset_reg) {
+		val = readl(pipe3->pll_reset_reg);
+		writel(val | SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
+		mdelay(1);
+		writel(val & ~SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
+	}
+
 	return 0;
 }
 
@@ -331,9 +334,11 @@
 	if (!pipe3->power_reg)
 		return -EINVAL;
 
-	pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset");
-	if (!pipe3->pll_reset_reg)
-		return -EINVAL;
+	if (device_is_compatible(dev, "ti,phy-pipe3-sata")) {
+		pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset");
+		if (!pipe3->pll_reset_reg)
+			return -EINVAL;
+	}
 
 	pipe3->dpll_map = (struct pipe3_dpll_map *)dev_get_driver_data(dev);
 
@@ -350,8 +355,19 @@
 	{ },                                    /* Terminator */
 };
 
+static struct pipe3_dpll_map dpll_map_usb[] = {
+	{12000000, {1250, 5, 4, 20, 0} },	/* 12 MHz */
+	{16800000, {3125, 20, 4, 20, 0} },	/* 16.8 MHz */
+	{19200000, {1172, 8, 4, 20, 65537} },	/* 19.2 MHz */
+	{20000000, {1000, 7, 4, 10, 0} },	/* 20 MHz */
+	{26000000, {1250, 12, 4, 20, 0} },	/* 26 MHz */
+	{38400000, {3125, 47, 4, 20, 92843} },	/* 38.4 MHz */
+	{ },					/* Terminator */
+};
+
 static const struct udevice_id pipe3_phy_ids[] = {
 	{ .compatible = "ti,phy-pipe3-sata", .data = (ulong)&dpll_map_sata },
+	{ .compatible = "ti,omap-usb3", .data = (ulong)&dpll_map_usb},
 	{ }
 };
 
diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c b/drivers/pinctrl/meson/pinctrl-meson-axg.c
index a54fbce..3bbbe81 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-axg.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c
@@ -14,7 +14,7 @@
 
 #include "pinctrl-meson-axg.h"
 
-#define EE_OFF	14
+#define EE_OFF	15
 
 /* emmc */
 static const unsigned int emmc_nand_d0_pins[] = {BOOT_0};
@@ -893,17 +893,17 @@
 };
 
 static struct meson_bank meson_axg_periphs_banks[] = {
-	/*   name    first      last      pullen  pull    dir     out     in  */
-	BANK("Z",    GPIOZ_0,	GPIOZ_10, 3,  0,  3,  0,  9,  0,  10, 0,  11, 0),
-	BANK("BOOT", BOOT_0,	BOOT_14,  4,  0,  4,  0,  12, 0,  13, 0,  14, 0),
-	BANK("A",    GPIOA_0,	GPIOA_20, 0,  0,  0,  0,  0,  0,  1,  0,  2,  0),
-	BANK("X",    GPIOX_0,	GPIOX_22, 2,  0,  2,  0,  6,  0,  7,  0,  8,  0),
-	BANK("Y",    GPIOY_0,	GPIOY_15, 1,  0,  1,  0,  3,  0,  4,  0,  5,  0),
+	/*   name    first                      last                    pullen  pull    dir     out     in  */
+	BANK("Z",    PIN(GPIOZ_0, EE_OFF),	PIN(GPIOZ_10, EE_OFF), 3,  0,  3,  0,  9,  0,  10, 0,  11, 0),
+	BANK("BOOT", PIN(BOOT_0, EE_OFF),	PIN(BOOT_14, EE_OFF),  4,  0,  4,  0,  12, 0,  13, 0,  14, 0),
+	BANK("A",    PIN(GPIOA_0, EE_OFF),	PIN(GPIOA_20, EE_OFF), 0,  0,  0,  0,  0,  0,  1,  0,  2,  0),
+	BANK("X",    PIN(GPIOX_0, EE_OFF),	PIN(GPIOX_22, EE_OFF), 2,  0,  2,  0,  6,  0,  7,  0,  8,  0),
+	BANK("Y",    PIN(GPIOY_0, EE_OFF),	PIN(GPIOY_15, EE_OFF), 1,  0,  1,  0,  3,  0,  4,  0,  5,  0),
 };
 
 static struct meson_bank meson_axg_aobus_banks[] = {
-	/*   name    first      last       pullen  pull    dir     out     in  */
-	BANK("AO",   GPIOAO_0,  GPIOAO_13, 0,  16,  0, 0,  0,  0,  0, 16,  1,  0),
+	/*   name    first              last              pullen  pull    dir     out     in  */
+	BANK("AO",   PIN(GPIOAO_0, 0),  PIN(GPIOAO_13, 0), 0,  16,  0, 0,  0,  0,  0, 16,  1,  0),
 };
 
 static struct meson_pmx_bank meson_axg_periphs_pmx_banks[] = {
@@ -931,11 +931,11 @@
 
 struct meson_pinctrl_data meson_axg_periphs_pinctrl_data = {
 	.name		= "periphs-banks",
-	.pin_base	= 11,
+	.pin_base	= 15,
 	.groups		= meson_axg_periphs_groups,
 	.funcs		= meson_axg_periphs_functions,
 	.banks		= meson_axg_periphs_banks,
-	.num_pins	= 100,
+	.num_pins	= 86,
 	.num_groups	= ARRAY_SIZE(meson_axg_periphs_groups),
 	.num_funcs	= ARRAY_SIZE(meson_axg_periphs_functions),
 	.num_banks	= ARRAY_SIZE(meson_axg_periphs_banks),
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c
index 0bd6152..b539749 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -136,7 +136,7 @@
 	if (ret)
 		return ret;
 
-	clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), 1);
+	setbits_le32(priv->reg_gpio + reg, BIT(bit));
 
 	return 0;
 }
@@ -152,7 +152,7 @@
 	if (ret)
 		return ret;
 
-	clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), 0);
+	clrbits_le32(priv->reg_gpio + reg, BIT(bit));
 
 	ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_OUT, &reg, &bit);
 	if (ret)
diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c
index 6d4117d..24affe0 100644
--- a/drivers/pinctrl/pinctrl_stm32.c
+++ b/drivers/pinctrl/pinctrl_stm32.c
@@ -1,6 +1,7 @@
 #include <common.h>
 #include <dm.h>
 #include <dm/pinctrl.h>
+#include <hwspinlock.h>
 #include <asm/arch/gpio.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
@@ -14,8 +15,8 @@
 #define OTYPE_MSK			1
 #define AFR_MASK			0xF
 
-#ifndef CONFIG_SPL_BUILD
 struct stm32_pinctrl_priv {
+	struct hwspinlock hws;
 	int pinctrl_ngpios;
 	struct list_head gpio_dev;
 };
@@ -25,7 +26,7 @@
 	struct list_head list;
 };
 
-#define MAX_PIN_PER_BANK		16
+#ifndef CONFIG_SPL_BUILD
 
 static char pin_name[PINNAME_SIZE];
 #define PINMUX_MODE_COUNT		5
@@ -51,6 +52,39 @@
 	return af;
 }
 
+static int stm32_populate_gpio_dev_list(struct udevice *dev)
+{
+	struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
+	struct udevice *gpio_dev;
+	struct udevice *child;
+	struct stm32_gpio_bank *gpio_bank;
+	int ret;
+
+	/*
+	 * parse pin-controller sub-nodes (ie gpio bank nodes) and fill
+	 * a list with all gpio device reference which belongs to the
+	 * current pin-controller. This list is used to find pin_name and
+	 * pin muxing
+	 */
+	list_for_each_entry(child, &dev->child_head, sibling_node) {
+		ret = uclass_get_device_by_name(UCLASS_GPIO, child->name,
+						&gpio_dev);
+		if (ret < 0)
+			continue;
+
+		gpio_bank = malloc(sizeof(*gpio_bank));
+		if (!gpio_bank) {
+			dev_err(dev, "Not enough memory\n");
+			return -ENOMEM;
+		}
+
+		gpio_bank->gpio_dev = gpio_dev;
+		list_add_tail(&gpio_bank->list, &priv->gpio_dev);
+	}
+
+	return 0;
+}
+
 static int stm32_pinctrl_get_pins_count(struct udevice *dev)
 {
 	struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
@@ -64,6 +98,8 @@
 	if (priv->pinctrl_ngpios)
 		return priv->pinctrl_ngpios;
 
+	if (list_empty(&priv->gpio_dev))
+		stm32_populate_gpio_dev_list(dev);
 	/*
 	 * walk through all banks to retrieve the pin-controller
 	 * pins number
@@ -78,22 +114,34 @@
 }
 
 static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
-						  unsigned int selector)
+						  unsigned int selector,
+						  unsigned int *idx)
 {
 	struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
 	struct stm32_gpio_bank *gpio_bank;
 	struct gpio_dev_priv *uc_priv;
-	int first_pin = 0;
+	int pin_count = 0;
+
+	if (list_empty(&priv->gpio_dev))
+		stm32_populate_gpio_dev_list(dev);
 
 	/* look up for the bank which owns the requested pin */
 	list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
 		uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
 
-		if (selector < (first_pin + uc_priv->gpio_count))
-			/* we found the bank */
-			return gpio_bank->gpio_dev;
+		if (selector < (pin_count + uc_priv->gpio_count)) {
+			/*
+			 * we found the bank, convert pin selector to
+			 * gpio bank index
+			 */
+			*idx = stm32_offset_to_index(gpio_bank->gpio_dev,
+						     selector - pin_count);
+			if (*idx < 0)
+				return NULL;
 
-		first_pin += uc_priv->gpio_count;
+			return gpio_bank->gpio_dev;
+		}
+		pin_count += uc_priv->gpio_count;
 	}
 
 	return NULL;
@@ -104,9 +152,10 @@
 {
 	struct gpio_dev_priv *uc_priv;
 	struct udevice *gpio_dev;
+	unsigned int gpio_idx;
 
 	/* look up for the bank which owns the requested pin */
-	gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector);
+	gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
 	if (!gpio_dev) {
 		snprintf(pin_name, PINNAME_SIZE, "Error");
 	} else {
@@ -114,7 +163,7 @@
 
 		snprintf(pin_name, PINNAME_SIZE, "%s%d",
 			 uc_priv->bank_name,
-			 selector % MAX_PIN_PER_BANK);
+			 gpio_idx);
 	}
 
 	return pin_name;
@@ -127,23 +176,21 @@
 {
 	struct udevice *gpio_dev;
 	const char *label;
-	int gpio_pin;
 	int mode;
 	int af_num;
+	unsigned int gpio_idx;
 
 	/* look up for the bank which owns the requested pin */
-	gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector);
+	gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
 
 	if (!gpio_dev)
 		return -ENODEV;
 
-	/* translate pin-controller pin number to gpio pin number */
-	gpio_pin = selector % MAX_PIN_PER_BANK;
+	mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label);
 
-	mode = gpio_get_raw_function(gpio_dev, gpio_pin, &label);
+	dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n",
+		selector, gpio_idx, mode);
 
-	dev_dbg(dev, "selector = %d gpio_pin = %d mode = %d\n",
-		selector, gpio_pin, mode);
 
 	switch (mode) {
 	case GPIOF_UNKNOWN:
@@ -153,7 +200,7 @@
 		snprintf(buf, size, "%s", pinmux_mode[mode]);
 		break;
 	case GPIOF_FUNC:
-		af_num = stm32_pinctrl_get_af(gpio_dev, gpio_pin);
+		af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
 		snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num);
 		break;
 	case GPIOF_OUTPUT:
@@ -166,53 +213,44 @@
 	return 0;
 }
 
+#endif
+
 int stm32_pinctrl_probe(struct udevice *dev)
 {
 	struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
-	struct udevice *gpio_dev;
-	struct udevice *child;
-	struct stm32_gpio_bank *gpio_bank;
 	int ret;
 
 	INIT_LIST_HEAD(&priv->gpio_dev);
 
-	/*
-	 * parse pin-controller sub-nodes (ie gpio bank nodes) and fill
-	 * a list with all gpio device reference which belongs to the
-	 * current pin-controller. This list is used to find pin_name and
-	 * pin muxing
-	 */
-	list_for_each_entry(child, &dev->child_head, sibling_node) {
-		ret = uclass_get_device_by_name(UCLASS_GPIO, child->name,
-						&gpio_dev);
-		if (ret < 0)
-			continue;
-
-		gpio_bank = malloc(sizeof(*gpio_bank));
-		if (!gpio_bank) {
-			dev_err(dev, "Not enough memory\n");
-			return -ENOMEM;
-		}
-
-		gpio_bank->gpio_dev = gpio_dev;
-		list_add_tail(&gpio_bank->list, &priv->gpio_dev);
-	}
+	/* hwspinlock property is optional, just log the error */
+	ret = hwspinlock_get_by_index(dev, 0, &priv->hws);
+	if (ret)
+		debug("%s: hwspinlock_get_by_index may have failed (%d)\n",
+		      __func__, ret);
 
 	return 0;
 }
-#endif
 
 static int stm32_gpio_config(struct gpio_desc *desc,
 			     const struct stm32_gpio_ctl *ctl)
 {
 	struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
 	struct stm32_gpio_regs *regs = priv->regs;
+	struct stm32_pinctrl_priv *ctrl_priv;
+	int ret;
 	u32 index;
 
 	if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
 	    ctl->pupd > 2 || ctl->speed > 3)
 		return -EINVAL;
 
+	ctrl_priv = dev_get_priv(dev_get_parent(desc->dev));
+	ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10);
+	if (ret == -ETIME) {
+		dev_err(desc->dev, "HWSpinlock timeout\n");
+		return ret;
+	}
+
 	index = (desc->offset & 0x07) * 4;
 	clrsetbits_le32(&regs->afr[desc->offset >> 3], AFR_MASK << index,
 			ctl->af << index);
@@ -227,6 +265,8 @@
 	index = desc->offset;
 	clrsetbits_le32(&regs->otyper, OTYPE_MSK << index, ctl->otype << index);
 
+	hwspinlock_unlock(&ctrl_priv->hws);
+
 	return 0;
 }
 
@@ -393,8 +433,6 @@
 	.of_match		= stm32_pinctrl_ids,
 	.ops			= &stm32_pinctrl_ops,
 	.bind			= dm_scan_fdt_dev,
-#ifndef CONFIG_SPL_BUILD
 	.probe			= stm32_pinctrl_probe,
 	.priv_auto_alloc_size	= sizeof(struct stm32_pinctrl_priv),
-#endif
 };
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 1a38524..9495dca 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -197,6 +197,49 @@
 	On A83T / H8 boards aldo3 is AVCC, VCC-PL, and VCC-LED, and should be
 	3.0V.
 
+choice
+	prompt "axp pmic (a)ldo3 voltage rate control"
+	depends on AXP209_POWER
+	default AXP_ALDO3_VOLT_SLOPE_NONE
+	---help---
+	The AXP can slowly ramp up voltage to reduce the inrush current when
+	changing voltages.
+	Note, this does not apply when enabling/disabling LDO3. See
+	"axp pmic (a)ldo3 inrush quirk" below to enable a slew rate to limit
+	inrush current on broken board designs.
+
+config AXP_ALDO3_VOLT_SLOPE_NONE
+	bool "No voltage slope"
+	---help---
+	Tries to reach the next voltage setting near instantaneously. Measurements
+	indicate that this is about 0.0167 V/uS.
+
+config AXP_ALDO3_VOLT_SLOPE_16
+	bool "1.6 mV per uS"
+	---help---
+	Increases the voltage by 1.6 mV per uS until the final voltage has
+	been reached. Note that the scaling is in 25 mV steps and thus
+	the slew rate in reality is about 25 mV/31.250 uS.
+
+config AXP_ALDO3_VOLT_SLOPE_08
+	bool "0.8 mV per uS"
+	---help---
+	Increases the voltage by 0.8 mV per uS until the final voltage has
+	been reached. Note that the scaling is in 25 mV steps however and thus
+	the slew rate in reality is about 25 mV/15.625 uS.
+	This is the slowest supported rate.
+
+endchoice
+
+config AXP_ALDO3_INRUSH_QUIRK
+	bool "axp pmic (a)ldo3 inrush quirk"
+	depends on AXP209_POWER
+	default n
+	---help---
+	The reference design denotes a value of 4.7 uF for the output capacitor
+	of LDO3. Some boards have too high capacitance causing 	an inrush current
+	and resulting an AXP209 shutdown.
+
 config AXP_ALDO4_VOLT
 	int "axp pmic (a)ldo4 voltage"
 	depends on AXP209_POWER
diff --git a/drivers/power/axp209.c b/drivers/power/axp209.c
index 6de5ec6..67b4209 100644
--- a/drivers/power/axp209.c
+++ b/drivers/power/axp209.c
@@ -9,6 +9,16 @@
 #include <asm/arch/pmic_bus.h>
 #include <axp_pmic.h>
 
+#ifdef CONFIG_AXP_ALDO3_VOLT_SLOPE_08
+#  define AXP209_VRC_SLOPE AXP209_VRC_LDO3_800uV_uS
+#endif
+#ifdef CONFIG_AXP_ALDO3_VOLT_SLOPE_16
+#  define AXP209_VRC_SLOPE AXP209_VRC_LDO3_1600uV_uS
+#endif
+#if defined CONFIG_AXP_ALDO3_VOLT_SLOPE_NONE || !defined AXP209_VRC_SLOPE
+#  define AXP209_VRC_SLOPE 0x00
+#endif
+
 static u8 axp209_mvolt_to_cfg(int mvolt, int min, int max, int div)
 {
 	if (mvolt < min)
@@ -81,8 +91,7 @@
 	if (rc)
 		return rc;
 
-	/* LDO2 configuration is in upper 4 bits */
-	reg = (reg & 0x0f) | (cfg << 4);
+	reg |= AXP209_LDO24_LDO2_SET(reg, cfg);
 	rc = pmic_bus_write(AXP209_LDO24_VOLTAGE, reg);
 	if (rc)
 		return rc;
@@ -99,10 +108,49 @@
 		return pmic_bus_clrbits(AXP209_OUTPUT_CTRL,
 					AXP209_OUTPUT_CTRL_LDO3);
 
+	/*
+	 * Some boards have trouble reaching the target voltage without causing
+	 * great inrush currents. To prevent this, boards can enable a certain
+	 * slope to ramp up voltage. Note, this only works when changing an
+	 * already active power rail. When toggling power on, the AXP ramps up
+	 * steeply at 0.0167 V/uS.
+	 */
+	rc = pmic_bus_read(AXP209_VRC_DCDC2_LDO3, &cfg);
+	cfg = AXP209_VRC_LDO3_SLOPE_SET(cfg, AXP209_VRC_SLOPE);
+	rc |= pmic_bus_write(AXP209_VRC_DCDC2_LDO3, cfg);
+
+	if (rc)
+		return rc;
+
+#ifdef CONFIG_AXP_ALDO3_INRUSH_QUIRK
+	/*
+	 * On some boards, LDO3 has a too big capacitor installed. When
+	 * turning on LDO3, this causes the AXP209 to shutdown on
+	 * voltages over 1.9 volt. As a workaround, we enable LDO3
+	 * first with the lowest possible voltage. If this still causes
+	 * high inrush currents, the voltage slope should be increased.
+	 */
+	rc = pmic_bus_read(AXP209_OUTPUT_CTRL, &cfg);
+	if (rc)
+		return rc;
+
+	if (!(cfg & AXP209_OUTPUT_CTRL_LDO3)) {
+		rc = pmic_bus_write(AXP209_LDO3_VOLTAGE, 0x0); /* 0.7 Volt */
+		mdelay(1);
+		rc |= pmic_bus_setbits(AXP209_OUTPUT_CTRL,
+				       AXP209_OUTPUT_CTRL_LDO3);
+
-	if (mvolt == -1)
-		cfg = 0x80;	/* determined by LDO3IN pin */
-	else
+		if (rc)
+			return rc;
+	}
+#endif
+
+	if (mvolt == -1) {
+		cfg = AXP209_LDO3_VOLTAGE_FROM_LDO3IN;
+	} else {
 		cfg = axp209_mvolt_to_cfg(mvolt, 700, 3500, 25);
+		cfg = AXP209_LDO3_VOLTAGE_SET(cfg);
+	}
 
 	rc = pmic_bus_write(AXP209_LDO3_VOLTAGE, cfg);
 	if (rc)
@@ -131,8 +179,7 @@
 	if (rc)
 		return rc;
 
-	/* LDO4 configuration is in lower 4 bits */
-	reg = (reg & 0xf0) | (cfg << 0);
+	reg |= AXP209_LDO24_LDO4_SET(reg, cfg);
 	rc = pmic_bus_write(AXP209_LDO24_VOLTAGE, reg);
 	if (rc)
 		return rc;
@@ -153,10 +200,7 @@
 	if (rc)
 		return rc;
 
-	/* Low 4 bits is chip version */
-	ver &= 0x0f;
-
-	if (ver != 0x1)
+	if ((ver & AXP209_CHIP_VERSION_MASK) != 0x1)
 		return -EINVAL;
 
 	/* Mask all interrupts */
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 3bcc61e..6252dd8 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -506,16 +506,10 @@
 
 config BCM6345_SERIAL
 	bool "Support for BCM6345 UART"
-	depends on DM_SERIAL && ARCH_BMIPS
+	depends on DM_SERIAL
 	help
 	  Select this to enable UART on BCM6345 SoCs.
 
-config BCM6858_SERIAL
-	bool "Support for BCM6858 UART"
-	depends on DM_SERIAL && ARCH_BCM6858
-	help
-	  Select this to enable UART on BCM6358 SoCs.
-
 config FSL_LINFLEXUART
 	bool "Freescale Linflex UART support"
 	depends on DM_SERIAL
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index b6377b1..2f8d065 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -35,7 +35,6 @@
 obj-$(CONFIG_ARM_DCC) += arm_dcc.o
 obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
 obj-$(CONFIG_BCM6345_SERIAL) += serial_bcm6345.o
-obj-$(CONFIG_BCM6858_SERIAL) += serial_bcm6858.o
 obj-$(CONFIG_EFI_APP) += serial_efi.o
 obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
 obj-$(CONFIG_MCFUART) += mcfuart.o
diff --git a/drivers/serial/serial_bcm6345.c b/drivers/serial/serial_bcm6345.c
index a0e709a..9ad8c77 100644
--- a/drivers/serial/serial_bcm6345.c
+++ b/drivers/serial/serial_bcm6345.c
@@ -89,26 +89,26 @@
 /* enable rx & tx operation on uart */
 static void bcm6345_serial_enable(void __iomem *base)
 {
-	setbits_be32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK |
-		     UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
+	setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK |
+		   UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
 }
 
 /* disable rx & tx operation on uart */
 static void bcm6345_serial_disable(void __iomem *base)
 {
-	clrbits_be32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK |
-		     UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
+	clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK |
+		   UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
 }
 
 /* clear all unread data in rx fifo and unsent data in tx fifo */
 static void bcm6345_serial_flush(void __iomem *base)
 {
 	/* empty rx and tx fifo */
-	setbits_be32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK |
-		     UART_CTL_RSTTXFIFO_MASK);
+	setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK |
+		   UART_CTL_RSTTXFIFO_MASK);
 
 	/* read any pending char to make sure all irq status are cleared */
-	readl_be(base + UART_FIFO_REG);
+	readl(base + UART_FIFO_REG);
 }
 
 static int bcm6345_serial_init(void __iomem *base, ulong clk, u32 baudrate)
@@ -120,40 +120,40 @@
 	bcm6345_serial_flush(base);
 
 	/* set uart control config */
-	clrsetbits_be32(base + UART_CTL_REG,
-			/* clear rx timeout */
-			UART_CTL_RXTIMEOUT_MASK |
-			/* clear stop bits */
-			UART_CTL_STOPBITS_MASK |
-			/* clear bits per symbol */
-			UART_CTL_BITSPERSYM_MASK |
-			/* clear xmit break */
-			UART_CTL_XMITBRK_MASK |
-			/* clear reserved bit */
-			UART_CTL_RSVD_MASK |
-			/* disable parity */
-			UART_CTL_RXPAREN_MASK |
-			UART_CTL_TXPAREN_MASK |
-			/* disable loopback */
-			UART_CTL_LOOPBACK_MASK,
-			/* set timeout to 5 */
-			UART_CTL_RXTIMEOUT_5 |
-			/* set 8 bits/symbol */
-			UART_CTL_BITSPERSYM_8 |
-			/* set 1 stop bit */
-			UART_CTL_STOPBITS_1 |
-			/* set parity to even */
-			UART_CTL_RXPAREVEN_MASK |
-			UART_CTL_TXPAREVEN_MASK);
+	clrsetbits_32(base + UART_CTL_REG,
+		      /* clear rx timeout */
+		      UART_CTL_RXTIMEOUT_MASK |
+		      /* clear stop bits */
+		      UART_CTL_STOPBITS_MASK |
+		      /* clear bits per symbol */
+		      UART_CTL_BITSPERSYM_MASK |
+		      /* clear xmit break */
+		      UART_CTL_XMITBRK_MASK |
+		      /* clear reserved bit */
+		      UART_CTL_RSVD_MASK |
+		      /* disable parity */
+		      UART_CTL_RXPAREN_MASK |
+		      UART_CTL_TXPAREN_MASK |
+		      /* disable loopback */
+		      UART_CTL_LOOPBACK_MASK,
+		      /* set timeout to 5 */
+		      UART_CTL_RXTIMEOUT_5 |
+		      /* set 8 bits/symbol */
+		      UART_CTL_BITSPERSYM_8 |
+		      /* set 1 stop bit */
+		      UART_CTL_STOPBITS_1 |
+		      /* set parity to even */
+		      UART_CTL_RXPAREVEN_MASK |
+		      UART_CTL_TXPAREVEN_MASK);
 
 	/* set uart fifo config */
-	clrsetbits_be32(base + UART_FIFO_CFG_REG,
-			/* clear fifo config */
-			UART_FIFO_CFG_RX_MASK |
-			UART_FIFO_CFG_TX_MASK,
-			/* set fifo config to 4 */
-			UART_FIFO_CFG_RX_4 |
-			UART_FIFO_CFG_TX_4);
+	clrsetbits_32(base + UART_FIFO_CFG_REG,
+		      /* clear fifo config */
+		      UART_FIFO_CFG_RX_MASK |
+		      UART_FIFO_CFG_TX_MASK,
+		      /* set fifo config to 4 */
+		      UART_FIFO_CFG_RX_4 |
+		      UART_FIFO_CFG_TX_4);
 
 	/* set baud rate */
 	val = ((clk / baudrate) >> 4);
@@ -161,10 +161,10 @@
 		val = (val >> 1);
 	else
 		val = (val >> 1) - 1;
-	writel_be(val, base + UART_BAUD_REG);
+	writel(val, base + UART_BAUD_REG);
 
 	/* clear interrupts */
-	writel_be(0, base + UART_IR_REG);
+	writel(0, base + UART_IR_REG);
 
 	/* enable uart */
 	bcm6345_serial_enable(base);
@@ -175,7 +175,7 @@
 static int bcm6345_serial_pending(struct udevice *dev, bool input)
 {
 	struct bcm6345_serial_priv *priv = dev_get_priv(dev);
-	u32 val = readl_be(priv->base + UART_IR_REG);
+	u32 val = readl(priv->base + UART_IR_REG);
 
 	if (input)
 		return !!(val & UART_IR_STAT(UART_IR_RXNOTEMPTY));
@@ -195,11 +195,11 @@
 	struct bcm6345_serial_priv *priv = dev_get_priv(dev);
 	u32 val;
 
-	val = readl_be(priv->base + UART_IR_REG);
+	val = readl(priv->base + UART_IR_REG);
 	if (!(val & UART_IR_STAT(UART_IR_TXEMPTY)))
 		return -EAGAIN;
 
-	writel_be(ch, priv->base + UART_FIFO_REG);
+	writel(ch, priv->base + UART_FIFO_REG);
 
 	return 0;
 }
@@ -209,14 +209,13 @@
 	struct bcm6345_serial_priv *priv = dev_get_priv(dev);
 	u32 val;
 
-	val = readl_be(priv->base + UART_IR_REG);
+	val = readl(priv->base + UART_IR_REG);
 	if (val & UART_IR_STAT(UART_IR_RXOVER))
-		setbits_be32(priv->base + UART_CTL_REG,
-			     UART_CTL_RSTRXFIFO_MASK);
+		setbits_32(priv->base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK);
 	if (!(val & UART_IR_STAT(UART_IR_RXNOTEMPTY)))
 		return -EAGAIN;
 
-	val = readl_be(priv->base + UART_FIFO_REG);
+	val = readl(priv->base + UART_FIFO_REG);
 	if (val & UART_FIFO_ANYERR_MASK)
 		return -EAGAIN;
 
@@ -277,7 +276,7 @@
 static inline void wait_xfered(void __iomem *base)
 {
 	do {
-		u32 val = readl_be(base + UART_IR_REG);
+		u32 val = readl(base + UART_IR_REG);
 		if (val & UART_IR_STAT(UART_IR_TXEMPTY))
 			break;
 	} while (1);
@@ -288,7 +287,7 @@
 	void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
 
 	wait_xfered(base);
-	writel_be(ch, base + UART_FIFO_REG);
+	writel(ch, base + UART_FIFO_REG);
 	wait_xfered(base);
 }
 
diff --git a/drivers/serial/serial_bcm6858.c b/drivers/serial/serial_bcm6858.c
deleted file mode 100644
index 8aa3705..0000000
--- a/drivers/serial/serial_bcm6858.c
+++ /dev/null
@@ -1,300 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
- *
- * Derived from linux/drivers/tty/serial/bcm63xx_uart.c:
- *	Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
- * Derived from linux/drivers/tty/serial/serial_bcm6345.c
- *	Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
- */
-
-#include <clk.h>
-#include <dm.h>
-#include <debug_uart.h>
-#include <errno.h>
-#include <serial.h>
-#include <asm/io.h>
-#include <asm/types.h>
-
-/* UART Control register */
-#define UART_CTL_REG			0x0
-#define UART_CTL_RXTIMEOUT_MASK		0x1f
-#define UART_CTL_RXTIMEOUT_5		0x5
-#define UART_CTL_RSTRXFIFO_SHIFT	6
-#define UART_CTL_RSTRXFIFO_MASK		(1 << UART_CTL_RSTRXFIFO_SHIFT)
-#define UART_CTL_RSTTXFIFO_SHIFT	7
-#define UART_CTL_RSTTXFIFO_MASK		(1 << UART_CTL_RSTTXFIFO_SHIFT)
-#define UART_CTL_STOPBITS_SHIFT		8
-#define UART_CTL_STOPBITS_MASK		(0xf << UART_CTL_STOPBITS_SHIFT)
-#define UART_CTL_STOPBITS_1		(0x7 << UART_CTL_STOPBITS_SHIFT)
-#define UART_CTL_BITSPERSYM_SHIFT	12
-#define UART_CTL_BITSPERSYM_MASK	(0x3 << UART_CTL_BITSPERSYM_SHIFT)
-#define UART_CTL_BITSPERSYM_8		(0x3 << UART_CTL_BITSPERSYM_SHIFT)
-#define UART_CTL_XMITBRK_SHIFT		14
-#define UART_CTL_XMITBRK_MASK		(1 << UART_CTL_XMITBRK_SHIFT)
-#define UART_CTL_RSVD_SHIFT		15
-#define UART_CTL_RSVD_MASK		(1 << UART_CTL_RSVD_SHIFT)
-#define UART_CTL_RXPAREVEN_SHIFT	16
-#define UART_CTL_RXPAREVEN_MASK		(1 << UART_CTL_RXPAREVEN_SHIFT)
-#define UART_CTL_RXPAREN_SHIFT		17
-#define UART_CTL_RXPAREN_MASK		(1 << UART_CTL_RXPAREN_SHIFT)
-#define UART_CTL_TXPAREVEN_SHIFT	18
-#define UART_CTL_TXPAREVEN_MASK		(1 << UART_CTL_TXPAREVEN_SHIFT)
-#define UART_CTL_TXPAREN_SHIFT		19
-#define UART_CTL_TXPAREN_MASK		(1 << UART_CTL_TXPAREN_SHIFT)
-#define UART_CTL_LOOPBACK_SHIFT		20
-#define UART_CTL_LOOPBACK_MASK		(1 << UART_CTL_LOOPBACK_SHIFT)
-#define UART_CTL_RXEN_SHIFT		21
-#define UART_CTL_RXEN_MASK		(1 << UART_CTL_RXEN_SHIFT)
-#define UART_CTL_TXEN_SHIFT		22
-#define UART_CTL_TXEN_MASK		(1 << UART_CTL_TXEN_SHIFT)
-#define UART_CTL_BRGEN_SHIFT		23
-#define UART_CTL_BRGEN_MASK		(1 << UART_CTL_BRGEN_SHIFT)
-
-/* UART Baudword register */
-#define UART_BAUD_REG			0x4
-
-/* UART FIFO Config register */
-#define UART_FIFO_CFG_REG		0x8
-#define UART_FIFO_CFG_RX_SHIFT		8
-#define UART_FIFO_CFG_RX_MASK		(0xf << UART_FIFO_CFG_RX_SHIFT)
-#define UART_FIFO_CFG_RX_4		(0x4 << UART_FIFO_CFG_RX_SHIFT)
-#define UART_FIFO_CFG_TX_SHIFT		12
-#define UART_FIFO_CFG_TX_MASK		(0xf << UART_FIFO_CFG_TX_SHIFT)
-#define UART_FIFO_CFG_TX_4		(0x4 << UART_FIFO_CFG_TX_SHIFT)
-
-/* UART Interrupt register */
-#define UART_IR_REG			0x10
-#define UART_IR_STAT(x)			(1 << (x))
-#define UART_IR_TXEMPTY			5
-#define UART_IR_RXOVER			7
-#define UART_IR_RXNOTEMPTY		11
-
-/* UART FIFO register */
-#define UART_FIFO_REG			0x14
-#define UART_FIFO_VALID_MASK		0xff
-#define UART_FIFO_FRAMEERR_SHIFT	8
-#define UART_FIFO_FRAMEERR_MASK		(1 << UART_FIFO_FRAMEERR_SHIFT)
-#define UART_FIFO_PARERR_SHIFT		9
-#define UART_FIFO_PARERR_MASK		(1 << UART_FIFO_PARERR_SHIFT)
-#define UART_FIFO_BRKDET_SHIFT		10
-#define UART_FIFO_BRKDET_MASK		(1 << UART_FIFO_BRKDET_SHIFT)
-#define UART_FIFO_ANYERR_MASK		(UART_FIFO_FRAMEERR_MASK |	\
-					UART_FIFO_PARERR_MASK |		\
-					UART_FIFO_BRKDET_MASK)
-
-struct bcm6858_serial_priv {
-	void __iomem *base;
-	ulong uartclk;
-};
-
-/* enable rx & tx operation on uart */
-static void bcm6858_serial_enable(void __iomem *base)
-{
-	setbits_le32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK |
-		     UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
-}
-
-/* disable rx & tx operation on uart */
-static void bcm6858_serial_disable(void __iomem *base)
-{
-	clrbits_le32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK |
-		     UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
-}
-
-/* clear all unread data in rx fifo and unsent data in tx fifo */
-static void bcm6858_serial_flush(void __iomem *base)
-{
-	/* empty rx and tx fifo */
-	setbits_le32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK |
-		     UART_CTL_RSTTXFIFO_MASK);
-
-	/* read any pending char to make sure all irq status are cleared */
-	readl(base + UART_FIFO_REG);
-}
-
-static int bcm6858_serial_init(void __iomem *base, ulong clk, u32 baudrate)
-{
-	u32 val;
-
-	/* mask all irq and flush port */
-	bcm6858_serial_disable(base);
-	bcm6858_serial_flush(base);
-
-	/* set uart control config */
-	clrsetbits_le32(base + UART_CTL_REG,
-			/* clear rx timeout */
-			UART_CTL_RXTIMEOUT_MASK |
-			/* clear stop bits */
-			UART_CTL_STOPBITS_MASK |
-			/* clear bits per symbol */
-			UART_CTL_BITSPERSYM_MASK |
-			/* clear xmit break */
-			UART_CTL_XMITBRK_MASK |
-			/* clear reserved bit */
-			UART_CTL_RSVD_MASK |
-			/* disable parity */
-			UART_CTL_RXPAREN_MASK |
-			UART_CTL_TXPAREN_MASK |
-			/* disable loopback */
-			UART_CTL_LOOPBACK_MASK,
-			/* set timeout to 5 */
-			UART_CTL_RXTIMEOUT_5 |
-			/* set 8 bits/symbol */
-			UART_CTL_BITSPERSYM_8 |
-			/* set 1 stop bit */
-			UART_CTL_STOPBITS_1 |
-			/* set parity to even */
-			UART_CTL_RXPAREVEN_MASK |
-			UART_CTL_TXPAREVEN_MASK);
-
-	/* set uart fifo config */
-	clrsetbits_le32(base + UART_FIFO_CFG_REG,
-			/* clear fifo config */
-			UART_FIFO_CFG_RX_MASK |
-			UART_FIFO_CFG_TX_MASK,
-			/* set fifo config to 4 */
-			UART_FIFO_CFG_RX_4 |
-			UART_FIFO_CFG_TX_4);
-
-	/* set baud rate */
-	val = ((clk / baudrate) >> 4);
-	if (val & 0x1)
-		val = (val >> 1);
-	else
-		val = (val >> 1) - 1;
-	writel(val, base + UART_BAUD_REG);
-
-	/* clear interrupts */
-	writel(0, base + UART_IR_REG);
-
-	/* enable uart */
-	bcm6858_serial_enable(base);
-
-	return 0;
-}
-
-static int bcm6858_serial_pending(struct udevice *dev, bool input)
-{
-	struct bcm6858_serial_priv *priv = dev_get_priv(dev);
-	u32 val = readl(priv->base + UART_IR_REG);
-
-	if (input)
-		return !!(val & UART_IR_STAT(UART_IR_RXNOTEMPTY));
-	else
-		return !(val & UART_IR_STAT(UART_IR_TXEMPTY));
-}
-
-static int bcm6858_serial_setbrg(struct udevice *dev, int baudrate)
-{
-	struct bcm6858_serial_priv *priv = dev_get_priv(dev);
-
-	return bcm6858_serial_init(priv->base, priv->uartclk, baudrate);
-}
-
-static int bcm6858_serial_putc(struct udevice *dev, const char ch)
-{
-	struct bcm6858_serial_priv *priv = dev_get_priv(dev);
-	u32 val;
-
-	val = readl(priv->base + UART_IR_REG);
-	if (!(val & UART_IR_STAT(UART_IR_TXEMPTY)))
-		return -EAGAIN;
-
-	writel(ch, priv->base + UART_FIFO_REG);
-
-	return 0;
-}
-
-static int bcm6858_serial_getc(struct udevice *dev)
-{
-	struct bcm6858_serial_priv *priv = dev_get_priv(dev);
-	u32 val;
-
-	val = readl(priv->base + UART_IR_REG);
-	if (val & UART_IR_STAT(UART_IR_RXOVER))
-		setbits_le32(priv->base + UART_CTL_REG,
-			     UART_CTL_RSTRXFIFO_MASK);
-
-	if (!(val & UART_IR_STAT(UART_IR_RXNOTEMPTY)))
-		return -EAGAIN;
-
-	val = readl(priv->base + UART_FIFO_REG);
-	if (val & UART_FIFO_ANYERR_MASK)
-		return -EAGAIN;
-
-	return val & UART_FIFO_VALID_MASK;
-}
-
-static int bcm6858_serial_probe(struct udevice *dev)
-{
-	struct bcm6858_serial_priv *priv = dev_get_priv(dev);
-	struct clk clk;
-	int ret;
-
-	/* get address */
-	priv->base = dev_remap_addr(dev);
-	if (!priv->base)
-		return -EINVAL;
-
-	/* get clock rate */
-	ret = clk_get_by_index(dev, 0, &clk);
-	if (ret < 0)
-		return ret;
-	priv->uartclk = clk_get_rate(&clk);
-	clk_free(&clk);
-
-	/* initialize serial */
-	return bcm6858_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE);
-}
-
-static const struct dm_serial_ops bcm6858_serial_ops = {
-	.putc = bcm6858_serial_putc,
-	.pending = bcm6858_serial_pending,
-	.getc = bcm6858_serial_getc,
-	.setbrg = bcm6858_serial_setbrg,
-};
-
-static const struct udevice_id bcm6858_serial_ids[] = {
-	{ .compatible = "brcm,bcm6858-uart" },
-	{ /* sentinel */ }
-};
-
-U_BOOT_DRIVER(bcm6858_serial) = {
-	.name = "bcm6858-uart",
-	.id = UCLASS_SERIAL,
-	.of_match = bcm6858_serial_ids,
-	.probe = bcm6858_serial_probe,
-	.priv_auto_alloc_size = sizeof(struct bcm6858_serial_priv),
-	.ops = &bcm6858_serial_ops,
-	.flags = DM_FLAG_PRE_RELOC,
-};
-
-#ifdef CONFIG_DEBUG_UART_BCM6858
-static inline void _debug_uart_init(void)
-{
-	void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
-
-	bcm6858_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
-}
-
-static inline void wait_xfered(void __iomem *base)
-{
-	do {
-		u32 val = readl(base + UART_IR_REG);
-		if (val & UART_IR_STAT(UART_IR_TXEMPTY))
-			break;
-	} while (1);
-}
-
-static inline void _debug_uart_putc(int ch)
-{
-	void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
-
-	wait_xfered(base);
-	writel(ch, base + UART_FIFO_REG);
-	wait_xfered(base);
-}
-
-DEBUG_UART_FUNCS
-#endif
diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c
index ee6ad9c..a31d737 100644
--- a/drivers/serial/serial_omap.c
+++ b/drivers/serial/serial_omap.c
@@ -7,7 +7,6 @@
  */
 
 #include <common.h>
-#include <debug_uart.h>
 #include <dm.h>
 #include <dt-structs.h>
 #include <ns16550.h>
@@ -20,6 +19,47 @@
 
 #ifdef CONFIG_DEBUG_UART_OMAP
 
+#ifndef CONFIG_SYS_NS16550_IER
+#define CONFIG_SYS_NS16550_IER  0x00
+#endif
+
+#define UART_MCRVAL 0x00
+#define UART_LCRVAL UART_LCR_8N1
+
+static inline void serial_out_shift(void *addr, int shift, int value)
+{
+#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
+	outb(value, (ulong)addr);
+#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_LITTLE_ENDIAN)
+	out_le32(addr, value);
+#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
+	out_be32(addr, value);
+#elif defined(CONFIG_SYS_NS16550_MEM32)
+	writel(value, addr);
+#elif defined(CONFIG_SYS_BIG_ENDIAN)
+	writeb(value, addr + (1 << shift) - 1);
+#else
+	writeb(value, addr);
+#endif
+}
+
+static inline int serial_in_shift(void *addr, int shift)
+{
+#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
+	return inb((ulong)addr);
+#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_LITTLE_ENDIAN)
+	return in_le32(addr);
+#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
+	return in_be32(addr);
+#elif defined(CONFIG_SYS_NS16550_MEM32)
+	return readl(addr);
+#elif defined(CONFIG_SYS_BIG_ENDIAN)
+	return readb(addr + (1 << shift) - 1);
+#else
+	return readb(addr);
+#endif
+}
+
 #include <debug_uart.h>
 
 static inline void _debug_uart_init(void)
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index d456beb..98f8343 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -52,6 +52,20 @@
 	depends on DM_USB
 	default y
 
+config DM_USB_GADGET
+	bool "Enable driver model for USB Gadget"
+	depends on DM_USB
+	help
+	  Enable driver model for USB Gadget (Peripheral
+	  mode)
+
+config SPL_DM_USB_GADGET
+	bool "Enable driver model for USB Gadget in sPL"
+	depends on SPL_DM_USB
+	help
+	  Enable driver model for USB Gadget in SPL
+	  (Peripheral mode)
+
 source "drivers/usb/host/Kconfig"
 
 source "drivers/usb/dwc3/Kconfig"
diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index 943b763..bbd8105 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -38,10 +38,11 @@
 	  Say 'Y' here if you have one such device
 
 config USB_DWC3_GENERIC
-	bool "Xilinx ZynqMP and similar Platforms"
-	depends on DM_USB && USB_DWC3
+	bool "Generic implementation of a DWC3 wrapper (aka dwc3 glue)"
+	depends on DM_USB && USB_DWC3 && MISC
 	help
-	  Some platforms can reuse this DWC3 generic implementation.
+	  Select this for Xilinx ZynqMP and similar Platforms.
+	  This wrapper supports Host and Peripheral operation modes.
 
 config USB_DWC3_UNIPHIER
 	bool "DesignWare USB3 Host Support on UniPhier Platforms"
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index f1ca619..56e2a04 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -19,7 +19,7 @@
 #include <asm/dma-mapping.h>
 #include <linux/ioport.h>
 #include <dm.h>
-
+#include <generic-phy.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
 
@@ -789,8 +789,92 @@
 MODULE_LICENSE("GPL v2");
 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
 
+#if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB)
+int dwc3_setup_phy(struct udevice *dev, struct phy **array, int *num_phys)
+{
+	int i, ret, count;
+	struct phy *usb_phys;
+
+	/* Return if no phy declared */
+	if (!dev_read_prop(dev, "phys", NULL))
+		return 0;
+	count = dev_count_phandle_with_args(dev, "phys", "#phy-cells");
+	if (count <= 0)
+		return count;
+
+	usb_phys = devm_kcalloc(dev, count, sizeof(struct phy),
+				GFP_KERNEL);
+	if (!usb_phys)
+		return -ENOMEM;
+
+	for (i = 0; i < count; i++) {
+		ret = generic_phy_get_by_index(dev, i, &usb_phys[i]);
+		if (ret && ret != -ENOENT) {
+			pr_err("Failed to get USB PHY%d for %s\n",
+			       i, dev->name);
+			return ret;
+		}
+	}
+
+	for (i = 0; i < count; i++) {
+		ret = generic_phy_init(&usb_phys[i]);
+		if (ret) {
+			pr_err("Can't init USB PHY%d for %s\n",
+			       i, dev->name);
+			goto phys_init_err;
+		}
+	}
+
+	for (i = 0; i < count; i++) {
+		ret = generic_phy_power_on(&usb_phys[i]);
+		if (ret) {
+			pr_err("Can't power USB PHY%d for %s\n",
+			       i, dev->name);
+			goto phys_poweron_err;
+		}
+	}
+
+	*array = usb_phys;
+	*num_phys =  count;
+	return 0;
+
+phys_poweron_err:
+	for (i = count - 1; i >= 0; i--)
+		generic_phy_power_off(&usb_phys[i]);
+
+	for (i = 0; i < count; i++)
+		generic_phy_exit(&usb_phys[i]);
+
+	return ret;
+
+phys_init_err:
+	for (; i >= 0; i--)
+		generic_phy_exit(&usb_phys[i]);
+
+	return ret;
+}
+
+int dwc3_shutdown_phy(struct udevice *dev, struct phy *usb_phys, int num_phys)
+{
+	int i, ret;
+
+	for (i = 0; i < num_phys; i++) {
+		if (!generic_phy_valid(&usb_phys[i]))
+			continue;
+
+		ret = generic_phy_power_off(&usb_phys[i]);
+		ret |= generic_phy_exit(&usb_phys[i]);
+		if (ret) {
+			pr_err("Can't shutdown USB PHY%d for %s\n",
+			       i, dev->name);
+		}
+	}
+
-#if CONFIG_IS_ENABLED(DM_USB)
+	return 0;
+}
+#endif
 
+#if CONFIG_IS_ENABLED(DM_USB_GADGET)
 int dwc3_init(struct dwc3 *dwc)
 {
 	int ret;
@@ -841,5 +925,4 @@
 	dwc3_core_exit(dwc);
 	kfree(dwc->mem);
 }
-
 #endif
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 56c9fd6..bc6bba1 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -8,72 +8,89 @@
  */
 
 #include <common.h>
+#include <asm-generic/io.h>
 #include <dm.h>
 #include <dm/device-internal.h>
 #include <dm/lists.h>
-#include <linux/usb/otg.h>
-#include <linux/compat.h>
+#include <dwc3-uboot.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
 #include <malloc.h>
 #include <usb.h>
 #include "core.h"
 #include "gadget.h"
-#include "linux-compat.h"
+#include <reset.h>
+#include <clk.h>
 
-DECLARE_GLOBAL_DATA_PTR;
+#if CONFIG_IS_ENABLED(DM_USB_GADGET)
+struct dwc3_generic_peripheral {
+	struct dwc3 dwc3;
+	struct phy *phys;
+	int num_phys;
+	fdt_addr_t base;
+};
 
-int usb_gadget_handle_interrupts(int index)
+int dm_usb_gadget_handle_interrupts(struct udevice *dev)
 {
-	struct dwc3 *priv;
-	struct udevice *dev;
-	int ret;
-
-	ret = uclass_first_device(UCLASS_USB_DEV_GENERIC, &dev);
-	if (!dev || ret) {
-		pr_err("No USB device found\n");
-		return -ENODEV;
-	}
-
-	priv = dev_get_priv(dev);
+	struct dwc3_generic_peripheral *priv = dev_get_priv(dev);
+	struct dwc3 *dwc3 = &priv->dwc3;
 
-	dwc3_gadget_uboot_handle_interrupt(priv);
+	dwc3_gadget_uboot_handle_interrupt(dwc3);
 
 	return 0;
 }
 
 static int dwc3_generic_peripheral_probe(struct udevice *dev)
 {
-	struct dwc3 *priv = dev_get_priv(dev);
+	int rc;
+	struct dwc3_generic_peripheral *priv = dev_get_priv(dev);
+	struct dwc3 *dwc3 = &priv->dwc3;
 
-	return dwc3_init(priv);
+	rc = dwc3_setup_phy(dev, &priv->phys, &priv->num_phys);
+	if (rc)
+		return rc;
+
+	dwc3->regs = map_physmem(priv->base, DWC3_OTG_REGS_END, MAP_NOCACHE);
+	dwc3->regs += DWC3_GLOBALS_REGS_START;
+	dwc3->dev = dev;
+
+	rc =  dwc3_init(dwc3);
+	if (rc) {
+		unmap_physmem(dwc3->regs, MAP_NOCACHE);
+		return rc;
+	}
+
+	return 0;
 }
 
 static int dwc3_generic_peripheral_remove(struct udevice *dev)
 {
-	struct dwc3 *priv = dev_get_priv(dev);
+	struct dwc3_generic_peripheral *priv = dev_get_priv(dev);
+	struct dwc3 *dwc3 = &priv->dwc3;
 
-	dwc3_remove(priv);
+	dwc3_remove(dwc3);
+	dwc3_shutdown_phy(dev, priv->phys, priv->num_phys);
+	unmap_physmem(dwc3->regs, MAP_NOCACHE);
 
 	return 0;
 }
 
 static int dwc3_generic_peripheral_ofdata_to_platdata(struct udevice *dev)
 {
-	struct dwc3 *priv = dev_get_priv(dev);
+	struct dwc3_generic_peripheral *priv = dev_get_priv(dev);
+	struct dwc3 *dwc3 = &priv->dwc3;
 	int node = dev_of_offset(dev);
 
-	priv->regs = (void *)devfdt_get_addr(dev);
-	priv->regs += DWC3_GLOBALS_REGS_START;
+	priv->base = devfdt_get_addr(dev);
 
-	priv->maximum_speed = usb_get_maximum_speed(node);
-	if (priv->maximum_speed == USB_SPEED_UNKNOWN) {
+	dwc3->maximum_speed = usb_get_maximum_speed(node);
+	if (dwc3->maximum_speed == USB_SPEED_UNKNOWN) {
 		pr_err("Invalid usb maximum speed\n");
 		return -ENODEV;
 	}
 
-	priv->dr_mode = usb_get_dr_mode(node);
-	if (priv->dr_mode == USB_DR_MODE_UNKNOWN) {
+	dwc3->dr_mode = usb_get_dr_mode(node);
+	if (dwc3->dr_mode == USB_DR_MODE_UNKNOWN) {
 		pr_err("Invalid usb mode setup\n");
 		return -ENODEV;
 	}
@@ -81,24 +98,112 @@
 	return 0;
 }
 
-static int dwc3_generic_peripheral_bind(struct udevice *dev)
-{
-	return device_probe(dev);
-}
-
 U_BOOT_DRIVER(dwc3_generic_peripheral) = {
 	.name	= "dwc3-generic-peripheral",
-	.id	= UCLASS_USB_DEV_GENERIC,
+	.id	= UCLASS_USB_GADGET_GENERIC,
 	.ofdata_to_platdata = dwc3_generic_peripheral_ofdata_to_platdata,
 	.probe = dwc3_generic_peripheral_probe,
 	.remove = dwc3_generic_peripheral_remove,
-	.bind = dwc3_generic_peripheral_bind,
-	.platdata_auto_alloc_size = sizeof(struct usb_platdata),
-	.priv_auto_alloc_size = sizeof(struct dwc3),
-	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
+	.priv_auto_alloc_size = sizeof(struct dwc3_generic_peripheral),
+};
+#endif
+
+struct dwc3_glue_data {
+	struct clk_bulk		clks;
+	struct reset_ctl_bulk	resets;
+	fdt_addr_t regs;
 };
 
-static int dwc3_generic_bind(struct udevice *parent)
+struct dwc3_glue_ops {
+	void (*select_dr_mode)(struct udevice *dev, int index,
+			       enum usb_dr_mode mode);
+};
+
+void dwc3_ti_select_dr_mode(struct udevice *dev, int index,
+			    enum usb_dr_mode mode)
+{
+#define USBOTGSS_UTMI_OTG_STATUS		0x0084
+#define USBOTGSS_UTMI_OTG_OFFSET		0x0480
+
+/* UTMI_OTG_STATUS REGISTER */
+#define USBOTGSS_UTMI_OTG_STATUS_SW_MODE	BIT(31)
+#define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT	BIT(9)
+#define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE BIT(8)
+#define USBOTGSS_UTMI_OTG_STATUS_IDDIG		BIT(4)
+#define USBOTGSS_UTMI_OTG_STATUS_SESSEND	BIT(3)
+#define USBOTGSS_UTMI_OTG_STATUS_SESSVALID	BIT(2)
+#define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID	BIT(1)
+enum dwc3_omap_utmi_mode {
+	DWC3_OMAP_UTMI_MODE_UNKNOWN = 0,
+	DWC3_OMAP_UTMI_MODE_HW,
+	DWC3_OMAP_UTMI_MODE_SW,
+};
+
+	u32 use_id_pin;
+	u32 host_mode;
+	u32 reg;
+	u32 utmi_mode;
+	u32 utmi_status_offset = USBOTGSS_UTMI_OTG_STATUS;
+
+	struct dwc3_glue_data *glue = dev_get_platdata(dev);
+	void *base = map_physmem(glue->regs, 0x10000, MAP_NOCACHE);
+
+	if (device_is_compatible(dev, "ti,am437x-dwc3"))
+		utmi_status_offset += USBOTGSS_UTMI_OTG_OFFSET;
+
+	utmi_mode = dev_read_u32_default(dev, "utmi-mode",
+					 DWC3_OMAP_UTMI_MODE_UNKNOWN);
+	if (utmi_mode != DWC3_OMAP_UTMI_MODE_HW) {
+		debug("%s: OTG is not supported. defaulting to PERIPHERAL\n",
+		      dev->name);
+		mode = USB_DR_MODE_PERIPHERAL;
+	}
+
+	switch (mode)  {
+	case USB_DR_MODE_PERIPHERAL:
+		use_id_pin = 0;
+		host_mode = 0;
+		break;
+	case USB_DR_MODE_HOST:
+		use_id_pin = 0;
+		host_mode = 1;
+		break;
+	case USB_DR_MODE_OTG:
+	default:
+		use_id_pin = 1;
+		host_mode = 0;
+		break;
+	}
+
+	reg = readl(base + utmi_status_offset);
+
+	reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SW_MODE);
+	if (!use_id_pin)
+		reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
+
+	writel(reg, base + utmi_status_offset);
+
+	reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSEND |
+		USBOTGSS_UTMI_OTG_STATUS_VBUSVALID |
+		USBOTGSS_UTMI_OTG_STATUS_IDDIG);
+
+	reg |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID |
+		USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
+
+	if (!host_mode)
+		reg |= USBOTGSS_UTMI_OTG_STATUS_IDDIG |
+			USBOTGSS_UTMI_OTG_STATUS_VBUSVALID;
+
+	writel(reg, base + utmi_status_offset);
+
+	unmap_physmem(base, MAP_NOCACHE);
+}
+
+struct dwc3_glue_ops ti_ops = {
+	.select_dr_mode = dwc3_ti_select_dr_mode,
+};
+
+static int dwc3_glue_bind(struct udevice *parent)
 {
 	const void *fdt = gd->fdt_blob;
 	int node;
@@ -109,29 +214,32 @@
 		const char *name = fdt_get_name(fdt, node, NULL);
 		enum usb_dr_mode dr_mode;
 		struct udevice *dev;
-		const char *driver;
+		const char *driver = NULL;
 
 		debug("%s: subnode name: %s\n", __func__, name);
-		if (strncmp(name, "dwc3@", 4))
-			continue;
 
 		dr_mode = usb_get_dr_mode(node);
 
 		switch (dr_mode) {
 		case USB_DR_MODE_PERIPHERAL:
 		case USB_DR_MODE_OTG:
+#if CONFIG_IS_ENABLED(DM_USB_GADGET)
 			debug("%s: dr_mode: OTG or Peripheral\n", __func__);
 			driver = "dwc3-generic-peripheral";
+#endif
 			break;
 		case USB_DR_MODE_HOST:
 			debug("%s: dr_mode: HOST\n", __func__);
-			driver = "dwc3-generic-host";
+			driver = "xhci-dwc3";
 			break;
 		default:
 			debug("%s: unsupported dr_mode\n", __func__);
 			return -ENODEV;
 		};
 
+		if (!driver)
+			continue;
+
 		ret = device_bind_driver_to_node(parent, driver, name,
 						 offset_to_ofnode(node), &dev);
 		if (ret) {
@@ -144,14 +252,107 @@
 	return 0;
 }
 
+static int dwc3_glue_reset_init(struct udevice *dev,
+				struct dwc3_glue_data *glue)
+{
+	int ret;
+
+	ret = reset_get_bulk(dev, &glue->resets);
+	if (ret == -ENOTSUPP)
+		return 0;
+	else if (ret)
+		return ret;
+
+	ret = reset_deassert_bulk(&glue->resets);
+	if (ret) {
+		reset_release_bulk(&glue->resets);
+		return ret;
+	}
+
+	return 0;
+}
+
-static const struct udevice_id dwc3_generic_ids[] = {
+static int dwc3_glue_clk_init(struct udevice *dev,
+			      struct dwc3_glue_data *glue)
+{
+	int ret;
+
+	ret = clk_get_bulk(dev, &glue->clks);
+	if (ret == -ENOSYS)
+		return 0;
+	if (ret)
+		return ret;
+
+#if CONFIG_IS_ENABLED(CLK)
+	ret = clk_enable_bulk(&glue->clks);
+	if (ret) {
+		clk_release_bulk(&glue->clks);
+		return ret;
+	}
+#endif
+
+	return 0;
+}
+
+static int dwc3_glue_probe(struct udevice *dev)
+{
+	struct dwc3_glue_ops *ops = (struct dwc3_glue_ops *)dev_get_driver_data(dev);
+	struct dwc3_glue_data *glue = dev_get_platdata(dev);
+	struct udevice *child = NULL;
+	int index = 0;
+	int ret;
+
+	glue->regs = dev_read_addr(dev);
+
+	ret = dwc3_glue_clk_init(dev, glue);
+	if (ret)
+		return ret;
+
+	ret = dwc3_glue_reset_init(dev, glue);
+	if (ret)
+		return ret;
+
+	ret = device_find_first_child(dev, &child);
+	if (ret)
+		return ret;
+
+	while (child) {
+		enum usb_dr_mode dr_mode;
+
+		dr_mode = usb_get_dr_mode(dev_of_offset(child));
+		device_find_next_child(&child);
+		if (ops && ops->select_dr_mode)
+			ops->select_dr_mode(dev, index, dr_mode);
+		index++;
+	}
+
+	return 0;
+}
+
+static int dwc3_glue_remove(struct udevice *dev)
+{
+	struct dwc3_glue_data *glue = dev_get_platdata(dev);
+
+	reset_release_bulk(&glue->resets);
+
+	clk_release_bulk(&glue->clks);
+
+	return dm_scan_fdt_dev(dev);
+}
+
+static const struct udevice_id dwc3_glue_ids[] = {
 	{ .compatible = "xlnx,zynqmp-dwc3" },
+	{ .compatible = "ti,dwc3", .data = (ulong)&ti_ops },
 	{ }
 };
 
 U_BOOT_DRIVER(dwc3_generic_wrapper) = {
 	.name	= "dwc3-generic-wrapper",
 	.id	= UCLASS_MISC,
-	.of_match = dwc3_generic_ids,
-	.bind = dwc3_generic_bind,
+	.of_match = dwc3_glue_ids,
+	.bind = dwc3_glue_bind,
+	.probe = dwc3_glue_probe,
+	.remove = dwc3_glue_remove,
+	.platdata_auto_alloc_size = sizeof(struct dwc3_glue_data),
+
 };
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index 4f68887..818efb3 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -12,7 +12,7 @@
  *
  * commit c00552ebaf : Merge 3.18-rc7 into usb-next
  */
-
+#include <common.h>
 #include <linux/kernel.h>
 #include <linux/list.h>
 
diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c
index 193583b..3b3d9af 100644
--- a/drivers/usb/gadget/ether.c
+++ b/drivers/usb/gadget/ether.c
@@ -100,9 +100,6 @@
 	struct usb_gadget	*gadget;
 	struct usb_request	*req;		/* for control responses */
 	struct usb_request	*stat_req;	/* for cdc & rndis status */
-#if CONFIG_IS_ENABLED(DM_USB)
-	struct udevice		*usb_udev;
-#endif
 
 	u8			config;
 	struct usb_ep		*in_ep, *out_ep, *status_ep;
@@ -2336,40 +2333,17 @@
 }
 
 /*-------------------------------------------------------------------------*/
-
-#if CONFIG_IS_ENABLED(DM_USB)
-int dm_usb_init(struct eth_dev *e_dev)
-{
-	struct udevice *dev = NULL;
-	int ret;
-
-	ret = uclass_first_device(UCLASS_USB_DEV_GENERIC, &dev);
-	if (!dev || ret) {
-		pr_err("No USB device found\n");
-		return -ENODEV;
-	}
-
-	e_dev->usb_udev = dev;
-
-	return ret;
-}
-#endif
-
 static int _usb_eth_init(struct ether_priv *priv)
 {
 	struct eth_dev *dev = &priv->ethdev;
 	struct usb_gadget *gadget;
 	unsigned long ts;
+	int ret;
 	unsigned long timeout = USB_CONNECT_TIMEOUT;
 
-#if CONFIG_IS_ENABLED(DM_USB)
-	if (dm_usb_init(dev)) {
-		pr_err("USB ether not found\n");
-		return -ENODEV;
-	}
-#else
-	board_usb_init(0, USB_INIT_DEVICE);
-#endif
+	ret = usb_gadget_initialize(0);
+	if (ret)
+		return ret;
 
 	/* Configure default mac-addresses for the USB ethernet device */
 #ifdef CONFIG_USBNET_DEV_ADDR
@@ -2541,9 +2515,7 @@
 	}
 
 	usb_gadget_unregister_driver(&priv->eth_driver);
-#if !CONFIG_IS_ENABLED(DM_USB)
-	board_usb_cleanup(0, USB_INIT_DEVICE);
-#endif
+	usb_gadget_release(0);
 }
 
 #ifndef CONFIG_DM_ETH
@@ -2699,7 +2671,7 @@
 	struct udevice *usb_dev;
 	int ret;
 
-	ret = uclass_first_device(UCLASS_USB_DEV_GENERIC, &usb_dev);
+	ret = uclass_first_device(UCLASS_USB_GADGET_GENERIC, &usb_dev);
 	if (!usb_dev || ret) {
 		pr_err("No USB device found\n");
 		return ret;
diff --git a/drivers/usb/gadget/udc/Makefile b/drivers/usb/gadget/udc/Makefile
index 449339f..38ac2dd 100644
--- a/drivers/usb/gadget/udc/Makefile
+++ b/drivers/usb/gadget/udc/Makefile
@@ -2,4 +2,8 @@
 #
 # USB peripheral controller drivers
 
+ifndef CONFIG_$(SPL_)DM_USB_GADGET
 obj-$(CONFIG_USB_DWC3_GADGET)	+= udc-core.o
+endif
+
+obj-$(CONFIG_$(SPL_)DM_USB_GADGET)	+= udc-uclass.o udc-core.o
diff --git a/drivers/usb/gadget/udc/udc-core.c b/drivers/usb/gadget/udc/udc-core.c
index f5c30dd..62b4778 100644
--- a/drivers/usb/gadget/udc/udc-core.c
+++ b/drivers/usb/gadget/udc/udc-core.c
@@ -18,7 +18,8 @@
 #include <asm/cache.h>
 #include <asm/dma-mapping.h>
 #include <common.h>
-
+#include <dm.h>
+#include <dm/device-internal.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
 
diff --git a/drivers/usb/gadget/udc/udc-uclass.c b/drivers/usb/gadget/udc/udc-uclass.c
new file mode 100644
index 0000000..0620518
--- /dev/null
+++ b/drivers/usb/gadget/udc/udc-uclass.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
+ * Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <linux/usb/gadget.h>
+
+#define MAX_UDC_DEVICES 4
+static struct udevice *dev_array[MAX_UDC_DEVICES];
+int usb_gadget_initialize(int index)
+{
+	int ret;
+	struct udevice *dev = NULL;
+
+	if (index < 0 || index >= ARRAY_SIZE(dev_array))
+		return -EINVAL;
+	if (dev_array[index])
+		return 0;
+	ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, index, &dev);
+	if (!dev || ret) {
+		pr_err("No USB device found\n");
+		return -ENODEV;
+	}
+	dev_array[index] = dev;
+	return 0;
+}
+
+int usb_gadget_release(int index)
+{
+#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE)
+	int ret;
+	if (index < 0 || index >= ARRAY_SIZE(dev_array))
+		return -EINVAL;
+
+	ret = device_remove(dev_array[index], DM_REMOVE_NORMAL);
+	if (!ret)
+		dev_array[index] = NULL;
+	return ret;
+#else
+	return -ENOTSUPP;
+#endif
+}
+
+int usb_gadget_handle_interrupts(int index)
+{
+	if (index < 0 || index >= ARRAY_SIZE(dev_array))
+		return -EINVAL;
+	return dm_usb_gadget_handle_interrupts(dev_array[index]);
+}
+
+UCLASS_DRIVER(usb_gadget_generic) = {
+	.id		= UCLASS_USB_GADGET_GENERIC,
+	.name		= "usb_gadget_generic",
+};
diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
index dd0d156..83b9f11 100644
--- a/drivers/usb/host/xhci-dwc3.c
+++ b/drivers/usb/host/xhci-dwc3.c
@@ -12,6 +12,7 @@
 #include <fdtdec.h>
 #include <generic-phy.h>
 #include <usb.h>
+#include <dwc3-uboot.h>
 
 #include "xhci.h"
 #include <asm/io.h>
@@ -110,105 +111,21 @@
 }
 
 #if CONFIG_IS_ENABLED(DM_USB)
-static int xhci_dwc3_setup_phy(struct udevice *dev)
-{
-	struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
-	int i, ret, count;
-
-	/* Return if no phy declared */
-	if (!dev_read_prop(dev, "phys", NULL))
-		return 0;
-
-	count = dev_count_phandle_with_args(dev, "phys", "#phy-cells");
-	if (count <= 0)
-		return count;
-
-	plat->usb_phys = devm_kcalloc(dev, count, sizeof(struct phy),
-				      GFP_KERNEL);
-	if (!plat->usb_phys)
-		return -ENOMEM;
-
-	for (i = 0; i < count; i++) {
-		ret = generic_phy_get_by_index(dev, i, &plat->usb_phys[i]);
-		if (ret && ret != -ENOENT) {
-			pr_err("Failed to get USB PHY%d for %s\n",
-			       i, dev->name);
-			return ret;
-		}
-
-		++plat->num_phys;
-	}
-
-	for (i = 0; i < plat->num_phys; i++) {
-		ret = generic_phy_init(&plat->usb_phys[i]);
-		if (ret) {
-			pr_err("Can't init USB PHY%d for %s\n",
-			       i, dev->name);
-			goto phys_init_err;
-		}
-	}
-
-	for (i = 0; i < plat->num_phys; i++) {
-		ret = generic_phy_power_on(&plat->usb_phys[i]);
-		if (ret) {
-			pr_err("Can't power USB PHY%d for %s\n",
-			       i, dev->name);
-			goto phys_poweron_err;
-		}
-	}
-
-	return 0;
-
-phys_poweron_err:
-	for (; i >= 0; i--)
-		generic_phy_power_off(&plat->usb_phys[i]);
-
-	for (i = 0; i < plat->num_phys; i++)
-		generic_phy_exit(&plat->usb_phys[i]);
-
-	return ret;
-
-phys_init_err:
-	for (; i >= 0; i--)
-		generic_phy_exit(&plat->usb_phys[i]);
-
-	return ret;
-}
-
-static int xhci_dwc3_shutdown_phy(struct udevice *dev)
-{
-	struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
-	int i, ret;
-
-	for (i = 0; i < plat->num_phys; i++) {
-		if (!generic_phy_valid(&plat->usb_phys[i]))
-			continue;
-
-		ret = generic_phy_power_off(&plat->usb_phys[i]);
-		ret |= generic_phy_exit(&plat->usb_phys[i]);
-		if (ret) {
-			pr_err("Can't shutdown USB PHY%d for %s\n",
-			       i, dev->name);
-		}
-	}
-
-	return 0;
-}
-
 static int xhci_dwc3_probe(struct udevice *dev)
 {
 	struct xhci_hcor *hcor;
 	struct xhci_hccr *hccr;
 	struct dwc3 *dwc3_reg;
 	enum usb_dr_mode dr_mode;
+	struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
 	int ret;
 
 	hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev));
 	hcor = (struct xhci_hcor *)((uintptr_t)hccr +
 			HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
 
-	ret = xhci_dwc3_setup_phy(dev);
-	if (ret)
+	ret = dwc3_setup_phy(dev, &plat->usb_phys, &plat->num_phys);
+	if (ret && (ret != -ENOTSUPP))
 		return ret;
 
 	dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
@@ -227,7 +144,9 @@
 
 static int xhci_dwc3_remove(struct udevice *dev)
 {
-	xhci_dwc3_shutdown_phy(dev);
+	struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
+
+	dwc3_shutdown_phy(dev, plat->usb_phys, plat->num_phys);
 
 	return xhci_deregister(dev);
 }
diff --git a/drivers/usb/musb-new/omap2430.c b/drivers/usb/musb-new/omap2430.c
index 58aed72..32743aa 100644
--- a/drivers/usb/musb-new/omap2430.c
+++ b/drivers/usb/musb-new/omap2430.c
@@ -263,7 +263,7 @@
 #ifdef CONFIG_USB_MUSB_HOST
 	.id		= UCLASS_USB,
 #else
-	.id		= UCLASS_USB_DEV_GENERIC,
+	.id		= UCLASS_USB_GADGET_GENERIC,
 #endif
 	.of_match = omap2430_musb_ids,
 	.ofdata_to_platdata = omap2430_musb_ofdata_to_platdata,
diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index 6cf9826..d7170a3 100644
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c
@@ -535,7 +535,7 @@
 #ifdef CONFIG_USB_MUSB_HOST
 	.id		= UCLASS_USB,
 #else
-	.id		= UCLASS_USB_DEV_GENERIC,
+	.id		= UCLASS_USB_GADGET_GENERIC,
 #endif
 	.of_match	= sunxi_musb_ids,
 	.probe		= musb_usb_probe,
diff --git a/drivers/w1/w1-uclass.c b/drivers/w1/w1-uclass.c
index cb41b68..042b3b5 100644
--- a/drivers/w1/w1-uclass.c
+++ b/drivers/w1/w1-uclass.c
@@ -84,10 +84,6 @@
 			rn |= (tmp64 << i);
 		}
 
-		/* last device or error, aborting here */
-		if ((triplet_ret & 0x03) == 0x03)
-			last_device = true;
-
 		if ((triplet_ret & 0x03) != 0x03) {
 			if (desc_bit == last_zero || last_zero < 0) {
 				last_device = 1;
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index 4bc3030..ac8913e 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -571,6 +571,17 @@
 				mydata->sect_size, cur_part_info.blksz);
 		return -1;
 	}
+	if (mydata->clust_size == 0) {
+		printf("Error: FAT cluster size not set\n");
+		return -1;
+	}
+	if ((unsigned int)mydata->clust_size * mydata->sect_size >
+	    MAX_CLUSTSIZE) {
+		printf("Error: FAT cluster size too big (cs=%u, max=%u)\n",
+		       (unsigned int)mydata->clust_size * mydata->sect_size,
+		       MAX_CLUSTSIZE);
+		return -1;
+	}
 
 	if (mydata->fatsize == 32) {
 		mydata->data_begin = mydata->rootdir_sect -
@@ -810,6 +821,9 @@
 
 		slot2str((dir_slot *)dent, buf, &idx);
 
+		if (n + idx >= sizeof(itr->l_name))
+			return NULL;
+
 		/* shift accumulated long-name up and copy new part in: */
 		memmove(itr->l_name + idx, itr->l_name, n);
 		memcpy(itr->l_name, buf, idx);
diff --git a/include/axp209.h b/include/axp209.h
index b7de6ed..f4f1b2f 100644
--- a/include/axp209.h
+++ b/include/axp209.h
@@ -3,11 +3,14 @@
  * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
  */
 
+#include <linux/bitops.h>
+
 enum axp209_reg {
 	AXP209_POWER_STATUS = 0x00,
 	AXP209_CHIP_VERSION = 0x03,
 	AXP209_OUTPUT_CTRL = 0x12,
 	AXP209_DCDC2_VOLTAGE = 0x23,
+	AXP209_VRC_DCDC2_LDO3 = 0x25,
 	AXP209_DCDC3_VOLTAGE = 0x27,
 	AXP209_LDO24_VOLTAGE = 0x28,
 	AXP209_LDO3_VOLTAGE = 0x29,
@@ -20,29 +23,64 @@
 	AXP209_SHUTDOWN = 0x32,
 };
 
+#define AXP209_POWER_STATUS_ON_BY_DC	BIT(0)
+#define AXP209_POWER_STATUS_VBUS_USABLE	BIT(4)
+
+#define AXP209_CHIP_VERSION_MASK	0x0f
+
-#define AXP209_POWER_STATUS_ON_BY_DC	(1 << 0)
-#define AXP209_POWER_STATUS_VBUS_USABLE	(1 << 4)
+#define AXP209_OUTPUT_CTRL_EXTEN	BIT(0)
+#define AXP209_OUTPUT_CTRL_DCDC3	BIT(1)
+#define AXP209_OUTPUT_CTRL_LDO2		BIT(2)
+#define AXP209_OUTPUT_CTRL_LDO4		BIT(3)
+#define AXP209_OUTPUT_CTRL_DCDC2	BIT(4)
+#define AXP209_OUTPUT_CTRL_LDO3		BIT(6)
 
-#define AXP209_OUTPUT_CTRL_EXTEN	(1 << 0)
-#define AXP209_OUTPUT_CTRL_DCDC3	(1 << 1)
-#define AXP209_OUTPUT_CTRL_LDO2		(1 << 2)
-#define AXP209_OUTPUT_CTRL_LDO4		(1 << 3)
-#define AXP209_OUTPUT_CTRL_DCDC2	(1 << 4)
-#define AXP209_OUTPUT_CTRL_LDO3		(1 << 6)
+/*
+ * AXP209 datasheet contains wrong information about LDO3 VRC:
+ * - VRC is actually enabled when BIT(1) is True
+ * - VRC is actually not enabled by default (BIT(3) = 0 after reset)
+ */
+#define AXP209_VRC_LDO3_EN		BIT(3)
+#define AXP209_VRC_DCDC2_EN		BIT(2)
+#define AXP209_VRC_LDO3_800uV_uS	(BIT(1) | AXP209_VRC_LDO3_EN)
+#define AXP209_VRC_LDO3_1600uV_uS	AXP209_VRC_LDO3_EN
+#define AXP209_VRC_DCDC2_800uV_uS	(BIT(0) | AXP209_VRC_DCDC2_EN)
+#define AXP209_VRC_DCDC2_1600uV_uS	AXP209_VRC_DCDC2_EN
+#define AXP209_VRC_LDO3_MASK		0xa
+#define AXP209_VRC_DCDC2_MASK		0x5
+#define AXP209_VRC_DCDC2_SLOPE_SET(reg, cfg) \
+	(((reg) & ~AXP209_VRC_DCDC2_MASK) | \
+	((cfg) & AXP209_VRC_DCDC2_MASK))
+#define AXP209_VRC_LDO3_SLOPE_SET(reg, cfg) \
+	(((reg) & ~AXP209_VRC_LDO3_MASK) | \
+	((cfg) & AXP209_VRC_LDO3_MASK))
 
-#define AXP209_IRQ5_PEK_UP		(1 << 6)
-#define AXP209_IRQ5_PEK_DOWN		(1 << 5)
+#define AXP209_LDO24_LDO2_MASK		0xf0
+#define AXP209_LDO24_LDO4_MASK		0x0f
+#define AXP209_LDO24_LDO2_SET(reg, cfg)	\
+	(((reg) & ~AXP209_LDO24_LDO2_MASK) | \
+	(((cfg) << 4) & AXP209_LDO24_LDO2_MASK))
+#define AXP209_LDO24_LDO4_SET(reg, cfg)	\
+	(((reg) & ~AXP209_LDO24_LDO4_MASK) | \
+	(((cfg) << 0) & AXP209_LDO24_LDO4_MASK))
 
-#define AXP209_POWEROFF			(1 << 7)
+#define AXP209_LDO3_VOLTAGE_FROM_LDO3IN	BIT(7)
+#define AXP209_LDO3_VOLTAGE_MASK	0x7f
+#define AXP209_LDO3_VOLTAGE_SET(x)	((x) & AXP209_LDO3_VOLTAGE_MASK)
+
+#define AXP209_IRQ5_PEK_UP		BIT(6)
+#define AXP209_IRQ5_PEK_DOWN		BIT(5)
+
+#define AXP209_POWEROFF			BIT(7)
 
 /* For axp_gpio.c */
 #define AXP_POWER_STATUS		0x00
-#define AXP_POWER_STATUS_VBUS_PRESENT		(1 << 5)
+#define AXP_POWER_STATUS_VBUS_PRESENT	BIT(5)
 #define AXP_GPIO0_CTRL			0x90
 #define AXP_GPIO1_CTRL			0x92
 #define AXP_GPIO2_CTRL			0x93
-#define AXP_GPIO_CTRL_OUTPUT_LOW		0x00 /* Drive pin low */
-#define AXP_GPIO_CTRL_OUTPUT_HIGH		0x01 /* Drive pin high */
-#define AXP_GPIO_CTRL_INPUT			0x02 /* Input */
+#define AXP_GPIO_CTRL_OUTPUT_LOW	0x00 /* Drive pin low */
+#define AXP_GPIO_CTRL_OUTPUT_HIGH	0x01 /* Drive pin high */
+#define AXP_GPIO_CTRL_INPUT		0x02 /* Input */
 #define AXP_GPIO_STATE			0x94
-#define AXP_GPIO_STATE_OFFSET			4
+#define AXP_GPIO_STATE_OFFSET		4
diff --git a/include/configs/helios4.h b/include/configs/helios4.h
index ce912ea..3157225 100644
--- a/include/configs/helios4.h
+++ b/include/configs/helios4.h
@@ -6,6 +6,8 @@
 #ifndef _CONFIG_HELIOS4_H
 #define _CONFIG_HELIOS4_H
 
+#include <linux/sizes.h>
+
 /*
  * High Level Configuration Options (easy to change)
  */
@@ -23,6 +25,9 @@
 
 /* SPI NOR flash default params, used by sf commands */
 #define CONFIG_SF_DEFAULT_BUS		1
+#define CONFIG_SF_DEFAULT_CS		0
+#define CONFIG_SF_DEFAULT_SPEED		104000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
 
 /*
  * SDIO/MMC Card Configuration
@@ -43,28 +48,33 @@
 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 					CONFIG_SYS_SCSI_MAX_LUN)
 
+#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI
+/*
+ * SPI Flash configuration for the environment access
+ */
+#define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_SECT_SIZE		SZ_64K
+#define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_OFFSET		SZ_1M
+#endif
+
+#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC
 /* Environment in MMC */
 #define CONFIG_SYS_MMC_ENV_DEV		0
 #define CONFIG_ENV_SECT_SIZE		0x200
-#define CONFIG_ENV_SIZE			0x10000
-/*
- * For SD - reserve 1 LBA for MBR + 1M for u-boot image. The MMC/eMMC
- * boot image starts @ LBA-0.
- * As result in MMC/eMMC case it will be a 1 sector gap between u-boot
- * image and environment
- */
-#define CONFIG_ENV_OFFSET		0xf0000
+#define CONFIG_ENV_SIZE			0x2000
+/* stay within first 1M */
+#define CONFIG_ENV_OFFSET		(SZ_1M - CONFIG_ENV_SIZE)
 #define CONFIG_ENV_ADDR			CONFIG_ENV_OFFSET
+#endif
 
 #define CONFIG_PHY_MARVELL		/* there is a marvell phy */
 #define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
 
-/* PCIe support */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_PCI_MVEBU
-#define CONFIG_PCI_SCAN_SHOW
-#endif
-
 /* Keep device tree and initrd in lower memory so the kernel can access them */
 #define RELOCATION_LIMITS_ENV_SETTINGS	\
 	"fdt_high=0x10000000\0"		\
@@ -80,7 +90,13 @@
  */
 #define SPL_BOOT_SPI_NOR_FLASH		1
 #define SPL_BOOT_SDIO_MMC_CARD		2
+
+#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI
+#define CONFIG_SPL_BOOT_DEVICE		SPL_BOOT_SPI_NOR_FLASH
+#endif
+#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC
 #define CONFIG_SPL_BOOT_DEVICE		SPL_BOOT_SDIO_MMC_CARD
+#endif
 
 /* Defines for SPL */
 #define CONFIG_SPL_SIZE			(140 << 10)
@@ -99,12 +115,16 @@
 
 #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
 /* SPL related SPI defines */
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
 #define CONFIG_SYS_U_BOOT_OFFS		CONFIG_SYS_SPI_U_BOOT_OFFS
 #endif
 
 #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
 /* SPL related MMC defines */
+#define CONFIG_SPL_MMC_SUPPORT
 #define CONFIG_SYS_MMC_U_BOOT_OFFS		(160 << 10)
 #define CONFIG_SYS_U_BOOT_OFFS			CONFIG_SYS_MMC_U_BOOT_OFFS
 #ifdef CONFIG_SPL_BUILD
diff --git a/include/crc.h b/include/crc.h
deleted file mode 100644
index 2a00af5..0000000
--- a/include/crc.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: eCos-2.0 */
-/*
- *==========================================================================
- *
- *      crc.h
- *
- *      Interface for the CRC algorithms.
- *
- *==========================================================================
- *==========================================================================
- *#####DESCRIPTIONBEGIN####
- *
- * Author(s):    Andrew Lunn
- * Contributors: Andrew Lunn
- * Date:         2002-08-06
- * Purpose:
- * Description:
- *
- * This code is part of eCos (tm).
- *
- *####DESCRIPTIONEND####
- *
- *==========================================================================
- */
-
-#ifndef _SERVICES_CRC_CRC_H_
-#define _SERVICES_CRC_CRC_H_
-
-#include <linux/types.h>
-
-#ifndef __externC
-# ifdef __cplusplus
-#  define __externC extern "C"
-# else
-#  define __externC extern
-# endif
-#endif
-
-/* 16 bit CRC with polynomial x^16+x^12+x^5+1 (CRC-CCITT) */
-
-uint16_t crc16_ccitt(uint16_t crc_start, unsigned char *s, int len);
-
-#endif /* _SERVICES_CRC_CRC_H_ */
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 62d9e2f..5d4e207 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -42,6 +42,7 @@
 	UCLASS_FIRMWARE,	/* Firmware */
 	UCLASS_FS_FIRMWARE_LOADER,		/* Generic loader */
 	UCLASS_GPIO,		/* Bank of general-purpose I/O pins */
+	UCLASS_HWSPINLOCK,	/* Hardware semaphores */
 	UCLASS_I2C,		/* I2C bus */
 	UCLASS_I2C_EEPROM,	/* I2C EEPROM device */
 	UCLASS_I2C_GENERIC,	/* Generic I2C device */
@@ -93,6 +94,7 @@
 	UCLASS_USB,		/* USB bus */
 	UCLASS_USB_DEV_GENERIC,	/* USB generic device */
 	UCLASS_USB_HUB,		/* USB hub */
+	UCLASS_USB_GADGET_GENERIC,	/* USB generic device */
 	UCLASS_VIDEO,		/* Video or LCD device */
 	UCLASS_VIDEO_BRIDGE,	/* Video bridge, e.g. DisplayPort to LVDS */
 	UCLASS_VIDEO_CONSOLE,	/* Text console driver for video device */
diff --git a/include/dma-uclass.h b/include/dma-uclass.h
new file mode 100644
index 0000000..31b43fb
--- /dev/null
+++ b/include/dma-uclass.h
@@ -0,0 +1,128 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
+ * Copyright (C) 2015 - 2018 Texas Instruments Incorporated <www.ti.com>
+ * Written by Mugunthan V N <mugunthanvnm@ti.com>
+ *
+ */
+
+#ifndef _DMA_UCLASS_H
+#define _DMA_UCLASS_H
+
+/* See dma.h for background documentation. */
+
+#include <dma.h>
+
+struct ofnode_phandle_args;
+
+/*
+ * struct dma_ops - Driver model DMA operations
+ *
+ * The uclass interface is implemented by all DMA devices which use
+ * driver model.
+ */
+struct dma_ops {
+#ifdef CONFIG_DMA_CHANNELS
+	/**
+	 * of_xlate - Translate a client's device-tree (OF) DMA specifier.
+	 *
+	 * The DMA core calls this function as the first step in implementing
+	 * a client's dma_get_by_*() call.
+	 *
+	 * If this function pointer is set to NULL, the DMA core will use a
+	 * default implementation, which assumes #dma-cells = <1>, and that
+	 * the DT cell contains a simple integer DMA Channel.
+	 *
+	 * At present, the DMA API solely supports device-tree. If this
+	 * changes, other xxx_xlate() functions may be added to support those
+	 * other mechanisms.
+	 *
+	 * @dma: The dma struct to hold the translation result.
+	 * @args:	The dma specifier values from device tree.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*of_xlate)(struct dma *dma,
+			struct ofnode_phandle_args *args);
+	/**
+	 * request - Request a translated DMA.
+	 *
+	 * The DMA core calls this function as the second step in
+	 * implementing a client's dma_get_by_*() call, following a successful
+	 * xxx_xlate() call, or as the only step in implementing a client's
+	 * dma_request() call.
+	 *
+	 * @dma: The DMA struct to request; this has been filled in by
+	 *   a previoux xxx_xlate() function call, or by the caller of
+	 *   dma_request().
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*request)(struct dma *dma);
+	/**
+	 * free - Free a previously requested dma.
+	 *
+	 * This is the implementation of the client dma_free() API.
+	 *
+	 * @dma: The DMA to free.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*free)(struct dma *dma);
+	/**
+	 * enable() - Enable a DMA Channel.
+	 *
+	 * @dma: The DMA Channel to manipulate.
+	 * @return zero on success, or -ve error code.
+	 */
+	int (*enable)(struct dma *dma);
+	/**
+	 * disable() - Disable a DMA Channel.
+	 *
+	 * @dma: The DMA Channel to manipulate.
+	 * @return zero on success, or -ve error code.
+	 */
+	int (*disable)(struct dma *dma);
+	/**
+	 * prepare_rcv_buf() - Prepare/Add receive DMA buffer.
+	 *
+	 * @dma: The DMA Channel to manipulate.
+	 * @dst: The receive buffer pointer.
+	 * @size: The receive buffer size
+	 * @return zero on success, or -ve error code.
+	 */
+	int (*prepare_rcv_buf)(struct dma *dma, void *dst, size_t size);
+	/**
+	 * receive() - Receive a DMA transfer.
+	 *
+	 * @dma: The DMA Channel to manipulate.
+	 * @dst: The destination pointer.
+	 * @metadata: DMA driver's specific data
+	 * @return zero on success, or -ve error code.
+	 */
+	int (*receive)(struct dma *dma, void **dst, void *metadata);
+	/**
+	 * send() - Send a DMA transfer.
+	 *
+	 * @dma: The DMA Channel to manipulate.
+	 * @src: The source pointer.
+	 * @len: Length of the data to be sent (number of bytes).
+	 * @metadata: DMA driver's specific data
+	 * @return zero on success, or -ve error code.
+	 */
+	int (*send)(struct dma *dma, void *src, size_t len, void *metadata);
+#endif /* CONFIG_DMA_CHANNELS */
+	/**
+	 * transfer() - Issue a DMA transfer. The implementation must
+	 *   wait until the transfer is done.
+	 *
+	 * @dev: The DMA device
+	 * @direction: direction of data transfer (should be one from
+	 *   enum dma_direction)
+	 * @dst: The destination pointer.
+	 * @src: The source pointer.
+	 * @len: Length of the data to be copied (number of bytes).
+	 * @return zero on success, or -ve error code.
+	 */
+	int (*transfer)(struct udevice *dev, int direction, void *dst,
+			void *src, size_t len);
+};
+
+#endif /* _DMA_UCLASS_H */
diff --git a/include/dma.h b/include/dma.h
index 50e9652..d1c3d0d 100644
--- a/include/dma.h
+++ b/include/dma.h
@@ -1,12 +1,17 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * (C) Copyright 2015
- *     Texas Instruments Incorporated, <www.ti.com>
+ * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
+ * Copyright (C) 2015 - 2018 Texas Instruments Incorporated <www.ti.com>
+ * Written by Mugunthan V N <mugunthanvnm@ti.com>
+ *
  */
 
 #ifndef _DMA_H_
 #define _DMA_H_
 
+#include <linux/errno.h>
+#include <linux/types.h>
+
 /*
  * enum dma_direction - dma transfer direction indicator
  * @DMA_MEM_TO_MEM: Memcpy mode
@@ -27,28 +32,6 @@
 #define DMA_SUPPORTS_DEV_TO_DEV	BIT(3)
 
 /*
- * struct dma_ops - Driver model DMA operations
- *
- * The uclass interface is implemented by all DMA devices which use
- * driver model.
- */
-struct dma_ops {
-	/*
-	 * Get the current timer count
-	 *
-	 * @dev: The DMA device
-	 * @direction: direction of data transfer should be one from
-		       enum dma_direction
-	 * @dst: Destination pointer
-	 * @src: Source pointer
-	 * @len: Length of the data to be copied.
-	 * @return: 0 if OK, -ve on error
-	 */
-	int (*transfer)(struct udevice *dev, int direction, void *dst,
-			void *src, size_t len);
-};
-
-/*
  * struct dma_dev_priv - information about a device used by the uclass
  *
  * @supported: mode of transfers that DMA can support, should be
@@ -58,6 +41,257 @@
 	u32 supported;
 };
 
+#ifdef CONFIG_DMA_CHANNELS
+/**
+ * A DMA is a feature of computer systems that allows certain hardware
+ * subsystems to access main system memory, independent of the CPU.
+ * DMA channels are typically generated externally to the HW module
+ * consuming them, by an entity this API calls a DMA provider. This API
+ * provides a standard means for drivers to enable and disable DMAs, and to
+ * copy, send and receive data using DMA.
+ *
+ * A driver that implements UCLASS_DMA is a DMA provider. A provider will
+ * often implement multiple separate DMAs, since the hardware it manages
+ * often has this capability. dma_uclass.h describes the interface which
+ * DMA providers must implement.
+ *
+ * DMA consumers/clients are the HW modules driven by the DMA channels. This
+ * header file describes the API used by drivers for those HW modules.
+ *
+ * DMA consumer DMA_MEM_TO_DEV (transmit) usage example (based on networking).
+ * Note. dma_send() is sync operation always -  it'll start transfer and will
+ * poll for it to complete:
+ *	- get/request dma channel
+ *	struct dma dma_tx;
+ *	ret = dma_get_by_name(common->dev, "tx0", &dma_tx);
+ *	if (ret) ...
+ *
+ *	- enable dma channel
+ *	ret = dma_enable(&dma_tx);
+ *	if (ret) ...
+ *
+ *	- dma transmit DMA_MEM_TO_DEV.
+ *	struct ti_drv_packet_data packet_data;
+ *
+ *	packet_data.opt1 = val1;
+ *	packet_data.opt2 = val2;
+ *	ret = dma_send(&dma_tx, packet, length, &packet_data);
+ *	if (ret) ..
+ *
+ * DMA consumer DMA_DEV_TO_MEM (receive) usage example (based on networking).
+ * Note. dma_receive() is sync operation always - it'll start transfer
+ * (if required) and will poll for it to complete (or for any previously
+ * configured dev2mem transfer to complete):
+ *	- get/request dma channel
+ *	struct dma dma_rx;
+ *	ret = dma_get_by_name(common->dev, "rx0", &dma_rx);
+ *	if (ret) ...
+ *
+ *	- enable dma channel
+ *	ret = dma_enable(&dma_rx);
+ *	if (ret) ...
+ *
+ *	- dma receive DMA_DEV_TO_MEM.
+ *	struct ti_drv_packet_data packet_data;
+ *
+ *	len = dma_receive(&dma_rx, (void **)packet, &packet_data);
+ *	if (ret < 0) ...
+ *
+ * DMA consumer DMA_DEV_TO_MEM (receive) zero-copy usage example (based on
+ * networking). Networking subsystem allows to configure and use few receive
+ * buffers (dev2mem), as Networking RX DMA channels usually implemented
+ * as streaming interface
+ *	- get/request dma channel
+ *	struct dma dma_rx;
+ *	ret = dma_get_by_name(common->dev, "rx0", &dma_rx);
+ *	if (ret) ...
+ *
+ *	for (i = 0; i < RX_DESC_NUM; i++) {
+ *		ret = dma_prepare_rcv_buf(&dma_rx,
+ *					  net_rx_packets[i],
+ *					  RX_BUF_SIZE);
+ *		if (ret) ...
+ *	}
+ *
+ *	- enable dma channel
+ *	ret = dma_enable(&dma_rx);
+ *	if (ret) ...
+ *
+ *	- dma receive DMA_DEV_TO_MEM.
+ *	struct ti_drv_packet_data packet_data;
+ *
+ *	len = dma_receive(&dma_rx, (void **)packet, &packet_data);
+ *	if (ret < 0) ..
+ *
+ *	-- process packet --
+ *
+ *	- return buffer back to DAM channel
+ *	ret = dma_prepare_rcv_buf(&dma_rx,
+ *				  net_rx_packets[rx_next],
+ *				  RX_BUF_SIZE);
+ */
+
+struct udevice;
+
+/**
+ * struct dma - A handle to (allowing control of) a single DMA.
+ *
+ * Clients provide storage for DMA handles. The content of the structure is
+ * managed solely by the DMA API and DMA drivers. A DMA struct is
+ * initialized by "get"ing the DMA struct. The DMA struct is passed to all
+ * other DMA APIs to identify which DMA channel to operate upon.
+ *
+ * @dev: The device which implements the DMA channel.
+ * @id: The DMA channel ID within the provider.
+ *
+ * Currently, the DMA API assumes that a single integer ID is enough to
+ * identify and configure any DMA channel for any DMA provider. If this
+ * assumption becomes invalid in the future, the struct could be expanded to
+ * either (a) add more fields to allow DMA providers to store additional
+ * information, or (b) replace the id field with an opaque pointer, which the
+ * provider would dynamically allocated during its .of_xlate op, and process
+ * during is .request op. This may require the addition of an extra op to clean
+ * up the allocation.
+ */
+struct dma {
+	struct udevice *dev;
+	/*
+	 * Written by of_xlate. We assume a single id is enough for now. In the
+	 * future, we might add more fields here.
+	 */
+	unsigned long id;
+};
+
+# if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DMA)
+/**
+ * dma_get_by_index - Get/request a DMA by integer index.
+ *
+ * This looks up and requests a DMA. The index is relative to the client
+ * device; each device is assumed to have n DMAs associated with it somehow,
+ * and this function finds and requests one of them. The mapping of client
+ * device DMA indices to provider DMAs may be via device-tree properties,
+ * board-provided mapping tables, or some other mechanism.
+ *
+ * @dev:	The client device.
+ * @index:	The index of the DMA to request, within the client's list of
+ *		DMA channels.
+ * @dma:	A pointer to a DMA struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int dma_get_by_index(struct udevice *dev, int index, struct dma *dma);
+
+/**
+ * dma_get_by_name - Get/request a DMA by name.
+ *
+ * This looks up and requests a DMA. The name is relative to the client
+ * device; each device is assumed to have n DMAs associated with it somehow,
+ * and this function finds and requests one of them. The mapping of client
+ * device DMA names to provider DMAs may be via device-tree properties,
+ * board-provided mapping tables, or some other mechanism.
+ *
+ * @dev:	The client device.
+ * @name:	The name of the DMA to request, within the client's list of
+ *		DMA channels.
+ * @dma:	A pointer to a DMA struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int dma_get_by_name(struct udevice *dev, const char *name, struct dma *dma);
+# else
+static inline int dma_get_by_index(struct udevice *dev, int index,
+				   struct dma *dma)
+{
+	return -ENOSYS;
+}
+
+static inline int dma_get_by_name(struct udevice *dev, const char *name,
+				  struct dma *dma)
+{
+	return -ENOSYS;
+}
+# endif
+
+/**
+ * dma_request - Request a DMA by provider-specific ID.
+ *
+ * This requests a DMA using a provider-specific ID. Generally, this function
+ * should not be used, since dma_get_by_index/name() provide an interface that
+ * better separates clients from intimate knowledge of DMA providers.
+ * However, this function may be useful in core SoC-specific code.
+ *
+ * @dev: The DMA provider device.
+ * @dma: A pointer to a DMA struct to initialize. The caller must
+ *	 have already initialized any field in this struct which the
+ *	 DMA provider uses to identify the DMA channel.
+ * @return 0 if OK, or a negative error code.
+ */
+int dma_request(struct udevice *dev, struct dma *dma);
+
+/**
+ * dma_free - Free a previously requested DMA.
+ *
+ * @dma: A DMA struct that was previously successfully requested by
+ *	 dma_request/get_by_*().
+ * @return 0 if OK, or a negative error code.
+ */
+int dma_free(struct dma *dma);
+
+/**
+ * dma_enable() - Enable (turn on) a DMA channel.
+ *
+ * @dma: A DMA struct that was previously successfully requested by
+ *	 dma_request/get_by_*().
+ * @return zero on success, or -ve error code.
+ */
+int dma_enable(struct dma *dma);
+
+/**
+ * dma_disable() - Disable (turn off) a DMA channel.
+ *
+ * @dma: A DMA struct that was previously successfully requested by
+ *	 dma_request/get_by_*().
+ * @return zero on success, or -ve error code.
+ */
+int dma_disable(struct dma *dma);
+
+/**
+ * dma_prepare_rcv_buf() - Prepare/add receive DMA buffer.
+ *
+ * It allows to implement zero-copy async DMA_DEV_TO_MEM (receive) transactions
+ * if supported by DMA providers.
+ *
+ * @dma: A DMA struct that was previously successfully requested by
+ *	 dma_request/get_by_*().
+ * @dst: The receive buffer pointer.
+ * @size: The receive buffer size
+ * @return zero on success, or -ve error code.
+ */
+int dma_prepare_rcv_buf(struct dma *dma, void *dst, size_t size);
+
+/**
+ * dma_receive() - Receive a DMA transfer.
+ *
+ * @dma: A DMA struct that was previously successfully requested by
+ *	 dma_request/get_by_*().
+ * @dst: The destination pointer.
+ * @metadata: DMA driver's channel specific data
+ * @return length of received data on success, or zero - no data,
+ * or -ve error code.
+ */
+int dma_receive(struct dma *dma, void **dst, void *metadata);
+
+/**
+ * dma_send() - Send a DMA transfer.
+ *
+ * @dma: A DMA struct that was previously successfully requested by
+ *	 dma_request/get_by_*().
+ * @src: The source pointer.
+ * @len: Length of the data to be sent (number of bytes).
+ * @metadata: DMA driver's channel specific data
+ * @return zero on success, or -ve error code.
+ */
+int dma_send(struct dma *dma, void *src, size_t len, void *metadata);
+#endif /* CONFIG_DMA_CHANNELS */
+
 /*
  * dma_get_device - get a DMA device which supports transfer
  * type of transfer_type
diff --git a/include/dt-bindings/clock/am3.h b/include/dt-bindings/clock/am3.h
new file mode 100644
index 0000000..86a8806
--- /dev/null
+++ b/include/dt-bindings/clock/am3.h
@@ -0,0 +1,227 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_AM3_H
+#define __DT_BINDINGS_CLK_AM3_H
+
+#define AM3_CLKCTRL_OFFSET	0x0
+#define AM3_CLKCTRL_INDEX(offset)	((offset) - AM3_CLKCTRL_OFFSET)
+
+/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
+
+/* l4_per clocks */
+#define AM3_L4_PER_CLKCTRL_OFFSET	0x14
+#define AM3_L4_PER_CLKCTRL_INDEX(offset)	((offset) - AM3_L4_PER_CLKCTRL_OFFSET)
+#define AM3_CPGMAC0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x14)
+#define AM3_LCDC_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x18)
+#define AM3_USB_OTG_HS_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x1c)
+#define AM3_TPTC0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x24)
+#define AM3_EMIF_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x28)
+#define AM3_OCMCRAM_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x2c)
+#define AM3_GPMC_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x30)
+#define AM3_MCASP0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x34)
+#define AM3_UART6_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x38)
+#define AM3_MMC1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x3c)
+#define AM3_ELM_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x40)
+#define AM3_I2C3_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x44)
+#define AM3_I2C2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x48)
+#define AM3_SPI0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x4c)
+#define AM3_SPI1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x50)
+#define AM3_L4_LS_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x60)
+#define AM3_MCASP1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x68)
+#define AM3_UART2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x6c)
+#define AM3_UART3_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x70)
+#define AM3_UART4_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x74)
+#define AM3_UART5_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x78)
+#define AM3_TIMER7_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x7c)
+#define AM3_TIMER2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x80)
+#define AM3_TIMER3_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x84)
+#define AM3_TIMER4_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x88)
+#define AM3_RNG_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x90)
+#define AM3_AES_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x94)
+#define AM3_SHAM_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xa0)
+#define AM3_GPIO2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xac)
+#define AM3_GPIO3_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xb0)
+#define AM3_GPIO4_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xb4)
+#define AM3_TPCC_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xbc)
+#define AM3_D_CAN0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xc0)
+#define AM3_D_CAN1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xc4)
+#define AM3_EPWMSS1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xcc)
+#define AM3_EPWMSS0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xd4)
+#define AM3_EPWMSS2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xd8)
+#define AM3_L3_INSTR_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xdc)
+#define AM3_L3_MAIN_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xe0)
+#define AM3_PRUSS_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xe8)
+#define AM3_TIMER5_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xec)
+#define AM3_TIMER6_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xf0)
+#define AM3_MMC2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xf4)
+#define AM3_MMC3_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xf8)
+#define AM3_TPTC1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xfc)
+#define AM3_TPTC2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x100)
+#define AM3_SPINLOCK_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x10c)
+#define AM3_MAILBOX_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x110)
+#define AM3_L4_HS_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x120)
+#define AM3_OCPWP_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x130)
+#define AM3_CLKDIV32K_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x14c)
+
+/* l4_wkup clocks */
+#define AM3_L4_WKUP_CLKCTRL_OFFSET	0x4
+#define AM3_L4_WKUP_CLKCTRL_INDEX(offset)	((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET)
+#define AM3_CONTROL_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0x4)
+#define AM3_GPIO1_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0x8)
+#define AM3_L4_WKUP_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xc)
+#define AM3_DEBUGSS_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0x14)
+#define AM3_WKUP_M3_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xb0)
+#define AM3_UART1_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xb4)
+#define AM3_I2C1_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xb8)
+#define AM3_ADC_TSC_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xbc)
+#define AM3_SMARTREFLEX0_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xc0)
+#define AM3_TIMER1_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xc4)
+#define AM3_SMARTREFLEX1_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xc8)
+#define AM3_WD_TIMER2_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xd4)
+
+/* mpu clocks */
+#define AM3_MPU_CLKCTRL_OFFSET	0x4
+#define AM3_MPU_CLKCTRL_INDEX(offset)	((offset) - AM3_MPU_CLKCTRL_OFFSET)
+#define AM3_MPU_CLKCTRL	AM3_MPU_CLKCTRL_INDEX(0x4)
+
+/* l4_rtc clocks */
+#define AM3_RTC_CLKCTRL	AM3_CLKCTRL_INDEX(0x0)
+
+/* gfx_l3 clocks */
+#define AM3_GFX_L3_CLKCTRL_OFFSET	0x4
+#define AM3_GFX_L3_CLKCTRL_INDEX(offset)	((offset) - AM3_GFX_L3_CLKCTRL_OFFSET)
+#define AM3_GFX_CLKCTRL	AM3_GFX_L3_CLKCTRL_INDEX(0x4)
+
+/* l4_cefuse clocks */
+#define AM3_L4_CEFUSE_CLKCTRL_OFFSET	0x20
+#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset)	((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET)
+#define AM3_CEFUSE_CLKCTRL	AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20)
+
+/* XXX: Compatibility part end */
+
+/* l4ls clocks */
+#define AM3_L4LS_CLKCTRL_OFFSET	0x38
+#define AM3_L4LS_CLKCTRL_INDEX(offset)	((offset) - AM3_L4LS_CLKCTRL_OFFSET)
+#define AM3_L4LS_UART6_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x38)
+#define AM3_L4LS_MMC1_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x3c)
+#define AM3_L4LS_ELM_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x40)
+#define AM3_L4LS_I2C3_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x44)
+#define AM3_L4LS_I2C2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x48)
+#define AM3_L4LS_SPI0_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x4c)
+#define AM3_L4LS_SPI1_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x50)
+#define AM3_L4LS_L4_LS_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x60)
+#define AM3_L4LS_UART2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x6c)
+#define AM3_L4LS_UART3_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x70)
+#define AM3_L4LS_UART4_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x74)
+#define AM3_L4LS_UART5_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x78)
+#define AM3_L4LS_TIMER7_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x7c)
+#define AM3_L4LS_TIMER2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x80)
+#define AM3_L4LS_TIMER3_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x84)
+#define AM3_L4LS_TIMER4_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x88)
+#define AM3_L4LS_RNG_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x90)
+#define AM3_L4LS_GPIO2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xac)
+#define AM3_L4LS_GPIO3_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xb0)
+#define AM3_L4LS_GPIO4_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xb4)
+#define AM3_L4LS_D_CAN0_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xc0)
+#define AM3_L4LS_D_CAN1_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xc4)
+#define AM3_L4LS_EPWMSS1_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xcc)
+#define AM3_L4LS_EPWMSS0_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xd4)
+#define AM3_L4LS_EPWMSS2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xd8)
+#define AM3_L4LS_TIMER5_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xec)
+#define AM3_L4LS_TIMER6_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xf0)
+#define AM3_L4LS_MMC2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xf4)
+#define AM3_L4LS_SPINLOCK_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x10c)
+#define AM3_L4LS_MAILBOX_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x110)
+#define AM3_L4LS_OCPWP_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x130)
+
+/* l3s clocks */
+#define AM3_L3S_CLKCTRL_OFFSET	0x1c
+#define AM3_L3S_CLKCTRL_INDEX(offset)	((offset) - AM3_L3S_CLKCTRL_OFFSET)
+#define AM3_L3S_USB_OTG_HS_CLKCTRL	AM3_L3S_CLKCTRL_INDEX(0x1c)
+#define AM3_L3S_GPMC_CLKCTRL	AM3_L3S_CLKCTRL_INDEX(0x30)
+#define AM3_L3S_MCASP0_CLKCTRL	AM3_L3S_CLKCTRL_INDEX(0x34)
+#define AM3_L3S_MCASP1_CLKCTRL	AM3_L3S_CLKCTRL_INDEX(0x68)
+#define AM3_L3S_MMC3_CLKCTRL	AM3_L3S_CLKCTRL_INDEX(0xf8)
+
+/* l3 clocks */
+#define AM3_L3_CLKCTRL_OFFSET	0x24
+#define AM3_L3_CLKCTRL_INDEX(offset)	((offset) - AM3_L3_CLKCTRL_OFFSET)
+#define AM3_L3_TPTC0_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0x24)
+#define AM3_L3_EMIF_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0x28)
+#define AM3_L3_OCMCRAM_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0x2c)
+#define AM3_L3_AES_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0x94)
+#define AM3_L3_SHAM_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0xa0)
+#define AM3_L3_TPCC_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0xbc)
+#define AM3_L3_L3_INSTR_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0xdc)
+#define AM3_L3_L3_MAIN_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0xe0)
+#define AM3_L3_TPTC1_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0xfc)
+#define AM3_L3_TPTC2_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0x100)
+
+/* l4hs clocks */
+#define AM3_L4HS_CLKCTRL_OFFSET	0x120
+#define AM3_L4HS_CLKCTRL_INDEX(offset)	((offset) - AM3_L4HS_CLKCTRL_OFFSET)
+#define AM3_L4HS_L4_HS_CLKCTRL	AM3_L4HS_CLKCTRL_INDEX(0x120)
+
+/* pruss_ocp clocks */
+#define AM3_PRUSS_OCP_CLKCTRL_OFFSET	0xe8
+#define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset)	((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET)
+#define AM3_PRUSS_OCP_PRUSS_CLKCTRL	AM3_PRUSS_OCP_CLKCTRL_INDEX(0xe8)
+
+/* cpsw_125mhz clocks */
+#define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL	AM3_CLKCTRL_INDEX(0x14)
+
+/* lcdc clocks */
+#define AM3_LCDC_CLKCTRL_OFFSET	0x18
+#define AM3_LCDC_CLKCTRL_INDEX(offset)	((offset) - AM3_LCDC_CLKCTRL_OFFSET)
+#define AM3_LCDC_LCDC_CLKCTRL	AM3_LCDC_CLKCTRL_INDEX(0x18)
+
+/* clk_24mhz clocks */
+#define AM3_CLK_24MHZ_CLKCTRL_OFFSET	0x14c
+#define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset)	((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET)
+#define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL	AM3_CLK_24MHZ_CLKCTRL_INDEX(0x14c)
+
+/* l4_wkup clocks */
+#define AM3_L4_WKUP_CONTROL_CLKCTRL	AM3_CLKCTRL_INDEX(0x4)
+#define AM3_L4_WKUP_GPIO1_CLKCTRL	AM3_CLKCTRL_INDEX(0x8)
+#define AM3_L4_WKUP_L4_WKUP_CLKCTRL	AM3_CLKCTRL_INDEX(0xc)
+#define AM3_L4_WKUP_UART1_CLKCTRL	AM3_CLKCTRL_INDEX(0xb4)
+#define AM3_L4_WKUP_I2C1_CLKCTRL	AM3_CLKCTRL_INDEX(0xb8)
+#define AM3_L4_WKUP_ADC_TSC_CLKCTRL	AM3_CLKCTRL_INDEX(0xbc)
+#define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL	AM3_CLKCTRL_INDEX(0xc0)
+#define AM3_L4_WKUP_TIMER1_CLKCTRL	AM3_CLKCTRL_INDEX(0xc4)
+#define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL	AM3_CLKCTRL_INDEX(0xc8)
+#define AM3_L4_WKUP_WD_TIMER2_CLKCTRL	AM3_CLKCTRL_INDEX(0xd4)
+
+/* l3_aon clocks */
+#define AM3_L3_AON_CLKCTRL_OFFSET	0x14
+#define AM3_L3_AON_CLKCTRL_INDEX(offset)	((offset) - AM3_L3_AON_CLKCTRL_OFFSET)
+#define AM3_L3_AON_DEBUGSS_CLKCTRL	AM3_L3_AON_CLKCTRL_INDEX(0x14)
+
+/* l4_wkup_aon clocks */
+#define AM3_L4_WKUP_AON_CLKCTRL_OFFSET	0xb0
+#define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset)	((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET)
+#define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL	AM3_L4_WKUP_AON_CLKCTRL_INDEX(0xb0)
+
+/* mpu clocks */
+#define AM3_MPU_MPU_CLKCTRL	AM3_CLKCTRL_INDEX(0x4)
+
+/* l4_rtc clocks */
+#define AM3_L4_RTC_RTC_CLKCTRL	AM3_CLKCTRL_INDEX(0x0)
+
+/* gfx_l3 clocks */
+#define AM3_GFX_L3_GFX_CLKCTRL	AM3_CLKCTRL_INDEX(0x4)
+
+/* l4_cefuse clocks */
+#define AM3_L4_CEFUSE_CEFUSE_CLKCTRL	AM3_CLKCTRL_INDEX(0x20)
+
+#endif
diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h
index 228ab3b..9941cc3 100644
--- a/include/dwc3-uboot.h
+++ b/include/dwc3-uboot.h
@@ -38,4 +38,23 @@
 int dwc3_uboot_init(struct dwc3_device *dev);
 void dwc3_uboot_exit(int index);
 void dwc3_uboot_handle_interrupt(int index);
+
+struct phy;
+#if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB)
+int dwc3_setup_phy(struct udevice *dev, struct phy **array, int *num_phys);
+int dwc3_shutdown_phy(struct udevice *dev, struct phy *usb_phys, int num_phys);
+#else
+static inline int dwc3_setup_phy(struct udevice *dev, struct phy **array,
+				 int *num_phys)
+{
+	return -ENOTSUPP;
+}
+
+static inline int dwc3_shutdown_phy(struct udevice *dev, struct phy *usb_phys,
+				    int num_phys)
+{
+	return -ENOTSUPP;
+}
+#endif
+
 #endif /* __DWC3_UBOOT_H_ */
diff --git a/include/hwspinlock.h b/include/hwspinlock.h
new file mode 100644
index 0000000..99389c1
--- /dev/null
+++ b/include/hwspinlock.h
@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ */
+
+#ifndef _HWSPINLOCK_H_
+#define _HWSPINLOCK_H_
+
+/**
+ * Implement a hwspinlock uclass.
+ * Hardware spinlocks are used to perform hardware protection of
+ * critical sections and synchronisation between multiprocessors.
+ */
+
+struct udevice;
+
+/**
+ * struct hwspinlock - A handle to (allowing control of) a single hardware
+ * spinlock.
+ *
+ * @dev: The device which implements the hardware spinlock.
+ * @id: The hardware spinlock ID within the provider.
+ */
+struct hwspinlock {
+	struct udevice *dev;
+	unsigned long id;
+};
+
+#if CONFIG_IS_ENABLED(DM_HWSPINLOCK)
+
+/**
+ * hwspinlock_get_by_index - Get a hardware spinlock by integer index
+ *
+ * This looks up and request a hardware spinlock. The index is relative to the
+ * client device; each device is assumed to have n hardware spinlock associated
+ * with it somehow, and this function finds and requests one of them.
+ *
+ * @dev:	The client device.
+ * @index:	The index of the hardware spinlock to request, within the
+ *		client's list of hardware spinlock.
+ * @hws:	A pointer to a hardware spinlock struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int hwspinlock_get_by_index(struct udevice *dev,
+			    int index, struct hwspinlock *hws);
+
+/**
+ * Lock the hardware spinlock
+ *
+ * @hws:	A hardware spinlock struct that previously requested by
+ *		hwspinlock_get_by_index
+ * @timeout:	Timeout value in msecs
+ * @return: 0 if OK, -ETIMEDOUT if timeout, -ve on other errors
+ */
+int hwspinlock_lock_timeout(struct hwspinlock *hws, unsigned int timeout);
+
+/**
+ * Unlock the hardware spinlock
+ *
+ * @hws:	A hardware spinlock struct that previously requested by
+ *		hwspinlock_get_by_index
+ * @return: 0 if OK, -ve on error
+ */
+int hwspinlock_unlock(struct hwspinlock *hws);
+
+#else
+
+static inline int hwspinlock_get_by_index(struct udevice *dev,
+					  int index,
+					  struct hwspinlock *hws)
+{
+	return -ENOSYS;
+}
+
+static inline int hwspinlock_lock_timeout(struct hwspinlock *hws,
+					  int timeout)
+{
+	return -ENOSYS;
+}
+
+static inline int hwspinlock_unlock(struct hwspinlock *hws)
+{
+	return -ENOSYS;
+}
+
+#endif /* CONFIG_DM_HWSPINLOCK */
+
+struct ofnode_phandle_args;
+
+/**
+ * struct hwspinlock_ops - Driver model hwspinlock operations
+ *
+ * The uclass interface is implemented by all hwspinlock devices which use
+ * driver model.
+ */
+struct hwspinlock_ops {
+	/**
+	 * of_xlate - Translate a client's device-tree (OF) hardware specifier.
+	 *
+	 * The hardware core calls this function as the first step in
+	 * implementing a client's hwspinlock_get_by_*() call.
+	 *
+	 * @hws:	The hardware spinlock struct to hold the translation
+	 *			result.
+	 * @args:	The hardware spinlock specifier values from device tree.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*of_xlate)(struct hwspinlock *hws,
+			struct ofnode_phandle_args *args);
+
+	/**
+	 * Lock the hardware spinlock
+	 *
+	 * @dev:	hwspinlock Device
+	 * @index:	index of the lock to be used
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*lock)(struct udevice *dev, int index);
+
+	/**
+	 * Unlock the hardware spinlock
+	 *
+	 * @dev:	hwspinlock Device
+	 * @index:	index of the lock to be unlocked
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*unlock)(struct udevice *dev, int index);
+
+	/**
+	 * Relax - optional
+	 *       Platform-specific relax method, called by hwspinlock core
+	 *       while spinning on a lock, between two successive call to
+	 *       lock
+	 *
+	 * @dev:	hwspinlock Device
+	 */
+	void (*relax)(struct udevice *dev);
+};
+
+#endif /* _HWSPINLOCK_H_ */
diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h
index b824f13..497798a 100644
--- a/include/linux/usb/gadget.h
+++ b/include/linux/usb/gadget.h
@@ -19,6 +19,7 @@
 #define __LINUX_USB_GADGET_H
 
 #include <errno.h>
+#include <usb.h>
 #include <linux/compat.h>
 #include <linux/list.h>
 
@@ -926,4 +927,21 @@
 
 extern int usb_gadget_handle_interrupts(int index);
 
+#if CONFIG_IS_ENABLED(DM_USB_GADGET)
+int usb_gadget_initialize(int index);
+int usb_gadget_release(int index);
+int dm_usb_gadget_handle_interrupts(struct udevice *dev);
+#else
+#include <usb.h>
+static inline int usb_gadget_initialize(int index)
+{
+	return board_usb_init(index, USB_INIT_DEVICE);
+}
+
+static inline int usb_gadget_release(int index)
+{
+	return board_usb_cleanup(index, USB_INIT_DEVICE);
+}
+#endif
+
 #endif	/* __LINUX_USB_GADGET_H */
diff --git a/include/spl.h b/include/spl.h
index ee92832..ff4e627 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -52,9 +52,9 @@
 /* A string name for SPL or TPL */
 #ifdef CONFIG_SPL_BUILD
 # ifdef CONFIG_TPL_BUILD
-#  define SPL_TPL_NAME	"tpl"
+#  define SPL_TPL_NAME	"TPL"
 # else
-#  define SPL_TPL_NAME	"spl"
+#  define SPL_TPL_NAME	"SPL"
 # endif
 # define SPL_TPL_PROMPT	SPL_TPL_NAME ": "
 #else
diff --git a/include/syscon.h b/include/syscon.h
index 2aa73e5..3df96e3 100644
--- a/include/syscon.h
+++ b/include/syscon.h
@@ -74,6 +74,19 @@
 struct regmap *syscon_get_regmap_by_driver_data(ulong driver_data);
 
 /**
+ * syscon_regmap_lookup_by_phandle() - Look up a controller by a phandle
+ *
+ * This operates by looking up the given name in the device (device
+ * tree property) of the device using the system controller.
+ *
+ * @dev:	Device using the system controller
+ * @name:	Name of property referring to the system controller
+ * @return	A pointer to the regmap if found, ERR_PTR(-ve) on error
+ */
+struct regmap *syscon_regmap_lookup_by_phandle(struct udevice *dev,
+					       const char *name);
+
+/**
  * syscon_get_first_range() - get the first memory range from a syscon regmap
  *
  * @driver_data:	Driver data value to look up
diff --git a/include/u-boot/crc.h b/include/u-boot/crc.h
index e98cb46..788ef29 100644
--- a/include/u-boot/crc.h
+++ b/include/u-boot/crc.h
@@ -11,6 +11,20 @@
 /* lib/crc8.c */
 unsigned int crc8(unsigned int crc_start, const unsigned char *vptr, int len);
 
+/* lib/crc16.c - 16 bit CRC with polynomial x^16+x^12+x^5+1 (CRC-CCITT) */
+uint16_t crc16_ccitt(uint16_t crc_start, const unsigned char *s, int len);
+/**
+ * crc16_ccitt_wd_buf - Perform CRC16-CCIT on an input buffer and return the
+ *                      16-bit result (network byte-order) in an output buffer
+ *
+ * @in:	input buffer
+ * @len: input buffer length
+ * @out: output buffer (at least 2 bytes)
+ * @chunk_sz: ignored
+ */
+void crc16_ccitt_wd_buf(const uint8_t *in, uint len,
+			uint8_t *out, uint chunk_sz);
+
 /* lib/crc32.c */
 uint32_t crc32 (uint32_t, const unsigned char *, uint);
 uint32_t crc32_wd (uint32_t, const unsigned char *, uint, uint);
diff --git a/lib/Makefile b/lib/Makefile
index 8321355..a6dd928 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -76,6 +76,7 @@
 
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o
+obj-$(CONFIG_$(SPL_TPL_)HASH_SUPPORT) += crc16.o
 obj-$(CONFIG_SPL_NET_SUPPORT) += net_utils.o
 endif
 obj-$(CONFIG_ADDR_MAP) += addr_map.o
diff --git a/lib/crc16.c b/lib/crc16.c
index 763ae33..f46ba72 100644
--- a/lib/crc16.c
+++ b/lib/crc16.c
@@ -22,7 +22,12 @@
  *==========================================================================
  */
 
-#include "crc.h"
+#ifdef USE_HOSTCC
+#include <arpa/inet.h>
+#else
+#include <common.h>
+#endif
+#include <u-boot/crc.h>
 
 /* Table of CRC constants - implements x^16+x^12+x^5+1 */
 static const uint16_t crc16_tab[] = {
@@ -60,14 +65,20 @@
 	0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0,
 };
 
-uint16_t crc16_ccitt(uint16_t crc_start, unsigned char *buf, int len)
+uint16_t crc16_ccitt(uint16_t cksum, const unsigned char *buf, int len)
 {
-	int i;
-	uint16_t cksum;
-
-	cksum = crc_start;
-	for (i = 0;  i < len;  i++)
+	for (int i = 0;  i < len;  i++)
 		cksum = crc16_tab[((cksum>>8) ^ *buf++) & 0xff] ^ (cksum << 8);
 
 	return cksum;
 }
+
+void crc16_ccitt_wd_buf(const uint8_t *in, uint len,
+			uint8_t *out, uint chunk_sz)
+{
+	uint16_t crc;
+
+	crc = crc16_ccitt(0, in, len);
+	crc = htons(crc);
+	memcpy(out, &crc, sizeof(crc));
+}
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 213e0fd..2c9081e 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -19,6 +19,7 @@
 obj-$(CONFIG_DM_ETH) += eth.o
 obj-$(CONFIG_FIRMWARE) += firmware.o
 obj-$(CONFIG_DM_GPIO) += gpio.o
+obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock.o
 obj-$(CONFIG_DM_I2C) += i2c.o
 obj-$(CONFIG_LED) += led.o
 obj-$(CONFIG_DM_MAILBOX) += mailbox.o
@@ -54,4 +55,5 @@
 obj-$(CONFIG_CPU) += cpu.o
 obj-$(CONFIG_TEE) += tee.o
 obj-$(CONFIG_VIRTIO_SANDBOX) += virtio.o
+obj-$(CONFIG_DMA) += dma.o
 endif
diff --git a/test/dm/dma.c b/test/dm/dma.c
new file mode 100644
index 0000000..b56d177
--- /dev/null
+++ b/test/dm/dma.c
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Direct Memory Access U-Class tests
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated <www.ti.com>
+ * Grygorii Strashko <grygorii.strashko@ti.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/test.h>
+#include <dma.h>
+#include <test/ut.h>
+
+static int dm_test_dma_m2m(struct unit_test_state *uts)
+{
+	struct udevice *dev;
+	struct dma dma_m2m;
+	u8 src_buf[512];
+	u8 dst_buf[512];
+	size_t len = 512;
+	int i;
+
+	ut_assertok(uclass_get_device_by_name(UCLASS_DMA, "dma", &dev));
+	ut_assertok(dma_get_by_name(dev, "m2m", &dma_m2m));
+
+	memset(dst_buf, 0, len);
+	for (i = 0; i < len; i++)
+		src_buf[i] = i;
+
+	ut_assertok(dma_memcpy(dst_buf, src_buf, len));
+
+	ut_assertok(memcmp(src_buf, dst_buf, len));
+	return 0;
+}
+DM_TEST(dm_test_dma_m2m, DM_TESTF_SCAN_FDT);
+
+static int dm_test_dma(struct unit_test_state *uts)
+{
+	struct udevice *dev;
+	struct dma dma_tx, dma_rx;
+	u8 src_buf[512];
+	u8 dst_buf[512];
+	void *dst_ptr;
+	size_t len = 512;
+	u32 meta1, meta2;
+	int i;
+
+	ut_assertok(uclass_get_device_by_name(UCLASS_DMA, "dma", &dev));
+
+	ut_assertok(dma_get_by_name(dev, "tx0", &dma_tx));
+	ut_assertok(dma_get_by_name(dev, "rx0", &dma_rx));
+
+	ut_assertok(dma_enable(&dma_tx));
+	ut_assertok(dma_enable(&dma_rx));
+
+	memset(dst_buf, 0, len);
+	for (i = 0; i < len; i++)
+		src_buf[i] = i;
+	meta1 = 0xADADDEAD;
+	meta2 = 0;
+	dst_ptr = &dst_buf;
+
+	ut_assertok(dma_send(&dma_tx, src_buf, len, &meta1));
+
+	ut_asserteq(len, dma_receive(&dma_rx, &dst_ptr, &meta2));
+	ut_asserteq(0xADADDEAD, meta2);
+
+	ut_assertok(dma_disable(&dma_tx));
+	ut_assertok(dma_disable(&dma_rx));
+
+	ut_assertok(dma_free(&dma_tx));
+	ut_assertok(dma_free(&dma_rx));
+	ut_assertok(memcmp(src_buf, dst_buf, len));
+
+	return 0;
+}
+DM_TEST(dm_test_dma, DM_TESTF_SCAN_FDT);
+
+static int dm_test_dma_rx(struct unit_test_state *uts)
+{
+	struct udevice *dev;
+	struct dma dma_tx, dma_rx;
+	u8 src_buf[512];
+	u8 dst_buf[512];
+	void *dst_ptr;
+	size_t len = 512;
+	u32 meta1, meta2;
+	int i;
+
+	ut_assertok(uclass_get_device_by_name(UCLASS_DMA, "dma", &dev));
+
+	ut_assertok(dma_get_by_name(dev, "tx0", &dma_tx));
+	ut_assertok(dma_get_by_name(dev, "rx0", &dma_rx));
+
+	ut_assertok(dma_enable(&dma_tx));
+	ut_assertok(dma_enable(&dma_rx));
+
+	memset(dst_buf, 0, len);
+	for (i = 0; i < len; i++)
+		src_buf[i] = i;
+	meta1 = 0xADADDEAD;
+	meta2 = 0;
+	dst_ptr = NULL;
+
+	ut_assertok(dma_prepare_rcv_buf(&dma_tx, dst_buf, len));
+
+	ut_assertok(dma_send(&dma_tx, src_buf, len, &meta1));
+
+	ut_asserteq(len, dma_receive(&dma_rx, &dst_ptr, &meta2));
+	ut_asserteq(0xADADDEAD, meta2);
+	ut_asserteq_ptr(dst_buf, dst_ptr);
+
+	ut_assertok(dma_disable(&dma_tx));
+	ut_assertok(dma_disable(&dma_rx));
+
+	ut_assertok(dma_free(&dma_tx));
+	ut_assertok(dma_free(&dma_rx));
+	ut_assertok(memcmp(src_buf, dst_buf, len));
+
+	return 0;
+}
+DM_TEST(dm_test_dma_rx, DM_TESTF_SCAN_FDT);
diff --git a/test/dm/hwspinlock.c b/test/dm/hwspinlock.c
new file mode 100644
index 0000000..09ec38b
--- /dev/null
+++ b/test/dm/hwspinlock.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <hwspinlock.h>
+#include <asm/state.h>
+#include <asm/test.h>
+#include <dm/test.h>
+#include <test/ut.h>
+
+/* Test that hwspinlock driver functions are called */
+static int dm_test_hwspinlock_base(struct unit_test_state *uts)
+{
+	struct sandbox_state *state = state_get_current();
+	struct hwspinlock hws;
+
+	ut_assertok(uclass_get_device(UCLASS_HWSPINLOCK, 0, &hws.dev));
+	ut_assertnonnull(hws.dev);
+	ut_asserteq(false, state->hwspinlock);
+
+	hws.id = 0;
+	ut_assertok(hwspinlock_lock_timeout(&hws, 1));
+	ut_asserteq(true, state->hwspinlock);
+
+	ut_assertok(hwspinlock_unlock(&hws));
+	ut_asserteq(false, state->hwspinlock);
+
+	ut_assertok(hwspinlock_lock_timeout(&hws, 1));
+	ut_assertok(!hwspinlock_lock_timeout(&hws, 1));
+
+	ut_assertok(hwspinlock_unlock(&hws));
+	ut_assertok(!hwspinlock_unlock(&hws));
+
+	return 0;
+}
+
+DM_TEST(dm_test_hwspinlock_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
diff --git a/test/dm/syscon.c b/test/dm/syscon.c
index 77c7928..a294dda 100644
--- a/test/dm/syscon.c
+++ b/test/dm/syscon.c
@@ -6,6 +6,7 @@
 #include <common.h>
 #include <dm.h>
 #include <syscon.h>
+#include <regmap.h>
 #include <asm/test.h>
 #include <dm/test.h>
 #include <test/ut.h>
@@ -43,3 +44,31 @@
 	return 0;
 }
 DM_TEST(dm_test_syscon_by_driver_data, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test system controller by phandle */
+static int dm_test_syscon_by_phandle(struct unit_test_state *uts)
+{
+	struct udevice *dev;
+	struct regmap *map;
+
+	ut_assertok(uclass_get_device_by_name(UCLASS_TEST_PROBE, "test4",
+					      &dev));
+
+	ut_assertok_ptr(syscon_regmap_lookup_by_phandle(dev, "first-syscon"));
+	map = syscon_regmap_lookup_by_phandle(dev, "first-syscon");
+	ut_assert(map);
+	ut_assert(!IS_ERR(map));
+	ut_asserteq(1, map->range_count);
+
+	ut_assertok_ptr(syscon_regmap_lookup_by_phandle(dev,
+							"second-sys-ctrl"));
+	map = syscon_regmap_lookup_by_phandle(dev, "second-sys-ctrl");
+	ut_assert(map);
+	ut_assert(!IS_ERR(map));
+	ut_asserteq(4, map->range_count);
+
+	ut_assert(IS_ERR(syscon_regmap_lookup_by_phandle(dev, "not-present")));
+
+	return 0;
+}
+DM_TEST(dm_test_syscon_by_phandle, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
diff --git a/test/py/u_boot_console_base.py b/test/py/u_boot_console_base.py
index e044eb3..326b2ac 100644
--- a/test/py/u_boot_console_base.py
+++ b/test/py/u_boot_console_base.py
@@ -16,7 +16,7 @@
 import u_boot_spawn
 
 # Regexes for text we expect U-Boot to send to the console.
-pattern_u_boot_spl_signon = re.compile('(U-Boot spl \\d{4}\\.\\d{2}[^\r\n]*\\))')
+pattern_u_boot_spl_signon = re.compile('(U-Boot SPL \\d{4}\\.\\d{2}[^\r\n]*\\))')
 pattern_u_boot_main_signon = re.compile('(U-Boot \\d{4}\\.\\d{2}[^\r\n]*\\))')
 pattern_stop_autoboot_prompt = re.compile('Hit any key to stop autoboot: ')
 pattern_unknown_command = re.compile('Unknown command \'.*\' - try \'help\'')
diff --git a/tools/Makefile b/tools/Makefile
index c93d17a..c26b631 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -106,6 +106,7 @@
 			stm32image.o \
 			$(ROCKCHIP_OBS) \
 			socfpgaimage.o \
+			lib/crc16.o \
 			lib/sha1.o \
 			lib/sha256.o \
 			common/hash.o \