tree 0677a1998c4697e1662fc7ec28ffb87fcb39482f
parent fd6bcb53b6be9132360f170743abe5c4affde219
author Marek Vasut <marex@denx.de> 1533586060 +0200
committer Marek Vasut <marex@denx.de> 1534192542 +0200

ARM: dts: socfpga: Add u-boot,dm-pre-reloc to necessary clock nodes

Add the pre-reloc DT markers to clock nodes needed in SPL and early
U-Boot stages. This is required to let the Arria10 clock driver start
early and provide clock information for UART and SDMMC.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>