Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscv
+ riscv: Add Zbb support
+ riscv: Add preliminary RISC-V falcon mode support
+ riscv: Remove dram_init_banksize()
+ andes: rearrange PLICSW scheme
+ visionfive2: enable bootstage configs
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index e88c267..e430347 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -975,7 +975,7 @@
};
wdt-gpio-toggle {
- gpios = <&gpio_a 7 0>;
+ gpios = <&gpio_a 8 0>;
compatible = "linux,wdt-gpio";
hw_margin_ms = <100>;
hw_algo = "toggle";
diff --git a/drivers/watchdog/npcm_wdt.c b/drivers/watchdog/npcm_wdt.c
index e56aa0e..57b6121 100644
--- a/drivers/watchdog/npcm_wdt.c
+++ b/drivers/watchdog/npcm_wdt.c
@@ -69,15 +69,21 @@
static int npcm_wdt_reset(struct udevice *dev)
{
struct npcm_wdt_priv *priv = dev_get_priv(dev);
+ u32 val;
- writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, priv->regs);
+ val = readl(priv->regs);
+ writel(val | NPCM_WTR, priv->regs);
return 0;
}
static int npcm_wdt_expire_now(struct udevice *dev, ulong flags)
{
- return npcm_wdt_reset(dev);
+ struct npcm_wdt_priv *priv = dev_get_priv(dev);
+
+ writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, priv->regs);
+
+ return 0;
}
static int npcm_wdt_of_to_plat(struct udevice *dev)
diff --git a/test/dm/wdt.c b/test/dm/wdt.c
index 653d7b1..2bbebcd 100644
--- a/test/dm/wdt.c
+++ b/test/dm/wdt.c
@@ -54,7 +54,7 @@
*/
struct udevice *wdt, *gpio;
const u64 timeout = 42;
- const int offset = 7;
+ const int offset = 8;
int val;
ut_assertok(uclass_get_device_by_name(UCLASS_WDT,
@@ -115,7 +115,7 @@
struct udevice *gpio_wdt, *sandbox_wdt;
struct udevice *gpio;
const u64 timeout = 42;
- const int offset = 7;
+ const int offset = 8;
uint reset_count;
int val;